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1 /*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9
10 #if defined(CONFIG_SYS_NAND_BASE)
11 #include <nand.h>
12 #include <asm/errno.h>
13 #include <asm/io.h>
14
15 static int state;
16 static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte);
17 static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
18 static u_char sc_nand_read_byte(struct mtd_info *mtd);
19 static u16 sc_nand_read_word(struct mtd_info *mtd);
20 static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
21 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
22 static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
23 #endif
24 static int sc_nand_device_ready(struct mtd_info *mtdinfo);
25
26 #define FPGA_NAND_CMD_MASK (0x7 << 28)
27 #define FPGA_NAND_CMD_COMMAND (0x0 << 28)
28 #define FPGA_NAND_CMD_ADDR (0x1 << 28)
29 #define FPGA_NAND_CMD_READ (0x2 << 28)
30 #define FPGA_NAND_CMD_WRITE (0x3 << 28)
31 #define FPGA_NAND_BUSY (0x1 << 15)
32 #define FPGA_NAND_ENABLE (0x1 << 31)
33 #define FPGA_NAND_DATA_SHIFT 16
34
35 /**
36 * sc_nand_write_byte - write one byte to the chip
37 * @mtd: MTD device structure
38 * @byte: pointer to data byte to write
39 */
40 static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte)
41 {
42 sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
43 }
44
45 /**
46 * sc_nand_write_buf - write buffer to chip
47 * @mtd: MTD device structure
48 * @buf: data buffer
49 * @len: number of bytes to write
50 */
51 static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
52 {
53 int i;
54 struct nand_chip *this = mtd->priv;
55
56 for (i = 0; i < len; i++) {
57 out_be32(this->IO_ADDR_W,
58 state | (buf[i] << FPGA_NAND_DATA_SHIFT));
59 }
60 }
61
62
63 /**
64 * sc_nand_read_byte - read one byte from the chip
65 * @mtd: MTD device structure
66 */
67 static u_char sc_nand_read_byte(struct mtd_info *mtd)
68 {
69 u8 byte;
70 sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
71 return byte;
72 }
73
74 /**
75 * sc_nand_read_word - read one word from the chip
76 * @mtd: MTD device structure
77 */
78 static u16 sc_nand_read_word(struct mtd_info *mtd)
79 {
80 u16 word;
81 sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
82 return word;
83 }
84
85 /**
86 * sc_nand_read_buf - read chip data into buffer
87 * @mtd: MTD device structure
88 * @buf: buffer to store date
89 * @len: number of bytes to read
90 */
91 static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
92 {
93 int i;
94 struct nand_chip *this = mtd->priv;
95 int val;
96
97 val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
98
99 out_be32(this->IO_ADDR_W, val);
100 for (i = 0; i < len; i++) {
101 buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
102 }
103 }
104
105 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
106 /**
107 * sc_nand_verify_buf - Verify chip data against buffer
108 * @mtd: MTD device structure
109 * @buf: buffer containing the data to compare
110 * @len: number of bytes to compare
111 */
112 static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
113 {
114 int i;
115
116 for (i = 0; i < len; i++) {
117 if (buf[i] != sc_nand_read_byte(mtd));
118 return -EFAULT;
119 }
120 return 0;
121 }
122 #endif
123
124 /**
125 * sc_nand_device_ready - Check the NAND device is ready for next command.
126 * @mtd: MTD device structure
127 */
128 static int sc_nand_device_ready(struct mtd_info *mtdinfo)
129 {
130 struct nand_chip *this = mtdinfo->priv;
131
132 if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
133 return 0; /* busy */
134 return 1;
135 }
136
137 /**
138 * sc_nand_hwcontrol - NAND control functions wrapper.
139 * @mtd: MTD device structure
140 * @cmd: Command
141 */
142 static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
143 {
144 if (ctrl & NAND_CTRL_CHANGE) {
145 state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
146
147 switch (ctrl & (NAND_ALE | NAND_CLE)) {
148 case 0:
149 state |= FPGA_NAND_CMD_WRITE;
150 break;
151
152 case NAND_ALE:
153 state |= FPGA_NAND_CMD_ADDR;
154 break;
155
156 case NAND_CLE:
157 state |= FPGA_NAND_CMD_COMMAND;
158 break;
159
160 default:
161 printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
162 }
163
164 if (ctrl & NAND_NCE)
165 state |= FPGA_NAND_ENABLE;
166 }
167
168 if (cmd != NAND_CMD_NONE)
169 sc_nand_write_byte(mtdinfo, cmd);
170 }
171
172 int board_nand_init(struct nand_chip *nand)
173 {
174 nand->cmd_ctrl = sc_nand_hwcontrol;
175 nand->ecc.mode = NAND_ECC_SOFT;
176 nand->dev_ready = sc_nand_device_ready;
177 nand->read_byte = sc_nand_read_byte;
178 nand->read_word = sc_nand_read_word;
179 nand->write_buf = sc_nand_write_buf;
180 nand->read_buf = sc_nand_read_buf;
181 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
182 nand->verify_buf = sc_nand_verify_buf;
183 #endif
184
185 return 0;
186 }
187
188 #endif