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Add Arm Assembly (aarch64) support for RNG
[thirdparty/openssl.git] / crypto / armcap.c
1 /*
2 * Copyright 2011-2021 The OpenSSL Project Authors. All Rights Reserved.
3 *
4 * Licensed under the Apache License 2.0 (the "License"). You may not use
5 * this file except in compliance with the License. You can obtain a copy
6 * in the file LICENSE in the source distribution or at
7 * https://www.openssl.org/source/license.html
8 */
9
10 #include <stdio.h>
11 #include <stdlib.h>
12 #include <string.h>
13 #include <setjmp.h>
14 #include <signal.h>
15 #include <openssl/crypto.h>
16 #ifdef __APPLE__
17 #include <sys/sysctl.h>
18 #endif
19 #include "internal/cryptlib.h"
20 #include <unistd.h>
21
22 #include "arm_arch.h"
23
24 unsigned int OPENSSL_armcap_P = 0;
25 unsigned int OPENSSL_arm_midr = 0;
26 unsigned int OPENSSL_armv8_rsa_neonized = 0;
27
28 #if __ARM_MAX_ARCH__<7
29 void OPENSSL_cpuid_setup(void)
30 {
31 }
32
33 uint32_t OPENSSL_rdtsc(void)
34 {
35 return 0;
36 }
37 #else
38 static sigset_t all_masked;
39
40 static sigjmp_buf ill_jmp;
41 static void ill_handler(int sig)
42 {
43 siglongjmp(ill_jmp, sig);
44 }
45
46 /*
47 * Following subroutines could have been inlined, but it's not all
48 * ARM compilers support inline assembler...
49 */
50 void _armv7_neon_probe(void);
51 void _armv8_aes_probe(void);
52 void _armv8_sha1_probe(void);
53 void _armv8_sha256_probe(void);
54 void _armv8_pmull_probe(void);
55 # ifdef __aarch64__
56 void _armv8_sha512_probe(void);
57 unsigned int _armv8_cpuid_probe(void);
58 void _armv8_rng_probe(void);
59
60 size_t OPENSSL_rndr_asm(unsigned char *buf, size_t len);
61 size_t OPENSSL_rndrrs_asm(unsigned char *buf, size_t len);
62
63 size_t OPENSSL_rndr_bytes(unsigned char *buf, size_t len);
64 size_t OPENSSL_rndrrs_bytes(unsigned char *buf, size_t len);
65
66 static size_t OPENSSL_rndr_wrapper(size_t (*func)(unsigned char *, size_t), unsigned char *buf, size_t len)
67 {
68 size_t buffer_size;
69 int i;
70
71 for (i = 0; i < 8; i++) {
72 buffer_size = func(buf, len);
73 if (buffer_size == len)
74 break;
75 usleep(5000); /* 5000 microseconds (5 milliseconds) */
76 }
77 return buffer_size;
78 }
79
80 size_t OPENSSL_rndr_bytes(unsigned char *buf, size_t len)
81 {
82 return OPENSSL_rndr_wrapper(OPENSSL_rndr_asm, buf, len);
83 }
84
85 size_t OPENSSL_rndrrs_bytes(unsigned char *buf, size_t len)
86 {
87 return OPENSSL_rndr_wrapper(OPENSSL_rndrrs_asm, buf, len);
88 }
89 # endif
90 uint32_t _armv7_tick(void);
91
92 uint32_t OPENSSL_rdtsc(void)
93 {
94 if (OPENSSL_armcap_P & ARMV7_TICK)
95 return _armv7_tick();
96 else
97 return 0;
98 }
99
100 # if defined(__GNUC__) && __GNUC__>=2
101 void OPENSSL_cpuid_setup(void) __attribute__ ((constructor));
102 # endif
103
104 # if defined(__GLIBC__) && defined(__GLIBC_PREREQ)
105 # if __GLIBC_PREREQ(2, 16)
106 # include <sys/auxv.h>
107 # define OSSL_IMPLEMENT_GETAUXVAL
108 # endif
109 # elif defined(__ANDROID_API__)
110 /* see https://developer.android.google.cn/ndk/guides/cpu-features */
111 # if __ANDROID_API__ >= 18
112 # include <sys/auxv.h>
113 # define OSSL_IMPLEMENT_GETAUXVAL
114 # endif
115 # endif
116 # if defined(__FreeBSD__)
117 # include <sys/param.h>
118 # if __FreeBSD_version >= 1200000
119 # include <sys/auxv.h>
120 # define OSSL_IMPLEMENT_GETAUXVAL
121
122 static unsigned long getauxval(unsigned long key)
123 {
124 unsigned long val = 0ul;
125
126 if (elf_aux_info((int)key, &val, sizeof(val)) != 0)
127 return 0ul;
128
129 return val;
130 }
131 # endif
132 # endif
133
134 /*
135 * Android: according to https://developer.android.com/ndk/guides/cpu-features,
136 * getauxval is supported starting with API level 18
137 */
138 # if defined(__ANDROID__) && defined(__ANDROID_API__) && __ANDROID_API__ >= 18
139 # include <sys/auxv.h>
140 # define OSSL_IMPLEMENT_GETAUXVAL
141 # endif
142
143 /*
144 * ARM puts the feature bits for Crypto Extensions in AT_HWCAP2, whereas
145 * AArch64 used AT_HWCAP.
146 */
147 # ifndef AT_HWCAP
148 # define AT_HWCAP 16
149 # endif
150 # ifndef AT_HWCAP2
151 # define AT_HWCAP2 26
152 # endif
153 # if defined(__arm__) || defined (__arm)
154 # define HWCAP AT_HWCAP
155 # define HWCAP_NEON (1 << 12)
156
157 # define HWCAP_CE AT_HWCAP2
158 # define HWCAP_CE_AES (1 << 0)
159 # define HWCAP_CE_PMULL (1 << 1)
160 # define HWCAP_CE_SHA1 (1 << 2)
161 # define HWCAP_CE_SHA256 (1 << 3)
162 # elif defined(__aarch64__)
163 # define HWCAP AT_HWCAP
164 # define HWCAP_NEON (1 << 1)
165
166 # define HWCAP_CE HWCAP
167 # define HWCAP_CE_AES (1 << 3)
168 # define HWCAP_CE_PMULL (1 << 4)
169 # define HWCAP_CE_SHA1 (1 << 5)
170 # define HWCAP_CE_SHA256 (1 << 6)
171 # define HWCAP_CPUID (1 << 11)
172 # define HWCAP_CE_SHA512 (1 << 21)
173 /* AT_HWCAP2 */
174 # define HWCAP2 26
175 # define HWCAP2_RNG (1 << 16)
176 # endif
177
178 void OPENSSL_cpuid_setup(void)
179 {
180 const char *e;
181 struct sigaction ill_oact, ill_act;
182 sigset_t oset;
183 static int trigger = 0;
184
185 if (trigger)
186 return;
187 trigger = 1;
188
189 OPENSSL_armcap_P = 0;
190
191 if ((e = getenv("OPENSSL_armcap"))) {
192 OPENSSL_armcap_P = (unsigned int)strtoul(e, NULL, 0);
193 return;
194 }
195
196 # if defined(__APPLE__)
197 # if !defined(__aarch64__)
198 /*
199 * Capability probing by catching SIGILL appears to be problematic
200 * on iOS. But since Apple universe is "monocultural", it's actually
201 * possible to simply set pre-defined processor capability mask.
202 */
203 if (1) {
204 OPENSSL_armcap_P = ARMV7_NEON;
205 return;
206 }
207 /*
208 * One could do same even for __aarch64__ iOS builds. It's not done
209 * exclusively for reasons of keeping code unified across platforms.
210 * Unified code works because it never triggers SIGILL on Apple
211 * devices...
212 */
213 # else
214 {
215 unsigned int sha512;
216 size_t len = sizeof(sha512);
217
218 if (sysctlbyname("hw.optional.armv8_2_sha512", &sha512, &len, NULL, 0) == 0 && sha512 == 1)
219 OPENSSL_armcap_P |= ARMV8_SHA512;
220 }
221 # endif
222 # endif
223
224 # ifdef OSSL_IMPLEMENT_GETAUXVAL
225 if (getauxval(HWCAP) & HWCAP_NEON) {
226 unsigned long hwcap = getauxval(HWCAP_CE);
227
228 OPENSSL_armcap_P |= ARMV7_NEON;
229
230 if (hwcap & HWCAP_CE_AES)
231 OPENSSL_armcap_P |= ARMV8_AES;
232
233 if (hwcap & HWCAP_CE_PMULL)
234 OPENSSL_armcap_P |= ARMV8_PMULL;
235
236 if (hwcap & HWCAP_CE_SHA1)
237 OPENSSL_armcap_P |= ARMV8_SHA1;
238
239 if (hwcap & HWCAP_CE_SHA256)
240 OPENSSL_armcap_P |= ARMV8_SHA256;
241
242 # ifdef __aarch64__
243 if (hwcap & HWCAP_CE_SHA512)
244 OPENSSL_armcap_P |= ARMV8_SHA512;
245
246 if (hwcap & HWCAP_CPUID)
247 OPENSSL_armcap_P |= ARMV8_CPUID;
248 # endif
249 }
250 # ifdef __aarch64__
251 if (getauxval(HWCAP2) & HWCAP2_RNG)
252 OPENSSL_armcap_P |= ARMV8_RNG;
253 # endif
254 # endif
255
256 sigfillset(&all_masked);
257 sigdelset(&all_masked, SIGILL);
258 sigdelset(&all_masked, SIGTRAP);
259 sigdelset(&all_masked, SIGFPE);
260 sigdelset(&all_masked, SIGBUS);
261 sigdelset(&all_masked, SIGSEGV);
262
263 memset(&ill_act, 0, sizeof(ill_act));
264 ill_act.sa_handler = ill_handler;
265 ill_act.sa_mask = all_masked;
266
267 sigprocmask(SIG_SETMASK, &ill_act.sa_mask, &oset);
268 sigaction(SIGILL, &ill_act, &ill_oact);
269
270 /* If we used getauxval, we already have all the values */
271 # ifndef OSSL_IMPLEMENT_GETAUXVAL
272 if (sigsetjmp(ill_jmp, 1) == 0) {
273 _armv7_neon_probe();
274 OPENSSL_armcap_P |= ARMV7_NEON;
275 if (sigsetjmp(ill_jmp, 1) == 0) {
276 _armv8_pmull_probe();
277 OPENSSL_armcap_P |= ARMV8_PMULL | ARMV8_AES;
278 } else if (sigsetjmp(ill_jmp, 1) == 0) {
279 _armv8_aes_probe();
280 OPENSSL_armcap_P |= ARMV8_AES;
281 }
282 if (sigsetjmp(ill_jmp, 1) == 0) {
283 _armv8_sha1_probe();
284 OPENSSL_armcap_P |= ARMV8_SHA1;
285 }
286 if (sigsetjmp(ill_jmp, 1) == 0) {
287 _armv8_sha256_probe();
288 OPENSSL_armcap_P |= ARMV8_SHA256;
289 }
290 # if defined(__aarch64__) && !defined(__APPLE__)
291 if (sigsetjmp(ill_jmp, 1) == 0) {
292 _armv8_sha512_probe();
293 OPENSSL_armcap_P |= ARMV8_SHA512;
294 }
295 # endif
296 }
297 # ifdef __aarch64__
298 if (sigsetjmp(ill_jmp, 1) == 0) {
299 _armv8_rng_probe();
300 OPENSSL_armcap_P |= ARMV8_RNG;
301 }
302 # endif
303 # endif
304
305 /* Things that getauxval didn't tell us */
306 if (sigsetjmp(ill_jmp, 1) == 0) {
307 _armv7_tick();
308 OPENSSL_armcap_P |= ARMV7_TICK;
309 }
310
311 sigaction(SIGILL, &ill_oact, NULL);
312 sigprocmask(SIG_SETMASK, &oset, NULL);
313
314 # ifdef __aarch64__
315 if (OPENSSL_armcap_P & ARMV8_CPUID)
316 OPENSSL_arm_midr = _armv8_cpuid_probe();
317
318 if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) ||
319 MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N1)) &&
320 (OPENSSL_armcap_P & ARMV7_NEON)) {
321 OPENSSL_armv8_rsa_neonized = 1;
322 }
323 # endif
324 }
325 #endif