crypto/armv4cpuid.S

   1 #include "arm_arch.h"
   2
   3 .text
   4 .code   32
   5
   6 .align  5
   7 .global OPENSSL_atomic_add
   8 .type   OPENSSL_atomic_add,%function
   9 OPENSSL_atomic_add:
  10 #if __ARM_ARCH__>=6
  11 .Ladd:  ldrex   r2,[r0]
  12         add     r3,r2,r1
  13         strex   r2,r3,[r0]
  14         cmp     r2,#0
  15         bne     .Ladd
  16         mov     r0,r3
  17         bx      lr
  18 #else
  19         stmdb   sp!,{r4-r6,lr}
  20         ldr     r2,.Lspinlock
  21         adr     r3,.Lspinlock
  22         mov     r4,r0
  23         mov     r5,r1
  24         add     r6,r3,r2        @ &spinlock
  25         b       .+8
  26 .Lspin: bl      sched_yield
  27         mov     r0,#-1
  28         swp     r0,r0,[r6]
  29         cmp     r0,#0
  30         bne     .Lspin
  31
  32         ldr     r2,[r4]
  33         add     r2,r2,r5
  34         str     r2,[r4]
  35         str     r0,[r6]         @ release spinlock
  36         ldmia   sp!,{r4-r6,lr}
  37         tst     lr,#1
  38         moveq   pc,lr
  39         .word   0xe12fff1e      @ bx    lr
  40 #endif
  41 .size   OPENSSL_atomic_add,.-OPENSSL_atomic_add
  42
  43 .global OPENSSL_cleanse
  44 .type   OPENSSL_cleanse,%function
  45 OPENSSL_cleanse:
  46         eor     ip,ip,ip
  47         cmp     r1,#7
  48         subhs   r1,r1,#4
  49         bhs     .Lot
  50         cmp     r1,#0
  51         beq     .Lcleanse_done
  52 .Little:
  53         strb    ip,[r0],#1
  54         subs    r1,r1,#1
  55         bhi     .Little
  56         b       .Lcleanse_done
  57
  58 .Lot:   tst     r0,#3
  59         beq     .Laligned
  60         strb    ip,[r0],#1
  61         sub     r1,r1,#1
  62         b       .Lot
  63 .Laligned:
  64         str     ip,[r0],#4
  65         subs    r1,r1,#4
  66         bhs     .Laligned
  67         adds    r1,r1,#4
  68         bne     .Little
  69 .Lcleanse_done:
  70 #if __ARM_ARCH__>=5
  71         bx      lr
  72 #else
  73         tst     lr,#1
  74         moveq   pc,lr
  75         .word   0xe12fff1e      @ bx    lr
  76 #endif
  77 .size   OPENSSL_cleanse,.-OPENSSL_cleanse
  78
  79 #if __ARM_MAX_ARCH__>=7
  80 .arch   armv7-a
  81 .fpu    neon
  82
  83 .align  5
  84 .global _armv7_neon_probe
  85 .type   _armv7_neon_probe,%function
  86 _armv7_neon_probe:
  87         vorr    q0,q0,q0
  88         bx      lr
  89 .size   _armv7_neon_probe,.-_armv7_neon_probe
  90
  91 .global _armv7_tick
  92 .type   _armv7_tick,%function
  93 _armv7_tick:
  94         mrrc    p15,1,r0,r1,c14         @ CNTVCT
  95         bx      lr
  96 .size   _armv7_tick,.-_armv7_tick
  97
  98 .global _armv8_aes_probe
  99 .type   _armv8_aes_probe,%function
 100 _armv8_aes_probe:
 101         .byte   0x00,0x03,0xb0,0xf3     @ aese.8        q0,q0
 102         bx      lr
 103 .size   _armv8_aes_probe,.-_armv8_aes_probe
 104
 105 .global _armv8_sha1_probe
 106 .type   _armv8_sha1_probe,%function
 107 _armv8_sha1_probe:
 108         .byte   0x40,0x0c,0x00,0xf2     @ sha1c.32      q0,q0,q0
 109         bx      lr
 110 .size   _armv8_sha1_probe,.-_armv8_sha1_probe
 111
 112 .global _armv8_sha256_probe
 113 .type   _armv8_sha256_probe,%function
 114 _armv8_sha256_probe:
 115         .byte   0x40,0x0c,0x00,0xf3     @ sha256h.32    q0,q0,q0
 116         bx      lr
 117 .size   _armv8_sha256_probe,.-_armv8_sha256_probe
 118 .global _armv8_pmull_probe
 119 .type   _armv8_pmull_probe,%function
 120 _armv8_pmull_probe:
 121         .byte   0x00,0x0e,0xa0,0xf2     @ vmull.p64     q0,d0,d0
 122         bx      lr
 123 .size   _armv8_pmull_probe,.-_armv8_pmull_probe
 124 #endif
 125
 126 .global OPENSSL_wipe_cpu
 127 .type   OPENSSL_wipe_cpu,%function
 128 OPENSSL_wipe_cpu:
 129 #if __ARM_MAX_ARCH__>=7
 130         ldr     r0,.LOPENSSL_armcap
 131         adr     r1,.LOPENSSL_armcap
 132         ldr     r0,[r1,r0]
 133 #endif
 134         eor     r2,r2,r2
 135         eor     r3,r3,r3
 136         eor     ip,ip,ip
 137 #if __ARM_MAX_ARCH__>=7
 138         tst     r0,#1
 139         beq     .Lwipe_done
 140         veor    q0, q0, q0
 141         veor    q1, q1, q1
 142         veor    q2, q2, q2
 143         veor    q3, q3, q3
 144         veor    q8, q8, q8
 145         veor    q9, q9, q9
 146         veor    q10, q10, q10
 147         veor    q11, q11, q11
 148         veor    q12, q12, q12
 149         veor    q13, q13, q13
 150         veor    q14, q14, q14
 151         veor    q15, q15, q15
 152 .Lwipe_done:
 153 #endif
 154         mov     r0,sp
 155 #if __ARM_ARCH__>=5
 156         bx      lr
 157 #else
 158         tst     lr,#1
 159         moveq   pc,lr
 160         .word   0xe12fff1e      @ bx    lr
 161 #endif
 162 .size   OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
 163
 164 .global OPENSSL_instrument_bus
 165 .type   OPENSSL_instrument_bus,%function
 166 OPENSSL_instrument_bus:
 167         eor     r0,r0,r0
 168 #if __ARM_ARCH__>=5
 169         bx      lr
 170 #else
 171         tst     lr,#1
 172         moveq   pc,lr
 173         .word   0xe12fff1e      @ bx    lr
 174 #endif
 175 .size   OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
 176
 177 .global OPENSSL_instrument_bus2
 178 .type   OPENSSL_instrument_bus2,%function
 179 OPENSSL_instrument_bus2:
 180         eor     r0,r0,r0
 181 #if __ARM_ARCH__>=5
 182         bx      lr
 183 #else
 184         tst     lr,#1
 185         moveq   pc,lr
 186         .word   0xe12fff1e      @ bx    lr
 187 #endif
 188 .size   OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
 189
 190 .align  5
 191 #if __ARM_MAX_ARCH__>=7
 192 .LOPENSSL_armcap:
 193 .word   OPENSSL_armcap_P-.LOPENSSL_armcap
 194 #endif
 195 #if __ARM_ARCH__>=6
 196 .align  5
 197 #else
 198 .Lspinlock:
 199 .word   atomic_add_spinlock-.Lspinlock
 200 .align  5
 201
 202 .data
 203 .align  2
 204 atomic_add_spinlock:
 205 .word   0
 206 #endif
 207
 208 .comm   OPENSSL_armcap_P,4,4
 209 .hidden OPENSSL_armcap_P