]>
git.ipfire.org Git - thirdparty/openssl.git/blob - crypto/ppccap.c
2 * Copyright 2009-2018 The OpenSSL Project Authors. All Rights Reserved.
4 * Licensed under the Apache License 2.0 (the "License"). You may not use
5 * this file except in compliance with the License. You can obtain a copy
6 * in the file LICENSE in the source distribution or at
7 * https://www.openssl.org/source/license.html
16 #if defined(__linux) || defined(_AIX)
17 # include <sys/utsname.h>
19 #if defined(_AIX53) /* defined even on post-5.3 */
20 # include <sys/systemcfg.h>
21 # if !defined(__power_set)
22 # define __power_set(a) (_system_configuration.implementation & (a))
25 #if defined(__APPLE__) && defined(__MACH__)
26 # include <sys/types.h>
27 # include <sys/sysctl.h>
29 #include <openssl/crypto.h>
30 #include <openssl/bn.h>
31 #include <internal/cryptlib.h>
32 #include <crypto/chacha.h>
33 #include "bn/bn_local.h"
37 unsigned int OPENSSL_ppccap_P
= 0;
39 static sigset_t all_masked
;
42 #ifdef OPENSSL_BN_ASM_MONT
43 int bn_mul_mont(BN_ULONG
*rp
, const BN_ULONG
*ap
, const BN_ULONG
*bp
,
44 const BN_ULONG
*np
, const BN_ULONG
*n0
, int num
)
46 int bn_mul_mont_int(BN_ULONG
*rp
, const BN_ULONG
*ap
, const BN_ULONG
*bp
,
47 const BN_ULONG
*np
, const BN_ULONG
*n0
, int num
);
48 int bn_mul4x_mont_int(BN_ULONG
*rp
, const BN_ULONG
*ap
, const BN_ULONG
*bp
,
49 const BN_ULONG
*np
, const BN_ULONG
*n0
, int num
);
55 return bn_mul4x_mont_int(rp
, ap
, bp
, np
, n0
, num
);
58 * There used to be [optional] call to bn_mul_mont_fpu64 here,
59 * but above subroutine is faster on contemporary processors.
60 * Formulation means that there might be old processors where
61 * FPU code path would be faster, POWER6 perhaps, but there was
62 * no opportunity to figure it out...
65 return bn_mul_mont_int(rp
, ap
, bp
, np
, n0
, num
);
68 void sha256_block_p8(void *ctx
, const void *inp
, size_t len
);
69 void sha256_block_ppc(void *ctx
, const void *inp
, size_t len
);
70 void sha256_block_data_order(void *ctx
, const void *inp
, size_t len
);
71 void sha256_block_data_order(void *ctx
, const void *inp
, size_t len
)
73 OPENSSL_ppccap_P
& PPC_CRYPTO207
? sha256_block_p8(ctx
, inp
, len
) :
74 sha256_block_ppc(ctx
, inp
, len
);
77 void sha512_block_p8(void *ctx
, const void *inp
, size_t len
);
78 void sha512_block_ppc(void *ctx
, const void *inp
, size_t len
);
79 void sha512_block_data_order(void *ctx
, const void *inp
, size_t len
);
80 void sha512_block_data_order(void *ctx
, const void *inp
, size_t len
)
82 OPENSSL_ppccap_P
& PPC_CRYPTO207
? sha512_block_p8(ctx
, inp
, len
) :
83 sha512_block_ppc(ctx
, inp
, len
);
87 * TODO(3.0): Temporarily disabled some assembler that hasn't been brought into
88 * the FIPS module yet.
91 # ifndef OPENSSL_NO_CHACHA
92 void ChaCha20_ctr32_int(unsigned char *out
, const unsigned char *inp
,
93 size_t len
, const unsigned int key
[8],
94 const unsigned int counter
[4]);
95 void ChaCha20_ctr32_vmx(unsigned char *out
, const unsigned char *inp
,
96 size_t len
, const unsigned int key
[8],
97 const unsigned int counter
[4]);
98 void ChaCha20_ctr32_vsx(unsigned char *out
, const unsigned char *inp
,
99 size_t len
, const unsigned int key
[8],
100 const unsigned int counter
[4]);
101 void ChaCha20_ctr32(unsigned char *out
, const unsigned char *inp
,
102 size_t len
, const unsigned int key
[8],
103 const unsigned int counter
[4])
105 OPENSSL_ppccap_P
& PPC_CRYPTO207
106 ? ChaCha20_ctr32_vsx(out
, inp
, len
, key
, counter
)
107 : OPENSSL_ppccap_P
& PPC_ALTIVEC
108 ? ChaCha20_ctr32_vmx(out
, inp
, len
, key
, counter
)
109 : ChaCha20_ctr32_int(out
, inp
, len
, key
, counter
);
113 # ifndef OPENSSL_NO_POLY1305
114 void poly1305_init_int(void *ctx
, const unsigned char key
[16]);
115 void poly1305_blocks(void *ctx
, const unsigned char *inp
, size_t len
,
116 unsigned int padbit
);
117 void poly1305_emit(void *ctx
, unsigned char mac
[16],
118 const unsigned int nonce
[4]);
119 void poly1305_init_fpu(void *ctx
, const unsigned char key
[16]);
120 void poly1305_blocks_fpu(void *ctx
, const unsigned char *inp
, size_t len
,
121 unsigned int padbit
);
122 void poly1305_emit_fpu(void *ctx
, unsigned char mac
[16],
123 const unsigned int nonce
[4]);
124 void poly1305_init_vsx(void *ctx
, const unsigned char key
[16]);
125 void poly1305_blocks_vsx(void *ctx
, const unsigned char *inp
, size_t len
,
126 unsigned int padbit
);
127 void poly1305_emit_vsx(void *ctx
, unsigned char mac
[16],
128 const unsigned int nonce
[4]);
129 int poly1305_init(void *ctx
, const unsigned char key
[16], void *func
[2]);
130 int poly1305_init(void *ctx
, const unsigned char key
[16], void *func
[2])
132 if (OPENSSL_ppccap_P
& PPC_CRYPTO207
) {
133 poly1305_init_int(ctx
, key
);
134 func
[0] = (void*)(uintptr_t)poly1305_blocks_vsx
;
135 func
[1] = (void*)(uintptr_t)poly1305_emit
;
136 } else if (sizeof(size_t) == 4 && (OPENSSL_ppccap_P
& PPC_FPU
)) {
137 poly1305_init_fpu(ctx
, key
);
138 func
[0] = (void*)(uintptr_t)poly1305_blocks_fpu
;
139 func
[1] = (void*)(uintptr_t)poly1305_emit_fpu
;
141 poly1305_init_int(ctx
, key
);
142 func
[0] = (void*)(uintptr_t)poly1305_blocks
;
143 func
[1] = (void*)(uintptr_t)poly1305_emit
;
148 #endif /* FIPS_MODE */
150 #ifdef ECP_NISTZ256_ASM
151 void ecp_nistz256_mul_mont(unsigned long res
[4], const unsigned long a
[4],
152 const unsigned long b
[4]);
154 void ecp_nistz256_to_mont(unsigned long res
[4], const unsigned long in
[4]);
155 void ecp_nistz256_to_mont(unsigned long res
[4], const unsigned long in
[4])
157 static const unsigned long RR
[] = { 0x0000000000000003U
,
160 0x00000004fffffffdU
};
162 ecp_nistz256_mul_mont(res
, in
, RR
);
165 void ecp_nistz256_from_mont(unsigned long res
[4], const unsigned long in
[4]);
166 void ecp_nistz256_from_mont(unsigned long res
[4], const unsigned long in
[4])
168 static const unsigned long one
[] = { 1, 0, 0, 0 };
170 ecp_nistz256_mul_mont(res
, in
, one
);
174 static sigjmp_buf ill_jmp
;
175 static void ill_handler(int sig
)
177 siglongjmp(ill_jmp
, sig
);
180 void OPENSSL_fpu_probe(void);
181 void OPENSSL_ppc64_probe(void);
182 void OPENSSL_altivec_probe(void);
183 void OPENSSL_crypto207_probe(void);
184 void OPENSSL_madd300_probe(void);
186 long OPENSSL_rdtsc_mftb(void);
187 long OPENSSL_rdtsc_mfspr268(void);
189 uint32_t OPENSSL_rdtsc(void)
191 if (OPENSSL_ppccap_P
& PPC_MFTB
)
192 return OPENSSL_rdtsc_mftb();
193 else if (OPENSSL_ppccap_P
& PPC_MFSPR268
)
194 return OPENSSL_rdtsc_mfspr268();
199 size_t OPENSSL_instrument_bus_mftb(unsigned int *, size_t);
200 size_t OPENSSL_instrument_bus_mfspr268(unsigned int *, size_t);
202 size_t OPENSSL_instrument_bus(unsigned int *out
, size_t cnt
)
204 if (OPENSSL_ppccap_P
& PPC_MFTB
)
205 return OPENSSL_instrument_bus_mftb(out
, cnt
);
206 else if (OPENSSL_ppccap_P
& PPC_MFSPR268
)
207 return OPENSSL_instrument_bus_mfspr268(out
, cnt
);
212 size_t OPENSSL_instrument_bus2_mftb(unsigned int *, size_t, size_t);
213 size_t OPENSSL_instrument_bus2_mfspr268(unsigned int *, size_t, size_t);
215 size_t OPENSSL_instrument_bus2(unsigned int *out
, size_t cnt
, size_t max
)
217 if (OPENSSL_ppccap_P
& PPC_MFTB
)
218 return OPENSSL_instrument_bus2_mftb(out
, cnt
, max
);
219 else if (OPENSSL_ppccap_P
& PPC_MFSPR268
)
220 return OPENSSL_instrument_bus2_mfspr268(out
, cnt
, max
);
225 #if defined(__GLIBC__) && defined(__GLIBC_PREREQ)
226 # if __GLIBC_PREREQ(2, 16)
227 # include <sys/auxv.h>
228 # define OSSL_IMPLEMENT_GETAUXVAL
232 /* I wish <sys/auxv.h> was universally available */
233 #define HWCAP 16 /* AT_HWCAP */
234 #define HWCAP_PPC64 (1U << 30)
235 #define HWCAP_ALTIVEC (1U << 28)
236 #define HWCAP_FPU (1U << 27)
237 #define HWCAP_POWER6_EXT (1U << 9)
238 #define HWCAP_VSX (1U << 7)
240 #define HWCAP2 26 /* AT_HWCAP2 */
241 #define HWCAP_VEC_CRYPTO (1U << 25)
242 #define HWCAP_ARCH_3_00 (1U << 23)
244 # if defined(__GNUC__) && __GNUC__>=2
245 __attribute__ ((constructor
))
247 void OPENSSL_cpuid_setup(void)
250 struct sigaction ill_oact
, ill_act
;
252 static int trigger
= 0;
258 if ((e
= getenv("OPENSSL_ppccap"))) {
259 OPENSSL_ppccap_P
= strtoul(e
, NULL
, 0);
263 OPENSSL_ppccap_P
= 0;
266 OPENSSL_ppccap_P
|= PPC_FPU
;
268 if (sizeof(size_t) == 4) {
270 # if defined(_SC_AIX_KERNEL_BITMODE)
271 if (sysconf(_SC_AIX_KERNEL_BITMODE
) != 64)
274 if (uname(&uts
) != 0 || atoi(uts
.version
) < 6)
278 # if defined(__power_set)
280 * Value used in __power_set is a single-bit 1<<n one denoting
281 * specific processor class. Incidentally 0xffffffff<<n can be
282 * used to denote specific processor and its successors.
284 if (sizeof(size_t) == 4) {
285 /* In 32-bit case PPC_FPU64 is always fastest [if option] */
286 if (__power_set(0xffffffffU
<<13)) /* POWER5 and later */
287 OPENSSL_ppccap_P
|= PPC_FPU64
;
289 /* In 64-bit case PPC_FPU64 is fastest only on POWER6 */
290 if (__power_set(0x1U
<<14)) /* POWER6 */
291 OPENSSL_ppccap_P
|= PPC_FPU64
;
294 if (__power_set(0xffffffffU
<<14)) /* POWER6 and later */
295 OPENSSL_ppccap_P
|= PPC_ALTIVEC
;
297 if (__power_set(0xffffffffU
<<16)) /* POWER8 and later */
298 OPENSSL_ppccap_P
|= PPC_CRYPTO207
;
300 if (__power_set(0xffffffffU
<<17)) /* POWER9 and later */
301 OPENSSL_ppccap_P
|= PPC_MADD300
;
307 #if defined(__APPLE__) && defined(__MACH__)
308 OPENSSL_ppccap_P
|= PPC_FPU
;
312 size_t len
= sizeof(val
);
314 if (sysctlbyname("hw.optional.64bitops", &val
, &len
, NULL
, 0) == 0) {
316 OPENSSL_ppccap_P
|= PPC_FPU64
;
320 if (sysctlbyname("hw.optional.altivec", &val
, &len
, NULL
, 0) == 0) {
322 OPENSSL_ppccap_P
|= PPC_ALTIVEC
;
329 #ifdef OSSL_IMPLEMENT_GETAUXVAL
331 unsigned long hwcap
= getauxval(HWCAP
);
332 unsigned long hwcap2
= getauxval(HWCAP2
);
334 if (hwcap
& HWCAP_FPU
) {
335 OPENSSL_ppccap_P
|= PPC_FPU
;
337 if (sizeof(size_t) == 4) {
338 /* In 32-bit case PPC_FPU64 is always fastest [if option] */
339 if (hwcap
& HWCAP_PPC64
)
340 OPENSSL_ppccap_P
|= PPC_FPU64
;
342 /* In 64-bit case PPC_FPU64 is fastest only on POWER6 */
343 if (hwcap
& HWCAP_POWER6_EXT
)
344 OPENSSL_ppccap_P
|= PPC_FPU64
;
348 if (hwcap
& HWCAP_ALTIVEC
) {
349 OPENSSL_ppccap_P
|= PPC_ALTIVEC
;
351 if ((hwcap
& HWCAP_VSX
) && (hwcap2
& HWCAP_VEC_CRYPTO
))
352 OPENSSL_ppccap_P
|= PPC_CRYPTO207
;
355 if (hwcap2
& HWCAP_ARCH_3_00
) {
356 OPENSSL_ppccap_P
|= PPC_MADD300
;
361 sigfillset(&all_masked
);
362 sigdelset(&all_masked
, SIGILL
);
363 sigdelset(&all_masked
, SIGTRAP
);
365 sigdelset(&all_masked
, SIGEMT
);
367 sigdelset(&all_masked
, SIGFPE
);
368 sigdelset(&all_masked
, SIGBUS
);
369 sigdelset(&all_masked
, SIGSEGV
);
371 memset(&ill_act
, 0, sizeof(ill_act
));
372 ill_act
.sa_handler
= ill_handler
;
373 ill_act
.sa_mask
= all_masked
;
375 sigprocmask(SIG_SETMASK
, &ill_act
.sa_mask
, &oset
);
376 sigaction(SIGILL
, &ill_act
, &ill_oact
);
378 #ifndef OSSL_IMPLEMENT_GETAUXVAL
379 if (sigsetjmp(ill_jmp
,1) == 0) {
381 OPENSSL_ppccap_P
|= PPC_FPU
;
383 if (sizeof(size_t) == 4) {
386 if (uname(&uts
) == 0 && strcmp(uts
.machine
, "ppc64") == 0)
388 if (sigsetjmp(ill_jmp
, 1) == 0) {
389 OPENSSL_ppc64_probe();
390 OPENSSL_ppccap_P
|= PPC_FPU64
;
394 * Wanted code detecting POWER6 CPU and setting PPC_FPU64
399 if (sigsetjmp(ill_jmp
, 1) == 0) {
400 OPENSSL_altivec_probe();
401 OPENSSL_ppccap_P
|= PPC_ALTIVEC
;
402 if (sigsetjmp(ill_jmp
, 1) == 0) {
403 OPENSSL_crypto207_probe();
404 OPENSSL_ppccap_P
|= PPC_CRYPTO207
;
408 if (sigsetjmp(ill_jmp
, 1) == 0) {
409 OPENSSL_madd300_probe();
410 OPENSSL_ppccap_P
|= PPC_MADD300
;
414 if (sigsetjmp(ill_jmp
, 1) == 0) {
415 OPENSSL_rdtsc_mftb();
416 OPENSSL_ppccap_P
|= PPC_MFTB
;
417 } else if (sigsetjmp(ill_jmp
, 1) == 0) {
418 OPENSSL_rdtsc_mfspr268();
419 OPENSSL_ppccap_P
|= PPC_MFSPR268
;
422 sigaction(SIGILL
, &ill_oact
, NULL
);
423 sigprocmask(SIG_SETMASK
, &oset
, NULL
);