drivers/block/sata_ceva.c

   1 /*
   2  * (C) Copyright 2015 - 2016 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <netdev.h>
  10 #include <ahci.h>
  11 #include <scsi.h>
  12 #include <asm/arch/hardware.h>
  13
  14 #include <asm/io.h>
  15
  16 /* Vendor Specific Register Offsets */
  17 #define AHCI_VEND_PCFG  0xA4
  18 #define AHCI_VEND_PPCFG 0xA8
  19 #define AHCI_VEND_PP2C  0xAC
  20 #define AHCI_VEND_PP3C  0xB0
  21 #define AHCI_VEND_PP4C  0xB4
  22 #define AHCI_VEND_PP5C  0xB8
  23 #define AHCI_VEND_PAXIC 0xC0
  24 #define AHCI_VEND_PTC   0xC8
  25
  26 /* Vendor Specific Register bit definitions */
  27 #define PAXIC_ADBW_BW64 0x1
  28 #define PAXIC_MAWIDD    (1 << 8)
  29 #define PAXIC_MARIDD    (1 << 16)
  30 #define PAXIC_OTL       (0x4 << 20)
  31
  32 #define PCFG_TPSS_VAL   (0x32 << 16)
  33 #define PCFG_TPRS_VAL   (0x2 << 12)
  34 #define PCFG_PAD_VAL    0x2
  35
  36 #define PPCFG_TTA       0x1FFFE
  37 #define PPCFG_PSSO_EN   (1 << 28)
  38 #define PPCFG_PSS_EN    (1 << 29)
  39 #define PPCFG_ESDF_EN   (1 << 31)
  40
  41 #define PP2C_CIBGMN     0x0F
  42 #define PP2C_CIBGMX     (0x25 << 8)
  43 #define PP2C_CIBGN      (0x18 << 16)
  44 #define PP2C_CINMP      (0x29 << 24)
  45
  46 #define PP3C_CWBGMN     0x04
  47 #define PP3C_CWBGMX     (0x0B << 8)
  48 #define PP3C_CWBGN      (0x08 << 16)
  49 #define PP3C_CWNMP      (0x0F << 24)
  50
  51 #define PP4C_BMX        0x0a
  52 #define PP4C_BNM        (0x08 << 8)
  53 #define PP4C_SFD        (0x4a << 16)
  54 #define PP4C_PTST       (0x06 << 24)
  55
  56 #define PP5C_RIT        0x60216
  57 #define PP5C_RCT        (0x7f0 << 20)
  58
  59 #define PTC_RX_WM_VAL   0x40
  60 #define PTC_RSVD        (1 << 27)
  61
  62 #define PORT0_BASE      0x100
  63 #define PORT1_BASE      0x180
  64
  65 /* Port Control Register Bit Definitions */
  66 #define PORT_SCTL_SPD_GEN3      (0x3 << 4)
  67 #define PORT_SCTL_SPD_GEN2      (0x2 << 4)
  68 #define PORT_SCTL_SPD_GEN1      (0x1 << 4)
  69 #define PORT_SCTL_IPM           (0x3 << 8)
  70
  71 #define PORT_BASE       0x100
  72 #define PORT_OFFSET     0x80
  73 #define NR_PORTS        2
  74 #define DRV_NAME        "ahci-ceva"
  75 #define CEVA_FLAG_BROKEN_GEN2   1
  76
  77 static int ceva_init_sata(ulong mmio)
  78 {
  79         ulong tmp;
  80         int i;
  81
  82         /*
  83          * AXI Data bus width to 64
  84          * Set Mem Addr Read, Write ID for data transfers
  85          * Transfer limit to 72 DWord
  86          */
  87         tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
  88         writel(tmp, mmio + AHCI_VEND_PAXIC);
  89
  90         /* Set AHCI Enable */
  91         tmp = readl(mmio + HOST_CTL);
  92         tmp |= HOST_AHCI_EN;
  93         writel(tmp, mmio + HOST_CTL);
  94
  95         for (i = 0; i < NR_PORTS; i++) {
  96                 /* TPSS TPRS scalars, CISE and Port Addr */
  97                 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
  98                 writel(tmp, mmio + AHCI_VEND_PCFG);
  99
 100                 /* Port Phy Cfg register enables */
 101                 tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
 102                 writel(tmp, mmio + AHCI_VEND_PPCFG);
 103
 104                 /* Rx Watermark setting  */
 105                 tmp = PTC_RX_WM_VAL | PTC_RSVD;
 106                 writel(tmp, mmio + AHCI_VEND_PTC);
 107
 108                 /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
 109                 tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
 110                 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
 111         }
 112         return 0;
 113 }
 114
 115 static int sata_ceva_probe(struct udevice *dev)
 116 {
 117         struct scsi_platdata *plat = dev_get_platdata(dev);
 118
 119         ceva_init_sata(plat->base);
 120         return 0;
 121 }
 122
 123 static const struct udevice_id sata_ceva_ids[] = {
 124         { .compatible = "ceva,ahci-1v84" },
 125         { }
 126 };
 127
 128 static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
 129 {
 130         struct scsi_platdata *plat = dev_get_platdata(dev);
 131
 132         plat->base = dev_get_addr(dev);
 133         if (plat->base == FDT_ADDR_T_NONE)
 134                 return -EINVAL;
 135
 136         /* Hardcode number for ceva sata controller */
 137         plat->max_lun = 1; /* Actually two but untested */
 138         plat->max_id = 2;
 139
 140         return 0;
 141 }
 142
 143 U_BOOT_DRIVER(ceva_host_blk) = {
 144         .name = "ceva_sata",
 145         .id = UCLASS_SCSI,
 146         .of_match = sata_ceva_ids,
 147         .probe = sata_ceva_probe,
 148         .ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
 149         .platdata_auto_alloc_size = sizeof(struct scsi_platdata),
 150 };