3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
36 #include <asm/arch/mmc_host_def.h>
37 #if !defined(CONFIG_SOC_KEYSTONE)
39 #include <asm/arch/sys_proto.h>
41 #ifdef CONFIG_MMC_OMAP36XX_PINS
42 #include <asm/arch/mux.h>
46 DECLARE_GLOBAL_DATA_PTR
;
48 /* simplify defines to OMAP_HSMMC_USE_GPIO */
49 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51 #define OMAP_HSMMC_USE_GPIO
53 #undef OMAP_HSMMC_USE_GPIO
56 /* common definitions for all OMAPs */
57 #define SYSCTL_SRC (1 << 25)
58 #define SYSCTL_SRD (1 << 26)
60 struct omap_hsmmc_data
{
61 struct hsmmc
*base_addr
;
62 #if !CONFIG_IS_ENABLED(DM_MMC)
63 struct mmc_config cfg
;
67 #ifdef OMAP_HSMMC_USE_GPIO
68 #if CONFIG_IS_ENABLED(DM_MMC)
69 struct gpio_desc cd_gpio
; /* Change Detect GPIO */
70 struct gpio_desc wp_gpio
; /* Write Protect GPIO */
78 #ifndef CONFIG_OMAP34XX
79 struct omap_hsmmc_adma_desc
*adma_desc_table
;
84 #ifndef CONFIG_OMAP34XX
85 struct omap_hsmmc_adma_desc
{
92 #define ADMA_MAX_LEN 63488
94 /* Decriptor table defines */
95 #define ADMA_DESC_ATTR_VALID BIT(0)
96 #define ADMA_DESC_ATTR_END BIT(1)
97 #define ADMA_DESC_ATTR_INT BIT(2)
98 #define ADMA_DESC_ATTR_ACT1 BIT(4)
99 #define ADMA_DESC_ATTR_ACT2 BIT(5)
101 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
102 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
105 /* If we fail after 1 second wait, something is really bad */
106 #define MAX_RETRY_MS 1000
108 /* DMA transfers can take a long time if a lot a data is transferred.
109 * The timeout must take in account the amount of data. Let's assume
110 * that the time will never exceed 333 ms per MB (in other word we assume
111 * that the bandwidth is always above 3MB/s).
113 #define DMA_TIMEOUT_PER_MB 333
114 #define OMAP_HSMMC_USE_ADMA BIT(2)
116 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
);
117 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
119 static void omap_hsmmc_start_clock(struct hsmmc
*mmc_base
);
120 static void omap_hsmmc_stop_clock(struct hsmmc
*mmc_base
);
122 static inline struct omap_hsmmc_data
*omap_hsmmc_get_data(struct mmc
*mmc
)
124 #if CONFIG_IS_ENABLED(DM_MMC)
125 return dev_get_priv(mmc
->dev
);
127 return (struct omap_hsmmc_data
*)mmc
->priv
;
130 static inline struct mmc_config
*omap_hsmmc_get_cfg(struct mmc
*mmc
)
132 #if CONFIG_IS_ENABLED(DM_MMC)
133 struct omap_hsmmc_plat
*plat
= dev_get_platdata(mmc
->dev
);
136 return &((struct omap_hsmmc_data
*)mmc
->priv
)->cfg
;
140 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
141 static int omap_mmc_setup_gpio_in(int gpio
, const char *label
)
145 #ifndef CONFIG_DM_GPIO
146 if (!gpio_is_valid(gpio
))
149 ret
= gpio_request(gpio
, label
);
153 ret
= gpio_direction_input(gpio
);
161 static unsigned char mmc_board_init(struct mmc
*mmc
)
163 #if defined(CONFIG_OMAP34XX)
164 struct mmc_config
*cfg
= omap_hsmmc_get_cfg(mmc
);
165 t2_t
*t2_base
= (t2_t
*)T2_BASE
;
166 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
168 #ifdef CONFIG_MMC_OMAP36XX_PINS
169 u32 wkup_ctrl
= readl(OMAP34XX_CTRL_WKUP_CTRL
);
172 pbias_lite
= readl(&t2_base
->pbias_lite
);
173 pbias_lite
&= ~(PBIASLITEPWRDNZ1
| PBIASLITEPWRDNZ0
);
174 #ifdef CONFIG_TARGET_OMAP3_CAIRO
175 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
176 pbias_lite
&= ~PBIASLITEVMODE0
;
178 #ifdef CONFIG_MMC_OMAP36XX_PINS
179 if (get_cpu_family() == CPU_OMAP36XX
) {
180 /* Disable extended drain IO before changing PBIAS */
181 wkup_ctrl
&= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ
;
182 writel(wkup_ctrl
, OMAP34XX_CTRL_WKUP_CTRL
);
185 writel(pbias_lite
, &t2_base
->pbias_lite
);
187 writel(pbias_lite
| PBIASLITEPWRDNZ1
|
188 PBIASSPEEDCTRL0
| PBIASLITEPWRDNZ0
,
189 &t2_base
->pbias_lite
);
191 #ifdef CONFIG_MMC_OMAP36XX_PINS
192 if (get_cpu_family() == CPU_OMAP36XX
)
193 /* Enable extended drain IO after changing PBIAS */
195 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ
,
196 OMAP34XX_CTRL_WKUP_CTRL
);
198 writel(readl(&t2_base
->devconf0
) | MMCSDIO1ADPCLKISEL
,
201 writel(readl(&t2_base
->devconf1
) | MMCSDIO2ADPCLKISEL
,
204 /* Change from default of 52MHz to 26MHz if necessary */
205 if (!(cfg
->host_caps
& MMC_MODE_HS_52MHz
))
206 writel(readl(&t2_base
->ctl_prog_io1
) & ~CTLPROGIO1SPEEDCTRL
,
207 &t2_base
->ctl_prog_io1
);
209 writel(readl(&prcm_base
->fclken1_core
) |
210 EN_MMC1
| EN_MMC2
| EN_MMC3
,
211 &prcm_base
->fclken1_core
);
213 writel(readl(&prcm_base
->iclken1_core
) |
214 EN_MMC1
| EN_MMC2
| EN_MMC3
,
215 &prcm_base
->iclken1_core
);
218 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
219 /* PBIAS config needed for MMC1 only */
220 if (mmc_get_blk_desc(mmc
)->devnum
== 0)
221 vmmc_pbias_config(LDO_VOLT_3V0
);
227 void mmc_init_stream(struct hsmmc
*mmc_base
)
231 writel(readl(&mmc_base
->con
) | INIT_INITSTREAM
, &mmc_base
->con
);
233 writel(MMC_CMD0
, &mmc_base
->cmd
);
234 start
= get_timer(0);
235 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
236 if (get_timer(0) - start
> MAX_RETRY_MS
) {
237 printf("%s: timedout waiting for cc!\n", __func__
);
241 writel(CC_MASK
, &mmc_base
->stat
)
243 writel(MMC_CMD0
, &mmc_base
->cmd
)
245 start
= get_timer(0);
246 while (!(readl(&mmc_base
->stat
) & CC_MASK
)) {
247 if (get_timer(0) - start
> MAX_RETRY_MS
) {
248 printf("%s: timedout waiting for cc2!\n", __func__
);
252 writel(readl(&mmc_base
->con
) & ~INIT_INITSTREAM
, &mmc_base
->con
);
255 static int omap_hsmmc_init_setup(struct mmc
*mmc
)
257 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
258 struct hsmmc
*mmc_base
;
259 unsigned int reg_val
;
263 mmc_base
= priv
->base_addr
;
266 writel(readl(&mmc_base
->sysconfig
) | MMC_SOFTRESET
,
267 &mmc_base
->sysconfig
);
268 start
= get_timer(0);
269 while ((readl(&mmc_base
->sysstatus
) & RESETDONE
) == 0) {
270 if (get_timer(0) - start
> MAX_RETRY_MS
) {
271 printf("%s: timedout waiting for cc2!\n", __func__
);
275 writel(readl(&mmc_base
->sysctl
) | SOFTRESETALL
, &mmc_base
->sysctl
);
276 start
= get_timer(0);
277 while ((readl(&mmc_base
->sysctl
) & SOFTRESETALL
) != 0x0) {
278 if (get_timer(0) - start
> MAX_RETRY_MS
) {
279 printf("%s: timedout waiting for softresetall!\n",
284 #ifndef CONFIG_OMAP34XX
285 reg_val
= readl(&mmc_base
->hl_hwinfo
);
286 if (reg_val
& MADMA_EN
)
287 priv
->controller_flags
|= OMAP_HSMMC_USE_ADMA
;
289 writel(DTW_1_BITMODE
| SDBP_PWROFF
| SDVS_3V0
, &mmc_base
->hctl
);
290 writel(readl(&mmc_base
->capa
) | VS30_3V0SUP
| VS18_1V8SUP
,
293 reg_val
= readl(&mmc_base
->con
) & RESERVED_MASK
;
295 writel(CTPL_MMC_SD
| reg_val
| WPP_ACTIVEHIGH
| CDP_ACTIVEHIGH
|
296 MIT_CTO
| DW8_1_4BITMODE
| MODE_FUNC
| STR_BLOCK
|
297 HR_NOHOSTRESP
| INIT_NOINIT
| NOOPENDRAIN
, &mmc_base
->con
);
300 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
| CEN_MASK
),
301 (ICE_STOP
| DTO_15THDTO
));
302 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
303 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
304 start
= get_timer(0);
305 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
306 if (get_timer(0) - start
> MAX_RETRY_MS
) {
307 printf("%s: timedout waiting for ics!\n", __func__
);
311 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
313 writel(readl(&mmc_base
->hctl
) | SDBP_PWRON
, &mmc_base
->hctl
);
315 writel(IE_BADA
| IE_CERR
| IE_DEB
| IE_DCRC
| IE_DTO
| IE_CIE
|
316 IE_CEB
| IE_CCRC
| IE_ADMAE
| IE_CTO
| IE_BRR
| IE_BWR
| IE_TC
|
317 IE_CC
, &mmc_base
->ie
);
319 mmc_init_stream(mmc_base
);
325 * MMC controller internal finite state machine reset
327 * Used to reset command or data internal state machines, using respectively
328 * SRC or SRD bit of SYSCTL register
330 static void mmc_reset_controller_fsm(struct hsmmc
*mmc_base
, u32 bit
)
334 mmc_reg_out(&mmc_base
->sysctl
, bit
, bit
);
337 * CMD(DAT) lines reset procedures are slightly different
338 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
339 * According to OMAP3 TRM:
340 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
342 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
343 * procedure steps must be as follows:
344 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
345 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
346 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
347 * 3. Wait until the SRC (SRD) bit returns to 0x0
348 * (reset procedure is completed).
350 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
351 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
352 if (!(readl(&mmc_base
->sysctl
) & bit
)) {
353 start
= get_timer(0);
354 while (!(readl(&mmc_base
->sysctl
) & bit
)) {
355 if (get_timer(0) - start
> MAX_RETRY_MS
)
360 start
= get_timer(0);
361 while ((readl(&mmc_base
->sysctl
) & bit
) != 0) {
362 if (get_timer(0) - start
> MAX_RETRY_MS
) {
363 printf("%s: timedout waiting for sysctl %x to clear\n",
370 #ifndef CONFIG_OMAP34XX
371 static void omap_hsmmc_adma_desc(struct mmc
*mmc
, char *buf
, u16 len
, bool end
)
373 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
374 struct omap_hsmmc_adma_desc
*desc
;
377 desc
= &priv
->adma_desc_table
[priv
->desc_slot
];
379 attr
= ADMA_DESC_ATTR_VALID
| ADMA_DESC_TRANSFER_DATA
;
383 attr
|= ADMA_DESC_ATTR_END
;
386 desc
->addr
= (u32
)buf
;
391 static void omap_hsmmc_prepare_adma_table(struct mmc
*mmc
,
392 struct mmc_data
*data
)
394 uint total_len
= data
->blocksize
* data
->blocks
;
395 uint desc_count
= DIV_ROUND_UP(total_len
, ADMA_MAX_LEN
);
396 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
401 priv
->adma_desc_table
= (struct omap_hsmmc_adma_desc
*)
402 memalign(ARCH_DMA_MINALIGN
, desc_count
*
403 sizeof(struct omap_hsmmc_adma_desc
));
405 if (data
->flags
& MMC_DATA_READ
)
408 buf
= (char *)data
->src
;
411 omap_hsmmc_adma_desc(mmc
, buf
, ADMA_MAX_LEN
, false);
413 total_len
-= ADMA_MAX_LEN
;
416 omap_hsmmc_adma_desc(mmc
, buf
, total_len
, true);
418 flush_dcache_range((long)priv
->adma_desc_table
,
419 (long)priv
->adma_desc_table
+
421 sizeof(struct omap_hsmmc_adma_desc
),
425 static void omap_hsmmc_prepare_data(struct mmc
*mmc
, struct mmc_data
*data
)
427 struct hsmmc
*mmc_base
;
428 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
432 mmc_base
= priv
->base_addr
;
433 omap_hsmmc_prepare_adma_table(mmc
, data
);
435 if (data
->flags
& MMC_DATA_READ
)
438 buf
= (char *)data
->src
;
440 val
= readl(&mmc_base
->hctl
);
442 writel(val
, &mmc_base
->hctl
);
444 val
= readl(&mmc_base
->con
);
446 writel(val
, &mmc_base
->con
);
448 writel((u32
)priv
->adma_desc_table
, &mmc_base
->admasal
);
450 flush_dcache_range((u32
)buf
,
452 ROUND(data
->blocksize
* data
->blocks
,
456 static void omap_hsmmc_dma_cleanup(struct mmc
*mmc
)
458 struct hsmmc
*mmc_base
;
459 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
462 mmc_base
= priv
->base_addr
;
464 val
= readl(&mmc_base
->con
);
466 writel(val
, &mmc_base
->con
);
468 val
= readl(&mmc_base
->hctl
);
470 writel(val
, &mmc_base
->hctl
);
472 kfree(priv
->adma_desc_table
);
475 #define omap_hsmmc_adma_desc
476 #define omap_hsmmc_prepare_adma_table
477 #define omap_hsmmc_prepare_data
478 #define omap_hsmmc_dma_cleanup
481 #if !CONFIG_IS_ENABLED(DM_MMC)
482 static int omap_hsmmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
,
483 struct mmc_data
*data
)
485 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
487 static int omap_hsmmc_send_cmd(struct udevice
*dev
, struct mmc_cmd
*cmd
,
488 struct mmc_data
*data
)
490 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
491 #ifndef CONFIG_OMAP34XX
492 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
493 struct mmc
*mmc
= upriv
->mmc
;
496 struct hsmmc
*mmc_base
;
497 unsigned int flags
, mmc_stat
;
500 mmc_base
= priv
->base_addr
;
502 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
505 start
= get_timer(0);
506 while ((readl(&mmc_base
->pstate
) & (DATI_MASK
| CMDI_MASK
)) != 0) {
507 if (get_timer(0) - start
> MAX_RETRY_MS
) {
508 printf("%s: timedout waiting on cmd inhibit to clear\n",
513 writel(0xFFFFFFFF, &mmc_base
->stat
);
514 start
= get_timer(0);
515 while (readl(&mmc_base
->stat
)) {
516 if (get_timer(0) - start
> MAX_RETRY_MS
) {
517 printf("%s: timedout waiting for STAT (%x) to clear\n",
518 __func__
, readl(&mmc_base
->stat
));
524 * CMDIDX[13:8] : Command index
525 * DATAPRNT[5] : Data Present Select
526 * ENCMDIDX[4] : Command Index Check Enable
527 * ENCMDCRC[3] : Command CRC Check Enable
532 * 11 = Length 48 Check busy after response
534 /* Delay added before checking the status of frq change
535 * retry not supported by mmc.c(core file)
537 if (cmd
->cmdidx
== SD_CMD_APP_SEND_SCR
)
538 udelay(50000); /* wait 50 ms */
540 if (!(cmd
->resp_type
& MMC_RSP_PRESENT
))
542 else if (cmd
->resp_type
& MMC_RSP_136
)
543 flags
= RSP_TYPE_LGHT136
| CICE_NOCHECK
;
544 else if (cmd
->resp_type
& MMC_RSP_BUSY
)
545 flags
= RSP_TYPE_LGHT48B
;
547 flags
= RSP_TYPE_LGHT48
;
549 /* enable default flags */
550 flags
= flags
| (CMD_TYPE_NORMAL
| CICE_NOCHECK
| CCCE_NOCHECK
|
552 flags
&= ~(ACEN_ENABLE
| BCE_ENABLE
| DE_ENABLE
);
554 if (cmd
->resp_type
& MMC_RSP_CRC
)
556 if (cmd
->resp_type
& MMC_RSP_OPCODE
)
560 if ((cmd
->cmdidx
== MMC_CMD_READ_MULTIPLE_BLOCK
) ||
561 (cmd
->cmdidx
== MMC_CMD_WRITE_MULTIPLE_BLOCK
)) {
562 flags
|= (MSBS_MULTIBLK
| BCE_ENABLE
| ACEN_ENABLE
);
563 data
->blocksize
= 512;
564 writel(data
->blocksize
| (data
->blocks
<< 16),
567 writel(data
->blocksize
| NBLK_STPCNT
, &mmc_base
->blk
);
569 if (data
->flags
& MMC_DATA_READ
)
570 flags
|= (DP_DATA
| DDIR_READ
);
572 flags
|= (DP_DATA
| DDIR_WRITE
);
574 #ifndef CONFIG_OMAP34XX
575 if ((priv
->controller_flags
& OMAP_HSMMC_USE_ADMA
) &&
576 !mmc_is_tuning_cmd(cmd
->cmdidx
)) {
577 omap_hsmmc_prepare_data(mmc
, data
);
583 writel(cmd
->cmdarg
, &mmc_base
->arg
);
584 udelay(20); /* To fix "No status update" error on eMMC */
585 writel((cmd
->cmdidx
<< 24) | flags
, &mmc_base
->cmd
);
587 start
= get_timer(0);
589 mmc_stat
= readl(&mmc_base
->stat
);
590 if (get_timer(start
) > MAX_RETRY_MS
) {
591 printf("%s : timeout: No status update\n", __func__
);
596 if ((mmc_stat
& IE_CTO
) != 0) {
597 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRC
);
599 } else if ((mmc_stat
& ERRI_MASK
) != 0)
602 if (mmc_stat
& CC_MASK
) {
603 writel(CC_MASK
, &mmc_base
->stat
);
604 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
605 if (cmd
->resp_type
& MMC_RSP_136
) {
606 /* response type 2 */
607 cmd
->response
[3] = readl(&mmc_base
->rsp10
);
608 cmd
->response
[2] = readl(&mmc_base
->rsp32
);
609 cmd
->response
[1] = readl(&mmc_base
->rsp54
);
610 cmd
->response
[0] = readl(&mmc_base
->rsp76
);
612 /* response types 1, 1b, 3, 4, 5, 6 */
613 cmd
->response
[0] = readl(&mmc_base
->rsp10
);
617 #ifndef CONFIG_OMAP34XX
618 if ((priv
->controller_flags
& OMAP_HSMMC_USE_ADMA
) && data
&&
619 !mmc_is_tuning_cmd(cmd
->cmdidx
)) {
622 if (mmc_stat
& IE_ADMAE
) {
623 omap_hsmmc_dma_cleanup(mmc
);
627 sz_mb
= DIV_ROUND_UP(data
->blocksize
* data
->blocks
, 1 << 20);
628 timeout
= sz_mb
* DMA_TIMEOUT_PER_MB
;
629 if (timeout
< MAX_RETRY_MS
)
630 timeout
= MAX_RETRY_MS
;
632 start
= get_timer(0);
634 mmc_stat
= readl(&mmc_base
->stat
);
635 if (mmc_stat
& TC_MASK
) {
636 writel(readl(&mmc_base
->stat
) | TC_MASK
,
640 if (get_timer(start
) > timeout
) {
641 printf("%s : DMA timeout: No status update\n",
647 omap_hsmmc_dma_cleanup(mmc
);
652 if (data
&& (data
->flags
& MMC_DATA_READ
)) {
653 mmc_read_data(mmc_base
, data
->dest
,
654 data
->blocksize
* data
->blocks
);
655 } else if (data
&& (data
->flags
& MMC_DATA_WRITE
)) {
656 mmc_write_data(mmc_base
, data
->src
,
657 data
->blocksize
* data
->blocks
);
662 static int mmc_read_data(struct hsmmc
*mmc_base
, char *buf
, unsigned int size
)
664 unsigned int *output_buf
= (unsigned int *)buf
;
665 unsigned int mmc_stat
;
671 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
675 ulong start
= get_timer(0);
677 mmc_stat
= readl(&mmc_base
->stat
);
678 if (get_timer(0) - start
> MAX_RETRY_MS
) {
679 printf("%s: timedout waiting for status!\n",
683 } while (mmc_stat
== 0);
685 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
686 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
688 if ((mmc_stat
& ERRI_MASK
) != 0)
691 if (mmc_stat
& BRR_MASK
) {
694 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
696 for (k
= 0; k
< count
; k
++) {
697 *output_buf
= readl(&mmc_base
->data
);
703 if (mmc_stat
& BWR_MASK
)
704 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
707 if (mmc_stat
& TC_MASK
) {
708 writel(readl(&mmc_base
->stat
) | TC_MASK
,
716 static int mmc_write_data(struct hsmmc
*mmc_base
, const char *buf
,
719 unsigned int *input_buf
= (unsigned int *)buf
;
720 unsigned int mmc_stat
;
726 count
= (size
> MMCSD_SECTOR_SIZE
) ? MMCSD_SECTOR_SIZE
: size
;
730 ulong start
= get_timer(0);
732 mmc_stat
= readl(&mmc_base
->stat
);
733 if (get_timer(0) - start
> MAX_RETRY_MS
) {
734 printf("%s: timedout waiting for status!\n",
738 } while (mmc_stat
== 0);
740 if ((mmc_stat
& (IE_DTO
| IE_DCRC
| IE_DEB
)) != 0)
741 mmc_reset_controller_fsm(mmc_base
, SYSCTL_SRD
);
743 if ((mmc_stat
& ERRI_MASK
) != 0)
746 if (mmc_stat
& BWR_MASK
) {
749 writel(readl(&mmc_base
->stat
) | BWR_MASK
,
751 for (k
= 0; k
< count
; k
++) {
752 writel(*input_buf
, &mmc_base
->data
);
758 if (mmc_stat
& BRR_MASK
)
759 writel(readl(&mmc_base
->stat
) | BRR_MASK
,
762 if (mmc_stat
& TC_MASK
) {
763 writel(readl(&mmc_base
->stat
) | TC_MASK
,
771 static void omap_hsmmc_stop_clock(struct hsmmc
*mmc_base
)
773 writel(readl(&mmc_base
->sysctl
) & ~CEN_ENABLE
, &mmc_base
->sysctl
);
776 static void omap_hsmmc_start_clock(struct hsmmc
*mmc_base
)
778 writel(readl(&mmc_base
->sysctl
) | CEN_ENABLE
, &mmc_base
->sysctl
);
781 static void omap_hsmmc_set_clock(struct mmc
*mmc
)
783 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
784 struct hsmmc
*mmc_base
;
785 unsigned int dsor
= 0;
788 mmc_base
= priv
->base_addr
;
789 omap_hsmmc_stop_clock(mmc_base
);
791 /* TODO: Is setting DTO required here? */
792 mmc_reg_out(&mmc_base
->sysctl
, (ICE_MASK
| DTO_MASK
),
793 (ICE_STOP
| DTO_15THDTO
));
795 if (mmc
->clock
!= 0) {
796 dsor
= DIV_ROUND_UP(MMC_CLOCK_REFERENCE
* 1000000, mmc
->clock
);
803 mmc_reg_out(&mmc_base
->sysctl
, ICE_MASK
| CLKD_MASK
,
804 (dsor
<< CLKD_OFFSET
) | ICE_OSCILLATE
);
806 start
= get_timer(0);
807 while ((readl(&mmc_base
->sysctl
) & ICS_MASK
) == ICS_NOTREADY
) {
808 if (get_timer(0) - start
> MAX_RETRY_MS
) {
809 printf("%s: timedout waiting for ics!\n", __func__
);
814 priv
->clock
= mmc
->clock
;
815 omap_hsmmc_start_clock(mmc_base
);
818 static void omap_hsmmc_set_bus_width(struct mmc
*mmc
)
820 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
821 struct hsmmc
*mmc_base
;
823 mmc_base
= priv
->base_addr
;
824 /* configue bus width */
825 switch (mmc
->bus_width
) {
827 writel(readl(&mmc_base
->con
) | DTW_8_BITMODE
,
832 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
834 writel(readl(&mmc_base
->hctl
) | DTW_4_BITMODE
,
840 writel(readl(&mmc_base
->con
) & ~DTW_8_BITMODE
,
842 writel(readl(&mmc_base
->hctl
) & ~DTW_4_BITMODE
,
847 priv
->bus_width
= mmc
->bus_width
;
850 #if !CONFIG_IS_ENABLED(DM_MMC)
851 static int omap_hsmmc_set_ios(struct mmc
*mmc
)
853 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
855 static int omap_hsmmc_set_ios(struct udevice
*dev
)
857 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
858 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
859 struct mmc
*mmc
= upriv
->mmc
;
862 if (priv
->bus_width
!= mmc
->bus_width
)
863 omap_hsmmc_set_bus_width(mmc
);
865 if (priv
->clock
!= mmc
->clock
)
866 omap_hsmmc_set_clock(mmc
);
871 #ifdef OMAP_HSMMC_USE_GPIO
872 #if CONFIG_IS_ENABLED(DM_MMC)
873 static int omap_hsmmc_getcd(struct udevice
*dev
)
875 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
878 value
= dm_gpio_get_value(&priv
->cd_gpio
);
879 /* if no CD return as 1 */
883 if (priv
->cd_inverted
)
888 static int omap_hsmmc_getwp(struct udevice
*dev
)
890 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
893 value
= dm_gpio_get_value(&priv
->wp_gpio
);
894 /* if no WP return as 0 */
900 static int omap_hsmmc_getcd(struct mmc
*mmc
)
902 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
905 /* if no CD return as 1 */
906 cd_gpio
= priv
->cd_gpio
;
910 /* NOTE: assumes card detect signal is active-low */
911 return !gpio_get_value(cd_gpio
);
914 static int omap_hsmmc_getwp(struct mmc
*mmc
)
916 struct omap_hsmmc_data
*priv
= omap_hsmmc_get_data(mmc
);
919 /* if no WP return as 0 */
920 wp_gpio
= priv
->wp_gpio
;
924 /* NOTE: assumes write protect signal is active-high */
925 return gpio_get_value(wp_gpio
);
930 #if CONFIG_IS_ENABLED(DM_MMC)
931 static const struct dm_mmc_ops omap_hsmmc_ops
= {
932 .send_cmd
= omap_hsmmc_send_cmd
,
933 .set_ios
= omap_hsmmc_set_ios
,
934 #ifdef OMAP_HSMMC_USE_GPIO
935 .get_cd
= omap_hsmmc_getcd
,
936 .get_wp
= omap_hsmmc_getwp
,
940 static const struct mmc_ops omap_hsmmc_ops
= {
941 .send_cmd
= omap_hsmmc_send_cmd
,
942 .set_ios
= omap_hsmmc_set_ios
,
943 .init
= omap_hsmmc_init_setup
,
944 #ifdef OMAP_HSMMC_USE_GPIO
945 .getcd
= omap_hsmmc_getcd
,
946 .getwp
= omap_hsmmc_getwp
,
951 #if !CONFIG_IS_ENABLED(DM_MMC)
952 int omap_mmc_init(int dev_index
, uint host_caps_mask
, uint f_max
, int cd_gpio
,
956 struct omap_hsmmc_data
*priv
;
957 struct mmc_config
*cfg
;
960 priv
= malloc(sizeof(*priv
));
964 host_caps_val
= MMC_MODE_4BIT
| MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
968 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
970 #ifdef OMAP_HSMMC2_BASE
972 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC2_BASE
;
973 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
974 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
975 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
976 defined(CONFIG_HSMMC2_8BIT)
977 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
978 host_caps_val
|= MMC_MODE_8BIT
;
982 #ifdef OMAP_HSMMC3_BASE
984 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC3_BASE
;
985 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
986 /* Enable 8-bit interface for eMMC on DRA7XX */
987 host_caps_val
|= MMC_MODE_8BIT
;
992 priv
->base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
;
995 #ifdef OMAP_HSMMC_USE_GPIO
996 /* on error gpio values are set to -1, which is what we want */
997 priv
->cd_gpio
= omap_mmc_setup_gpio_in(cd_gpio
, "mmc_cd");
998 priv
->wp_gpio
= omap_mmc_setup_gpio_in(wp_gpio
, "mmc_wp");
1003 cfg
->name
= "OMAP SD/MMC";
1004 cfg
->ops
= &omap_hsmmc_ops
;
1006 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
1007 cfg
->host_caps
= host_caps_val
& ~host_caps_mask
;
1009 cfg
->f_min
= 400000;
1014 if (cfg
->host_caps
& MMC_MODE_HS
) {
1015 if (cfg
->host_caps
& MMC_MODE_HS_52MHz
)
1016 cfg
->f_max
= 52000000;
1018 cfg
->f_max
= 26000000;
1020 cfg
->f_max
= 20000000;
1023 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
1025 #if defined(CONFIG_OMAP34XX)
1027 * Silicon revs 2.1 and older do not support multiblock transfers.
1029 if ((get_cpu_family() == CPU_OMAP34XX
) && (get_cpu_rev() <= CPU_3XX_ES21
))
1032 mmc
= mmc_create(cfg
, priv
);
1039 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1040 static int omap_hsmmc_ofdata_to_platdata(struct udevice
*dev
)
1042 struct omap_hsmmc_plat
*plat
= dev_get_platdata(dev
);
1043 struct mmc_config
*cfg
= &plat
->cfg
;
1044 const void *fdt
= gd
->fdt_blob
;
1045 int node
= dev_of_offset(dev
);
1048 plat
->base_addr
= map_physmem(devfdt_get_addr(dev
),
1049 sizeof(struct hsmmc
*),
1052 cfg
->host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
1053 val
= fdtdec_get_int(fdt
, node
, "bus-width", -1);
1055 printf("error: bus-width property missing\n");
1061 cfg
->host_caps
|= MMC_MODE_8BIT
;
1063 cfg
->host_caps
|= MMC_MODE_4BIT
;
1066 printf("error: invalid bus-width property\n");
1070 cfg
->f_min
= 400000;
1071 cfg
->f_max
= fdtdec_get_int(fdt
, node
, "max-frequency", 52000000);
1072 cfg
->voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
1073 cfg
->b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
1075 #ifdef OMAP_HSMMC_USE_GPIO
1076 plat
->cd_inverted
= fdtdec_get_bool(fdt
, node
, "cd-inverted");
1085 static int omap_hsmmc_bind(struct udevice
*dev
)
1087 struct omap_hsmmc_plat
*plat
= dev_get_platdata(dev
);
1089 return mmc_bind(dev
, &plat
->mmc
, &plat
->cfg
);
1092 static int omap_hsmmc_probe(struct udevice
*dev
)
1094 struct omap_hsmmc_plat
*plat
= dev_get_platdata(dev
);
1095 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
1096 struct omap_hsmmc_data
*priv
= dev_get_priv(dev
);
1097 struct mmc_config
*cfg
= &plat
->cfg
;
1100 cfg
->name
= "OMAP SD/MMC";
1101 priv
->base_addr
= plat
->base_addr
;
1102 #ifdef OMAP_HSMMC_USE_GPIO
1103 priv
->cd_inverted
= plat
->cd_inverted
;
1109 mmc
= mmc_create(cfg
, priv
);
1114 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1115 gpio_request_by_name(dev
, "cd-gpios", 0, &priv
->cd_gpio
, GPIOD_IS_IN
);
1116 gpio_request_by_name(dev
, "wp-gpios", 0, &priv
->wp_gpio
, GPIOD_IS_IN
);
1122 return omap_hsmmc_init_setup(mmc
);
1125 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1126 static const struct udevice_id omap_hsmmc_ids
[] = {
1127 { .compatible
= "ti,omap3-hsmmc" },
1128 { .compatible
= "ti,omap4-hsmmc" },
1129 { .compatible
= "ti,am33xx-hsmmc" },
1134 U_BOOT_DRIVER(omap_hsmmc
) = {
1135 .name
= "omap_hsmmc",
1137 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1138 .of_match
= omap_hsmmc_ids
,
1139 .ofdata_to_platdata
= omap_hsmmc_ofdata_to_platdata
,
1140 .platdata_auto_alloc_size
= sizeof(struct omap_hsmmc_plat
),
1143 .bind
= omap_hsmmc_bind
,
1145 .ops
= &omap_hsmmc_ops
,
1146 .probe
= omap_hsmmc_probe
,
1147 .priv_auto_alloc_size
= sizeof(struct omap_hsmmc_data
),
1148 .flags
= DM_FLAG_PRE_RELOC
,