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Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash
[people/ms/u-boot.git] / drivers / mtd / nand / nand_base.c
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <common.h>
36
37 #define ENOTSUPP 524 /* Operation is not supported */
38
39 #include <malloc.h>
40 #include <watchdog.h>
41 #include <linux/err.h>
42 #include <linux/mtd/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/nand_bch.h>
47
48 #ifdef CONFIG_MTD_PARTITIONS
49 #include <linux/mtd/partitions.h>
50 #endif
51
52 #include <asm/io.h>
53 #include <asm/errno.h>
54
55 /*
56 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
57 * a flash. NAND flash is initialized prior to interrupts so standard timers
58 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
59 * which is greater than (max NAND reset time / NAND status read time).
60 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
61 */
62 #ifndef CONFIG_SYS_NAND_RESET_CNT
63 #define CONFIG_SYS_NAND_RESET_CNT 200000
64 #endif
65
66 /* Define default oob placement schemes for large and small page devices */
67 static struct nand_ecclayout nand_oob_8 = {
68 .eccbytes = 3,
69 .eccpos = {0, 1, 2},
70 .oobfree = {
71 {.offset = 3,
72 .length = 2},
73 {.offset = 6,
74 .length = 2} }
75 };
76
77 static struct nand_ecclayout nand_oob_16 = {
78 .eccbytes = 6,
79 .eccpos = {0, 1, 2, 3, 6, 7},
80 .oobfree = {
81 {.offset = 8,
82 . length = 8} }
83 };
84
85 static struct nand_ecclayout nand_oob_64 = {
86 .eccbytes = 24,
87 .eccpos = {
88 40, 41, 42, 43, 44, 45, 46, 47,
89 48, 49, 50, 51, 52, 53, 54, 55,
90 56, 57, 58, 59, 60, 61, 62, 63},
91 .oobfree = {
92 {.offset = 2,
93 .length = 38} }
94 };
95
96 static struct nand_ecclayout nand_oob_128 = {
97 .eccbytes = 48,
98 .eccpos = {
99 80, 81, 82, 83, 84, 85, 86, 87,
100 88, 89, 90, 91, 92, 93, 94, 95,
101 96, 97, 98, 99, 100, 101, 102, 103,
102 104, 105, 106, 107, 108, 109, 110, 111,
103 112, 113, 114, 115, 116, 117, 118, 119,
104 120, 121, 122, 123, 124, 125, 126, 127},
105 .oobfree = {
106 {.offset = 2,
107 .length = 78} }
108 };
109
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
111 int new_state);
112
113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
115
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
117
118 static int check_offs_len(struct mtd_info *mtd,
119 loff_t ofs, uint64_t len)
120 {
121 struct nand_chip *chip = mtd->priv;
122 int ret = 0;
123
124 /* Start address must align on block boundary */
125 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
126 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
127 ret = -EINVAL;
128 }
129
130 /* Length must align on block boundary */
131 if (len & ((1 << chip->phys_erase_shift) - 1)) {
132 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
133 __func__);
134 ret = -EINVAL;
135 }
136
137 /* Do not allow past end of device */
138 if (ofs + len > mtd->size) {
139 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
140 __func__);
141 ret = -EINVAL;
142 }
143
144 return ret;
145 }
146
147 /**
148 * nand_release_device - [GENERIC] release chip
149 * @mtd: MTD device structure
150 *
151 * Deselect, release chip lock and wake up anyone waiting on the device
152 */
153 static void nand_release_device(struct mtd_info *mtd)
154 {
155 struct nand_chip *chip = mtd->priv;
156
157 /* De-select the NAND device */
158 chip->select_chip(mtd, -1);
159 }
160
161 /**
162 * nand_read_byte - [DEFAULT] read one byte from the chip
163 * @mtd: MTD device structure
164 *
165 * Default read function for 8bit buswith
166 */
167 uint8_t nand_read_byte(struct mtd_info *mtd)
168 {
169 struct nand_chip *chip = mtd->priv;
170 return readb(chip->IO_ADDR_R);
171 }
172
173 /**
174 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
175 * @mtd: MTD device structure
176 *
177 * Default read function for 16bit buswith with
178 * endianess conversion
179 */
180 static uint8_t nand_read_byte16(struct mtd_info *mtd)
181 {
182 struct nand_chip *chip = mtd->priv;
183 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
184 }
185
186 /**
187 * nand_read_word - [DEFAULT] read one word from the chip
188 * @mtd: MTD device structure
189 *
190 * Default read function for 16bit buswith without
191 * endianess conversion
192 */
193 static u16 nand_read_word(struct mtd_info *mtd)
194 {
195 struct nand_chip *chip = mtd->priv;
196 return readw(chip->IO_ADDR_R);
197 }
198
199 /**
200 * nand_select_chip - [DEFAULT] control CE line
201 * @mtd: MTD device structure
202 * @chipnr: chipnumber to select, -1 for deselect
203 *
204 * Default select function for 1 chip devices.
205 */
206 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
207 {
208 struct nand_chip *chip = mtd->priv;
209
210 switch (chipnr) {
211 case -1:
212 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
213 break;
214 case 0:
215 break;
216
217 default:
218 BUG();
219 }
220 }
221
222 /**
223 * nand_write_buf - [DEFAULT] write buffer to chip
224 * @mtd: MTD device structure
225 * @buf: data buffer
226 * @len: number of bytes to write
227 *
228 * Default write function for 8bit buswith
229 */
230 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
231 {
232 int i;
233 struct nand_chip *chip = mtd->priv;
234
235 for (i = 0; i < len; i++)
236 writeb(buf[i], chip->IO_ADDR_W);
237 }
238
239 /**
240 * nand_read_buf - [DEFAULT] read chip data into buffer
241 * @mtd: MTD device structure
242 * @buf: buffer to store date
243 * @len: number of bytes to read
244 *
245 * Default read function for 8bit buswith
246 */
247 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
248 {
249 int i;
250 struct nand_chip *chip = mtd->priv;
251
252 for (i = 0; i < len; i++)
253 buf[i] = readb(chip->IO_ADDR_R);
254 }
255
256 /**
257 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
258 * @mtd: MTD device structure
259 * @buf: buffer containing the data to compare
260 * @len: number of bytes to compare
261 *
262 * Default verify function for 8bit buswith
263 */
264 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
265 {
266 int i;
267 struct nand_chip *chip = mtd->priv;
268
269 for (i = 0; i < len; i++)
270 if (buf[i] != readb(chip->IO_ADDR_R))
271 return -EFAULT;
272 return 0;
273 }
274
275 /**
276 * nand_write_buf16 - [DEFAULT] write buffer to chip
277 * @mtd: MTD device structure
278 * @buf: data buffer
279 * @len: number of bytes to write
280 *
281 * Default write function for 16bit buswith
282 */
283 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
284 {
285 int i;
286 struct nand_chip *chip = mtd->priv;
287 u16 *p = (u16 *) buf;
288 len >>= 1;
289
290 for (i = 0; i < len; i++)
291 writew(p[i], chip->IO_ADDR_W);
292
293 }
294
295 /**
296 * nand_read_buf16 - [DEFAULT] read chip data into buffer
297 * @mtd: MTD device structure
298 * @buf: buffer to store date
299 * @len: number of bytes to read
300 *
301 * Default read function for 16bit buswith
302 */
303 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
304 {
305 int i;
306 struct nand_chip *chip = mtd->priv;
307 u16 *p = (u16 *) buf;
308 len >>= 1;
309
310 for (i = 0; i < len; i++)
311 p[i] = readw(chip->IO_ADDR_R);
312 }
313
314 /**
315 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
316 * @mtd: MTD device structure
317 * @buf: buffer containing the data to compare
318 * @len: number of bytes to compare
319 *
320 * Default verify function for 16bit buswith
321 */
322 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
323 {
324 int i;
325 struct nand_chip *chip = mtd->priv;
326 u16 *p = (u16 *) buf;
327 len >>= 1;
328
329 for (i = 0; i < len; i++)
330 if (p[i] != readw(chip->IO_ADDR_R))
331 return -EFAULT;
332
333 return 0;
334 }
335
336 /**
337 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
338 * @mtd: MTD device structure
339 * @ofs: offset from device start
340 * @getchip: 0, if the chip is already selected
341 *
342 * Check, if the block is bad.
343 */
344 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
345 {
346 int page, chipnr, res = 0;
347 struct nand_chip *chip = mtd->priv;
348 u16 bad;
349
350 if (chip->options & NAND_BBT_SCANLASTPAGE)
351 ofs += mtd->erasesize - mtd->writesize;
352
353 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
354
355 if (getchip) {
356 chipnr = (int)(ofs >> chip->chip_shift);
357
358 nand_get_device(chip, mtd, FL_READING);
359
360 /* Select the NAND device */
361 chip->select_chip(mtd, chipnr);
362 }
363
364 if (chip->options & NAND_BUSWIDTH_16) {
365 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
366 page);
367 bad = cpu_to_le16(chip->read_word(mtd));
368 if (chip->badblockpos & 0x1)
369 bad >>= 8;
370 else
371 bad &= 0xFF;
372 } else {
373 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
374 bad = chip->read_byte(mtd);
375 }
376
377 if (likely(chip->badblockbits == 8))
378 res = bad != 0xFF;
379 else
380 res = hweight8(bad) < chip->badblockbits;
381
382 if (getchip)
383 nand_release_device(mtd);
384
385 return res;
386 }
387
388 /**
389 * nand_default_block_markbad - [DEFAULT] mark a block bad
390 * @mtd: MTD device structure
391 * @ofs: offset from device start
392 *
393 * This is the default implementation, which can be overridden by
394 * a hardware specific driver.
395 */
396 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
397 {
398 struct nand_chip *chip = mtd->priv;
399 uint8_t buf[2] = { 0, 0 };
400 int block, ret, i = 0;
401
402 if (chip->options & NAND_BBT_SCANLASTPAGE)
403 ofs += mtd->erasesize - mtd->writesize;
404
405 /* Get block number */
406 block = (int)(ofs >> chip->bbt_erase_shift);
407 if (chip->bbt)
408 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
409
410 /* Do we have a flash based bad block table ? */
411 if (chip->options & NAND_USE_FLASH_BBT)
412 ret = nand_update_bbt(mtd, ofs);
413 else {
414 nand_get_device(chip, mtd, FL_WRITING);
415
416 /* Write to first two pages and to byte 1 and 6 if necessary.
417 * If we write to more than one location, the first error
418 * encountered quits the procedure. We write two bytes per
419 * location, so we dont have to mess with 16 bit access.
420 */
421 do {
422 chip->ops.len = chip->ops.ooblen = 2;
423 chip->ops.datbuf = NULL;
424 chip->ops.oobbuf = buf;
425 chip->ops.ooboffs = chip->badblockpos & ~0x01;
426
427 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
428
429 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
430 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
431 & ~0x01;
432 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
433 }
434 i++;
435 ofs += mtd->writesize;
436 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
437 i < 2);
438
439 nand_release_device(mtd);
440 }
441 if (!ret)
442 mtd->ecc_stats.badblocks++;
443
444 return ret;
445 }
446
447 /**
448 * nand_check_wp - [GENERIC] check if the chip is write protected
449 * @mtd: MTD device structure
450 * Check, if the device is write protected
451 *
452 * The function expects, that the device is already selected
453 */
454 static int nand_check_wp(struct mtd_info *mtd)
455 {
456 struct nand_chip *chip = mtd->priv;
457
458 /* broken xD cards report WP despite being writable */
459 if (chip->options & NAND_BROKEN_XD)
460 return 0;
461
462 /* Check the WP bit */
463 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
464 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
465 }
466
467 /**
468 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
469 * @mtd: MTD device structure
470 * @ofs: offset from device start
471 * @getchip: 0, if the chip is already selected
472 * @allowbbt: 1, if its allowed to access the bbt area
473 *
474 * Check, if the block is bad. Either by reading the bad block table or
475 * calling of the scan function.
476 */
477 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
478 int allowbbt)
479 {
480 struct nand_chip *chip = mtd->priv;
481
482 if (!chip->bbt)
483 return chip->block_bad(mtd, ofs, getchip);
484
485 /* Return info from the table */
486 return nand_isbad_bbt(mtd, ofs, allowbbt);
487 }
488
489 /*
490 * Wait for the ready pin, after a command
491 * The timeout is catched later.
492 */
493 void nand_wait_ready(struct mtd_info *mtd)
494 {
495 struct nand_chip *chip = mtd->priv;
496 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
497 u32 time_start;
498
499 time_start = get_timer(0);
500
501 /* wait until command is processed or timeout occures */
502 while (get_timer(time_start) < timeo) {
503 if (chip->dev_ready)
504 if (chip->dev_ready(mtd))
505 break;
506 }
507 }
508
509 /**
510 * nand_command - [DEFAULT] Send command to NAND device
511 * @mtd: MTD device structure
512 * @command: the command to be sent
513 * @column: the column address for this command, -1 if none
514 * @page_addr: the page address for this command, -1 if none
515 *
516 * Send command to NAND device. This function is used for small page
517 * devices (256/512 Bytes per page)
518 */
519 static void nand_command(struct mtd_info *mtd, unsigned int command,
520 int column, int page_addr)
521 {
522 register struct nand_chip *chip = mtd->priv;
523 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
524 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
525
526 /*
527 * Write out the command to the device.
528 */
529 if (command == NAND_CMD_SEQIN) {
530 int readcmd;
531
532 if (column >= mtd->writesize) {
533 /* OOB area */
534 column -= mtd->writesize;
535 readcmd = NAND_CMD_READOOB;
536 } else if (column < 256) {
537 /* First 256 bytes --> READ0 */
538 readcmd = NAND_CMD_READ0;
539 } else {
540 column -= 256;
541 readcmd = NAND_CMD_READ1;
542 }
543 chip->cmd_ctrl(mtd, readcmd, ctrl);
544 ctrl &= ~NAND_CTRL_CHANGE;
545 }
546 chip->cmd_ctrl(mtd, command, ctrl);
547
548 /*
549 * Address cycle, when necessary
550 */
551 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
552 /* Serially input address */
553 if (column != -1) {
554 /* Adjust columns for 16 bit buswidth */
555 if (chip->options & NAND_BUSWIDTH_16)
556 column >>= 1;
557 chip->cmd_ctrl(mtd, column, ctrl);
558 ctrl &= ~NAND_CTRL_CHANGE;
559 }
560 if (page_addr != -1) {
561 chip->cmd_ctrl(mtd, page_addr, ctrl);
562 ctrl &= ~NAND_CTRL_CHANGE;
563 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
564 /* One more address cycle for devices > 32MiB */
565 if (chip->chipsize > (32 << 20))
566 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
567 }
568 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
569
570 /*
571 * program and erase have their own busy handlers
572 * status and sequential in needs no delay
573 */
574 switch (command) {
575
576 case NAND_CMD_PAGEPROG:
577 case NAND_CMD_ERASE1:
578 case NAND_CMD_ERASE2:
579 case NAND_CMD_SEQIN:
580 case NAND_CMD_STATUS:
581 return;
582
583 case NAND_CMD_RESET:
584 if (chip->dev_ready)
585 break;
586 udelay(chip->chip_delay);
587 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
588 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
589 chip->cmd_ctrl(mtd,
590 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
591 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
592 (rst_sts_cnt--));
593 return;
594
595 /* This applies to read commands */
596 default:
597 /*
598 * If we don't have access to the busy pin, we apply the given
599 * command delay
600 */
601 if (!chip->dev_ready) {
602 udelay(chip->chip_delay);
603 return;
604 }
605 }
606 /* Apply this short delay always to ensure that we do wait tWB in
607 * any case on any machine. */
608 ndelay(100);
609
610 nand_wait_ready(mtd);
611 }
612
613 /**
614 * nand_command_lp - [DEFAULT] Send command to NAND large page device
615 * @mtd: MTD device structure
616 * @command: the command to be sent
617 * @column: the column address for this command, -1 if none
618 * @page_addr: the page address for this command, -1 if none
619 *
620 * Send command to NAND device. This is the version for the new large page
621 * devices We dont have the separate regions as we have in the small page
622 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
623 */
624 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
625 int column, int page_addr)
626 {
627 register struct nand_chip *chip = mtd->priv;
628 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
629
630 /* Emulate NAND_CMD_READOOB */
631 if (command == NAND_CMD_READOOB) {
632 column += mtd->writesize;
633 command = NAND_CMD_READ0;
634 }
635
636 /* Command latch cycle */
637 chip->cmd_ctrl(mtd, command & 0xff,
638 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
639
640 if (column != -1 || page_addr != -1) {
641 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
642
643 /* Serially input address */
644 if (column != -1) {
645 /* Adjust columns for 16 bit buswidth */
646 if (chip->options & NAND_BUSWIDTH_16)
647 column >>= 1;
648 chip->cmd_ctrl(mtd, column, ctrl);
649 ctrl &= ~NAND_CTRL_CHANGE;
650 chip->cmd_ctrl(mtd, column >> 8, ctrl);
651 }
652 if (page_addr != -1) {
653 chip->cmd_ctrl(mtd, page_addr, ctrl);
654 chip->cmd_ctrl(mtd, page_addr >> 8,
655 NAND_NCE | NAND_ALE);
656 /* One more address cycle for devices > 128MiB */
657 if (chip->chipsize > (128 << 20))
658 chip->cmd_ctrl(mtd, page_addr >> 16,
659 NAND_NCE | NAND_ALE);
660 }
661 }
662 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
663
664 /*
665 * program and erase have their own busy handlers
666 * status, sequential in, and deplete1 need no delay
667 */
668 switch (command) {
669
670 case NAND_CMD_CACHEDPROG:
671 case NAND_CMD_PAGEPROG:
672 case NAND_CMD_ERASE1:
673 case NAND_CMD_ERASE2:
674 case NAND_CMD_SEQIN:
675 case NAND_CMD_RNDIN:
676 case NAND_CMD_STATUS:
677 case NAND_CMD_DEPLETE1:
678 return;
679
680 /*
681 * read error status commands require only a short delay
682 */
683 case NAND_CMD_STATUS_ERROR:
684 case NAND_CMD_STATUS_ERROR0:
685 case NAND_CMD_STATUS_ERROR1:
686 case NAND_CMD_STATUS_ERROR2:
687 case NAND_CMD_STATUS_ERROR3:
688 udelay(chip->chip_delay);
689 return;
690
691 case NAND_CMD_RESET:
692 if (chip->dev_ready)
693 break;
694 udelay(chip->chip_delay);
695 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
696 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
697 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
698 NAND_NCE | NAND_CTRL_CHANGE);
699 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
700 (rst_sts_cnt--));
701 return;
702
703 case NAND_CMD_RNDOUT:
704 /* No ready / busy check necessary */
705 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
706 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
707 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
708 NAND_NCE | NAND_CTRL_CHANGE);
709 return;
710
711 case NAND_CMD_READ0:
712 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
713 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
714 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
715 NAND_NCE | NAND_CTRL_CHANGE);
716
717 /* This applies to read commands */
718 default:
719 /*
720 * If we don't have access to the busy pin, we apply the given
721 * command delay
722 */
723 if (!chip->dev_ready) {
724 udelay(chip->chip_delay);
725 return;
726 }
727 }
728
729 /* Apply this short delay always to ensure that we do wait tWB in
730 * any case on any machine. */
731 ndelay(100);
732
733 nand_wait_ready(mtd);
734 }
735
736 /**
737 * nand_get_device - [GENERIC] Get chip for selected access
738 * @chip: the nand chip descriptor
739 * @mtd: MTD device structure
740 * @new_state: the state which is requested
741 *
742 * Get the device and lock it for exclusive access
743 */
744 static int
745 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
746 {
747 chip->state = new_state;
748 return 0;
749 }
750
751 /**
752 * nand_wait - [DEFAULT] wait until the command is done
753 * @mtd: MTD device structure
754 * @chip: NAND chip structure
755 *
756 * Wait for command done. This applies to erase and program only
757 * Erase can take up to 400ms and program up to 20ms according to
758 * general NAND and SmartMedia specs
759 */
760 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
761 {
762 unsigned long timeo;
763 int state = chip->state;
764 u32 time_start;
765
766 if (state == FL_ERASING)
767 timeo = (CONFIG_SYS_HZ * 400) / 1000;
768 else
769 timeo = (CONFIG_SYS_HZ * 20) / 1000;
770
771 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
772 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
773 else
774 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
775
776 time_start = get_timer(0);
777
778 while (1) {
779 if (get_timer(time_start) > timeo) {
780 printf("Timeout!");
781 return 0x01;
782 }
783
784 if (chip->dev_ready) {
785 if (chip->dev_ready(mtd))
786 break;
787 } else {
788 if (chip->read_byte(mtd) & NAND_STATUS_READY)
789 break;
790 }
791 }
792 #ifdef PPCHAMELON_NAND_TIMER_HACK
793 time_start = get_timer(0);
794 while (get_timer(time_start) < 10)
795 ;
796 #endif /* PPCHAMELON_NAND_TIMER_HACK */
797
798 return (int)chip->read_byte(mtd);
799 }
800
801 /**
802 * nand_read_page_raw - [Intern] read raw page data without ecc
803 * @mtd: mtd info structure
804 * @chip: nand chip info structure
805 * @buf: buffer to store read data
806 * @page: page number to read
807 *
808 * Not for syndrome calculating ecc controllers, which use a special oob layout
809 */
810 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
811 uint8_t *buf, int page)
812 {
813 chip->read_buf(mtd, buf, mtd->writesize);
814 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
815 return 0;
816 }
817
818 /**
819 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
820 * @mtd: mtd info structure
821 * @chip: nand chip info structure
822 * @buf: buffer to store read data
823 * @page: page number to read
824 *
825 * We need a special oob layout and handling even when OOB isn't used.
826 */
827 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
828 struct nand_chip *chip,
829 uint8_t *buf, int page)
830 {
831 int eccsize = chip->ecc.size;
832 int eccbytes = chip->ecc.bytes;
833 uint8_t *oob = chip->oob_poi;
834 int steps, size;
835
836 for (steps = chip->ecc.steps; steps > 0; steps--) {
837 chip->read_buf(mtd, buf, eccsize);
838 buf += eccsize;
839
840 if (chip->ecc.prepad) {
841 chip->read_buf(mtd, oob, chip->ecc.prepad);
842 oob += chip->ecc.prepad;
843 }
844
845 chip->read_buf(mtd, oob, eccbytes);
846 oob += eccbytes;
847
848 if (chip->ecc.postpad) {
849 chip->read_buf(mtd, oob, chip->ecc.postpad);
850 oob += chip->ecc.postpad;
851 }
852 }
853
854 size = mtd->oobsize - (oob - chip->oob_poi);
855 if (size)
856 chip->read_buf(mtd, oob, size);
857
858 return 0;
859 }
860
861 /**
862 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
863 * @mtd: mtd info structure
864 * @chip: nand chip info structure
865 * @buf: buffer to store read data
866 * @page: page number to read
867 */
868 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
869 uint8_t *buf, int page)
870 {
871 int i, eccsize = chip->ecc.size;
872 int eccbytes = chip->ecc.bytes;
873 int eccsteps = chip->ecc.steps;
874 uint8_t *p = buf;
875 uint8_t *ecc_calc = chip->buffers->ecccalc;
876 uint8_t *ecc_code = chip->buffers->ecccode;
877 uint32_t *eccpos = chip->ecc.layout->eccpos;
878
879 chip->ecc.read_page_raw(mtd, chip, buf, page);
880
881 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
882 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
883
884 for (i = 0; i < chip->ecc.total; i++)
885 ecc_code[i] = chip->oob_poi[eccpos[i]];
886
887 eccsteps = chip->ecc.steps;
888 p = buf;
889
890 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
891 int stat;
892
893 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
894 if (stat < 0)
895 mtd->ecc_stats.failed++;
896 else
897 mtd->ecc_stats.corrected += stat;
898 }
899 return 0;
900 }
901
902 /**
903 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
904 * @mtd: mtd info structure
905 * @chip: nand chip info structure
906 * @data_offs: offset of requested data within the page
907 * @readlen: data length
908 * @bufpoi: buffer to store read data
909 */
910 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
911 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
912 {
913 int start_step, end_step, num_steps;
914 uint32_t *eccpos = chip->ecc.layout->eccpos;
915 uint8_t *p;
916 int data_col_addr, i, gaps = 0;
917 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
918 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
919 int index = 0;
920
921 /* Column address wihin the page aligned to ECC size (256bytes). */
922 start_step = data_offs / chip->ecc.size;
923 end_step = (data_offs + readlen - 1) / chip->ecc.size;
924 num_steps = end_step - start_step + 1;
925
926 /* Data size aligned to ECC ecc.size*/
927 datafrag_len = num_steps * chip->ecc.size;
928 eccfrag_len = num_steps * chip->ecc.bytes;
929
930 data_col_addr = start_step * chip->ecc.size;
931 /* If we read not a page aligned data */
932 if (data_col_addr != 0)
933 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
934
935 p = bufpoi + data_col_addr;
936 chip->read_buf(mtd, p, datafrag_len);
937
938 /* Calculate ECC */
939 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
940 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
941
942 /* The performance is faster if to position offsets
943 according to ecc.pos. Let make sure here that
944 there are no gaps in ecc positions */
945 for (i = 0; i < eccfrag_len - 1; i++) {
946 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
947 eccpos[i + start_step * chip->ecc.bytes + 1]) {
948 gaps = 1;
949 break;
950 }
951 }
952 if (gaps) {
953 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
954 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
955 } else {
956 /* send the command to read the particular ecc bytes */
957 /* take care about buswidth alignment in read_buf */
958 index = start_step * chip->ecc.bytes;
959
960 aligned_pos = eccpos[index] & ~(busw - 1);
961 aligned_len = eccfrag_len;
962 if (eccpos[index] & (busw - 1))
963 aligned_len++;
964 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
965 aligned_len++;
966
967 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
968 mtd->writesize + aligned_pos, -1);
969 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
970 }
971
972 for (i = 0; i < eccfrag_len; i++)
973 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
974
975 p = bufpoi + data_col_addr;
976 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
977 int stat;
978
979 stat = chip->ecc.correct(mtd, p,
980 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
981 if (stat < 0)
982 mtd->ecc_stats.failed++;
983 else
984 mtd->ecc_stats.corrected += stat;
985 }
986 return 0;
987 }
988
989 /**
990 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
991 * @mtd: mtd info structure
992 * @chip: nand chip info structure
993 * @buf: buffer to store read data
994 * @page: page number to read
995 *
996 * Not for syndrome calculating ecc controllers which need a special oob layout
997 */
998 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
999 uint8_t *buf, int page)
1000 {
1001 int i, eccsize = chip->ecc.size;
1002 int eccbytes = chip->ecc.bytes;
1003 int eccsteps = chip->ecc.steps;
1004 uint8_t *p = buf;
1005 uint8_t *ecc_calc = chip->buffers->ecccalc;
1006 uint8_t *ecc_code = chip->buffers->ecccode;
1007 uint32_t *eccpos = chip->ecc.layout->eccpos;
1008
1009 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1010 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1011 chip->read_buf(mtd, p, eccsize);
1012 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1013 }
1014 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1015
1016 for (i = 0; i < chip->ecc.total; i++)
1017 ecc_code[i] = chip->oob_poi[eccpos[i]];
1018
1019 eccsteps = chip->ecc.steps;
1020 p = buf;
1021
1022 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1023 int stat;
1024
1025 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1026 if (stat < 0)
1027 mtd->ecc_stats.failed++;
1028 else
1029 mtd->ecc_stats.corrected += stat;
1030 }
1031 return 0;
1032 }
1033
1034 /**
1035 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1036 * @mtd: mtd info structure
1037 * @chip: nand chip info structure
1038 * @buf: buffer to store read data
1039 * @page: page number to read
1040 *
1041 * Hardware ECC for large page chips, require OOB to be read first.
1042 * For this ECC mode, the write_page method is re-used from ECC_HW.
1043 * These methods read/write ECC from the OOB area, unlike the
1044 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1045 * "infix ECC" scheme and reads/writes ECC from the data area, by
1046 * overwriting the NAND manufacturer bad block markings.
1047 */
1048 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1049 struct nand_chip *chip, uint8_t *buf, int page)
1050 {
1051 int i, eccsize = chip->ecc.size;
1052 int eccbytes = chip->ecc.bytes;
1053 int eccsteps = chip->ecc.steps;
1054 uint8_t *p = buf;
1055 uint8_t *ecc_code = chip->buffers->ecccode;
1056 uint32_t *eccpos = chip->ecc.layout->eccpos;
1057 uint8_t *ecc_calc = chip->buffers->ecccalc;
1058
1059 /* Read the OOB area first */
1060 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1061 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1062 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1063
1064 for (i = 0; i < chip->ecc.total; i++)
1065 ecc_code[i] = chip->oob_poi[eccpos[i]];
1066
1067 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1068 int stat;
1069
1070 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1071 chip->read_buf(mtd, p, eccsize);
1072 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1073
1074 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1075 if (stat < 0)
1076 mtd->ecc_stats.failed++;
1077 else
1078 mtd->ecc_stats.corrected += stat;
1079 }
1080 return 0;
1081 }
1082
1083 /**
1084 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1085 * @mtd: mtd info structure
1086 * @chip: nand chip info structure
1087 * @buf: buffer to store read data
1088 * @page: page number to read
1089 *
1090 * The hw generator calculates the error syndrome automatically. Therefor
1091 * we need a special oob layout and handling.
1092 */
1093 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1094 uint8_t *buf, int page)
1095 {
1096 int i, eccsize = chip->ecc.size;
1097 int eccbytes = chip->ecc.bytes;
1098 int eccsteps = chip->ecc.steps;
1099 uint8_t *p = buf;
1100 uint8_t *oob = chip->oob_poi;
1101
1102 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1103 int stat;
1104
1105 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1106 chip->read_buf(mtd, p, eccsize);
1107
1108 if (chip->ecc.prepad) {
1109 chip->read_buf(mtd, oob, chip->ecc.prepad);
1110 oob += chip->ecc.prepad;
1111 }
1112
1113 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1114 chip->read_buf(mtd, oob, eccbytes);
1115 stat = chip->ecc.correct(mtd, p, oob, NULL);
1116
1117 if (stat < 0)
1118 mtd->ecc_stats.failed++;
1119 else
1120 mtd->ecc_stats.corrected += stat;
1121
1122 oob += eccbytes;
1123
1124 if (chip->ecc.postpad) {
1125 chip->read_buf(mtd, oob, chip->ecc.postpad);
1126 oob += chip->ecc.postpad;
1127 }
1128 }
1129
1130 /* Calculate remaining oob bytes */
1131 i = mtd->oobsize - (oob - chip->oob_poi);
1132 if (i)
1133 chip->read_buf(mtd, oob, i);
1134
1135 return 0;
1136 }
1137
1138 /**
1139 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1140 * @chip: nand chip structure
1141 * @oob: oob destination address
1142 * @ops: oob ops structure
1143 * @len: size of oob to transfer
1144 */
1145 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1146 struct mtd_oob_ops *ops, size_t len)
1147 {
1148 switch (ops->mode) {
1149
1150 case MTD_OOB_PLACE:
1151 case MTD_OOB_RAW:
1152 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1153 return oob + len;
1154
1155 case MTD_OOB_AUTO: {
1156 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1157 uint32_t boffs = 0, roffs = ops->ooboffs;
1158 size_t bytes = 0;
1159
1160 for (; free->length && len; free++, len -= bytes) {
1161 /* Read request not from offset 0 ? */
1162 if (unlikely(roffs)) {
1163 if (roffs >= free->length) {
1164 roffs -= free->length;
1165 continue;
1166 }
1167 boffs = free->offset + roffs;
1168 bytes = min_t(size_t, len,
1169 (free->length - roffs));
1170 roffs = 0;
1171 } else {
1172 bytes = min_t(size_t, len, free->length);
1173 boffs = free->offset;
1174 }
1175 memcpy(oob, chip->oob_poi + boffs, bytes);
1176 oob += bytes;
1177 }
1178 return oob;
1179 }
1180 default:
1181 BUG();
1182 }
1183 return NULL;
1184 }
1185
1186 /**
1187 * nand_do_read_ops - [Internal] Read data with ECC
1188 *
1189 * @mtd: MTD device structure
1190 * @from: offset to read from
1191 * @ops: oob ops structure
1192 *
1193 * Internal function. Called with chip held.
1194 */
1195 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1196 struct mtd_oob_ops *ops)
1197 {
1198 int chipnr, page, realpage, col, bytes, aligned;
1199 struct nand_chip *chip = mtd->priv;
1200 struct mtd_ecc_stats stats;
1201 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1202 int sndcmd = 1;
1203 int ret = 0;
1204 uint32_t readlen = ops->len;
1205 uint32_t oobreadlen = ops->ooblen;
1206 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1207 mtd->oobavail : mtd->oobsize;
1208
1209 uint8_t *bufpoi, *oob, *buf;
1210
1211 stats = mtd->ecc_stats;
1212
1213 chipnr = (int)(from >> chip->chip_shift);
1214 chip->select_chip(mtd, chipnr);
1215
1216 realpage = (int)(from >> chip->page_shift);
1217 page = realpage & chip->pagemask;
1218
1219 col = (int)(from & (mtd->writesize - 1));
1220
1221 buf = ops->datbuf;
1222 oob = ops->oobbuf;
1223
1224 while (1) {
1225 WATCHDOG_RESET();
1226
1227 bytes = min(mtd->writesize - col, readlen);
1228 aligned = (bytes == mtd->writesize);
1229
1230 /* Is the current page in the buffer ? */
1231 if (realpage != chip->pagebuf || oob) {
1232 bufpoi = aligned ? buf : chip->buffers->databuf;
1233
1234 if (likely(sndcmd)) {
1235 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1236 sndcmd = 0;
1237 }
1238
1239 /* Now read the page into the buffer */
1240 if (unlikely(ops->mode == MTD_OOB_RAW))
1241 ret = chip->ecc.read_page_raw(mtd, chip,
1242 bufpoi, page);
1243 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1244 ret = chip->ecc.read_subpage(mtd, chip,
1245 col, bytes, bufpoi);
1246 else
1247 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1248 page);
1249 if (ret < 0)
1250 break;
1251
1252 /* Transfer not aligned data */
1253 if (!aligned) {
1254 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1255 !(mtd->ecc_stats.failed - stats.failed))
1256 chip->pagebuf = realpage;
1257 memcpy(buf, chip->buffers->databuf + col, bytes);
1258 }
1259
1260 buf += bytes;
1261
1262 if (unlikely(oob)) {
1263
1264 int toread = min(oobreadlen, max_oobsize);
1265
1266 if (toread) {
1267 oob = nand_transfer_oob(chip,
1268 oob, ops, toread);
1269 oobreadlen -= toread;
1270 }
1271 }
1272
1273 if (!(chip->options & NAND_NO_READRDY)) {
1274 /*
1275 * Apply delay or wait for ready/busy pin. Do
1276 * this before the AUTOINCR check, so no
1277 * problems arise if a chip which does auto
1278 * increment is marked as NOAUTOINCR by the
1279 * board driver.
1280 */
1281 if (!chip->dev_ready)
1282 udelay(chip->chip_delay);
1283 else
1284 nand_wait_ready(mtd);
1285 }
1286 } else {
1287 memcpy(buf, chip->buffers->databuf + col, bytes);
1288 buf += bytes;
1289 }
1290
1291 readlen -= bytes;
1292
1293 if (!readlen)
1294 break;
1295
1296 /* For subsequent reads align to page boundary. */
1297 col = 0;
1298 /* Increment page address */
1299 realpage++;
1300
1301 page = realpage & chip->pagemask;
1302 /* Check, if we cross a chip boundary */
1303 if (!page) {
1304 chipnr++;
1305 chip->select_chip(mtd, -1);
1306 chip->select_chip(mtd, chipnr);
1307 }
1308
1309 /* Check, if the chip supports auto page increment
1310 * or if we have hit a block boundary.
1311 */
1312 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1313 sndcmd = 1;
1314 }
1315
1316 ops->retlen = ops->len - (size_t) readlen;
1317 if (oob)
1318 ops->oobretlen = ops->ooblen - oobreadlen;
1319
1320 if (ret)
1321 return ret;
1322
1323 if (mtd->ecc_stats.failed - stats.failed)
1324 return -EBADMSG;
1325
1326 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1327 }
1328
1329 /**
1330 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1331 * @mtd: MTD device structure
1332 * @from: offset to read from
1333 * @len: number of bytes to read
1334 * @retlen: pointer to variable to store the number of read bytes
1335 * @buf: the databuffer to put data
1336 *
1337 * Get hold of the chip and call nand_do_read
1338 */
1339 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1340 size_t *retlen, uint8_t *buf)
1341 {
1342 struct nand_chip *chip = mtd->priv;
1343 int ret;
1344
1345 /* Do not allow reads past end of device */
1346 if ((from + len) > mtd->size)
1347 return -EINVAL;
1348 if (!len)
1349 return 0;
1350
1351 nand_get_device(chip, mtd, FL_READING);
1352
1353 chip->ops.len = len;
1354 chip->ops.datbuf = buf;
1355 chip->ops.oobbuf = NULL;
1356
1357 ret = nand_do_read_ops(mtd, from, &chip->ops);
1358
1359 *retlen = chip->ops.retlen;
1360
1361 nand_release_device(mtd);
1362
1363 return ret;
1364 }
1365
1366 /**
1367 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1368 * @mtd: mtd info structure
1369 * @chip: nand chip info structure
1370 * @page: page number to read
1371 * @sndcmd: flag whether to issue read command or not
1372 */
1373 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1374 int page, int sndcmd)
1375 {
1376 if (sndcmd) {
1377 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1378 sndcmd = 0;
1379 }
1380 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1381 return sndcmd;
1382 }
1383
1384 /**
1385 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1386 * with syndromes
1387 * @mtd: mtd info structure
1388 * @chip: nand chip info structure
1389 * @page: page number to read
1390 * @sndcmd: flag whether to issue read command or not
1391 */
1392 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1393 int page, int sndcmd)
1394 {
1395 uint8_t *buf = chip->oob_poi;
1396 int length = mtd->oobsize;
1397 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1398 int eccsize = chip->ecc.size;
1399 uint8_t *bufpoi = buf;
1400 int i, toread, sndrnd = 0, pos;
1401
1402 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1403 for (i = 0; i < chip->ecc.steps; i++) {
1404 if (sndrnd) {
1405 pos = eccsize + i * (eccsize + chunk);
1406 if (mtd->writesize > 512)
1407 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1408 else
1409 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1410 } else
1411 sndrnd = 1;
1412 toread = min_t(int, length, chunk);
1413 chip->read_buf(mtd, bufpoi, toread);
1414 bufpoi += toread;
1415 length -= toread;
1416 }
1417 if (length > 0)
1418 chip->read_buf(mtd, bufpoi, length);
1419
1420 return 1;
1421 }
1422
1423 /**
1424 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1425 * @mtd: mtd info structure
1426 * @chip: nand chip info structure
1427 * @page: page number to write
1428 */
1429 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1430 int page)
1431 {
1432 int status = 0;
1433 const uint8_t *buf = chip->oob_poi;
1434 int length = mtd->oobsize;
1435
1436 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1437 chip->write_buf(mtd, buf, length);
1438 /* Send command to program the OOB data */
1439 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1440
1441 status = chip->waitfunc(mtd, chip);
1442
1443 return status & NAND_STATUS_FAIL ? -EIO : 0;
1444 }
1445
1446 /**
1447 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1448 * with syndrome - only for large page flash !
1449 * @mtd: mtd info structure
1450 * @chip: nand chip info structure
1451 * @page: page number to write
1452 */
1453 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1454 struct nand_chip *chip, int page)
1455 {
1456 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1457 int eccsize = chip->ecc.size, length = mtd->oobsize;
1458 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1459 const uint8_t *bufpoi = chip->oob_poi;
1460
1461 /*
1462 * data-ecc-data-ecc ... ecc-oob
1463 * or
1464 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1465 */
1466 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1467 pos = steps * (eccsize + chunk);
1468 steps = 0;
1469 } else
1470 pos = eccsize;
1471
1472 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1473 for (i = 0; i < steps; i++) {
1474 if (sndcmd) {
1475 if (mtd->writesize <= 512) {
1476 uint32_t fill = 0xFFFFFFFF;
1477
1478 len = eccsize;
1479 while (len > 0) {
1480 int num = min_t(int, len, 4);
1481 chip->write_buf(mtd, (uint8_t *)&fill,
1482 num);
1483 len -= num;
1484 }
1485 } else {
1486 pos = eccsize + i * (eccsize + chunk);
1487 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1488 }
1489 } else
1490 sndcmd = 1;
1491 len = min_t(int, length, chunk);
1492 chip->write_buf(mtd, bufpoi, len);
1493 bufpoi += len;
1494 length -= len;
1495 }
1496 if (length > 0)
1497 chip->write_buf(mtd, bufpoi, length);
1498
1499 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1500 status = chip->waitfunc(mtd, chip);
1501
1502 return status & NAND_STATUS_FAIL ? -EIO : 0;
1503 }
1504
1505 /**
1506 * nand_do_read_oob - [Intern] NAND read out-of-band
1507 * @mtd: MTD device structure
1508 * @from: offset to read from
1509 * @ops: oob operations description structure
1510 *
1511 * NAND read out-of-band data from the spare area
1512 */
1513 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1514 struct mtd_oob_ops *ops)
1515 {
1516 int page, realpage, chipnr, sndcmd = 1;
1517 struct nand_chip *chip = mtd->priv;
1518 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1519 int readlen = ops->ooblen;
1520 int len;
1521 uint8_t *buf = ops->oobbuf;
1522
1523 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1524 __func__, (unsigned long long)from, readlen);
1525
1526 if (ops->mode == MTD_OOB_AUTO)
1527 len = chip->ecc.layout->oobavail;
1528 else
1529 len = mtd->oobsize;
1530
1531 if (unlikely(ops->ooboffs >= len)) {
1532 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1533 "outside oob\n", __func__);
1534 return -EINVAL;
1535 }
1536
1537 /* Do not allow reads past end of device */
1538 if (unlikely(from >= mtd->size ||
1539 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1540 (from >> chip->page_shift)) * len)) {
1541 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1542 "of device\n", __func__);
1543 return -EINVAL;
1544 }
1545
1546 chipnr = (int)(from >> chip->chip_shift);
1547 chip->select_chip(mtd, chipnr);
1548
1549 /* Shift to get page */
1550 realpage = (int)(from >> chip->page_shift);
1551 page = realpage & chip->pagemask;
1552
1553 while (1) {
1554 WATCHDOG_RESET();
1555 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1556
1557 len = min(len, readlen);
1558 buf = nand_transfer_oob(chip, buf, ops, len);
1559
1560 if (!(chip->options & NAND_NO_READRDY)) {
1561 /*
1562 * Apply delay or wait for ready/busy pin. Do this
1563 * before the AUTOINCR check, so no problems arise if a
1564 * chip which does auto increment is marked as
1565 * NOAUTOINCR by the board driver.
1566 */
1567 if (!chip->dev_ready)
1568 udelay(chip->chip_delay);
1569 else
1570 nand_wait_ready(mtd);
1571 }
1572
1573 readlen -= len;
1574 if (!readlen)
1575 break;
1576
1577 /* Increment page address */
1578 realpage++;
1579
1580 page = realpage & chip->pagemask;
1581 /* Check, if we cross a chip boundary */
1582 if (!page) {
1583 chipnr++;
1584 chip->select_chip(mtd, -1);
1585 chip->select_chip(mtd, chipnr);
1586 }
1587
1588 /* Check, if the chip supports auto page increment
1589 * or if we have hit a block boundary.
1590 */
1591 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1592 sndcmd = 1;
1593 }
1594
1595 ops->oobretlen = ops->ooblen;
1596 return 0;
1597 }
1598
1599 /**
1600 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1601 * @mtd: MTD device structure
1602 * @from: offset to read from
1603 * @ops: oob operation description structure
1604 *
1605 * NAND read data and/or out-of-band data
1606 */
1607 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1608 struct mtd_oob_ops *ops)
1609 {
1610 struct nand_chip *chip = mtd->priv;
1611 int ret = -ENOTSUPP;
1612
1613 ops->retlen = 0;
1614
1615 /* Do not allow reads past end of device */
1616 if (ops->datbuf && (from + ops->len) > mtd->size) {
1617 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1618 "beyond end of device\n", __func__);
1619 return -EINVAL;
1620 }
1621
1622 nand_get_device(chip, mtd, FL_READING);
1623
1624 switch (ops->mode) {
1625 case MTD_OOB_PLACE:
1626 case MTD_OOB_AUTO:
1627 case MTD_OOB_RAW:
1628 break;
1629
1630 default:
1631 goto out;
1632 }
1633
1634 if (!ops->datbuf)
1635 ret = nand_do_read_oob(mtd, from, ops);
1636 else
1637 ret = nand_do_read_ops(mtd, from, ops);
1638
1639 out:
1640 nand_release_device(mtd);
1641 return ret;
1642 }
1643
1644
1645 /**
1646 * nand_write_page_raw - [Intern] raw page write function
1647 * @mtd: mtd info structure
1648 * @chip: nand chip info structure
1649 * @buf: data buffer
1650 *
1651 * Not for syndrome calculating ecc controllers, which use a special oob layout
1652 */
1653 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1654 const uint8_t *buf)
1655 {
1656 chip->write_buf(mtd, buf, mtd->writesize);
1657 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1658 }
1659
1660 /**
1661 * nand_write_page_raw_syndrome - [Intern] raw page write function
1662 * @mtd: mtd info structure
1663 * @chip: nand chip info structure
1664 * @buf: data buffer
1665 *
1666 * We need a special oob layout and handling even when ECC isn't checked.
1667 */
1668 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1669 struct nand_chip *chip,
1670 const uint8_t *buf)
1671 {
1672 int eccsize = chip->ecc.size;
1673 int eccbytes = chip->ecc.bytes;
1674 uint8_t *oob = chip->oob_poi;
1675 int steps, size;
1676
1677 for (steps = chip->ecc.steps; steps > 0; steps--) {
1678 chip->write_buf(mtd, buf, eccsize);
1679 buf += eccsize;
1680
1681 if (chip->ecc.prepad) {
1682 chip->write_buf(mtd, oob, chip->ecc.prepad);
1683 oob += chip->ecc.prepad;
1684 }
1685
1686 chip->read_buf(mtd, oob, eccbytes);
1687 oob += eccbytes;
1688
1689 if (chip->ecc.postpad) {
1690 chip->write_buf(mtd, oob, chip->ecc.postpad);
1691 oob += chip->ecc.postpad;
1692 }
1693 }
1694
1695 size = mtd->oobsize - (oob - chip->oob_poi);
1696 if (size)
1697 chip->write_buf(mtd, oob, size);
1698 }
1699 /**
1700 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1701 * @mtd: mtd info structure
1702 * @chip: nand chip info structure
1703 * @buf: data buffer
1704 */
1705 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1706 const uint8_t *buf)
1707 {
1708 int i, eccsize = chip->ecc.size;
1709 int eccbytes = chip->ecc.bytes;
1710 int eccsteps = chip->ecc.steps;
1711 uint8_t *ecc_calc = chip->buffers->ecccalc;
1712 const uint8_t *p = buf;
1713 uint32_t *eccpos = chip->ecc.layout->eccpos;
1714
1715 /* Software ecc calculation */
1716 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1717 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1718
1719 for (i = 0; i < chip->ecc.total; i++)
1720 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1721
1722 chip->ecc.write_page_raw(mtd, chip, buf);
1723 }
1724
1725 /**
1726 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1727 * @mtd: mtd info structure
1728 * @chip: nand chip info structure
1729 * @buf: data buffer
1730 */
1731 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1732 const uint8_t *buf)
1733 {
1734 int i, eccsize = chip->ecc.size;
1735 int eccbytes = chip->ecc.bytes;
1736 int eccsteps = chip->ecc.steps;
1737 uint8_t *ecc_calc = chip->buffers->ecccalc;
1738 const uint8_t *p = buf;
1739 uint32_t *eccpos = chip->ecc.layout->eccpos;
1740
1741 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1742 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1743 chip->write_buf(mtd, p, eccsize);
1744 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1745 }
1746
1747 for (i = 0; i < chip->ecc.total; i++)
1748 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1749
1750 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1751 }
1752
1753 /**
1754 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1755 * @mtd: mtd info structure
1756 * @chip: nand chip info structure
1757 * @buf: data buffer
1758 *
1759 * The hw generator calculates the error syndrome automatically. Therefor
1760 * we need a special oob layout and handling.
1761 */
1762 static void nand_write_page_syndrome(struct mtd_info *mtd,
1763 struct nand_chip *chip, const uint8_t *buf)
1764 {
1765 int i, eccsize = chip->ecc.size;
1766 int eccbytes = chip->ecc.bytes;
1767 int eccsteps = chip->ecc.steps;
1768 const uint8_t *p = buf;
1769 uint8_t *oob = chip->oob_poi;
1770
1771 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1772
1773 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1774 chip->write_buf(mtd, p, eccsize);
1775
1776 if (chip->ecc.prepad) {
1777 chip->write_buf(mtd, oob, chip->ecc.prepad);
1778 oob += chip->ecc.prepad;
1779 }
1780
1781 chip->ecc.calculate(mtd, p, oob);
1782 chip->write_buf(mtd, oob, eccbytes);
1783 oob += eccbytes;
1784
1785 if (chip->ecc.postpad) {
1786 chip->write_buf(mtd, oob, chip->ecc.postpad);
1787 oob += chip->ecc.postpad;
1788 }
1789 }
1790
1791 /* Calculate remaining oob bytes */
1792 i = mtd->oobsize - (oob - chip->oob_poi);
1793 if (i)
1794 chip->write_buf(mtd, oob, i);
1795 }
1796
1797 /**
1798 * nand_write_page - [REPLACEABLE] write one page
1799 * @mtd: MTD device structure
1800 * @chip: NAND chip descriptor
1801 * @buf: the data to write
1802 * @page: page number to write
1803 * @cached: cached programming
1804 * @raw: use _raw version of write_page
1805 */
1806 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1807 const uint8_t *buf, int page, int cached, int raw)
1808 {
1809 int status;
1810
1811 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1812
1813 if (unlikely(raw))
1814 chip->ecc.write_page_raw(mtd, chip, buf);
1815 else
1816 chip->ecc.write_page(mtd, chip, buf);
1817
1818 /*
1819 * Cached progamming disabled for now, Not sure if its worth the
1820 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1821 */
1822 cached = 0;
1823
1824 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1825
1826 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1827 status = chip->waitfunc(mtd, chip);
1828 /*
1829 * See if operation failed and additional status checks are
1830 * available
1831 */
1832 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1833 status = chip->errstat(mtd, chip, FL_WRITING, status,
1834 page);
1835
1836 if (status & NAND_STATUS_FAIL)
1837 return -EIO;
1838 } else {
1839 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1840 status = chip->waitfunc(mtd, chip);
1841 }
1842
1843 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1844 /* Send command to read back the data */
1845 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1846
1847 if (chip->verify_buf(mtd, buf, mtd->writesize))
1848 return -EIO;
1849 #endif
1850 return 0;
1851 }
1852
1853 /**
1854 * nand_fill_oob - [Internal] Transfer client buffer to oob
1855 * @chip: nand chip structure
1856 * @oob: oob data buffer
1857 * @len: oob data write length
1858 * @ops: oob ops structure
1859 */
1860 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
1861 struct mtd_oob_ops *ops)
1862 {
1863 switch (ops->mode) {
1864
1865 case MTD_OOB_PLACE:
1866 case MTD_OOB_RAW:
1867 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1868 return oob + len;
1869
1870 case MTD_OOB_AUTO: {
1871 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1872 uint32_t boffs = 0, woffs = ops->ooboffs;
1873 size_t bytes = 0;
1874
1875 for (; free->length && len; free++, len -= bytes) {
1876 /* Write request not from offset 0 ? */
1877 if (unlikely(woffs)) {
1878 if (woffs >= free->length) {
1879 woffs -= free->length;
1880 continue;
1881 }
1882 boffs = free->offset + woffs;
1883 bytes = min_t(size_t, len,
1884 (free->length - woffs));
1885 woffs = 0;
1886 } else {
1887 bytes = min_t(size_t, len, free->length);
1888 boffs = free->offset;
1889 }
1890 memcpy(chip->oob_poi + boffs, oob, bytes);
1891 oob += bytes;
1892 }
1893 return oob;
1894 }
1895 default:
1896 BUG();
1897 }
1898 return NULL;
1899 }
1900
1901 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1902
1903 /**
1904 * nand_do_write_ops - [Internal] NAND write with ECC
1905 * @mtd: MTD device structure
1906 * @to: offset to write to
1907 * @ops: oob operations description structure
1908 *
1909 * NAND write with ECC
1910 */
1911 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1912 struct mtd_oob_ops *ops)
1913 {
1914 int chipnr, realpage, page, blockmask, column;
1915 struct nand_chip *chip = mtd->priv;
1916 uint32_t writelen = ops->len;
1917
1918 uint32_t oobwritelen = ops->ooblen;
1919 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
1920 mtd->oobavail : mtd->oobsize;
1921
1922 uint8_t *oob = ops->oobbuf;
1923 uint8_t *buf = ops->datbuf;
1924 int ret, subpage;
1925
1926 ops->retlen = 0;
1927 if (!writelen)
1928 return 0;
1929
1930 column = to & (mtd->writesize - 1);
1931 subpage = column || (writelen & (mtd->writesize - 1));
1932
1933 if (subpage && oob)
1934 return -EINVAL;
1935
1936 chipnr = (int)(to >> chip->chip_shift);
1937 chip->select_chip(mtd, chipnr);
1938
1939 /* Check, if it is write protected */
1940 if (nand_check_wp(mtd)) {
1941 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1942 return -EIO;
1943 }
1944
1945 realpage = (int)(to >> chip->page_shift);
1946 page = realpage & chip->pagemask;
1947 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1948
1949 /* Invalidate the page cache, when we write to the cached page */
1950 if (to <= (chip->pagebuf << chip->page_shift) &&
1951 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1952 chip->pagebuf = -1;
1953
1954 /* If we're not given explicit OOB data, let it be 0xFF */
1955 if (likely(!oob))
1956 memset(chip->oob_poi, 0xff, mtd->oobsize);
1957
1958 /* Don't allow multipage oob writes with offset */
1959 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
1960 return -EINVAL;
1961
1962 while (1) {
1963 WATCHDOG_RESET();
1964
1965 int bytes = mtd->writesize;
1966 int cached = writelen > bytes && page != blockmask;
1967 uint8_t *wbuf = buf;
1968
1969 /* Partial page write ? */
1970 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1971 cached = 0;
1972 bytes = min_t(int, bytes - column, (int) writelen);
1973 chip->pagebuf = -1;
1974 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1975 memcpy(&chip->buffers->databuf[column], buf, bytes);
1976 wbuf = chip->buffers->databuf;
1977 }
1978
1979 if (unlikely(oob)) {
1980 size_t len = min(oobwritelen, oobmaxlen);
1981 oob = nand_fill_oob(chip, oob, len, ops);
1982 oobwritelen -= len;
1983 }
1984
1985 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1986 (ops->mode == MTD_OOB_RAW));
1987 if (ret)
1988 break;
1989
1990 writelen -= bytes;
1991 if (!writelen)
1992 break;
1993
1994 column = 0;
1995 buf += bytes;
1996 realpage++;
1997
1998 page = realpage & chip->pagemask;
1999 /* Check, if we cross a chip boundary */
2000 if (!page) {
2001 chipnr++;
2002 chip->select_chip(mtd, -1);
2003 chip->select_chip(mtd, chipnr);
2004 }
2005 }
2006
2007 ops->retlen = ops->len - writelen;
2008 if (unlikely(oob))
2009 ops->oobretlen = ops->ooblen;
2010 return ret;
2011 }
2012
2013 /**
2014 * nand_write - [MTD Interface] NAND write with ECC
2015 * @mtd: MTD device structure
2016 * @to: offset to write to
2017 * @len: number of bytes to write
2018 * @retlen: pointer to variable to store the number of written bytes
2019 * @buf: the data to write
2020 *
2021 * NAND write with ECC
2022 */
2023 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2024 size_t *retlen, const uint8_t *buf)
2025 {
2026 struct nand_chip *chip = mtd->priv;
2027 int ret;
2028
2029 /* Do not allow writes past end of device */
2030 if ((to + len) > mtd->size)
2031 return -EINVAL;
2032 if (!len)
2033 return 0;
2034
2035 nand_get_device(chip, mtd, FL_WRITING);
2036
2037 chip->ops.len = len;
2038 chip->ops.datbuf = (uint8_t *)buf;
2039 chip->ops.oobbuf = NULL;
2040
2041 ret = nand_do_write_ops(mtd, to, &chip->ops);
2042
2043 *retlen = chip->ops.retlen;
2044
2045 nand_release_device(mtd);
2046
2047 return ret;
2048 }
2049
2050 /**
2051 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2052 * @mtd: MTD device structure
2053 * @to: offset to write to
2054 * @ops: oob operation description structure
2055 *
2056 * NAND write out-of-band
2057 */
2058 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2059 struct mtd_oob_ops *ops)
2060 {
2061 int chipnr, page, status, len;
2062 struct nand_chip *chip = mtd->priv;
2063
2064 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2065 __func__, (unsigned int)to, (int)ops->ooblen);
2066
2067 if (ops->mode == MTD_OOB_AUTO)
2068 len = chip->ecc.layout->oobavail;
2069 else
2070 len = mtd->oobsize;
2071
2072 /* Do not allow write past end of page */
2073 if ((ops->ooboffs + ops->ooblen) > len) {
2074 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2075 "past end of page\n", __func__);
2076 return -EINVAL;
2077 }
2078
2079 if (unlikely(ops->ooboffs >= len)) {
2080 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2081 "write outside oob\n", __func__);
2082 return -EINVAL;
2083 }
2084
2085 /* Do not allow write past end of device */
2086 if (unlikely(to >= mtd->size ||
2087 ops->ooboffs + ops->ooblen >
2088 ((mtd->size >> chip->page_shift) -
2089 (to >> chip->page_shift)) * len)) {
2090 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2091 "end of device\n", __func__);
2092 return -EINVAL;
2093 }
2094
2095 chipnr = (int)(to >> chip->chip_shift);
2096 chip->select_chip(mtd, chipnr);
2097
2098 /* Shift to get page */
2099 page = (int)(to >> chip->page_shift);
2100
2101 /*
2102 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2103 * of my DiskOnChip 2000 test units) will clear the whole data page too
2104 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2105 * it in the doc2000 driver in August 1999. dwmw2.
2106 */
2107 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2108
2109 /* Check, if it is write protected */
2110 if (nand_check_wp(mtd))
2111 return -EROFS;
2112
2113 /* Invalidate the page cache, if we write to the cached page */
2114 if (page == chip->pagebuf)
2115 chip->pagebuf = -1;
2116
2117 memset(chip->oob_poi, 0xff, mtd->oobsize);
2118 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
2119 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2120 memset(chip->oob_poi, 0xff, mtd->oobsize);
2121
2122 if (status)
2123 return status;
2124
2125 ops->oobretlen = ops->ooblen;
2126
2127 return 0;
2128 }
2129
2130 /**
2131 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2132 * @mtd: MTD device structure
2133 * @to: offset to write to
2134 * @ops: oob operation description structure
2135 */
2136 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2137 struct mtd_oob_ops *ops)
2138 {
2139 struct nand_chip *chip = mtd->priv;
2140 int ret = -ENOTSUPP;
2141
2142 ops->retlen = 0;
2143
2144 /* Do not allow writes past end of device */
2145 if (ops->datbuf && (to + ops->len) > mtd->size) {
2146 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2147 "end of device\n", __func__);
2148 return -EINVAL;
2149 }
2150
2151 nand_get_device(chip, mtd, FL_WRITING);
2152
2153 switch (ops->mode) {
2154 case MTD_OOB_PLACE:
2155 case MTD_OOB_AUTO:
2156 case MTD_OOB_RAW:
2157 break;
2158
2159 default:
2160 goto out;
2161 }
2162
2163 if (!ops->datbuf)
2164 ret = nand_do_write_oob(mtd, to, ops);
2165 else
2166 ret = nand_do_write_ops(mtd, to, ops);
2167
2168 out:
2169 nand_release_device(mtd);
2170 return ret;
2171 }
2172
2173 /**
2174 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2175 * @mtd: MTD device structure
2176 * @page: the page address of the block which will be erased
2177 *
2178 * Standard erase command for NAND chips
2179 */
2180 static void single_erase_cmd(struct mtd_info *mtd, int page)
2181 {
2182 struct nand_chip *chip = mtd->priv;
2183 /* Send commands to erase a block */
2184 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2185 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2186 }
2187
2188 /**
2189 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2190 * @mtd: MTD device structure
2191 * @page: the page address of the block which will be erased
2192 *
2193 * AND multi block erase command function
2194 * Erase 4 consecutive blocks
2195 */
2196 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2197 {
2198 struct nand_chip *chip = mtd->priv;
2199 /* Send commands to erase a block */
2200 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2201 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2202 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2203 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2204 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2205 }
2206
2207 /**
2208 * nand_erase - [MTD Interface] erase block(s)
2209 * @mtd: MTD device structure
2210 * @instr: erase instruction
2211 *
2212 * Erase one ore more blocks
2213 */
2214 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2215 {
2216 return nand_erase_nand(mtd, instr, 0);
2217 }
2218
2219 #define BBT_PAGE_MASK 0xffffff3f
2220 /**
2221 * nand_erase_nand - [Internal] erase block(s)
2222 * @mtd: MTD device structure
2223 * @instr: erase instruction
2224 * @allowbbt: allow erasing the bbt area
2225 *
2226 * Erase one ore more blocks
2227 */
2228 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2229 int allowbbt)
2230 {
2231 int page, status, pages_per_block, ret, chipnr;
2232 struct nand_chip *chip = mtd->priv;
2233 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2234 unsigned int bbt_masked_page = 0xffffffff;
2235 loff_t len;
2236
2237 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2238 __func__, (unsigned long long)instr->addr,
2239 (unsigned long long)instr->len);
2240
2241 if (check_offs_len(mtd, instr->addr, instr->len))
2242 return -EINVAL;
2243
2244 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2245
2246 /* Grab the lock and see if the device is available */
2247 nand_get_device(chip, mtd, FL_ERASING);
2248
2249 /* Shift to get first page */
2250 page = (int)(instr->addr >> chip->page_shift);
2251 chipnr = (int)(instr->addr >> chip->chip_shift);
2252
2253 /* Calculate pages in each block */
2254 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2255
2256 /* Select the NAND device */
2257 chip->select_chip(mtd, chipnr);
2258
2259 /* Check, if it is write protected */
2260 if (nand_check_wp(mtd)) {
2261 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2262 __func__);
2263 instr->state = MTD_ERASE_FAILED;
2264 goto erase_exit;
2265 }
2266
2267 /*
2268 * If BBT requires refresh, set the BBT page mask to see if the BBT
2269 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2270 * can not be matched. This is also done when the bbt is actually
2271 * erased to avoid recusrsive updates
2272 */
2273 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2274 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2275
2276 /* Loop through the pages */
2277 len = instr->len;
2278
2279 instr->state = MTD_ERASING;
2280
2281 while (len) {
2282 WATCHDOG_RESET();
2283 /*
2284 * heck if we have a bad block, we do not erase bad blocks !
2285 */
2286 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2287 chip->page_shift, 0, allowbbt)) {
2288 printk(KERN_WARNING "%s: attempt to erase a bad block "
2289 "at page 0x%08x\n", __func__, page);
2290 instr->state = MTD_ERASE_FAILED;
2291 goto erase_exit;
2292 }
2293
2294 /*
2295 * Invalidate the page cache, if we erase the block which
2296 * contains the current cached page
2297 */
2298 if (page <= chip->pagebuf && chip->pagebuf <
2299 (page + pages_per_block))
2300 chip->pagebuf = -1;
2301
2302 chip->erase_cmd(mtd, page & chip->pagemask);
2303
2304 status = chip->waitfunc(mtd, chip);
2305
2306 /*
2307 * See if operation failed and additional status checks are
2308 * available
2309 */
2310 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2311 status = chip->errstat(mtd, chip, FL_ERASING,
2312 status, page);
2313
2314 /* See if block erase succeeded */
2315 if (status & NAND_STATUS_FAIL) {
2316 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2317 "page 0x%08x\n", __func__, page);
2318 instr->state = MTD_ERASE_FAILED;
2319 instr->fail_addr =
2320 ((loff_t)page << chip->page_shift);
2321 goto erase_exit;
2322 }
2323
2324 /*
2325 * If BBT requires refresh, set the BBT rewrite flag to the
2326 * page being erased
2327 */
2328 if (bbt_masked_page != 0xffffffff &&
2329 (page & BBT_PAGE_MASK) == bbt_masked_page)
2330 rewrite_bbt[chipnr] =
2331 ((loff_t)page << chip->page_shift);
2332
2333 /* Increment page address and decrement length */
2334 len -= (1 << chip->phys_erase_shift);
2335 page += pages_per_block;
2336
2337 /* Check, if we cross a chip boundary */
2338 if (len && !(page & chip->pagemask)) {
2339 chipnr++;
2340 chip->select_chip(mtd, -1);
2341 chip->select_chip(mtd, chipnr);
2342
2343 /*
2344 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2345 * page mask to see if this BBT should be rewritten
2346 */
2347 if (bbt_masked_page != 0xffffffff &&
2348 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2349 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2350 BBT_PAGE_MASK;
2351 }
2352 }
2353 instr->state = MTD_ERASE_DONE;
2354
2355 erase_exit:
2356
2357 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2358
2359 /* Deselect and wake up anyone waiting on the device */
2360 nand_release_device(mtd);
2361
2362 /* Do call back function */
2363 if (!ret)
2364 mtd_erase_callback(instr);
2365
2366 /*
2367 * If BBT requires refresh and erase was successful, rewrite any
2368 * selected bad block tables
2369 */
2370 if (bbt_masked_page == 0xffffffff || ret)
2371 return ret;
2372
2373 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2374 if (!rewrite_bbt[chipnr])
2375 continue;
2376 /* update the BBT for chip */
2377 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2378 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2379 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2380 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2381 }
2382
2383 /* Return more or less happy */
2384 return ret;
2385 }
2386
2387 /**
2388 * nand_sync - [MTD Interface] sync
2389 * @mtd: MTD device structure
2390 *
2391 * Sync is actually a wait for chip ready function
2392 */
2393 static void nand_sync(struct mtd_info *mtd)
2394 {
2395 struct nand_chip *chip = mtd->priv;
2396
2397 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2398
2399 /* Grab the lock and see if the device is available */
2400 nand_get_device(chip, mtd, FL_SYNCING);
2401 /* Release it and go back */
2402 nand_release_device(mtd);
2403 }
2404
2405 /**
2406 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2407 * @mtd: MTD device structure
2408 * @offs: offset relative to mtd start
2409 */
2410 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2411 {
2412 /* Check for invalid offset */
2413 if (offs > mtd->size)
2414 return -EINVAL;
2415
2416 return nand_block_checkbad(mtd, offs, 1, 0);
2417 }
2418
2419 /**
2420 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2421 * @mtd: MTD device structure
2422 * @ofs: offset relative to mtd start
2423 */
2424 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2425 {
2426 struct nand_chip *chip = mtd->priv;
2427 int ret;
2428
2429 ret = nand_block_isbad(mtd, ofs);
2430 if (ret) {
2431 /* If it was bad already, return success and do nothing. */
2432 if (ret > 0)
2433 return 0;
2434 return ret;
2435 }
2436
2437 return chip->block_markbad(mtd, ofs);
2438 }
2439
2440 /*
2441 * Set default functions
2442 */
2443 static void nand_set_defaults(struct nand_chip *chip, int busw)
2444 {
2445 /* check for proper chip_delay setup, set 20us if not */
2446 if (!chip->chip_delay)
2447 chip->chip_delay = 20;
2448
2449 /* check, if a user supplied command function given */
2450 if (chip->cmdfunc == NULL)
2451 chip->cmdfunc = nand_command;
2452
2453 /* check, if a user supplied wait function given */
2454 if (chip->waitfunc == NULL)
2455 chip->waitfunc = nand_wait;
2456
2457 if (!chip->select_chip)
2458 chip->select_chip = nand_select_chip;
2459 if (!chip->read_byte)
2460 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2461 if (!chip->read_word)
2462 chip->read_word = nand_read_word;
2463 if (!chip->block_bad)
2464 chip->block_bad = nand_block_bad;
2465 if (!chip->block_markbad)
2466 chip->block_markbad = nand_default_block_markbad;
2467 if (!chip->write_buf)
2468 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2469 if (!chip->read_buf)
2470 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2471 if (!chip->verify_buf)
2472 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2473 if (!chip->scan_bbt)
2474 chip->scan_bbt = nand_default_bbt;
2475 if (!chip->controller)
2476 chip->controller = &chip->hwcontrol;
2477 }
2478
2479 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2480 /*
2481 * sanitize ONFI strings so we can safely print them
2482 */
2483 static void sanitize_string(char *s, size_t len)
2484 {
2485 ssize_t i;
2486
2487 /* null terminate */
2488 s[len - 1] = 0;
2489
2490 /* remove non printable chars */
2491 for (i = 0; i < len - 1; i++) {
2492 if (s[i] < ' ' || s[i] > 127)
2493 s[i] = '?';
2494 }
2495
2496 /* remove trailing spaces */
2497 strim(s);
2498 }
2499
2500 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2501 {
2502 int i;
2503 while (len--) {
2504 crc ^= *p++ << 8;
2505 for (i = 0; i < 8; i++)
2506 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2507 }
2508
2509 return crc;
2510 }
2511
2512 /*
2513 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2514 */
2515 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2516 int *busw)
2517 {
2518 struct nand_onfi_params *p = &chip->onfi_params;
2519 int i;
2520 int val;
2521
2522 /* try ONFI for unknow chip or LP */
2523 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2524 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2525 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2526 return 0;
2527
2528 printk(KERN_INFO "ONFI flash detected\n");
2529 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2530 for (i = 0; i < 3; i++) {
2531 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2532 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2533 le16_to_cpu(p->crc)) {
2534 printk(KERN_INFO "ONFI param page %d valid\n", i);
2535 break;
2536 }
2537 }
2538
2539 if (i == 3)
2540 return 0;
2541
2542 /* check version */
2543 val = le16_to_cpu(p->revision);
2544 if (val & (1 << 5))
2545 chip->onfi_version = 23;
2546 else if (val & (1 << 4))
2547 chip->onfi_version = 22;
2548 else if (val & (1 << 3))
2549 chip->onfi_version = 21;
2550 else if (val & (1 << 2))
2551 chip->onfi_version = 20;
2552 else if (val & (1 << 1))
2553 chip->onfi_version = 10;
2554 else
2555 chip->onfi_version = 0;
2556
2557 if (!chip->onfi_version) {
2558 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2559 __func__, val);
2560 return 0;
2561 }
2562
2563 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2564 sanitize_string(p->model, sizeof(p->model));
2565 if (!mtd->name)
2566 mtd->name = p->model;
2567 mtd->writesize = le32_to_cpu(p->byte_per_page);
2568 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2569 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2570 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2571 *busw = 0;
2572 if (le16_to_cpu(p->features) & 1)
2573 *busw = NAND_BUSWIDTH_16;
2574
2575 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2576 chip->options |= (NAND_NO_READRDY |
2577 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2578
2579 return 1;
2580 }
2581 #else
2582 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2583 struct nand_chip *chip,
2584 int *busw)
2585 {
2586 return 0;
2587 }
2588 #endif
2589
2590 /*
2591 * Get the flash and manufacturer id and lookup if the type is supported
2592 */
2593 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2594 struct nand_chip *chip,
2595 int busw,
2596 int *maf_id, int *dev_id,
2597 const struct nand_flash_dev *type)
2598 {
2599 int i, maf_idx;
2600 u8 id_data[8];
2601 int ret;
2602
2603 /* Select the device */
2604 chip->select_chip(mtd, 0);
2605
2606 /*
2607 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2608 * after power-up
2609 */
2610 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2611
2612 /* Send the command for reading device ID */
2613 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2614
2615 /* Read manufacturer and device IDs */
2616 *maf_id = chip->read_byte(mtd);
2617 *dev_id = chip->read_byte(mtd);
2618
2619 /* Try again to make sure, as some systems the bus-hold or other
2620 * interface concerns can cause random data which looks like a
2621 * possibly credible NAND flash to appear. If the two results do
2622 * not match, ignore the device completely.
2623 */
2624
2625 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2626
2627 for (i = 0; i < 2; i++)
2628 id_data[i] = chip->read_byte(mtd);
2629
2630 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2631 printk(KERN_INFO "%s: second ID read did not match "
2632 "%02x,%02x against %02x,%02x\n", __func__,
2633 *maf_id, *dev_id, id_data[0], id_data[1]);
2634 return ERR_PTR(-ENODEV);
2635 }
2636
2637 if (!type)
2638 type = nand_flash_ids;
2639
2640 for (; type->name != NULL; type++)
2641 if (*dev_id == type->id)
2642 break;
2643
2644 chip->onfi_version = 0;
2645 if (!type->name || !type->pagesize) {
2646 /* Check is chip is ONFI compliant */
2647 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2648 if (ret)
2649 goto ident_done;
2650 }
2651
2652 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2653
2654 /* Read entire ID string */
2655
2656 for (i = 0; i < 8; i++)
2657 id_data[i] = chip->read_byte(mtd);
2658
2659 if (!type->name)
2660 return ERR_PTR(-ENODEV);
2661
2662 if (!mtd->name)
2663 mtd->name = type->name;
2664
2665 chip->chipsize = (uint64_t)type->chipsize << 20;
2666
2667 if (!type->pagesize && chip->init_size) {
2668 /* set the pagesize, oobsize, erasesize by the driver*/
2669 busw = chip->init_size(mtd, chip, id_data);
2670 } else if (!type->pagesize) {
2671 int extid;
2672 /* The 3rd id byte holds MLC / multichip data */
2673 chip->cellinfo = id_data[2];
2674 /* The 4th id byte is the important one */
2675 extid = id_data[3];
2676
2677 /*
2678 * Field definitions are in the following datasheets:
2679 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2680 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
2681 *
2682 * Check for wraparound + Samsung ID + nonzero 6th byte
2683 * to decide what to do.
2684 */
2685 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2686 id_data[0] == NAND_MFR_SAMSUNG &&
2687 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2688 id_data[5] != 0x00) {
2689 /* Calc pagesize */
2690 mtd->writesize = 2048 << (extid & 0x03);
2691 extid >>= 2;
2692 /* Calc oobsize */
2693 switch (extid & 0x03) {
2694 case 1:
2695 mtd->oobsize = 128;
2696 break;
2697 case 2:
2698 mtd->oobsize = 218;
2699 break;
2700 case 3:
2701 mtd->oobsize = 400;
2702 break;
2703 default:
2704 mtd->oobsize = 436;
2705 break;
2706 }
2707 extid >>= 2;
2708 /* Calc blocksize */
2709 mtd->erasesize = (128 * 1024) <<
2710 (((extid >> 1) & 0x04) | (extid & 0x03));
2711 busw = 0;
2712 } else {
2713 /* Calc pagesize */
2714 mtd->writesize = 1024 << (extid & 0x03);
2715 extid >>= 2;
2716 /* Calc oobsize */
2717 mtd->oobsize = (8 << (extid & 0x01)) *
2718 (mtd->writesize >> 9);
2719 extid >>= 2;
2720 /* Calc blocksize. Blocksize is multiples of 64KiB */
2721 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2722 extid >>= 2;
2723 /* Get buswidth information */
2724 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2725 }
2726 } else {
2727 /*
2728 * Old devices have chip data hardcoded in the device id table
2729 */
2730 mtd->erasesize = type->erasesize;
2731 mtd->writesize = type->pagesize;
2732 mtd->oobsize = mtd->writesize / 32;
2733 busw = type->options & NAND_BUSWIDTH_16;
2734
2735 /*
2736 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
2737 * some Spansion chips have erasesize that conflicts with size
2738 * listed in nand_ids table
2739 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
2740 */
2741 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
2742 id_data[5] == 0x00 && id_data[6] == 0x00 &&
2743 id_data[7] == 0x00 && mtd->writesize == 512) {
2744 mtd->erasesize = 128 * 1024;
2745 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
2746 }
2747 }
2748 /* Get chip options, preserve non chip based options */
2749 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2750 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2751
2752 /* Check if chip is a not a samsung device. Do not clear the
2753 * options for chips which are not having an extended id.
2754 */
2755 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2756 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2757 ident_done:
2758
2759 /*
2760 * Set chip as a default. Board drivers can override it, if necessary
2761 */
2762 chip->options |= NAND_NO_AUTOINCR;
2763
2764 /* Try to identify manufacturer */
2765 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2766 if (nand_manuf_ids[maf_idx].id == *maf_id)
2767 break;
2768 }
2769
2770 /*
2771 * Check, if buswidth is correct. Hardware drivers should set
2772 * chip correct !
2773 */
2774 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2775 printk(KERN_INFO "NAND device: Manufacturer ID:"
2776 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2777 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2778 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2779 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2780 busw ? 16 : 8);
2781 return ERR_PTR(-EINVAL);
2782 }
2783
2784 /* Calculate the address shift from the page size */
2785 chip->page_shift = ffs(mtd->writesize) - 1;
2786 /* Convert chipsize to number of pages per chip -1. */
2787 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2788
2789 chip->bbt_erase_shift = chip->phys_erase_shift =
2790 ffs(mtd->erasesize) - 1;
2791 if (chip->chipsize & 0xffffffff)
2792 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2793 else {
2794 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
2795 chip->chip_shift += 32 - 1;
2796 }
2797
2798 chip->badblockbits = 8;
2799
2800 /* Set the bad block position */
2801 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
2802 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
2803 else
2804 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
2805
2806 /*
2807 * Bad block marker is stored in the last page of each block
2808 * on Samsung and Hynix MLC devices; stored in first two pages
2809 * of each block on Micron devices with 2KiB pages and on
2810 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
2811 * only the first page.
2812 */
2813 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2814 (*maf_id == NAND_MFR_SAMSUNG ||
2815 *maf_id == NAND_MFR_HYNIX))
2816 chip->options |= NAND_BBT_SCANLASTPAGE;
2817 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2818 (*maf_id == NAND_MFR_SAMSUNG ||
2819 *maf_id == NAND_MFR_HYNIX ||
2820 *maf_id == NAND_MFR_TOSHIBA ||
2821 *maf_id == NAND_MFR_AMD)) ||
2822 (mtd->writesize == 2048 &&
2823 *maf_id == NAND_MFR_MICRON))
2824 chip->options |= NAND_BBT_SCAN2NDPAGE;
2825
2826 /*
2827 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
2828 */
2829 if (!(busw & NAND_BUSWIDTH_16) &&
2830 *maf_id == NAND_MFR_STMICRO &&
2831 mtd->writesize == 2048) {
2832 chip->options |= NAND_BBT_SCANBYTE1AND6;
2833 chip->badblockpos = 0;
2834 }
2835
2836 /* Check for AND chips with 4 page planes */
2837 if (chip->options & NAND_4PAGE_ARRAY)
2838 chip->erase_cmd = multi_erase_cmd;
2839 else
2840 chip->erase_cmd = single_erase_cmd;
2841
2842 /* Do not replace user supplied command function ! */
2843 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2844 chip->cmdfunc = nand_command_lp;
2845
2846 /* TODO onfi flash name */
2847 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2848 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
2849 nand_manuf_ids[maf_idx].name,
2850 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2851 chip->onfi_version ? chip->onfi_params.model : type->name);
2852 #else
2853 type->name);
2854 #endif
2855
2856 return type;
2857 }
2858
2859 /**
2860 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2861 * @mtd: MTD device structure
2862 * @maxchips: Number of chips to scan for
2863 * @table: Alternative NAND ID table
2864 *
2865 * This is the first phase of the normal nand_scan() function. It
2866 * reads the flash ID and sets up MTD fields accordingly.
2867 *
2868 * The mtd->owner field must be set to the module of the caller.
2869 */
2870 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2871 const struct nand_flash_dev *table)
2872 {
2873 int i, busw, nand_maf_id, nand_dev_id;
2874 struct nand_chip *chip = mtd->priv;
2875 const struct nand_flash_dev *type;
2876
2877 /* Get buswidth to select the correct functions */
2878 busw = chip->options & NAND_BUSWIDTH_16;
2879 /* Set the default functions */
2880 nand_set_defaults(chip, busw);
2881
2882 /* Read the flash type */
2883 type = nand_get_flash_type(mtd, chip, busw,
2884 &nand_maf_id, &nand_dev_id, table);
2885
2886 if (IS_ERR(type)) {
2887 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2888 printk(KERN_WARNING "No NAND device found!!!\n");
2889 #endif
2890 chip->select_chip(mtd, -1);
2891 return PTR_ERR(type);
2892 }
2893
2894 /* Check for a chip array */
2895 for (i = 1; i < maxchips; i++) {
2896 chip->select_chip(mtd, i);
2897 /* See comment in nand_get_flash_type for reset */
2898 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2899 /* Send the command for reading device ID */
2900 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2901 /* Read manufacturer and device IDs */
2902 if (nand_maf_id != chip->read_byte(mtd) ||
2903 nand_dev_id != chip->read_byte(mtd))
2904 break;
2905 }
2906 #ifdef DEBUG
2907 if (i > 1)
2908 printk(KERN_INFO "%d NAND chips detected\n", i);
2909 #endif
2910
2911 /* Store the number of chips and calc total size for mtd */
2912 chip->numchips = i;
2913 mtd->size = i * chip->chipsize;
2914
2915 return 0;
2916 }
2917
2918
2919 /**
2920 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2921 * @mtd: MTD device structure
2922 *
2923 * This is the second phase of the normal nand_scan() function. It
2924 * fills out all the uninitialized function pointers with the defaults
2925 * and scans for a bad block table if appropriate.
2926 */
2927 int nand_scan_tail(struct mtd_info *mtd)
2928 {
2929 int i;
2930 struct nand_chip *chip = mtd->priv;
2931
2932 if (!(chip->options & NAND_OWN_BUFFERS))
2933 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2934 if (!chip->buffers)
2935 return -ENOMEM;
2936
2937 /* Set the internal oob buffer location, just after the page data */
2938 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2939
2940 /*
2941 * If no default placement scheme is given, select an appropriate one
2942 */
2943 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
2944 switch (mtd->oobsize) {
2945 case 8:
2946 chip->ecc.layout = &nand_oob_8;
2947 break;
2948 case 16:
2949 chip->ecc.layout = &nand_oob_16;
2950 break;
2951 case 64:
2952 chip->ecc.layout = &nand_oob_64;
2953 break;
2954 case 128:
2955 chip->ecc.layout = &nand_oob_128;
2956 break;
2957 default:
2958 printk(KERN_WARNING "No oob scheme defined for "
2959 "oobsize %d\n", mtd->oobsize);
2960 }
2961 }
2962
2963 if (!chip->write_page)
2964 chip->write_page = nand_write_page;
2965
2966 /*
2967 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2968 * selected and we have 256 byte pagesize fallback to software ECC
2969 */
2970
2971 switch (chip->ecc.mode) {
2972 case NAND_ECC_HW_OOB_FIRST:
2973 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2974 if (!chip->ecc.calculate || !chip->ecc.correct ||
2975 !chip->ecc.hwctl) {
2976 printk(KERN_WARNING "No ECC functions supplied; "
2977 "Hardware ECC not possible\n");
2978 BUG();
2979 }
2980 if (!chip->ecc.read_page)
2981 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2982
2983 case NAND_ECC_HW:
2984 /* Use standard hwecc read page function ? */
2985 if (!chip->ecc.read_page)
2986 chip->ecc.read_page = nand_read_page_hwecc;
2987 if (!chip->ecc.write_page)
2988 chip->ecc.write_page = nand_write_page_hwecc;
2989 if (!chip->ecc.read_page_raw)
2990 chip->ecc.read_page_raw = nand_read_page_raw;
2991 if (!chip->ecc.write_page_raw)
2992 chip->ecc.write_page_raw = nand_write_page_raw;
2993 if (!chip->ecc.read_oob)
2994 chip->ecc.read_oob = nand_read_oob_std;
2995 if (!chip->ecc.write_oob)
2996 chip->ecc.write_oob = nand_write_oob_std;
2997
2998 case NAND_ECC_HW_SYNDROME:
2999 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3000 !chip->ecc.hwctl) &&
3001 (!chip->ecc.read_page ||
3002 chip->ecc.read_page == nand_read_page_hwecc ||
3003 !chip->ecc.write_page ||
3004 chip->ecc.write_page == nand_write_page_hwecc)) {
3005 printk(KERN_WARNING "No ECC functions supplied; "
3006 "Hardware ECC not possible\n");
3007 BUG();
3008 }
3009 /* Use standard syndrome read/write page function ? */
3010 if (!chip->ecc.read_page)
3011 chip->ecc.read_page = nand_read_page_syndrome;
3012 if (!chip->ecc.write_page)
3013 chip->ecc.write_page = nand_write_page_syndrome;
3014 if (!chip->ecc.read_page_raw)
3015 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3016 if (!chip->ecc.write_page_raw)
3017 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3018 if (!chip->ecc.read_oob)
3019 chip->ecc.read_oob = nand_read_oob_syndrome;
3020 if (!chip->ecc.write_oob)
3021 chip->ecc.write_oob = nand_write_oob_syndrome;
3022
3023 if (mtd->writesize >= chip->ecc.size)
3024 break;
3025 printk(KERN_WARNING "%d byte HW ECC not possible on "
3026 "%d byte page size, fallback to SW ECC\n",
3027 chip->ecc.size, mtd->writesize);
3028 chip->ecc.mode = NAND_ECC_SOFT;
3029
3030 case NAND_ECC_SOFT:
3031 if (!mtd_nand_has_ecc_soft()) {
3032 printk(KERN_WARNING "CONFIG_MTD_ECC_SOFT not enabled\n");
3033 return -EINVAL;
3034 }
3035 chip->ecc.calculate = nand_calculate_ecc;
3036 chip->ecc.correct = nand_correct_data;
3037 chip->ecc.read_page = nand_read_page_swecc;
3038 chip->ecc.read_subpage = nand_read_subpage;
3039 chip->ecc.write_page = nand_write_page_swecc;
3040 chip->ecc.read_page_raw = nand_read_page_raw;
3041 chip->ecc.write_page_raw = nand_write_page_raw;
3042 chip->ecc.read_oob = nand_read_oob_std;
3043 chip->ecc.write_oob = nand_write_oob_std;
3044 if (!chip->ecc.size)
3045 chip->ecc.size = 256;
3046 chip->ecc.bytes = 3;
3047 break;
3048
3049 case NAND_ECC_SOFT_BCH:
3050 if (!mtd_nand_has_bch()) {
3051 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3052 return -EINVAL;
3053 }
3054 chip->ecc.calculate = nand_bch_calculate_ecc;
3055 chip->ecc.correct = nand_bch_correct_data;
3056 chip->ecc.read_page = nand_read_page_swecc;
3057 chip->ecc.read_subpage = nand_read_subpage;
3058 chip->ecc.write_page = nand_write_page_swecc;
3059 chip->ecc.read_page_raw = nand_read_page_raw;
3060 chip->ecc.write_page_raw = nand_write_page_raw;
3061 chip->ecc.read_oob = nand_read_oob_std;
3062 chip->ecc.write_oob = nand_write_oob_std;
3063 /*
3064 * Board driver should supply ecc.size and ecc.bytes values to
3065 * select how many bits are correctable; see nand_bch_init()
3066 * for details.
3067 * Otherwise, default to 4 bits for large page devices
3068 */
3069 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3070 chip->ecc.size = 512;
3071 chip->ecc.bytes = 7;
3072 }
3073 chip->ecc.priv = nand_bch_init(mtd,
3074 chip->ecc.size,
3075 chip->ecc.bytes,
3076 &chip->ecc.layout);
3077 if (!chip->ecc.priv)
3078 printk(KERN_WARNING "BCH ECC initialization failed!\n");
3079
3080 break;
3081
3082 case NAND_ECC_NONE:
3083 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3084 "This is not recommended !!\n");
3085 chip->ecc.read_page = nand_read_page_raw;
3086 chip->ecc.write_page = nand_write_page_raw;
3087 chip->ecc.read_oob = nand_read_oob_std;
3088 chip->ecc.read_page_raw = nand_read_page_raw;
3089 chip->ecc.write_page_raw = nand_write_page_raw;
3090 chip->ecc.write_oob = nand_write_oob_std;
3091 chip->ecc.size = mtd->writesize;
3092 chip->ecc.bytes = 0;
3093 break;
3094
3095 default:
3096 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3097 chip->ecc.mode);
3098 BUG();
3099 }
3100
3101 /*
3102 * The number of bytes available for a client to place data into
3103 * the out of band area
3104 */
3105 chip->ecc.layout->oobavail = 0;
3106 for (i = 0; chip->ecc.layout->oobfree[i].length
3107 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3108 chip->ecc.layout->oobavail +=
3109 chip->ecc.layout->oobfree[i].length;
3110 mtd->oobavail = chip->ecc.layout->oobavail;
3111
3112 /*
3113 * Set the number of read / write steps for one page depending on ECC
3114 * mode
3115 */
3116 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3117 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3118 printk(KERN_WARNING "Invalid ecc parameters\n");
3119 BUG();
3120 }
3121 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3122
3123 /*
3124 * Allow subpage writes up to ecc.steps. Not possible for MLC
3125 * FLASH.
3126 */
3127 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3128 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3129 switch (chip->ecc.steps) {
3130 case 2:
3131 mtd->subpage_sft = 1;
3132 break;
3133 case 4:
3134 case 8:
3135 case 16:
3136 mtd->subpage_sft = 2;
3137 break;
3138 }
3139 }
3140 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3141
3142 /* Initialize state */
3143 chip->state = FL_READY;
3144
3145 /* De-select the device */
3146 chip->select_chip(mtd, -1);
3147
3148 /* Invalidate the pagebuffer reference */
3149 chip->pagebuf = -1;
3150
3151 /* Fill in remaining MTD driver data */
3152 mtd->type = MTD_NANDFLASH;
3153 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3154 MTD_CAP_NANDFLASH;
3155 mtd->erase = nand_erase;
3156 mtd->point = NULL;
3157 mtd->unpoint = NULL;
3158 mtd->read = nand_read;
3159 mtd->write = nand_write;
3160 mtd->read_oob = nand_read_oob;
3161 mtd->write_oob = nand_write_oob;
3162 mtd->sync = nand_sync;
3163 mtd->lock = NULL;
3164 mtd->unlock = NULL;
3165 mtd->block_isbad = nand_block_isbad;
3166 mtd->block_markbad = nand_block_markbad;
3167
3168 /* propagate ecc.layout to mtd_info */
3169 mtd->ecclayout = chip->ecc.layout;
3170
3171 /* Check, if we should skip the bad block table scan */
3172 if (chip->options & NAND_SKIP_BBTSCAN)
3173 return 0;
3174
3175 /* Build bad block table */
3176 return chip->scan_bbt(mtd);
3177 }
3178
3179 /**
3180 * nand_scan - [NAND Interface] Scan for the NAND device
3181 * @mtd: MTD device structure
3182 * @maxchips: Number of chips to scan for
3183 *
3184 * This fills out all the uninitialized function pointers
3185 * with the defaults.
3186 * The flash ID is read and the mtd/chip structures are
3187 * filled with the appropriate values.
3188 * The mtd->owner field must be set to the module of the caller
3189 *
3190 */
3191 int nand_scan(struct mtd_info *mtd, int maxchips)
3192 {
3193 int ret;
3194
3195 ret = nand_scan_ident(mtd, maxchips, NULL);
3196 if (!ret)
3197 ret = nand_scan_tail(mtd);
3198 return ret;
3199 }
3200
3201 /**
3202 * nand_release - [NAND Interface] Free resources held by the NAND device
3203 * @mtd: MTD device structure
3204 */
3205 void nand_release(struct mtd_info *mtd)
3206 {
3207 struct nand_chip *chip = mtd->priv;
3208
3209 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3210 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3211
3212 #ifdef CONFIG_MTD_PARTITIONS
3213 /* Deregister partitions */
3214 del_mtd_partitions(mtd);
3215 #endif
3216
3217 /* Free bad block table memory */
3218 kfree(chip->bbt);
3219 if (!(chip->options & NAND_OWN_BUFFERS))
3220 kfree(chip->buffers);
3221
3222 /* Free bad block descriptor memory */
3223 if (chip->badblock_pattern && chip->badblock_pattern->options
3224 & NAND_BBT_DYNAMICSTRUCT)
3225 kfree(chip->badblock_pattern);
3226 }
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