3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #if CONFIG_IS_ENABLED(OF_CONTROL)
37 #include <linux/err.h>
38 #include <linux/compat.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/nand_ecc.h>
42 #include <linux/mtd/nand_bch.h>
43 #ifdef CONFIG_MTD_PARTITIONS
44 #include <linux/mtd/partitions.h>
47 #include <linux/errno.h>
49 /* Define default oob placement schemes for large and small page devices */
50 static struct nand_ecclayout nand_oob_8
= {
60 static struct nand_ecclayout nand_oob_16
= {
62 .eccpos
= {0, 1, 2, 3, 6, 7},
68 static struct nand_ecclayout nand_oob_64
= {
71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
79 static struct nand_ecclayout nand_oob_128
= {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
93 static int nand_get_device(struct mtd_info
*mtd
, int new_state
);
95 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
96 struct mtd_oob_ops
*ops
);
99 * For devices which display every fart in the system on a separate LED. Is
100 * compiled away when LED support is disabled.
102 DEFINE_LED_TRIGGER(nand_led_trigger
);
104 static int check_offs_len(struct mtd_info
*mtd
,
105 loff_t ofs
, uint64_t len
)
107 struct nand_chip
*chip
= mtd_to_nand(mtd
);
110 /* Start address must align on block boundary */
111 if (ofs
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
112 pr_debug("%s: unaligned address\n", __func__
);
116 /* Length must align on block boundary */
117 if (len
& ((1ULL << chip
->phys_erase_shift
) - 1)) {
118 pr_debug("%s: length not block aligned\n", __func__
);
126 * nand_release_device - [GENERIC] release chip
127 * @mtd: MTD device structure
129 * Release chip lock and wake up anyone waiting on the device.
131 static void nand_release_device(struct mtd_info
*mtd
)
133 struct nand_chip
*chip
= mtd_to_nand(mtd
);
135 /* De-select the NAND device */
136 chip
->select_chip(mtd
, -1);
140 * nand_read_byte - [DEFAULT] read one byte from the chip
141 * @mtd: MTD device structure
143 * Default read function for 8bit buswidth
145 uint8_t nand_read_byte(struct mtd_info
*mtd
)
147 struct nand_chip
*chip
= mtd_to_nand(mtd
);
148 return readb(chip
->IO_ADDR_R
);
152 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
153 * @mtd: MTD device structure
155 * Default read function for 16bit buswidth with endianness conversion.
158 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
160 struct nand_chip
*chip
= mtd_to_nand(mtd
);
161 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
165 * nand_read_word - [DEFAULT] read one word from the chip
166 * @mtd: MTD device structure
168 * Default read function for 16bit buswidth without endianness conversion.
170 static u16
nand_read_word(struct mtd_info
*mtd
)
172 struct nand_chip
*chip
= mtd_to_nand(mtd
);
173 return readw(chip
->IO_ADDR_R
);
177 * nand_select_chip - [DEFAULT] control CE line
178 * @mtd: MTD device structure
179 * @chipnr: chipnumber to select, -1 for deselect
181 * Default select function for 1 chip devices.
183 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
185 struct nand_chip
*chip
= mtd_to_nand(mtd
);
189 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
200 * nand_write_byte - [DEFAULT] write single byte to chip
201 * @mtd: MTD device structure
202 * @byte: value to write
204 * Default function to write a byte to I/O[7:0]
206 static void nand_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
208 struct nand_chip
*chip
= mtd_to_nand(mtd
);
210 chip
->write_buf(mtd
, &byte
, 1);
214 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
215 * @mtd: MTD device structure
216 * @byte: value to write
218 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
220 static void nand_write_byte16(struct mtd_info
*mtd
, uint8_t byte
)
222 struct nand_chip
*chip
= mtd_to_nand(mtd
);
223 uint16_t word
= byte
;
226 * It's not entirely clear what should happen to I/O[15:8] when writing
227 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
229 * When the host supports a 16-bit bus width, only data is
230 * transferred at the 16-bit width. All address and command line
231 * transfers shall use only the lower 8-bits of the data bus. During
232 * command transfers, the host may place any value on the upper
233 * 8-bits of the data bus. During address transfers, the host shall
234 * set the upper 8-bits of the data bus to 00h.
236 * One user of the write_byte callback is nand_onfi_set_features. The
237 * four parameters are specified to be written to I/O[7:0], but this is
238 * neither an address nor a command transfer. Let's assume a 0 on the
239 * upper I/O lines is OK.
241 chip
->write_buf(mtd
, (uint8_t *)&word
, 2);
244 static void iowrite8_rep(void *addr
, const uint8_t *buf
, int len
)
248 for (i
= 0; i
< len
; i
++)
249 writeb(buf
[i
], addr
);
251 static void ioread8_rep(void *addr
, uint8_t *buf
, int len
)
255 for (i
= 0; i
< len
; i
++)
256 buf
[i
] = readb(addr
);
259 static void ioread16_rep(void *addr
, void *buf
, int len
)
262 u16
*p
= (u16
*) buf
;
264 for (i
= 0; i
< len
; i
++)
268 static void iowrite16_rep(void *addr
, void *buf
, int len
)
271 u16
*p
= (u16
*) buf
;
273 for (i
= 0; i
< len
; i
++)
278 * nand_write_buf - [DEFAULT] write buffer to chip
279 * @mtd: MTD device structure
281 * @len: number of bytes to write
283 * Default write function for 8bit buswidth.
285 void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
287 struct nand_chip
*chip
= mtd_to_nand(mtd
);
289 iowrite8_rep(chip
->IO_ADDR_W
, buf
, len
);
293 * nand_read_buf - [DEFAULT] read chip data into buffer
294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
298 * Default read function for 8bit buswidth.
300 void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
302 struct nand_chip
*chip
= mtd_to_nand(mtd
);
304 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
308 * nand_write_buf16 - [DEFAULT] write buffer to chip
309 * @mtd: MTD device structure
311 * @len: number of bytes to write
313 * Default write function for 16bit buswidth.
315 void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
317 struct nand_chip
*chip
= mtd_to_nand(mtd
);
318 u16
*p
= (u16
*) buf
;
320 iowrite16_rep(chip
->IO_ADDR_W
, p
, len
>> 1);
324 * nand_read_buf16 - [DEFAULT] read chip data into buffer
325 * @mtd: MTD device structure
326 * @buf: buffer to store date
327 * @len: number of bytes to read
329 * Default read function for 16bit buswidth.
331 void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
333 struct nand_chip
*chip
= mtd_to_nand(mtd
);
334 u16
*p
= (u16
*) buf
;
336 ioread16_rep(chip
->IO_ADDR_R
, p
, len
>> 1);
340 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
341 * @mtd: MTD device structure
342 * @ofs: offset from device start
344 * Check, if the block is bad.
346 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
348 int page
, res
= 0, i
= 0;
349 struct nand_chip
*chip
= mtd_to_nand(mtd
);
352 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
353 ofs
+= mtd
->erasesize
- mtd
->writesize
;
355 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
358 if (chip
->options
& NAND_BUSWIDTH_16
) {
359 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
360 chip
->badblockpos
& 0xFE, page
);
361 bad
= cpu_to_le16(chip
->read_word(mtd
));
362 if (chip
->badblockpos
& 0x1)
367 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
369 bad
= chip
->read_byte(mtd
);
372 if (likely(chip
->badblockbits
== 8))
375 res
= hweight8(bad
) < chip
->badblockbits
;
376 ofs
+= mtd
->writesize
;
377 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
379 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
385 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
386 * @mtd: MTD device structure
387 * @ofs: offset from device start
389 * This is the default implementation, which can be overridden by a hardware
390 * specific driver. It provides the details for writing a bad block marker to a
393 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
395 struct nand_chip
*chip
= mtd_to_nand(mtd
);
396 struct mtd_oob_ops ops
;
397 uint8_t buf
[2] = { 0, 0 };
398 int ret
= 0, res
, i
= 0;
400 memset(&ops
, 0, sizeof(ops
));
402 ops
.ooboffs
= chip
->badblockpos
;
403 if (chip
->options
& NAND_BUSWIDTH_16
) {
404 ops
.ooboffs
&= ~0x01;
405 ops
.len
= ops
.ooblen
= 2;
407 ops
.len
= ops
.ooblen
= 1;
409 ops
.mode
= MTD_OPS_PLACE_OOB
;
411 /* Write to first/last page(s) if necessary */
412 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
413 ofs
+= mtd
->erasesize
- mtd
->writesize
;
415 res
= nand_do_write_oob(mtd
, ofs
, &ops
);
420 ofs
+= mtd
->writesize
;
421 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
427 * nand_block_markbad_lowlevel - mark a block bad
428 * @mtd: MTD device structure
429 * @ofs: offset from device start
431 * This function performs the generic NAND bad block marking steps (i.e., bad
432 * block table(s) and/or marker(s)). We only allow the hardware driver to
433 * specify how to write bad block markers to OOB (chip->block_markbad).
435 * We try operations in the following order:
436 * (1) erase the affected block, to allow OOB marker to be written cleanly
437 * (2) write bad block marker to OOB area of affected block (unless flag
438 * NAND_BBT_NO_OOB_BBM is present)
440 * Note that we retain the first error encountered in (2) or (3), finish the
441 * procedures, and dump the error in the end.
443 static int nand_block_markbad_lowlevel(struct mtd_info
*mtd
, loff_t ofs
)
445 struct nand_chip
*chip
= mtd_to_nand(mtd
);
448 if (!(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
)) {
449 struct erase_info einfo
;
451 /* Attempt erase before marking OOB */
452 memset(&einfo
, 0, sizeof(einfo
));
455 einfo
.len
= 1ULL << chip
->phys_erase_shift
;
456 nand_erase_nand(mtd
, &einfo
, 0);
458 /* Write bad block marker to OOB */
459 nand_get_device(mtd
, FL_WRITING
);
460 ret
= chip
->block_markbad(mtd
, ofs
);
461 nand_release_device(mtd
);
464 /* Mark block bad in BBT */
466 res
= nand_markbad_bbt(mtd
, ofs
);
472 mtd
->ecc_stats
.badblocks
++;
478 * nand_check_wp - [GENERIC] check if the chip is write protected
479 * @mtd: MTD device structure
481 * Check, if the device is write protected. The function expects, that the
482 * device is already selected.
484 static int nand_check_wp(struct mtd_info
*mtd
)
486 struct nand_chip
*chip
= mtd_to_nand(mtd
);
488 /* Broken xD cards report WP despite being writable */
489 if (chip
->options
& NAND_BROKEN_XD
)
492 /* Check the WP bit */
493 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
494 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
498 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
499 * @mtd: MTD device structure
500 * @ofs: offset from device start
502 * Check if the block is marked as reserved.
504 static int nand_block_isreserved(struct mtd_info
*mtd
, loff_t ofs
)
506 struct nand_chip
*chip
= mtd_to_nand(mtd
);
510 /* Return info from the table */
511 return nand_isreserved_bbt(mtd
, ofs
);
515 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
516 * @mtd: MTD device structure
517 * @ofs: offset from device start
518 * @allowbbt: 1, if its allowed to access the bbt area
520 * Check, if the block is bad. Either by reading the bad block table or
521 * calling of the scan function.
523 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int allowbbt
)
525 struct nand_chip
*chip
= mtd_to_nand(mtd
);
527 if (!(chip
->options
& NAND_SKIP_BBTSCAN
) &&
528 !(chip
->options
& NAND_BBT_SCANNED
)) {
529 chip
->options
|= NAND_BBT_SCANNED
;
534 return chip
->block_bad(mtd
, ofs
);
536 /* Return info from the table */
537 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
541 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
542 * @mtd: MTD device structure
544 * Wait for the ready pin after a command, and warn if a timeout occurs.
546 void nand_wait_ready(struct mtd_info
*mtd
)
548 struct nand_chip
*chip
= mtd_to_nand(mtd
);
549 u32 timeo
= (CONFIG_SYS_HZ
* 400) / 1000;
552 time_start
= get_timer(0);
553 /* Wait until command is processed or timeout occurs */
554 while (get_timer(time_start
) < timeo
) {
556 if (chip
->dev_ready(mtd
))
560 if (!chip
->dev_ready(mtd
))
561 pr_warn("timeout while waiting for chip to become ready\n");
563 EXPORT_SYMBOL_GPL(nand_wait_ready
);
566 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
567 * @mtd: MTD device structure
568 * @timeo: Timeout in ms
570 * Wait for status ready (i.e. command done) or timeout.
572 static void nand_wait_status_ready(struct mtd_info
*mtd
, unsigned long timeo
)
574 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
577 timeo
= (CONFIG_SYS_HZ
* timeo
) / 1000;
578 time_start
= get_timer(0);
579 while (get_timer(time_start
) < timeo
) {
580 if ((chip
->read_byte(mtd
) & NAND_STATUS_READY
))
587 * nand_command - [DEFAULT] Send command to NAND device
588 * @mtd: MTD device structure
589 * @command: the command to be sent
590 * @column: the column address for this command, -1 if none
591 * @page_addr: the page address for this command, -1 if none
593 * Send command to NAND device. This function is used for small page devices
594 * (512 Bytes per page).
596 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
597 int column
, int page_addr
)
599 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
600 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
602 /* Write out the command to the device */
603 if (command
== NAND_CMD_SEQIN
) {
606 if (column
>= mtd
->writesize
) {
608 column
-= mtd
->writesize
;
609 readcmd
= NAND_CMD_READOOB
;
610 } else if (column
< 256) {
611 /* First 256 bytes --> READ0 */
612 readcmd
= NAND_CMD_READ0
;
615 readcmd
= NAND_CMD_READ1
;
617 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
618 ctrl
&= ~NAND_CTRL_CHANGE
;
620 chip
->cmd_ctrl(mtd
, command
, ctrl
);
622 /* Address cycle, when necessary */
623 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
624 /* Serially input address */
626 /* Adjust columns for 16 bit buswidth */
627 if (chip
->options
& NAND_BUSWIDTH_16
&&
628 !nand_opcode_8bits(command
))
630 chip
->cmd_ctrl(mtd
, column
, ctrl
);
631 ctrl
&= ~NAND_CTRL_CHANGE
;
633 if (page_addr
!= -1) {
634 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
635 ctrl
&= ~NAND_CTRL_CHANGE
;
636 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
637 /* One more address cycle for devices > 32MiB */
638 if (chip
->chipsize
> (32 << 20))
639 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
641 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
644 * Program and erase have their own busy handlers status and sequential
649 case NAND_CMD_PAGEPROG
:
650 case NAND_CMD_ERASE1
:
651 case NAND_CMD_ERASE2
:
653 case NAND_CMD_STATUS
:
654 case NAND_CMD_READID
:
655 case NAND_CMD_SET_FEATURES
:
661 udelay(chip
->chip_delay
);
662 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
663 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
665 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
666 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
667 nand_wait_status_ready(mtd
, 250);
670 /* This applies to read commands */
673 * If we don't have access to the busy pin, we apply the given
676 if (!chip
->dev_ready
) {
677 udelay(chip
->chip_delay
);
682 * Apply this short delay always to ensure that we do wait tWB in
683 * any case on any machine.
687 nand_wait_ready(mtd
);
691 * nand_command_lp - [DEFAULT] Send command to NAND large page device
692 * @mtd: MTD device structure
693 * @command: the command to be sent
694 * @column: the column address for this command, -1 if none
695 * @page_addr: the page address for this command, -1 if none
697 * Send command to NAND device. This is the version for the new large page
698 * devices. We don't have the separate regions as we have in the small page
699 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
701 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
702 int column
, int page_addr
)
704 register struct nand_chip
*chip
= mtd_to_nand(mtd
);
706 /* Emulate NAND_CMD_READOOB */
707 if (command
== NAND_CMD_READOOB
) {
708 column
+= mtd
->writesize
;
709 command
= NAND_CMD_READ0
;
712 /* Command latch cycle */
713 chip
->cmd_ctrl(mtd
, command
, NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
715 if (column
!= -1 || page_addr
!= -1) {
716 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
718 /* Serially input address */
720 /* Adjust columns for 16 bit buswidth */
721 if (chip
->options
& NAND_BUSWIDTH_16
&&
722 !nand_opcode_8bits(command
))
724 chip
->cmd_ctrl(mtd
, column
, ctrl
);
725 ctrl
&= ~NAND_CTRL_CHANGE
;
726 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
728 if (page_addr
!= -1) {
729 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
730 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
731 NAND_NCE
| NAND_ALE
);
732 /* One more address cycle for devices > 128MiB */
733 if (chip
->chipsize
> (128 << 20))
734 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
735 NAND_NCE
| NAND_ALE
);
738 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
741 * Program and erase have their own busy handlers status, sequential
742 * in and status need no delay.
746 case NAND_CMD_CACHEDPROG
:
747 case NAND_CMD_PAGEPROG
:
748 case NAND_CMD_ERASE1
:
749 case NAND_CMD_ERASE2
:
752 case NAND_CMD_STATUS
:
753 case NAND_CMD_READID
:
754 case NAND_CMD_SET_FEATURES
:
760 udelay(chip
->chip_delay
);
761 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
762 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
763 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
764 NAND_NCE
| NAND_CTRL_CHANGE
);
765 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
766 nand_wait_status_ready(mtd
, 250);
769 case NAND_CMD_RNDOUT
:
770 /* No ready / busy check necessary */
771 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
772 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
773 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
774 NAND_NCE
| NAND_CTRL_CHANGE
);
778 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
779 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
780 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
781 NAND_NCE
| NAND_CTRL_CHANGE
);
783 /* This applies to read commands */
786 * If we don't have access to the busy pin, we apply the given
789 if (!chip
->dev_ready
) {
790 udelay(chip
->chip_delay
);
796 * Apply this short delay always to ensure that we do wait tWB in
797 * any case on any machine.
801 nand_wait_ready(mtd
);
805 * panic_nand_get_device - [GENERIC] Get chip for selected access
806 * @chip: the nand chip descriptor
807 * @mtd: MTD device structure
808 * @new_state: the state which is requested
810 * Used when in panic, no locks are taken.
812 static void panic_nand_get_device(struct nand_chip
*chip
,
813 struct mtd_info
*mtd
, int new_state
)
815 /* Hardware controller shared among independent devices */
816 chip
->controller
->active
= chip
;
817 chip
->state
= new_state
;
821 * nand_get_device - [GENERIC] Get chip for selected access
822 * @mtd: MTD device structure
823 * @new_state: the state which is requested
825 * Get the device and lock it for exclusive access
828 nand_get_device(struct mtd_info
*mtd
, int new_state
)
830 struct nand_chip
*chip
= mtd_to_nand(mtd
);
831 chip
->state
= new_state
;
836 * panic_nand_wait - [GENERIC] wait until the command is done
837 * @mtd: MTD device structure
838 * @chip: NAND chip structure
841 * Wait for command done. This is a helper function for nand_wait used when
842 * we are in interrupt context. May happen when in panic and trying to write
843 * an oops through mtdoops.
845 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
849 for (i
= 0; i
< timeo
; i
++) {
850 if (chip
->dev_ready
) {
851 if (chip
->dev_ready(mtd
))
854 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
862 * nand_wait - [DEFAULT] wait until the command is done
863 * @mtd: MTD device structure
864 * @chip: NAND chip structure
866 * Wait for command done. This applies to erase and program only.
868 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
871 unsigned long timeo
= 400;
873 led_trigger_event(nand_led_trigger
, LED_FULL
);
876 * Apply this short delay always to ensure that we do wait tWB in any
877 * case on any machine.
881 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
883 u32 timer
= (CONFIG_SYS_HZ
* timeo
) / 1000;
886 time_start
= get_timer(0);
887 while (get_timer(time_start
) < timer
) {
888 if (chip
->dev_ready
) {
889 if (chip
->dev_ready(mtd
))
892 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
896 led_trigger_event(nand_led_trigger
, LED_OFF
);
898 status
= (int)chip
->read_byte(mtd
);
899 /* This can happen if in case of timeout or buggy dev_ready */
900 WARN_ON(!(status
& NAND_STATUS_READY
));
905 * nand_reset_data_interface - Reset data interface and timings
906 * @chip: The NAND chip
908 * Reset the Data interface and timings to ONFI mode 0.
910 * Returns 0 for success or negative error code otherwise.
912 static int nand_reset_data_interface(struct nand_chip
*chip
)
914 struct mtd_info
*mtd
= nand_to_mtd(chip
);
915 const struct nand_data_interface
*conf
;
918 if (!chip
->setup_data_interface
)
922 * The ONFI specification says:
924 * To transition from NV-DDR or NV-DDR2 to the SDR data
925 * interface, the host shall use the Reset (FFh) command
926 * using SDR timing mode 0. A device in any timing mode is
927 * required to recognize Reset (FFh) command issued in SDR
931 * Configure the data interface in SDR mode and set the
932 * timings to timing mode 0.
935 conf
= nand_get_default_data_interface();
936 ret
= chip
->setup_data_interface(mtd
, conf
, false);
938 pr_err("Failed to configure data interface to SDR timing mode 0\n");
944 * nand_setup_data_interface - Setup the best data interface and timings
945 * @chip: The NAND chip
947 * Find and configure the best data interface and NAND timings supported by
948 * the chip and the driver.
949 * First tries to retrieve supported timing modes from ONFI information,
950 * and if the NAND chip does not support ONFI, relies on the
951 * ->onfi_timing_mode_default specified in the nand_ids table.
953 * Returns 0 for success or negative error code otherwise.
955 static int nand_setup_data_interface(struct nand_chip
*chip
)
957 struct mtd_info
*mtd
= nand_to_mtd(chip
);
960 if (!chip
->setup_data_interface
|| !chip
->data_interface
)
964 * Ensure the timing mode has been changed on the chip side
965 * before changing timings on the controller side.
967 if (chip
->onfi_version
) {
968 u8 tmode_param
[ONFI_SUBFEATURE_PARAM_LEN
] = {
969 chip
->onfi_timing_mode_default
,
972 ret
= chip
->onfi_set_features(mtd
, chip
,
973 ONFI_FEATURE_ADDR_TIMING_MODE
,
979 ret
= chip
->setup_data_interface(mtd
, chip
->data_interface
, false);
985 * nand_init_data_interface - find the best data interface and timings
986 * @chip: The NAND chip
988 * Find the best data interface and NAND timings supported by the chip
990 * First tries to retrieve supported timing modes from ONFI information,
991 * and if the NAND chip does not support ONFI, relies on the
992 * ->onfi_timing_mode_default specified in the nand_ids table. After this
993 * function nand_chip->data_interface is initialized with the best timing mode
996 * Returns 0 for success or negative error code otherwise.
998 static int nand_init_data_interface(struct nand_chip
*chip
)
1000 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1001 int modes
, mode
, ret
;
1003 if (!chip
->setup_data_interface
)
1007 * First try to identify the best timings from ONFI parameters and
1008 * if the NAND does not support ONFI, fallback to the default ONFI
1011 modes
= onfi_get_async_timing_mode(chip
);
1012 if (modes
== ONFI_TIMING_MODE_UNKNOWN
) {
1013 if (!chip
->onfi_timing_mode_default
)
1016 modes
= GENMASK(chip
->onfi_timing_mode_default
, 0);
1019 chip
->data_interface
= kzalloc(sizeof(*chip
->data_interface
),
1021 if (!chip
->data_interface
)
1024 for (mode
= fls(modes
) - 1; mode
>= 0; mode
--) {
1025 ret
= onfi_init_data_interface(chip
, chip
->data_interface
,
1026 NAND_SDR_IFACE
, mode
);
1030 ret
= chip
->setup_data_interface(mtd
, chip
->data_interface
,
1033 chip
->onfi_timing_mode_default
= mode
;
1041 static void __maybe_unused
nand_release_data_interface(struct nand_chip
*chip
)
1043 kfree(chip
->data_interface
);
1047 * nand_reset - Reset and initialize a NAND device
1048 * @chip: The NAND chip
1049 * @chipnr: Internal die id
1051 * Returns 0 for success or negative error code otherwise
1053 int nand_reset(struct nand_chip
*chip
, int chipnr
)
1055 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1058 ret
= nand_reset_data_interface(chip
);
1063 * The CS line has to be released before we can apply the new NAND
1064 * interface settings, hence this weird ->select_chip() dance.
1066 chip
->select_chip(mtd
, chipnr
);
1067 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
1068 chip
->select_chip(mtd
, -1);
1070 chip
->select_chip(mtd
, chipnr
);
1071 ret
= nand_setup_data_interface(chip
);
1072 chip
->select_chip(mtd
, -1);
1080 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1081 * @buf: buffer to test
1082 * @len: buffer length
1083 * @bitflips_threshold: maximum number of bitflips
1085 * Check if a buffer contains only 0xff, which means the underlying region
1086 * has been erased and is ready to be programmed.
1087 * The bitflips_threshold specify the maximum number of bitflips before
1088 * considering the region is not erased.
1089 * Note: The logic of this function has been extracted from the memweight
1090 * implementation, except that nand_check_erased_buf function exit before
1091 * testing the whole buffer if the number of bitflips exceed the
1092 * bitflips_threshold value.
1094 * Returns a positive number of bitflips less than or equal to
1095 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1098 static int nand_check_erased_buf(void *buf
, int len
, int bitflips_threshold
)
1100 const unsigned char *bitmap
= buf
;
1104 for (; len
&& ((uintptr_t)bitmap
) % sizeof(long);
1106 weight
= hweight8(*bitmap
);
1107 bitflips
+= BITS_PER_BYTE
- weight
;
1108 if (unlikely(bitflips
> bitflips_threshold
))
1112 for (; len
>= 4; len
-= 4, bitmap
+= 4) {
1113 weight
= hweight32(*((u32
*)bitmap
));
1114 bitflips
+= 32 - weight
;
1115 if (unlikely(bitflips
> bitflips_threshold
))
1119 for (; len
> 0; len
--, bitmap
++) {
1120 weight
= hweight8(*bitmap
);
1121 bitflips
+= BITS_PER_BYTE
- weight
;
1122 if (unlikely(bitflips
> bitflips_threshold
))
1130 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1132 * @data: data buffer to test
1133 * @datalen: data length
1135 * @ecclen: ECC length
1136 * @extraoob: extra OOB buffer
1137 * @extraooblen: extra OOB length
1138 * @bitflips_threshold: maximum number of bitflips
1140 * Check if a data buffer and its associated ECC and OOB data contains only
1141 * 0xff pattern, which means the underlying region has been erased and is
1142 * ready to be programmed.
1143 * The bitflips_threshold specify the maximum number of bitflips before
1144 * considering the region as not erased.
1147 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1148 * different from the NAND page size. When fixing bitflips, ECC engines will
1149 * report the number of errors per chunk, and the NAND core infrastructure
1150 * expect you to return the maximum number of bitflips for the whole page.
1151 * This is why you should always use this function on a single chunk and
1152 * not on the whole page. After checking each chunk you should update your
1153 * max_bitflips value accordingly.
1154 * 2/ When checking for bitflips in erased pages you should not only check
1155 * the payload data but also their associated ECC data, because a user might
1156 * have programmed almost all bits to 1 but a few. In this case, we
1157 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1159 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1160 * data are protected by the ECC engine.
1161 * It could also be used if you support subpages and want to attach some
1162 * extra OOB data to an ECC chunk.
1164 * Returns a positive number of bitflips less than or equal to
1165 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1166 * threshold. In case of success, the passed buffers are filled with 0xff.
1168 int nand_check_erased_ecc_chunk(void *data
, int datalen
,
1169 void *ecc
, int ecclen
,
1170 void *extraoob
, int extraooblen
,
1171 int bitflips_threshold
)
1173 int data_bitflips
= 0, ecc_bitflips
= 0, extraoob_bitflips
= 0;
1175 data_bitflips
= nand_check_erased_buf(data
, datalen
,
1176 bitflips_threshold
);
1177 if (data_bitflips
< 0)
1178 return data_bitflips
;
1180 bitflips_threshold
-= data_bitflips
;
1182 ecc_bitflips
= nand_check_erased_buf(ecc
, ecclen
, bitflips_threshold
);
1183 if (ecc_bitflips
< 0)
1184 return ecc_bitflips
;
1186 bitflips_threshold
-= ecc_bitflips
;
1188 extraoob_bitflips
= nand_check_erased_buf(extraoob
, extraooblen
,
1189 bitflips_threshold
);
1190 if (extraoob_bitflips
< 0)
1191 return extraoob_bitflips
;
1194 memset(data
, 0xff, datalen
);
1197 memset(ecc
, 0xff, ecclen
);
1199 if (extraoob_bitflips
)
1200 memset(extraoob
, 0xff, extraooblen
);
1202 return data_bitflips
+ ecc_bitflips
+ extraoob_bitflips
;
1204 EXPORT_SYMBOL(nand_check_erased_ecc_chunk
);
1207 * nand_read_page_raw - [INTERN] read raw page data without ecc
1208 * @mtd: mtd info structure
1209 * @chip: nand chip info structure
1210 * @buf: buffer to store read data
1211 * @oob_required: caller requires OOB data read to chip->oob_poi
1212 * @page: page number to read
1214 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1216 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1217 uint8_t *buf
, int oob_required
, int page
)
1219 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1221 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1226 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1227 * @mtd: mtd info structure
1228 * @chip: nand chip info structure
1229 * @buf: buffer to store read data
1230 * @oob_required: caller requires OOB data read to chip->oob_poi
1231 * @page: page number to read
1233 * We need a special oob layout and handling even when OOB isn't used.
1235 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1236 struct nand_chip
*chip
, uint8_t *buf
,
1237 int oob_required
, int page
)
1239 int eccsize
= chip
->ecc
.size
;
1240 int eccbytes
= chip
->ecc
.bytes
;
1241 uint8_t *oob
= chip
->oob_poi
;
1244 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1245 chip
->read_buf(mtd
, buf
, eccsize
);
1248 if (chip
->ecc
.prepad
) {
1249 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1250 oob
+= chip
->ecc
.prepad
;
1253 chip
->read_buf(mtd
, oob
, eccbytes
);
1256 if (chip
->ecc
.postpad
) {
1257 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1258 oob
+= chip
->ecc
.postpad
;
1262 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1264 chip
->read_buf(mtd
, oob
, size
);
1270 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1271 * @mtd: mtd info structure
1272 * @chip: nand chip info structure
1273 * @buf: buffer to store read data
1274 * @oob_required: caller requires OOB data read to chip->oob_poi
1275 * @page: page number to read
1277 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1278 uint8_t *buf
, int oob_required
, int page
)
1280 int i
, eccsize
= chip
->ecc
.size
;
1281 int eccbytes
= chip
->ecc
.bytes
;
1282 int eccsteps
= chip
->ecc
.steps
;
1284 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1285 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1286 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1287 unsigned int max_bitflips
= 0;
1289 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1291 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1292 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1294 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1295 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1297 eccsteps
= chip
->ecc
.steps
;
1300 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1303 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1305 mtd
->ecc_stats
.failed
++;
1307 mtd
->ecc_stats
.corrected
+= stat
;
1308 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1311 return max_bitflips
;
1315 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1316 * @mtd: mtd info structure
1317 * @chip: nand chip info structure
1318 * @data_offs: offset of requested data within the page
1319 * @readlen: data length
1320 * @bufpoi: buffer to store read data
1321 * @page: page number to read
1323 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1324 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
,
1327 int start_step
, end_step
, num_steps
;
1328 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1330 int data_col_addr
, i
, gaps
= 0;
1331 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1332 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1334 unsigned int max_bitflips
= 0;
1336 /* Column address within the page aligned to ECC size (256bytes) */
1337 start_step
= data_offs
/ chip
->ecc
.size
;
1338 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1339 num_steps
= end_step
- start_step
+ 1;
1340 index
= start_step
* chip
->ecc
.bytes
;
1342 /* Data size aligned to ECC ecc.size */
1343 datafrag_len
= num_steps
* chip
->ecc
.size
;
1344 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1346 data_col_addr
= start_step
* chip
->ecc
.size
;
1347 /* If we read not a page aligned data */
1348 if (data_col_addr
!= 0)
1349 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1351 p
= bufpoi
+ data_col_addr
;
1352 chip
->read_buf(mtd
, p
, datafrag_len
);
1355 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1356 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1359 * The performance is faster if we position offsets according to
1360 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1362 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1363 if (eccpos
[i
+ index
] + 1 != eccpos
[i
+ index
+ 1]) {
1369 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1370 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1373 * Send the command to read the particular ECC bytes take care
1374 * about buswidth alignment in read_buf.
1376 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1377 aligned_len
= eccfrag_len
;
1378 if (eccpos
[index
] & (busw
- 1))
1380 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1383 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1384 mtd
->writesize
+ aligned_pos
, -1);
1385 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1388 for (i
= 0; i
< eccfrag_len
; i
++)
1389 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1391 p
= bufpoi
+ data_col_addr
;
1392 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1395 stat
= chip
->ecc
.correct(mtd
, p
,
1396 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1397 if (stat
== -EBADMSG
&&
1398 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1399 /* check for empty pages with bitflips */
1400 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1401 &chip
->buffers
->ecccode
[i
],
1404 chip
->ecc
.strength
);
1408 mtd
->ecc_stats
.failed
++;
1410 mtd
->ecc_stats
.corrected
+= stat
;
1411 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1414 return max_bitflips
;
1418 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1419 * @mtd: mtd info structure
1420 * @chip: nand chip info structure
1421 * @buf: buffer to store read data
1422 * @oob_required: caller requires OOB data read to chip->oob_poi
1423 * @page: page number to read
1425 * Not for syndrome calculating ECC controllers which need a special oob layout.
1427 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1428 uint8_t *buf
, int oob_required
, int page
)
1430 int i
, eccsize
= chip
->ecc
.size
;
1431 int eccbytes
= chip
->ecc
.bytes
;
1432 int eccsteps
= chip
->ecc
.steps
;
1434 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1435 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1436 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1437 unsigned int max_bitflips
= 0;
1439 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1440 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1441 chip
->read_buf(mtd
, p
, eccsize
);
1442 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1444 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1446 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1447 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1449 eccsteps
= chip
->ecc
.steps
;
1452 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1455 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1456 if (stat
== -EBADMSG
&&
1457 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1458 /* check for empty pages with bitflips */
1459 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1460 &ecc_code
[i
], eccbytes
,
1462 chip
->ecc
.strength
);
1466 mtd
->ecc_stats
.failed
++;
1468 mtd
->ecc_stats
.corrected
+= stat
;
1469 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1472 return max_bitflips
;
1476 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1477 * @mtd: mtd info structure
1478 * @chip: nand chip info structure
1479 * @buf: buffer to store read data
1480 * @oob_required: caller requires OOB data read to chip->oob_poi
1481 * @page: page number to read
1483 * Hardware ECC for large page chips, require OOB to be read first. For this
1484 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1485 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1486 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1487 * the data area, by overwriting the NAND manufacturer bad block markings.
1489 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1490 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1492 int i
, eccsize
= chip
->ecc
.size
;
1493 int eccbytes
= chip
->ecc
.bytes
;
1494 int eccsteps
= chip
->ecc
.steps
;
1496 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1497 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1498 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1499 unsigned int max_bitflips
= 0;
1501 /* Read the OOB area first */
1502 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1503 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1504 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1506 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1507 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1509 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1512 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1513 chip
->read_buf(mtd
, p
, eccsize
);
1514 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1516 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1517 if (stat
== -EBADMSG
&&
1518 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1519 /* check for empty pages with bitflips */
1520 stat
= nand_check_erased_ecc_chunk(p
, eccsize
,
1521 &ecc_code
[i
], eccbytes
,
1523 chip
->ecc
.strength
);
1527 mtd
->ecc_stats
.failed
++;
1529 mtd
->ecc_stats
.corrected
+= stat
;
1530 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1533 return max_bitflips
;
1537 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1538 * @mtd: mtd info structure
1539 * @chip: nand chip info structure
1540 * @buf: buffer to store read data
1541 * @oob_required: caller requires OOB data read to chip->oob_poi
1542 * @page: page number to read
1544 * The hw generator calculates the error syndrome automatically. Therefore we
1545 * need a special oob layout and handling.
1547 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1548 uint8_t *buf
, int oob_required
, int page
)
1550 int i
, eccsize
= chip
->ecc
.size
;
1551 int eccbytes
= chip
->ecc
.bytes
;
1552 int eccsteps
= chip
->ecc
.steps
;
1553 int eccpadbytes
= eccbytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1555 uint8_t *oob
= chip
->oob_poi
;
1556 unsigned int max_bitflips
= 0;
1558 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1561 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1562 chip
->read_buf(mtd
, p
, eccsize
);
1564 if (chip
->ecc
.prepad
) {
1565 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1566 oob
+= chip
->ecc
.prepad
;
1569 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1570 chip
->read_buf(mtd
, oob
, eccbytes
);
1571 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1575 if (chip
->ecc
.postpad
) {
1576 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1577 oob
+= chip
->ecc
.postpad
;
1580 if (stat
== -EBADMSG
&&
1581 (chip
->ecc
.options
& NAND_ECC_GENERIC_ERASED_CHECK
)) {
1582 /* check for empty pages with bitflips */
1583 stat
= nand_check_erased_ecc_chunk(p
, chip
->ecc
.size
,
1587 chip
->ecc
.strength
);
1591 mtd
->ecc_stats
.failed
++;
1593 mtd
->ecc_stats
.corrected
+= stat
;
1594 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1598 /* Calculate remaining oob bytes */
1599 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1601 chip
->read_buf(mtd
, oob
, i
);
1603 return max_bitflips
;
1607 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1608 * @chip: nand chip structure
1609 * @oob: oob destination address
1610 * @ops: oob ops structure
1611 * @len: size of oob to transfer
1613 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1614 struct mtd_oob_ops
*ops
, size_t len
)
1616 switch (ops
->mode
) {
1618 case MTD_OPS_PLACE_OOB
:
1620 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1623 case MTD_OPS_AUTO_OOB
: {
1624 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1625 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1628 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1629 /* Read request not from offset 0? */
1630 if (unlikely(roffs
)) {
1631 if (roffs
>= free
->length
) {
1632 roffs
-= free
->length
;
1635 boffs
= free
->offset
+ roffs
;
1636 bytes
= min_t(size_t, len
,
1637 (free
->length
- roffs
));
1640 bytes
= min_t(size_t, len
, free
->length
);
1641 boffs
= free
->offset
;
1643 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1655 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1656 * @mtd: MTD device structure
1657 * @retry_mode: the retry mode to use
1659 * Some vendors supply a special command to shift the Vt threshold, to be used
1660 * when there are too many bitflips in a page (i.e., ECC error). After setting
1661 * a new threshold, the host should retry reading the page.
1663 static int nand_setup_read_retry(struct mtd_info
*mtd
, int retry_mode
)
1665 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1667 pr_debug("setting READ RETRY mode %d\n", retry_mode
);
1669 if (retry_mode
>= chip
->read_retries
)
1672 if (!chip
->setup_read_retry
)
1675 return chip
->setup_read_retry(mtd
, retry_mode
);
1679 * nand_do_read_ops - [INTERN] Read data with ECC
1680 * @mtd: MTD device structure
1681 * @from: offset to read from
1682 * @ops: oob ops structure
1684 * Internal function. Called with chip held.
1686 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1687 struct mtd_oob_ops
*ops
)
1689 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1690 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1692 uint32_t readlen
= ops
->len
;
1693 uint32_t oobreadlen
= ops
->ooblen
;
1694 uint32_t max_oobsize
= mtd_oobavail(mtd
, ops
);
1696 uint8_t *bufpoi
, *oob
, *buf
;
1698 unsigned int max_bitflips
= 0;
1700 bool ecc_fail
= false;
1702 chipnr
= (int)(from
>> chip
->chip_shift
);
1703 chip
->select_chip(mtd
, chipnr
);
1705 realpage
= (int)(from
>> chip
->page_shift
);
1706 page
= realpage
& chip
->pagemask
;
1708 col
= (int)(from
& (mtd
->writesize
- 1));
1712 oob_required
= oob
? 1 : 0;
1715 unsigned int ecc_failures
= mtd
->ecc_stats
.failed
;
1718 bytes
= min(mtd
->writesize
- col
, readlen
);
1719 aligned
= (bytes
== mtd
->writesize
);
1726 /* Is the current page in the buffer? */
1727 if (realpage
!= chip
->pagebuf
|| oob
) {
1728 bufpoi
= use_bufpoi
? chip
->buffers
->databuf
: buf
;
1730 if (use_bufpoi
&& aligned
)
1731 pr_debug("%s: using read bounce buffer for buf@%p\n",
1735 if (nand_standard_page_accessors(&chip
->ecc
))
1736 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1739 * Now read the page into the buffer. Absent an error,
1740 * the read methods return max bitflips per ecc step.
1742 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1743 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1746 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1748 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1752 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1753 oob_required
, page
);
1756 /* Invalidate page cache */
1761 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1763 /* Transfer not aligned data */
1765 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1766 !(mtd
->ecc_stats
.failed
- ecc_failures
) &&
1767 (ops
->mode
!= MTD_OPS_RAW
)) {
1768 chip
->pagebuf
= realpage
;
1769 chip
->pagebuf_bitflips
= ret
;
1771 /* Invalidate page cache */
1774 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1777 if (unlikely(oob
)) {
1778 int toread
= min(oobreadlen
, max_oobsize
);
1781 oob
= nand_transfer_oob(chip
,
1783 oobreadlen
-= toread
;
1787 if (chip
->options
& NAND_NEED_READRDY
) {
1788 /* Apply delay or wait for ready/busy pin */
1789 if (!chip
->dev_ready
)
1790 udelay(chip
->chip_delay
);
1792 nand_wait_ready(mtd
);
1795 if (mtd
->ecc_stats
.failed
- ecc_failures
) {
1796 if (retry_mode
+ 1 < chip
->read_retries
) {
1798 ret
= nand_setup_read_retry(mtd
,
1803 /* Reset failures; retry */
1804 mtd
->ecc_stats
.failed
= ecc_failures
;
1807 /* No more retry modes; real failure */
1814 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1816 max_bitflips
= max_t(unsigned int, max_bitflips
,
1817 chip
->pagebuf_bitflips
);
1822 /* Reset to retry mode 0 */
1824 ret
= nand_setup_read_retry(mtd
, 0);
1833 /* For subsequent reads align to page boundary */
1835 /* Increment page address */
1838 page
= realpage
& chip
->pagemask
;
1839 /* Check, if we cross a chip boundary */
1842 chip
->select_chip(mtd
, -1);
1843 chip
->select_chip(mtd
, chipnr
);
1846 chip
->select_chip(mtd
, -1);
1848 ops
->retlen
= ops
->len
- (size_t) readlen
;
1850 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1858 return max_bitflips
;
1862 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1863 * @mtd: MTD device structure
1864 * @from: offset to read from
1865 * @len: number of bytes to read
1866 * @retlen: pointer to variable to store the number of read bytes
1867 * @buf: the databuffer to put data
1869 * Get hold of the chip and call nand_do_read.
1871 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1872 size_t *retlen
, uint8_t *buf
)
1874 struct mtd_oob_ops ops
;
1877 nand_get_device(mtd
, FL_READING
);
1878 memset(&ops
, 0, sizeof(ops
));
1881 ops
.mode
= MTD_OPS_PLACE_OOB
;
1882 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1883 *retlen
= ops
.retlen
;
1884 nand_release_device(mtd
);
1889 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1890 * @mtd: mtd info structure
1891 * @chip: nand chip info structure
1892 * @page: page number to read
1894 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1897 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1898 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1903 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1905 * @mtd: mtd info structure
1906 * @chip: nand chip info structure
1907 * @page: page number to read
1909 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1912 int length
= mtd
->oobsize
;
1913 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1914 int eccsize
= chip
->ecc
.size
;
1915 uint8_t *bufpoi
= chip
->oob_poi
;
1916 int i
, toread
, sndrnd
= 0, pos
;
1918 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1919 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1921 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1922 if (mtd
->writesize
> 512)
1923 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1925 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1928 toread
= min_t(int, length
, chunk
);
1929 chip
->read_buf(mtd
, bufpoi
, toread
);
1934 chip
->read_buf(mtd
, bufpoi
, length
);
1940 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1941 * @mtd: mtd info structure
1942 * @chip: nand chip info structure
1943 * @page: page number to write
1945 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1949 const uint8_t *buf
= chip
->oob_poi
;
1950 int length
= mtd
->oobsize
;
1952 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1953 chip
->write_buf(mtd
, buf
, length
);
1954 /* Send command to program the OOB data */
1955 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1957 status
= chip
->waitfunc(mtd
, chip
);
1959 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1963 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1964 * with syndrome - only for large page flash
1965 * @mtd: mtd info structure
1966 * @chip: nand chip info structure
1967 * @page: page number to write
1969 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1970 struct nand_chip
*chip
, int page
)
1972 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1973 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1974 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1975 const uint8_t *bufpoi
= chip
->oob_poi
;
1978 * data-ecc-data-ecc ... ecc-oob
1980 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1982 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1983 pos
= steps
* (eccsize
+ chunk
);
1988 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1989 for (i
= 0; i
< steps
; i
++) {
1991 if (mtd
->writesize
<= 512) {
1992 uint32_t fill
= 0xFFFFFFFF;
1996 int num
= min_t(int, len
, 4);
1997 chip
->write_buf(mtd
, (uint8_t *)&fill
,
2002 pos
= eccsize
+ i
* (eccsize
+ chunk
);
2003 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
2007 len
= min_t(int, length
, chunk
);
2008 chip
->write_buf(mtd
, bufpoi
, len
);
2013 chip
->write_buf(mtd
, bufpoi
, length
);
2015 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2016 status
= chip
->waitfunc(mtd
, chip
);
2018 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
2022 * nand_do_read_oob - [INTERN] NAND read out-of-band
2023 * @mtd: MTD device structure
2024 * @from: offset to read from
2025 * @ops: oob operations description structure
2027 * NAND read out-of-band data from the spare area.
2029 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
2030 struct mtd_oob_ops
*ops
)
2032 int page
, realpage
, chipnr
;
2033 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2034 struct mtd_ecc_stats stats
;
2035 int readlen
= ops
->ooblen
;
2037 uint8_t *buf
= ops
->oobbuf
;
2040 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2041 __func__
, (unsigned long long)from
, readlen
);
2043 stats
= mtd
->ecc_stats
;
2045 len
= mtd_oobavail(mtd
, ops
);
2047 if (unlikely(ops
->ooboffs
>= len
)) {
2048 pr_debug("%s: attempt to start read outside oob\n",
2053 /* Do not allow reads past end of device */
2054 if (unlikely(from
>= mtd
->size
||
2055 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
2056 (from
>> chip
->page_shift
)) * len
)) {
2057 pr_debug("%s: attempt to read beyond end of device\n",
2062 chipnr
= (int)(from
>> chip
->chip_shift
);
2063 chip
->select_chip(mtd
, chipnr
);
2065 /* Shift to get page */
2066 realpage
= (int)(from
>> chip
->page_shift
);
2067 page
= realpage
& chip
->pagemask
;
2072 if (ops
->mode
== MTD_OPS_RAW
)
2073 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
2075 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
2080 len
= min(len
, readlen
);
2081 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
2083 if (chip
->options
& NAND_NEED_READRDY
) {
2084 /* Apply delay or wait for ready/busy pin */
2085 if (!chip
->dev_ready
)
2086 udelay(chip
->chip_delay
);
2088 nand_wait_ready(mtd
);
2095 /* Increment page address */
2098 page
= realpage
& chip
->pagemask
;
2099 /* Check, if we cross a chip boundary */
2102 chip
->select_chip(mtd
, -1);
2103 chip
->select_chip(mtd
, chipnr
);
2106 chip
->select_chip(mtd
, -1);
2108 ops
->oobretlen
= ops
->ooblen
- readlen
;
2113 if (mtd
->ecc_stats
.failed
- stats
.failed
)
2116 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
2120 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2121 * @mtd: MTD device structure
2122 * @from: offset to read from
2123 * @ops: oob operation description structure
2125 * NAND read data and/or out-of-band data.
2127 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
2128 struct mtd_oob_ops
*ops
)
2130 int ret
= -ENOTSUPP
;
2134 /* Do not allow reads past end of device */
2135 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
2136 pr_debug("%s: attempt to read beyond end of device\n",
2141 nand_get_device(mtd
, FL_READING
);
2143 switch (ops
->mode
) {
2144 case MTD_OPS_PLACE_OOB
:
2145 case MTD_OPS_AUTO_OOB
:
2154 ret
= nand_do_read_oob(mtd
, from
, ops
);
2156 ret
= nand_do_read_ops(mtd
, from
, ops
);
2159 nand_release_device(mtd
);
2165 * nand_write_page_raw - [INTERN] raw page write function
2166 * @mtd: mtd info structure
2167 * @chip: nand chip info structure
2169 * @oob_required: must write chip->oob_poi to OOB
2170 * @page: page number to write
2172 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2174 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2175 const uint8_t *buf
, int oob_required
, int page
)
2177 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
2179 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2185 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2186 * @mtd: mtd info structure
2187 * @chip: nand chip info structure
2189 * @oob_required: must write chip->oob_poi to OOB
2190 * @page: page number to write
2192 * We need a special oob layout and handling even when ECC isn't checked.
2194 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
2195 struct nand_chip
*chip
,
2196 const uint8_t *buf
, int oob_required
,
2199 int eccsize
= chip
->ecc
.size
;
2200 int eccbytes
= chip
->ecc
.bytes
;
2201 uint8_t *oob
= chip
->oob_poi
;
2204 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
2205 chip
->write_buf(mtd
, buf
, eccsize
);
2208 if (chip
->ecc
.prepad
) {
2209 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2210 oob
+= chip
->ecc
.prepad
;
2213 chip
->write_buf(mtd
, oob
, eccbytes
);
2216 if (chip
->ecc
.postpad
) {
2217 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2218 oob
+= chip
->ecc
.postpad
;
2222 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2224 chip
->write_buf(mtd
, oob
, size
);
2229 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2230 * @mtd: mtd info structure
2231 * @chip: nand chip info structure
2233 * @oob_required: must write chip->oob_poi to OOB
2234 * @page: page number to write
2236 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2237 const uint8_t *buf
, int oob_required
,
2240 int i
, eccsize
= chip
->ecc
.size
;
2241 int eccbytes
= chip
->ecc
.bytes
;
2242 int eccsteps
= chip
->ecc
.steps
;
2243 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2244 const uint8_t *p
= buf
;
2245 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2247 /* Software ECC calculation */
2248 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
2249 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2251 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2252 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2254 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1, page
);
2258 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2259 * @mtd: mtd info structure
2260 * @chip: nand chip info structure
2262 * @oob_required: must write chip->oob_poi to OOB
2263 * @page: page number to write
2265 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2266 const uint8_t *buf
, int oob_required
,
2269 int i
, eccsize
= chip
->ecc
.size
;
2270 int eccbytes
= chip
->ecc
.bytes
;
2271 int eccsteps
= chip
->ecc
.steps
;
2272 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2273 const uint8_t *p
= buf
;
2274 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2276 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2277 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2278 chip
->write_buf(mtd
, p
, eccsize
);
2279 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
2282 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2283 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2285 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2292 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2293 * @mtd: mtd info structure
2294 * @chip: nand chip info structure
2295 * @offset: column address of subpage within the page
2296 * @data_len: data length
2298 * @oob_required: must write chip->oob_poi to OOB
2299 * @page: page number to write
2301 static int nand_write_subpage_hwecc(struct mtd_info
*mtd
,
2302 struct nand_chip
*chip
, uint32_t offset
,
2303 uint32_t data_len
, const uint8_t *buf
,
2304 int oob_required
, int page
)
2306 uint8_t *oob_buf
= chip
->oob_poi
;
2307 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
2308 int ecc_size
= chip
->ecc
.size
;
2309 int ecc_bytes
= chip
->ecc
.bytes
;
2310 int ecc_steps
= chip
->ecc
.steps
;
2311 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
2312 uint32_t start_step
= offset
/ ecc_size
;
2313 uint32_t end_step
= (offset
+ data_len
- 1) / ecc_size
;
2314 int oob_bytes
= mtd
->oobsize
/ ecc_steps
;
2317 for (step
= 0; step
< ecc_steps
; step
++) {
2318 /* configure controller for WRITE access */
2319 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2321 /* write data (untouched subpages already masked by 0xFF) */
2322 chip
->write_buf(mtd
, buf
, ecc_size
);
2324 /* mask ECC of un-touched subpages by padding 0xFF */
2325 if ((step
< start_step
) || (step
> end_step
))
2326 memset(ecc_calc
, 0xff, ecc_bytes
);
2328 chip
->ecc
.calculate(mtd
, buf
, ecc_calc
);
2330 /* mask OOB of un-touched subpages by padding 0xFF */
2331 /* if oob_required, preserve OOB metadata of written subpage */
2332 if (!oob_required
|| (step
< start_step
) || (step
> end_step
))
2333 memset(oob_buf
, 0xff, oob_bytes
);
2336 ecc_calc
+= ecc_bytes
;
2337 oob_buf
+= oob_bytes
;
2340 /* copy calculated ECC for whole page to chip->buffer->oob */
2341 /* this include masked-value(0xFF) for unwritten subpages */
2342 ecc_calc
= chip
->buffers
->ecccalc
;
2343 for (i
= 0; i
< chip
->ecc
.total
; i
++)
2344 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
2346 /* write OOB buffer to NAND device */
2347 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
2354 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2355 * @mtd: mtd info structure
2356 * @chip: nand chip info structure
2358 * @oob_required: must write chip->oob_poi to OOB
2359 * @page: page number to write
2361 * The hw generator calculates the error syndrome automatically. Therefore we
2362 * need a special oob layout and handling.
2364 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
2365 struct nand_chip
*chip
,
2366 const uint8_t *buf
, int oob_required
,
2369 int i
, eccsize
= chip
->ecc
.size
;
2370 int eccbytes
= chip
->ecc
.bytes
;
2371 int eccsteps
= chip
->ecc
.steps
;
2372 const uint8_t *p
= buf
;
2373 uint8_t *oob
= chip
->oob_poi
;
2375 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2377 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2378 chip
->write_buf(mtd
, p
, eccsize
);
2380 if (chip
->ecc
.prepad
) {
2381 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2382 oob
+= chip
->ecc
.prepad
;
2385 chip
->ecc
.calculate(mtd
, p
, oob
);
2386 chip
->write_buf(mtd
, oob
, eccbytes
);
2389 if (chip
->ecc
.postpad
) {
2390 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2391 oob
+= chip
->ecc
.postpad
;
2395 /* Calculate remaining oob bytes */
2396 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2398 chip
->write_buf(mtd
, oob
, i
);
2404 * nand_write_page - [REPLACEABLE] write one page
2405 * @mtd: MTD device structure
2406 * @chip: NAND chip descriptor
2407 * @offset: address offset within the page
2408 * @data_len: length of actual data to be written
2409 * @buf: the data to write
2410 * @oob_required: must write chip->oob_poi to OOB
2411 * @page: page number to write
2412 * @cached: cached programming
2413 * @raw: use _raw version of write_page
2415 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2416 uint32_t offset
, int data_len
, const uint8_t *buf
,
2417 int oob_required
, int page
, int cached
, int raw
)
2419 int status
, subpage
;
2421 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
2422 chip
->ecc
.write_subpage
)
2423 subpage
= offset
|| (data_len
< mtd
->writesize
);
2427 if (nand_standard_page_accessors(&chip
->ecc
))
2428 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2431 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
,
2432 oob_required
, page
);
2434 status
= chip
->ecc
.write_subpage(mtd
, chip
, offset
, data_len
,
2435 buf
, oob_required
, page
);
2437 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2444 * Cached progamming disabled for now. Not sure if it's worth the
2445 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2449 if (!cached
|| !NAND_HAS_CACHEPROG(chip
)) {
2451 if (nand_standard_page_accessors(&chip
->ecc
))
2452 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2453 status
= chip
->waitfunc(mtd
, chip
);
2455 * See if operation failed and additional status checks are
2458 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2459 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2462 if (status
& NAND_STATUS_FAIL
)
2465 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2466 status
= chip
->waitfunc(mtd
, chip
);
2473 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2474 * @mtd: MTD device structure
2475 * @oob: oob data buffer
2476 * @len: oob data write length
2477 * @ops: oob ops structure
2479 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2480 struct mtd_oob_ops
*ops
)
2482 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2485 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2486 * data from a previous OOB read.
2488 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2490 switch (ops
->mode
) {
2492 case MTD_OPS_PLACE_OOB
:
2494 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2497 case MTD_OPS_AUTO_OOB
: {
2498 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2499 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2502 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2503 /* Write request not from offset 0? */
2504 if (unlikely(woffs
)) {
2505 if (woffs
>= free
->length
) {
2506 woffs
-= free
->length
;
2509 boffs
= free
->offset
+ woffs
;
2510 bytes
= min_t(size_t, len
,
2511 (free
->length
- woffs
));
2514 bytes
= min_t(size_t, len
, free
->length
);
2515 boffs
= free
->offset
;
2517 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2528 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2531 * nand_do_write_ops - [INTERN] NAND write with ECC
2532 * @mtd: MTD device structure
2533 * @to: offset to write to
2534 * @ops: oob operations description structure
2536 * NAND write with ECC.
2538 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2539 struct mtd_oob_ops
*ops
)
2541 int chipnr
, realpage
, page
, blockmask
, column
;
2542 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2543 uint32_t writelen
= ops
->len
;
2545 uint32_t oobwritelen
= ops
->ooblen
;
2546 uint32_t oobmaxlen
= mtd_oobavail(mtd
, ops
);
2548 uint8_t *oob
= ops
->oobbuf
;
2549 uint8_t *buf
= ops
->datbuf
;
2551 int oob_required
= oob
? 1 : 0;
2557 /* Reject writes, which are not page aligned */
2558 if (NOTALIGNED(to
)) {
2559 pr_notice("%s: attempt to write non page aligned data\n",
2564 column
= to
& (mtd
->writesize
- 1);
2566 chipnr
= (int)(to
>> chip
->chip_shift
);
2567 chip
->select_chip(mtd
, chipnr
);
2569 /* Check, if it is write protected */
2570 if (nand_check_wp(mtd
)) {
2575 realpage
= (int)(to
>> chip
->page_shift
);
2576 page
= realpage
& chip
->pagemask
;
2577 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2579 /* Invalidate the page cache, when we write to the cached page */
2580 if (to
<= ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) &&
2581 ((loff_t
)chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2584 /* Don't allow multipage oob writes with offset */
2585 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
)) {
2591 int bytes
= mtd
->writesize
;
2592 int cached
= writelen
> bytes
&& page
!= blockmask
;
2593 uint8_t *wbuf
= buf
;
2595 int part_pagewr
= (column
|| writelen
< mtd
->writesize
);
2603 /* Partial page write?, or need to use bounce buffer */
2605 pr_debug("%s: using write bounce buffer for buf@%p\n",
2609 bytes
= min_t(int, bytes
- column
, writelen
);
2611 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2612 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2613 wbuf
= chip
->buffers
->databuf
;
2616 if (unlikely(oob
)) {
2617 size_t len
= min(oobwritelen
, oobmaxlen
);
2618 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2621 /* We still need to erase leftover OOB data */
2622 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2624 ret
= chip
->write_page(mtd
, chip
, column
, bytes
, wbuf
,
2625 oob_required
, page
, cached
,
2626 (ops
->mode
== MTD_OPS_RAW
));
2638 page
= realpage
& chip
->pagemask
;
2639 /* Check, if we cross a chip boundary */
2642 chip
->select_chip(mtd
, -1);
2643 chip
->select_chip(mtd
, chipnr
);
2647 ops
->retlen
= ops
->len
- writelen
;
2649 ops
->oobretlen
= ops
->ooblen
;
2652 chip
->select_chip(mtd
, -1);
2657 * panic_nand_write - [MTD Interface] NAND write with ECC
2658 * @mtd: MTD device structure
2659 * @to: offset to write to
2660 * @len: number of bytes to write
2661 * @retlen: pointer to variable to store the number of written bytes
2662 * @buf: the data to write
2664 * NAND write with ECC. Used when performing writes in interrupt context, this
2665 * may for example be called by mtdoops when writing an oops while in panic.
2667 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2668 size_t *retlen
, const uint8_t *buf
)
2670 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2671 struct mtd_oob_ops ops
;
2674 /* Wait for the device to get ready */
2675 panic_nand_wait(mtd
, chip
, 400);
2677 /* Grab the device */
2678 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2680 memset(&ops
, 0, sizeof(ops
));
2682 ops
.datbuf
= (uint8_t *)buf
;
2683 ops
.mode
= MTD_OPS_PLACE_OOB
;
2685 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2687 *retlen
= ops
.retlen
;
2692 * nand_write - [MTD Interface] NAND write with ECC
2693 * @mtd: MTD device structure
2694 * @to: offset to write to
2695 * @len: number of bytes to write
2696 * @retlen: pointer to variable to store the number of written bytes
2697 * @buf: the data to write
2699 * NAND write with ECC.
2701 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2702 size_t *retlen
, const uint8_t *buf
)
2704 struct mtd_oob_ops ops
;
2707 nand_get_device(mtd
, FL_WRITING
);
2708 memset(&ops
, 0, sizeof(ops
));
2710 ops
.datbuf
= (uint8_t *)buf
;
2711 ops
.mode
= MTD_OPS_PLACE_OOB
;
2712 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2713 *retlen
= ops
.retlen
;
2714 nand_release_device(mtd
);
2719 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2720 * @mtd: MTD device structure
2721 * @to: offset to write to
2722 * @ops: oob operation description structure
2724 * NAND write out-of-band.
2726 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2727 struct mtd_oob_ops
*ops
)
2729 int chipnr
, page
, status
, len
;
2730 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2732 pr_debug("%s: to = 0x%08x, len = %i\n",
2733 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2735 len
= mtd_oobavail(mtd
, ops
);
2737 /* Do not allow write past end of page */
2738 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2739 pr_debug("%s: attempt to write past end of page\n",
2744 if (unlikely(ops
->ooboffs
>= len
)) {
2745 pr_debug("%s: attempt to start write outside oob\n",
2750 /* Do not allow write past end of device */
2751 if (unlikely(to
>= mtd
->size
||
2752 ops
->ooboffs
+ ops
->ooblen
>
2753 ((mtd
->size
>> chip
->page_shift
) -
2754 (to
>> chip
->page_shift
)) * len
)) {
2755 pr_debug("%s: attempt to write beyond end of device\n",
2760 chipnr
= (int)(to
>> chip
->chip_shift
);
2763 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2764 * of my DiskOnChip 2000 test units) will clear the whole data page too
2765 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2766 * it in the doc2000 driver in August 1999. dwmw2.
2768 nand_reset(chip
, chipnr
);
2770 chip
->select_chip(mtd
, chipnr
);
2772 /* Shift to get page */
2773 page
= (int)(to
>> chip
->page_shift
);
2775 /* Check, if it is write protected */
2776 if (nand_check_wp(mtd
)) {
2777 chip
->select_chip(mtd
, -1);
2781 /* Invalidate the page cache, if we write to the cached page */
2782 if (page
== chip
->pagebuf
)
2785 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2787 if (ops
->mode
== MTD_OPS_RAW
)
2788 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2790 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2792 chip
->select_chip(mtd
, -1);
2797 ops
->oobretlen
= ops
->ooblen
;
2803 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2804 * @mtd: MTD device structure
2805 * @to: offset to write to
2806 * @ops: oob operation description structure
2808 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2809 struct mtd_oob_ops
*ops
)
2811 int ret
= -ENOTSUPP
;
2815 /* Do not allow writes past end of device */
2816 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2817 pr_debug("%s: attempt to write beyond end of device\n",
2822 nand_get_device(mtd
, FL_WRITING
);
2824 switch (ops
->mode
) {
2825 case MTD_OPS_PLACE_OOB
:
2826 case MTD_OPS_AUTO_OOB
:
2835 ret
= nand_do_write_oob(mtd
, to
, ops
);
2837 ret
= nand_do_write_ops(mtd
, to
, ops
);
2840 nand_release_device(mtd
);
2845 * single_erase - [GENERIC] NAND standard block erase command function
2846 * @mtd: MTD device structure
2847 * @page: the page address of the block which will be erased
2849 * Standard erase command for NAND chips. Returns NAND status.
2851 static int single_erase(struct mtd_info
*mtd
, int page
)
2853 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2854 /* Send commands to erase a block */
2855 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2856 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2858 return chip
->waitfunc(mtd
, chip
);
2862 * nand_erase - [MTD Interface] erase block(s)
2863 * @mtd: MTD device structure
2864 * @instr: erase instruction
2866 * Erase one ore more blocks.
2868 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2870 return nand_erase_nand(mtd
, instr
, 0);
2874 * nand_erase_nand - [INTERN] erase block(s)
2875 * @mtd: MTD device structure
2876 * @instr: erase instruction
2877 * @allowbbt: allow erasing the bbt area
2879 * Erase one ore more blocks.
2881 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2884 int page
, status
, pages_per_block
, ret
, chipnr
;
2885 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2888 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2889 __func__
, (unsigned long long)instr
->addr
,
2890 (unsigned long long)instr
->len
);
2892 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2895 /* Grab the lock and see if the device is available */
2896 nand_get_device(mtd
, FL_ERASING
);
2898 /* Shift to get first page */
2899 page
= (int)(instr
->addr
>> chip
->page_shift
);
2900 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2902 /* Calculate pages in each block */
2903 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2905 /* Select the NAND device */
2906 chip
->select_chip(mtd
, chipnr
);
2908 /* Check, if it is write protected */
2909 if (nand_check_wp(mtd
)) {
2910 pr_debug("%s: device is write protected!\n",
2912 instr
->state
= MTD_ERASE_FAILED
;
2916 /* Loop through the pages */
2919 instr
->state
= MTD_ERASING
;
2924 /* Check if we have a bad block, we do not erase bad blocks! */
2925 if (!instr
->scrub
&& nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2926 chip
->page_shift
, allowbbt
)) {
2927 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2929 instr
->state
= MTD_ERASE_FAILED
;
2934 * Invalidate the page cache, if we erase the block which
2935 * contains the current cached page.
2937 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2938 (page
+ pages_per_block
))
2941 status
= chip
->erase(mtd
, page
& chip
->pagemask
);
2944 * See if operation failed and additional status checks are
2947 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2948 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2951 /* See if block erase succeeded */
2952 if (status
& NAND_STATUS_FAIL
) {
2953 pr_debug("%s: failed erase, page 0x%08x\n",
2955 instr
->state
= MTD_ERASE_FAILED
;
2957 ((loff_t
)page
<< chip
->page_shift
);
2961 /* Increment page address and decrement length */
2962 len
-= (1ULL << chip
->phys_erase_shift
);
2963 page
+= pages_per_block
;
2965 /* Check, if we cross a chip boundary */
2966 if (len
&& !(page
& chip
->pagemask
)) {
2968 chip
->select_chip(mtd
, -1);
2969 chip
->select_chip(mtd
, chipnr
);
2972 instr
->state
= MTD_ERASE_DONE
;
2976 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2978 /* Deselect and wake up anyone waiting on the device */
2979 chip
->select_chip(mtd
, -1);
2980 nand_release_device(mtd
);
2982 /* Do call back function */
2984 mtd_erase_callback(instr
);
2986 /* Return more or less happy */
2991 * nand_sync - [MTD Interface] sync
2992 * @mtd: MTD device structure
2994 * Sync is actually a wait for chip ready function.
2996 static void nand_sync(struct mtd_info
*mtd
)
2998 pr_debug("%s: called\n", __func__
);
3000 /* Grab the lock and see if the device is available */
3001 nand_get_device(mtd
, FL_SYNCING
);
3002 /* Release it and go back */
3003 nand_release_device(mtd
);
3007 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3008 * @mtd: MTD device structure
3009 * @offs: offset relative to mtd start
3011 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
3013 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3014 int chipnr
= (int)(offs
>> chip
->chip_shift
);
3017 /* Select the NAND device */
3018 nand_get_device(mtd
, FL_READING
);
3019 chip
->select_chip(mtd
, chipnr
);
3021 ret
= nand_block_checkbad(mtd
, offs
, 0);
3023 chip
->select_chip(mtd
, -1);
3024 nand_release_device(mtd
);
3030 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3031 * @mtd: MTD device structure
3032 * @ofs: offset relative to mtd start
3034 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
3038 ret
= nand_block_isbad(mtd
, ofs
);
3040 /* If it was bad already, return success and do nothing */
3046 return nand_block_markbad_lowlevel(mtd
, ofs
);
3050 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3051 * @mtd: MTD device structure
3052 * @chip: nand chip info structure
3053 * @addr: feature address.
3054 * @subfeature_param: the subfeature parameters, a four bytes array.
3056 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3057 int addr
, uint8_t *subfeature_param
)
3062 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3063 if (!chip
->onfi_version
||
3064 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3065 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3069 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
3070 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3071 chip
->write_byte(mtd
, subfeature_param
[i
]);
3073 status
= chip
->waitfunc(mtd
, chip
);
3074 if (status
& NAND_STATUS_FAIL
)
3080 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3081 * @mtd: MTD device structure
3082 * @chip: nand chip info structure
3083 * @addr: feature address.
3084 * @subfeature_param: the subfeature parameters, a four bytes array.
3086 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3087 int addr
, uint8_t *subfeature_param
)
3091 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3092 if (!chip
->onfi_version
||
3093 !(le16_to_cpu(chip
->onfi_params
.opt_cmd
)
3094 & ONFI_OPT_CMD_SET_GET_FEATURES
))
3098 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
3099 for (i
= 0; i
< ONFI_SUBFEATURE_PARAM_LEN
; ++i
)
3100 *subfeature_param
++ = chip
->read_byte(mtd
);
3104 /* Set default functions */
3105 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
3107 /* check for proper chip_delay setup, set 20us if not */
3108 if (!chip
->chip_delay
)
3109 chip
->chip_delay
= 20;
3111 /* check, if a user supplied command function given */
3112 if (chip
->cmdfunc
== NULL
)
3113 chip
->cmdfunc
= nand_command
;
3115 /* check, if a user supplied wait function given */
3116 if (chip
->waitfunc
== NULL
)
3117 chip
->waitfunc
= nand_wait
;
3119 if (!chip
->select_chip
)
3120 chip
->select_chip
= nand_select_chip
;
3122 /* set for ONFI nand */
3123 if (!chip
->onfi_set_features
)
3124 chip
->onfi_set_features
= nand_onfi_set_features
;
3125 if (!chip
->onfi_get_features
)
3126 chip
->onfi_get_features
= nand_onfi_get_features
;
3128 /* If called twice, pointers that depend on busw may need to be reset */
3129 if (!chip
->read_byte
|| chip
->read_byte
== nand_read_byte
)
3130 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
3131 if (!chip
->read_word
)
3132 chip
->read_word
= nand_read_word
;
3133 if (!chip
->block_bad
)
3134 chip
->block_bad
= nand_block_bad
;
3135 if (!chip
->block_markbad
)
3136 chip
->block_markbad
= nand_default_block_markbad
;
3137 if (!chip
->write_buf
|| chip
->write_buf
== nand_write_buf
)
3138 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
3139 if (!chip
->write_byte
|| chip
->write_byte
== nand_write_byte
)
3140 chip
->write_byte
= busw
? nand_write_byte16
: nand_write_byte
;
3141 if (!chip
->read_buf
|| chip
->read_buf
== nand_read_buf
)
3142 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
3143 if (!chip
->scan_bbt
)
3144 chip
->scan_bbt
= nand_default_bbt
;
3146 if (!chip
->controller
) {
3147 chip
->controller
= &chip
->hwcontrol
;
3148 spin_lock_init(&chip
->controller
->lock
);
3149 init_waitqueue_head(&chip
->controller
->wq
);
3154 /* Sanitize ONFI strings so we can safely print them */
3155 static void sanitize_string(char *s
, size_t len
)
3159 /* Null terminate */
3162 /* Remove non printable chars */
3163 for (i
= 0; i
< len
- 1; i
++) {
3164 if (s
[i
] < ' ' || s
[i
] > 127)
3168 /* Remove trailing spaces */
3172 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
3177 for (i
= 0; i
< 8; i
++)
3178 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
3184 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3185 /* Parse the Extended Parameter Page. */
3186 static int nand_flash_detect_ext_param_page(struct mtd_info
*mtd
,
3187 struct nand_chip
*chip
, struct nand_onfi_params
*p
)
3189 struct onfi_ext_param_page
*ep
;
3190 struct onfi_ext_section
*s
;
3191 struct onfi_ext_ecc_info
*ecc
;
3197 len
= le16_to_cpu(p
->ext_param_page_length
) * 16;
3198 ep
= kmalloc(len
, GFP_KERNEL
);
3202 /* Send our own NAND_CMD_PARAM. */
3203 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3205 /* Use the Change Read Column command to skip the ONFI param pages. */
3206 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
3207 sizeof(*p
) * p
->num_of_param_pages
, -1);
3209 /* Read out the Extended Parameter Page. */
3210 chip
->read_buf(mtd
, (uint8_t *)ep
, len
);
3211 if ((onfi_crc16(ONFI_CRC_BASE
, ((uint8_t *)ep
) + 2, len
- 2)
3212 != le16_to_cpu(ep
->crc
))) {
3213 pr_debug("fail in the CRC.\n");
3218 * Check the signature.
3219 * Do not strictly follow the ONFI spec, maybe changed in future.
3221 if (strncmp((char *)ep
->sig
, "EPPS", 4)) {
3222 pr_debug("The signature is invalid.\n");
3226 /* find the ECC section. */
3227 cursor
= (uint8_t *)(ep
+ 1);
3228 for (i
= 0; i
< ONFI_EXT_SECTION_MAX
; i
++) {
3229 s
= ep
->sections
+ i
;
3230 if (s
->type
== ONFI_SECTION_TYPE_2
)
3232 cursor
+= s
->length
* 16;
3234 if (i
== ONFI_EXT_SECTION_MAX
) {
3235 pr_debug("We can not find the ECC section.\n");
3239 /* get the info we want. */
3240 ecc
= (struct onfi_ext_ecc_info
*)cursor
;
3242 if (!ecc
->codeword_size
) {
3243 pr_debug("Invalid codeword size\n");
3247 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3248 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3256 static int nand_setup_read_retry_micron(struct mtd_info
*mtd
, int retry_mode
)
3258 struct nand_chip
*chip
= mtd_to_nand(mtd
);
3259 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {retry_mode
};
3261 return chip
->onfi_set_features(mtd
, chip
, ONFI_FEATURE_ADDR_READ_RETRY
,
3266 * Configure chip properties from Micron vendor-specific ONFI table
3268 static void nand_onfi_detect_micron(struct nand_chip
*chip
,
3269 struct nand_onfi_params
*p
)
3271 struct nand_onfi_vendor_micron
*micron
= (void *)p
->vendor
;
3273 if (le16_to_cpu(p
->vendor_revision
) < 1)
3276 chip
->read_retries
= micron
->read_retry_options
;
3277 chip
->setup_read_retry
= nand_setup_read_retry_micron
;
3281 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3283 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3286 struct nand_onfi_params
*p
= &chip
->onfi_params
;
3290 /* Try ONFI for unknown chip or LP */
3291 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
3292 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
3293 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
3296 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
3297 for (i
= 0; i
< 3; i
++) {
3298 for (j
= 0; j
< sizeof(*p
); j
++)
3299 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3300 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
3301 le16_to_cpu(p
->crc
)) {
3307 pr_err("Could not find valid ONFI parameter page; aborting\n");
3312 val
= le16_to_cpu(p
->revision
);
3314 chip
->onfi_version
= 23;
3315 else if (val
& (1 << 4))
3316 chip
->onfi_version
= 22;
3317 else if (val
& (1 << 3))
3318 chip
->onfi_version
= 21;
3319 else if (val
& (1 << 2))
3320 chip
->onfi_version
= 20;
3321 else if (val
& (1 << 1))
3322 chip
->onfi_version
= 10;
3324 if (!chip
->onfi_version
) {
3325 pr_info("unsupported ONFI version: %d\n", val
);
3329 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3330 sanitize_string(p
->model
, sizeof(p
->model
));
3332 mtd
->name
= p
->model
;
3334 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3337 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3338 * (don't ask me who thought of this...). MTD assumes that these
3339 * dimensions will be power-of-2, so just truncate the remaining area.
3341 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3342 mtd
->erasesize
*= mtd
->writesize
;
3344 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3346 /* See erasesize comment */
3347 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3348 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3349 chip
->bits_per_cell
= p
->bits_per_cell
;
3351 if (onfi_feature(chip
) & ONFI_FEATURE_16_BIT_BUS
)
3352 *busw
= NAND_BUSWIDTH_16
;
3356 if (p
->ecc_bits
!= 0xff) {
3357 chip
->ecc_strength_ds
= p
->ecc_bits
;
3358 chip
->ecc_step_ds
= 512;
3359 } else if (chip
->onfi_version
>= 21 &&
3360 (onfi_feature(chip
) & ONFI_FEATURE_EXT_PARAM_PAGE
)) {
3363 * The nand_flash_detect_ext_param_page() uses the
3364 * Change Read Column command which maybe not supported
3365 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3366 * now. We do not replace user supplied command function.
3368 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3369 chip
->cmdfunc
= nand_command_lp
;
3371 /* The Extended Parameter Page is supported since ONFI 2.1. */
3372 if (nand_flash_detect_ext_param_page(mtd
, chip
, p
))
3373 pr_warn("Failed to detect ONFI extended param page\n");
3375 pr_warn("Could not retrieve ONFI ECC requirements\n");
3378 if (p
->jedec_id
== NAND_MFR_MICRON
)
3379 nand_onfi_detect_micron(chip
, p
);
3384 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3392 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3394 static int nand_flash_detect_jedec(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3397 struct nand_jedec_params
*p
= &chip
->jedec_params
;
3398 struct jedec_ecc_info
*ecc
;
3402 /* Try JEDEC for unknown chip or LP */
3403 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x40, -1);
3404 if (chip
->read_byte(mtd
) != 'J' || chip
->read_byte(mtd
) != 'E' ||
3405 chip
->read_byte(mtd
) != 'D' || chip
->read_byte(mtd
) != 'E' ||
3406 chip
->read_byte(mtd
) != 'C')
3409 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0x40, -1);
3410 for (i
= 0; i
< 3; i
++) {
3411 for (j
= 0; j
< sizeof(*p
); j
++)
3412 ((uint8_t *)p
)[j
] = chip
->read_byte(mtd
);
3414 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 510) ==
3415 le16_to_cpu(p
->crc
))
3420 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3425 val
= le16_to_cpu(p
->revision
);
3427 chip
->jedec_version
= 10;
3428 else if (val
& (1 << 1))
3429 chip
->jedec_version
= 1; /* vendor specific version */
3431 if (!chip
->jedec_version
) {
3432 pr_info("unsupported JEDEC version: %d\n", val
);
3436 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
3437 sanitize_string(p
->model
, sizeof(p
->model
));
3439 mtd
->name
= p
->model
;
3441 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
3443 /* Please reference to the comment for nand_flash_detect_onfi. */
3444 mtd
->erasesize
= 1 << (fls(le32_to_cpu(p
->pages_per_block
)) - 1);
3445 mtd
->erasesize
*= mtd
->writesize
;
3447 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
3449 /* Please reference to the comment for nand_flash_detect_onfi. */
3450 chip
->chipsize
= 1 << (fls(le32_to_cpu(p
->blocks_per_lun
)) - 1);
3451 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
3452 chip
->bits_per_cell
= p
->bits_per_cell
;
3454 if (jedec_feature(chip
) & JEDEC_FEATURE_16_BIT_BUS
)
3455 *busw
= NAND_BUSWIDTH_16
;
3460 ecc
= &p
->ecc_info
[0];
3462 if (ecc
->codeword_size
>= 9) {
3463 chip
->ecc_strength_ds
= ecc
->ecc_bits
;
3464 chip
->ecc_step_ds
= 1 << ecc
->codeword_size
;
3466 pr_warn("Invalid codeword size\n");
3473 * nand_id_has_period - Check if an ID string has a given wraparound period
3474 * @id_data: the ID string
3475 * @arrlen: the length of the @id_data array
3476 * @period: the period of repitition
3478 * Check if an ID string is repeated within a given sequence of bytes at
3479 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3480 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3481 * if the repetition has a period of @period; otherwise, returns zero.
3483 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
3486 for (i
= 0; i
< period
; i
++)
3487 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
3488 if (id_data
[i
] != id_data
[j
])
3494 * nand_id_len - Get the length of an ID string returned by CMD_READID
3495 * @id_data: the ID string
3496 * @arrlen: the length of the @id_data array
3498 * Returns the length of the ID string, according to known wraparound/trailing
3499 * zero patterns. If no pattern exists, returns the length of the array.
3501 static int nand_id_len(u8
*id_data
, int arrlen
)
3503 int last_nonzero
, period
;
3505 /* Find last non-zero byte */
3506 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
3507 if (id_data
[last_nonzero
])
3511 if (last_nonzero
< 0)
3514 /* Calculate wraparound period */
3515 for (period
= 1; period
< arrlen
; period
++)
3516 if (nand_id_has_period(id_data
, arrlen
, period
))
3519 /* There's a repeated pattern */
3520 if (period
< arrlen
)
3523 /* There are trailing zeros */
3524 if (last_nonzero
< arrlen
- 1)
3525 return last_nonzero
+ 1;
3527 /* No pattern detected */
3531 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3532 static int nand_get_bits_per_cell(u8 cellinfo
)
3536 bits
= cellinfo
& NAND_CI_CELLTYPE_MSK
;
3537 bits
>>= NAND_CI_CELLTYPE_SHIFT
;
3542 * Many new NAND share similar device ID codes, which represent the size of the
3543 * chip. The rest of the parameters must be decoded according to generic or
3544 * manufacturer-specific "extended ID" decoding patterns.
3546 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3547 u8 id_data
[8], int *busw
)
3550 /* The 3rd id byte holds MLC / multichip data */
3551 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3552 /* The 4th id byte is the important one */
3555 id_len
= nand_id_len(id_data
, 8);
3558 * Field definitions are in the following datasheets:
3559 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3560 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3561 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3563 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3564 * ID to decide what to do.
3566 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
3567 !nand_is_slc(chip
) && id_data
[5] != 0x00) {
3569 mtd
->writesize
= 2048 << (extid
& 0x03);
3572 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3592 default: /* Other cases are "reserved" (unknown) */
3593 mtd
->oobsize
= 1024;
3597 /* Calc blocksize */
3598 mtd
->erasesize
= (128 * 1024) <<
3599 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3601 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3602 !nand_is_slc(chip
)) {
3606 mtd
->writesize
= 2048 << (extid
& 0x03);
3609 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3633 /* Calc blocksize */
3634 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3636 mtd
->erasesize
= (128 * 1024) << tmp
;
3637 else if (tmp
== 0x03)
3638 mtd
->erasesize
= 768 * 1024;
3640 mtd
->erasesize
= (64 * 1024) << tmp
;
3644 mtd
->writesize
= 1024 << (extid
& 0x03);
3647 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3648 (mtd
->writesize
>> 9);
3650 /* Calc blocksize. Blocksize is multiples of 64KiB */
3651 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3653 /* Get buswidth information */
3654 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3657 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3658 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3660 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3662 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3664 if (id_len
>= 6 && id_data
[0] == NAND_MFR_TOSHIBA
&&
3665 nand_is_slc(chip
) &&
3666 (id_data
[5] & 0x7) == 0x6 /* 24nm */ &&
3667 !(id_data
[4] & 0x80) /* !BENAND */) {
3668 mtd
->oobsize
= 32 * mtd
->writesize
>> 9;
3675 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3676 * decodes a matching ID table entry and assigns the MTD size parameters for
3679 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3680 struct nand_flash_dev
*type
, u8 id_data
[8],
3683 int maf_id
= id_data
[0];
3685 mtd
->erasesize
= type
->erasesize
;
3686 mtd
->writesize
= type
->pagesize
;
3687 mtd
->oobsize
= mtd
->writesize
/ 32;
3688 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3690 /* All legacy ID NAND are small-page, SLC */
3691 chip
->bits_per_cell
= 1;
3694 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3695 * some Spansion chips have erasesize that conflicts with size
3696 * listed in nand_ids table.
3697 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3699 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3700 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3701 && mtd
->writesize
== 512) {
3702 mtd
->erasesize
= 128 * 1024;
3703 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3708 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3709 * heuristic patterns using various detected parameters (e.g., manufacturer,
3710 * page size, cell-type information).
3712 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3713 struct nand_chip
*chip
, u8 id_data
[8])
3715 int maf_id
= id_data
[0];
3717 /* Set the bad block position */
3718 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3719 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3721 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3724 * Bad block marker is stored in the last page of each block on Samsung
3725 * and Hynix MLC devices; stored in first two pages of each block on
3726 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3727 * AMD/Spansion, and Macronix. All others scan only the first page.
3729 if (!nand_is_slc(chip
) &&
3730 (maf_id
== NAND_MFR_SAMSUNG
||
3731 maf_id
== NAND_MFR_HYNIX
))
3732 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3733 else if ((nand_is_slc(chip
) &&
3734 (maf_id
== NAND_MFR_SAMSUNG
||
3735 maf_id
== NAND_MFR_HYNIX
||
3736 maf_id
== NAND_MFR_TOSHIBA
||
3737 maf_id
== NAND_MFR_AMD
||
3738 maf_id
== NAND_MFR_MACRONIX
)) ||
3739 (mtd
->writesize
== 2048 &&
3740 maf_id
== NAND_MFR_MICRON
))
3741 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3744 static inline bool is_full_id_nand(struct nand_flash_dev
*type
)
3746 return type
->id_len
;
3749 static bool find_full_id_nand(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3750 struct nand_flash_dev
*type
, u8
*id_data
, int *busw
)
3752 if (!strncmp((char *)type
->id
, (char *)id_data
, type
->id_len
)) {
3753 mtd
->writesize
= type
->pagesize
;
3754 mtd
->erasesize
= type
->erasesize
;
3755 mtd
->oobsize
= type
->oobsize
;
3757 chip
->bits_per_cell
= nand_get_bits_per_cell(id_data
[2]);
3758 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3759 chip
->options
|= type
->options
;
3760 chip
->ecc_strength_ds
= NAND_ECC_STRENGTH(type
);
3761 chip
->ecc_step_ds
= NAND_ECC_STEP(type
);
3762 chip
->onfi_timing_mode_default
=
3763 type
->onfi_timing_mode_default
;
3765 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3768 mtd
->name
= type
->name
;
3776 * Get the flash and manufacturer id and lookup if the type is supported.
3778 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3779 struct nand_chip
*chip
,
3780 int *maf_id
, int *dev_id
,
3781 struct nand_flash_dev
*type
)
3788 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3791 nand_reset(chip
, 0);
3793 /* Select the device */
3794 chip
->select_chip(mtd
, 0);
3796 /* Send the command for reading device ID */
3797 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3799 /* Read manufacturer and device IDs */
3800 *maf_id
= chip
->read_byte(mtd
);
3801 *dev_id
= chip
->read_byte(mtd
);
3804 * Try again to make sure, as some systems the bus-hold or other
3805 * interface concerns can cause random data which looks like a
3806 * possibly credible NAND flash to appear. If the two results do
3807 * not match, ignore the device completely.
3810 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3812 /* Read entire ID string */
3813 for (i
= 0; i
< 8; i
++)
3814 id_data
[i
] = chip
->read_byte(mtd
);
3816 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3817 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3818 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3819 return ERR_PTR(-ENODEV
);
3823 type
= nand_flash_ids
;
3825 for (; type
->name
!= NULL
; type
++) {
3826 if (is_full_id_nand(type
)) {
3827 if (find_full_id_nand(mtd
, chip
, type
, id_data
, &busw
))
3829 } else if (*dev_id
== type
->dev_id
) {
3834 chip
->onfi_version
= 0;
3835 if (!type
->name
|| !type
->pagesize
) {
3836 /* Check if the chip is ONFI compliant */
3837 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3840 /* Check if the chip is JEDEC compliant */
3841 if (nand_flash_detect_jedec(mtd
, chip
, &busw
))
3846 return ERR_PTR(-ENODEV
);
3849 mtd
->name
= type
->name
;
3851 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3853 if (!type
->pagesize
) {
3854 /* Decode parameters from extended ID */
3855 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3857 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3859 /* Get chip options */
3860 chip
->options
|= type
->options
;
3863 * Check if chip is not a Samsung device. Do not clear the
3864 * options for chips which do not have an extended id.
3866 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3867 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3870 /* Try to identify manufacturer */
3871 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3872 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3876 if (chip
->options
& NAND_BUSWIDTH_AUTO
) {
3877 WARN_ON(chip
->options
& NAND_BUSWIDTH_16
);
3878 chip
->options
|= busw
;
3879 nand_set_defaults(chip
, busw
);
3880 } else if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3882 * Check, if buswidth is correct. Hardware drivers should set
3885 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3887 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3888 pr_warn("bus width %d instead %d bit\n",
3889 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3891 return ERR_PTR(-EINVAL
);
3894 nand_decode_bbm_options(mtd
, chip
, id_data
);
3896 /* Calculate the address shift from the page size */
3897 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3898 /* Convert chipsize to number of pages per chip -1 */
3899 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3901 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3902 ffs(mtd
->erasesize
) - 1;
3903 if (chip
->chipsize
& 0xffffffff)
3904 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3906 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3907 chip
->chip_shift
+= 32 - 1;
3910 chip
->badblockbits
= 8;
3911 chip
->erase
= single_erase
;
3913 /* Do not replace user supplied command function! */
3914 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3915 chip
->cmdfunc
= nand_command_lp
;
3917 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3920 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3921 if (chip
->onfi_version
)
3922 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3923 chip
->onfi_params
.model
);
3924 else if (chip
->jedec_version
)
3925 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3926 chip
->jedec_params
.model
);
3928 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3931 if (chip
->jedec_version
)
3932 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3933 chip
->jedec_params
.model
);
3935 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3938 pr_info("%s %s\n", nand_manuf_ids
[maf_idx
].name
,
3942 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3943 (int)(chip
->chipsize
>> 20), nand_is_slc(chip
) ? "SLC" : "MLC",
3944 mtd
->erasesize
>> 10, mtd
->writesize
, mtd
->oobsize
);
3948 #if CONFIG_IS_ENABLED(OF_CONTROL)
3949 DECLARE_GLOBAL_DATA_PTR
;
3951 static int nand_dt_init(struct mtd_info
*mtd
, struct nand_chip
*chip
, int node
)
3953 int ret
, ecc_mode
= -1, ecc_strength
, ecc_step
;
3954 const void *blob
= gd
->fdt_blob
;
3957 ret
= fdtdec_get_int(blob
, node
, "nand-bus-width", -1);
3959 chip
->options
|= NAND_BUSWIDTH_16
;
3961 if (fdtdec_get_bool(blob
, node
, "nand-on-flash-bbt"))
3962 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
3964 str
= fdt_getprop(blob
, node
, "nand-ecc-mode", NULL
);
3966 if (!strcmp(str
, "none"))
3967 ecc_mode
= NAND_ECC_NONE
;
3968 else if (!strcmp(str
, "soft"))
3969 ecc_mode
= NAND_ECC_SOFT
;
3970 else if (!strcmp(str
, "hw"))
3971 ecc_mode
= NAND_ECC_HW
;
3972 else if (!strcmp(str
, "hw_syndrome"))
3973 ecc_mode
= NAND_ECC_HW_SYNDROME
;
3974 else if (!strcmp(str
, "hw_oob_first"))
3975 ecc_mode
= NAND_ECC_HW_OOB_FIRST
;
3976 else if (!strcmp(str
, "soft_bch"))
3977 ecc_mode
= NAND_ECC_SOFT_BCH
;
3981 ecc_strength
= fdtdec_get_int(blob
, node
, "nand-ecc-strength", -1);
3982 ecc_step
= fdtdec_get_int(blob
, node
, "nand-ecc-step-size", -1);
3984 if ((ecc_step
>= 0 && !(ecc_strength
>= 0)) ||
3985 (!(ecc_step
>= 0) && ecc_strength
>= 0)) {
3986 pr_err("must set both strength and step size in DT\n");
3991 chip
->ecc
.mode
= ecc_mode
;
3993 if (ecc_strength
>= 0)
3994 chip
->ecc
.strength
= ecc_strength
;
3997 chip
->ecc
.size
= ecc_step
;
3999 if (fdt_getprop(blob
, node
, "nand-ecc-maximize", NULL
))
4000 chip
->ecc
.options
|= NAND_ECC_MAXIMIZE
;
4005 static int nand_dt_init(struct mtd_info
*mtd
, struct nand_chip
*chip
, int node
)
4009 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
4012 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4013 * @mtd: MTD device structure
4014 * @maxchips: number of chips to scan for
4015 * @table: alternative NAND ID table
4017 * This is the first phase of the normal nand_scan() function. It reads the
4018 * flash ID and sets up MTD fields accordingly.
4021 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
4022 struct nand_flash_dev
*table
)
4024 int i
, nand_maf_id
, nand_dev_id
;
4025 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4026 struct nand_flash_dev
*type
;
4029 if (chip
->flash_node
) {
4030 ret
= nand_dt_init(mtd
, chip
, chip
->flash_node
);
4035 /* Set the default functions */
4036 nand_set_defaults(chip
, chip
->options
& NAND_BUSWIDTH_16
);
4038 /* Read the flash type */
4039 type
= nand_get_flash_type(mtd
, chip
, &nand_maf_id
,
4040 &nand_dev_id
, table
);
4043 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
4044 pr_warn("No NAND device found\n");
4045 chip
->select_chip(mtd
, -1);
4046 return PTR_ERR(type
);
4049 /* Initialize the ->data_interface field. */
4050 ret
= nand_init_data_interface(chip
);
4055 * Setup the data interface correctly on the chip and controller side.
4056 * This explicit call to nand_setup_data_interface() is only required
4057 * for the first die, because nand_reset() has been called before
4058 * ->data_interface and ->default_onfi_timing_mode were set.
4059 * For the other dies, nand_reset() will automatically switch to the
4062 ret
= nand_setup_data_interface(chip
);
4066 chip
->select_chip(mtd
, -1);
4068 /* Check for a chip array */
4069 for (i
= 1; i
< maxchips
; i
++) {
4070 /* See comment in nand_get_flash_type for reset */
4071 nand_reset(chip
, i
);
4073 chip
->select_chip(mtd
, i
);
4074 /* Send the command for reading device ID */
4075 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
4076 /* Read manufacturer and device IDs */
4077 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
4078 nand_dev_id
!= chip
->read_byte(mtd
)) {
4079 chip
->select_chip(mtd
, -1);
4082 chip
->select_chip(mtd
, -1);
4087 pr_info("%d chips detected\n", i
);
4090 /* Store the number of chips and calc total size for mtd */
4092 mtd
->size
= i
* chip
->chipsize
;
4096 EXPORT_SYMBOL(nand_scan_ident
);
4099 * Check if the chip configuration meet the datasheet requirements.
4101 * If our configuration corrects A bits per B bytes and the minimum
4102 * required correction level is X bits per Y bytes, then we must ensure
4103 * both of the following are true:
4105 * (1) A / B >= X / Y
4108 * Requirement (1) ensures we can correct for the required bitflip density.
4109 * Requirement (2) ensures we can correct even when all bitflips are clumped
4110 * in the same sector.
4112 static bool nand_ecc_strength_good(struct mtd_info
*mtd
)
4114 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4115 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4118 if (ecc
->size
== 0 || chip
->ecc_step_ds
== 0)
4119 /* Not enough information */
4123 * We get the number of corrected bits per page to compare
4124 * the correction density.
4126 corr
= (mtd
->writesize
* ecc
->strength
) / ecc
->size
;
4127 ds_corr
= (mtd
->writesize
* chip
->ecc_strength_ds
) / chip
->ecc_step_ds
;
4129 return corr
>= ds_corr
&& ecc
->strength
>= chip
->ecc_strength_ds
;
4132 static bool invalid_ecc_page_accessors(struct nand_chip
*chip
)
4134 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4136 if (nand_standard_page_accessors(ecc
))
4140 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4141 * controller driver implements all the page accessors because
4142 * default helpers are not suitable when the core does not
4143 * send the READ0/PAGEPROG commands.
4145 return (!ecc
->read_page
|| !ecc
->write_page
||
4146 !ecc
->read_page_raw
|| !ecc
->write_page_raw
||
4147 (NAND_HAS_SUBPAGE_READ(chip
) && !ecc
->read_subpage
) ||
4148 (NAND_HAS_SUBPAGE_WRITE(chip
) && !ecc
->write_subpage
&&
4149 ecc
->hwctl
&& ecc
->calculate
));
4153 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4154 * @mtd: MTD device structure
4156 * This is the second phase of the normal nand_scan() function. It fills out
4157 * all the uninitialized function pointers with the defaults and scans for a
4158 * bad block table if appropriate.
4160 int nand_scan_tail(struct mtd_info
*mtd
)
4163 struct nand_chip
*chip
= mtd_to_nand(mtd
);
4164 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
4165 struct nand_buffers
*nbuf
;
4167 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4168 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
4169 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
4171 if (invalid_ecc_page_accessors(chip
)) {
4172 pr_err("Invalid ECC page accessors setup\n");
4176 if (!(chip
->options
& NAND_OWN_BUFFERS
)) {
4177 nbuf
= kzalloc(sizeof(struct nand_buffers
), GFP_KERNEL
);
4178 chip
->buffers
= nbuf
;
4184 /* Set the internal oob buffer location, just after the page data */
4185 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
4188 * If no default placement scheme is given, select an appropriate one.
4190 if (!ecc
->layout
&& (ecc
->mode
!= NAND_ECC_SOFT_BCH
)) {
4191 switch (mtd
->oobsize
) {
4193 ecc
->layout
= &nand_oob_8
;
4196 ecc
->layout
= &nand_oob_16
;
4199 ecc
->layout
= &nand_oob_64
;
4202 ecc
->layout
= &nand_oob_128
;
4205 pr_warn("No oob scheme defined for oobsize %d\n",
4211 if (!chip
->write_page
)
4212 chip
->write_page
= nand_write_page
;
4215 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4216 * selected and we have 256 byte pagesize fallback to software ECC
4219 switch (ecc
->mode
) {
4220 case NAND_ECC_HW_OOB_FIRST
:
4221 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4222 if (!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) {
4223 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4226 if (!ecc
->read_page
)
4227 ecc
->read_page
= nand_read_page_hwecc_oob_first
;
4230 /* Use standard hwecc read page function? */
4231 if (!ecc
->read_page
)
4232 ecc
->read_page
= nand_read_page_hwecc
;
4233 if (!ecc
->write_page
)
4234 ecc
->write_page
= nand_write_page_hwecc
;
4235 if (!ecc
->read_page_raw
)
4236 ecc
->read_page_raw
= nand_read_page_raw
;
4237 if (!ecc
->write_page_raw
)
4238 ecc
->write_page_raw
= nand_write_page_raw
;
4240 ecc
->read_oob
= nand_read_oob_std
;
4241 if (!ecc
->write_oob
)
4242 ecc
->write_oob
= nand_write_oob_std
;
4243 if (!ecc
->read_subpage
)
4244 ecc
->read_subpage
= nand_read_subpage
;
4245 if (!ecc
->write_subpage
&& ecc
->hwctl
&& ecc
->calculate
)
4246 ecc
->write_subpage
= nand_write_subpage_hwecc
;
4248 case NAND_ECC_HW_SYNDROME
:
4249 if ((!ecc
->calculate
|| !ecc
->correct
|| !ecc
->hwctl
) &&
4251 ecc
->read_page
== nand_read_page_hwecc
||
4253 ecc
->write_page
== nand_write_page_hwecc
)) {
4254 pr_warn("No ECC functions supplied; hardware ECC not possible\n");
4257 /* Use standard syndrome read/write page function? */
4258 if (!ecc
->read_page
)
4259 ecc
->read_page
= nand_read_page_syndrome
;
4260 if (!ecc
->write_page
)
4261 ecc
->write_page
= nand_write_page_syndrome
;
4262 if (!ecc
->read_page_raw
)
4263 ecc
->read_page_raw
= nand_read_page_raw_syndrome
;
4264 if (!ecc
->write_page_raw
)
4265 ecc
->write_page_raw
= nand_write_page_raw_syndrome
;
4267 ecc
->read_oob
= nand_read_oob_syndrome
;
4268 if (!ecc
->write_oob
)
4269 ecc
->write_oob
= nand_write_oob_syndrome
;
4271 if (mtd
->writesize
>= ecc
->size
) {
4272 if (!ecc
->strength
) {
4273 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4278 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4279 ecc
->size
, mtd
->writesize
);
4280 ecc
->mode
= NAND_ECC_SOFT
;
4283 ecc
->calculate
= nand_calculate_ecc
;
4284 ecc
->correct
= nand_correct_data
;
4285 ecc
->read_page
= nand_read_page_swecc
;
4286 ecc
->read_subpage
= nand_read_subpage
;
4287 ecc
->write_page
= nand_write_page_swecc
;
4288 ecc
->read_page_raw
= nand_read_page_raw
;
4289 ecc
->write_page_raw
= nand_write_page_raw
;
4290 ecc
->read_oob
= nand_read_oob_std
;
4291 ecc
->write_oob
= nand_write_oob_std
;
4298 case NAND_ECC_SOFT_BCH
:
4299 if (!mtd_nand_has_bch()) {
4300 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4303 ecc
->calculate
= nand_bch_calculate_ecc
;
4304 ecc
->correct
= nand_bch_correct_data
;
4305 ecc
->read_page
= nand_read_page_swecc
;
4306 ecc
->read_subpage
= nand_read_subpage
;
4307 ecc
->write_page
= nand_write_page_swecc
;
4308 ecc
->read_page_raw
= nand_read_page_raw
;
4309 ecc
->write_page_raw
= nand_write_page_raw
;
4310 ecc
->read_oob
= nand_read_oob_std
;
4311 ecc
->write_oob
= nand_write_oob_std
;
4313 * Board driver should supply ecc.size and ecc.strength values
4314 * to select how many bits are correctable. Otherwise, default
4315 * to 4 bits for large page devices.
4317 if (!ecc
->size
&& (mtd
->oobsize
>= 64)) {
4322 /* See nand_bch_init() for details. */
4324 ecc
->priv
= nand_bch_init(mtd
);
4326 pr_warn("BCH ECC initialization failed!\n");
4332 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4333 ecc
->read_page
= nand_read_page_raw
;
4334 ecc
->write_page
= nand_write_page_raw
;
4335 ecc
->read_oob
= nand_read_oob_std
;
4336 ecc
->read_page_raw
= nand_read_page_raw
;
4337 ecc
->write_page_raw
= nand_write_page_raw
;
4338 ecc
->write_oob
= nand_write_oob_std
;
4339 ecc
->size
= mtd
->writesize
;
4345 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc
->mode
);
4349 /* For many systems, the standard OOB write also works for raw */
4350 if (!ecc
->read_oob_raw
)
4351 ecc
->read_oob_raw
= ecc
->read_oob
;
4352 if (!ecc
->write_oob_raw
)
4353 ecc
->write_oob_raw
= ecc
->write_oob
;
4356 * The number of bytes available for a client to place data into
4357 * the out of band area.
4361 for (i
= 0; ecc
->layout
->oobfree
[i
].length
; i
++)
4362 mtd
->oobavail
+= ecc
->layout
->oobfree
[i
].length
;
4365 /* ECC sanity check: warn if it's too weak */
4366 if (!nand_ecc_strength_good(mtd
))
4367 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4371 * Set the number of read / write steps for one page depending on ECC
4374 ecc
->steps
= mtd
->writesize
/ ecc
->size
;
4375 if (ecc
->steps
* ecc
->size
!= mtd
->writesize
) {
4376 pr_warn("Invalid ECC parameters\n");
4379 ecc
->total
= ecc
->steps
* ecc
->bytes
;
4381 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4382 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) && nand_is_slc(chip
)) {
4383 switch (ecc
->steps
) {
4385 mtd
->subpage_sft
= 1;
4390 mtd
->subpage_sft
= 2;
4394 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
4396 /* Initialize state */
4397 chip
->state
= FL_READY
;
4399 /* Invalidate the pagebuffer reference */
4402 /* Large page NAND with SOFT_ECC should support subpage reads */
4403 switch (ecc
->mode
) {
4405 case NAND_ECC_SOFT_BCH
:
4406 if (chip
->page_shift
> 9)
4407 chip
->options
|= NAND_SUBPAGE_READ
;
4414 /* Fill in remaining MTD driver data */
4415 mtd
->type
= nand_is_slc(chip
) ? MTD_NANDFLASH
: MTD_MLCNANDFLASH
;
4416 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
4418 mtd
->_erase
= nand_erase
;
4419 mtd
->_read
= nand_read
;
4420 mtd
->_write
= nand_write
;
4421 mtd
->_panic_write
= panic_nand_write
;
4422 mtd
->_read_oob
= nand_read_oob
;
4423 mtd
->_write_oob
= nand_write_oob
;
4424 mtd
->_sync
= nand_sync
;
4426 mtd
->_unlock
= NULL
;
4427 mtd
->_block_isreserved
= nand_block_isreserved
;
4428 mtd
->_block_isbad
= nand_block_isbad
;
4429 mtd
->_block_markbad
= nand_block_markbad
;
4430 mtd
->writebufsize
= mtd
->writesize
;
4432 /* propagate ecc info to mtd_info */
4433 mtd
->ecclayout
= ecc
->layout
;
4434 mtd
->ecc_strength
= ecc
->strength
;
4435 mtd
->ecc_step_size
= ecc
->size
;
4437 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4438 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4441 if (!mtd
->bitflip_threshold
)
4442 mtd
->bitflip_threshold
= DIV_ROUND_UP(mtd
->ecc_strength
* 3, 4);
4446 EXPORT_SYMBOL(nand_scan_tail
);
4449 * nand_scan - [NAND Interface] Scan for the NAND device
4450 * @mtd: MTD device structure
4451 * @maxchips: number of chips to scan for
4453 * This fills out all the uninitialized function pointers with the defaults.
4454 * The flash ID is read and the mtd/chip structures are filled with the
4455 * appropriate values.
4457 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
4461 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
4463 ret
= nand_scan_tail(mtd
);
4466 EXPORT_SYMBOL(nand_scan
);
4468 MODULE_LICENSE("GPL");
4469 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4470 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4471 MODULE_DESCRIPTION("Generic NAND flash driver code");