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mtd: driver _read() returns max_bitflips; mtd_read() returns -EUCLEAN
[people/ms/u-boot.git] / drivers / mtd / nand / nand_base.c
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <common.h>
36
37 #define ENOTSUPP 524 /* Operation is not supported */
38
39 #include <malloc.h>
40 #include <watchdog.h>
41 #include <linux/err.h>
42 #include <linux/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/nand_bch.h>
47
48 #ifdef CONFIG_MTD_PARTITIONS
49 #include <linux/mtd/partitions.h>
50 #endif
51
52 #include <asm/io.h>
53 #include <asm/errno.h>
54
55 /*
56 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
57 * a flash. NAND flash is initialized prior to interrupts so standard timers
58 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
59 * which is greater than (max NAND reset time / NAND status read time).
60 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
61 */
62 #ifndef CONFIG_SYS_NAND_RESET_CNT
63 #define CONFIG_SYS_NAND_RESET_CNT 200000
64 #endif
65
66 /* Define default oob placement schemes for large and small page devices */
67 static struct nand_ecclayout nand_oob_8 = {
68 .eccbytes = 3,
69 .eccpos = {0, 1, 2},
70 .oobfree = {
71 {.offset = 3,
72 .length = 2},
73 {.offset = 6,
74 .length = 2} }
75 };
76
77 static struct nand_ecclayout nand_oob_16 = {
78 .eccbytes = 6,
79 .eccpos = {0, 1, 2, 3, 6, 7},
80 .oobfree = {
81 {.offset = 8,
82 . length = 8} }
83 };
84
85 static struct nand_ecclayout nand_oob_64 = {
86 .eccbytes = 24,
87 .eccpos = {
88 40, 41, 42, 43, 44, 45, 46, 47,
89 48, 49, 50, 51, 52, 53, 54, 55,
90 56, 57, 58, 59, 60, 61, 62, 63},
91 .oobfree = {
92 {.offset = 2,
93 .length = 38} }
94 };
95
96 static struct nand_ecclayout nand_oob_128 = {
97 .eccbytes = 48,
98 .eccpos = {
99 80, 81, 82, 83, 84, 85, 86, 87,
100 88, 89, 90, 91, 92, 93, 94, 95,
101 96, 97, 98, 99, 100, 101, 102, 103,
102 104, 105, 106, 107, 108, 109, 110, 111,
103 112, 113, 114, 115, 116, 117, 118, 119,
104 120, 121, 122, 123, 124, 125, 126, 127},
105 .oobfree = {
106 {.offset = 2,
107 .length = 78} }
108 };
109
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
111 int new_state);
112
113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
115
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
117
118 static int check_offs_len(struct mtd_info *mtd,
119 loff_t ofs, uint64_t len)
120 {
121 struct nand_chip *chip = mtd->priv;
122 int ret = 0;
123
124 /* Start address must align on block boundary */
125 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
126 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
127 ret = -EINVAL;
128 }
129
130 /* Length must align on block boundary */
131 if (len & ((1 << chip->phys_erase_shift) - 1)) {
132 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
133 __func__);
134 ret = -EINVAL;
135 }
136
137 return ret;
138 }
139
140 /**
141 * nand_release_device - [GENERIC] release chip
142 * @mtd: MTD device structure
143 *
144 * Deselect, release chip lock and wake up anyone waiting on the device.
145 */
146 static void nand_release_device(struct mtd_info *mtd)
147 {
148 struct nand_chip *chip = mtd->priv;
149
150 /* De-select the NAND device */
151 chip->select_chip(mtd, -1);
152 }
153
154 /**
155 * nand_read_byte - [DEFAULT] read one byte from the chip
156 * @mtd: MTD device structure
157 *
158 * Default read function for 8bit buswidth.
159 */
160 uint8_t nand_read_byte(struct mtd_info *mtd)
161 {
162 struct nand_chip *chip = mtd->priv;
163 return readb(chip->IO_ADDR_R);
164 }
165
166 /**
167 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
168 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
169 * @mtd: MTD device structure
170 *
171 * Default read function for 16bit buswidth with endianness conversion.
172 *
173 */
174 static uint8_t nand_read_byte16(struct mtd_info *mtd)
175 {
176 struct nand_chip *chip = mtd->priv;
177 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
178 }
179
180 /**
181 * nand_read_word - [DEFAULT] read one word from the chip
182 * @mtd: MTD device structure
183 *
184 * Default read function for 16bit buswidth without endianness conversion.
185 */
186 static u16 nand_read_word(struct mtd_info *mtd)
187 {
188 struct nand_chip *chip = mtd->priv;
189 return readw(chip->IO_ADDR_R);
190 }
191
192 /**
193 * nand_select_chip - [DEFAULT] control CE line
194 * @mtd: MTD device structure
195 * @chipnr: chipnumber to select, -1 for deselect
196 *
197 * Default select function for 1 chip devices.
198 */
199 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
200 {
201 struct nand_chip *chip = mtd->priv;
202
203 switch (chipnr) {
204 case -1:
205 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
206 break;
207 case 0:
208 break;
209
210 default:
211 BUG();
212 }
213 }
214
215 /**
216 * nand_write_buf - [DEFAULT] write buffer to chip
217 * @mtd: MTD device structure
218 * @buf: data buffer
219 * @len: number of bytes to write
220 *
221 * Default write function for 8bit buswidth.
222 */
223 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
224 {
225 int i;
226 struct nand_chip *chip = mtd->priv;
227
228 for (i = 0; i < len; i++)
229 writeb(buf[i], chip->IO_ADDR_W);
230 }
231
232 /**
233 * nand_read_buf - [DEFAULT] read chip data into buffer
234 * @mtd: MTD device structure
235 * @buf: buffer to store date
236 * @len: number of bytes to read
237 *
238 * Default read function for 8bit buswidth.
239 */
240 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
241 {
242 int i;
243 struct nand_chip *chip = mtd->priv;
244
245 for (i = 0; i < len; i++)
246 buf[i] = readb(chip->IO_ADDR_R);
247 }
248
249 /**
250 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
251 * @mtd: MTD device structure
252 * @buf: buffer containing the data to compare
253 * @len: number of bytes to compare
254 *
255 * Default verify function for 8bit buswidth.
256 */
257 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
258 {
259 int i;
260 struct nand_chip *chip = mtd->priv;
261
262 for (i = 0; i < len; i++)
263 if (buf[i] != readb(chip->IO_ADDR_R))
264 return -EFAULT;
265 return 0;
266 }
267
268 /**
269 * nand_write_buf16 - [DEFAULT] write buffer to chip
270 * @mtd: MTD device structure
271 * @buf: data buffer
272 * @len: number of bytes to write
273 *
274 * Default write function for 16bit buswidth.
275 */
276 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
277 {
278 int i;
279 struct nand_chip *chip = mtd->priv;
280 u16 *p = (u16 *) buf;
281 len >>= 1;
282
283 for (i = 0; i < len; i++)
284 writew(p[i], chip->IO_ADDR_W);
285
286 }
287
288 /**
289 * nand_read_buf16 - [DEFAULT] read chip data into buffer
290 * @mtd: MTD device structure
291 * @buf: buffer to store date
292 * @len: number of bytes to read
293 *
294 * Default read function for 16bit buswidth.
295 */
296 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
297 {
298 int i;
299 struct nand_chip *chip = mtd->priv;
300 u16 *p = (u16 *) buf;
301 len >>= 1;
302
303 for (i = 0; i < len; i++)
304 p[i] = readw(chip->IO_ADDR_R);
305 }
306
307 /**
308 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
309 * @mtd: MTD device structure
310 * @buf: buffer containing the data to compare
311 * @len: number of bytes to compare
312 *
313 * Default verify function for 16bit buswidth.
314 */
315 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
316 {
317 int i;
318 struct nand_chip *chip = mtd->priv;
319 u16 *p = (u16 *) buf;
320 len >>= 1;
321
322 for (i = 0; i < len; i++)
323 if (p[i] != readw(chip->IO_ADDR_R))
324 return -EFAULT;
325
326 return 0;
327 }
328
329 /**
330 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
331 * @mtd: MTD device structure
332 * @ofs: offset from device start
333 * @getchip: 0, if the chip is already selected
334 *
335 * Check, if the block is bad.
336 */
337 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
338 {
339 int page, chipnr, res = 0, i = 0;
340 struct nand_chip *chip = mtd->priv;
341 u16 bad;
342
343 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
344 ofs += mtd->erasesize - mtd->writesize;
345
346 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
347
348 if (getchip) {
349 chipnr = (int)(ofs >> chip->chip_shift);
350
351 nand_get_device(chip, mtd, FL_READING);
352
353 /* Select the NAND device */
354 chip->select_chip(mtd, chipnr);
355 }
356
357 do {
358 if (chip->options & NAND_BUSWIDTH_16) {
359 chip->cmdfunc(mtd, NAND_CMD_READOOB,
360 chip->badblockpos & 0xFE, page);
361 bad = cpu_to_le16(chip->read_word(mtd));
362 if (chip->badblockpos & 0x1)
363 bad >>= 8;
364 else
365 bad &= 0xFF;
366 } else {
367 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
368 page);
369 bad = chip->read_byte(mtd);
370 }
371
372 if (likely(chip->badblockbits == 8))
373 res = bad != 0xFF;
374 else
375 res = hweight8(bad) < chip->badblockbits;
376 ofs += mtd->writesize;
377 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
378 i++;
379 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
380
381 if (getchip)
382 nand_release_device(mtd);
383
384 return res;
385 }
386
387 /**
388 * nand_default_block_markbad - [DEFAULT] mark a block bad
389 * @mtd: MTD device structure
390 * @ofs: offset from device start
391 *
392 * This is the default implementation, which can be overridden by a hardware
393 * specific driver. We try operations in the following order, according to our
394 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
395 * (1) erase the affected block, to allow OOB marker to be written cleanly
396 * (2) update in-memory BBT
397 * (3) write bad block marker to OOB area of affected block
398 * (4) update flash-based BBT
399 * Note that we retain the first error encountered in (3) or (4), finish the
400 * procedures, and dump the error in the end.
401 */
402 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
403 {
404 struct nand_chip *chip = mtd->priv;
405 uint8_t buf[2] = { 0, 0 };
406 int block, res, ret = 0, i = 0;
407 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
408
409 if (write_oob) {
410 struct erase_info einfo;
411
412 /* Attempt erase before marking OOB */
413 memset(&einfo, 0, sizeof(einfo));
414 einfo.mtd = mtd;
415 einfo.addr = ofs;
416 einfo.len = 1 << chip->phys_erase_shift;
417 nand_erase_nand(mtd, &einfo, 0);
418 }
419
420 /* Get block number */
421 block = (int)(ofs >> chip->bbt_erase_shift);
422 /* Mark block bad in memory-based BBT */
423 if (chip->bbt)
424 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
425
426 /* Write bad block marker to OOB */
427 if (write_oob) {
428 struct mtd_oob_ops ops;
429 loff_t wr_ofs = ofs;
430
431 nand_get_device(chip, mtd, FL_WRITING);
432
433 ops.datbuf = NULL;
434 ops.oobbuf = buf;
435 ops.ooboffs = chip->badblockpos;
436 if (chip->options & NAND_BUSWIDTH_16) {
437 ops.ooboffs &= ~0x01;
438 ops.len = ops.ooblen = 2;
439 } else {
440 ops.len = ops.ooblen = 1;
441 }
442 ops.mode = MTD_OPS_PLACE_OOB;
443
444 /* Write to first/last page(s) if necessary */
445 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
446 wr_ofs += mtd->erasesize - mtd->writesize;
447 do {
448 res = nand_do_write_oob(mtd, wr_ofs, &ops);
449 if (!ret)
450 ret = res;
451
452 i++;
453 wr_ofs += mtd->writesize;
454 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
455
456 nand_release_device(mtd);
457 }
458
459 /* Update flash-based bad block table */
460 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
461 res = nand_update_bbt(mtd, ofs);
462 if (!ret)
463 ret = res;
464 }
465
466 if (!ret)
467 mtd->ecc_stats.badblocks++;
468
469 return ret;
470 }
471
472 /**
473 * nand_check_wp - [GENERIC] check if the chip is write protected
474 * @mtd: MTD device structure
475 *
476 * Check, if the device is write protected. The function expects, that the
477 * device is already selected.
478 */
479 static int nand_check_wp(struct mtd_info *mtd)
480 {
481 struct nand_chip *chip = mtd->priv;
482
483 /* Broken xD cards report WP despite being writable */
484 if (chip->options & NAND_BROKEN_XD)
485 return 0;
486
487 /* Check the WP bit */
488 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
489 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
490 }
491
492 /**
493 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
494 * @mtd: MTD device structure
495 * @ofs: offset from device start
496 * @getchip: 0, if the chip is already selected
497 * @allowbbt: 1, if its allowed to access the bbt area
498 *
499 * Check, if the block is bad. Either by reading the bad block table or
500 * calling of the scan function.
501 */
502 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
503 int allowbbt)
504 {
505 struct nand_chip *chip = mtd->priv;
506
507 if (!(chip->options & NAND_BBT_SCANNED)) {
508 chip->options |= NAND_BBT_SCANNED;
509 chip->scan_bbt(mtd);
510 }
511
512 if (!chip->bbt)
513 return chip->block_bad(mtd, ofs, getchip);
514
515 /* Return info from the table */
516 return nand_isbad_bbt(mtd, ofs, allowbbt);
517 }
518
519 /* Wait for the ready pin, after a command. The timeout is caught later. */
520 void nand_wait_ready(struct mtd_info *mtd)
521 {
522 struct nand_chip *chip = mtd->priv;
523 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
524 u32 time_start;
525
526 time_start = get_timer(0);
527
528 /* Wait until command is processed or timeout occurs */
529 while (get_timer(time_start) < timeo) {
530 if (chip->dev_ready)
531 if (chip->dev_ready(mtd))
532 break;
533 }
534 }
535
536 /**
537 * nand_command - [DEFAULT] Send command to NAND device
538 * @mtd: MTD device structure
539 * @command: the command to be sent
540 * @column: the column address for this command, -1 if none
541 * @page_addr: the page address for this command, -1 if none
542 *
543 * Send command to NAND device. This function is used for small page devices
544 * (256/512 Bytes per page).
545 */
546 static void nand_command(struct mtd_info *mtd, unsigned int command,
547 int column, int page_addr)
548 {
549 register struct nand_chip *chip = mtd->priv;
550 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
551 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
552
553 /* Write out the command to the device */
554 if (command == NAND_CMD_SEQIN) {
555 int readcmd;
556
557 if (column >= mtd->writesize) {
558 /* OOB area */
559 column -= mtd->writesize;
560 readcmd = NAND_CMD_READOOB;
561 } else if (column < 256) {
562 /* First 256 bytes --> READ0 */
563 readcmd = NAND_CMD_READ0;
564 } else {
565 column -= 256;
566 readcmd = NAND_CMD_READ1;
567 }
568 chip->cmd_ctrl(mtd, readcmd, ctrl);
569 ctrl &= ~NAND_CTRL_CHANGE;
570 }
571 chip->cmd_ctrl(mtd, command, ctrl);
572
573 /* Address cycle, when necessary */
574 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
575 /* Serially input address */
576 if (column != -1) {
577 /* Adjust columns for 16 bit buswidth */
578 if (chip->options & NAND_BUSWIDTH_16)
579 column >>= 1;
580 chip->cmd_ctrl(mtd, column, ctrl);
581 ctrl &= ~NAND_CTRL_CHANGE;
582 }
583 if (page_addr != -1) {
584 chip->cmd_ctrl(mtd, page_addr, ctrl);
585 ctrl &= ~NAND_CTRL_CHANGE;
586 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
587 /* One more address cycle for devices > 32MiB */
588 if (chip->chipsize > (32 << 20))
589 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
590 }
591 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
592
593 /*
594 * Program and erase have their own busy handlers status and sequential
595 * in needs no delay
596 */
597 switch (command) {
598
599 case NAND_CMD_PAGEPROG:
600 case NAND_CMD_ERASE1:
601 case NAND_CMD_ERASE2:
602 case NAND_CMD_SEQIN:
603 case NAND_CMD_STATUS:
604 return;
605
606 case NAND_CMD_RESET:
607 if (chip->dev_ready)
608 break;
609 udelay(chip->chip_delay);
610 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
611 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
612 chip->cmd_ctrl(mtd,
613 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
614 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
615 (rst_sts_cnt--));
616 return;
617
618 /* This applies to read commands */
619 default:
620 /*
621 * If we don't have access to the busy pin, we apply the given
622 * command delay
623 */
624 if (!chip->dev_ready) {
625 udelay(chip->chip_delay);
626 return;
627 }
628 }
629 /*
630 * Apply this short delay always to ensure that we do wait tWB in
631 * any case on any machine.
632 */
633 ndelay(100);
634
635 nand_wait_ready(mtd);
636 }
637
638 /**
639 * nand_command_lp - [DEFAULT] Send command to NAND large page device
640 * @mtd: MTD device structure
641 * @command: the command to be sent
642 * @column: the column address for this command, -1 if none
643 * @page_addr: the page address for this command, -1 if none
644 *
645 * Send command to NAND device. This is the version for the new large page
646 * devices. We don't have the separate regions as we have in the small page
647 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
648 */
649 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
650 int column, int page_addr)
651 {
652 register struct nand_chip *chip = mtd->priv;
653 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
654
655 /* Emulate NAND_CMD_READOOB */
656 if (command == NAND_CMD_READOOB) {
657 column += mtd->writesize;
658 command = NAND_CMD_READ0;
659 }
660
661 /* Command latch cycle */
662 chip->cmd_ctrl(mtd, command & 0xff,
663 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
664
665 if (column != -1 || page_addr != -1) {
666 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
667
668 /* Serially input address */
669 if (column != -1) {
670 /* Adjust columns for 16 bit buswidth */
671 if (chip->options & NAND_BUSWIDTH_16)
672 column >>= 1;
673 chip->cmd_ctrl(mtd, column, ctrl);
674 ctrl &= ~NAND_CTRL_CHANGE;
675 chip->cmd_ctrl(mtd, column >> 8, ctrl);
676 }
677 if (page_addr != -1) {
678 chip->cmd_ctrl(mtd, page_addr, ctrl);
679 chip->cmd_ctrl(mtd, page_addr >> 8,
680 NAND_NCE | NAND_ALE);
681 /* One more address cycle for devices > 128MiB */
682 if (chip->chipsize > (128 << 20))
683 chip->cmd_ctrl(mtd, page_addr >> 16,
684 NAND_NCE | NAND_ALE);
685 }
686 }
687 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
688
689 /*
690 * Program and erase have their own busy handlers status, sequential
691 * in, and deplete1 need no delay.
692 */
693 switch (command) {
694
695 case NAND_CMD_CACHEDPROG:
696 case NAND_CMD_PAGEPROG:
697 case NAND_CMD_ERASE1:
698 case NAND_CMD_ERASE2:
699 case NAND_CMD_SEQIN:
700 case NAND_CMD_RNDIN:
701 case NAND_CMD_STATUS:
702 case NAND_CMD_DEPLETE1:
703 return;
704
705 case NAND_CMD_STATUS_ERROR:
706 case NAND_CMD_STATUS_ERROR0:
707 case NAND_CMD_STATUS_ERROR1:
708 case NAND_CMD_STATUS_ERROR2:
709 case NAND_CMD_STATUS_ERROR3:
710 /* Read error status commands require only a short delay */
711 udelay(chip->chip_delay);
712 return;
713
714 case NAND_CMD_RESET:
715 if (chip->dev_ready)
716 break;
717 udelay(chip->chip_delay);
718 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
719 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
720 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
721 NAND_NCE | NAND_CTRL_CHANGE);
722 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
723 (rst_sts_cnt--));
724 return;
725
726 case NAND_CMD_RNDOUT:
727 /* No ready / busy check necessary */
728 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
729 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
730 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
731 NAND_NCE | NAND_CTRL_CHANGE);
732 return;
733
734 case NAND_CMD_READ0:
735 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
736 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
737 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
738 NAND_NCE | NAND_CTRL_CHANGE);
739
740 /* This applies to read commands */
741 default:
742 /*
743 * If we don't have access to the busy pin, we apply the given
744 * command delay.
745 */
746 if (!chip->dev_ready) {
747 udelay(chip->chip_delay);
748 return;
749 }
750 }
751
752 /*
753 * Apply this short delay always to ensure that we do wait tWB in
754 * any case on any machine.
755 */
756 ndelay(100);
757
758 nand_wait_ready(mtd);
759 }
760
761 /**
762 * nand_get_device - [GENERIC] Get chip for selected access
763 * @chip: the nand chip descriptor
764 * @mtd: MTD device structure
765 * @new_state: the state which is requested
766 *
767 * Get the device and lock it for exclusive access
768 */
769 static int
770 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
771 {
772 chip->state = new_state;
773 return 0;
774 }
775
776 /**
777 * nand_wait - [DEFAULT] wait until the command is done
778 * @mtd: MTD device structure
779 * @chip: NAND chip structure
780 *
781 * Wait for command done. This applies to erase and program only. Erase can
782 * take up to 400ms and program up to 20ms according to general NAND and
783 * SmartMedia specs.
784 */
785 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
786 {
787 unsigned long timeo;
788 int state = chip->state;
789 u32 time_start;
790
791 if (state == FL_ERASING)
792 timeo = (CONFIG_SYS_HZ * 400) / 1000;
793 else
794 timeo = (CONFIG_SYS_HZ * 20) / 1000;
795
796 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
797 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
798 else
799 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
800
801 time_start = get_timer(0);
802
803 while (1) {
804 if (get_timer(time_start) > timeo) {
805 printf("Timeout!");
806 return 0x01;
807 }
808
809 if (chip->dev_ready) {
810 if (chip->dev_ready(mtd))
811 break;
812 } else {
813 if (chip->read_byte(mtd) & NAND_STATUS_READY)
814 break;
815 }
816 }
817 #ifdef PPCHAMELON_NAND_TIMER_HACK
818 time_start = get_timer(0);
819 while (get_timer(time_start) < 10)
820 ;
821 #endif /* PPCHAMELON_NAND_TIMER_HACK */
822
823 return (int)chip->read_byte(mtd);
824 }
825
826 /**
827 * nand_read_page_raw - [INTERN] read raw page data without ecc
828 * @mtd: mtd info structure
829 * @chip: nand chip info structure
830 * @buf: buffer to store read data
831 * @oob_required: caller requires OOB data read to chip->oob_poi
832 * @page: page number to read
833 *
834 * Not for syndrome calculating ECC controllers, which use a special oob layout.
835 */
836 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
837 uint8_t *buf, int oob_required, int page)
838 {
839 chip->read_buf(mtd, buf, mtd->writesize);
840 if (oob_required)
841 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
842 return 0;
843 }
844
845 /**
846 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
847 * @mtd: mtd info structure
848 * @chip: nand chip info structure
849 * @buf: buffer to store read data
850 * @oob_required: caller requires OOB data read to chip->oob_poi
851 * @page: page number to read
852 *
853 * We need a special oob layout and handling even when OOB isn't used.
854 */
855 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
856 struct nand_chip *chip, uint8_t *buf,
857 int oob_required, int page)
858 {
859 int eccsize = chip->ecc.size;
860 int eccbytes = chip->ecc.bytes;
861 uint8_t *oob = chip->oob_poi;
862 int steps, size;
863
864 for (steps = chip->ecc.steps; steps > 0; steps--) {
865 chip->read_buf(mtd, buf, eccsize);
866 buf += eccsize;
867
868 if (chip->ecc.prepad) {
869 chip->read_buf(mtd, oob, chip->ecc.prepad);
870 oob += chip->ecc.prepad;
871 }
872
873 chip->read_buf(mtd, oob, eccbytes);
874 oob += eccbytes;
875
876 if (chip->ecc.postpad) {
877 chip->read_buf(mtd, oob, chip->ecc.postpad);
878 oob += chip->ecc.postpad;
879 }
880 }
881
882 size = mtd->oobsize - (oob - chip->oob_poi);
883 if (size)
884 chip->read_buf(mtd, oob, size);
885
886 return 0;
887 }
888
889 /**
890 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
891 * @mtd: mtd info structure
892 * @chip: nand chip info structure
893 * @buf: buffer to store read data
894 * @oob_required: caller requires OOB data read to chip->oob_poi
895 * @page: page number to read
896 */
897 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
898 uint8_t *buf, int oob_required, int page)
899 {
900 int i, eccsize = chip->ecc.size;
901 int eccbytes = chip->ecc.bytes;
902 int eccsteps = chip->ecc.steps;
903 uint8_t *p = buf;
904 uint8_t *ecc_calc = chip->buffers->ecccalc;
905 uint8_t *ecc_code = chip->buffers->ecccode;
906 uint32_t *eccpos = chip->ecc.layout->eccpos;
907
908 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
909
910 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
911 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
912
913 for (i = 0; i < chip->ecc.total; i++)
914 ecc_code[i] = chip->oob_poi[eccpos[i]];
915
916 eccsteps = chip->ecc.steps;
917 p = buf;
918
919 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
920 int stat;
921
922 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
923 if (stat < 0)
924 mtd->ecc_stats.failed++;
925 else
926 mtd->ecc_stats.corrected += stat;
927 }
928 return 0;
929 }
930
931 /**
932 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
933 * @mtd: mtd info structure
934 * @chip: nand chip info structure
935 * @data_offs: offset of requested data within the page
936 * @readlen: data length
937 * @bufpoi: buffer to store read data
938 */
939 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
940 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
941 {
942 int start_step, end_step, num_steps;
943 uint32_t *eccpos = chip->ecc.layout->eccpos;
944 uint8_t *p;
945 int data_col_addr, i, gaps = 0;
946 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
947 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
948 int index = 0;
949
950 /* Column address within the page aligned to ECC size (256bytes) */
951 start_step = data_offs / chip->ecc.size;
952 end_step = (data_offs + readlen - 1) / chip->ecc.size;
953 num_steps = end_step - start_step + 1;
954
955 /* Data size aligned to ECC ecc.size */
956 datafrag_len = num_steps * chip->ecc.size;
957 eccfrag_len = num_steps * chip->ecc.bytes;
958
959 data_col_addr = start_step * chip->ecc.size;
960 /* If we read not a page aligned data */
961 if (data_col_addr != 0)
962 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
963
964 p = bufpoi + data_col_addr;
965 chip->read_buf(mtd, p, datafrag_len);
966
967 /* Calculate ECC */
968 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
969 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
970
971 /*
972 * The performance is faster if we position offsets according to
973 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
974 */
975 for (i = 0; i < eccfrag_len - 1; i++) {
976 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
977 eccpos[i + start_step * chip->ecc.bytes + 1]) {
978 gaps = 1;
979 break;
980 }
981 }
982 if (gaps) {
983 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
984 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
985 } else {
986 /*
987 * Send the command to read the particular ECC bytes take care
988 * about buswidth alignment in read_buf.
989 */
990 index = start_step * chip->ecc.bytes;
991
992 aligned_pos = eccpos[index] & ~(busw - 1);
993 aligned_len = eccfrag_len;
994 if (eccpos[index] & (busw - 1))
995 aligned_len++;
996 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
997 aligned_len++;
998
999 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1000 mtd->writesize + aligned_pos, -1);
1001 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1002 }
1003
1004 for (i = 0; i < eccfrag_len; i++)
1005 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1006
1007 p = bufpoi + data_col_addr;
1008 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1009 int stat;
1010
1011 stat = chip->ecc.correct(mtd, p,
1012 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1013 if (stat < 0)
1014 mtd->ecc_stats.failed++;
1015 else
1016 mtd->ecc_stats.corrected += stat;
1017 }
1018 return 0;
1019 }
1020
1021 /**
1022 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1023 * @mtd: mtd info structure
1024 * @chip: nand chip info structure
1025 * @buf: buffer to store read data
1026 * @oob_required: caller requires OOB data read to chip->oob_poi
1027 * @page: page number to read
1028 *
1029 * Not for syndrome calculating ECC controllers which need a special oob layout.
1030 */
1031 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1032 uint8_t *buf, int oob_required, int page)
1033 {
1034 int i, eccsize = chip->ecc.size;
1035 int eccbytes = chip->ecc.bytes;
1036 int eccsteps = chip->ecc.steps;
1037 uint8_t *p = buf;
1038 uint8_t *ecc_calc = chip->buffers->ecccalc;
1039 uint8_t *ecc_code = chip->buffers->ecccode;
1040 uint32_t *eccpos = chip->ecc.layout->eccpos;
1041
1042 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1043 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1044 chip->read_buf(mtd, p, eccsize);
1045 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1046 }
1047 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1048
1049 for (i = 0; i < chip->ecc.total; i++)
1050 ecc_code[i] = chip->oob_poi[eccpos[i]];
1051
1052 eccsteps = chip->ecc.steps;
1053 p = buf;
1054
1055 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1056 int stat;
1057
1058 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1059 if (stat < 0)
1060 mtd->ecc_stats.failed++;
1061 else
1062 mtd->ecc_stats.corrected += stat;
1063 }
1064 return 0;
1065 }
1066
1067 /**
1068 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1069 * @mtd: mtd info structure
1070 * @chip: nand chip info structure
1071 * @buf: buffer to store read data
1072 * @oob_required: caller requires OOB data read to chip->oob_poi
1073 * @page: page number to read
1074 *
1075 * Hardware ECC for large page chips, require OOB to be read first. For this
1076 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1077 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1078 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1079 * the data area, by overwriting the NAND manufacturer bad block markings.
1080 */
1081 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1082 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1083 {
1084 int i, eccsize = chip->ecc.size;
1085 int eccbytes = chip->ecc.bytes;
1086 int eccsteps = chip->ecc.steps;
1087 uint8_t *p = buf;
1088 uint8_t *ecc_code = chip->buffers->ecccode;
1089 uint32_t *eccpos = chip->ecc.layout->eccpos;
1090 uint8_t *ecc_calc = chip->buffers->ecccalc;
1091
1092 /* Read the OOB area first */
1093 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1094 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1095 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1096
1097 for (i = 0; i < chip->ecc.total; i++)
1098 ecc_code[i] = chip->oob_poi[eccpos[i]];
1099
1100 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1101 int stat;
1102
1103 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1104 chip->read_buf(mtd, p, eccsize);
1105 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1106
1107 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1108 if (stat < 0)
1109 mtd->ecc_stats.failed++;
1110 else
1111 mtd->ecc_stats.corrected += stat;
1112 }
1113 return 0;
1114 }
1115
1116 /**
1117 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1118 * @mtd: mtd info structure
1119 * @chip: nand chip info structure
1120 * @buf: buffer to store read data
1121 * @oob_required: caller requires OOB data read to chip->oob_poi
1122 * @page: page number to read
1123 *
1124 * The hw generator calculates the error syndrome automatically. Therefore we
1125 * need a special oob layout and handling.
1126 */
1127 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1128 uint8_t *buf, int oob_required, int page)
1129 {
1130 int i, eccsize = chip->ecc.size;
1131 int eccbytes = chip->ecc.bytes;
1132 int eccsteps = chip->ecc.steps;
1133 uint8_t *p = buf;
1134 uint8_t *oob = chip->oob_poi;
1135
1136 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1137 int stat;
1138
1139 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1140 chip->read_buf(mtd, p, eccsize);
1141
1142 if (chip->ecc.prepad) {
1143 chip->read_buf(mtd, oob, chip->ecc.prepad);
1144 oob += chip->ecc.prepad;
1145 }
1146
1147 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1148 chip->read_buf(mtd, oob, eccbytes);
1149 stat = chip->ecc.correct(mtd, p, oob, NULL);
1150
1151 if (stat < 0)
1152 mtd->ecc_stats.failed++;
1153 else
1154 mtd->ecc_stats.corrected += stat;
1155
1156 oob += eccbytes;
1157
1158 if (chip->ecc.postpad) {
1159 chip->read_buf(mtd, oob, chip->ecc.postpad);
1160 oob += chip->ecc.postpad;
1161 }
1162 }
1163
1164 /* Calculate remaining oob bytes */
1165 i = mtd->oobsize - (oob - chip->oob_poi);
1166 if (i)
1167 chip->read_buf(mtd, oob, i);
1168
1169 return 0;
1170 }
1171
1172 /**
1173 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1174 * @chip: nand chip structure
1175 * @oob: oob destination address
1176 * @ops: oob ops structure
1177 * @len: size of oob to transfer
1178 */
1179 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1180 struct mtd_oob_ops *ops, size_t len)
1181 {
1182 switch (ops->mode) {
1183
1184 case MTD_OPS_PLACE_OOB:
1185 case MTD_OPS_RAW:
1186 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1187 return oob + len;
1188
1189 case MTD_OPS_AUTO_OOB: {
1190 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1191 uint32_t boffs = 0, roffs = ops->ooboffs;
1192 size_t bytes = 0;
1193
1194 for (; free->length && len; free++, len -= bytes) {
1195 /* Read request not from offset 0? */
1196 if (unlikely(roffs)) {
1197 if (roffs >= free->length) {
1198 roffs -= free->length;
1199 continue;
1200 }
1201 boffs = free->offset + roffs;
1202 bytes = min_t(size_t, len,
1203 (free->length - roffs));
1204 roffs = 0;
1205 } else {
1206 bytes = min_t(size_t, len, free->length);
1207 boffs = free->offset;
1208 }
1209 memcpy(oob, chip->oob_poi + boffs, bytes);
1210 oob += bytes;
1211 }
1212 return oob;
1213 }
1214 default:
1215 BUG();
1216 }
1217 return NULL;
1218 }
1219
1220 /**
1221 * nand_do_read_ops - [INTERN] Read data with ECC
1222 * @mtd: MTD device structure
1223 * @from: offset to read from
1224 * @ops: oob ops structure
1225 *
1226 * Internal function. Called with chip held.
1227 */
1228 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1229 struct mtd_oob_ops *ops)
1230 {
1231 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1232 struct nand_chip *chip = mtd->priv;
1233 struct mtd_ecc_stats stats;
1234 int ret = 0;
1235 uint32_t readlen = ops->len;
1236 uint32_t oobreadlen = ops->ooblen;
1237 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1238 mtd->oobavail : mtd->oobsize;
1239
1240 uint8_t *bufpoi, *oob, *buf;
1241 unsigned int max_bitflips = 0;
1242
1243 stats = mtd->ecc_stats;
1244
1245 chipnr = (int)(from >> chip->chip_shift);
1246 chip->select_chip(mtd, chipnr);
1247
1248 realpage = (int)(from >> chip->page_shift);
1249 page = realpage & chip->pagemask;
1250
1251 col = (int)(from & (mtd->writesize - 1));
1252
1253 buf = ops->datbuf;
1254 oob = ops->oobbuf;
1255 oob_required = oob ? 1 : 0;
1256
1257 while (1) {
1258 WATCHDOG_RESET();
1259
1260 bytes = min(mtd->writesize - col, readlen);
1261 aligned = (bytes == mtd->writesize);
1262
1263 /* Is the current page in the buffer? */
1264 if (realpage != chip->pagebuf || oob) {
1265 bufpoi = aligned ? buf : chip->buffers->databuf;
1266
1267 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1268
1269 /*
1270 * Now read the page into the buffer. Absent an error,
1271 * the read methods return max bitflips per ecc step.
1272 */
1273 if (unlikely(ops->mode == MTD_OPS_RAW))
1274 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1275 oob_required,
1276 page);
1277 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1278 !oob)
1279 ret = chip->ecc.read_subpage(mtd, chip,
1280 col, bytes, bufpoi);
1281 else
1282 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1283 oob_required, page);
1284 if (ret < 0) {
1285 if (!aligned)
1286 /* Invalidate page cache */
1287 chip->pagebuf = -1;
1288 break;
1289 }
1290
1291 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1292
1293 /* Transfer not aligned data */
1294 if (!aligned) {
1295 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1296 !(mtd->ecc_stats.failed - stats.failed) &&
1297 (ops->mode != MTD_OPS_RAW)) {
1298 chip->pagebuf = realpage;
1299 chip->pagebuf_bitflips = ret;
1300 } else {
1301 /* Invalidate page cache */
1302 chip->pagebuf = -1;
1303 }
1304 memcpy(buf, chip->buffers->databuf + col, bytes);
1305 }
1306
1307 buf += bytes;
1308
1309 if (unlikely(oob)) {
1310 int toread = min(oobreadlen, max_oobsize);
1311
1312 if (toread) {
1313 oob = nand_transfer_oob(chip,
1314 oob, ops, toread);
1315 oobreadlen -= toread;
1316 }
1317 }
1318 } else {
1319 memcpy(buf, chip->buffers->databuf + col, bytes);
1320 buf += bytes;
1321 max_bitflips = max_t(unsigned int, max_bitflips,
1322 chip->pagebuf_bitflips);
1323 }
1324
1325 readlen -= bytes;
1326
1327 if (!readlen)
1328 break;
1329
1330 /* For subsequent reads align to page boundary */
1331 col = 0;
1332 /* Increment page address */
1333 realpage++;
1334
1335 page = realpage & chip->pagemask;
1336 /* Check, if we cross a chip boundary */
1337 if (!page) {
1338 chipnr++;
1339 chip->select_chip(mtd, -1);
1340 chip->select_chip(mtd, chipnr);
1341 }
1342 }
1343
1344 ops->retlen = ops->len - (size_t) readlen;
1345 if (oob)
1346 ops->oobretlen = ops->ooblen - oobreadlen;
1347
1348 if (ret)
1349 return ret;
1350
1351 if (mtd->ecc_stats.failed - stats.failed)
1352 return -EBADMSG;
1353
1354 return max_bitflips;
1355 }
1356
1357 /**
1358 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1359 * @mtd: MTD device structure
1360 * @from: offset to read from
1361 * @len: number of bytes to read
1362 * @retlen: pointer to variable to store the number of read bytes
1363 * @buf: the databuffer to put data
1364 *
1365 * Get hold of the chip and call nand_do_read.
1366 */
1367 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1368 size_t *retlen, uint8_t *buf)
1369 {
1370 struct nand_chip *chip = mtd->priv;
1371 struct mtd_oob_ops ops;
1372 int ret;
1373
1374 nand_get_device(chip, mtd, FL_READING);
1375 ops.len = len;
1376 ops.datbuf = buf;
1377 ops.oobbuf = NULL;
1378 ops.mode = MTD_OPS_PLACE_OOB;
1379 ret = nand_do_read_ops(mtd, from, &ops);
1380 *retlen = ops.retlen;
1381 nand_release_device(mtd);
1382 return ret;
1383 }
1384
1385 /**
1386 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1387 * @mtd: mtd info structure
1388 * @chip: nand chip info structure
1389 * @page: page number to read
1390 */
1391 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1392 int page)
1393 {
1394 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1395 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1396 return 0;
1397 }
1398
1399 /**
1400 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1401 * with syndromes
1402 * @mtd: mtd info structure
1403 * @chip: nand chip info structure
1404 * @page: page number to read
1405 */
1406 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1407 int page)
1408 {
1409 uint8_t *buf = chip->oob_poi;
1410 int length = mtd->oobsize;
1411 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1412 int eccsize = chip->ecc.size;
1413 uint8_t *bufpoi = buf;
1414 int i, toread, sndrnd = 0, pos;
1415
1416 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1417 for (i = 0; i < chip->ecc.steps; i++) {
1418 if (sndrnd) {
1419 pos = eccsize + i * (eccsize + chunk);
1420 if (mtd->writesize > 512)
1421 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1422 else
1423 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1424 } else
1425 sndrnd = 1;
1426 toread = min_t(int, length, chunk);
1427 chip->read_buf(mtd, bufpoi, toread);
1428 bufpoi += toread;
1429 length -= toread;
1430 }
1431 if (length > 0)
1432 chip->read_buf(mtd, bufpoi, length);
1433
1434 return 0;
1435 }
1436
1437 /**
1438 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1439 * @mtd: mtd info structure
1440 * @chip: nand chip info structure
1441 * @page: page number to write
1442 */
1443 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1444 int page)
1445 {
1446 int status = 0;
1447 const uint8_t *buf = chip->oob_poi;
1448 int length = mtd->oobsize;
1449
1450 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1451 chip->write_buf(mtd, buf, length);
1452 /* Send command to program the OOB data */
1453 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1454
1455 status = chip->waitfunc(mtd, chip);
1456
1457 return status & NAND_STATUS_FAIL ? -EIO : 0;
1458 }
1459
1460 /**
1461 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1462 * with syndrome - only for large page flash
1463 * @mtd: mtd info structure
1464 * @chip: nand chip info structure
1465 * @page: page number to write
1466 */
1467 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1468 struct nand_chip *chip, int page)
1469 {
1470 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1471 int eccsize = chip->ecc.size, length = mtd->oobsize;
1472 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1473 const uint8_t *bufpoi = chip->oob_poi;
1474
1475 /*
1476 * data-ecc-data-ecc ... ecc-oob
1477 * or
1478 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1479 */
1480 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1481 pos = steps * (eccsize + chunk);
1482 steps = 0;
1483 } else
1484 pos = eccsize;
1485
1486 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1487 for (i = 0; i < steps; i++) {
1488 if (sndcmd) {
1489 if (mtd->writesize <= 512) {
1490 uint32_t fill = 0xFFFFFFFF;
1491
1492 len = eccsize;
1493 while (len > 0) {
1494 int num = min_t(int, len, 4);
1495 chip->write_buf(mtd, (uint8_t *)&fill,
1496 num);
1497 len -= num;
1498 }
1499 } else {
1500 pos = eccsize + i * (eccsize + chunk);
1501 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1502 }
1503 } else
1504 sndcmd = 1;
1505 len = min_t(int, length, chunk);
1506 chip->write_buf(mtd, bufpoi, len);
1507 bufpoi += len;
1508 length -= len;
1509 }
1510 if (length > 0)
1511 chip->write_buf(mtd, bufpoi, length);
1512
1513 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1514 status = chip->waitfunc(mtd, chip);
1515
1516 return status & NAND_STATUS_FAIL ? -EIO : 0;
1517 }
1518
1519 /**
1520 * nand_do_read_oob - [INTERN] NAND read out-of-band
1521 * @mtd: MTD device structure
1522 * @from: offset to read from
1523 * @ops: oob operations description structure
1524 *
1525 * NAND read out-of-band data from the spare area.
1526 */
1527 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1528 struct mtd_oob_ops *ops)
1529 {
1530 int page, realpage, chipnr;
1531 struct nand_chip *chip = mtd->priv;
1532 struct mtd_ecc_stats stats;
1533 int readlen = ops->ooblen;
1534 int len;
1535 uint8_t *buf = ops->oobbuf;
1536 int ret = 0;
1537
1538 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1539 __func__, (unsigned long long)from, readlen);
1540
1541 stats = mtd->ecc_stats;
1542
1543 if (ops->mode == MTD_OPS_AUTO_OOB)
1544 len = chip->ecc.layout->oobavail;
1545 else
1546 len = mtd->oobsize;
1547
1548 if (unlikely(ops->ooboffs >= len)) {
1549 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1550 "outside oob\n", __func__);
1551 return -EINVAL;
1552 }
1553
1554 /* Do not allow reads past end of device */
1555 if (unlikely(from >= mtd->size ||
1556 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1557 (from >> chip->page_shift)) * len)) {
1558 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1559 "of device\n", __func__);
1560 return -EINVAL;
1561 }
1562
1563 chipnr = (int)(from >> chip->chip_shift);
1564 chip->select_chip(mtd, chipnr);
1565
1566 /* Shift to get page */
1567 realpage = (int)(from >> chip->page_shift);
1568 page = realpage & chip->pagemask;
1569
1570 while (1) {
1571 WATCHDOG_RESET();
1572 if (ops->mode == MTD_OPS_RAW)
1573 ret = chip->ecc.read_oob_raw(mtd, chip, page);
1574 else
1575 ret = chip->ecc.read_oob(mtd, chip, page);
1576
1577 if (ret < 0)
1578 break;
1579
1580 len = min(len, readlen);
1581 buf = nand_transfer_oob(chip, buf, ops, len);
1582
1583 readlen -= len;
1584 if (!readlen)
1585 break;
1586
1587 /* Increment page address */
1588 realpage++;
1589
1590 page = realpage & chip->pagemask;
1591 /* Check, if we cross a chip boundary */
1592 if (!page) {
1593 chipnr++;
1594 chip->select_chip(mtd, -1);
1595 chip->select_chip(mtd, chipnr);
1596 }
1597 }
1598
1599 ops->oobretlen = ops->ooblen - readlen;
1600
1601 if (ret < 0)
1602 return ret;
1603
1604 if (mtd->ecc_stats.failed - stats.failed)
1605 return -EBADMSG;
1606
1607 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1608 }
1609
1610 /**
1611 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1612 * @mtd: MTD device structure
1613 * @from: offset to read from
1614 * @ops: oob operation description structure
1615 *
1616 * NAND read data and/or out-of-band data.
1617 */
1618 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1619 struct mtd_oob_ops *ops)
1620 {
1621 struct nand_chip *chip = mtd->priv;
1622 int ret = -ENOTSUPP;
1623
1624 ops->retlen = 0;
1625
1626 /* Do not allow reads past end of device */
1627 if (ops->datbuf && (from + ops->len) > mtd->size) {
1628 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1629 "beyond end of device\n", __func__);
1630 return -EINVAL;
1631 }
1632
1633 nand_get_device(chip, mtd, FL_READING);
1634
1635 switch (ops->mode) {
1636 case MTD_OPS_PLACE_OOB:
1637 case MTD_OPS_AUTO_OOB:
1638 case MTD_OPS_RAW:
1639 break;
1640
1641 default:
1642 goto out;
1643 }
1644
1645 if (!ops->datbuf)
1646 ret = nand_do_read_oob(mtd, from, ops);
1647 else
1648 ret = nand_do_read_ops(mtd, from, ops);
1649
1650 out:
1651 nand_release_device(mtd);
1652 return ret;
1653 }
1654
1655
1656 /**
1657 * nand_write_page_raw - [INTERN] raw page write function
1658 * @mtd: mtd info structure
1659 * @chip: nand chip info structure
1660 * @buf: data buffer
1661 * @oob_required: must write chip->oob_poi to OOB
1662 *
1663 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1664 */
1665 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1666 const uint8_t *buf, int oob_required)
1667 {
1668 chip->write_buf(mtd, buf, mtd->writesize);
1669 if (oob_required)
1670 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1671
1672 return 0;
1673 }
1674
1675 /**
1676 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1677 * @mtd: mtd info structure
1678 * @chip: nand chip info structure
1679 * @buf: data buffer
1680 * @oob_required: must write chip->oob_poi to OOB
1681 *
1682 * We need a special oob layout and handling even when ECC isn't checked.
1683 */
1684 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1685 struct nand_chip *chip,
1686 const uint8_t *buf, int oob_required)
1687 {
1688 int eccsize = chip->ecc.size;
1689 int eccbytes = chip->ecc.bytes;
1690 uint8_t *oob = chip->oob_poi;
1691 int steps, size;
1692
1693 for (steps = chip->ecc.steps; steps > 0; steps--) {
1694 chip->write_buf(mtd, buf, eccsize);
1695 buf += eccsize;
1696
1697 if (chip->ecc.prepad) {
1698 chip->write_buf(mtd, oob, chip->ecc.prepad);
1699 oob += chip->ecc.prepad;
1700 }
1701
1702 chip->read_buf(mtd, oob, eccbytes);
1703 oob += eccbytes;
1704
1705 if (chip->ecc.postpad) {
1706 chip->write_buf(mtd, oob, chip->ecc.postpad);
1707 oob += chip->ecc.postpad;
1708 }
1709 }
1710
1711 size = mtd->oobsize - (oob - chip->oob_poi);
1712 if (size)
1713 chip->write_buf(mtd, oob, size);
1714
1715 return 0;
1716 }
1717 /**
1718 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1719 * @mtd: mtd info structure
1720 * @chip: nand chip info structure
1721 * @buf: data buffer
1722 * @oob_required: must write chip->oob_poi to OOB
1723 */
1724 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1725 const uint8_t *buf, int oob_required)
1726 {
1727 int i, eccsize = chip->ecc.size;
1728 int eccbytes = chip->ecc.bytes;
1729 int eccsteps = chip->ecc.steps;
1730 uint8_t *ecc_calc = chip->buffers->ecccalc;
1731 const uint8_t *p = buf;
1732 uint32_t *eccpos = chip->ecc.layout->eccpos;
1733
1734 /* Software ECC calculation */
1735 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1736 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1737
1738 for (i = 0; i < chip->ecc.total; i++)
1739 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1740
1741 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1742 }
1743
1744 /**
1745 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1746 * @mtd: mtd info structure
1747 * @chip: nand chip info structure
1748 * @buf: data buffer
1749 * @oob_required: must write chip->oob_poi to OOB
1750 */
1751 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1752 const uint8_t *buf, int oob_required)
1753 {
1754 int i, eccsize = chip->ecc.size;
1755 int eccbytes = chip->ecc.bytes;
1756 int eccsteps = chip->ecc.steps;
1757 uint8_t *ecc_calc = chip->buffers->ecccalc;
1758 const uint8_t *p = buf;
1759 uint32_t *eccpos = chip->ecc.layout->eccpos;
1760
1761 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1762 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1763 chip->write_buf(mtd, p, eccsize);
1764 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1765 }
1766
1767 for (i = 0; i < chip->ecc.total; i++)
1768 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1769
1770 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1771
1772 return 0;
1773 }
1774
1775 /**
1776 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1777 * @mtd: mtd info structure
1778 * @chip: nand chip info structure
1779 * @buf: data buffer
1780 * @oob_required: must write chip->oob_poi to OOB
1781 *
1782 * The hw generator calculates the error syndrome automatically. Therefore we
1783 * need a special oob layout and handling.
1784 */
1785 static int nand_write_page_syndrome(struct mtd_info *mtd,
1786 struct nand_chip *chip,
1787 const uint8_t *buf, int oob_required)
1788 {
1789 int i, eccsize = chip->ecc.size;
1790 int eccbytes = chip->ecc.bytes;
1791 int eccsteps = chip->ecc.steps;
1792 const uint8_t *p = buf;
1793 uint8_t *oob = chip->oob_poi;
1794
1795 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1796
1797 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1798 chip->write_buf(mtd, p, eccsize);
1799
1800 if (chip->ecc.prepad) {
1801 chip->write_buf(mtd, oob, chip->ecc.prepad);
1802 oob += chip->ecc.prepad;
1803 }
1804
1805 chip->ecc.calculate(mtd, p, oob);
1806 chip->write_buf(mtd, oob, eccbytes);
1807 oob += eccbytes;
1808
1809 if (chip->ecc.postpad) {
1810 chip->write_buf(mtd, oob, chip->ecc.postpad);
1811 oob += chip->ecc.postpad;
1812 }
1813 }
1814
1815 /* Calculate remaining oob bytes */
1816 i = mtd->oobsize - (oob - chip->oob_poi);
1817 if (i)
1818 chip->write_buf(mtd, oob, i);
1819
1820 return 0;
1821 }
1822
1823 /**
1824 * nand_write_page - [REPLACEABLE] write one page
1825 * @mtd: MTD device structure
1826 * @chip: NAND chip descriptor
1827 * @buf: the data to write
1828 * @oob_required: must write chip->oob_poi to OOB
1829 * @page: page number to write
1830 * @cached: cached programming
1831 * @raw: use _raw version of write_page
1832 */
1833 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1834 const uint8_t *buf, int oob_required, int page,
1835 int cached, int raw)
1836 {
1837 int status;
1838
1839 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1840
1841 if (unlikely(raw))
1842 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
1843 else
1844 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1845
1846 if (status < 0)
1847 return status;
1848
1849 /*
1850 * Cached progamming disabled for now. Not sure if it's worth the
1851 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
1852 */
1853 cached = 0;
1854
1855 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1856
1857 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1858 status = chip->waitfunc(mtd, chip);
1859 /*
1860 * See if operation failed and additional status checks are
1861 * available.
1862 */
1863 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1864 status = chip->errstat(mtd, chip, FL_WRITING, status,
1865 page);
1866
1867 if (status & NAND_STATUS_FAIL)
1868 return -EIO;
1869 } else {
1870 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1871 status = chip->waitfunc(mtd, chip);
1872 }
1873
1874 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1875 /* Send command to read back the data */
1876 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1877
1878 if (chip->verify_buf(mtd, buf, mtd->writesize))
1879 return -EIO;
1880
1881 /* Make sure the next page prog is preceded by a status read */
1882 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1883 #endif
1884 return 0;
1885 }
1886
1887 /**
1888 * nand_fill_oob - [INTERN] Transfer client buffer to oob
1889 * @mtd: MTD device structure
1890 * @oob: oob data buffer
1891 * @len: oob data write length
1892 * @ops: oob ops structure
1893 */
1894 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
1895 struct mtd_oob_ops *ops)
1896 {
1897 struct nand_chip *chip = mtd->priv;
1898
1899 /*
1900 * Initialise to all 0xFF, to avoid the possibility of left over OOB
1901 * data from a previous OOB read.
1902 */
1903 memset(chip->oob_poi, 0xff, mtd->oobsize);
1904
1905 switch (ops->mode) {
1906
1907 case MTD_OPS_PLACE_OOB:
1908 case MTD_OPS_RAW:
1909 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1910 return oob + len;
1911
1912 case MTD_OPS_AUTO_OOB: {
1913 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1914 uint32_t boffs = 0, woffs = ops->ooboffs;
1915 size_t bytes = 0;
1916
1917 for (; free->length && len; free++, len -= bytes) {
1918 /* Write request not from offset 0? */
1919 if (unlikely(woffs)) {
1920 if (woffs >= free->length) {
1921 woffs -= free->length;
1922 continue;
1923 }
1924 boffs = free->offset + woffs;
1925 bytes = min_t(size_t, len,
1926 (free->length - woffs));
1927 woffs = 0;
1928 } else {
1929 bytes = min_t(size_t, len, free->length);
1930 boffs = free->offset;
1931 }
1932 memcpy(chip->oob_poi + boffs, oob, bytes);
1933 oob += bytes;
1934 }
1935 return oob;
1936 }
1937 default:
1938 BUG();
1939 }
1940 return NULL;
1941 }
1942
1943 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1944
1945 /**
1946 * nand_do_write_ops - [INTERN] NAND write with ECC
1947 * @mtd: MTD device structure
1948 * @to: offset to write to
1949 * @ops: oob operations description structure
1950 *
1951 * NAND write with ECC.
1952 */
1953 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1954 struct mtd_oob_ops *ops)
1955 {
1956 int chipnr, realpage, page, blockmask, column;
1957 struct nand_chip *chip = mtd->priv;
1958 uint32_t writelen = ops->len;
1959
1960 uint32_t oobwritelen = ops->ooblen;
1961 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
1962 mtd->oobavail : mtd->oobsize;
1963
1964 uint8_t *oob = ops->oobbuf;
1965 uint8_t *buf = ops->datbuf;
1966 int ret, subpage;
1967 int oob_required = oob ? 1 : 0;
1968
1969 ops->retlen = 0;
1970 if (!writelen)
1971 return 0;
1972
1973 column = to & (mtd->writesize - 1);
1974 subpage = column || (writelen & (mtd->writesize - 1));
1975
1976 if (subpage && oob)
1977 return -EINVAL;
1978
1979 chipnr = (int)(to >> chip->chip_shift);
1980 chip->select_chip(mtd, chipnr);
1981
1982 /* Check, if it is write protected */
1983 if (nand_check_wp(mtd)) {
1984 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1985 return -EIO;
1986 }
1987
1988 realpage = (int)(to >> chip->page_shift);
1989 page = realpage & chip->pagemask;
1990 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1991
1992 /* Invalidate the page cache, when we write to the cached page */
1993 if (to <= (chip->pagebuf << chip->page_shift) &&
1994 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1995 chip->pagebuf = -1;
1996
1997 /* Don't allow multipage oob writes with offset */
1998 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
1999 return -EINVAL;
2000
2001 while (1) {
2002 WATCHDOG_RESET();
2003
2004 int bytes = mtd->writesize;
2005 int cached = writelen > bytes && page != blockmask;
2006 uint8_t *wbuf = buf;
2007
2008 /* Partial page write? */
2009 if (unlikely(column || writelen < mtd->writesize)) {
2010 cached = 0;
2011 bytes = min_t(int, bytes - column, (int) writelen);
2012 chip->pagebuf = -1;
2013 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2014 memcpy(&chip->buffers->databuf[column], buf, bytes);
2015 wbuf = chip->buffers->databuf;
2016 }
2017
2018 if (unlikely(oob)) {
2019 size_t len = min(oobwritelen, oobmaxlen);
2020 oob = nand_fill_oob(mtd, oob, len, ops);
2021 oobwritelen -= len;
2022 } else {
2023 /* We still need to erase leftover OOB data */
2024 memset(chip->oob_poi, 0xff, mtd->oobsize);
2025 }
2026
2027 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2028 cached, (ops->mode == MTD_OPS_RAW));
2029 if (ret)
2030 break;
2031
2032 writelen -= bytes;
2033 if (!writelen)
2034 break;
2035
2036 column = 0;
2037 buf += bytes;
2038 realpage++;
2039
2040 page = realpage & chip->pagemask;
2041 /* Check, if we cross a chip boundary */
2042 if (!page) {
2043 chipnr++;
2044 chip->select_chip(mtd, -1);
2045 chip->select_chip(mtd, chipnr);
2046 }
2047 }
2048
2049 ops->retlen = ops->len - writelen;
2050 if (unlikely(oob))
2051 ops->oobretlen = ops->ooblen;
2052 return ret;
2053 }
2054
2055 /**
2056 * nand_write - [MTD Interface] NAND write with ECC
2057 * @mtd: MTD device structure
2058 * @to: offset to write to
2059 * @len: number of bytes to write
2060 * @retlen: pointer to variable to store the number of written bytes
2061 * @buf: the data to write
2062 *
2063 * NAND write with ECC.
2064 */
2065 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2066 size_t *retlen, const uint8_t *buf)
2067 {
2068 struct nand_chip *chip = mtd->priv;
2069 struct mtd_oob_ops ops;
2070 int ret;
2071
2072 nand_get_device(chip, mtd, FL_WRITING);
2073 ops.len = len;
2074 ops.datbuf = (uint8_t *)buf;
2075 ops.oobbuf = NULL;
2076 ops.mode = MTD_OPS_PLACE_OOB;
2077 ret = nand_do_write_ops(mtd, to, &ops);
2078 *retlen = ops.retlen;
2079 nand_release_device(mtd);
2080 return ret;
2081 }
2082
2083 /**
2084 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2085 * @mtd: MTD device structure
2086 * @to: offset to write to
2087 * @ops: oob operation description structure
2088 *
2089 * NAND write out-of-band.
2090 */
2091 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2092 struct mtd_oob_ops *ops)
2093 {
2094 int chipnr, page, status, len;
2095 struct nand_chip *chip = mtd->priv;
2096
2097 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2098 __func__, (unsigned int)to, (int)ops->ooblen);
2099
2100 if (ops->mode == MTD_OPS_AUTO_OOB)
2101 len = chip->ecc.layout->oobavail;
2102 else
2103 len = mtd->oobsize;
2104
2105 /* Do not allow write past end of page */
2106 if ((ops->ooboffs + ops->ooblen) > len) {
2107 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2108 "past end of page\n", __func__);
2109 return -EINVAL;
2110 }
2111
2112 if (unlikely(ops->ooboffs >= len)) {
2113 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2114 "write outside oob\n", __func__);
2115 return -EINVAL;
2116 }
2117
2118 /* Do not allow write past end of device */
2119 if (unlikely(to >= mtd->size ||
2120 ops->ooboffs + ops->ooblen >
2121 ((mtd->size >> chip->page_shift) -
2122 (to >> chip->page_shift)) * len)) {
2123 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2124 "end of device\n", __func__);
2125 return -EINVAL;
2126 }
2127
2128 chipnr = (int)(to >> chip->chip_shift);
2129 chip->select_chip(mtd, chipnr);
2130
2131 /* Shift to get page */
2132 page = (int)(to >> chip->page_shift);
2133
2134 /*
2135 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2136 * of my DiskOnChip 2000 test units) will clear the whole data page too
2137 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2138 * it in the doc2000 driver in August 1999. dwmw2.
2139 */
2140 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2141
2142 /* Check, if it is write protected */
2143 if (nand_check_wp(mtd))
2144 return -EROFS;
2145
2146 /* Invalidate the page cache, if we write to the cached page */
2147 if (page == chip->pagebuf)
2148 chip->pagebuf = -1;
2149
2150 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2151
2152 if (ops->mode == MTD_OPS_RAW)
2153 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2154 else
2155 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2156
2157 if (status)
2158 return status;
2159
2160 ops->oobretlen = ops->ooblen;
2161
2162 return 0;
2163 }
2164
2165 /**
2166 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2167 * @mtd: MTD device structure
2168 * @to: offset to write to
2169 * @ops: oob operation description structure
2170 */
2171 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2172 struct mtd_oob_ops *ops)
2173 {
2174 struct nand_chip *chip = mtd->priv;
2175 int ret = -ENOTSUPP;
2176
2177 ops->retlen = 0;
2178
2179 /* Do not allow writes past end of device */
2180 if (ops->datbuf && (to + ops->len) > mtd->size) {
2181 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2182 "end of device\n", __func__);
2183 return -EINVAL;
2184 }
2185
2186 nand_get_device(chip, mtd, FL_WRITING);
2187
2188 switch (ops->mode) {
2189 case MTD_OPS_PLACE_OOB:
2190 case MTD_OPS_AUTO_OOB:
2191 case MTD_OPS_RAW:
2192 break;
2193
2194 default:
2195 goto out;
2196 }
2197
2198 if (!ops->datbuf)
2199 ret = nand_do_write_oob(mtd, to, ops);
2200 else
2201 ret = nand_do_write_ops(mtd, to, ops);
2202
2203 out:
2204 nand_release_device(mtd);
2205 return ret;
2206 }
2207
2208 /**
2209 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2210 * @mtd: MTD device structure
2211 * @page: the page address of the block which will be erased
2212 *
2213 * Standard erase command for NAND chips.
2214 */
2215 static void single_erase_cmd(struct mtd_info *mtd, int page)
2216 {
2217 struct nand_chip *chip = mtd->priv;
2218 /* Send commands to erase a block */
2219 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2220 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2221 }
2222
2223 /**
2224 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2225 * @mtd: MTD device structure
2226 * @page: the page address of the block which will be erased
2227 *
2228 * AND multi block erase command function. Erase 4 consecutive blocks.
2229 */
2230 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2231 {
2232 struct nand_chip *chip = mtd->priv;
2233 /* Send commands to erase a block */
2234 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2235 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2236 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2237 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2238 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2239 }
2240
2241 /**
2242 * nand_erase - [MTD Interface] erase block(s)
2243 * @mtd: MTD device structure
2244 * @instr: erase instruction
2245 *
2246 * Erase one ore more blocks.
2247 */
2248 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2249 {
2250 return nand_erase_nand(mtd, instr, 0);
2251 }
2252
2253 #define BBT_PAGE_MASK 0xffffff3f
2254 /**
2255 * nand_erase_nand - [INTERN] erase block(s)
2256 * @mtd: MTD device structure
2257 * @instr: erase instruction
2258 * @allowbbt: allow erasing the bbt area
2259 *
2260 * Erase one ore more blocks.
2261 */
2262 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2263 int allowbbt)
2264 {
2265 int page, status, pages_per_block, ret, chipnr;
2266 struct nand_chip *chip = mtd->priv;
2267 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2268 unsigned int bbt_masked_page = 0xffffffff;
2269 loff_t len;
2270
2271 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2272 __func__, (unsigned long long)instr->addr,
2273 (unsigned long long)instr->len);
2274
2275 if (check_offs_len(mtd, instr->addr, instr->len))
2276 return -EINVAL;
2277
2278 /* Grab the lock and see if the device is available */
2279 nand_get_device(chip, mtd, FL_ERASING);
2280
2281 /* Shift to get first page */
2282 page = (int)(instr->addr >> chip->page_shift);
2283 chipnr = (int)(instr->addr >> chip->chip_shift);
2284
2285 /* Calculate pages in each block */
2286 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2287
2288 /* Select the NAND device */
2289 chip->select_chip(mtd, chipnr);
2290
2291 /* Check, if it is write protected */
2292 if (nand_check_wp(mtd)) {
2293 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2294 __func__);
2295 instr->state = MTD_ERASE_FAILED;
2296 goto erase_exit;
2297 }
2298
2299 /*
2300 * If BBT requires refresh, set the BBT page mask to see if the BBT
2301 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2302 * can not be matched. This is also done when the bbt is actually
2303 * erased to avoid recursive updates.
2304 */
2305 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2306 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2307
2308 /* Loop through the pages */
2309 len = instr->len;
2310
2311 instr->state = MTD_ERASING;
2312
2313 while (len) {
2314 WATCHDOG_RESET();
2315 /* Check if we have a bad block, we do not erase bad blocks! */
2316 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2317 chip->page_shift, 0, allowbbt)) {
2318 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2319 __func__, page);
2320 instr->state = MTD_ERASE_FAILED;
2321 goto erase_exit;
2322 }
2323
2324 /*
2325 * Invalidate the page cache, if we erase the block which
2326 * contains the current cached page.
2327 */
2328 if (page <= chip->pagebuf && chip->pagebuf <
2329 (page + pages_per_block))
2330 chip->pagebuf = -1;
2331
2332 chip->erase_cmd(mtd, page & chip->pagemask);
2333
2334 status = chip->waitfunc(mtd, chip);
2335
2336 /*
2337 * See if operation failed and additional status checks are
2338 * available
2339 */
2340 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2341 status = chip->errstat(mtd, chip, FL_ERASING,
2342 status, page);
2343
2344 /* See if block erase succeeded */
2345 if (status & NAND_STATUS_FAIL) {
2346 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2347 "page 0x%08x\n", __func__, page);
2348 instr->state = MTD_ERASE_FAILED;
2349 instr->fail_addr =
2350 ((loff_t)page << chip->page_shift);
2351 goto erase_exit;
2352 }
2353
2354 /*
2355 * If BBT requires refresh, set the BBT rewrite flag to the
2356 * page being erased.
2357 */
2358 if (bbt_masked_page != 0xffffffff &&
2359 (page & BBT_PAGE_MASK) == bbt_masked_page)
2360 rewrite_bbt[chipnr] =
2361 ((loff_t)page << chip->page_shift);
2362
2363 /* Increment page address and decrement length */
2364 len -= (1 << chip->phys_erase_shift);
2365 page += pages_per_block;
2366
2367 /* Check, if we cross a chip boundary */
2368 if (len && !(page & chip->pagemask)) {
2369 chipnr++;
2370 chip->select_chip(mtd, -1);
2371 chip->select_chip(mtd, chipnr);
2372
2373 /*
2374 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2375 * page mask to see if this BBT should be rewritten.
2376 */
2377 if (bbt_masked_page != 0xffffffff &&
2378 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2379 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2380 BBT_PAGE_MASK;
2381 }
2382 }
2383 instr->state = MTD_ERASE_DONE;
2384
2385 erase_exit:
2386
2387 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2388
2389 /* Deselect and wake up anyone waiting on the device */
2390 nand_release_device(mtd);
2391
2392 /* Do call back function */
2393 if (!ret)
2394 mtd_erase_callback(instr);
2395
2396 /*
2397 * If BBT requires refresh and erase was successful, rewrite any
2398 * selected bad block tables.
2399 */
2400 if (bbt_masked_page == 0xffffffff || ret)
2401 return ret;
2402
2403 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2404 if (!rewrite_bbt[chipnr])
2405 continue;
2406 /* Update the BBT for chip */
2407 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2408 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2409 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2410 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2411 }
2412
2413 /* Return more or less happy */
2414 return ret;
2415 }
2416
2417 /**
2418 * nand_sync - [MTD Interface] sync
2419 * @mtd: MTD device structure
2420 *
2421 * Sync is actually a wait for chip ready function.
2422 */
2423 static void nand_sync(struct mtd_info *mtd)
2424 {
2425 struct nand_chip *chip = mtd->priv;
2426
2427 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2428
2429 /* Grab the lock and see if the device is available */
2430 nand_get_device(chip, mtd, FL_SYNCING);
2431 /* Release it and go back */
2432 nand_release_device(mtd);
2433 }
2434
2435 /**
2436 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2437 * @mtd: MTD device structure
2438 * @offs: offset relative to mtd start
2439 */
2440 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2441 {
2442 return nand_block_checkbad(mtd, offs, 1, 0);
2443 }
2444
2445 /**
2446 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2447 * @mtd: MTD device structure
2448 * @ofs: offset relative to mtd start
2449 */
2450 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2451 {
2452 struct nand_chip *chip = mtd->priv;
2453 int ret;
2454
2455 ret = nand_block_isbad(mtd, ofs);
2456 if (ret) {
2457 /* If it was bad already, return success and do nothing */
2458 if (ret > 0)
2459 return 0;
2460 return ret;
2461 }
2462
2463 return chip->block_markbad(mtd, ofs);
2464 }
2465
2466 /**
2467 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2468 * @mtd: MTD device structure
2469 * @chip: nand chip info structure
2470 * @addr: feature address.
2471 * @subfeature_param: the subfeature parameters, a four bytes array.
2472 */
2473 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2474 int addr, uint8_t *subfeature_param)
2475 {
2476 int status;
2477
2478 if (!chip->onfi_version)
2479 return -EINVAL;
2480
2481 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2482 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2483 status = chip->waitfunc(mtd, chip);
2484 if (status & NAND_STATUS_FAIL)
2485 return -EIO;
2486 return 0;
2487 }
2488
2489 /**
2490 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2491 * @mtd: MTD device structure
2492 * @chip: nand chip info structure
2493 * @addr: feature address.
2494 * @subfeature_param: the subfeature parameters, a four bytes array.
2495 */
2496 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2497 int addr, uint8_t *subfeature_param)
2498 {
2499 if (!chip->onfi_version)
2500 return -EINVAL;
2501
2502 /* clear the sub feature parameters */
2503 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2504
2505 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2506 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2507 return 0;
2508 }
2509
2510 /* Set default functions */
2511 static void nand_set_defaults(struct nand_chip *chip, int busw)
2512 {
2513 /* check for proper chip_delay setup, set 20us if not */
2514 if (!chip->chip_delay)
2515 chip->chip_delay = 20;
2516
2517 /* check, if a user supplied command function given */
2518 if (chip->cmdfunc == NULL)
2519 chip->cmdfunc = nand_command;
2520
2521 /* check, if a user supplied wait function given */
2522 if (chip->waitfunc == NULL)
2523 chip->waitfunc = nand_wait;
2524
2525 if (!chip->select_chip)
2526 chip->select_chip = nand_select_chip;
2527 if (!chip->read_byte)
2528 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2529 if (!chip->read_word)
2530 chip->read_word = nand_read_word;
2531 if (!chip->block_bad)
2532 chip->block_bad = nand_block_bad;
2533 if (!chip->block_markbad)
2534 chip->block_markbad = nand_default_block_markbad;
2535 if (!chip->write_buf)
2536 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2537 if (!chip->read_buf)
2538 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2539 if (!chip->verify_buf)
2540 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2541 if (!chip->scan_bbt)
2542 chip->scan_bbt = nand_default_bbt;
2543 if (!chip->controller)
2544 chip->controller = &chip->hwcontrol;
2545 }
2546
2547 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2548 /* Sanitize ONFI strings so we can safely print them */
2549 static void sanitize_string(char *s, size_t len)
2550 {
2551 ssize_t i;
2552
2553 /* Null terminate */
2554 s[len - 1] = 0;
2555
2556 /* Remove non printable chars */
2557 for (i = 0; i < len - 1; i++) {
2558 if (s[i] < ' ' || s[i] > 127)
2559 s[i] = '?';
2560 }
2561
2562 /* Remove trailing spaces */
2563 strim(s);
2564 }
2565
2566 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2567 {
2568 int i;
2569 while (len--) {
2570 crc ^= *p++ << 8;
2571 for (i = 0; i < 8; i++)
2572 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2573 }
2574
2575 return crc;
2576 }
2577
2578 /*
2579 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2580 */
2581 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2582 int *busw)
2583 {
2584 struct nand_onfi_params *p = &chip->onfi_params;
2585 int i;
2586 int val;
2587
2588 /* Try ONFI for unknown chip or LP */
2589 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2590 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2591 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2592 return 0;
2593
2594 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2595 for (i = 0; i < 3; i++) {
2596 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2597 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2598 le16_to_cpu(p->crc)) {
2599 pr_info("ONFI param page %d valid\n", i);
2600 break;
2601 }
2602 }
2603
2604 if (i == 3)
2605 return 0;
2606
2607 /* Check version */
2608 val = le16_to_cpu(p->revision);
2609 if (val & (1 << 5))
2610 chip->onfi_version = 23;
2611 else if (val & (1 << 4))
2612 chip->onfi_version = 22;
2613 else if (val & (1 << 3))
2614 chip->onfi_version = 21;
2615 else if (val & (1 << 2))
2616 chip->onfi_version = 20;
2617 else if (val & (1 << 1))
2618 chip->onfi_version = 10;
2619 else
2620 chip->onfi_version = 0;
2621
2622 if (!chip->onfi_version) {
2623 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2624 return 0;
2625 }
2626
2627 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2628 sanitize_string(p->model, sizeof(p->model));
2629 if (!mtd->name)
2630 mtd->name = p->model;
2631 mtd->writesize = le32_to_cpu(p->byte_per_page);
2632 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2633 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2634 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2635 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2636 *busw = 0;
2637 if (le16_to_cpu(p->features) & 1)
2638 *busw = NAND_BUSWIDTH_16;
2639
2640 pr_info("ONFI flash detected\n");
2641 return 1;
2642 }
2643 #else
2644 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2645 struct nand_chip *chip,
2646 int *busw)
2647 {
2648 return 0;
2649 }
2650 #endif
2651
2652 /*
2653 * nand_id_has_period - Check if an ID string has a given wraparound period
2654 * @id_data: the ID string
2655 * @arrlen: the length of the @id_data array
2656 * @period: the period of repitition
2657 *
2658 * Check if an ID string is repeated within a given sequence of bytes at
2659 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2660 * period of 2). This is a helper function for nand_id_len(). Returns non-zero
2661 * if the repetition has a period of @period; otherwise, returns zero.
2662 */
2663 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2664 {
2665 int i, j;
2666 for (i = 0; i < period; i++)
2667 for (j = i + period; j < arrlen; j += period)
2668 if (id_data[i] != id_data[j])
2669 return 0;
2670 return 1;
2671 }
2672
2673 /*
2674 * nand_id_len - Get the length of an ID string returned by CMD_READID
2675 * @id_data: the ID string
2676 * @arrlen: the length of the @id_data array
2677
2678 * Returns the length of the ID string, according to known wraparound/trailing
2679 * zero patterns. If no pattern exists, returns the length of the array.
2680 */
2681 static int nand_id_len(u8 *id_data, int arrlen)
2682 {
2683 int last_nonzero, period;
2684
2685 /* Find last non-zero byte */
2686 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2687 if (id_data[last_nonzero])
2688 break;
2689
2690 /* All zeros */
2691 if (last_nonzero < 0)
2692 return 0;
2693
2694 /* Calculate wraparound period */
2695 for (period = 1; period < arrlen; period++)
2696 if (nand_id_has_period(id_data, arrlen, period))
2697 break;
2698
2699 /* There's a repeated pattern */
2700 if (period < arrlen)
2701 return period;
2702
2703 /* There are trailing zeros */
2704 if (last_nonzero < arrlen - 1)
2705 return last_nonzero + 1;
2706
2707 /* No pattern detected */
2708 return arrlen;
2709 }
2710
2711 /*
2712 * Many new NAND share similar device ID codes, which represent the size of the
2713 * chip. The rest of the parameters must be decoded according to generic or
2714 * manufacturer-specific "extended ID" decoding patterns.
2715 */
2716 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2717 u8 id_data[8], int *busw)
2718 {
2719 int extid, id_len;
2720 /* The 3rd id byte holds MLC / multichip data */
2721 chip->cellinfo = id_data[2];
2722 /* The 4th id byte is the important one */
2723 extid = id_data[3];
2724
2725 id_len = nand_id_len(id_data, 8);
2726
2727 /*
2728 * Field definitions are in the following datasheets:
2729 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2730 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
2731 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
2732 *
2733 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
2734 * ID to decide what to do.
2735 */
2736 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
2737 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2738 id_data[5] != 0x00) {
2739 /* Calc pagesize */
2740 mtd->writesize = 2048 << (extid & 0x03);
2741 extid >>= 2;
2742 /* Calc oobsize */
2743 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
2744 case 1:
2745 mtd->oobsize = 128;
2746 break;
2747 case 2:
2748 mtd->oobsize = 218;
2749 break;
2750 case 3:
2751 mtd->oobsize = 400;
2752 break;
2753 case 4:
2754 mtd->oobsize = 436;
2755 break;
2756 case 5:
2757 mtd->oobsize = 512;
2758 break;
2759 case 6:
2760 default: /* Other cases are "reserved" (unknown) */
2761 mtd->oobsize = 640;
2762 break;
2763 }
2764 extid >>= 2;
2765 /* Calc blocksize */
2766 mtd->erasesize = (128 * 1024) <<
2767 (((extid >> 1) & 0x04) | (extid & 0x03));
2768 *busw = 0;
2769 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
2770 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2771 unsigned int tmp;
2772
2773 /* Calc pagesize */
2774 mtd->writesize = 2048 << (extid & 0x03);
2775 extid >>= 2;
2776 /* Calc oobsize */
2777 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
2778 case 0:
2779 mtd->oobsize = 128;
2780 break;
2781 case 1:
2782 mtd->oobsize = 224;
2783 break;
2784 case 2:
2785 mtd->oobsize = 448;
2786 break;
2787 case 3:
2788 mtd->oobsize = 64;
2789 break;
2790 case 4:
2791 mtd->oobsize = 32;
2792 break;
2793 case 5:
2794 mtd->oobsize = 16;
2795 break;
2796 default:
2797 mtd->oobsize = 640;
2798 break;
2799 }
2800 extid >>= 2;
2801 /* Calc blocksize */
2802 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
2803 if (tmp < 0x03)
2804 mtd->erasesize = (128 * 1024) << tmp;
2805 else if (tmp == 0x03)
2806 mtd->erasesize = 768 * 1024;
2807 else
2808 mtd->erasesize = (64 * 1024) << tmp;
2809 *busw = 0;
2810 } else {
2811 /* Calc pagesize */
2812 mtd->writesize = 1024 << (extid & 0x03);
2813 extid >>= 2;
2814 /* Calc oobsize */
2815 mtd->oobsize = (8 << (extid & 0x01)) *
2816 (mtd->writesize >> 9);
2817 extid >>= 2;
2818 /* Calc blocksize. Blocksize is multiples of 64KiB */
2819 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2820 extid >>= 2;
2821 /* Get buswidth information */
2822 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2823 }
2824 }
2825
2826 /*
2827 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
2828 * decodes a matching ID table entry and assigns the MTD size parameters for
2829 * the chip.
2830 */
2831 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
2832 const struct nand_flash_dev *type, u8 id_data[8],
2833 int *busw)
2834 {
2835 int maf_id = id_data[0];
2836
2837 mtd->erasesize = type->erasesize;
2838 mtd->writesize = type->pagesize;
2839 mtd->oobsize = mtd->writesize / 32;
2840 *busw = type->options & NAND_BUSWIDTH_16;
2841
2842 /*
2843 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
2844 * some Spansion chips have erasesize that conflicts with size
2845 * listed in nand_ids table.
2846 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
2847 */
2848 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
2849 && id_data[6] == 0x00 && id_data[7] == 0x00
2850 && mtd->writesize == 512) {
2851 mtd->erasesize = 128 * 1024;
2852 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
2853 }
2854 }
2855
2856 /*
2857 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
2858 * heuristic patterns using various detected parameters (e.g., manufacturer,
2859 * page size, cell-type information).
2860 */
2861 static void nand_decode_bbm_options(struct mtd_info *mtd,
2862 struct nand_chip *chip, u8 id_data[8])
2863 {
2864 int maf_id = id_data[0];
2865
2866 /* Set the bad block position */
2867 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
2868 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
2869 else
2870 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
2871
2872 /*
2873 * Bad block marker is stored in the last page of each block on Samsung
2874 * and Hynix MLC devices; stored in first two pages of each block on
2875 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
2876 * AMD/Spansion, and Macronix. All others scan only the first page.
2877 */
2878 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2879 (maf_id == NAND_MFR_SAMSUNG ||
2880 maf_id == NAND_MFR_HYNIX))
2881 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
2882 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2883 (maf_id == NAND_MFR_SAMSUNG ||
2884 maf_id == NAND_MFR_HYNIX ||
2885 maf_id == NAND_MFR_TOSHIBA ||
2886 maf_id == NAND_MFR_AMD ||
2887 maf_id == NAND_MFR_MACRONIX)) ||
2888 (mtd->writesize == 2048 &&
2889 maf_id == NAND_MFR_MICRON))
2890 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
2891 }
2892
2893 /*
2894 * Get the flash and manufacturer id and lookup if the type is supported.
2895 */
2896 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2897 struct nand_chip *chip,
2898 int busw,
2899 int *maf_id, int *dev_id,
2900 const struct nand_flash_dev *type)
2901 {
2902 const char *name;
2903 int i, maf_idx;
2904 u8 id_data[8];
2905
2906 /* Select the device */
2907 chip->select_chip(mtd, 0);
2908
2909 /*
2910 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2911 * after power-up.
2912 */
2913 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2914
2915 /* Send the command for reading device ID */
2916 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2917
2918 /* Read manufacturer and device IDs */
2919 *maf_id = chip->read_byte(mtd);
2920 *dev_id = chip->read_byte(mtd);
2921
2922 /*
2923 * Try again to make sure, as some systems the bus-hold or other
2924 * interface concerns can cause random data which looks like a
2925 * possibly credible NAND flash to appear. If the two results do
2926 * not match, ignore the device completely.
2927 */
2928
2929 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2930
2931 /* Read entire ID string */
2932 for (i = 0; i < 8; i++)
2933 id_data[i] = chip->read_byte(mtd);
2934
2935 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2936 pr_info("%s: second ID read did not match "
2937 "%02x,%02x against %02x,%02x\n", __func__,
2938 *maf_id, *dev_id, id_data[0], id_data[1]);
2939 return ERR_PTR(-ENODEV);
2940 }
2941
2942 if (!type)
2943 type = nand_flash_ids;
2944
2945 for (; type->name != NULL; type++)
2946 if (*dev_id == type->id)
2947 break;
2948
2949 chip->onfi_version = 0;
2950 if (!type->name || !type->pagesize) {
2951 /* Check is chip is ONFI compliant */
2952 if (nand_flash_detect_onfi(mtd, chip, &busw))
2953 goto ident_done;
2954 }
2955
2956 if (!type->name)
2957 return ERR_PTR(-ENODEV);
2958
2959 if (!mtd->name)
2960 mtd->name = type->name;
2961
2962 chip->chipsize = (uint64_t)type->chipsize << 20;
2963
2964 if (!type->pagesize && chip->init_size) {
2965 /* Set the pagesize, oobsize, erasesize by the driver */
2966 busw = chip->init_size(mtd, chip, id_data);
2967 } else if (!type->pagesize) {
2968 /* Decode parameters from extended ID */
2969 nand_decode_ext_id(mtd, chip, id_data, &busw);
2970 } else {
2971 nand_decode_id(mtd, chip, type, id_data, &busw);
2972 }
2973 /* Get chip options, preserve non chip based options */
2974 chip->options |= type->options;
2975
2976 /*
2977 * Check if chip is not a Samsung device. Do not clear the
2978 * options for chips which do not have an extended id.
2979 */
2980 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2981 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2982 ident_done:
2983
2984 /* Try to identify manufacturer */
2985 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2986 if (nand_manuf_ids[maf_idx].id == *maf_id)
2987 break;
2988 }
2989
2990 /*
2991 * Check, if buswidth is correct. Hardware drivers should set
2992 * chip correct!
2993 */
2994 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2995 pr_info("NAND device: Manufacturer ID:"
2996 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2997 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2998 pr_warn("NAND bus width %d instead %d bit\n",
2999 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3000 busw ? 16 : 8);
3001 return ERR_PTR(-EINVAL);
3002 }
3003
3004 nand_decode_bbm_options(mtd, chip, id_data);
3005
3006 /* Calculate the address shift from the page size */
3007 chip->page_shift = ffs(mtd->writesize) - 1;
3008 /* Convert chipsize to number of pages per chip -1 */
3009 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3010
3011 chip->bbt_erase_shift = chip->phys_erase_shift =
3012 ffs(mtd->erasesize) - 1;
3013 if (chip->chipsize & 0xffffffff)
3014 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3015 else {
3016 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3017 chip->chip_shift += 32 - 1;
3018 }
3019
3020 chip->badblockbits = 8;
3021
3022 /* Check for AND chips with 4 page planes */
3023 if (chip->options & NAND_4PAGE_ARRAY)
3024 chip->erase_cmd = multi_erase_cmd;
3025 else
3026 chip->erase_cmd = single_erase_cmd;
3027
3028 /* Do not replace user supplied command function! */
3029 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3030 chip->cmdfunc = nand_command_lp;
3031
3032 name = type->name;
3033 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3034 if (chip->onfi_version)
3035 name = chip->onfi_params.model;
3036 #endif
3037 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3038 " page size: %d, OOB size: %d\n",
3039 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3040 name,
3041 mtd->writesize, mtd->oobsize);
3042
3043 return type;
3044 }
3045
3046 /**
3047 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3048 * @mtd: MTD device structure
3049 * @maxchips: number of chips to scan for
3050 * @table: alternative NAND ID table
3051 *
3052 * This is the first phase of the normal nand_scan() function. It reads the
3053 * flash ID and sets up MTD fields accordingly.
3054 *
3055 * The mtd->owner field must be set to the module of the caller.
3056 */
3057 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3058 const struct nand_flash_dev *table)
3059 {
3060 int i, busw, nand_maf_id, nand_dev_id;
3061 struct nand_chip *chip = mtd->priv;
3062 const struct nand_flash_dev *type;
3063
3064 /* Get buswidth to select the correct functions */
3065 busw = chip->options & NAND_BUSWIDTH_16;
3066 /* Set the default functions */
3067 nand_set_defaults(chip, busw);
3068
3069 /* Read the flash type */
3070 type = nand_get_flash_type(mtd, chip, busw,
3071 &nand_maf_id, &nand_dev_id, table);
3072
3073 if (IS_ERR(type)) {
3074 #ifndef CONFIG_SYS_NAND_QUIET_TEST
3075 pr_warn("No NAND device found\n");
3076 #endif
3077 chip->select_chip(mtd, -1);
3078 return PTR_ERR(type);
3079 }
3080
3081 /* Check for a chip array */
3082 for (i = 1; i < maxchips; i++) {
3083 chip->select_chip(mtd, i);
3084 /* See comment in nand_get_flash_type for reset */
3085 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3086 /* Send the command for reading device ID */
3087 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3088 /* Read manufacturer and device IDs */
3089 if (nand_maf_id != chip->read_byte(mtd) ||
3090 nand_dev_id != chip->read_byte(mtd))
3091 break;
3092 }
3093 #ifdef DEBUG
3094 if (i > 1)
3095 pr_info("%d NAND chips detected\n", i);
3096 #endif
3097
3098 /* Store the number of chips and calc total size for mtd */
3099 chip->numchips = i;
3100 mtd->size = i * chip->chipsize;
3101
3102 return 0;
3103 }
3104
3105
3106 /**
3107 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3108 * @mtd: MTD device structure
3109 *
3110 * This is the second phase of the normal nand_scan() function. It fills out
3111 * all the uninitialized function pointers with the defaults and scans for a
3112 * bad block table if appropriate.
3113 */
3114 int nand_scan_tail(struct mtd_info *mtd)
3115 {
3116 int i;
3117 struct nand_chip *chip = mtd->priv;
3118
3119 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3120 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3121 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3122
3123 if (!(chip->options & NAND_OWN_BUFFERS))
3124 chip->buffers = memalign(ARCH_DMA_MINALIGN,
3125 sizeof(*chip->buffers));
3126 if (!chip->buffers)
3127 return -ENOMEM;
3128
3129 /* Set the internal oob buffer location, just after the page data */
3130 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3131
3132 /*
3133 * If no default placement scheme is given, select an appropriate one.
3134 */
3135 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3136 switch (mtd->oobsize) {
3137 case 8:
3138 chip->ecc.layout = &nand_oob_8;
3139 break;
3140 case 16:
3141 chip->ecc.layout = &nand_oob_16;
3142 break;
3143 case 64:
3144 chip->ecc.layout = &nand_oob_64;
3145 break;
3146 case 128:
3147 chip->ecc.layout = &nand_oob_128;
3148 break;
3149 default:
3150 pr_warn("No oob scheme defined for oobsize %d\n",
3151 mtd->oobsize);
3152 }
3153 }
3154
3155 if (!chip->write_page)
3156 chip->write_page = nand_write_page;
3157
3158 /* set for ONFI nand */
3159 if (!chip->onfi_set_features)
3160 chip->onfi_set_features = nand_onfi_set_features;
3161 if (!chip->onfi_get_features)
3162 chip->onfi_get_features = nand_onfi_get_features;
3163
3164 /*
3165 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3166 * selected and we have 256 byte pagesize fallback to software ECC
3167 */
3168
3169 switch (chip->ecc.mode) {
3170 case NAND_ECC_HW_OOB_FIRST:
3171 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3172 if (!chip->ecc.calculate || !chip->ecc.correct ||
3173 !chip->ecc.hwctl) {
3174 pr_warn("No ECC functions supplied; "
3175 "hardware ECC not possible\n");
3176 BUG();
3177 }
3178 if (!chip->ecc.read_page)
3179 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3180
3181 case NAND_ECC_HW:
3182 /* Use standard hwecc read page function? */
3183 if (!chip->ecc.read_page)
3184 chip->ecc.read_page = nand_read_page_hwecc;
3185 if (!chip->ecc.write_page)
3186 chip->ecc.write_page = nand_write_page_hwecc;
3187 if (!chip->ecc.read_page_raw)
3188 chip->ecc.read_page_raw = nand_read_page_raw;
3189 if (!chip->ecc.write_page_raw)
3190 chip->ecc.write_page_raw = nand_write_page_raw;
3191 if (!chip->ecc.read_oob)
3192 chip->ecc.read_oob = nand_read_oob_std;
3193 if (!chip->ecc.write_oob)
3194 chip->ecc.write_oob = nand_write_oob_std;
3195
3196 case NAND_ECC_HW_SYNDROME:
3197 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3198 !chip->ecc.hwctl) &&
3199 (!chip->ecc.read_page ||
3200 chip->ecc.read_page == nand_read_page_hwecc ||
3201 !chip->ecc.write_page ||
3202 chip->ecc.write_page == nand_write_page_hwecc)) {
3203 pr_warn("No ECC functions supplied; "
3204 "hardware ECC not possible\n");
3205 BUG();
3206 }
3207 /* Use standard syndrome read/write page function? */
3208 if (!chip->ecc.read_page)
3209 chip->ecc.read_page = nand_read_page_syndrome;
3210 if (!chip->ecc.write_page)
3211 chip->ecc.write_page = nand_write_page_syndrome;
3212 if (!chip->ecc.read_page_raw)
3213 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3214 if (!chip->ecc.write_page_raw)
3215 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3216 if (!chip->ecc.read_oob)
3217 chip->ecc.read_oob = nand_read_oob_syndrome;
3218 if (!chip->ecc.write_oob)
3219 chip->ecc.write_oob = nand_write_oob_syndrome;
3220
3221 if (mtd->writesize >= chip->ecc.size) {
3222 if (!chip->ecc.strength) {
3223 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3224 BUG();
3225 }
3226 break;
3227 }
3228 pr_warn("%d byte HW ECC not possible on "
3229 "%d byte page size, fallback to SW ECC\n",
3230 chip->ecc.size, mtd->writesize);
3231 chip->ecc.mode = NAND_ECC_SOFT;
3232
3233 case NAND_ECC_SOFT:
3234 chip->ecc.calculate = nand_calculate_ecc;
3235 chip->ecc.correct = nand_correct_data;
3236 chip->ecc.read_page = nand_read_page_swecc;
3237 chip->ecc.read_subpage = nand_read_subpage;
3238 chip->ecc.write_page = nand_write_page_swecc;
3239 chip->ecc.read_page_raw = nand_read_page_raw;
3240 chip->ecc.write_page_raw = nand_write_page_raw;
3241 chip->ecc.read_oob = nand_read_oob_std;
3242 chip->ecc.write_oob = nand_write_oob_std;
3243 if (!chip->ecc.size)
3244 chip->ecc.size = 256;
3245 chip->ecc.bytes = 3;
3246 chip->ecc.strength = 1;
3247 break;
3248
3249 case NAND_ECC_SOFT_BCH:
3250 if (!mtd_nand_has_bch()) {
3251 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3252 return -EINVAL;
3253 }
3254 chip->ecc.calculate = nand_bch_calculate_ecc;
3255 chip->ecc.correct = nand_bch_correct_data;
3256 chip->ecc.read_page = nand_read_page_swecc;
3257 chip->ecc.read_subpage = nand_read_subpage;
3258 chip->ecc.write_page = nand_write_page_swecc;
3259 chip->ecc.read_page_raw = nand_read_page_raw;
3260 chip->ecc.write_page_raw = nand_write_page_raw;
3261 chip->ecc.read_oob = nand_read_oob_std;
3262 chip->ecc.write_oob = nand_write_oob_std;
3263 /*
3264 * Board driver should supply ecc.size and ecc.bytes values to
3265 * select how many bits are correctable; see nand_bch_init()
3266 * for details. Otherwise, default to 4 bits for large page
3267 * devices.
3268 */
3269 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3270 chip->ecc.size = 512;
3271 chip->ecc.bytes = 7;
3272 }
3273 chip->ecc.priv = nand_bch_init(mtd,
3274 chip->ecc.size,
3275 chip->ecc.bytes,
3276 &chip->ecc.layout);
3277 if (!chip->ecc.priv)
3278 pr_warn("BCH ECC initialization failed!\n");
3279 chip->ecc.strength =
3280 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3281 break;
3282
3283 case NAND_ECC_NONE:
3284 pr_warn("NAND_ECC_NONE selected by board driver. "
3285 "This is not recommended !!\n");
3286 chip->ecc.read_page = nand_read_page_raw;
3287 chip->ecc.write_page = nand_write_page_raw;
3288 chip->ecc.read_oob = nand_read_oob_std;
3289 chip->ecc.read_page_raw = nand_read_page_raw;
3290 chip->ecc.write_page_raw = nand_write_page_raw;
3291 chip->ecc.write_oob = nand_write_oob_std;
3292 chip->ecc.size = mtd->writesize;
3293 chip->ecc.bytes = 0;
3294 break;
3295
3296 default:
3297 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3298 BUG();
3299 }
3300
3301 /* For many systems, the standard OOB write also works for raw */
3302 if (!chip->ecc.read_oob_raw)
3303 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3304 if (!chip->ecc.write_oob_raw)
3305 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3306
3307 /*
3308 * The number of bytes available for a client to place data into
3309 * the out of band area.
3310 */
3311 chip->ecc.layout->oobavail = 0;
3312 for (i = 0; chip->ecc.layout->oobfree[i].length
3313 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3314 chip->ecc.layout->oobavail +=
3315 chip->ecc.layout->oobfree[i].length;
3316 mtd->oobavail = chip->ecc.layout->oobavail;
3317
3318 /*
3319 * Set the number of read / write steps for one page depending on ECC
3320 * mode.
3321 */
3322 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3323 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3324 pr_warn("Invalid ECC parameters\n");
3325 BUG();
3326 }
3327 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3328
3329 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3330 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3331 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3332 switch (chip->ecc.steps) {
3333 case 2:
3334 mtd->subpage_sft = 1;
3335 break;
3336 case 4:
3337 case 8:
3338 case 16:
3339 mtd->subpage_sft = 2;
3340 break;
3341 }
3342 }
3343 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3344
3345 /* Initialize state */
3346 chip->state = FL_READY;
3347
3348 /* De-select the device */
3349 chip->select_chip(mtd, -1);
3350
3351 /* Invalidate the pagebuffer reference */
3352 chip->pagebuf = -1;
3353
3354 /* Large page NAND with SOFT_ECC should support subpage reads */
3355 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3356 chip->options |= NAND_SUBPAGE_READ;
3357
3358 /* Fill in remaining MTD driver data */
3359 mtd->type = MTD_NANDFLASH;
3360 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3361 MTD_CAP_NANDFLASH;
3362 mtd->_erase = nand_erase;
3363 mtd->_point = NULL;
3364 mtd->_unpoint = NULL;
3365 mtd->_read = nand_read;
3366 mtd->_write = nand_write;
3367 mtd->_read_oob = nand_read_oob;
3368 mtd->_write_oob = nand_write_oob;
3369 mtd->_sync = nand_sync;
3370 mtd->_lock = NULL;
3371 mtd->_unlock = NULL;
3372 mtd->_block_isbad = nand_block_isbad;
3373 mtd->_block_markbad = nand_block_markbad;
3374
3375 /* propagate ecc info to mtd_info */
3376 mtd->ecclayout = chip->ecc.layout;
3377 mtd->ecc_strength = chip->ecc.strength;
3378 /*
3379 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3380 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3381 * properly set.
3382 */
3383 if (!mtd->bitflip_threshold)
3384 mtd->bitflip_threshold = mtd->ecc_strength;
3385
3386 /* Check, if we should skip the bad block table scan */
3387 if (chip->options & NAND_SKIP_BBTSCAN)
3388 chip->options |= NAND_BBT_SCANNED;
3389
3390 return 0;
3391 }
3392
3393 /**
3394 * nand_scan - [NAND Interface] Scan for the NAND device
3395 * @mtd: MTD device structure
3396 * @maxchips: number of chips to scan for
3397 *
3398 * This fills out all the uninitialized function pointers with the defaults.
3399 * The flash ID is read and the mtd/chip structures are filled with the
3400 * appropriate values. The mtd->owner field must be set to the module of the
3401 * caller.
3402 */
3403 int nand_scan(struct mtd_info *mtd, int maxchips)
3404 {
3405 int ret;
3406
3407 ret = nand_scan_ident(mtd, maxchips, NULL);
3408 if (!ret)
3409 ret = nand_scan_tail(mtd);
3410 return ret;
3411 }
3412
3413 /**
3414 * nand_release - [NAND Interface] Free resources held by the NAND device
3415 * @mtd: MTD device structure
3416 */
3417 void nand_release(struct mtd_info *mtd)
3418 {
3419 struct nand_chip *chip = mtd->priv;
3420
3421 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3422 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3423
3424 #ifdef CONFIG_MTD_PARTITIONS
3425 /* Deregister partitions */
3426 del_mtd_partitions(mtd);
3427 #endif
3428
3429 /* Free bad block table memory */
3430 kfree(chip->bbt);
3431 if (!(chip->options & NAND_OWN_BUFFERS))
3432 kfree(chip->buffers);
3433
3434 /* Free bad block descriptor memory */
3435 if (chip->badblock_pattern && chip->badblock_pattern->options
3436 & NAND_BBT_DYNAMICSTRUCT)
3437 kfree(chip->badblock_pattern);
3438 }
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