]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/fec_mxc.c
2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
33 #include <asm/errno.h>
35 DECLARE_GLOBAL_DATA_PTR
;
38 #error "CONFIG_MII has to be defined!"
44 uint8_t data
[1500]; /**< actual data */
45 int length
; /**< actual length */
46 int used
; /**< buffer in use or not */
47 uint8_t head
[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
50 struct fec_priv gfec
= {
51 .eth
= (struct ethernet_regs
*)IMX_FEC_BASE
,
63 * MII-interface related functions
65 static int fec_miiphy_read(char *dev
, uint8_t phyAddr
, uint8_t regAddr
,
68 struct eth_device
*edev
= eth_get_dev_by_name(dev
);
69 struct fec_priv
*fec
= (struct fec_priv
*)edev
->priv
;
71 uint32_t reg
; /* convenient holder for the PHY register */
72 uint32_t phy
; /* convenient holder for the PHY */
76 * reading from any PHY's register is done by properly
77 * programming the FEC's MII data register.
79 writel(FEC_IEVENT_MII
, &fec
->eth
->ievent
);
80 reg
= regAddr
<< FEC_MII_DATA_RA_SHIFT
;
81 phy
= phyAddr
<< FEC_MII_DATA_PA_SHIFT
;
83 writel(FEC_MII_DATA_ST
| FEC_MII_DATA_OP_RD
| FEC_MII_DATA_TA
|
84 phy
| reg
, &fec
->eth
->mii_data
);
87 * wait for the related interrupt
89 start
= get_timer_masked();
90 while (!(readl(&fec
->eth
->ievent
) & FEC_IEVENT_MII
)) {
91 if (get_timer(start
) > (CONFIG_SYS_HZ
/ 1000)) {
92 printf("Read MDIO failed...\n");
98 * clear mii interrupt bit
100 writel(FEC_IEVENT_MII
, &fec
->eth
->ievent
);
103 * it's now safe to read the PHY's register
105 *retVal
= readl(&fec
->eth
->mii_data
);
106 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr
,
111 static int fec_miiphy_write(char *dev
, uint8_t phyAddr
, uint8_t regAddr
,
114 struct eth_device
*edev
= eth_get_dev_by_name(dev
);
115 struct fec_priv
*fec
= (struct fec_priv
*)edev
->priv
;
117 uint32_t reg
; /* convenient holder for the PHY register */
118 uint32_t phy
; /* convenient holder for the PHY */
121 reg
= regAddr
<< FEC_MII_DATA_RA_SHIFT
;
122 phy
= phyAddr
<< FEC_MII_DATA_PA_SHIFT
;
124 writel(FEC_MII_DATA_ST
| FEC_MII_DATA_OP_WR
|
125 FEC_MII_DATA_TA
| phy
| reg
| data
, &fec
->eth
->mii_data
);
128 * wait for the MII interrupt
130 start
= get_timer_masked();
131 while (!(readl(&fec
->eth
->ievent
) & FEC_IEVENT_MII
)) {
132 if (get_timer(start
) > (CONFIG_SYS_HZ
/ 1000)) {
133 printf("Write MDIO failed...\n");
139 * clear MII interrupt bit
141 writel(FEC_IEVENT_MII
, &fec
->eth
->ievent
);
142 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr
,
148 static int miiphy_restart_aneg(struct eth_device
*dev
)
151 * Wake up from sleep if necessary
152 * Reset PHY, then delay 300ns
154 miiphy_write(dev
->name
, CONFIG_FEC_MXC_PHYADDR
, PHY_MIPGSR
, 0x00FF);
155 miiphy_write(dev
->name
, CONFIG_FEC_MXC_PHYADDR
, PHY_BMCR
,
160 * Set the auto-negotiation advertisement register bits
162 miiphy_write(dev
->name
, CONFIG_FEC_MXC_PHYADDR
, PHY_ANAR
,
163 PHY_ANLPAR_TXFD
| PHY_ANLPAR_TX
| PHY_ANLPAR_10FD
|
164 PHY_ANLPAR_10
| PHY_ANLPAR_PSB_802_3
);
165 miiphy_write(dev
->name
, CONFIG_FEC_MXC_PHYADDR
, PHY_BMCR
,
166 PHY_BMCR_AUTON
| PHY_BMCR_RST_NEG
);
171 static int miiphy_wait_aneg(struct eth_device
*dev
)
177 * Wait for AN completion
179 start
= get_timer_masked();
181 if (get_timer(start
) > (CONFIG_SYS_HZ
* 5)) {
182 printf("%s: Autonegotiation timeout\n", dev
->name
);
186 if (miiphy_read(dev
->name
, CONFIG_FEC_MXC_PHYADDR
,
187 PHY_BMSR
, &status
)) {
188 printf("%s: Autonegotiation failed. status: 0x%04x\n",
192 } while (!(status
& PHY_BMSR_LS
));
196 static int fec_rx_task_enable(struct fec_priv
*fec
)
198 writel(1 << 24, &fec
->eth
->r_des_active
);
202 static int fec_rx_task_disable(struct fec_priv
*fec
)
207 static int fec_tx_task_enable(struct fec_priv
*fec
)
209 writel(1 << 24, &fec
->eth
->x_des_active
);
213 static int fec_tx_task_disable(struct fec_priv
*fec
)
219 * Initialize receive task's buffer descriptors
220 * @param[in] fec all we know about the device yet
221 * @param[in] count receive buffer count to be allocated
222 * @param[in] size size of each receive buffer
223 * @return 0 on success
225 * For this task we need additional memory for the data buffers. And each
226 * data buffer requires some alignment. Thy must be aligned to a specific
227 * boundary each (DB_DATA_ALIGNMENT).
229 static int fec_rbd_init(struct fec_priv
*fec
, int count
, int size
)
234 /* reserve data memory and consider alignment */
235 if (fec
->rdb_ptr
== NULL
)
236 fec
->rdb_ptr
= malloc(size
* count
+ DB_DATA_ALIGNMENT
);
237 p
= (uint32_t)fec
->rdb_ptr
;
239 puts("fec_imx27: not enough malloc memory!\n");
242 memset((void *)p
, 0, size
* count
+ DB_DATA_ALIGNMENT
);
243 p
+= DB_DATA_ALIGNMENT
-1;
244 p
&= ~(DB_DATA_ALIGNMENT
-1);
246 for (ix
= 0; ix
< count
; ix
++) {
247 writel(p
, &fec
->rbd_base
[ix
].data_pointer
);
249 writew(FEC_RBD_EMPTY
, &fec
->rbd_base
[ix
].status
);
250 writew(0, &fec
->rbd_base
[ix
].data_length
);
253 * mark the last RBD to close the ring
255 writew(FEC_RBD_WRAP
| FEC_RBD_EMPTY
, &fec
->rbd_base
[ix
- 1].status
);
262 * Initialize transmit task's buffer descriptors
263 * @param[in] fec all we know about the device yet
265 * Transmit buffers are created externally. We only have to init the BDs here.\n
266 * Note: There is a race condition in the hardware. When only one BD is in
267 * use it must be marked with the WRAP bit to use it for every transmitt.
268 * This bit in combination with the READY bit results into double transmit
269 * of each data buffer. It seems the state machine checks READY earlier then
270 * resetting it after the first transfer.
271 * Using two BDs solves this issue.
273 static void fec_tbd_init(struct fec_priv
*fec
)
275 writew(0x0000, &fec
->tbd_base
[0].status
);
276 writew(FEC_TBD_WRAP
, &fec
->tbd_base
[1].status
);
281 * Mark the given read buffer descriptor as free
282 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
283 * @param[in] pRbd buffer descriptor to mark free again
285 static void fec_rbd_clean(int last
, struct fec_bd
*pRbd
)
288 * Reset buffer descriptor as empty
291 writew(FEC_RBD_WRAP
| FEC_RBD_EMPTY
, &pRbd
->status
);
293 writew(FEC_RBD_EMPTY
, &pRbd
->status
);
297 writew(0, &pRbd
->data_length
);
300 static int fec_get_hwaddr(struct eth_device
*dev
, unsigned char *mac
)
302 struct iim_regs
*iim
= (struct iim_regs
*)IMX_IIM_BASE
;
305 for (i
= 0; i
< 6; i
++)
306 mac
[6-1-i
] = readl(&iim
->iim_bank_area0
[IIM0_MAC
+ i
]);
308 return is_valid_ether_addr(mac
);
311 static int fec_set_hwaddr(struct eth_device
*dev
, unsigned char *mac
)
313 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
315 writel(0, &fec
->eth
->iaddr1
);
316 writel(0, &fec
->eth
->iaddr2
);
317 writel(0, &fec
->eth
->gaddr1
);
318 writel(0, &fec
->eth
->gaddr2
);
321 * Set physical address
323 writel((mac
[0] << 24) + (mac
[1] << 16) + (mac
[2] << 8) + mac
[3],
325 writel((mac
[4] << 24) + (mac
[5] << 16) + 0x8808, &fec
->eth
->paddr2
);
331 * Start the FEC engine
332 * @param[in] dev Our device to handle
334 static int fec_open(struct eth_device
*edev
)
336 struct fec_priv
*fec
= (struct fec_priv
*)edev
->priv
;
338 debug("fec_open: fec_open(dev)\n");
339 /* full-duplex, heartbeat disabled */
340 writel(1 << 2, &fec
->eth
->x_cntrl
);
344 * Enable FEC-Lite controller
346 writel(FEC_ECNTRL_ETHER_EN
, &fec
->eth
->ecntrl
);
348 miiphy_wait_aneg(edev
);
349 miiphy_speed(edev
->name
, CONFIG_FEC_MXC_PHYADDR
);
350 miiphy_duplex(edev
->name
, CONFIG_FEC_MXC_PHYADDR
);
353 * Enable SmartDMA receive task
355 fec_rx_task_enable(fec
);
361 static int fec_init(struct eth_device
*dev
, bd_t
* bd
)
364 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
367 * reserve memory for both buffer descriptor chains at once
368 * Datasheet forces the startaddress of each chain is 16 byte
371 if (fec
->base_ptr
== NULL
)
372 fec
->base_ptr
= malloc((2 + FEC_RBD_NUM
) *
373 sizeof(struct fec_bd
) + DB_ALIGNMENT
);
374 base
= (uint32_t)fec
->base_ptr
;
376 puts("fec_imx27: not enough malloc memory!\n");
379 memset((void *)base
, 0, (2 + FEC_RBD_NUM
) *
380 sizeof(struct fec_bd
) + DB_ALIGNMENT
);
381 base
+= (DB_ALIGNMENT
-1);
382 base
&= ~(DB_ALIGNMENT
-1);
384 fec
->rbd_base
= (struct fec_bd
*)base
;
386 base
+= FEC_RBD_NUM
* sizeof(struct fec_bd
);
388 fec
->tbd_base
= (struct fec_bd
*)base
;
391 * Set interrupt mask register
393 writel(0x00000000, &fec
->eth
->imask
);
396 * Clear FEC-Lite interrupt event register(IEVENT)
398 writel(0xffffffff, &fec
->eth
->ievent
);
402 * Set FEC-Lite receive control register(R_CNTRL):
404 if (fec
->xcv_type
== SEVENWIRE
) {
406 * Frame length=1518; 7-wire mode
408 writel(0x05ee0020, &fec
->eth
->r_cntrl
); /* FIXME 0x05ee0000 */
411 * Frame length=1518; MII mode;
413 writel(0x05ee0024, &fec
->eth
->r_cntrl
); /* FIXME 0x05ee0004 */
415 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
416 * and do not drop the Preamble.
418 writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
419 &fec
->eth
->mii_speed
);
420 debug("fec_init: mii_speed %#lx\n",
421 (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
424 * Set Opcode/Pause Duration Register
426 writel(0x00010020, &fec
->eth
->op_pause
); /* FIXME 0xffff0020; */
427 writel(0x2, &fec
->eth
->x_wmrk
);
429 * Set multicast address filter
431 writel(0x00000000, &fec
->eth
->gaddr1
);
432 writel(0x00000000, &fec
->eth
->gaddr2
);
436 long *mib_ptr
= (long *)(IMX_FEC_BASE
+ 0x200);
437 while (mib_ptr
<= (long *)(IMX_FEC_BASE
+ 0x2FC))
440 /* FIFO receive start register */
441 writel(0x520, &fec
->eth
->r_fstart
);
443 /* size and address of each buffer */
444 writel(FEC_MAX_PKT_SIZE
, &fec
->eth
->emrbr
);
445 writel((uint32_t)fec
->tbd_base
, &fec
->eth
->etdsr
);
446 writel((uint32_t)fec
->rbd_base
, &fec
->eth
->erdsr
);
449 * Initialize RxBD/TxBD rings
451 if (fec_rbd_init(fec
, FEC_RBD_NUM
, FEC_MAX_PKT_SIZE
) < 0) {
453 fec
->base_ptr
= NULL
;
459 if (fec
->xcv_type
!= SEVENWIRE
)
460 miiphy_restart_aneg(dev
);
467 * Halt the FEC engine
468 * @param[in] dev Our device to handle
470 static void fec_halt(struct eth_device
*dev
)
472 struct fec_priv
*fec
= &gfec
;
473 int counter
= 0xffff;
476 * issue graceful stop command to the FEC transmitter if necessary
478 writel(FEC_ECNTRL_RESET
| readl(&fec
->eth
->x_cntrl
),
481 debug("eth_halt: wait for stop regs\n");
483 * wait for graceful stop to register
485 while ((counter
--) && (!(readl(&fec
->eth
->ievent
) & FEC_IEVENT_GRA
)))
486 ; /* FIXME ensure time */
489 * Disable SmartDMA tasks
491 fec_tx_task_disable(fec
);
492 fec_rx_task_disable(fec
);
495 * Disable the Ethernet Controller
496 * Note: this will also reset the BD index counter!
498 writel(0, &fec
->eth
->ecntrl
);
501 debug("eth_halt: done\n");
506 * @param[in] dev Our ethernet device to handle
507 * @param[in] packet Pointer to the data to be transmitted
508 * @param[in] length Data count in bytes
509 * @return 0 on success
511 static int fec_send(struct eth_device
*dev
, volatile void* packet
, int length
)
516 * This routine transmits one frame. This routine only accepts
517 * 6-byte Ethernet addresses.
519 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
522 * Check for valid length of data.
524 if ((length
> 1500) || (length
<= 0)) {
525 printf("Payload (%d) to large!\n", length
);
530 * Setup the transmit buffer
531 * Note: We are always using the first buffer for transmission,
532 * the second will be empty and only used to stop the DMA engine
534 writew(length
, &fec
->tbd_base
[fec
->tbd_index
].data_length
);
535 writel((uint32_t)packet
, &fec
->tbd_base
[fec
->tbd_index
].data_pointer
);
537 * update BD's status now
539 * - is always the last in a chain (means no chain)
540 * - should transmitt the CRC
541 * - might be the last BD in the list, so the address counter should
542 * wrap (-> keep the WRAP flag)
544 status
= readw(&fec
->tbd_base
[fec
->tbd_index
].status
) & FEC_TBD_WRAP
;
545 status
|= FEC_TBD_LAST
| FEC_TBD_TC
| FEC_TBD_READY
;
546 writew(status
, &fec
->tbd_base
[fec
->tbd_index
].status
);
549 * Enable SmartDMA transmit task
551 fec_tx_task_enable(fec
);
554 * wait until frame is sent .
556 while (readw(&fec
->tbd_base
[fec
->tbd_index
].status
) & FEC_TBD_READY
) {
559 debug("fec_send: status 0x%x index %d\n",
560 readw(&fec
->tbd_base
[fec
->tbd_index
].status
),
562 /* for next transmission use the other buffer */
572 * Pull one frame from the card
573 * @param[in] dev Our ethernet device to handle
574 * @return Length of packet read
576 static int fec_recv(struct eth_device
*dev
)
578 struct fec_priv
*fec
= (struct fec_priv
*)dev
->priv
;
579 struct fec_bd
*rbd
= &fec
->rbd_base
[fec
->rbd_index
];
580 unsigned long ievent
;
581 int frame_length
, len
= 0;
584 uchar buff
[FEC_MAX_PKT_SIZE
];
587 * Check if any critical events have happened
589 ievent
= readl(&fec
->eth
->ievent
);
590 writel(ievent
, &fec
->eth
->ievent
);
591 debug("fec_recv: ievent 0x%x\n", ievent
);
592 if (ievent
& FEC_IEVENT_BABR
) {
594 fec_init(dev
, fec
->bd
);
595 printf("some error: 0x%08lx\n", ievent
);
598 if (ievent
& FEC_IEVENT_HBERR
) {
599 /* Heartbeat error */
600 writel(0x00000001 | readl(&fec
->eth
->x_cntrl
),
603 if (ievent
& FEC_IEVENT_GRA
) {
604 /* Graceful stop complete */
605 if (readl(&fec
->eth
->x_cntrl
) & 0x00000001) {
607 writel(~0x00000001 & readl(&fec
->eth
->x_cntrl
),
609 fec_init(dev
, fec
->bd
);
614 * ensure reading the right buffer status
616 bd_status
= readw(&rbd
->status
);
617 debug("fec_recv: status 0x%x\n", bd_status
);
619 if (!(bd_status
& FEC_RBD_EMPTY
)) {
620 if ((bd_status
& FEC_RBD_LAST
) && !(bd_status
& FEC_RBD_ERR
) &&
621 ((readw(&rbd
->data_length
) - 4) > 14)) {
623 * Get buffer address and size
625 frame
= (struct nbuf
*)readl(&rbd
->data_pointer
);
626 frame_length
= readw(&rbd
->data_length
) - 4;
628 * Fill the buffer and pass it to upper layers
630 memcpy(buff
, frame
->data
, frame_length
);
631 NetReceive(buff
, frame_length
);
634 if (bd_status
& FEC_RBD_ERR
)
635 printf("error frame: 0x%08lx 0x%08x\n",
636 (ulong
)rbd
->data_pointer
,
640 * free the current buffer, restart the engine
641 * and move forward to the next buffer
643 fec_rbd_clean(fec
->rbd_index
== (FEC_RBD_NUM
- 1) ? 1 : 0, rbd
);
644 fec_rx_task_enable(fec
);
645 fec
->rbd_index
= (fec
->rbd_index
+ 1) % FEC_RBD_NUM
;
647 debug("fec_recv: stop\n");
652 static int fec_probe(bd_t
*bd
)
654 struct pll_regs
*pll
= (struct pll_regs
*)IMX_PLL_BASE
;
655 struct eth_device
*edev
;
656 struct fec_priv
*fec
= &gfec
;
657 unsigned char ethaddr_str
[20];
658 unsigned char ethaddr
[6];
659 char *tmp
= getenv("ethaddr");
662 /* enable FEC clock */
663 writel(readl(&pll
->pccr1
) | PCCR1_HCLK_FEC
, &pll
->pccr1
);
664 writel(readl(&pll
->pccr0
) | PCCR0_FEC_EN
, &pll
->pccr0
);
666 /* create and fill edev struct */
667 edev
= (struct eth_device
*)malloc(sizeof(struct eth_device
));
669 puts("fec_imx27: not enough malloc memory!\n");
673 edev
->init
= fec_init
;
674 edev
->send
= fec_send
;
675 edev
->recv
= fec_recv
;
676 edev
->halt
= fec_halt
;
678 fec
->eth
= (struct ethernet_regs
*)IMX_FEC_BASE
;
681 fec
->xcv_type
= MII100
;
684 writel(FEC_ECNTRL_RESET
, &fec
->eth
->ecntrl
);
685 while (readl(&fec
->eth
->ecntrl
) & 1)
689 * Set interrupt mask register
691 writel(0x00000000, &fec
->eth
->imask
);
694 * Clear FEC-Lite interrupt event register(IEVENT)
696 writel(0xffffffff, &fec
->eth
->ievent
);
699 * Set FEC-Lite receive control register(R_CNTRL):
702 * Frame length=1518; MII mode;
704 writel(0x05ee0024, &fec
->eth
->r_cntrl
); /* FIXME 0x05ee0004 */
706 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
707 * and do not drop the Preamble.
709 writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
710 &fec
->eth
->mii_speed
);
711 debug("fec_init: mii_speed %#lx\n",
712 (((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
714 sprintf(edev
->name
, "FEC_MXC");
716 miiphy_register(edev
->name
, fec_miiphy_read
, fec_miiphy_write
);
720 if ((NULL
!= tmp
) && (12 <= strlen(tmp
))) {
722 /* convert MAC from string to int */
723 for (i
= 0; i
< 6; i
++) {
724 ethaddr
[i
] = tmp
? simple_strtoul(tmp
, &end
, 16) : 0;
726 tmp
= (*end
) ? end
+ 1 : end
;
728 } else if (fec_get_hwaddr(edev
, ethaddr
) == 0) {
729 printf("got MAC address from EEPROM: %pM\n", ethaddr
);
730 setenv("ethaddr", (char *)ethaddr_str
);
732 memcpy(edev
->enetaddr
, ethaddr
, 6);
733 fec_set_hwaddr(edev
, ethaddr
);
738 int fecmxc_initialize(bd_t
*bd
)
742 debug("eth_init: fec_probe(bd)\n");
743 lout
= fec_probe(bd
);