2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/byteorder.h>
26 #include <asm/unaligned.h>
31 #include <linux/compiler.h>
35 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
36 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
39 static struct ehci_ctrl
{
40 struct ehci_hccr
*hccr
; /* R/O registers, not need for volatile */
41 struct ehci_hcor
*hcor
;
44 struct QH qh_list
__aligned(USB_DMA_MINALIGN
);
45 struct QH periodic_queue
__aligned(USB_DMA_MINALIGN
);
46 uint32_t *periodic_list
;
48 } ehcic
[CONFIG_USB_MAX_CONTROLLER_COUNT
];
50 #define ALIGN_END_ADDR(type, ptr, size) \
51 ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
53 static struct descriptor
{
54 struct usb_hub_descriptor hub
;
55 struct usb_device_descriptor device
;
56 struct usb_linux_config_descriptor config
;
57 struct usb_linux_interface_descriptor interface
;
58 struct usb_endpoint_descriptor endpoint
;
59 } __attribute__ ((packed
)) descriptor
= {
61 0x8, /* bDescLength */
62 0x29, /* bDescriptorType: hub descriptor */
63 2, /* bNrPorts -- runtime modified */
64 0, /* wHubCharacteristics */
65 10, /* bPwrOn2PwrGood */
66 0, /* bHubCntrCurrent */
67 {}, /* Device removable */
68 {} /* at most 7 ports! XXX */
72 1, /* bDescriptorType: UDESC_DEVICE */
73 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
74 9, /* bDeviceClass: UDCLASS_HUB */
75 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
76 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
77 64, /* bMaxPacketSize: 64 bytes */
78 0x0000, /* idVendor */
79 0x0000, /* idProduct */
80 cpu_to_le16(0x0100), /* bcdDevice */
81 1, /* iManufacturer */
83 0, /* iSerialNumber */
84 1 /* bNumConfigurations: 1 */
88 2, /* bDescriptorType: UDESC_CONFIG */
90 1, /* bNumInterface */
91 1, /* bConfigurationValue */
92 0, /* iConfiguration */
93 0x40, /* bmAttributes: UC_SELF_POWER */
98 4, /* bDescriptorType: UDESC_INTERFACE */
99 0, /* bInterfaceNumber */
100 0, /* bAlternateSetting */
101 1, /* bNumEndpoints */
102 9, /* bInterfaceClass: UICLASS_HUB */
103 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
104 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
109 5, /* bDescriptorType: UDESC_ENDPOINT */
110 0x81, /* bEndpointAddress:
111 * UE_DIR_IN | EHCI_INTR_ENDPT
113 3, /* bmAttributes: UE_INTERRUPT */
114 8, /* wMaxPacketSize */
119 #if defined(CONFIG_EHCI_IS_TDI)
120 #define ehci_is_TDI() (1)
122 #define ehci_is_TDI() (0)
125 int __ehci_get_port_speed(struct ehci_hcor
*hcor
, uint32_t reg
)
127 return PORTSC_PSPD(reg
);
130 int ehci_get_port_speed(struct ehci_hcor
*hcor
, uint32_t reg
)
131 __attribute__((weak
, alias("__ehci_get_port_speed")));
133 void __ehci_set_usbmode(int index
)
138 reg_ptr
= (uint32_t *)((u8
*)&ehcic
[index
].hcor
->or_usbcmd
+ USBMODE
);
139 tmp
= ehci_readl(reg_ptr
);
140 tmp
|= USBMODE_CM_HC
;
141 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
144 ehci_writel(reg_ptr
, tmp
);
147 void ehci_set_usbmode(int index
)
148 __attribute__((weak
, alias("__ehci_set_usbmode")));
150 void __ehci_powerup_fixup(uint32_t *status_reg
, uint32_t *reg
)
155 void ehci_powerup_fixup(uint32_t *status_reg
, uint32_t *reg
)
156 __attribute__((weak
, alias("__ehci_powerup_fixup")));
158 static int handshake(uint32_t *ptr
, uint32_t mask
, uint32_t done
, int usec
)
162 result
= ehci_readl(ptr
);
164 if (result
== ~(uint32_t)0)
174 static int ehci_reset(int index
)
179 cmd
= ehci_readl(&ehcic
[index
].hcor
->or_usbcmd
);
180 cmd
= (cmd
& ~CMD_RUN
) | CMD_RESET
;
181 ehci_writel(&ehcic
[index
].hcor
->or_usbcmd
, cmd
);
182 ret
= handshake((uint32_t *)&ehcic
[index
].hcor
->or_usbcmd
,
183 CMD_RESET
, 0, 250 * 1000);
185 printf("EHCI fail to reset\n");
190 ehci_set_usbmode(index
);
192 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
193 cmd
= ehci_readl(&ehcic
[index
].hcor
->or_txfilltuning
);
194 cmd
&= ~TXFIFO_THRESH_MASK
;
195 cmd
|= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH
);
196 ehci_writel(&ehcic
[index
].hcor
->or_txfilltuning
, cmd
);
202 static int ehci_td_buffer(struct qTD
*td
, void *buf
, size_t sz
)
204 uint32_t delta
, next
;
205 uint32_t addr
= (uint32_t)buf
;
208 if (addr
!= ALIGN(addr
, ARCH_DMA_MINALIGN
))
209 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf
);
211 flush_dcache_range(addr
, ALIGN(addr
+ sz
, ARCH_DMA_MINALIGN
));
214 while (idx
< QT_BUFFER_CNT
) {
215 td
->qt_buffer
[idx
] = cpu_to_hc32(addr
);
216 td
->qt_buffer_hi
[idx
] = 0;
217 next
= (addr
+ EHCI_PAGE_SIZE
) & ~(EHCI_PAGE_SIZE
- 1);
226 if (idx
== QT_BUFFER_CNT
) {
227 printf("out of buffer pointers (%u bytes left)\n", sz
);
234 static inline u8
ehci_encode_speed(enum usb_device_speed speed
)
236 #define QH_HIGH_SPEED 2
237 #define QH_FULL_SPEED 0
238 #define QH_LOW_SPEED 1
239 if (speed
== USB_SPEED_HIGH
)
240 return QH_HIGH_SPEED
;
241 if (speed
== USB_SPEED_LOW
)
243 return QH_FULL_SPEED
;
247 ehci_submit_async(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
248 int length
, struct devrequest
*req
)
250 ALLOC_ALIGN_BUFFER(struct QH
, qh
, 1, USB_DMA_MINALIGN
);
254 volatile struct qTD
*vtd
;
257 uint32_t endpt
, maxpacket
, token
, usbsts
;
262 struct ehci_ctrl
*ctrl
= dev
->controller
;
264 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev
, pipe
,
265 buffer
, length
, req
);
267 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
268 req
->request
, req
->request
,
269 req
->requesttype
, req
->requesttype
,
270 le16_to_cpu(req
->value
), le16_to_cpu(req
->value
),
271 le16_to_cpu(req
->index
));
273 #define PKT_ALIGN 512
275 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
276 * described by a transfer descriptor (the qTD). The qTDs form a linked
277 * list with a queue head (QH).
279 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
280 * have its beginning in a qTD transfer and its end in the following
281 * one, so the qTD transfer lengths have to be chosen accordingly.
283 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
284 * single pages. The first data buffer can start at any offset within a
285 * page (not considering the cache-line alignment issues), while the
286 * following buffers must be page-aligned. There is no alignment
287 * constraint on the size of a qTD transfer.
290 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
292 if (length
> 0 || req
== NULL
) {
294 * Determine the qTD transfer size that will be used for the
295 * data payload (not considering the first qTD transfer, which
296 * may be longer or shorter, and the final one, which may be
299 * In order to keep each packet within a qTD transfer, the qTD
300 * transfer size is aligned to PKT_ALIGN, which is a multiple of
301 * wMaxPacketSize (except in some cases for interrupt transfers,
302 * see comment in submit_int_msg()).
304 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
305 * QT_BUFFER_CNT full pages will be used.
307 int xfr_sz
= QT_BUFFER_CNT
;
309 * However, if the input buffer is not aligned to PKT_ALIGN, the
310 * qTD transfer size will be one page shorter, and the first qTD
311 * data buffer of each transfer will be page-unaligned.
313 if ((uint32_t)buffer
& (PKT_ALIGN
- 1))
315 /* Convert the qTD transfer size to bytes. */
316 xfr_sz
*= EHCI_PAGE_SIZE
;
318 * Approximate by excess the number of qTDs that will be
319 * required for the data payload. The exact formula is way more
320 * complicated and saves at most 2 qTDs, i.e. a total of 128
323 qtd_count
+= 2 + length
/ xfr_sz
;
326 * Threshold value based on the worst-case total size of the allocated qTDs for
327 * a mass-storage transfer of 65535 blocks of 512 bytes.
329 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
330 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
332 qtd
= memalign(USB_DMA_MINALIGN
, qtd_count
* sizeof(struct qTD
));
334 printf("unable to allocate TDs\n");
338 memset(qh
, 0, sizeof(struct QH
));
339 memset(qtd
, 0, qtd_count
* sizeof(*qtd
));
341 toggle
= usb_gettoggle(dev
, usb_pipeendpoint(pipe
), usb_pipeout(pipe
));
344 * Setup QH (3.6 in ehci-r10.pdf)
346 * qh_link ................. 03-00 H
347 * qh_endpt1 ............... 07-04 H
348 * qh_endpt2 ............... 0B-08 H
350 * qh_overlay.qt_next ...... 13-10 H
351 * - qh_overlay.qt_altnext
353 qh
->qh_link
= cpu_to_hc32((uint32_t)&ctrl
->qh_list
| QH_LINK_TYPE_QH
);
354 c
= (dev
->speed
!= USB_SPEED_HIGH
) && !usb_pipeendpoint(pipe
);
355 maxpacket
= usb_maxpacket(dev
, pipe
);
356 endpt
= QH_ENDPT1_RL(8) | QH_ENDPT1_C(c
) |
357 QH_ENDPT1_MAXPKTLEN(maxpacket
) | QH_ENDPT1_H(0) |
358 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD
) |
359 QH_ENDPT1_EPS(ehci_encode_speed(dev
->speed
)) |
360 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe
)) | QH_ENDPT1_I(0) |
361 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe
));
362 qh
->qh_endpt1
= cpu_to_hc32(endpt
);
363 endpt
= QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev
->portnr
) |
364 QH_ENDPT2_HUBADDR(dev
->parent
->devnum
) |
365 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
366 qh
->qh_endpt2
= cpu_to_hc32(endpt
);
367 qh
->qh_overlay
.qt_next
= cpu_to_hc32(QT_NEXT_TERMINATE
);
369 tdp
= &qh
->qh_overlay
.qt_next
;
373 * Setup request qTD (3.5 in ehci-r10.pdf)
375 * qt_next ................ 03-00 H
376 * qt_altnext ............. 07-04 H
377 * qt_token ............... 0B-08 H
379 * [ buffer, buffer_hi ] loaded with "req".
381 qtd
[qtd_counter
].qt_next
= cpu_to_hc32(QT_NEXT_TERMINATE
);
382 qtd
[qtd_counter
].qt_altnext
= cpu_to_hc32(QT_NEXT_TERMINATE
);
383 token
= QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req
)) |
384 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
385 QT_TOKEN_PID(QT_TOKEN_PID_SETUP
) |
386 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE
);
387 qtd
[qtd_counter
].qt_token
= cpu_to_hc32(token
);
388 if (ehci_td_buffer(&qtd
[qtd_counter
], req
, sizeof(*req
))) {
389 printf("unable to construct SETUP TD\n");
392 /* Update previous qTD! */
393 *tdp
= cpu_to_hc32((uint32_t)&qtd
[qtd_counter
]);
394 tdp
= &qtd
[qtd_counter
++].qt_next
;
398 if (length
> 0 || req
== NULL
) {
399 uint8_t *buf_ptr
= buffer
;
400 int left_length
= length
;
404 * Determine the size of this qTD transfer. By default,
405 * QT_BUFFER_CNT full pages can be used.
407 int xfr_bytes
= QT_BUFFER_CNT
* EHCI_PAGE_SIZE
;
409 * However, if the input buffer is not page-aligned, the
410 * portion of the first page before the buffer start
411 * offset within that page is unusable.
413 xfr_bytes
-= (uint32_t)buf_ptr
& (EHCI_PAGE_SIZE
- 1);
415 * In order to keep each packet within a qTD transfer,
416 * align the qTD transfer size to PKT_ALIGN.
418 xfr_bytes
&= ~(PKT_ALIGN
- 1);
420 * This transfer may be shorter than the available qTD
421 * transfer size that has just been computed.
423 xfr_bytes
= min(xfr_bytes
, left_length
);
426 * Setup request qTD (3.5 in ehci-r10.pdf)
428 * qt_next ................ 03-00 H
429 * qt_altnext ............. 07-04 H
430 * qt_token ............... 0B-08 H
432 * [ buffer, buffer_hi ] loaded with "buffer".
434 qtd
[qtd_counter
].qt_next
=
435 cpu_to_hc32(QT_NEXT_TERMINATE
);
436 qtd
[qtd_counter
].qt_altnext
=
437 cpu_to_hc32(QT_NEXT_TERMINATE
);
438 token
= QT_TOKEN_DT(toggle
) |
439 QT_TOKEN_TOTALBYTES(xfr_bytes
) |
440 QT_TOKEN_IOC(req
== NULL
) | QT_TOKEN_CPAGE(0) |
442 QT_TOKEN_PID(usb_pipein(pipe
) ?
443 QT_TOKEN_PID_IN
: QT_TOKEN_PID_OUT
) |
444 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE
);
445 qtd
[qtd_counter
].qt_token
= cpu_to_hc32(token
);
446 if (ehci_td_buffer(&qtd
[qtd_counter
], buf_ptr
,
448 printf("unable to construct DATA TD\n");
451 /* Update previous qTD! */
452 *tdp
= cpu_to_hc32((uint32_t)&qtd
[qtd_counter
]);
453 tdp
= &qtd
[qtd_counter
++].qt_next
;
455 * Data toggle has to be adjusted since the qTD transfer
456 * size is not always an even multiple of
459 if ((xfr_bytes
/ maxpacket
) & 1)
461 buf_ptr
+= xfr_bytes
;
462 left_length
-= xfr_bytes
;
463 } while (left_length
> 0);
468 * Setup request qTD (3.5 in ehci-r10.pdf)
470 * qt_next ................ 03-00 H
471 * qt_altnext ............. 07-04 H
472 * qt_token ............... 0B-08 H
474 qtd
[qtd_counter
].qt_next
= cpu_to_hc32(QT_NEXT_TERMINATE
);
475 qtd
[qtd_counter
].qt_altnext
= cpu_to_hc32(QT_NEXT_TERMINATE
);
476 token
= QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
477 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
478 QT_TOKEN_PID(usb_pipein(pipe
) ?
479 QT_TOKEN_PID_OUT
: QT_TOKEN_PID_IN
) |
480 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE
);
481 qtd
[qtd_counter
].qt_token
= cpu_to_hc32(token
);
482 /* Update previous qTD! */
483 *tdp
= cpu_to_hc32((uint32_t)&qtd
[qtd_counter
]);
484 tdp
= &qtd
[qtd_counter
++].qt_next
;
487 ctrl
->qh_list
.qh_link
= cpu_to_hc32((uint32_t)qh
| QH_LINK_TYPE_QH
);
490 flush_dcache_range((uint32_t)&ctrl
->qh_list
,
491 ALIGN_END_ADDR(struct QH
, &ctrl
->qh_list
, 1));
492 flush_dcache_range((uint32_t)qh
, ALIGN_END_ADDR(struct QH
, qh
, 1));
493 flush_dcache_range((uint32_t)qtd
,
494 ALIGN_END_ADDR(struct qTD
, qtd
, qtd_count
));
496 /* Set async. queue head pointer. */
497 ehci_writel(&ctrl
->hcor
->or_asynclistaddr
, (uint32_t)&ctrl
->qh_list
);
499 usbsts
= ehci_readl(&ctrl
->hcor
->or_usbsts
);
500 ehci_writel(&ctrl
->hcor
->or_usbsts
, (usbsts
& 0x3f));
502 /* Enable async. schedule. */
503 cmd
= ehci_readl(&ctrl
->hcor
->or_usbcmd
);
505 ehci_writel(&ctrl
->hcor
->or_usbcmd
, cmd
);
507 ret
= handshake((uint32_t *)&ctrl
->hcor
->or_usbsts
, STS_ASS
, STS_ASS
,
510 printf("EHCI fail timeout STS_ASS set\n");
514 /* Wait for TDs to be processed. */
516 vtd
= &qtd
[qtd_counter
- 1];
517 timeout
= USB_TIMEOUT_MS(pipe
);
519 /* Invalidate dcache */
520 invalidate_dcache_range((uint32_t)&ctrl
->qh_list
,
521 ALIGN_END_ADDR(struct QH
, &ctrl
->qh_list
, 1));
522 invalidate_dcache_range((uint32_t)qh
,
523 ALIGN_END_ADDR(struct QH
, qh
, 1));
524 invalidate_dcache_range((uint32_t)qtd
,
525 ALIGN_END_ADDR(struct qTD
, qtd
, qtd_count
));
527 token
= hc32_to_cpu(vtd
->qt_token
);
528 if (!(QT_TOKEN_GET_STATUS(token
) & QT_TOKEN_STATUS_ACTIVE
))
531 } while (get_timer(ts
) < timeout
);
534 * Invalidate the memory area occupied by buffer
535 * Don't try to fix the buffer alignment, if it isn't properly
536 * aligned it's upper layer's fault so let invalidate_dcache_range()
537 * vow about it. But we have to fix the length as it's actual
538 * transfer length and can be unaligned. This is potentially
539 * dangerous operation, it's responsibility of the calling
540 * code to make sure enough space is reserved.
542 invalidate_dcache_range((uint32_t)buffer
,
543 ALIGN((uint32_t)buffer
+ length
, ARCH_DMA_MINALIGN
));
545 /* Check that the TD processing happened */
546 if (QT_TOKEN_GET_STATUS(token
) & QT_TOKEN_STATUS_ACTIVE
)
547 printf("EHCI timed out on TD - token=%#x\n", token
);
549 /* Disable async schedule. */
550 cmd
= ehci_readl(&ctrl
->hcor
->or_usbcmd
);
552 ehci_writel(&ctrl
->hcor
->or_usbcmd
, cmd
);
554 ret
= handshake((uint32_t *)&ctrl
->hcor
->or_usbsts
, STS_ASS
, 0,
557 printf("EHCI fail timeout STS_ASS reset\n");
561 token
= hc32_to_cpu(qh
->qh_overlay
.qt_token
);
562 if (!(QT_TOKEN_GET_STATUS(token
) & QT_TOKEN_STATUS_ACTIVE
)) {
563 debug("TOKEN=%#x\n", token
);
564 switch (QT_TOKEN_GET_STATUS(token
) &
565 ~(QT_TOKEN_STATUS_SPLITXSTATE
| QT_TOKEN_STATUS_PERR
)) {
567 toggle
= QT_TOKEN_GET_DT(token
);
568 usb_settoggle(dev
, usb_pipeendpoint(pipe
),
569 usb_pipeout(pipe
), toggle
);
572 case QT_TOKEN_STATUS_HALTED
:
573 dev
->status
= USB_ST_STALLED
;
575 case QT_TOKEN_STATUS_ACTIVE
| QT_TOKEN_STATUS_DATBUFERR
:
576 case QT_TOKEN_STATUS_DATBUFERR
:
577 dev
->status
= USB_ST_BUF_ERR
;
579 case QT_TOKEN_STATUS_HALTED
| QT_TOKEN_STATUS_BABBLEDET
:
580 case QT_TOKEN_STATUS_BABBLEDET
:
581 dev
->status
= USB_ST_BABBLE_DET
;
584 dev
->status
= USB_ST_CRC_ERR
;
585 if (QT_TOKEN_GET_STATUS(token
) & QT_TOKEN_STATUS_HALTED
)
586 dev
->status
|= USB_ST_STALLED
;
589 dev
->act_len
= length
- QT_TOKEN_GET_TOTALBYTES(token
);
592 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
593 dev
->devnum
, ehci_readl(&ctrl
->hcor
->or_usbsts
),
594 ehci_readl(&ctrl
->hcor
->or_portsc
[0]),
595 ehci_readl(&ctrl
->hcor
->or_portsc
[1]));
599 return (dev
->status
!= USB_ST_NOT_PROC
) ? 0 : -1;
606 __weak
uint32_t *ehci_get_portsc_register(struct ehci_hcor
*hcor
, int port
)
608 if (port
< 0 || port
>= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS
) {
609 /* Printing the message would cause a scan failure! */
610 debug("The request port(%u) is not configured\n", port
);
614 return (uint32_t *)&hcor
->or_portsc
[port
];
618 ehci_submit_root(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
619 int length
, struct devrequest
*req
)
626 uint32_t *status_reg
;
627 int port
= le16_to_cpu(req
->index
) & 0xff;
628 struct ehci_ctrl
*ctrl
= dev
->controller
;
632 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
633 req
->request
, req
->request
,
634 req
->requesttype
, req
->requesttype
,
635 le16_to_cpu(req
->value
), le16_to_cpu(req
->index
));
637 typeReq
= req
->request
| req
->requesttype
<< 8;
640 case USB_REQ_GET_STATUS
| ((USB_RT_PORT
| USB_DIR_IN
) << 8):
641 case USB_REQ_SET_FEATURE
| ((USB_DIR_OUT
| USB_RT_PORT
) << 8):
642 case USB_REQ_CLEAR_FEATURE
| ((USB_DIR_OUT
| USB_RT_PORT
) << 8):
643 status_reg
= ehci_get_portsc_register(ctrl
->hcor
, port
- 1);
653 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
654 switch (le16_to_cpu(req
->value
) >> 8) {
656 debug("USB_DT_DEVICE request\n");
657 srcptr
= &descriptor
.device
;
658 srclen
= descriptor
.device
.bLength
;
661 debug("USB_DT_CONFIG config\n");
662 srcptr
= &descriptor
.config
;
663 srclen
= descriptor
.config
.bLength
+
664 descriptor
.interface
.bLength
+
665 descriptor
.endpoint
.bLength
;
668 debug("USB_DT_STRING config\n");
669 switch (le16_to_cpu(req
->value
) & 0xff) {
670 case 0: /* Language */
675 srcptr
= "\16\3u\0-\0b\0o\0o\0t\0";
678 case 2: /* Product */
679 srcptr
= "\52\3E\0H\0C\0I\0 "
681 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
685 debug("unknown value DT_STRING %x\n",
686 le16_to_cpu(req
->value
));
691 debug("unknown value %x\n", le16_to_cpu(req
->value
));
695 case USB_REQ_GET_DESCRIPTOR
| ((USB_DIR_IN
| USB_RT_HUB
) << 8):
696 switch (le16_to_cpu(req
->value
) >> 8) {
698 debug("USB_DT_HUB config\n");
699 srcptr
= &descriptor
.hub
;
700 srclen
= descriptor
.hub
.bLength
;
703 debug("unknown value %x\n", le16_to_cpu(req
->value
));
707 case USB_REQ_SET_ADDRESS
| (USB_RECIP_DEVICE
<< 8):
708 debug("USB_REQ_SET_ADDRESS\n");
709 ctrl
->rootdev
= le16_to_cpu(req
->value
);
711 case DeviceOutRequest
| USB_REQ_SET_CONFIGURATION
:
712 debug("USB_REQ_SET_CONFIGURATION\n");
715 case USB_REQ_GET_STATUS
| ((USB_DIR_IN
| USB_RT_HUB
) << 8):
716 tmpbuf
[0] = 1; /* USB_STATUS_SELFPOWERED */
721 case USB_REQ_GET_STATUS
| ((USB_RT_PORT
| USB_DIR_IN
) << 8):
722 memset(tmpbuf
, 0, 4);
723 reg
= ehci_readl(status_reg
);
724 if (reg
& EHCI_PS_CS
)
725 tmpbuf
[0] |= USB_PORT_STAT_CONNECTION
;
726 if (reg
& EHCI_PS_PE
)
727 tmpbuf
[0] |= USB_PORT_STAT_ENABLE
;
728 if (reg
& EHCI_PS_SUSP
)
729 tmpbuf
[0] |= USB_PORT_STAT_SUSPEND
;
730 if (reg
& EHCI_PS_OCA
)
731 tmpbuf
[0] |= USB_PORT_STAT_OVERCURRENT
;
732 if (reg
& EHCI_PS_PR
)
733 tmpbuf
[0] |= USB_PORT_STAT_RESET
;
734 if (reg
& EHCI_PS_PP
)
735 tmpbuf
[1] |= USB_PORT_STAT_POWER
>> 8;
738 switch (ehci_get_port_speed(ctrl
->hcor
, reg
)) {
742 tmpbuf
[1] |= USB_PORT_STAT_LOW_SPEED
>> 8;
746 tmpbuf
[1] |= USB_PORT_STAT_HIGH_SPEED
>> 8;
750 tmpbuf
[1] |= USB_PORT_STAT_HIGH_SPEED
>> 8;
753 if (reg
& EHCI_PS_CSC
)
754 tmpbuf
[2] |= USB_PORT_STAT_C_CONNECTION
;
755 if (reg
& EHCI_PS_PEC
)
756 tmpbuf
[2] |= USB_PORT_STAT_C_ENABLE
;
757 if (reg
& EHCI_PS_OCC
)
758 tmpbuf
[2] |= USB_PORT_STAT_C_OVERCURRENT
;
759 if (ctrl
->portreset
& (1 << port
))
760 tmpbuf
[2] |= USB_PORT_STAT_C_RESET
;
765 case USB_REQ_SET_FEATURE
| ((USB_DIR_OUT
| USB_RT_PORT
) << 8):
766 reg
= ehci_readl(status_reg
);
767 reg
&= ~EHCI_PS_CLEAR
;
768 switch (le16_to_cpu(req
->value
)) {
769 case USB_PORT_FEAT_ENABLE
:
771 ehci_writel(status_reg
, reg
);
773 case USB_PORT_FEAT_POWER
:
774 if (HCS_PPC(ehci_readl(&ctrl
->hccr
->cr_hcsparams
))) {
776 ehci_writel(status_reg
, reg
);
779 case USB_PORT_FEAT_RESET
:
780 if ((reg
& (EHCI_PS_PE
| EHCI_PS_CS
)) == EHCI_PS_CS
&&
782 EHCI_PS_IS_LOWSPEED(reg
)) {
783 /* Low speed device, give up ownership. */
784 debug("port %d low speed --> companion\n",
787 ehci_writel(status_reg
, reg
);
794 ehci_writel(status_reg
, reg
);
796 * caller must wait, then call GetPortStatus
797 * usb 2.0 specification say 50 ms resets on
800 ehci_powerup_fixup(status_reg
, ®
);
802 ehci_writel(status_reg
, reg
& ~EHCI_PS_PR
);
804 * A host controller must terminate the reset
805 * and stabilize the state of the port within
808 ret
= handshake(status_reg
, EHCI_PS_PR
, 0,
811 ctrl
->portreset
|= 1 << port
;
813 printf("port(%d) reset error\n",
817 case USB_PORT_FEAT_TEST
:
819 reg
|= ((le16_to_cpu(req
->index
) >> 8) & 0xf) << 16;
820 ehci_writel(status_reg
, reg
);
823 debug("unknown feature %x\n", le16_to_cpu(req
->value
));
826 /* unblock posted writes */
827 (void) ehci_readl(&ctrl
->hcor
->or_usbcmd
);
829 case USB_REQ_CLEAR_FEATURE
| ((USB_DIR_OUT
| USB_RT_PORT
) << 8):
830 reg
= ehci_readl(status_reg
);
831 reg
&= ~EHCI_PS_CLEAR
;
832 switch (le16_to_cpu(req
->value
)) {
833 case USB_PORT_FEAT_ENABLE
:
836 case USB_PORT_FEAT_C_ENABLE
:
839 case USB_PORT_FEAT_POWER
:
840 if (HCS_PPC(ehci_readl(&ctrl
->hccr
->cr_hcsparams
)))
843 case USB_PORT_FEAT_C_CONNECTION
:
846 case USB_PORT_FEAT_OVER_CURRENT
:
849 case USB_PORT_FEAT_C_RESET
:
850 ctrl
->portreset
&= ~(1 << port
);
853 debug("unknown feature %x\n", le16_to_cpu(req
->value
));
856 ehci_writel(status_reg
, reg
);
857 /* unblock posted write */
858 (void) ehci_readl(&ctrl
->hcor
->or_usbcmd
);
861 debug("Unknown request\n");
866 len
= min3(srclen
, le16_to_cpu(req
->length
), length
);
867 if (srcptr
!= NULL
&& len
> 0)
868 memcpy(buffer
, srcptr
, len
);
877 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
878 req
->requesttype
, req
->request
, le16_to_cpu(req
->value
),
879 le16_to_cpu(req
->index
), le16_to_cpu(req
->length
));
882 dev
->status
= USB_ST_STALLED
;
886 int usb_lowlevel_stop(int index
)
888 return ehci_hcd_stop(index
);
891 int usb_lowlevel_init(int index
, void **controller
)
899 if (ehci_hcd_init(index
, &ehcic
[index
].hccr
, &ehcic
[index
].hcor
))
902 /* EHCI spec section 4.1 */
903 if (ehci_reset(index
))
906 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
907 if (ehci_hcd_init(index
, &ehcic
[index
].hccr
, &ehcic
[index
].hcor
))
910 /* Set the high address word (aka segment) for 64-bit controller */
911 if (ehci_readl(&ehcic
[index
].hccr
->cr_hccparams
) & 1)
912 ehci_writel(ehcic
[index
].hcor
->or_ctrldssegment
, 0);
914 qh_list
= &ehcic
[index
].qh_list
;
916 /* Set head of reclaim list */
917 memset(qh_list
, 0, sizeof(*qh_list
));
918 qh_list
->qh_link
= cpu_to_hc32((uint32_t)qh_list
| QH_LINK_TYPE_QH
);
919 qh_list
->qh_endpt1
= cpu_to_hc32(QH_ENDPT1_H(1) |
920 QH_ENDPT1_EPS(USB_SPEED_HIGH
));
921 qh_list
->qh_curtd
= cpu_to_hc32(QT_NEXT_TERMINATE
);
922 qh_list
->qh_overlay
.qt_next
= cpu_to_hc32(QT_NEXT_TERMINATE
);
923 qh_list
->qh_overlay
.qt_altnext
= cpu_to_hc32(QT_NEXT_TERMINATE
);
924 qh_list
->qh_overlay
.qt_token
=
925 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED
));
927 /* Set async. queue head pointer. */
928 ehci_writel(&ehcic
[index
].hcor
->or_asynclistaddr
, (uint32_t)qh_list
);
931 * Set up periodic list
932 * Step 1: Parent QH for all periodic transfers.
934 periodic
= &ehcic
[index
].periodic_queue
;
935 memset(periodic
, 0, sizeof(*periodic
));
936 periodic
->qh_link
= cpu_to_hc32(QH_LINK_TERMINATE
);
937 periodic
->qh_overlay
.qt_next
= cpu_to_hc32(QT_NEXT_TERMINATE
);
938 periodic
->qh_overlay
.qt_altnext
= cpu_to_hc32(QT_NEXT_TERMINATE
);
941 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
942 * In particular, device specifications on polling frequency
943 * are disregarded. Keyboards seem to send NAK/NYet reliably
944 * when polled with an empty buffer.
946 * Split Transactions will be spread across microframes using
949 ehcic
[index
].periodic_list
= memalign(4096, 1024*4);
950 if (!ehcic
[index
].periodic_list
)
952 for (i
= 0; i
< 1024; i
++) {
953 ehcic
[index
].periodic_list
[i
] = (uint32_t)periodic
957 /* Set periodic list base address */
958 ehci_writel(&ehcic
[index
].hcor
->or_periodiclistbase
,
959 (uint32_t)ehcic
[index
].periodic_list
);
961 reg
= ehci_readl(&ehcic
[index
].hccr
->cr_hcsparams
);
962 descriptor
.hub
.bNbrPorts
= HCS_N_PORTS(reg
);
963 debug("Register %x NbrPorts %d\n", reg
, descriptor
.hub
.bNbrPorts
);
964 /* Port Indicators */
965 if (HCS_INDICATOR(reg
))
966 put_unaligned(get_unaligned(&descriptor
.hub
.wHubCharacteristics
)
967 | 0x80, &descriptor
.hub
.wHubCharacteristics
);
968 /* Port Power Control */
970 put_unaligned(get_unaligned(&descriptor
.hub
.wHubCharacteristics
)
971 | 0x01, &descriptor
.hub
.wHubCharacteristics
);
973 /* Start the host controller. */
974 cmd
= ehci_readl(&ehcic
[index
].hcor
->or_usbcmd
);
976 * Philips, Intel, and maybe others need CMD_RUN before the
977 * root hub will detect new devices (why?); NEC doesn't
979 cmd
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
981 ehci_writel(&ehcic
[index
].hcor
->or_usbcmd
, cmd
);
983 /* take control over the ports */
984 cmd
= ehci_readl(&ehcic
[index
].hcor
->or_configflag
);
986 ehci_writel(&ehcic
[index
].hcor
->or_configflag
, cmd
);
987 /* unblock posted write */
988 cmd
= ehci_readl(&ehcic
[index
].hcor
->or_usbcmd
);
990 reg
= HC_VERSION(ehci_readl(&ehcic
[index
].hccr
->cr_capbase
));
991 printf("USB EHCI %x.%02x\n", reg
>> 8, reg
& 0xff);
993 ehcic
[index
].rootdev
= 0;
995 *controller
= &ehcic
[index
];
1000 submit_bulk_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
1004 if (usb_pipetype(pipe
) != PIPE_BULK
) {
1005 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe
));
1008 return ehci_submit_async(dev
, pipe
, buffer
, length
, NULL
);
1012 submit_control_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
1013 int length
, struct devrequest
*setup
)
1015 struct ehci_ctrl
*ctrl
= dev
->controller
;
1017 if (usb_pipetype(pipe
) != PIPE_CONTROL
) {
1018 debug("non-control pipe (type=%lu)", usb_pipetype(pipe
));
1022 if (usb_pipedevice(pipe
) == ctrl
->rootdev
) {
1024 dev
->speed
= USB_SPEED_HIGH
;
1025 return ehci_submit_root(dev
, pipe
, buffer
, length
, setup
);
1027 return ehci_submit_async(dev
, pipe
, buffer
, length
, setup
);
1037 #define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f)
1040 enable_periodic(struct ehci_ctrl
*ctrl
)
1043 struct ehci_hcor
*hcor
= ctrl
->hcor
;
1046 cmd
= ehci_readl(&hcor
->or_usbcmd
);
1048 ehci_writel(&hcor
->or_usbcmd
, cmd
);
1050 ret
= handshake((uint32_t *)&hcor
->or_usbsts
,
1051 STS_PSS
, STS_PSS
, 100 * 1000);
1053 printf("EHCI failed: timeout when enabling periodic list\n");
1061 disable_periodic(struct ehci_ctrl
*ctrl
)
1064 struct ehci_hcor
*hcor
= ctrl
->hcor
;
1067 cmd
= ehci_readl(&hcor
->or_usbcmd
);
1069 ehci_writel(&hcor
->or_usbcmd
, cmd
);
1071 ret
= handshake((uint32_t *)&hcor
->or_usbsts
,
1072 STS_PSS
, 0, 100 * 1000);
1074 printf("EHCI failed: timeout when disabling periodic list\n");
1080 static int periodic_schedules
;
1083 create_int_queue(struct usb_device
*dev
, unsigned long pipe
, int queuesize
,
1084 int elementsize
, void *buffer
)
1086 struct ehci_ctrl
*ctrl
= dev
->controller
;
1087 struct int_queue
*result
= NULL
;
1090 debug("Enter create_int_queue\n");
1091 if (usb_pipetype(pipe
) != PIPE_INTERRUPT
) {
1092 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe
));
1096 /* limit to 4 full pages worth of data -
1097 * we can safely fit them in a single TD,
1098 * no matter the alignment
1100 if (elementsize
>= 16384) {
1101 debug("too large elements for interrupt transfers\n");
1105 result
= malloc(sizeof(*result
));
1107 debug("ehci intr queue: out of memory\n");
1110 result
->first
= memalign(32, sizeof(struct QH
) * queuesize
);
1111 if (!result
->first
) {
1112 debug("ehci intr queue: out of memory\n");
1115 result
->current
= result
->first
;
1116 result
->last
= result
->first
+ queuesize
- 1;
1117 result
->tds
= memalign(32, sizeof(struct qTD
) * queuesize
);
1119 debug("ehci intr queue: out of memory\n");
1122 memset(result
->first
, 0, sizeof(struct QH
) * queuesize
);
1123 memset(result
->tds
, 0, sizeof(struct qTD
) * queuesize
);
1125 for (i
= 0; i
< queuesize
; i
++) {
1126 struct QH
*qh
= result
->first
+ i
;
1127 struct qTD
*td
= result
->tds
+ i
;
1128 void **buf
= &qh
->buffer
;
1130 qh
->qh_link
= (uint32_t)(qh
+1) | QH_LINK_TYPE_QH
;
1131 if (i
== queuesize
- 1)
1132 qh
->qh_link
= QH_LINK_TERMINATE
;
1134 qh
->qh_overlay
.qt_next
= (uint32_t)td
;
1135 qh
->qh_endpt1
= (0 << 28) | /* No NAK reload (ehci 4.9) */
1136 (usb_maxpacket(dev
, pipe
) << 16) | /* MPS */
1138 QH_ENDPT1_EPS(ehci_encode_speed(dev
->speed
)) |
1139 (usb_pipeendpoint(pipe
) << 8) | /* Endpoint Number */
1140 (usb_pipedevice(pipe
) << 0);
1141 qh
->qh_endpt2
= (1 << 30) | /* 1 Tx per mframe */
1142 (1 << 0); /* S-mask: microframe 0 */
1143 if (dev
->speed
== USB_SPEED_LOW
||
1144 dev
->speed
== USB_SPEED_FULL
) {
1145 debug("TT: port: %d, hub address: %d\n",
1146 dev
->portnr
, dev
->parent
->devnum
);
1147 qh
->qh_endpt2
|= (dev
->portnr
<< 23) |
1148 (dev
->parent
->devnum
<< 16) |
1149 (0x1c << 8); /* C-mask: microframes 2-4 */
1152 td
->qt_next
= QT_NEXT_TERMINATE
;
1153 td
->qt_altnext
= QT_NEXT_TERMINATE
;
1154 debug("communication direction is '%s'\n",
1155 usb_pipein(pipe
) ? "in" : "out");
1156 td
->qt_token
= (elementsize
<< 16) |
1157 ((usb_pipein(pipe
) ? 1 : 0) << 8) | /* IN/OUT token */
1159 td
->qt_buffer
[0] = (uint32_t)buffer
+ i
* elementsize
;
1160 td
->qt_buffer
[1] = (td
->qt_buffer
[0] + 0x1000) & ~0xfff;
1161 td
->qt_buffer
[2] = (td
->qt_buffer
[0] + 0x2000) & ~0xfff;
1162 td
->qt_buffer
[3] = (td
->qt_buffer
[0] + 0x3000) & ~0xfff;
1163 td
->qt_buffer
[4] = (td
->qt_buffer
[0] + 0x4000) & ~0xfff;
1165 *buf
= buffer
+ i
* elementsize
;
1168 if (disable_periodic(ctrl
) < 0) {
1169 debug("FATAL: periodic should never fail, but did");
1173 /* hook up to periodic list */
1174 struct QH
*list
= &ctrl
->periodic_queue
;
1175 result
->last
->qh_link
= list
->qh_link
;
1176 list
->qh_link
= (uint32_t)result
->first
| QH_LINK_TYPE_QH
;
1178 if (enable_periodic(ctrl
) < 0) {
1179 debug("FATAL: periodic should never fail, but did");
1182 periodic_schedules
++;
1184 debug("Exit create_int_queue\n");
1191 free(result
->first
);
1198 void *poll_int_queue(struct usb_device
*dev
, struct int_queue
*queue
)
1200 struct QH
*cur
= queue
->current
;
1202 /* depleted queue */
1204 debug("Exit poll_int_queue with completed queue\n");
1208 if (cur
->qh_overlay
.qt_token
& 0x80) {
1209 debug("Exit poll_int_queue with no completed intr transfer. "
1210 "token is %x\n", cur
->qh_overlay
.qt_token
);
1213 if (!(cur
->qh_link
& QH_LINK_TERMINATE
))
1216 queue
->current
= NULL
;
1217 debug("Exit poll_int_queue with completed intr transfer. "
1218 "token is %x at %p (first at %p)\n", cur
->qh_overlay
.qt_token
,
1219 &cur
->qh_overlay
.qt_token
, queue
->first
);
1223 /* Do not free buffers associated with QHs, they're owned by someone else */
1225 destroy_int_queue(struct usb_device
*dev
, struct int_queue
*queue
)
1227 struct ehci_ctrl
*ctrl
= dev
->controller
;
1229 unsigned long timeout
;
1231 if (disable_periodic(ctrl
) < 0) {
1232 debug("FATAL: periodic should never fail, but did");
1235 periodic_schedules
--;
1237 struct QH
*cur
= &ctrl
->periodic_queue
;
1238 timeout
= get_timer(0) + 500; /* abort after 500ms */
1239 while (!(cur
->qh_link
& QH_LINK_TERMINATE
)) {
1240 debug("considering %p, with qh_link %x\n", cur
, cur
->qh_link
);
1241 if (NEXT_QH(cur
) == queue
->first
) {
1242 debug("found candidate. removing from chain\n");
1243 cur
->qh_link
= queue
->last
->qh_link
;
1248 if (get_timer(0) > timeout
) {
1249 printf("Timeout destroying interrupt endpoint queue\n");
1255 if (periodic_schedules
> 0) {
1256 result
= enable_periodic(ctrl
);
1258 debug("FATAL: periodic should never fail, but did");
1270 submit_int_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
1271 int length
, int interval
)
1274 struct int_queue
*queue
;
1275 unsigned long timeout
;
1276 int result
= 0, ret
;
1278 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1279 dev
, pipe
, buffer
, length
, interval
);
1282 * Interrupt transfers requiring several transactions are not supported
1283 * because bInterval is ignored.
1285 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1286 * <= PKT_ALIGN if several qTDs are required, while the USB
1287 * specification does not constrain this for interrupt transfers. That
1288 * means that ehci_submit_async() would support interrupt transfers
1289 * requiring several transactions only as long as the transfer size does
1290 * not require more than a single qTD.
1292 if (length
> usb_maxpacket(dev
, pipe
)) {
1293 printf("%s: Interrupt transfers requiring several "
1294 "transactions are not supported.\n", __func__
);
1298 queue
= create_int_queue(dev
, pipe
, 1, length
, buffer
);
1300 timeout
= get_timer(0) + USB_TIMEOUT_MS(pipe
);
1301 while ((backbuffer
= poll_int_queue(dev
, queue
)) == NULL
)
1302 if (get_timer(0) > timeout
) {
1303 printf("Timeout poll on interrupt endpoint\n");
1304 result
= -ETIMEDOUT
;
1308 if (backbuffer
!= buffer
) {
1309 debug("got wrong buffer back (%x instead of %x)\n",
1310 (uint32_t)backbuffer
, (uint32_t)buffer
);
1314 ret
= destroy_int_queue(dev
, queue
);
1318 /* everything worked out fine */