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Merge git://git.denx.de/u-boot-mmc
[people/ms/u-boot.git] / drivers / usb / host / ehci-hcd.c
1 /*-
2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
5 *
6 * All rights reserved.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <asm/byteorder.h>
14 #include <asm/unaligned.h>
15 #include <usb.h>
16 #include <asm/io.h>
17 #include <malloc.h>
18 #include <memalign.h>
19 #include <watchdog.h>
20 #include <linux/compiler.h>
21
22 #include "ehci.h"
23
24 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
25 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
26 #endif
27
28 /*
29 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
30 * Let's time out after 8 to have a little safety margin on top of that.
31 */
32 #define HCHALT_TIMEOUT (8 * 1000)
33
34 #ifndef CONFIG_DM_USB
35 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
36 #endif
37
38 #define ALIGN_END_ADDR(type, ptr, size) \
39 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
40
41 static struct descriptor {
42 struct usb_hub_descriptor hub;
43 struct usb_device_descriptor device;
44 struct usb_linux_config_descriptor config;
45 struct usb_linux_interface_descriptor interface;
46 struct usb_endpoint_descriptor endpoint;
47 } __attribute__ ((packed)) descriptor = {
48 {
49 0x8, /* bDescLength */
50 0x29, /* bDescriptorType: hub descriptor */
51 2, /* bNrPorts -- runtime modified */
52 0, /* wHubCharacteristics */
53 10, /* bPwrOn2PwrGood */
54 0, /* bHubCntrCurrent */
55 { /* Device removable */
56 } /* at most 7 ports! XXX */
57 },
58 {
59 0x12, /* bLength */
60 1, /* bDescriptorType: UDESC_DEVICE */
61 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
62 9, /* bDeviceClass: UDCLASS_HUB */
63 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
64 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
65 64, /* bMaxPacketSize: 64 bytes */
66 0x0000, /* idVendor */
67 0x0000, /* idProduct */
68 cpu_to_le16(0x0100), /* bcdDevice */
69 1, /* iManufacturer */
70 2, /* iProduct */
71 0, /* iSerialNumber */
72 1 /* bNumConfigurations: 1 */
73 },
74 {
75 0x9,
76 2, /* bDescriptorType: UDESC_CONFIG */
77 cpu_to_le16(0x19),
78 1, /* bNumInterface */
79 1, /* bConfigurationValue */
80 0, /* iConfiguration */
81 0x40, /* bmAttributes: UC_SELF_POWER */
82 0 /* bMaxPower */
83 },
84 {
85 0x9, /* bLength */
86 4, /* bDescriptorType: UDESC_INTERFACE */
87 0, /* bInterfaceNumber */
88 0, /* bAlternateSetting */
89 1, /* bNumEndpoints */
90 9, /* bInterfaceClass: UICLASS_HUB */
91 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
92 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
93 0 /* iInterface */
94 },
95 {
96 0x7, /* bLength */
97 5, /* bDescriptorType: UDESC_ENDPOINT */
98 0x81, /* bEndpointAddress:
99 * UE_DIR_IN | EHCI_INTR_ENDPT
100 */
101 3, /* bmAttributes: UE_INTERRUPT */
102 8, /* wMaxPacketSize */
103 255 /* bInterval */
104 },
105 };
106
107 #if defined(CONFIG_EHCI_IS_TDI)
108 #define ehci_is_TDI() (1)
109 #else
110 #define ehci_is_TDI() (0)
111 #endif
112
113 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
114 {
115 #ifdef CONFIG_DM_USB
116 return dev_get_priv(usb_get_bus(udev->dev));
117 #else
118 return udev->controller;
119 #endif
120 }
121
122 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
123 {
124 return PORTSC_PSPD(reg);
125 }
126
127 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
128 {
129 uint32_t tmp;
130 uint32_t *reg_ptr;
131
132 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
133 tmp = ehci_readl(reg_ptr);
134 tmp |= USBMODE_CM_HC;
135 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
136 tmp |= USBMODE_BE;
137 #else
138 tmp &= ~USBMODE_BE;
139 #endif
140 ehci_writel(reg_ptr, tmp);
141 }
142
143 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
144 uint32_t *reg)
145 {
146 mdelay(50);
147 }
148
149 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
150 {
151 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
152
153 if (port < 0 || port >= max_ports) {
154 /* Printing the message would cause a scan failure! */
155 debug("The request port(%u) exceeds maximum port number\n",
156 port);
157 return NULL;
158 }
159
160 return (uint32_t *)&ctrl->hcor->or_portsc[port];
161 }
162
163 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
164 {
165 uint32_t result;
166 do {
167 result = ehci_readl(ptr);
168 udelay(5);
169 if (result == ~(uint32_t)0)
170 return -1;
171 result &= mask;
172 if (result == done)
173 return 0;
174 usec--;
175 } while (usec > 0);
176 return -1;
177 }
178
179 static int ehci_reset(struct ehci_ctrl *ctrl)
180 {
181 uint32_t cmd;
182 int ret = 0;
183
184 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
185 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
186 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
187 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
188 CMD_RESET, 0, 250 * 1000);
189 if (ret < 0) {
190 printf("EHCI fail to reset\n");
191 goto out;
192 }
193
194 if (ehci_is_TDI())
195 ctrl->ops.set_usb_mode(ctrl);
196
197 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
198 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
199 cmd &= ~TXFIFO_THRESH_MASK;
200 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
201 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
202 #endif
203 out:
204 return ret;
205 }
206
207 static int ehci_shutdown(struct ehci_ctrl *ctrl)
208 {
209 int i, ret = 0;
210 uint32_t cmd, reg;
211 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
212
213 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
214 /* If not run, directly return */
215 if (!(cmd & CMD_RUN))
216 return 0;
217 cmd &= ~(CMD_PSE | CMD_ASE);
218 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
219 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
220 100 * 1000);
221
222 if (!ret) {
223 for (i = 0; i < max_ports; i++) {
224 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
225 reg |= EHCI_PS_SUSP;
226 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
227 }
228
229 cmd &= ~CMD_RUN;
230 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
231 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
232 HCHALT_TIMEOUT);
233 }
234
235 if (ret)
236 puts("EHCI failed to shut down host controller.\n");
237
238 return ret;
239 }
240
241 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
242 {
243 uint32_t delta, next;
244 unsigned long addr = (unsigned long)buf;
245 int idx;
246
247 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
248 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
249
250 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
251
252 idx = 0;
253 while (idx < QT_BUFFER_CNT) {
254 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
255 td->qt_buffer_hi[idx] = 0;
256 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
257 delta = next - addr;
258 if (delta >= sz)
259 break;
260 sz -= delta;
261 addr = next;
262 idx++;
263 }
264
265 if (idx == QT_BUFFER_CNT) {
266 printf("out of buffer pointers (%zu bytes left)\n", sz);
267 return -1;
268 }
269
270 return 0;
271 }
272
273 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
274 {
275 #define QH_HIGH_SPEED 2
276 #define QH_FULL_SPEED 0
277 #define QH_LOW_SPEED 1
278 if (speed == USB_SPEED_HIGH)
279 return QH_HIGH_SPEED;
280 if (speed == USB_SPEED_LOW)
281 return QH_LOW_SPEED;
282 return QH_FULL_SPEED;
283 }
284
285 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
286 struct QH *qh)
287 {
288 uint8_t portnr = 0;
289 uint8_t hubaddr = 0;
290
291 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
292 return;
293
294 usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
295
296 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
297 QH_ENDPT2_HUBADDR(hubaddr));
298 }
299
300 static int
301 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
302 int length, struct devrequest *req)
303 {
304 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
305 struct qTD *qtd;
306 int qtd_count = 0;
307 int qtd_counter = 0;
308 volatile struct qTD *vtd;
309 unsigned long ts;
310 uint32_t *tdp;
311 uint32_t endpt, maxpacket, token, usbsts;
312 uint32_t c, toggle;
313 uint32_t cmd;
314 int timeout;
315 int ret = 0;
316 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
317
318 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
319 buffer, length, req);
320 if (req != NULL)
321 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
322 req->request, req->request,
323 req->requesttype, req->requesttype,
324 le16_to_cpu(req->value), le16_to_cpu(req->value),
325 le16_to_cpu(req->index));
326
327 #define PKT_ALIGN 512
328 /*
329 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
330 * described by a transfer descriptor (the qTD). The qTDs form a linked
331 * list with a queue head (QH).
332 *
333 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
334 * have its beginning in a qTD transfer and its end in the following
335 * one, so the qTD transfer lengths have to be chosen accordingly.
336 *
337 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
338 * single pages. The first data buffer can start at any offset within a
339 * page (not considering the cache-line alignment issues), while the
340 * following buffers must be page-aligned. There is no alignment
341 * constraint on the size of a qTD transfer.
342 */
343 if (req != NULL)
344 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
345 qtd_count += 1 + 1;
346 if (length > 0 || req == NULL) {
347 /*
348 * Determine the qTD transfer size that will be used for the
349 * data payload (not considering the first qTD transfer, which
350 * may be longer or shorter, and the final one, which may be
351 * shorter).
352 *
353 * In order to keep each packet within a qTD transfer, the qTD
354 * transfer size is aligned to PKT_ALIGN, which is a multiple of
355 * wMaxPacketSize (except in some cases for interrupt transfers,
356 * see comment in submit_int_msg()).
357 *
358 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
359 * QT_BUFFER_CNT full pages will be used.
360 */
361 int xfr_sz = QT_BUFFER_CNT;
362 /*
363 * However, if the input buffer is not aligned to PKT_ALIGN, the
364 * qTD transfer size will be one page shorter, and the first qTD
365 * data buffer of each transfer will be page-unaligned.
366 */
367 if ((unsigned long)buffer & (PKT_ALIGN - 1))
368 xfr_sz--;
369 /* Convert the qTD transfer size to bytes. */
370 xfr_sz *= EHCI_PAGE_SIZE;
371 /*
372 * Approximate by excess the number of qTDs that will be
373 * required for the data payload. The exact formula is way more
374 * complicated and saves at most 2 qTDs, i.e. a total of 128
375 * bytes.
376 */
377 qtd_count += 2 + length / xfr_sz;
378 }
379 /*
380 * Threshold value based on the worst-case total size of the allocated qTDs for
381 * a mass-storage transfer of 65535 blocks of 512 bytes.
382 */
383 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
384 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
385 #endif
386 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
387 if (qtd == NULL) {
388 printf("unable to allocate TDs\n");
389 return -1;
390 }
391
392 memset(qh, 0, sizeof(struct QH));
393 memset(qtd, 0, qtd_count * sizeof(*qtd));
394
395 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
396
397 /*
398 * Setup QH (3.6 in ehci-r10.pdf)
399 *
400 * qh_link ................. 03-00 H
401 * qh_endpt1 ............... 07-04 H
402 * qh_endpt2 ............... 0B-08 H
403 * - qh_curtd
404 * qh_overlay.qt_next ...... 13-10 H
405 * - qh_overlay.qt_altnext
406 */
407 qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
408 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
409 maxpacket = usb_maxpacket(dev, pipe);
410 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
411 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
412 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
413 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
414 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
415 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
416 qh->qh_endpt1 = cpu_to_hc32(endpt);
417 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
418 qh->qh_endpt2 = cpu_to_hc32(endpt);
419 ehci_update_endpt2_dev_n_port(dev, qh);
420 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
421 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
422
423 tdp = &qh->qh_overlay.qt_next;
424 if (req != NULL) {
425 /*
426 * Setup request qTD (3.5 in ehci-r10.pdf)
427 *
428 * qt_next ................ 03-00 H
429 * qt_altnext ............. 07-04 H
430 * qt_token ............... 0B-08 H
431 *
432 * [ buffer, buffer_hi ] loaded with "req".
433 */
434 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
435 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
436 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
437 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
438 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
439 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
440 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
441 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
442 printf("unable to construct SETUP TD\n");
443 goto fail;
444 }
445 /* Update previous qTD! */
446 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
447 tdp = &qtd[qtd_counter++].qt_next;
448 toggle = 1;
449 }
450
451 if (length > 0 || req == NULL) {
452 uint8_t *buf_ptr = buffer;
453 int left_length = length;
454
455 do {
456 /*
457 * Determine the size of this qTD transfer. By default,
458 * QT_BUFFER_CNT full pages can be used.
459 */
460 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
461 /*
462 * However, if the input buffer is not page-aligned, the
463 * portion of the first page before the buffer start
464 * offset within that page is unusable.
465 */
466 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
467 /*
468 * In order to keep each packet within a qTD transfer,
469 * align the qTD transfer size to PKT_ALIGN.
470 */
471 xfr_bytes &= ~(PKT_ALIGN - 1);
472 /*
473 * This transfer may be shorter than the available qTD
474 * transfer size that has just been computed.
475 */
476 xfr_bytes = min(xfr_bytes, left_length);
477
478 /*
479 * Setup request qTD (3.5 in ehci-r10.pdf)
480 *
481 * qt_next ................ 03-00 H
482 * qt_altnext ............. 07-04 H
483 * qt_token ............... 0B-08 H
484 *
485 * [ buffer, buffer_hi ] loaded with "buffer".
486 */
487 qtd[qtd_counter].qt_next =
488 cpu_to_hc32(QT_NEXT_TERMINATE);
489 qtd[qtd_counter].qt_altnext =
490 cpu_to_hc32(QT_NEXT_TERMINATE);
491 token = QT_TOKEN_DT(toggle) |
492 QT_TOKEN_TOTALBYTES(xfr_bytes) |
493 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
494 QT_TOKEN_CERR(3) |
495 QT_TOKEN_PID(usb_pipein(pipe) ?
496 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
497 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
498 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
499 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
500 xfr_bytes)) {
501 printf("unable to construct DATA TD\n");
502 goto fail;
503 }
504 /* Update previous qTD! */
505 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
506 tdp = &qtd[qtd_counter++].qt_next;
507 /*
508 * Data toggle has to be adjusted since the qTD transfer
509 * size is not always an even multiple of
510 * wMaxPacketSize.
511 */
512 if ((xfr_bytes / maxpacket) & 1)
513 toggle ^= 1;
514 buf_ptr += xfr_bytes;
515 left_length -= xfr_bytes;
516 } while (left_length > 0);
517 }
518
519 if (req != NULL) {
520 /*
521 * Setup request qTD (3.5 in ehci-r10.pdf)
522 *
523 * qt_next ................ 03-00 H
524 * qt_altnext ............. 07-04 H
525 * qt_token ............... 0B-08 H
526 */
527 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
528 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
529 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
530 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
531 QT_TOKEN_PID(usb_pipein(pipe) ?
532 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
533 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
534 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
535 /* Update previous qTD! */
536 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
537 tdp = &qtd[qtd_counter++].qt_next;
538 }
539
540 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
541
542 /* Flush dcache */
543 flush_dcache_range((unsigned long)&ctrl->qh_list,
544 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
545 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
546 flush_dcache_range((unsigned long)qtd,
547 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
548
549 /* Set async. queue head pointer. */
550 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(&ctrl->qh_list));
551
552 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
553 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
554
555 /* Enable async. schedule. */
556 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
557 cmd |= CMD_ASE;
558 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
559
560 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
561 100 * 1000);
562 if (ret < 0) {
563 printf("EHCI fail timeout STS_ASS set\n");
564 goto fail;
565 }
566
567 /* Wait for TDs to be processed. */
568 ts = get_timer(0);
569 vtd = &qtd[qtd_counter - 1];
570 timeout = USB_TIMEOUT_MS(pipe);
571 do {
572 /* Invalidate dcache */
573 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
574 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
575 invalidate_dcache_range((unsigned long)qh,
576 ALIGN_END_ADDR(struct QH, qh, 1));
577 invalidate_dcache_range((unsigned long)qtd,
578 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
579
580 token = hc32_to_cpu(vtd->qt_token);
581 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
582 break;
583 WATCHDOG_RESET();
584 } while (get_timer(ts) < timeout);
585
586 /*
587 * Invalidate the memory area occupied by buffer
588 * Don't try to fix the buffer alignment, if it isn't properly
589 * aligned it's upper layer's fault so let invalidate_dcache_range()
590 * vow about it. But we have to fix the length as it's actual
591 * transfer length and can be unaligned. This is potentially
592 * dangerous operation, it's responsibility of the calling
593 * code to make sure enough space is reserved.
594 */
595 if (buffer != NULL && length > 0)
596 invalidate_dcache_range((unsigned long)buffer,
597 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
598
599 /* Check that the TD processing happened */
600 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
601 printf("EHCI timed out on TD - token=%#x\n", token);
602
603 /* Disable async schedule. */
604 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
605 cmd &= ~CMD_ASE;
606 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
607
608 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
609 100 * 1000);
610 if (ret < 0) {
611 printf("EHCI fail timeout STS_ASS reset\n");
612 goto fail;
613 }
614
615 token = hc32_to_cpu(qh->qh_overlay.qt_token);
616 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
617 debug("TOKEN=%#x\n", token);
618 switch (QT_TOKEN_GET_STATUS(token) &
619 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
620 case 0:
621 toggle = QT_TOKEN_GET_DT(token);
622 usb_settoggle(dev, usb_pipeendpoint(pipe),
623 usb_pipeout(pipe), toggle);
624 dev->status = 0;
625 break;
626 case QT_TOKEN_STATUS_HALTED:
627 dev->status = USB_ST_STALLED;
628 break;
629 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
630 case QT_TOKEN_STATUS_DATBUFERR:
631 dev->status = USB_ST_BUF_ERR;
632 break;
633 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
634 case QT_TOKEN_STATUS_BABBLEDET:
635 dev->status = USB_ST_BABBLE_DET;
636 break;
637 default:
638 dev->status = USB_ST_CRC_ERR;
639 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
640 dev->status |= USB_ST_STALLED;
641 break;
642 }
643 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
644 } else {
645 dev->act_len = 0;
646 #ifndef CONFIG_USB_EHCI_FARADAY
647 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
648 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
649 ehci_readl(&ctrl->hcor->or_portsc[0]),
650 ehci_readl(&ctrl->hcor->or_portsc[1]));
651 #endif
652 }
653
654 free(qtd);
655 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
656
657 fail:
658 free(qtd);
659 return -1;
660 }
661
662 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
663 void *buffer, int length, struct devrequest *req)
664 {
665 uint8_t tmpbuf[4];
666 u16 typeReq;
667 void *srcptr = NULL;
668 int len, srclen;
669 uint32_t reg;
670 uint32_t *status_reg;
671 int port = le16_to_cpu(req->index) & 0xff;
672 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
673
674 srclen = 0;
675
676 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
677 req->request, req->request,
678 req->requesttype, req->requesttype,
679 le16_to_cpu(req->value), le16_to_cpu(req->index));
680
681 typeReq = req->request | req->requesttype << 8;
682
683 switch (typeReq) {
684 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
685 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
686 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
687 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
688 if (!status_reg)
689 return -1;
690 break;
691 default:
692 status_reg = NULL;
693 break;
694 }
695
696 switch (typeReq) {
697 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
698 switch (le16_to_cpu(req->value) >> 8) {
699 case USB_DT_DEVICE:
700 debug("USB_DT_DEVICE request\n");
701 srcptr = &descriptor.device;
702 srclen = descriptor.device.bLength;
703 break;
704 case USB_DT_CONFIG:
705 debug("USB_DT_CONFIG config\n");
706 srcptr = &descriptor.config;
707 srclen = descriptor.config.bLength +
708 descriptor.interface.bLength +
709 descriptor.endpoint.bLength;
710 break;
711 case USB_DT_STRING:
712 debug("USB_DT_STRING config\n");
713 switch (le16_to_cpu(req->value) & 0xff) {
714 case 0: /* Language */
715 srcptr = "\4\3\1\0";
716 srclen = 4;
717 break;
718 case 1: /* Vendor */
719 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
720 srclen = 14;
721 break;
722 case 2: /* Product */
723 srcptr = "\52\3E\0H\0C\0I\0 "
724 "\0H\0o\0s\0t\0 "
725 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
726 srclen = 42;
727 break;
728 default:
729 debug("unknown value DT_STRING %x\n",
730 le16_to_cpu(req->value));
731 goto unknown;
732 }
733 break;
734 default:
735 debug("unknown value %x\n", le16_to_cpu(req->value));
736 goto unknown;
737 }
738 break;
739 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
740 switch (le16_to_cpu(req->value) >> 8) {
741 case USB_DT_HUB:
742 debug("USB_DT_HUB config\n");
743 srcptr = &descriptor.hub;
744 srclen = descriptor.hub.bLength;
745 break;
746 default:
747 debug("unknown value %x\n", le16_to_cpu(req->value));
748 goto unknown;
749 }
750 break;
751 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
752 debug("USB_REQ_SET_ADDRESS\n");
753 ctrl->rootdev = le16_to_cpu(req->value);
754 break;
755 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
756 debug("USB_REQ_SET_CONFIGURATION\n");
757 /* Nothing to do */
758 break;
759 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
760 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
761 tmpbuf[1] = 0;
762 srcptr = tmpbuf;
763 srclen = 2;
764 break;
765 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
766 memset(tmpbuf, 0, 4);
767 reg = ehci_readl(status_reg);
768 if (reg & EHCI_PS_CS)
769 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
770 if (reg & EHCI_PS_PE)
771 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
772 if (reg & EHCI_PS_SUSP)
773 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
774 if (reg & EHCI_PS_OCA)
775 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
776 if (reg & EHCI_PS_PR)
777 tmpbuf[0] |= USB_PORT_STAT_RESET;
778 if (reg & EHCI_PS_PP)
779 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
780
781 if (ehci_is_TDI()) {
782 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
783 case PORTSC_PSPD_FS:
784 break;
785 case PORTSC_PSPD_LS:
786 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
787 break;
788 case PORTSC_PSPD_HS:
789 default:
790 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
791 break;
792 }
793 } else {
794 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
795 }
796
797 if (reg & EHCI_PS_CSC)
798 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
799 if (reg & EHCI_PS_PEC)
800 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
801 if (reg & EHCI_PS_OCC)
802 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
803 if (ctrl->portreset & (1 << port))
804 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
805
806 srcptr = tmpbuf;
807 srclen = 4;
808 break;
809 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
810 reg = ehci_readl(status_reg);
811 reg &= ~EHCI_PS_CLEAR;
812 switch (le16_to_cpu(req->value)) {
813 case USB_PORT_FEAT_ENABLE:
814 reg |= EHCI_PS_PE;
815 ehci_writel(status_reg, reg);
816 break;
817 case USB_PORT_FEAT_POWER:
818 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
819 reg |= EHCI_PS_PP;
820 ehci_writel(status_reg, reg);
821 }
822 break;
823 case USB_PORT_FEAT_RESET:
824 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
825 !ehci_is_TDI() &&
826 EHCI_PS_IS_LOWSPEED(reg)) {
827 /* Low speed device, give up ownership. */
828 debug("port %d low speed --> companion\n",
829 port - 1);
830 reg |= EHCI_PS_PO;
831 ehci_writel(status_reg, reg);
832 return -ENXIO;
833 } else {
834 int ret;
835
836 reg |= EHCI_PS_PR;
837 reg &= ~EHCI_PS_PE;
838 ehci_writel(status_reg, reg);
839 /*
840 * caller must wait, then call GetPortStatus
841 * usb 2.0 specification say 50 ms resets on
842 * root
843 */
844 ctrl->ops.powerup_fixup(ctrl, status_reg, &reg);
845
846 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
847 /*
848 * A host controller must terminate the reset
849 * and stabilize the state of the port within
850 * 2 milliseconds
851 */
852 ret = handshake(status_reg, EHCI_PS_PR, 0,
853 2 * 1000);
854 if (!ret) {
855 reg = ehci_readl(status_reg);
856 if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
857 == EHCI_PS_CS && !ehci_is_TDI()) {
858 debug("port %d full speed --> companion\n", port - 1);
859 reg &= ~EHCI_PS_CLEAR;
860 reg |= EHCI_PS_PO;
861 ehci_writel(status_reg, reg);
862 return -ENXIO;
863 } else {
864 ctrl->portreset |= 1 << port;
865 }
866 } else {
867 printf("port(%d) reset error\n",
868 port - 1);
869 }
870 }
871 break;
872 case USB_PORT_FEAT_TEST:
873 ehci_shutdown(ctrl);
874 reg &= ~(0xf << 16);
875 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
876 ehci_writel(status_reg, reg);
877 break;
878 default:
879 debug("unknown feature %x\n", le16_to_cpu(req->value));
880 goto unknown;
881 }
882 /* unblock posted writes */
883 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
884 break;
885 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
886 reg = ehci_readl(status_reg);
887 reg &= ~EHCI_PS_CLEAR;
888 switch (le16_to_cpu(req->value)) {
889 case USB_PORT_FEAT_ENABLE:
890 reg &= ~EHCI_PS_PE;
891 break;
892 case USB_PORT_FEAT_C_ENABLE:
893 reg |= EHCI_PS_PE;
894 break;
895 case USB_PORT_FEAT_POWER:
896 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
897 reg &= ~EHCI_PS_PP;
898 break;
899 case USB_PORT_FEAT_C_CONNECTION:
900 reg |= EHCI_PS_CSC;
901 break;
902 case USB_PORT_FEAT_OVER_CURRENT:
903 reg |= EHCI_PS_OCC;
904 break;
905 case USB_PORT_FEAT_C_RESET:
906 ctrl->portreset &= ~(1 << port);
907 break;
908 default:
909 debug("unknown feature %x\n", le16_to_cpu(req->value));
910 goto unknown;
911 }
912 ehci_writel(status_reg, reg);
913 /* unblock posted write */
914 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
915 break;
916 default:
917 debug("Unknown request\n");
918 goto unknown;
919 }
920
921 mdelay(1);
922 len = min3(srclen, (int)le16_to_cpu(req->length), length);
923 if (srcptr != NULL && len > 0)
924 memcpy(buffer, srcptr, len);
925 else
926 debug("Len is 0\n");
927
928 dev->act_len = len;
929 dev->status = 0;
930 return 0;
931
932 unknown:
933 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
934 req->requesttype, req->request, le16_to_cpu(req->value),
935 le16_to_cpu(req->index), le16_to_cpu(req->length));
936
937 dev->act_len = 0;
938 dev->status = USB_ST_STALLED;
939 return -1;
940 }
941
942 static const struct ehci_ops default_ehci_ops = {
943 .set_usb_mode = ehci_set_usbmode,
944 .get_port_speed = ehci_get_port_speed,
945 .powerup_fixup = ehci_powerup_fixup,
946 .get_portsc_register = ehci_get_portsc_register,
947 };
948
949 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
950 {
951 if (!ops) {
952 ctrl->ops = default_ehci_ops;
953 } else {
954 ctrl->ops = *ops;
955 if (!ctrl->ops.set_usb_mode)
956 ctrl->ops.set_usb_mode = ehci_set_usbmode;
957 if (!ctrl->ops.get_port_speed)
958 ctrl->ops.get_port_speed = ehci_get_port_speed;
959 if (!ctrl->ops.powerup_fixup)
960 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
961 if (!ctrl->ops.get_portsc_register)
962 ctrl->ops.get_portsc_register =
963 ehci_get_portsc_register;
964 }
965 }
966
967 #ifndef CONFIG_DM_USB
968 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
969 {
970 struct ehci_ctrl *ctrl = &ehcic[index];
971
972 ctrl->priv = priv;
973 ehci_setup_ops(ctrl, ops);
974 }
975
976 void *ehci_get_controller_priv(int index)
977 {
978 return ehcic[index].priv;
979 }
980 #endif
981
982 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
983 {
984 struct QH *qh_list;
985 struct QH *periodic;
986 uint32_t reg;
987 uint32_t cmd;
988 int i;
989
990 /* Set the high address word (aka segment) for 64-bit controller */
991 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
992 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
993
994 qh_list = &ctrl->qh_list;
995
996 /* Set head of reclaim list */
997 memset(qh_list, 0, sizeof(*qh_list));
998 qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
999 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1000 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1001 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1002 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1003 qh_list->qh_overlay.qt_token =
1004 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1005
1006 flush_dcache_range((unsigned long)qh_list,
1007 ALIGN_END_ADDR(struct QH, qh_list, 1));
1008
1009 /* Set async. queue head pointer. */
1010 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
1011
1012 /*
1013 * Set up periodic list
1014 * Step 1: Parent QH for all periodic transfers.
1015 */
1016 ctrl->periodic_schedules = 0;
1017 periodic = &ctrl->periodic_queue;
1018 memset(periodic, 0, sizeof(*periodic));
1019 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1020 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1021 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1022
1023 flush_dcache_range((unsigned long)periodic,
1024 ALIGN_END_ADDR(struct QH, periodic, 1));
1025
1026 /*
1027 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1028 * In particular, device specifications on polling frequency
1029 * are disregarded. Keyboards seem to send NAK/NYet reliably
1030 * when polled with an empty buffer.
1031 *
1032 * Split Transactions will be spread across microframes using
1033 * S-mask and C-mask.
1034 */
1035 if (ctrl->periodic_list == NULL)
1036 ctrl->periodic_list = memalign(4096, 1024 * 4);
1037
1038 if (!ctrl->periodic_list)
1039 return -ENOMEM;
1040 for (i = 0; i < 1024; i++) {
1041 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1042 | QH_LINK_TYPE_QH);
1043 }
1044
1045 flush_dcache_range((unsigned long)ctrl->periodic_list,
1046 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1047 1024));
1048
1049 /* Set periodic list base address */
1050 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1051 (unsigned long)ctrl->periodic_list);
1052
1053 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1054 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1055 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1056 /* Port Indicators */
1057 if (HCS_INDICATOR(reg))
1058 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1059 | 0x80, &descriptor.hub.wHubCharacteristics);
1060 /* Port Power Control */
1061 if (HCS_PPC(reg))
1062 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1063 | 0x01, &descriptor.hub.wHubCharacteristics);
1064
1065 /* Start the host controller. */
1066 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1067 /*
1068 * Philips, Intel, and maybe others need CMD_RUN before the
1069 * root hub will detect new devices (why?); NEC doesn't
1070 */
1071 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1072 cmd |= CMD_RUN;
1073 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1074
1075 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1076 /* take control over the ports */
1077 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1078 cmd |= FLAG_CF;
1079 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1080 }
1081
1082 /* unblock posted write */
1083 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1084 mdelay(5);
1085 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1086 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1087
1088 return 0;
1089 }
1090
1091 #ifndef CONFIG_DM_USB
1092 int usb_lowlevel_stop(int index)
1093 {
1094 ehci_shutdown(&ehcic[index]);
1095 return ehci_hcd_stop(index);
1096 }
1097
1098 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1099 {
1100 struct ehci_ctrl *ctrl = &ehcic[index];
1101 uint tweaks = 0;
1102 int rc;
1103
1104 /**
1105 * Set ops to default_ehci_ops, ehci_hcd_init should call
1106 * ehci_set_controller_priv to change any of these function pointers.
1107 */
1108 ctrl->ops = default_ehci_ops;
1109
1110 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1111 if (rc)
1112 return rc;
1113 if (!ctrl->hccr || !ctrl->hcor)
1114 return -1;
1115 if (init == USB_INIT_DEVICE)
1116 goto done;
1117
1118 /* EHCI spec section 4.1 */
1119 if (ehci_reset(ctrl))
1120 return -1;
1121
1122 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1123 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1124 if (rc)
1125 return rc;
1126 #endif
1127 #ifdef CONFIG_USB_EHCI_FARADAY
1128 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1129 #endif
1130 rc = ehci_common_init(ctrl, tweaks);
1131 if (rc)
1132 return rc;
1133
1134 ctrl->rootdev = 0;
1135 done:
1136 *controller = &ehcic[index];
1137 return 0;
1138 }
1139 #endif
1140
1141 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1142 void *buffer, int length)
1143 {
1144
1145 if (usb_pipetype(pipe) != PIPE_BULK) {
1146 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1147 return -1;
1148 }
1149 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1150 }
1151
1152 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1153 void *buffer, int length,
1154 struct devrequest *setup)
1155 {
1156 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1157
1158 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1159 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1160 return -1;
1161 }
1162
1163 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1164 if (!ctrl->rootdev)
1165 dev->speed = USB_SPEED_HIGH;
1166 return ehci_submit_root(dev, pipe, buffer, length, setup);
1167 }
1168 return ehci_submit_async(dev, pipe, buffer, length, setup);
1169 }
1170
1171 struct int_queue {
1172 int elementsize;
1173 unsigned long pipe;
1174 struct QH *first;
1175 struct QH *current;
1176 struct QH *last;
1177 struct qTD *tds;
1178 };
1179
1180 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1181
1182 static int
1183 enable_periodic(struct ehci_ctrl *ctrl)
1184 {
1185 uint32_t cmd;
1186 struct ehci_hcor *hcor = ctrl->hcor;
1187 int ret;
1188
1189 cmd = ehci_readl(&hcor->or_usbcmd);
1190 cmd |= CMD_PSE;
1191 ehci_writel(&hcor->or_usbcmd, cmd);
1192
1193 ret = handshake((uint32_t *)&hcor->or_usbsts,
1194 STS_PSS, STS_PSS, 100 * 1000);
1195 if (ret < 0) {
1196 printf("EHCI failed: timeout when enabling periodic list\n");
1197 return -ETIMEDOUT;
1198 }
1199 udelay(1000);
1200 return 0;
1201 }
1202
1203 static int
1204 disable_periodic(struct ehci_ctrl *ctrl)
1205 {
1206 uint32_t cmd;
1207 struct ehci_hcor *hcor = ctrl->hcor;
1208 int ret;
1209
1210 cmd = ehci_readl(&hcor->or_usbcmd);
1211 cmd &= ~CMD_PSE;
1212 ehci_writel(&hcor->or_usbcmd, cmd);
1213
1214 ret = handshake((uint32_t *)&hcor->or_usbsts,
1215 STS_PSS, 0, 100 * 1000);
1216 if (ret < 0) {
1217 printf("EHCI failed: timeout when disabling periodic list\n");
1218 return -ETIMEDOUT;
1219 }
1220 return 0;
1221 }
1222
1223 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1224 unsigned long pipe, int queuesize, int elementsize,
1225 void *buffer, int interval)
1226 {
1227 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1228 struct int_queue *result = NULL;
1229 uint32_t i, toggle;
1230
1231 /*
1232 * Interrupt transfers requiring several transactions are not supported
1233 * because bInterval is ignored.
1234 *
1235 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1236 * <= PKT_ALIGN if several qTDs are required, while the USB
1237 * specification does not constrain this for interrupt transfers. That
1238 * means that ehci_submit_async() would support interrupt transfers
1239 * requiring several transactions only as long as the transfer size does
1240 * not require more than a single qTD.
1241 */
1242 if (elementsize > usb_maxpacket(dev, pipe)) {
1243 printf("%s: xfers requiring several transactions are not supported.\n",
1244 __func__);
1245 return NULL;
1246 }
1247
1248 debug("Enter create_int_queue\n");
1249 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1250 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1251 return NULL;
1252 }
1253
1254 /* limit to 4 full pages worth of data -
1255 * we can safely fit them in a single TD,
1256 * no matter the alignment
1257 */
1258 if (elementsize >= 16384) {
1259 debug("too large elements for interrupt transfers\n");
1260 return NULL;
1261 }
1262
1263 result = malloc(sizeof(*result));
1264 if (!result) {
1265 debug("ehci intr queue: out of memory\n");
1266 goto fail1;
1267 }
1268 result->elementsize = elementsize;
1269 result->pipe = pipe;
1270 result->first = memalign(USB_DMA_MINALIGN,
1271 sizeof(struct QH) * queuesize);
1272 if (!result->first) {
1273 debug("ehci intr queue: out of memory\n");
1274 goto fail2;
1275 }
1276 result->current = result->first;
1277 result->last = result->first + queuesize - 1;
1278 result->tds = memalign(USB_DMA_MINALIGN,
1279 sizeof(struct qTD) * queuesize);
1280 if (!result->tds) {
1281 debug("ehci intr queue: out of memory\n");
1282 goto fail3;
1283 }
1284 memset(result->first, 0, sizeof(struct QH) * queuesize);
1285 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1286
1287 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1288
1289 for (i = 0; i < queuesize; i++) {
1290 struct QH *qh = result->first + i;
1291 struct qTD *td = result->tds + i;
1292 void **buf = &qh->buffer;
1293
1294 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1295 if (i == queuesize - 1)
1296 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1297
1298 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1299 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1300 qh->qh_endpt1 =
1301 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1302 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1303 (1 << 14) |
1304 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1305 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1306 (usb_pipedevice(pipe) << 0));
1307 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1308 (1 << 0)); /* S-mask: microframe 0 */
1309 if (dev->speed == USB_SPEED_LOW ||
1310 dev->speed == USB_SPEED_FULL) {
1311 /* C-mask: microframes 2-4 */
1312 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1313 }
1314 ehci_update_endpt2_dev_n_port(dev, qh);
1315
1316 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1317 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1318 debug("communication direction is '%s'\n",
1319 usb_pipein(pipe) ? "in" : "out");
1320 td->qt_token = cpu_to_hc32(
1321 QT_TOKEN_DT(toggle) |
1322 (elementsize << 16) |
1323 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1324 0x80); /* active */
1325 td->qt_buffer[0] =
1326 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1327 td->qt_buffer[1] =
1328 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1329 td->qt_buffer[2] =
1330 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1331 td->qt_buffer[3] =
1332 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1333 td->qt_buffer[4] =
1334 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1335
1336 *buf = buffer + i * elementsize;
1337 toggle ^= 1;
1338 }
1339
1340 flush_dcache_range((unsigned long)buffer,
1341 ALIGN_END_ADDR(char, buffer,
1342 queuesize * elementsize));
1343 flush_dcache_range((unsigned long)result->first,
1344 ALIGN_END_ADDR(struct QH, result->first,
1345 queuesize));
1346 flush_dcache_range((unsigned long)result->tds,
1347 ALIGN_END_ADDR(struct qTD, result->tds,
1348 queuesize));
1349
1350 if (ctrl->periodic_schedules > 0) {
1351 if (disable_periodic(ctrl) < 0) {
1352 debug("FATAL: periodic should never fail, but did");
1353 goto fail3;
1354 }
1355 }
1356
1357 /* hook up to periodic list */
1358 struct QH *list = &ctrl->periodic_queue;
1359 result->last->qh_link = list->qh_link;
1360 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1361
1362 flush_dcache_range((unsigned long)result->last,
1363 ALIGN_END_ADDR(struct QH, result->last, 1));
1364 flush_dcache_range((unsigned long)list,
1365 ALIGN_END_ADDR(struct QH, list, 1));
1366
1367 if (enable_periodic(ctrl) < 0) {
1368 debug("FATAL: periodic should never fail, but did");
1369 goto fail3;
1370 }
1371 ctrl->periodic_schedules++;
1372
1373 debug("Exit create_int_queue\n");
1374 return result;
1375 fail3:
1376 if (result->tds)
1377 free(result->tds);
1378 fail2:
1379 if (result->first)
1380 free(result->first);
1381 if (result)
1382 free(result);
1383 fail1:
1384 return NULL;
1385 }
1386
1387 static void *_ehci_poll_int_queue(struct usb_device *dev,
1388 struct int_queue *queue)
1389 {
1390 struct QH *cur = queue->current;
1391 struct qTD *cur_td;
1392 uint32_t token, toggle;
1393 unsigned long pipe = queue->pipe;
1394
1395 /* depleted queue */
1396 if (cur == NULL) {
1397 debug("Exit poll_int_queue with completed queue\n");
1398 return NULL;
1399 }
1400 /* still active */
1401 cur_td = &queue->tds[queue->current - queue->first];
1402 invalidate_dcache_range((unsigned long)cur_td,
1403 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1404 token = hc32_to_cpu(cur_td->qt_token);
1405 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1406 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1407 return NULL;
1408 }
1409
1410 toggle = QT_TOKEN_GET_DT(token);
1411 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1412
1413 if (!(cur->qh_link & QH_LINK_TERMINATE))
1414 queue->current++;
1415 else
1416 queue->current = NULL;
1417
1418 invalidate_dcache_range((unsigned long)cur->buffer,
1419 ALIGN_END_ADDR(char, cur->buffer,
1420 queue->elementsize));
1421
1422 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1423 token, cur, queue->first);
1424 return cur->buffer;
1425 }
1426
1427 /* Do not free buffers associated with QHs, they're owned by someone else */
1428 static int _ehci_destroy_int_queue(struct usb_device *dev,
1429 struct int_queue *queue)
1430 {
1431 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1432 int result = -1;
1433 unsigned long timeout;
1434
1435 if (disable_periodic(ctrl) < 0) {
1436 debug("FATAL: periodic should never fail, but did");
1437 goto out;
1438 }
1439 ctrl->periodic_schedules--;
1440
1441 struct QH *cur = &ctrl->periodic_queue;
1442 timeout = get_timer(0) + 500; /* abort after 500ms */
1443 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1444 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1445 if (NEXT_QH(cur) == queue->first) {
1446 debug("found candidate. removing from chain\n");
1447 cur->qh_link = queue->last->qh_link;
1448 flush_dcache_range((unsigned long)cur,
1449 ALIGN_END_ADDR(struct QH, cur, 1));
1450 result = 0;
1451 break;
1452 }
1453 cur = NEXT_QH(cur);
1454 if (get_timer(0) > timeout) {
1455 printf("Timeout destroying interrupt endpoint queue\n");
1456 result = -1;
1457 goto out;
1458 }
1459 }
1460
1461 if (ctrl->periodic_schedules > 0) {
1462 result = enable_periodic(ctrl);
1463 if (result < 0)
1464 debug("FATAL: periodic should never fail, but did");
1465 }
1466
1467 out:
1468 free(queue->tds);
1469 free(queue->first);
1470 free(queue);
1471
1472 return result;
1473 }
1474
1475 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1476 void *buffer, int length, int interval)
1477 {
1478 void *backbuffer;
1479 struct int_queue *queue;
1480 unsigned long timeout;
1481 int result = 0, ret;
1482
1483 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1484 dev, pipe, buffer, length, interval);
1485
1486 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1487 if (!queue)
1488 return -1;
1489
1490 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1491 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1492 if (get_timer(0) > timeout) {
1493 printf("Timeout poll on interrupt endpoint\n");
1494 result = -ETIMEDOUT;
1495 break;
1496 }
1497
1498 if (backbuffer != buffer) {
1499 debug("got wrong buffer back (%p instead of %p)\n",
1500 backbuffer, buffer);
1501 return -EINVAL;
1502 }
1503
1504 ret = _ehci_destroy_int_queue(dev, queue);
1505 if (ret < 0)
1506 return ret;
1507
1508 /* everything worked out fine */
1509 return result;
1510 }
1511
1512 #ifndef CONFIG_DM_USB
1513 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1514 void *buffer, int length)
1515 {
1516 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1517 }
1518
1519 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1520 int length, struct devrequest *setup)
1521 {
1522 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1523 }
1524
1525 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1526 void *buffer, int length, int interval)
1527 {
1528 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
1529 }
1530
1531 struct int_queue *create_int_queue(struct usb_device *dev,
1532 unsigned long pipe, int queuesize, int elementsize,
1533 void *buffer, int interval)
1534 {
1535 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1536 buffer, interval);
1537 }
1538
1539 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1540 {
1541 return _ehci_poll_int_queue(dev, queue);
1542 }
1543
1544 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1545 {
1546 return _ehci_destroy_int_queue(dev, queue);
1547 }
1548 #endif
1549
1550 #ifdef CONFIG_DM_USB
1551 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1552 unsigned long pipe, void *buffer, int length,
1553 struct devrequest *setup)
1554 {
1555 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1556 dev->name, udev, udev->dev->name, udev->portnr);
1557
1558 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1559 }
1560
1561 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1562 unsigned long pipe, void *buffer, int length)
1563 {
1564 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1565 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1566 }
1567
1568 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1569 unsigned long pipe, void *buffer, int length,
1570 int interval)
1571 {
1572 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1573 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
1574 }
1575
1576 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1577 struct usb_device *udev, unsigned long pipe, int queuesize,
1578 int elementsize, void *buffer, int interval)
1579 {
1580 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1581 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1582 buffer, interval);
1583 }
1584
1585 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1586 struct int_queue *queue)
1587 {
1588 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1589 return _ehci_poll_int_queue(udev, queue);
1590 }
1591
1592 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1593 struct int_queue *queue)
1594 {
1595 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1596 return _ehci_destroy_int_queue(udev, queue);
1597 }
1598
1599 static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size)
1600 {
1601 /*
1602 * EHCD can handle any transfer length as long as there is enough
1603 * free heap space left, hence set the theoretical max number here.
1604 */
1605 *size = SIZE_MAX;
1606
1607 return 0;
1608 }
1609
1610 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1611 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1612 uint tweaks, enum usb_init_type init)
1613 {
1614 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1615 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1616 int ret = -1;
1617
1618 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1619 dev->name, ctrl, hccr, hcor, init);
1620
1621 if (!ctrl || !hccr || !hcor)
1622 goto err;
1623
1624 priv->desc_before_addr = true;
1625
1626 ehci_setup_ops(ctrl, ops);
1627 ctrl->hccr = hccr;
1628 ctrl->hcor = hcor;
1629 ctrl->priv = ctrl;
1630
1631 ctrl->init = init;
1632 if (ctrl->init == USB_INIT_DEVICE)
1633 goto done;
1634
1635 ret = ehci_reset(ctrl);
1636 if (ret)
1637 goto err;
1638
1639 if (ctrl->ops.init_after_reset) {
1640 ret = ctrl->ops.init_after_reset(ctrl);
1641 if (ret)
1642 goto err;
1643 }
1644
1645 ret = ehci_common_init(ctrl, tweaks);
1646 if (ret)
1647 goto err;
1648 done:
1649 return 0;
1650 err:
1651 free(ctrl);
1652 debug("%s: failed, ret=%d\n", __func__, ret);
1653 return ret;
1654 }
1655
1656 int ehci_deregister(struct udevice *dev)
1657 {
1658 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1659
1660 if (ctrl->init == USB_INIT_DEVICE)
1661 return 0;
1662
1663 ehci_shutdown(ctrl);
1664
1665 return 0;
1666 }
1667
1668 struct dm_usb_ops ehci_usb_ops = {
1669 .control = ehci_submit_control_msg,
1670 .bulk = ehci_submit_bulk_msg,
1671 .interrupt = ehci_submit_int_msg,
1672 .create_int_queue = ehci_create_int_queue,
1673 .poll_int_queue = ehci_poll_int_queue,
1674 .destroy_int_queue = ehci_destroy_int_queue,
1675 .get_max_xfer_size = ehci_get_max_xfer_size,
1676 };
1677
1678 #endif
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