]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/usb/host/ehci-hcd.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge git://git.denx.de/u-boot-marvell
[people/ms/u-boot.git] / drivers / usb / host / ehci-hcd.c
1 /*-
2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
5 *
6 * All rights reserved.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <asm/byteorder.h>
14 #include <asm/unaligned.h>
15 #include <usb.h>
16 #include <asm/io.h>
17 #include <malloc.h>
18 #include <watchdog.h>
19 #include <linux/compiler.h>
20
21 #include "ehci.h"
22
23 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
24 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
25 #endif
26
27 /*
28 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
29 * Let's time out after 8 to have a little safety margin on top of that.
30 */
31 #define HCHALT_TIMEOUT (8 * 1000)
32
33 #ifndef CONFIG_DM_USB
34 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
35 #endif
36
37 #define ALIGN_END_ADDR(type, ptr, size) \
38 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
39
40 static struct descriptor {
41 struct usb_hub_descriptor hub;
42 struct usb_device_descriptor device;
43 struct usb_linux_config_descriptor config;
44 struct usb_linux_interface_descriptor interface;
45 struct usb_endpoint_descriptor endpoint;
46 } __attribute__ ((packed)) descriptor = {
47 {
48 0x8, /* bDescLength */
49 0x29, /* bDescriptorType: hub descriptor */
50 2, /* bNrPorts -- runtime modified */
51 0, /* wHubCharacteristics */
52 10, /* bPwrOn2PwrGood */
53 0, /* bHubCntrCurrent */
54 {}, /* Device removable */
55 {} /* at most 7 ports! XXX */
56 },
57 {
58 0x12, /* bLength */
59 1, /* bDescriptorType: UDESC_DEVICE */
60 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
61 9, /* bDeviceClass: UDCLASS_HUB */
62 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
63 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
64 64, /* bMaxPacketSize: 64 bytes */
65 0x0000, /* idVendor */
66 0x0000, /* idProduct */
67 cpu_to_le16(0x0100), /* bcdDevice */
68 1, /* iManufacturer */
69 2, /* iProduct */
70 0, /* iSerialNumber */
71 1 /* bNumConfigurations: 1 */
72 },
73 {
74 0x9,
75 2, /* bDescriptorType: UDESC_CONFIG */
76 cpu_to_le16(0x19),
77 1, /* bNumInterface */
78 1, /* bConfigurationValue */
79 0, /* iConfiguration */
80 0x40, /* bmAttributes: UC_SELF_POWER */
81 0 /* bMaxPower */
82 },
83 {
84 0x9, /* bLength */
85 4, /* bDescriptorType: UDESC_INTERFACE */
86 0, /* bInterfaceNumber */
87 0, /* bAlternateSetting */
88 1, /* bNumEndpoints */
89 9, /* bInterfaceClass: UICLASS_HUB */
90 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
91 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
92 0 /* iInterface */
93 },
94 {
95 0x7, /* bLength */
96 5, /* bDescriptorType: UDESC_ENDPOINT */
97 0x81, /* bEndpointAddress:
98 * UE_DIR_IN | EHCI_INTR_ENDPT
99 */
100 3, /* bmAttributes: UE_INTERRUPT */
101 8, /* wMaxPacketSize */
102 255 /* bInterval */
103 },
104 };
105
106 #if defined(CONFIG_EHCI_IS_TDI)
107 #define ehci_is_TDI() (1)
108 #else
109 #define ehci_is_TDI() (0)
110 #endif
111
112 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
113 {
114 #ifdef CONFIG_DM_USB
115 return dev_get_priv(usb_get_bus(udev->dev));
116 #else
117 return udev->controller;
118 #endif
119 }
120
121 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
122 {
123 return PORTSC_PSPD(reg);
124 }
125
126 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
127 {
128 uint32_t tmp;
129 uint32_t *reg_ptr;
130
131 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
132 tmp = ehci_readl(reg_ptr);
133 tmp |= USBMODE_CM_HC;
134 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
135 tmp |= USBMODE_BE;
136 #endif
137 ehci_writel(reg_ptr, tmp);
138 }
139
140 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
141 uint32_t *reg)
142 {
143 mdelay(50);
144 }
145
146 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
147 {
148 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
149 /* Printing the message would cause a scan failure! */
150 debug("The request port(%u) is not configured\n", port);
151 return NULL;
152 }
153
154 return (uint32_t *)&ctrl->hcor->or_portsc[port];
155 }
156
157 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
158 {
159 uint32_t result;
160 do {
161 result = ehci_readl(ptr);
162 udelay(5);
163 if (result == ~(uint32_t)0)
164 return -1;
165 result &= mask;
166 if (result == done)
167 return 0;
168 usec--;
169 } while (usec > 0);
170 return -1;
171 }
172
173 static int ehci_reset(struct ehci_ctrl *ctrl)
174 {
175 uint32_t cmd;
176 int ret = 0;
177
178 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
179 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
180 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
181 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
182 CMD_RESET, 0, 250 * 1000);
183 if (ret < 0) {
184 printf("EHCI fail to reset\n");
185 goto out;
186 }
187
188 if (ehci_is_TDI())
189 ctrl->ops.set_usb_mode(ctrl);
190
191 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
192 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
193 cmd &= ~TXFIFO_THRESH_MASK;
194 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
195 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
196 #endif
197 out:
198 return ret;
199 }
200
201 static int ehci_shutdown(struct ehci_ctrl *ctrl)
202 {
203 int i, ret = 0;
204 uint32_t cmd, reg;
205
206 if (!ctrl || !ctrl->hcor)
207 return -EINVAL;
208
209 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
210 cmd &= ~(CMD_PSE | CMD_ASE);
211 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
212 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
213 100 * 1000);
214
215 if (!ret) {
216 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
217 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
218 reg |= EHCI_PS_SUSP;
219 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
220 }
221
222 cmd &= ~CMD_RUN;
223 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
224 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
225 HCHALT_TIMEOUT);
226 }
227
228 if (ret)
229 puts("EHCI failed to shut down host controller.\n");
230
231 return ret;
232 }
233
234 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
235 {
236 uint32_t delta, next;
237 uint32_t addr = (unsigned long)buf;
238 int idx;
239
240 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
241 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
242
243 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
244
245 idx = 0;
246 while (idx < QT_BUFFER_CNT) {
247 td->qt_buffer[idx] = cpu_to_hc32(addr);
248 td->qt_buffer_hi[idx] = 0;
249 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
250 delta = next - addr;
251 if (delta >= sz)
252 break;
253 sz -= delta;
254 addr = next;
255 idx++;
256 }
257
258 if (idx == QT_BUFFER_CNT) {
259 printf("out of buffer pointers (%zu bytes left)\n", sz);
260 return -1;
261 }
262
263 return 0;
264 }
265
266 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
267 {
268 #define QH_HIGH_SPEED 2
269 #define QH_FULL_SPEED 0
270 #define QH_LOW_SPEED 1
271 if (speed == USB_SPEED_HIGH)
272 return QH_HIGH_SPEED;
273 if (speed == USB_SPEED_LOW)
274 return QH_LOW_SPEED;
275 return QH_FULL_SPEED;
276 }
277
278 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
279 struct QH *qh)
280 {
281 struct usb_device *ttdev;
282 int parent_devnum;
283
284 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
285 return;
286
287 /*
288 * For full / low speed devices we need to get the devnum and portnr of
289 * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs
290 * in the tree before that one!
291 */
292 #ifdef CONFIG_DM_USB
293 /*
294 * When called from usb-uclass.c: usb_scan_device() udev->dev points
295 * to the parent udevice, not the actual udevice belonging to the
296 * udev as the device is not instantiated yet. So when searching
297 * for the first usb-2 parent start with udev->dev not
298 * udev->dev->parent .
299 */
300 struct udevice *parent;
301 struct usb_device *uparent;
302
303 ttdev = udev;
304 parent = udev->dev;
305 uparent = dev_get_parentdata(parent);
306
307 while (uparent->speed != USB_SPEED_HIGH) {
308 struct udevice *dev = parent;
309
310 if (device_get_uclass_id(dev->parent) != UCLASS_USB_HUB) {
311 printf("ehci: Error cannot find high-speed parent of usb-1 device\n");
312 return;
313 }
314
315 ttdev = dev_get_parentdata(dev);
316 parent = dev->parent;
317 uparent = dev_get_parentdata(parent);
318 }
319 parent_devnum = uparent->devnum;
320 #else
321 ttdev = udev;
322 while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH)
323 ttdev = ttdev->parent;
324 if (!ttdev->parent)
325 return;
326 parent_devnum = ttdev->parent->devnum;
327 #endif
328
329 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) |
330 QH_ENDPT2_HUBADDR(parent_devnum));
331 }
332
333 static int
334 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
335 int length, struct devrequest *req)
336 {
337 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
338 struct qTD *qtd;
339 int qtd_count = 0;
340 int qtd_counter = 0;
341 volatile struct qTD *vtd;
342 unsigned long ts;
343 uint32_t *tdp;
344 uint32_t endpt, maxpacket, token, usbsts;
345 uint32_t c, toggle;
346 uint32_t cmd;
347 int timeout;
348 int ret = 0;
349 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
350
351 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
352 buffer, length, req);
353 if (req != NULL)
354 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
355 req->request, req->request,
356 req->requesttype, req->requesttype,
357 le16_to_cpu(req->value), le16_to_cpu(req->value),
358 le16_to_cpu(req->index));
359
360 #define PKT_ALIGN 512
361 /*
362 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
363 * described by a transfer descriptor (the qTD). The qTDs form a linked
364 * list with a queue head (QH).
365 *
366 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
367 * have its beginning in a qTD transfer and its end in the following
368 * one, so the qTD transfer lengths have to be chosen accordingly.
369 *
370 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
371 * single pages. The first data buffer can start at any offset within a
372 * page (not considering the cache-line alignment issues), while the
373 * following buffers must be page-aligned. There is no alignment
374 * constraint on the size of a qTD transfer.
375 */
376 if (req != NULL)
377 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
378 qtd_count += 1 + 1;
379 if (length > 0 || req == NULL) {
380 /*
381 * Determine the qTD transfer size that will be used for the
382 * data payload (not considering the first qTD transfer, which
383 * may be longer or shorter, and the final one, which may be
384 * shorter).
385 *
386 * In order to keep each packet within a qTD transfer, the qTD
387 * transfer size is aligned to PKT_ALIGN, which is a multiple of
388 * wMaxPacketSize (except in some cases for interrupt transfers,
389 * see comment in submit_int_msg()).
390 *
391 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
392 * QT_BUFFER_CNT full pages will be used.
393 */
394 int xfr_sz = QT_BUFFER_CNT;
395 /*
396 * However, if the input buffer is not aligned to PKT_ALIGN, the
397 * qTD transfer size will be one page shorter, and the first qTD
398 * data buffer of each transfer will be page-unaligned.
399 */
400 if ((unsigned long)buffer & (PKT_ALIGN - 1))
401 xfr_sz--;
402 /* Convert the qTD transfer size to bytes. */
403 xfr_sz *= EHCI_PAGE_SIZE;
404 /*
405 * Approximate by excess the number of qTDs that will be
406 * required for the data payload. The exact formula is way more
407 * complicated and saves at most 2 qTDs, i.e. a total of 128
408 * bytes.
409 */
410 qtd_count += 2 + length / xfr_sz;
411 }
412 /*
413 * Threshold value based on the worst-case total size of the allocated qTDs for
414 * a mass-storage transfer of 65535 blocks of 512 bytes.
415 */
416 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
417 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
418 #endif
419 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
420 if (qtd == NULL) {
421 printf("unable to allocate TDs\n");
422 return -1;
423 }
424
425 memset(qh, 0, sizeof(struct QH));
426 memset(qtd, 0, qtd_count * sizeof(*qtd));
427
428 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
429
430 /*
431 * Setup QH (3.6 in ehci-r10.pdf)
432 *
433 * qh_link ................. 03-00 H
434 * qh_endpt1 ............... 07-04 H
435 * qh_endpt2 ............... 0B-08 H
436 * - qh_curtd
437 * qh_overlay.qt_next ...... 13-10 H
438 * - qh_overlay.qt_altnext
439 */
440 qh->qh_link = cpu_to_hc32((unsigned long)&ctrl->qh_list | QH_LINK_TYPE_QH);
441 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
442 maxpacket = usb_maxpacket(dev, pipe);
443 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
444 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
445 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
446 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
447 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
448 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
449 qh->qh_endpt1 = cpu_to_hc32(endpt);
450 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
451 qh->qh_endpt2 = cpu_to_hc32(endpt);
452 ehci_update_endpt2_dev_n_port(dev, qh);
453 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
454 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
455
456 tdp = &qh->qh_overlay.qt_next;
457
458 if (req != NULL) {
459 /*
460 * Setup request qTD (3.5 in ehci-r10.pdf)
461 *
462 * qt_next ................ 03-00 H
463 * qt_altnext ............. 07-04 H
464 * qt_token ............... 0B-08 H
465 *
466 * [ buffer, buffer_hi ] loaded with "req".
467 */
468 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
469 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
470 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
471 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
472 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
473 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
474 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
475 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
476 printf("unable to construct SETUP TD\n");
477 goto fail;
478 }
479 /* Update previous qTD! */
480 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
481 tdp = &qtd[qtd_counter++].qt_next;
482 toggle = 1;
483 }
484
485 if (length > 0 || req == NULL) {
486 uint8_t *buf_ptr = buffer;
487 int left_length = length;
488
489 do {
490 /*
491 * Determine the size of this qTD transfer. By default,
492 * QT_BUFFER_CNT full pages can be used.
493 */
494 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
495 /*
496 * However, if the input buffer is not page-aligned, the
497 * portion of the first page before the buffer start
498 * offset within that page is unusable.
499 */
500 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
501 /*
502 * In order to keep each packet within a qTD transfer,
503 * align the qTD transfer size to PKT_ALIGN.
504 */
505 xfr_bytes &= ~(PKT_ALIGN - 1);
506 /*
507 * This transfer may be shorter than the available qTD
508 * transfer size that has just been computed.
509 */
510 xfr_bytes = min(xfr_bytes, left_length);
511
512 /*
513 * Setup request qTD (3.5 in ehci-r10.pdf)
514 *
515 * qt_next ................ 03-00 H
516 * qt_altnext ............. 07-04 H
517 * qt_token ............... 0B-08 H
518 *
519 * [ buffer, buffer_hi ] loaded with "buffer".
520 */
521 qtd[qtd_counter].qt_next =
522 cpu_to_hc32(QT_NEXT_TERMINATE);
523 qtd[qtd_counter].qt_altnext =
524 cpu_to_hc32(QT_NEXT_TERMINATE);
525 token = QT_TOKEN_DT(toggle) |
526 QT_TOKEN_TOTALBYTES(xfr_bytes) |
527 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
528 QT_TOKEN_CERR(3) |
529 QT_TOKEN_PID(usb_pipein(pipe) ?
530 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
531 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
532 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
533 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
534 xfr_bytes)) {
535 printf("unable to construct DATA TD\n");
536 goto fail;
537 }
538 /* Update previous qTD! */
539 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
540 tdp = &qtd[qtd_counter++].qt_next;
541 /*
542 * Data toggle has to be adjusted since the qTD transfer
543 * size is not always an even multiple of
544 * wMaxPacketSize.
545 */
546 if ((xfr_bytes / maxpacket) & 1)
547 toggle ^= 1;
548 buf_ptr += xfr_bytes;
549 left_length -= xfr_bytes;
550 } while (left_length > 0);
551 }
552
553 if (req != NULL) {
554 /*
555 * Setup request qTD (3.5 in ehci-r10.pdf)
556 *
557 * qt_next ................ 03-00 H
558 * qt_altnext ............. 07-04 H
559 * qt_token ............... 0B-08 H
560 */
561 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
562 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
563 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
564 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
565 QT_TOKEN_PID(usb_pipein(pipe) ?
566 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
567 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
568 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
569 /* Update previous qTD! */
570 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
571 tdp = &qtd[qtd_counter++].qt_next;
572 }
573
574 ctrl->qh_list.qh_link = cpu_to_hc32((unsigned long)qh | QH_LINK_TYPE_QH);
575
576 /* Flush dcache */
577 flush_dcache_range((unsigned long)&ctrl->qh_list,
578 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
579 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
580 flush_dcache_range((unsigned long)qtd,
581 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
582
583 /* Set async. queue head pointer. */
584 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)&ctrl->qh_list);
585
586 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
587 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
588
589 /* Enable async. schedule. */
590 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
591 cmd |= CMD_ASE;
592 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
593
594 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
595 100 * 1000);
596 if (ret < 0) {
597 printf("EHCI fail timeout STS_ASS set\n");
598 goto fail;
599 }
600
601 /* Wait for TDs to be processed. */
602 ts = get_timer(0);
603 vtd = &qtd[qtd_counter - 1];
604 timeout = USB_TIMEOUT_MS(pipe);
605 do {
606 /* Invalidate dcache */
607 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
608 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
609 invalidate_dcache_range((unsigned long)qh,
610 ALIGN_END_ADDR(struct QH, qh, 1));
611 invalidate_dcache_range((unsigned long)qtd,
612 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
613
614 token = hc32_to_cpu(vtd->qt_token);
615 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
616 break;
617 WATCHDOG_RESET();
618 } while (get_timer(ts) < timeout);
619
620 /*
621 * Invalidate the memory area occupied by buffer
622 * Don't try to fix the buffer alignment, if it isn't properly
623 * aligned it's upper layer's fault so let invalidate_dcache_range()
624 * vow about it. But we have to fix the length as it's actual
625 * transfer length and can be unaligned. This is potentially
626 * dangerous operation, it's responsibility of the calling
627 * code to make sure enough space is reserved.
628 */
629 invalidate_dcache_range((unsigned long)buffer,
630 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
631
632 /* Check that the TD processing happened */
633 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
634 printf("EHCI timed out on TD - token=%#x\n", token);
635
636 /* Disable async schedule. */
637 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
638 cmd &= ~CMD_ASE;
639 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
640
641 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
642 100 * 1000);
643 if (ret < 0) {
644 printf("EHCI fail timeout STS_ASS reset\n");
645 goto fail;
646 }
647
648 token = hc32_to_cpu(qh->qh_overlay.qt_token);
649 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
650 debug("TOKEN=%#x\n", token);
651 switch (QT_TOKEN_GET_STATUS(token) &
652 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
653 case 0:
654 toggle = QT_TOKEN_GET_DT(token);
655 usb_settoggle(dev, usb_pipeendpoint(pipe),
656 usb_pipeout(pipe), toggle);
657 dev->status = 0;
658 break;
659 case QT_TOKEN_STATUS_HALTED:
660 dev->status = USB_ST_STALLED;
661 break;
662 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
663 case QT_TOKEN_STATUS_DATBUFERR:
664 dev->status = USB_ST_BUF_ERR;
665 break;
666 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
667 case QT_TOKEN_STATUS_BABBLEDET:
668 dev->status = USB_ST_BABBLE_DET;
669 break;
670 default:
671 dev->status = USB_ST_CRC_ERR;
672 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
673 dev->status |= USB_ST_STALLED;
674 break;
675 }
676 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
677 } else {
678 dev->act_len = 0;
679 #ifndef CONFIG_USB_EHCI_FARADAY
680 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
681 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
682 ehci_readl(&ctrl->hcor->or_portsc[0]),
683 ehci_readl(&ctrl->hcor->or_portsc[1]));
684 #endif
685 }
686
687 free(qtd);
688 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
689
690 fail:
691 free(qtd);
692 return -1;
693 }
694
695 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
696 void *buffer, int length, struct devrequest *req)
697 {
698 uint8_t tmpbuf[4];
699 u16 typeReq;
700 void *srcptr = NULL;
701 int len, srclen;
702 uint32_t reg;
703 uint32_t *status_reg;
704 int port = le16_to_cpu(req->index) & 0xff;
705 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
706
707 srclen = 0;
708
709 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
710 req->request, req->request,
711 req->requesttype, req->requesttype,
712 le16_to_cpu(req->value), le16_to_cpu(req->index));
713
714 typeReq = req->request | req->requesttype << 8;
715
716 switch (typeReq) {
717 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
718 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
719 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
720 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
721 if (!status_reg)
722 return -1;
723 break;
724 default:
725 status_reg = NULL;
726 break;
727 }
728
729 switch (typeReq) {
730 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
731 switch (le16_to_cpu(req->value) >> 8) {
732 case USB_DT_DEVICE:
733 debug("USB_DT_DEVICE request\n");
734 srcptr = &descriptor.device;
735 srclen = descriptor.device.bLength;
736 break;
737 case USB_DT_CONFIG:
738 debug("USB_DT_CONFIG config\n");
739 srcptr = &descriptor.config;
740 srclen = descriptor.config.bLength +
741 descriptor.interface.bLength +
742 descriptor.endpoint.bLength;
743 break;
744 case USB_DT_STRING:
745 debug("USB_DT_STRING config\n");
746 switch (le16_to_cpu(req->value) & 0xff) {
747 case 0: /* Language */
748 srcptr = "\4\3\1\0";
749 srclen = 4;
750 break;
751 case 1: /* Vendor */
752 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
753 srclen = 14;
754 break;
755 case 2: /* Product */
756 srcptr = "\52\3E\0H\0C\0I\0 "
757 "\0H\0o\0s\0t\0 "
758 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
759 srclen = 42;
760 break;
761 default:
762 debug("unknown value DT_STRING %x\n",
763 le16_to_cpu(req->value));
764 goto unknown;
765 }
766 break;
767 default:
768 debug("unknown value %x\n", le16_to_cpu(req->value));
769 goto unknown;
770 }
771 break;
772 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
773 switch (le16_to_cpu(req->value) >> 8) {
774 case USB_DT_HUB:
775 debug("USB_DT_HUB config\n");
776 srcptr = &descriptor.hub;
777 srclen = descriptor.hub.bLength;
778 break;
779 default:
780 debug("unknown value %x\n", le16_to_cpu(req->value));
781 goto unknown;
782 }
783 break;
784 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
785 debug("USB_REQ_SET_ADDRESS\n");
786 ctrl->rootdev = le16_to_cpu(req->value);
787 break;
788 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
789 debug("USB_REQ_SET_CONFIGURATION\n");
790 /* Nothing to do */
791 break;
792 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
793 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
794 tmpbuf[1] = 0;
795 srcptr = tmpbuf;
796 srclen = 2;
797 break;
798 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
799 memset(tmpbuf, 0, 4);
800 reg = ehci_readl(status_reg);
801 if (reg & EHCI_PS_CS)
802 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
803 if (reg & EHCI_PS_PE)
804 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
805 if (reg & EHCI_PS_SUSP)
806 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
807 if (reg & EHCI_PS_OCA)
808 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
809 if (reg & EHCI_PS_PR)
810 tmpbuf[0] |= USB_PORT_STAT_RESET;
811 if (reg & EHCI_PS_PP)
812 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
813
814 if (ehci_is_TDI()) {
815 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
816 case PORTSC_PSPD_FS:
817 break;
818 case PORTSC_PSPD_LS:
819 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
820 break;
821 case PORTSC_PSPD_HS:
822 default:
823 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
824 break;
825 }
826 } else {
827 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
828 }
829
830 if (reg & EHCI_PS_CSC)
831 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
832 if (reg & EHCI_PS_PEC)
833 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
834 if (reg & EHCI_PS_OCC)
835 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
836 if (ctrl->portreset & (1 << port))
837 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
838
839 srcptr = tmpbuf;
840 srclen = 4;
841 break;
842 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
843 reg = ehci_readl(status_reg);
844 reg &= ~EHCI_PS_CLEAR;
845 switch (le16_to_cpu(req->value)) {
846 case USB_PORT_FEAT_ENABLE:
847 reg |= EHCI_PS_PE;
848 ehci_writel(status_reg, reg);
849 break;
850 case USB_PORT_FEAT_POWER:
851 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
852 reg |= EHCI_PS_PP;
853 ehci_writel(status_reg, reg);
854 }
855 break;
856 case USB_PORT_FEAT_RESET:
857 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
858 !ehci_is_TDI() &&
859 EHCI_PS_IS_LOWSPEED(reg)) {
860 /* Low speed device, give up ownership. */
861 debug("port %d low speed --> companion\n",
862 port - 1);
863 reg |= EHCI_PS_PO;
864 ehci_writel(status_reg, reg);
865 return -ENXIO;
866 } else {
867 int ret;
868
869 reg |= EHCI_PS_PR;
870 reg &= ~EHCI_PS_PE;
871 ehci_writel(status_reg, reg);
872 /*
873 * caller must wait, then call GetPortStatus
874 * usb 2.0 specification say 50 ms resets on
875 * root
876 */
877 ctrl->ops.powerup_fixup(ctrl, status_reg, &reg);
878
879 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
880 /*
881 * A host controller must terminate the reset
882 * and stabilize the state of the port within
883 * 2 milliseconds
884 */
885 ret = handshake(status_reg, EHCI_PS_PR, 0,
886 2 * 1000);
887 if (!ret) {
888 reg = ehci_readl(status_reg);
889 if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
890 == EHCI_PS_CS && !ehci_is_TDI()) {
891 debug("port %d full speed --> companion\n", port - 1);
892 reg &= ~EHCI_PS_CLEAR;
893 reg |= EHCI_PS_PO;
894 ehci_writel(status_reg, reg);
895 return -ENXIO;
896 } else {
897 ctrl->portreset |= 1 << port;
898 }
899 } else {
900 printf("port(%d) reset error\n",
901 port - 1);
902 }
903 }
904 break;
905 case USB_PORT_FEAT_TEST:
906 ehci_shutdown(ctrl);
907 reg &= ~(0xf << 16);
908 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
909 ehci_writel(status_reg, reg);
910 break;
911 default:
912 debug("unknown feature %x\n", le16_to_cpu(req->value));
913 goto unknown;
914 }
915 /* unblock posted writes */
916 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
917 break;
918 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
919 reg = ehci_readl(status_reg);
920 reg &= ~EHCI_PS_CLEAR;
921 switch (le16_to_cpu(req->value)) {
922 case USB_PORT_FEAT_ENABLE:
923 reg &= ~EHCI_PS_PE;
924 break;
925 case USB_PORT_FEAT_C_ENABLE:
926 reg |= EHCI_PS_PE;
927 break;
928 case USB_PORT_FEAT_POWER:
929 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
930 reg &= ~EHCI_PS_PP;
931 break;
932 case USB_PORT_FEAT_C_CONNECTION:
933 reg |= EHCI_PS_CSC;
934 break;
935 case USB_PORT_FEAT_OVER_CURRENT:
936 reg |= EHCI_PS_OCC;
937 break;
938 case USB_PORT_FEAT_C_RESET:
939 ctrl->portreset &= ~(1 << port);
940 break;
941 default:
942 debug("unknown feature %x\n", le16_to_cpu(req->value));
943 goto unknown;
944 }
945 ehci_writel(status_reg, reg);
946 /* unblock posted write */
947 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
948 break;
949 default:
950 debug("Unknown request\n");
951 goto unknown;
952 }
953
954 mdelay(1);
955 len = min3(srclen, (int)le16_to_cpu(req->length), length);
956 if (srcptr != NULL && len > 0)
957 memcpy(buffer, srcptr, len);
958 else
959 debug("Len is 0\n");
960
961 dev->act_len = len;
962 dev->status = 0;
963 return 0;
964
965 unknown:
966 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
967 req->requesttype, req->request, le16_to_cpu(req->value),
968 le16_to_cpu(req->index), le16_to_cpu(req->length));
969
970 dev->act_len = 0;
971 dev->status = USB_ST_STALLED;
972 return -1;
973 }
974
975 const struct ehci_ops default_ehci_ops = {
976 .set_usb_mode = ehci_set_usbmode,
977 .get_port_speed = ehci_get_port_speed,
978 .powerup_fixup = ehci_powerup_fixup,
979 .get_portsc_register = ehci_get_portsc_register,
980 };
981
982 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
983 {
984 if (!ops) {
985 ctrl->ops = default_ehci_ops;
986 } else {
987 ctrl->ops = *ops;
988 if (!ctrl->ops.set_usb_mode)
989 ctrl->ops.set_usb_mode = ehci_set_usbmode;
990 if (!ctrl->ops.get_port_speed)
991 ctrl->ops.get_port_speed = ehci_get_port_speed;
992 if (!ctrl->ops.powerup_fixup)
993 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
994 if (!ctrl->ops.get_portsc_register)
995 ctrl->ops.get_portsc_register =
996 ehci_get_portsc_register;
997 }
998 }
999
1000 #ifndef CONFIG_DM_USB
1001 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
1002 {
1003 struct ehci_ctrl *ctrl = &ehcic[index];
1004
1005 ctrl->priv = priv;
1006 ehci_setup_ops(ctrl, ops);
1007 }
1008
1009 void *ehci_get_controller_priv(int index)
1010 {
1011 return ehcic[index].priv;
1012 }
1013 #endif
1014
1015 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
1016 {
1017 struct QH *qh_list;
1018 struct QH *periodic;
1019 uint32_t reg;
1020 uint32_t cmd;
1021 int i;
1022
1023 /* Set the high address word (aka segment) for 64-bit controller */
1024 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1025 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1026
1027 qh_list = &ctrl->qh_list;
1028
1029 /* Set head of reclaim list */
1030 memset(qh_list, 0, sizeof(*qh_list));
1031 qh_list->qh_link = cpu_to_hc32((unsigned long)qh_list | QH_LINK_TYPE_QH);
1032 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1033 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1034 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1035 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1036 qh_list->qh_overlay.qt_token =
1037 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1038
1039 flush_dcache_range((unsigned long)qh_list,
1040 ALIGN_END_ADDR(struct QH, qh_list, 1));
1041
1042 /* Set async. queue head pointer. */
1043 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)qh_list);
1044
1045 /*
1046 * Set up periodic list
1047 * Step 1: Parent QH for all periodic transfers.
1048 */
1049 ctrl->periodic_schedules = 0;
1050 periodic = &ctrl->periodic_queue;
1051 memset(periodic, 0, sizeof(*periodic));
1052 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1053 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1054 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1055
1056 flush_dcache_range((unsigned long)periodic,
1057 ALIGN_END_ADDR(struct QH, periodic, 1));
1058
1059 /*
1060 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1061 * In particular, device specifications on polling frequency
1062 * are disregarded. Keyboards seem to send NAK/NYet reliably
1063 * when polled with an empty buffer.
1064 *
1065 * Split Transactions will be spread across microframes using
1066 * S-mask and C-mask.
1067 */
1068 if (ctrl->periodic_list == NULL)
1069 ctrl->periodic_list = memalign(4096, 1024 * 4);
1070
1071 if (!ctrl->periodic_list)
1072 return -ENOMEM;
1073 for (i = 0; i < 1024; i++) {
1074 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1075 | QH_LINK_TYPE_QH);
1076 }
1077
1078 flush_dcache_range((unsigned long)ctrl->periodic_list,
1079 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1080 1024));
1081
1082 /* Set periodic list base address */
1083 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1084 (unsigned long)ctrl->periodic_list);
1085
1086 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1087 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1088 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1089 /* Port Indicators */
1090 if (HCS_INDICATOR(reg))
1091 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1092 | 0x80, &descriptor.hub.wHubCharacteristics);
1093 /* Port Power Control */
1094 if (HCS_PPC(reg))
1095 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1096 | 0x01, &descriptor.hub.wHubCharacteristics);
1097
1098 /* Start the host controller. */
1099 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1100 /*
1101 * Philips, Intel, and maybe others need CMD_RUN before the
1102 * root hub will detect new devices (why?); NEC doesn't
1103 */
1104 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1105 cmd |= CMD_RUN;
1106 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1107
1108 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1109 /* take control over the ports */
1110 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1111 cmd |= FLAG_CF;
1112 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1113 }
1114
1115 /* unblock posted write */
1116 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1117 mdelay(5);
1118 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1119 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1120
1121 return 0;
1122 }
1123
1124 #ifndef CONFIG_DM_USB
1125 int usb_lowlevel_stop(int index)
1126 {
1127 ehci_shutdown(&ehcic[index]);
1128 return ehci_hcd_stop(index);
1129 }
1130
1131 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1132 {
1133 struct ehci_ctrl *ctrl = &ehcic[index];
1134 uint tweaks = 0;
1135 int rc;
1136
1137 /**
1138 * Set ops to default_ehci_ops, ehci_hcd_init should call
1139 * ehci_set_controller_priv to change any of these function pointers.
1140 */
1141 ctrl->ops = default_ehci_ops;
1142
1143 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1144 if (rc)
1145 return rc;
1146 if (init == USB_INIT_DEVICE)
1147 goto done;
1148
1149 /* EHCI spec section 4.1 */
1150 if (ehci_reset(ctrl))
1151 return -1;
1152
1153 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1154 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1155 if (rc)
1156 return rc;
1157 #endif
1158 #ifdef CONFIG_USB_EHCI_FARADAY
1159 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1160 #endif
1161 rc = ehci_common_init(ctrl, tweaks);
1162 if (rc)
1163 return rc;
1164
1165 ctrl->rootdev = 0;
1166 done:
1167 *controller = &ehcic[index];
1168 return 0;
1169 }
1170 #endif
1171
1172 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1173 void *buffer, int length)
1174 {
1175
1176 if (usb_pipetype(pipe) != PIPE_BULK) {
1177 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1178 return -1;
1179 }
1180 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1181 }
1182
1183 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1184 void *buffer, int length,
1185 struct devrequest *setup)
1186 {
1187 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1188
1189 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1190 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1191 return -1;
1192 }
1193
1194 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1195 if (!ctrl->rootdev)
1196 dev->speed = USB_SPEED_HIGH;
1197 return ehci_submit_root(dev, pipe, buffer, length, setup);
1198 }
1199 return ehci_submit_async(dev, pipe, buffer, length, setup);
1200 }
1201
1202 struct int_queue {
1203 int elementsize;
1204 unsigned long pipe;
1205 struct QH *first;
1206 struct QH *current;
1207 struct QH *last;
1208 struct qTD *tds;
1209 };
1210
1211 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1212
1213 static int
1214 enable_periodic(struct ehci_ctrl *ctrl)
1215 {
1216 uint32_t cmd;
1217 struct ehci_hcor *hcor = ctrl->hcor;
1218 int ret;
1219
1220 cmd = ehci_readl(&hcor->or_usbcmd);
1221 cmd |= CMD_PSE;
1222 ehci_writel(&hcor->or_usbcmd, cmd);
1223
1224 ret = handshake((uint32_t *)&hcor->or_usbsts,
1225 STS_PSS, STS_PSS, 100 * 1000);
1226 if (ret < 0) {
1227 printf("EHCI failed: timeout when enabling periodic list\n");
1228 return -ETIMEDOUT;
1229 }
1230 udelay(1000);
1231 return 0;
1232 }
1233
1234 static int
1235 disable_periodic(struct ehci_ctrl *ctrl)
1236 {
1237 uint32_t cmd;
1238 struct ehci_hcor *hcor = ctrl->hcor;
1239 int ret;
1240
1241 cmd = ehci_readl(&hcor->or_usbcmd);
1242 cmd &= ~CMD_PSE;
1243 ehci_writel(&hcor->or_usbcmd, cmd);
1244
1245 ret = handshake((uint32_t *)&hcor->or_usbsts,
1246 STS_PSS, 0, 100 * 1000);
1247 if (ret < 0) {
1248 printf("EHCI failed: timeout when disabling periodic list\n");
1249 return -ETIMEDOUT;
1250 }
1251 return 0;
1252 }
1253
1254 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1255 unsigned long pipe, int queuesize, int elementsize,
1256 void *buffer, int interval)
1257 {
1258 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1259 struct int_queue *result = NULL;
1260 uint32_t i, toggle;
1261
1262 /*
1263 * Interrupt transfers requiring several transactions are not supported
1264 * because bInterval is ignored.
1265 *
1266 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1267 * <= PKT_ALIGN if several qTDs are required, while the USB
1268 * specification does not constrain this for interrupt transfers. That
1269 * means that ehci_submit_async() would support interrupt transfers
1270 * requiring several transactions only as long as the transfer size does
1271 * not require more than a single qTD.
1272 */
1273 if (elementsize > usb_maxpacket(dev, pipe)) {
1274 printf("%s: xfers requiring several transactions are not supported.\n",
1275 __func__);
1276 return NULL;
1277 }
1278
1279 debug("Enter create_int_queue\n");
1280 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1281 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1282 return NULL;
1283 }
1284
1285 /* limit to 4 full pages worth of data -
1286 * we can safely fit them in a single TD,
1287 * no matter the alignment
1288 */
1289 if (elementsize >= 16384) {
1290 debug("too large elements for interrupt transfers\n");
1291 return NULL;
1292 }
1293
1294 result = malloc(sizeof(*result));
1295 if (!result) {
1296 debug("ehci intr queue: out of memory\n");
1297 goto fail1;
1298 }
1299 result->elementsize = elementsize;
1300 result->pipe = pipe;
1301 result->first = memalign(USB_DMA_MINALIGN,
1302 sizeof(struct QH) * queuesize);
1303 if (!result->first) {
1304 debug("ehci intr queue: out of memory\n");
1305 goto fail2;
1306 }
1307 result->current = result->first;
1308 result->last = result->first + queuesize - 1;
1309 result->tds = memalign(USB_DMA_MINALIGN,
1310 sizeof(struct qTD) * queuesize);
1311 if (!result->tds) {
1312 debug("ehci intr queue: out of memory\n");
1313 goto fail3;
1314 }
1315 memset(result->first, 0, sizeof(struct QH) * queuesize);
1316 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1317
1318 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1319
1320 for (i = 0; i < queuesize; i++) {
1321 struct QH *qh = result->first + i;
1322 struct qTD *td = result->tds + i;
1323 void **buf = &qh->buffer;
1324
1325 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1326 if (i == queuesize - 1)
1327 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1328
1329 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1330 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1331 qh->qh_endpt1 =
1332 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1333 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1334 (1 << 14) |
1335 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1336 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1337 (usb_pipedevice(pipe) << 0));
1338 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1339 (1 << 0)); /* S-mask: microframe 0 */
1340 if (dev->speed == USB_SPEED_LOW ||
1341 dev->speed == USB_SPEED_FULL) {
1342 /* C-mask: microframes 2-4 */
1343 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1344 }
1345 ehci_update_endpt2_dev_n_port(dev, qh);
1346
1347 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1348 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1349 debug("communication direction is '%s'\n",
1350 usb_pipein(pipe) ? "in" : "out");
1351 td->qt_token = cpu_to_hc32(
1352 QT_TOKEN_DT(toggle) |
1353 (elementsize << 16) |
1354 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1355 0x80); /* active */
1356 td->qt_buffer[0] =
1357 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1358 td->qt_buffer[1] =
1359 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1360 td->qt_buffer[2] =
1361 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1362 td->qt_buffer[3] =
1363 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1364 td->qt_buffer[4] =
1365 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1366
1367 *buf = buffer + i * elementsize;
1368 toggle ^= 1;
1369 }
1370
1371 flush_dcache_range((unsigned long)buffer,
1372 ALIGN_END_ADDR(char, buffer,
1373 queuesize * elementsize));
1374 flush_dcache_range((unsigned long)result->first,
1375 ALIGN_END_ADDR(struct QH, result->first,
1376 queuesize));
1377 flush_dcache_range((unsigned long)result->tds,
1378 ALIGN_END_ADDR(struct qTD, result->tds,
1379 queuesize));
1380
1381 if (ctrl->periodic_schedules > 0) {
1382 if (disable_periodic(ctrl) < 0) {
1383 debug("FATAL: periodic should never fail, but did");
1384 goto fail3;
1385 }
1386 }
1387
1388 /* hook up to periodic list */
1389 struct QH *list = &ctrl->periodic_queue;
1390 result->last->qh_link = list->qh_link;
1391 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1392
1393 flush_dcache_range((unsigned long)result->last,
1394 ALIGN_END_ADDR(struct QH, result->last, 1));
1395 flush_dcache_range((unsigned long)list,
1396 ALIGN_END_ADDR(struct QH, list, 1));
1397
1398 if (enable_periodic(ctrl) < 0) {
1399 debug("FATAL: periodic should never fail, but did");
1400 goto fail3;
1401 }
1402 ctrl->periodic_schedules++;
1403
1404 debug("Exit create_int_queue\n");
1405 return result;
1406 fail3:
1407 if (result->tds)
1408 free(result->tds);
1409 fail2:
1410 if (result->first)
1411 free(result->first);
1412 if (result)
1413 free(result);
1414 fail1:
1415 return NULL;
1416 }
1417
1418 static void *_ehci_poll_int_queue(struct usb_device *dev,
1419 struct int_queue *queue)
1420 {
1421 struct QH *cur = queue->current;
1422 struct qTD *cur_td;
1423 uint32_t token, toggle;
1424 unsigned long pipe = queue->pipe;
1425
1426 /* depleted queue */
1427 if (cur == NULL) {
1428 debug("Exit poll_int_queue with completed queue\n");
1429 return NULL;
1430 }
1431 /* still active */
1432 cur_td = &queue->tds[queue->current - queue->first];
1433 invalidate_dcache_range((unsigned long)cur_td,
1434 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1435 token = hc32_to_cpu(cur_td->qt_token);
1436 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1437 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1438 return NULL;
1439 }
1440
1441 toggle = QT_TOKEN_GET_DT(token);
1442 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1443
1444 if (!(cur->qh_link & QH_LINK_TERMINATE))
1445 queue->current++;
1446 else
1447 queue->current = NULL;
1448
1449 invalidate_dcache_range((unsigned long)cur->buffer,
1450 ALIGN_END_ADDR(char, cur->buffer,
1451 queue->elementsize));
1452
1453 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1454 token, cur, queue->first);
1455 return cur->buffer;
1456 }
1457
1458 /* Do not free buffers associated with QHs, they're owned by someone else */
1459 static int _ehci_destroy_int_queue(struct usb_device *dev,
1460 struct int_queue *queue)
1461 {
1462 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1463 int result = -1;
1464 unsigned long timeout;
1465
1466 if (disable_periodic(ctrl) < 0) {
1467 debug("FATAL: periodic should never fail, but did");
1468 goto out;
1469 }
1470 ctrl->periodic_schedules--;
1471
1472 struct QH *cur = &ctrl->periodic_queue;
1473 timeout = get_timer(0) + 500; /* abort after 500ms */
1474 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1475 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1476 if (NEXT_QH(cur) == queue->first) {
1477 debug("found candidate. removing from chain\n");
1478 cur->qh_link = queue->last->qh_link;
1479 flush_dcache_range((unsigned long)cur,
1480 ALIGN_END_ADDR(struct QH, cur, 1));
1481 result = 0;
1482 break;
1483 }
1484 cur = NEXT_QH(cur);
1485 if (get_timer(0) > timeout) {
1486 printf("Timeout destroying interrupt endpoint queue\n");
1487 result = -1;
1488 goto out;
1489 }
1490 }
1491
1492 if (ctrl->periodic_schedules > 0) {
1493 result = enable_periodic(ctrl);
1494 if (result < 0)
1495 debug("FATAL: periodic should never fail, but did");
1496 }
1497
1498 out:
1499 free(queue->tds);
1500 free(queue->first);
1501 free(queue);
1502
1503 return result;
1504 }
1505
1506 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1507 void *buffer, int length, int interval)
1508 {
1509 void *backbuffer;
1510 struct int_queue *queue;
1511 unsigned long timeout;
1512 int result = 0, ret;
1513
1514 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1515 dev, pipe, buffer, length, interval);
1516
1517 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1518 if (!queue)
1519 return -1;
1520
1521 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1522 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1523 if (get_timer(0) > timeout) {
1524 printf("Timeout poll on interrupt endpoint\n");
1525 result = -ETIMEDOUT;
1526 break;
1527 }
1528
1529 if (backbuffer != buffer) {
1530 debug("got wrong buffer back (%p instead of %p)\n",
1531 backbuffer, buffer);
1532 return -EINVAL;
1533 }
1534
1535 ret = _ehci_destroy_int_queue(dev, queue);
1536 if (ret < 0)
1537 return ret;
1538
1539 /* everything worked out fine */
1540 return result;
1541 }
1542
1543 #ifndef CONFIG_DM_USB
1544 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1545 void *buffer, int length)
1546 {
1547 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1548 }
1549
1550 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1551 int length, struct devrequest *setup)
1552 {
1553 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1554 }
1555
1556 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1557 void *buffer, int length, int interval)
1558 {
1559 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
1560 }
1561
1562 struct int_queue *create_int_queue(struct usb_device *dev,
1563 unsigned long pipe, int queuesize, int elementsize,
1564 void *buffer, int interval)
1565 {
1566 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1567 buffer, interval);
1568 }
1569
1570 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1571 {
1572 return _ehci_poll_int_queue(dev, queue);
1573 }
1574
1575 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1576 {
1577 return _ehci_destroy_int_queue(dev, queue);
1578 }
1579 #endif
1580
1581 #ifdef CONFIG_DM_USB
1582 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1583 unsigned long pipe, void *buffer, int length,
1584 struct devrequest *setup)
1585 {
1586 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1587 dev->name, udev, udev->dev->name, udev->portnr);
1588
1589 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1590 }
1591
1592 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1593 unsigned long pipe, void *buffer, int length)
1594 {
1595 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1596 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1597 }
1598
1599 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1600 unsigned long pipe, void *buffer, int length,
1601 int interval)
1602 {
1603 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1604 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
1605 }
1606
1607 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1608 struct usb_device *udev, unsigned long pipe, int queuesize,
1609 int elementsize, void *buffer, int interval)
1610 {
1611 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1612 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1613 buffer, interval);
1614 }
1615
1616 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1617 struct int_queue *queue)
1618 {
1619 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1620 return _ehci_poll_int_queue(udev, queue);
1621 }
1622
1623 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1624 struct int_queue *queue)
1625 {
1626 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1627 return _ehci_destroy_int_queue(udev, queue);
1628 }
1629
1630 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1631 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1632 uint tweaks, enum usb_init_type init)
1633 {
1634 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1635 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1636 int ret;
1637
1638 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1639 dev->name, ctrl, hccr, hcor, init);
1640
1641 priv->desc_before_addr = true;
1642
1643 ehci_setup_ops(ctrl, ops);
1644 ctrl->hccr = hccr;
1645 ctrl->hcor = hcor;
1646 ctrl->priv = ctrl;
1647
1648 if (init == USB_INIT_DEVICE)
1649 goto done;
1650 ret = ehci_reset(ctrl);
1651 if (ret)
1652 goto err;
1653
1654 ret = ehci_common_init(ctrl, tweaks);
1655 if (ret)
1656 goto err;
1657 done:
1658 return 0;
1659 err:
1660 free(ctrl);
1661 debug("%s: failed, ret=%d\n", __func__, ret);
1662 return ret;
1663 }
1664
1665 int ehci_deregister(struct udevice *dev)
1666 {
1667 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1668
1669 ehci_shutdown(ctrl);
1670
1671 return 0;
1672 }
1673
1674 struct dm_usb_ops ehci_usb_ops = {
1675 .control = ehci_submit_control_msg,
1676 .bulk = ehci_submit_bulk_msg,
1677 .interrupt = ehci_submit_int_msg,
1678 .create_int_queue = ehci_create_int_queue,
1679 .poll_int_queue = ehci_poll_int_queue,
1680 .destroy_int_queue = ehci_destroy_int_queue,
1681 };
1682
1683 #endif
"Das U-Boot" Source Tree