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dm: usb: Add driver model support to EHCI
[people/ms/u-boot.git] / drivers / usb / host / ehci-hcd.c
1 /*-
2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
5 *
6 * All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
11 * the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23 #include <common.h>
24 #include <dm.h>
25 #include <errno.h>
26 #include <asm/byteorder.h>
27 #include <asm/unaligned.h>
28 #include <usb.h>
29 #include <asm/io.h>
30 #include <malloc.h>
31 #include <watchdog.h>
32 #include <linux/compiler.h>
33
34 #include "ehci.h"
35
36 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
37 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
38 #endif
39
40 /*
41 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
42 * Let's time out after 8 to have a little safety margin on top of that.
43 */
44 #define HCHALT_TIMEOUT (8 * 1000)
45
46 #ifndef CONFIG_DM_USB
47 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
48 #endif
49
50 #define ALIGN_END_ADDR(type, ptr, size) \
51 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
52
53 static struct descriptor {
54 struct usb_hub_descriptor hub;
55 struct usb_device_descriptor device;
56 struct usb_linux_config_descriptor config;
57 struct usb_linux_interface_descriptor interface;
58 struct usb_endpoint_descriptor endpoint;
59 } __attribute__ ((packed)) descriptor = {
60 {
61 0x8, /* bDescLength */
62 0x29, /* bDescriptorType: hub descriptor */
63 2, /* bNrPorts -- runtime modified */
64 0, /* wHubCharacteristics */
65 10, /* bPwrOn2PwrGood */
66 0, /* bHubCntrCurrent */
67 {}, /* Device removable */
68 {} /* at most 7 ports! XXX */
69 },
70 {
71 0x12, /* bLength */
72 1, /* bDescriptorType: UDESC_DEVICE */
73 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
74 9, /* bDeviceClass: UDCLASS_HUB */
75 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
76 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
77 64, /* bMaxPacketSize: 64 bytes */
78 0x0000, /* idVendor */
79 0x0000, /* idProduct */
80 cpu_to_le16(0x0100), /* bcdDevice */
81 1, /* iManufacturer */
82 2, /* iProduct */
83 0, /* iSerialNumber */
84 1 /* bNumConfigurations: 1 */
85 },
86 {
87 0x9,
88 2, /* bDescriptorType: UDESC_CONFIG */
89 cpu_to_le16(0x19),
90 1, /* bNumInterface */
91 1, /* bConfigurationValue */
92 0, /* iConfiguration */
93 0x40, /* bmAttributes: UC_SELF_POWER */
94 0 /* bMaxPower */
95 },
96 {
97 0x9, /* bLength */
98 4, /* bDescriptorType: UDESC_INTERFACE */
99 0, /* bInterfaceNumber */
100 0, /* bAlternateSetting */
101 1, /* bNumEndpoints */
102 9, /* bInterfaceClass: UICLASS_HUB */
103 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
104 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
105 0 /* iInterface */
106 },
107 {
108 0x7, /* bLength */
109 5, /* bDescriptorType: UDESC_ENDPOINT */
110 0x81, /* bEndpointAddress:
111 * UE_DIR_IN | EHCI_INTR_ENDPT
112 */
113 3, /* bmAttributes: UE_INTERRUPT */
114 8, /* wMaxPacketSize */
115 255 /* bInterval */
116 },
117 };
118
119 #if defined(CONFIG_EHCI_IS_TDI)
120 #define ehci_is_TDI() (1)
121 #else
122 #define ehci_is_TDI() (0)
123 #endif
124
125 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
126 {
127 #ifdef CONFIG_DM_USB
128 struct udevice *dev;
129
130 /* Find the USB controller */
131 for (dev = udev->dev;
132 device_get_uclass_id(dev) != UCLASS_USB;
133 dev = dev->parent)
134 ;
135 return dev_get_priv(dev);
136 #else
137 return udev->controller;
138 #endif
139 }
140
141 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
142 {
143 return PORTSC_PSPD(reg);
144 }
145
146 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
147 {
148 uint32_t tmp;
149 uint32_t *reg_ptr;
150
151 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
152 tmp = ehci_readl(reg_ptr);
153 tmp |= USBMODE_CM_HC;
154 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
155 tmp |= USBMODE_BE;
156 #endif
157 ehci_writel(reg_ptr, tmp);
158 }
159
160 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
161 uint32_t *reg)
162 {
163 mdelay(50);
164 }
165
166 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
167 {
168 if (port < 0 || port >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
169 /* Printing the message would cause a scan failure! */
170 debug("The request port(%u) is not configured\n", port);
171 return NULL;
172 }
173
174 return (uint32_t *)&ctrl->hcor->or_portsc[port];
175 }
176
177 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
178 {
179 uint32_t result;
180 do {
181 result = ehci_readl(ptr);
182 udelay(5);
183 if (result == ~(uint32_t)0)
184 return -1;
185 result &= mask;
186 if (result == done)
187 return 0;
188 usec--;
189 } while (usec > 0);
190 return -1;
191 }
192
193 static int ehci_reset(struct ehci_ctrl *ctrl)
194 {
195 uint32_t cmd;
196 int ret = 0;
197
198 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
199 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
200 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
201 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
202 CMD_RESET, 0, 250 * 1000);
203 if (ret < 0) {
204 printf("EHCI fail to reset\n");
205 goto out;
206 }
207
208 if (ehci_is_TDI())
209 ctrl->ops.set_usb_mode(ctrl);
210
211 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
212 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
213 cmd &= ~TXFIFO_THRESH_MASK;
214 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
215 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
216 #endif
217 out:
218 return ret;
219 }
220
221 static int ehci_shutdown(struct ehci_ctrl *ctrl)
222 {
223 int i, ret = 0;
224 uint32_t cmd, reg;
225
226 if (!ctrl || !ctrl->hcor)
227 return -EINVAL;
228
229 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
230 cmd &= ~(CMD_PSE | CMD_ASE);
231 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
232 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
233 100 * 1000);
234
235 if (!ret) {
236 for (i = 0; i < CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS; i++) {
237 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
238 reg |= EHCI_PS_SUSP;
239 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
240 }
241
242 cmd &= ~CMD_RUN;
243 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
244 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
245 HCHALT_TIMEOUT);
246 }
247
248 if (ret)
249 puts("EHCI failed to shut down host controller.\n");
250
251 return ret;
252 }
253
254 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
255 {
256 uint32_t delta, next;
257 uint32_t addr = (unsigned long)buf;
258 int idx;
259
260 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
261 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
262
263 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
264
265 idx = 0;
266 while (idx < QT_BUFFER_CNT) {
267 td->qt_buffer[idx] = cpu_to_hc32(addr);
268 td->qt_buffer_hi[idx] = 0;
269 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
270 delta = next - addr;
271 if (delta >= sz)
272 break;
273 sz -= delta;
274 addr = next;
275 idx++;
276 }
277
278 if (idx == QT_BUFFER_CNT) {
279 printf("out of buffer pointers (%zu bytes left)\n", sz);
280 return -1;
281 }
282
283 return 0;
284 }
285
286 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
287 {
288 #define QH_HIGH_SPEED 2
289 #define QH_FULL_SPEED 0
290 #define QH_LOW_SPEED 1
291 if (speed == USB_SPEED_HIGH)
292 return QH_HIGH_SPEED;
293 if (speed == USB_SPEED_LOW)
294 return QH_LOW_SPEED;
295 return QH_FULL_SPEED;
296 }
297
298 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
299 struct QH *qh)
300 {
301 struct usb_device *ttdev;
302 int parent_devnum;
303
304 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
305 return;
306
307 /*
308 * For full / low speed devices we need to get the devnum and portnr of
309 * the tt, so of the first upstream usb-2 hub, there may be usb-1 hubs
310 * in the tree before that one!
311 */
312 #ifdef CONFIG_DM_USB
313 struct udevice *parent;
314
315 for (ttdev = udev; ; ) {
316 struct udevice *dev = ttdev->dev;
317
318 if (dev->parent &&
319 device_get_uclass_id(dev->parent) == UCLASS_USB_HUB)
320 parent = dev->parent;
321 else
322 parent = NULL;
323 if (!parent)
324 return;
325 ttdev = dev_get_parentdata(parent);
326 if (!ttdev->speed != USB_SPEED_HIGH)
327 break;
328 }
329 parent_devnum = ttdev->devnum;
330 #else
331 ttdev = udev;
332 while (ttdev->parent && ttdev->parent->speed != USB_SPEED_HIGH)
333 ttdev = ttdev->parent;
334 if (!ttdev->parent)
335 return;
336 parent_devnum = ttdev->parent->devnum;
337 #endif
338
339 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(ttdev->portnr) |
340 QH_ENDPT2_HUBADDR(parent_devnum));
341 }
342
343 static int
344 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
345 int length, struct devrequest *req)
346 {
347 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
348 struct qTD *qtd;
349 int qtd_count = 0;
350 int qtd_counter = 0;
351 volatile struct qTD *vtd;
352 unsigned long ts;
353 uint32_t *tdp;
354 uint32_t endpt, maxpacket, token, usbsts;
355 uint32_t c, toggle;
356 uint32_t cmd;
357 int timeout;
358 int ret = 0;
359 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
360
361 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
362 buffer, length, req);
363 if (req != NULL)
364 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
365 req->request, req->request,
366 req->requesttype, req->requesttype,
367 le16_to_cpu(req->value), le16_to_cpu(req->value),
368 le16_to_cpu(req->index));
369
370 #define PKT_ALIGN 512
371 /*
372 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
373 * described by a transfer descriptor (the qTD). The qTDs form a linked
374 * list with a queue head (QH).
375 *
376 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
377 * have its beginning in a qTD transfer and its end in the following
378 * one, so the qTD transfer lengths have to be chosen accordingly.
379 *
380 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
381 * single pages. The first data buffer can start at any offset within a
382 * page (not considering the cache-line alignment issues), while the
383 * following buffers must be page-aligned. There is no alignment
384 * constraint on the size of a qTD transfer.
385 */
386 if (req != NULL)
387 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
388 qtd_count += 1 + 1;
389 if (length > 0 || req == NULL) {
390 /*
391 * Determine the qTD transfer size that will be used for the
392 * data payload (not considering the first qTD transfer, which
393 * may be longer or shorter, and the final one, which may be
394 * shorter).
395 *
396 * In order to keep each packet within a qTD transfer, the qTD
397 * transfer size is aligned to PKT_ALIGN, which is a multiple of
398 * wMaxPacketSize (except in some cases for interrupt transfers,
399 * see comment in submit_int_msg()).
400 *
401 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
402 * QT_BUFFER_CNT full pages will be used.
403 */
404 int xfr_sz = QT_BUFFER_CNT;
405 /*
406 * However, if the input buffer is not aligned to PKT_ALIGN, the
407 * qTD transfer size will be one page shorter, and the first qTD
408 * data buffer of each transfer will be page-unaligned.
409 */
410 if ((unsigned long)buffer & (PKT_ALIGN - 1))
411 xfr_sz--;
412 /* Convert the qTD transfer size to bytes. */
413 xfr_sz *= EHCI_PAGE_SIZE;
414 /*
415 * Approximate by excess the number of qTDs that will be
416 * required for the data payload. The exact formula is way more
417 * complicated and saves at most 2 qTDs, i.e. a total of 128
418 * bytes.
419 */
420 qtd_count += 2 + length / xfr_sz;
421 }
422 /*
423 * Threshold value based on the worst-case total size of the allocated qTDs for
424 * a mass-storage transfer of 65535 blocks of 512 bytes.
425 */
426 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
427 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
428 #endif
429 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
430 if (qtd == NULL) {
431 printf("unable to allocate TDs\n");
432 return -1;
433 }
434
435 memset(qh, 0, sizeof(struct QH));
436 memset(qtd, 0, qtd_count * sizeof(*qtd));
437
438 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
439
440 /*
441 * Setup QH (3.6 in ehci-r10.pdf)
442 *
443 * qh_link ................. 03-00 H
444 * qh_endpt1 ............... 07-04 H
445 * qh_endpt2 ............... 0B-08 H
446 * - qh_curtd
447 * qh_overlay.qt_next ...... 13-10 H
448 * - qh_overlay.qt_altnext
449 */
450 qh->qh_link = cpu_to_hc32((unsigned long)&ctrl->qh_list | QH_LINK_TYPE_QH);
451 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
452 maxpacket = usb_maxpacket(dev, pipe);
453 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
454 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
455 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
456 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
457 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
458 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
459 qh->qh_endpt1 = cpu_to_hc32(endpt);
460 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
461 qh->qh_endpt2 = cpu_to_hc32(endpt);
462 ehci_update_endpt2_dev_n_port(dev, qh);
463 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
464 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
465
466 tdp = &qh->qh_overlay.qt_next;
467
468 if (req != NULL) {
469 /*
470 * Setup request qTD (3.5 in ehci-r10.pdf)
471 *
472 * qt_next ................ 03-00 H
473 * qt_altnext ............. 07-04 H
474 * qt_token ............... 0B-08 H
475 *
476 * [ buffer, buffer_hi ] loaded with "req".
477 */
478 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
479 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
480 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
481 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
482 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
483 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
484 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
485 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
486 printf("unable to construct SETUP TD\n");
487 goto fail;
488 }
489 /* Update previous qTD! */
490 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
491 tdp = &qtd[qtd_counter++].qt_next;
492 toggle = 1;
493 }
494
495 if (length > 0 || req == NULL) {
496 uint8_t *buf_ptr = buffer;
497 int left_length = length;
498
499 do {
500 /*
501 * Determine the size of this qTD transfer. By default,
502 * QT_BUFFER_CNT full pages can be used.
503 */
504 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
505 /*
506 * However, if the input buffer is not page-aligned, the
507 * portion of the first page before the buffer start
508 * offset within that page is unusable.
509 */
510 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
511 /*
512 * In order to keep each packet within a qTD transfer,
513 * align the qTD transfer size to PKT_ALIGN.
514 */
515 xfr_bytes &= ~(PKT_ALIGN - 1);
516 /*
517 * This transfer may be shorter than the available qTD
518 * transfer size that has just been computed.
519 */
520 xfr_bytes = min(xfr_bytes, left_length);
521
522 /*
523 * Setup request qTD (3.5 in ehci-r10.pdf)
524 *
525 * qt_next ................ 03-00 H
526 * qt_altnext ............. 07-04 H
527 * qt_token ............... 0B-08 H
528 *
529 * [ buffer, buffer_hi ] loaded with "buffer".
530 */
531 qtd[qtd_counter].qt_next =
532 cpu_to_hc32(QT_NEXT_TERMINATE);
533 qtd[qtd_counter].qt_altnext =
534 cpu_to_hc32(QT_NEXT_TERMINATE);
535 token = QT_TOKEN_DT(toggle) |
536 QT_TOKEN_TOTALBYTES(xfr_bytes) |
537 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
538 QT_TOKEN_CERR(3) |
539 QT_TOKEN_PID(usb_pipein(pipe) ?
540 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
541 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
542 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
543 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
544 xfr_bytes)) {
545 printf("unable to construct DATA TD\n");
546 goto fail;
547 }
548 /* Update previous qTD! */
549 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
550 tdp = &qtd[qtd_counter++].qt_next;
551 /*
552 * Data toggle has to be adjusted since the qTD transfer
553 * size is not always an even multiple of
554 * wMaxPacketSize.
555 */
556 if ((xfr_bytes / maxpacket) & 1)
557 toggle ^= 1;
558 buf_ptr += xfr_bytes;
559 left_length -= xfr_bytes;
560 } while (left_length > 0);
561 }
562
563 if (req != NULL) {
564 /*
565 * Setup request qTD (3.5 in ehci-r10.pdf)
566 *
567 * qt_next ................ 03-00 H
568 * qt_altnext ............. 07-04 H
569 * qt_token ............... 0B-08 H
570 */
571 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
572 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
573 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
574 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
575 QT_TOKEN_PID(usb_pipein(pipe) ?
576 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
577 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
578 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
579 /* Update previous qTD! */
580 *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
581 tdp = &qtd[qtd_counter++].qt_next;
582 }
583
584 ctrl->qh_list.qh_link = cpu_to_hc32((unsigned long)qh | QH_LINK_TYPE_QH);
585
586 /* Flush dcache */
587 flush_dcache_range((unsigned long)&ctrl->qh_list,
588 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
589 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
590 flush_dcache_range((unsigned long)qtd,
591 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
592
593 /* Set async. queue head pointer. */
594 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)&ctrl->qh_list);
595
596 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
597 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
598
599 /* Enable async. schedule. */
600 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
601 cmd |= CMD_ASE;
602 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
603
604 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
605 100 * 1000);
606 if (ret < 0) {
607 printf("EHCI fail timeout STS_ASS set\n");
608 goto fail;
609 }
610
611 /* Wait for TDs to be processed. */
612 ts = get_timer(0);
613 vtd = &qtd[qtd_counter - 1];
614 timeout = USB_TIMEOUT_MS(pipe);
615 do {
616 /* Invalidate dcache */
617 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
618 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
619 invalidate_dcache_range((unsigned long)qh,
620 ALIGN_END_ADDR(struct QH, qh, 1));
621 invalidate_dcache_range((unsigned long)qtd,
622 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
623
624 token = hc32_to_cpu(vtd->qt_token);
625 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
626 break;
627 WATCHDOG_RESET();
628 } while (get_timer(ts) < timeout);
629
630 /*
631 * Invalidate the memory area occupied by buffer
632 * Don't try to fix the buffer alignment, if it isn't properly
633 * aligned it's upper layer's fault so let invalidate_dcache_range()
634 * vow about it. But we have to fix the length as it's actual
635 * transfer length and can be unaligned. This is potentially
636 * dangerous operation, it's responsibility of the calling
637 * code to make sure enough space is reserved.
638 */
639 invalidate_dcache_range((unsigned long)buffer,
640 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
641
642 /* Check that the TD processing happened */
643 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
644 printf("EHCI timed out on TD - token=%#x\n", token);
645
646 /* Disable async schedule. */
647 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
648 cmd &= ~CMD_ASE;
649 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
650
651 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
652 100 * 1000);
653 if (ret < 0) {
654 printf("EHCI fail timeout STS_ASS reset\n");
655 goto fail;
656 }
657
658 token = hc32_to_cpu(qh->qh_overlay.qt_token);
659 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
660 debug("TOKEN=%#x\n", token);
661 switch (QT_TOKEN_GET_STATUS(token) &
662 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
663 case 0:
664 toggle = QT_TOKEN_GET_DT(token);
665 usb_settoggle(dev, usb_pipeendpoint(pipe),
666 usb_pipeout(pipe), toggle);
667 dev->status = 0;
668 break;
669 case QT_TOKEN_STATUS_HALTED:
670 dev->status = USB_ST_STALLED;
671 break;
672 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
673 case QT_TOKEN_STATUS_DATBUFERR:
674 dev->status = USB_ST_BUF_ERR;
675 break;
676 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
677 case QT_TOKEN_STATUS_BABBLEDET:
678 dev->status = USB_ST_BABBLE_DET;
679 break;
680 default:
681 dev->status = USB_ST_CRC_ERR;
682 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
683 dev->status |= USB_ST_STALLED;
684 break;
685 }
686 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
687 } else {
688 dev->act_len = 0;
689 #ifndef CONFIG_USB_EHCI_FARADAY
690 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
691 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
692 ehci_readl(&ctrl->hcor->or_portsc[0]),
693 ehci_readl(&ctrl->hcor->or_portsc[1]));
694 #endif
695 }
696
697 free(qtd);
698 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
699
700 fail:
701 free(qtd);
702 return -1;
703 }
704
705 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
706 void *buffer, int length, struct devrequest *req)
707 {
708 uint8_t tmpbuf[4];
709 u16 typeReq;
710 void *srcptr = NULL;
711 int len, srclen;
712 uint32_t reg;
713 uint32_t *status_reg;
714 int port = le16_to_cpu(req->index) & 0xff;
715 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
716
717 srclen = 0;
718
719 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
720 req->request, req->request,
721 req->requesttype, req->requesttype,
722 le16_to_cpu(req->value), le16_to_cpu(req->index));
723
724 typeReq = req->request | req->requesttype << 8;
725
726 switch (typeReq) {
727 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
728 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
729 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
730 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
731 if (!status_reg)
732 return -1;
733 break;
734 default:
735 status_reg = NULL;
736 break;
737 }
738
739 switch (typeReq) {
740 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
741 switch (le16_to_cpu(req->value) >> 8) {
742 case USB_DT_DEVICE:
743 debug("USB_DT_DEVICE request\n");
744 srcptr = &descriptor.device;
745 srclen = descriptor.device.bLength;
746 break;
747 case USB_DT_CONFIG:
748 debug("USB_DT_CONFIG config\n");
749 srcptr = &descriptor.config;
750 srclen = descriptor.config.bLength +
751 descriptor.interface.bLength +
752 descriptor.endpoint.bLength;
753 break;
754 case USB_DT_STRING:
755 debug("USB_DT_STRING config\n");
756 switch (le16_to_cpu(req->value) & 0xff) {
757 case 0: /* Language */
758 srcptr = "\4\3\1\0";
759 srclen = 4;
760 break;
761 case 1: /* Vendor */
762 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
763 srclen = 14;
764 break;
765 case 2: /* Product */
766 srcptr = "\52\3E\0H\0C\0I\0 "
767 "\0H\0o\0s\0t\0 "
768 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
769 srclen = 42;
770 break;
771 default:
772 debug("unknown value DT_STRING %x\n",
773 le16_to_cpu(req->value));
774 goto unknown;
775 }
776 break;
777 default:
778 debug("unknown value %x\n", le16_to_cpu(req->value));
779 goto unknown;
780 }
781 break;
782 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
783 switch (le16_to_cpu(req->value) >> 8) {
784 case USB_DT_HUB:
785 debug("USB_DT_HUB config\n");
786 srcptr = &descriptor.hub;
787 srclen = descriptor.hub.bLength;
788 break;
789 default:
790 debug("unknown value %x\n", le16_to_cpu(req->value));
791 goto unknown;
792 }
793 break;
794 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
795 debug("USB_REQ_SET_ADDRESS\n");
796 ctrl->rootdev = le16_to_cpu(req->value);
797 break;
798 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
799 debug("USB_REQ_SET_CONFIGURATION\n");
800 /* Nothing to do */
801 break;
802 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
803 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
804 tmpbuf[1] = 0;
805 srcptr = tmpbuf;
806 srclen = 2;
807 break;
808 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
809 memset(tmpbuf, 0, 4);
810 reg = ehci_readl(status_reg);
811 if (reg & EHCI_PS_CS)
812 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
813 if (reg & EHCI_PS_PE)
814 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
815 if (reg & EHCI_PS_SUSP)
816 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
817 if (reg & EHCI_PS_OCA)
818 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
819 if (reg & EHCI_PS_PR)
820 tmpbuf[0] |= USB_PORT_STAT_RESET;
821 if (reg & EHCI_PS_PP)
822 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
823
824 if (ehci_is_TDI()) {
825 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
826 case PORTSC_PSPD_FS:
827 break;
828 case PORTSC_PSPD_LS:
829 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
830 break;
831 case PORTSC_PSPD_HS:
832 default:
833 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
834 break;
835 }
836 } else {
837 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
838 }
839
840 if (reg & EHCI_PS_CSC)
841 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
842 if (reg & EHCI_PS_PEC)
843 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
844 if (reg & EHCI_PS_OCC)
845 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
846 if (ctrl->portreset & (1 << port))
847 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
848
849 srcptr = tmpbuf;
850 srclen = 4;
851 break;
852 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
853 reg = ehci_readl(status_reg);
854 reg &= ~EHCI_PS_CLEAR;
855 switch (le16_to_cpu(req->value)) {
856 case USB_PORT_FEAT_ENABLE:
857 reg |= EHCI_PS_PE;
858 ehci_writel(status_reg, reg);
859 break;
860 case USB_PORT_FEAT_POWER:
861 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
862 reg |= EHCI_PS_PP;
863 ehci_writel(status_reg, reg);
864 }
865 break;
866 case USB_PORT_FEAT_RESET:
867 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
868 !ehci_is_TDI() &&
869 EHCI_PS_IS_LOWSPEED(reg)) {
870 /* Low speed device, give up ownership. */
871 debug("port %d low speed --> companion\n",
872 port - 1);
873 reg |= EHCI_PS_PO;
874 ehci_writel(status_reg, reg);
875 break;
876 } else {
877 int ret;
878
879 reg |= EHCI_PS_PR;
880 reg &= ~EHCI_PS_PE;
881 ehci_writel(status_reg, reg);
882 /*
883 * caller must wait, then call GetPortStatus
884 * usb 2.0 specification say 50 ms resets on
885 * root
886 */
887 ctrl->ops.powerup_fixup(ctrl, status_reg, &reg);
888
889 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
890 /*
891 * A host controller must terminate the reset
892 * and stabilize the state of the port within
893 * 2 milliseconds
894 */
895 ret = handshake(status_reg, EHCI_PS_PR, 0,
896 2 * 1000);
897 if (!ret)
898 ctrl->portreset |= 1 << port;
899 else
900 printf("port(%d) reset error\n",
901 port - 1);
902 }
903 break;
904 case USB_PORT_FEAT_TEST:
905 ehci_shutdown(ctrl);
906 reg &= ~(0xf << 16);
907 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
908 ehci_writel(status_reg, reg);
909 break;
910 default:
911 debug("unknown feature %x\n", le16_to_cpu(req->value));
912 goto unknown;
913 }
914 /* unblock posted writes */
915 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
916 break;
917 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
918 reg = ehci_readl(status_reg);
919 reg &= ~EHCI_PS_CLEAR;
920 switch (le16_to_cpu(req->value)) {
921 case USB_PORT_FEAT_ENABLE:
922 reg &= ~EHCI_PS_PE;
923 break;
924 case USB_PORT_FEAT_C_ENABLE:
925 reg |= EHCI_PS_PE;
926 break;
927 case USB_PORT_FEAT_POWER:
928 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
929 reg &= ~EHCI_PS_PP;
930 break;
931 case USB_PORT_FEAT_C_CONNECTION:
932 reg |= EHCI_PS_CSC;
933 break;
934 case USB_PORT_FEAT_OVER_CURRENT:
935 reg |= EHCI_PS_OCC;
936 break;
937 case USB_PORT_FEAT_C_RESET:
938 ctrl->portreset &= ~(1 << port);
939 break;
940 default:
941 debug("unknown feature %x\n", le16_to_cpu(req->value));
942 goto unknown;
943 }
944 ehci_writel(status_reg, reg);
945 /* unblock posted write */
946 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
947 break;
948 default:
949 debug("Unknown request\n");
950 goto unknown;
951 }
952
953 mdelay(1);
954 len = min3(srclen, (int)le16_to_cpu(req->length), length);
955 if (srcptr != NULL && len > 0)
956 memcpy(buffer, srcptr, len);
957 else
958 debug("Len is 0\n");
959
960 dev->act_len = len;
961 dev->status = 0;
962 return 0;
963
964 unknown:
965 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
966 req->requesttype, req->request, le16_to_cpu(req->value),
967 le16_to_cpu(req->index), le16_to_cpu(req->length));
968
969 dev->act_len = 0;
970 dev->status = USB_ST_STALLED;
971 return -1;
972 }
973
974 const struct ehci_ops default_ehci_ops = {
975 .set_usb_mode = ehci_set_usbmode,
976 .get_port_speed = ehci_get_port_speed,
977 .powerup_fixup = ehci_powerup_fixup,
978 .get_portsc_register = ehci_get_portsc_register,
979 };
980
981 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
982 {
983 if (!ops) {
984 ctrl->ops = default_ehci_ops;
985 } else {
986 ctrl->ops = *ops;
987 if (!ctrl->ops.set_usb_mode)
988 ctrl->ops.set_usb_mode = ehci_set_usbmode;
989 if (!ctrl->ops.get_port_speed)
990 ctrl->ops.get_port_speed = ehci_get_port_speed;
991 if (!ctrl->ops.powerup_fixup)
992 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
993 if (!ctrl->ops.get_portsc_register)
994 ctrl->ops.get_portsc_register =
995 ehci_get_portsc_register;
996 }
997 }
998
999 #ifndef CONFIG_DM_USB
1000 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
1001 {
1002 struct ehci_ctrl *ctrl = &ehcic[index];
1003
1004 ctrl->priv = priv;
1005 ehci_setup_ops(ctrl, ops);
1006 }
1007
1008 void *ehci_get_controller_priv(int index)
1009 {
1010 return ehcic[index].priv;
1011 }
1012 #endif
1013
1014 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
1015 {
1016 struct QH *qh_list;
1017 struct QH *periodic;
1018 uint32_t reg;
1019 uint32_t cmd;
1020 int i;
1021
1022 /* Set the high address word (aka segment) for 64-bit controller */
1023 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1024 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1025
1026 qh_list = &ctrl->qh_list;
1027
1028 /* Set head of reclaim list */
1029 memset(qh_list, 0, sizeof(*qh_list));
1030 qh_list->qh_link = cpu_to_hc32((unsigned long)qh_list | QH_LINK_TYPE_QH);
1031 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1032 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1033 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1034 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1035 qh_list->qh_overlay.qt_token =
1036 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1037
1038 flush_dcache_range((unsigned long)qh_list,
1039 ALIGN_END_ADDR(struct QH, qh_list, 1));
1040
1041 /* Set async. queue head pointer. */
1042 ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)qh_list);
1043
1044 /*
1045 * Set up periodic list
1046 * Step 1: Parent QH for all periodic transfers.
1047 */
1048 ctrl->periodic_schedules = 0;
1049 periodic = &ctrl->periodic_queue;
1050 memset(periodic, 0, sizeof(*periodic));
1051 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1052 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1053 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1054
1055 flush_dcache_range((unsigned long)periodic,
1056 ALIGN_END_ADDR(struct QH, periodic, 1));
1057
1058 /*
1059 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1060 * In particular, device specifications on polling frequency
1061 * are disregarded. Keyboards seem to send NAK/NYet reliably
1062 * when polled with an empty buffer.
1063 *
1064 * Split Transactions will be spread across microframes using
1065 * S-mask and C-mask.
1066 */
1067 if (ctrl->periodic_list == NULL)
1068 ctrl->periodic_list = memalign(4096, 1024 * 4);
1069
1070 if (!ctrl->periodic_list)
1071 return -ENOMEM;
1072 for (i = 0; i < 1024; i++) {
1073 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1074 | QH_LINK_TYPE_QH);
1075 }
1076
1077 flush_dcache_range((unsigned long)ctrl->periodic_list,
1078 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1079 1024));
1080
1081 /* Set periodic list base address */
1082 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1083 (unsigned long)ctrl->periodic_list);
1084
1085 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1086 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1087 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1088 /* Port Indicators */
1089 if (HCS_INDICATOR(reg))
1090 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1091 | 0x80, &descriptor.hub.wHubCharacteristics);
1092 /* Port Power Control */
1093 if (HCS_PPC(reg))
1094 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1095 | 0x01, &descriptor.hub.wHubCharacteristics);
1096
1097 /* Start the host controller. */
1098 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1099 /*
1100 * Philips, Intel, and maybe others need CMD_RUN before the
1101 * root hub will detect new devices (why?); NEC doesn't
1102 */
1103 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1104 cmd |= CMD_RUN;
1105 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1106
1107 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1108 /* take control over the ports */
1109 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1110 cmd |= FLAG_CF;
1111 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1112 }
1113
1114 /* unblock posted write */
1115 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1116 mdelay(5);
1117 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1118 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1119
1120 return 0;
1121 }
1122
1123 #ifndef CONFIG_DM_USB
1124 int usb_lowlevel_stop(int index)
1125 {
1126 ehci_shutdown(&ehcic[index]);
1127 return ehci_hcd_stop(index);
1128 }
1129
1130 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1131 {
1132 struct ehci_ctrl *ctrl = &ehcic[index];
1133 uint tweaks = 0;
1134 int rc;
1135
1136 /**
1137 * Set ops to default_ehci_ops, ehci_hcd_init should call
1138 * ehci_set_controller_priv to change any of these function pointers.
1139 */
1140 ctrl->ops = default_ehci_ops;
1141
1142 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1143 if (rc)
1144 return rc;
1145 if (init == USB_INIT_DEVICE)
1146 goto done;
1147
1148 /* EHCI spec section 4.1 */
1149 if (ehci_reset(ctrl))
1150 return -1;
1151
1152 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1153 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1154 if (rc)
1155 return rc;
1156 #endif
1157 #ifdef CONFIG_USB_EHCI_FARADAY
1158 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1159 #endif
1160 rc = ehci_common_init(ctrl, tweaks);
1161 if (rc)
1162 return rc;
1163
1164 ctrl->rootdev = 0;
1165 done:
1166 *controller = &ehcic[index];
1167 return 0;
1168 }
1169 #endif
1170
1171 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1172 void *buffer, int length)
1173 {
1174
1175 if (usb_pipetype(pipe) != PIPE_BULK) {
1176 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1177 return -1;
1178 }
1179 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1180 }
1181
1182 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1183 void *buffer, int length,
1184 struct devrequest *setup)
1185 {
1186 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1187
1188 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1189 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1190 return -1;
1191 }
1192
1193 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1194 if (!ctrl->rootdev)
1195 dev->speed = USB_SPEED_HIGH;
1196 return ehci_submit_root(dev, pipe, buffer, length, setup);
1197 }
1198 return ehci_submit_async(dev, pipe, buffer, length, setup);
1199 }
1200
1201 struct int_queue {
1202 int elementsize;
1203 struct QH *first;
1204 struct QH *current;
1205 struct QH *last;
1206 struct qTD *tds;
1207 };
1208
1209 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1210
1211 static int
1212 enable_periodic(struct ehci_ctrl *ctrl)
1213 {
1214 uint32_t cmd;
1215 struct ehci_hcor *hcor = ctrl->hcor;
1216 int ret;
1217
1218 cmd = ehci_readl(&hcor->or_usbcmd);
1219 cmd |= CMD_PSE;
1220 ehci_writel(&hcor->or_usbcmd, cmd);
1221
1222 ret = handshake((uint32_t *)&hcor->or_usbsts,
1223 STS_PSS, STS_PSS, 100 * 1000);
1224 if (ret < 0) {
1225 printf("EHCI failed: timeout when enabling periodic list\n");
1226 return -ETIMEDOUT;
1227 }
1228 udelay(1000);
1229 return 0;
1230 }
1231
1232 static int
1233 disable_periodic(struct ehci_ctrl *ctrl)
1234 {
1235 uint32_t cmd;
1236 struct ehci_hcor *hcor = ctrl->hcor;
1237 int ret;
1238
1239 cmd = ehci_readl(&hcor->or_usbcmd);
1240 cmd &= ~CMD_PSE;
1241 ehci_writel(&hcor->or_usbcmd, cmd);
1242
1243 ret = handshake((uint32_t *)&hcor->or_usbsts,
1244 STS_PSS, 0, 100 * 1000);
1245 if (ret < 0) {
1246 printf("EHCI failed: timeout when disabling periodic list\n");
1247 return -ETIMEDOUT;
1248 }
1249 return 0;
1250 }
1251
1252 struct int_queue *
1253 create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize,
1254 int elementsize, void *buffer, int interval)
1255 {
1256 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1257 struct int_queue *result = NULL;
1258 int i;
1259
1260 /*
1261 * Interrupt transfers requiring several transactions are not supported
1262 * because bInterval is ignored.
1263 *
1264 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1265 * <= PKT_ALIGN if several qTDs are required, while the USB
1266 * specification does not constrain this for interrupt transfers. That
1267 * means that ehci_submit_async() would support interrupt transfers
1268 * requiring several transactions only as long as the transfer size does
1269 * not require more than a single qTD.
1270 */
1271 if (elementsize > usb_maxpacket(dev, pipe)) {
1272 printf("%s: xfers requiring several transactions are not supported.\n",
1273 __func__);
1274 return NULL;
1275 }
1276
1277 debug("Enter create_int_queue\n");
1278 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1279 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1280 return NULL;
1281 }
1282
1283 /* limit to 4 full pages worth of data -
1284 * we can safely fit them in a single TD,
1285 * no matter the alignment
1286 */
1287 if (elementsize >= 16384) {
1288 debug("too large elements for interrupt transfers\n");
1289 return NULL;
1290 }
1291
1292 result = malloc(sizeof(*result));
1293 if (!result) {
1294 debug("ehci intr queue: out of memory\n");
1295 goto fail1;
1296 }
1297 result->elementsize = elementsize;
1298 result->first = memalign(USB_DMA_MINALIGN,
1299 sizeof(struct QH) * queuesize);
1300 if (!result->first) {
1301 debug("ehci intr queue: out of memory\n");
1302 goto fail2;
1303 }
1304 result->current = result->first;
1305 result->last = result->first + queuesize - 1;
1306 result->tds = memalign(USB_DMA_MINALIGN,
1307 sizeof(struct qTD) * queuesize);
1308 if (!result->tds) {
1309 debug("ehci intr queue: out of memory\n");
1310 goto fail3;
1311 }
1312 memset(result->first, 0, sizeof(struct QH) * queuesize);
1313 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1314
1315 for (i = 0; i < queuesize; i++) {
1316 struct QH *qh = result->first + i;
1317 struct qTD *td = result->tds + i;
1318 void **buf = &qh->buffer;
1319
1320 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1321 if (i == queuesize - 1)
1322 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1323
1324 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1325 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1326 qh->qh_endpt1 =
1327 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1328 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1329 (1 << 14) |
1330 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1331 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1332 (usb_pipedevice(pipe) << 0));
1333 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1334 (1 << 0)); /* S-mask: microframe 0 */
1335 if (dev->speed == USB_SPEED_LOW ||
1336 dev->speed == USB_SPEED_FULL) {
1337 /* C-mask: microframes 2-4 */
1338 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1339 }
1340 ehci_update_endpt2_dev_n_port(dev, qh);
1341
1342 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1343 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1344 debug("communication direction is '%s'\n",
1345 usb_pipein(pipe) ? "in" : "out");
1346 td->qt_token = cpu_to_hc32((elementsize << 16) |
1347 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1348 0x80); /* active */
1349 td->qt_buffer[0] =
1350 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1351 td->qt_buffer[1] =
1352 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1353 td->qt_buffer[2] =
1354 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1355 td->qt_buffer[3] =
1356 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1357 td->qt_buffer[4] =
1358 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1359
1360 *buf = buffer + i * elementsize;
1361 }
1362
1363 flush_dcache_range((unsigned long)buffer,
1364 ALIGN_END_ADDR(char, buffer,
1365 queuesize * elementsize));
1366 flush_dcache_range((unsigned long)result->first,
1367 ALIGN_END_ADDR(struct QH, result->first,
1368 queuesize));
1369 flush_dcache_range((unsigned long)result->tds,
1370 ALIGN_END_ADDR(struct qTD, result->tds,
1371 queuesize));
1372
1373 if (ctrl->periodic_schedules > 0) {
1374 if (disable_periodic(ctrl) < 0) {
1375 debug("FATAL: periodic should never fail, but did");
1376 goto fail3;
1377 }
1378 }
1379
1380 /* hook up to periodic list */
1381 struct QH *list = &ctrl->periodic_queue;
1382 result->last->qh_link = list->qh_link;
1383 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1384
1385 flush_dcache_range((unsigned long)result->last,
1386 ALIGN_END_ADDR(struct QH, result->last, 1));
1387 flush_dcache_range((unsigned long)list,
1388 ALIGN_END_ADDR(struct QH, list, 1));
1389
1390 if (enable_periodic(ctrl) < 0) {
1391 debug("FATAL: periodic should never fail, but did");
1392 goto fail3;
1393 }
1394 ctrl->periodic_schedules++;
1395
1396 debug("Exit create_int_queue\n");
1397 return result;
1398 fail3:
1399 if (result->tds)
1400 free(result->tds);
1401 fail2:
1402 if (result->first)
1403 free(result->first);
1404 if (result)
1405 free(result);
1406 fail1:
1407 return NULL;
1408 }
1409
1410 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1411 {
1412 struct QH *cur = queue->current;
1413 struct qTD *cur_td;
1414
1415 /* depleted queue */
1416 if (cur == NULL) {
1417 debug("Exit poll_int_queue with completed queue\n");
1418 return NULL;
1419 }
1420 /* still active */
1421 cur_td = &queue->tds[queue->current - queue->first];
1422 invalidate_dcache_range((unsigned long)cur_td,
1423 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1424 if (QT_TOKEN_GET_STATUS(hc32_to_cpu(cur_td->qt_token)) &
1425 QT_TOKEN_STATUS_ACTIVE) {
1426 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n",
1427 hc32_to_cpu(cur_td->qt_token));
1428 return NULL;
1429 }
1430 if (!(cur->qh_link & QH_LINK_TERMINATE))
1431 queue->current++;
1432 else
1433 queue->current = NULL;
1434
1435 invalidate_dcache_range((unsigned long)cur->buffer,
1436 ALIGN_END_ADDR(char, cur->buffer,
1437 queue->elementsize));
1438
1439 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1440 hc32_to_cpu(cur_td->qt_token), cur, queue->first);
1441 return cur->buffer;
1442 }
1443
1444 /* Do not free buffers associated with QHs, they're owned by someone else */
1445 int
1446 destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1447 {
1448 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1449 int result = -1;
1450 unsigned long timeout;
1451
1452 if (disable_periodic(ctrl) < 0) {
1453 debug("FATAL: periodic should never fail, but did");
1454 goto out;
1455 }
1456 ctrl->periodic_schedules--;
1457
1458 struct QH *cur = &ctrl->periodic_queue;
1459 timeout = get_timer(0) + 500; /* abort after 500ms */
1460 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1461 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1462 if (NEXT_QH(cur) == queue->first) {
1463 debug("found candidate. removing from chain\n");
1464 cur->qh_link = queue->last->qh_link;
1465 flush_dcache_range((unsigned long)cur,
1466 ALIGN_END_ADDR(struct QH, cur, 1));
1467 result = 0;
1468 break;
1469 }
1470 cur = NEXT_QH(cur);
1471 if (get_timer(0) > timeout) {
1472 printf("Timeout destroying interrupt endpoint queue\n");
1473 result = -1;
1474 goto out;
1475 }
1476 }
1477
1478 if (ctrl->periodic_schedules > 0) {
1479 result = enable_periodic(ctrl);
1480 if (result < 0)
1481 debug("FATAL: periodic should never fail, but did");
1482 }
1483
1484 out:
1485 free(queue->tds);
1486 free(queue->first);
1487 free(queue);
1488
1489 return result;
1490 }
1491
1492 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1493 void *buffer, int length, int interval)
1494 {
1495 void *backbuffer;
1496 struct int_queue *queue;
1497 unsigned long timeout;
1498 int result = 0, ret;
1499
1500 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1501 dev, pipe, buffer, length, interval);
1502
1503 queue = create_int_queue(dev, pipe, 1, length, buffer, interval);
1504 if (!queue)
1505 return -1;
1506
1507 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1508 while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
1509 if (get_timer(0) > timeout) {
1510 printf("Timeout poll on interrupt endpoint\n");
1511 result = -ETIMEDOUT;
1512 break;
1513 }
1514
1515 if (backbuffer != buffer) {
1516 debug("got wrong buffer back (%p instead of %p)\n",
1517 backbuffer, buffer);
1518 return -EINVAL;
1519 }
1520
1521 ret = destroy_int_queue(dev, queue);
1522 if (ret < 0)
1523 return ret;
1524
1525 /* everything worked out fine */
1526 return result;
1527 }
1528
1529 #ifndef CONFIG_DM_USB
1530 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1531 void *buffer, int length)
1532 {
1533 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1534 }
1535
1536 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1537 int length, struct devrequest *setup)
1538 {
1539 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1540 }
1541
1542 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1543 void *buffer, int length, int interval)
1544 {
1545 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
1546 }
1547 #endif
1548
1549 #ifdef CONFIG_DM_USB
1550 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1551 unsigned long pipe, void *buffer, int length,
1552 struct devrequest *setup)
1553 {
1554 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1555 dev->name, udev, udev->dev->name, udev->portnr);
1556
1557 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1558 }
1559
1560 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1561 unsigned long pipe, void *buffer, int length)
1562 {
1563 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1564 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1565 }
1566
1567 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1568 unsigned long pipe, void *buffer, int length,
1569 int interval)
1570 {
1571 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1572 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
1573 }
1574
1575 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1576 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1577 uint tweaks, enum usb_init_type init)
1578 {
1579 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1580 int ret;
1581
1582 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1583 dev->name, ctrl, hccr, hcor, init);
1584
1585 ehci_setup_ops(ctrl, ops);
1586 ctrl->hccr = hccr;
1587 ctrl->hcor = hcor;
1588 ctrl->priv = ctrl;
1589
1590 if (init == USB_INIT_DEVICE)
1591 goto done;
1592 ret = ehci_reset(ctrl);
1593 if (ret)
1594 goto err;
1595
1596 ret = ehci_common_init(ctrl, tweaks);
1597 if (ret)
1598 goto err;
1599 done:
1600 return 0;
1601 err:
1602 free(ctrl);
1603 debug("%s: failed, ret=%d\n", __func__, ret);
1604 return ret;
1605 }
1606
1607 int ehci_deregister(struct udevice *dev)
1608 {
1609 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1610
1611 ehci_shutdown(ctrl);
1612
1613 return 0;
1614 }
1615
1616 struct dm_usb_ops ehci_usb_ops = {
1617 .control = ehci_submit_control_msg,
1618 .bulk = ehci_submit_bulk_msg,
1619 .interrupt = ehci_submit_int_msg,
1620 };
1621
1622 #endif
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