1 2020-05-17 Jeff Law <law@redhat.com>
3 * config/h8300/predicates.md (pc_or_label_operand): New predicate.
4 * config/h8300/jumpcall.md (branch_true, branch_false): Consolidate
5 into a single pattern using pc_or_label_operand.
6 * config/h8300/combiner.md (bit branch patterns): Likewise.
7 * config/h8300/peepholes.md (HImode and SImode branches): Likewise.
9 2020-05-17 H.J. Lu <hongjiu.lu@intel.com>
12 * config/i386/i386-features.c (has_non_address_hard_reg):
14 (pseudo_reg_set): This. Return the SET expression. Ignore
16 (general_scalar_to_vector_candidate_p): Combine single_set and
17 has_non_address_hard_reg calls to pseudo_reg_set.
18 (timode_scalar_to_vector_candidate_p): Likewise.
19 * config/i386/i386.md (*pushv1ti2): New pattern.
21 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
24 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
26 * tree-vrp.c (operand_less_p): Move to...
27 * vr-values.c (operand_less_p): ...here.
28 * tree-vrp.h (operand_less_p): Remove.
30 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
32 * tree-vrp.c (operand_less_p): Move to...
33 * vr-values.c (operand_less_p): ...here.
34 * tree-vrp.h (operand_less_p): Remove.
36 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
38 * tree-vrp.c (class vrp_insert): Remove prototype for
41 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
43 * tree-vrp.c (class live_names): New.
44 (live_on_edge): Move into live_names.
45 (build_assert_expr_for): Move into vrp_insert.
46 (find_assert_locations_in_bb): Rename from
47 find_assert_locations_1.
48 (process_assert_insertions_for): Move into vrp_insert.
49 (compare_assert_loc): Same.
50 (remove_range_assertions): Same.
51 (dump_asserts_for): Rename to vrp_insert::dump.
52 (debug_asserts_for): Rename to vrp_insert::debug.
53 (dump_all_asserts): Rename to vrp_insert::dump.
54 (debug_all_asserts): Rename to vrp_insert::debug.
56 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
58 * tree-vrp.c (class vrp_prop): Move check_all_array_refs,
59 check_array_ref, check_mem_ref, and search_for_addr_array
61 (class array_bounds_checker): ...here.
62 (class check_array_bounds_dom_walker): Adjust to use
64 (check_all_array_refs): Move into array_bounds_checker and rename
66 (class vrp_folder): Make fold_predicate_in private.
68 2020-05-15 Jeff Law <law@redhat.com>
70 * config/h8300/h8300.md (SFI iterator): New iterator for
72 * config/h8300/peepholes.md (memory comparison): Use mode
73 iterator to consolidate 3 patterns into one.
74 (stack allocation and stack store): Handle SFmode. Handle
77 2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
79 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_2): Also require
82 2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
84 * config/i386/i386.md (SWI48DWI): New mode iterator.
85 (*push<mode>2): Allow XMM registers.
86 (*pushdi2_rex64): Ditto.
87 (*pushsi2_rex64): Ditto.
89 (push XMM reg splitter): New splitter
91 (*pushdf) Change "x" operand constraint to "v".
92 (*pushsf_rex64): Ditto.
95 2020-05-15 Richard Biener <rguenther@suse.de>
97 PR tree-optimization/92260
98 * tree-vect-slp.c (vect_get_constant_vectors): Compute
99 the number of vector stmts in a canonical way.
101 2020-05-15 Martin Liska <mliska@suse.cz>
103 * hsa-gen.c (get_symbol_for_decl): Fix misleading indentation
106 2020-05-15 Andrew Stubbs <ams@codesourcery.com>
108 * config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.
110 2020-05-15 Richard Biener <rguenther@suse.de>
112 PR tree-optimization/95133
113 * gimple-ssa-split-paths.c
114 (find_block_to_duplicate_for_splitting_paths): Check for
117 2020-05-15 Christophe Lyon <christophe.lyon@linaro.org>
119 * config/arm/arm.c (reg_needs_saving_p): Add support for interrupt
121 (arm_compute_save_reg0_reg12_mask): Use reg_needs_saving_p.
123 2020-05-15 Tobias Burnus <tobias@codesourcery.com>
126 * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with
127 OMP_TARGET_EXIT_DATA, use 'release:' unless the associated
130 2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
133 * config/i386/i386.md (isa): Add sse3_noavx.
134 (enabled): Handle sse3_noavx.
136 * config/i386/mmx.md (mmx_haddv2sf3): New expander.
137 (*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX
138 alternatives. Match commutative vec_select selector operands.
139 (*mmx_haddv2sf3_low): New insn pattern.
141 (*mmx_hsubv2sf3): Add SSE/AVX alternatives.
142 (*mmx_hsubv2sf3_low): New insn pattern.
144 2020-05-15 Richard Biener <rguenther@suse.de>
146 PR tree-optimization/33315
147 * tree-ssa-sink.c: Include tree-eh.h.
148 (sink_stats): Add commoned member.
149 (sink_common_stores_to_bb): New function implementing store
150 commoning by sinking to the successor.
151 (sink_code_in_bb): Call it, pass down TODO_cleanup_cfg returned.
152 (pass_sink_code::execute): Likewise. Record commoned stores
155 2020-05-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
157 PR rtl-optimization/37451, part of PR target/61837
158 * loop-doloop.c (doloop_simplify_count): New function. Simplify
159 (add -1; zero_ext; add +1) to zero_ext when not wrapping.
160 (doloop_modify): Call doloop_simplify_count.
162 2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
165 * doc/sourcebuild.texi: Document effective target lgccjit.
167 2020-05-14 Andrew Stubbs <ams@codesourcery.com>
169 * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a
170 define_expand, and rename the original to ...
171 (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand.
172 (add<mode>3_zext_dup_exec): Likewise, with ...
173 (add<mode>3_vcc_zext_dup_exec): ... this.
174 (add<mode>3_zext_dup2): Likewise, with ...
175 (add<mode>3_zext_dup_exec): ... this.
176 (add<mode>3_zext_dup2_exec): Likewise, with ...
177 (add<mode>3_zext_dup2): ... this.
178 * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch
179 addv64di3_zext* calls to use addv64di3_vcc_zext*.
181 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
184 * config/i386/sse.md (truncv2dfv2df2): New insn pattern.
185 (extendv2sfv2df2): Ditto.
187 2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
189 * configure: Regenerated.
191 2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
193 * config/arm/arm.c (reg_needs_saving_p): New function.
194 (use_return_insn): Use reg_needs_saving_p.
195 (arm_get_vfp_saved_size): Likewise.
196 (arm_compute_frame_layout): Likewise.
197 (arm_save_coproc_regs): Likewise.
198 (thumb1_expand_epilogue): Likewise.
199 (arm_expand_epilogue_apcs_frame): Likewise.
200 (arm_expand_epilogue): Likewise.
202 2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
204 * config/arm/arm.c (thumb1_expand_prologue): Update error message.
206 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
209 * config/i386/sse.md (sse2_cvtpi2pd): Add memory to alternative 1.
211 (floatv2siv2df2): New expander.
212 (floatunsv2siv2df2): New insn pattern.
214 (fix_truncv2dfv2si2): New expander.
215 (fixuns_truncv2dfv2si2): New insn pattern.
217 2020-05-14 Richard Sandiford <richard.sandiford@arm.com>
220 * config/aarch64/aarch64-sve-builtins.cc
221 (handle_arm_sve_vector_bits_attribute): Create a copy of the
222 original type's TYPE_MAIN_VARIANT, then reapply all the differences
223 between the original type and its main variant.
225 2020-05-14 Richard Biener <rguenther@suse.de>
228 * real.c (real_to_decimal_for_mode): Make sure we handle
229 a zero with nonzero exponent.
231 2020-05-14 Jakub Jelinek <jakub@redhat.com>
233 * Makefile.in (GTFILES): Add omp-general.c.
234 * cgraph.h (struct cgraph_node): Add declare_variant_alt and
235 calls_declare_variant_alt members and initialize them in the
237 * ipa.c (symbol_table::remove_unreachable_nodes): Handle direct
238 calls to declare_variant_alt nodes.
239 * lto-cgraph.c (lto_output_node): Write declare_variant_alt
240 and calls_declare_variant_alt.
241 (input_overwrite_node): Read them back.
242 * omp-simd-clone.c (simd_clone_create): Copy calls_declare_variant_alt
244 * tree-inline.c (expand_call_inline): Or in calls_declare_variant_alt
246 (tree_function_versioning): Copy calls_declare_variant_alt bit.
247 * omp-offload.c (execute_omp_device_lower): Call
248 omp_resolve_declare_variant on direct function calls.
249 (pass_omp_device_lower::gate): Also enable for
250 calls_declare_variant_alt functions.
251 * omp-general.c (omp_maybe_offloaded): Return false after inlining.
252 (omp_context_selector_matches): Handle the case when
253 cfun->curr_properties has PROP_gimple_any bit set.
254 (struct omp_declare_variant_entry): New type.
255 (struct omp_declare_variant_base_entry): New type.
256 (struct omp_declare_variant_hasher): New type.
257 (omp_declare_variant_hasher::hash, omp_declare_variant_hasher::equal):
259 (omp_declare_variants): New variable.
260 (struct omp_declare_variant_alt_hasher): New type.
261 (omp_declare_variant_alt_hasher::hash,
262 omp_declare_variant_alt_hasher::equal): New methods.
263 (omp_declare_variant_alt): New variables.
264 (omp_resolve_late_declare_variant): New function.
265 (omp_resolve_declare_variant): Call omp_resolve_late_declare_variant
266 when called late. Create a magic declare_variant_alt fndecl and
267 cgraph node and return that if decision needs to be deferred until
268 after gimplification.
269 * cgraph.c (symbol_table::create_edge): Or in calls_declare_variant_alt
273 * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member.
274 (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in
275 entry block if info->after_stmt is NULL, otherwise add after that stmt
276 and update it after adding each stmt.
277 (ipa_simd_modify_function_body): Initialize info.after_stmt.
279 * function.h (struct function): Add has_omp_target bit.
280 * omp-offload.c (omp_discover_declare_target_fn_r): New function,
282 (omp_discover_declare_target_tgt_fn_r): ... this.
283 (omp_discover_declare_target_var_r): Call
284 omp_discover_declare_target_tgt_fn_r instead of
285 omp_discover_declare_target_fn_r.
286 (omp_discover_implicit_declare_target): Also queue functions with
287 has_omp_target bit set, for those walk with
288 omp_discover_declare_target_fn_r, for declare target to functions
289 walk with omp_discover_declare_target_tgt_fn_r.
291 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
294 * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): Rename from mmx_pf2id.
295 Add SSE/AVX alternative. Change operand predicates from
296 nonimmediate_operand to register_mmxmem_operand.
297 Enable instruction pattern for TARGET_MMX_WITH_SSE.
298 (fix_truncv2sfv2si2): New expander.
299 (fixuns_truncv2sfv2si2): New insn pattern.
301 (mmx_floatv2siv2sf2): rename from mmx_floatv2si2.
302 Add SSE/AVX alternative. Change operand predicates from
303 nonimmediate_operand to register_mmxmem_operand.
304 Enable instruction pattern for TARGET_MMX_WITH_SSE.
305 (floatv2siv2sf2): New expander.
306 (floatunsv2siv2sf2): New insn pattern.
308 * config/i386/i386-builtin.def (IX86_BUILTIN_PF2ID):
310 (IX86_BUILTIN_PI2FD): Ditto.
312 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
314 * config/s390/s390.c (s390_emit_stack_probe): Call the probe_stack
316 * config/s390/s390.md ("@probe_stack2<mode>", "probe_stack"): New
319 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
321 * config/s390/s390.c (allocate_stack_space): Add missing updates
322 of last_probe_offset.
324 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
326 * config/s390/s390.md ("allocate_stack"): Call
327 anti_adjust_stack_and_probe_stack_clash when stack clash
328 protection is enabled.
329 * explow.c (anti_adjust_stack_and_probe_stack_clash): Remove
330 prototype. Remove static.
331 * explow.h (anti_adjust_stack_and_probe_stack_clash): Add
334 2020-05-13 Kelvin Nilsen <kelvin@gcc.gnu.org>
336 * config/rs6000/altivec.h (vec_extractl): New #define.
337 (vec_extracth): Likewise.
338 * config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant.
339 (UNSPEC_EXTRACTR): Likewise.
340 (vextractl<mode>): New expansion.
341 (vextractl<mode>_internal): New insn.
342 (vextractr<mode>): New expansion.
343 (vextractr<mode>_internal): New insn.
344 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vextdubvlx):
345 New built-in function.
346 (__builtin_altivec_vextduhvlx): Likewise.
347 (__builtin_altivec_vextduwvlx): Likewise.
348 (__builtin_altivec_vextddvlx): Likewise.
349 (__builtin_altivec_vextdubvhx): Likewise.
350 (__builtin_altivec_vextduhvhx): Likewise.
351 (__builtin_altivec_vextduwvhx): Likewise.
352 (__builtin_altivec_vextddvhx): Likewise.
353 (__builtin_vec_extractl): New overloaded built-in function.
354 (__builtin_vec_extracth): Likewise.
355 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
356 Define overloaded forms of __builtin_vec_extractl and
357 __builtin_vec_extracth.
358 (builtin_function_type): Add cases to mark arguments of new
359 built-in functions as unsigned.
360 (rs6000_common_init_builtins): Add
361 opaque_ftype_opaque_opaque_opaque_opaque.
362 * config/rs6000/rs6000.md (du_or_d): New mode attribute.
363 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
364 for a Future Architecture): Add description of vec_extractl and
365 vec_extractr built-in functions.
367 2020-05-13 Richard Biener <rguenther@suse.de>
369 * target.def (add_stmt_cost): Add new vectype parameter.
370 * targhooks.c (default_add_stmt_cost): Adjust.
371 * targhooks.h (default_add_stmt_cost): Likewise.
372 * config/aarch64/aarch64.c (aarch64_add_stmt_cost): Take new
374 * config/arm/arm.c (arm_add_stmt_cost): Likewise.
375 * config/i386/i386.c (ix86_add_stmt_cost): Likewise.
376 * config/rs6000/rs6000.c (rs6000_add_stmt_cost): Likewise.
378 * tree-vectorizer.h (stmt_info_for_cost::vectype): Add.
379 (dump_stmt_cost): Add new vectype parameter.
380 (add_stmt_cost): Likewise.
381 (record_stmt_cost): Likewise.
382 (record_stmt_cost): Add overload with old signature.
383 * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost):
385 (vect_get_known_peeling_cost): Likewise.
386 (vect_estimate_min_profitable_iters): Likewise.
387 * tree-vectorizer.c (dump_stmt_cost): Add new vectype parameter.
388 * tree-vect-stmts.c (record_stmt_cost): Likewise.
389 (vect_prologue_cost_for_slp_op): Remove stmt_vec_info parameter
390 and pass down correct vectype and NULL stmt_info.
391 (vect_model_simple_cost): Adjust.
392 (vect_model_store_cost): Likewise.
394 2020-05-13 Richard Biener <rguenther@suse.de>
396 * tree-vectorizer.h (SLP_INSTANCE_GROUP_SIZE): Remove.
397 (_slp_instance::group_size): Likewise.
398 * tree-vect-loop.c (vectorizable_reduction): The group size
399 is the number of lanes in the node.
400 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Likewise.
401 (vect_analyze_slp_instance): Do not set SLP_INSTANCE_GROUP_SIZE,
402 verify it matches the instance trees number of lanes.
403 (vect_slp_analyze_node_operations_1): Use the numer of lanes
404 in the node as group size.
405 (vect_bb_vectorization_profitable_p): Use the instance root
406 number of lanes for the size of life.
407 (vect_schedule_slp_instance): Use the number of lanes as
409 * tree-vect-stmts.c (vectorizable_load): Remove SLP instance
410 parameter. Use the number of lanes of the load for the group
411 size in the gap adjustment code.
412 (vect_analyze_stmt): Adjust.
413 (vect_transform_stmt): Likewise.
415 2020-05-13 Jakub Jelinek <jakub@redhat.com>
418 * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even
419 if the last insn is a note.
421 PR tree-optimization/95060
422 * tree-ssa-math-opts.c (convert_mult_to_fma_1): Fold a NEGATE_EXPR
423 if it is the single use of the FMA internal builtin.
425 2020-05-13 Bin Cheng <bin.cheng@linux.alibaba.com>
427 PR tree-optimization/94969
428 * tree-data-dependence.c (constant_access_functions): Rename to...
429 (invariant_access_functions): ...this. Add parameter. Check for
430 invariant access function, rather than constant.
431 (build_classic_dist_vector): Call above function.
432 * tree-loop-distribution.c (pg_add_dependence_edges): Add comment.
434 2020-05-13 Hongtao Liu <hongtao.liu@intel.com>
437 * doc/extend.texi (x86Operandmodifiers): Document more x86
439 * gcc/config/i386/i386.c: Add comment for operand modifier N and I.
441 2020-05-12 Giuliano Belinassi <giuliano.belinassi@usp.br>
443 * tree-vrp.c (class vrp_insert): New.
444 (insert_range_assertions): Move to class vrp_insert.
445 (dump_all_asserts): Same as above.
446 (dump_asserts_for): Same as above.
447 (live): Same as above.
448 (need_assert_for): Same as above.
449 (live_on_edge): Same as above.
450 (finish_register_edge_assert_for): Same as above.
451 (find_switch_asserts): Same as above.
452 (find_assert_locations): Same as above.
453 (find_assert_locations_1): Same as above.
454 (find_conditional_asserts): Same as above.
455 (process_assert_insertions): Same as above.
456 (register_new_assert_for): Same as above.
457 (vrp_prop): New variable fun.
458 (vrp_initialize): New parameter.
459 (identify_jump_threads): Same as above.
460 (execute_vrp): Same as above.
463 2020-05-12 Keith Packard <keith.packard@sifive.com>
465 * config/riscv/riscv.c (riscv_unique_section): New.
466 (TARGET_ASM_UNIQUE_SECTION): New.
468 2020-05-12 Craig Blackmore <craig.blackmore@embecosm.com>
470 * config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv.
471 * config/riscv/riscv-passes.def: New file.
472 * config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare.
473 * config/riscv/riscv-shorten-memrefs.c: New file.
474 * config/riscv/riscv.c (tree-pass.h): New include.
475 (riscv_compressed_reg_p): New Function
476 (riscv_compressed_lw_offset_p): Likewise.
477 (riscv_compressed_lw_address_p): Likewise.
478 (riscv_shorten_lw_offset): Likewise.
479 (riscv_legitimize_address): Attempt to convert base + large_offset
480 to compressible new_base + small_offset.
481 (riscv_address_cost): Make anticipated compressed load/stores
482 cheaper for code size than uncompressed load/stores.
483 (riscv_register_priority): Move compressed register check to
484 riscv_compressed_reg_p.
485 * config/riscv/riscv.h (C_S_BITS): Define.
486 (CSW_MAX_OFFSET): Define.
487 * config/riscv/riscv.opt (mshorten-memefs): New option.
488 * config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule.
489 (PASSES_EXTRA): Add riscv-passes.def.
490 * doc/invoke.texi: Document -mshorten-memrefs.
492 * config/riscv/riscv.c (riscv_new_address_profitable_p): New function.
493 (TARGET_NEW_ADDRESS_PROFITABLE_P): Define.
494 * doc/tm.texi: Regenerate.
495 * doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P): New hook.
496 * sched-deps.c (attempt_change): Use old address if it is cheaper than
498 * target.def (new_address_profitable_p): New hook.
499 * targhooks.c (default_new_address_profitable_p): New function.
500 * targhooks.h (default_new_address_profitable_p): Declare.
502 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
505 * config/i386/mmx.md (copysignv2sf3): New expander.
506 (xorsignv2sf3): Ditto.
507 (signbitv2sf3): Ditto.
509 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
512 * config/i386/mmx.md (fmav2sf4): New insn pattern.
517 2020-05-12 H.J. Lu <hongjiu.lu@intel.com>
519 * Makefile.in (CET_HOST_FLAGS): New.
520 (COMPILER): Add $(CET_HOST_FLAGS).
521 * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and
522 AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't
524 * aclocal.m4: Regenerated.
525 * configure: Likewise.
527 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
530 * config/i386/mmx.md (<code>v2sf2): New insn pattern.
531 (*mmx_<code>v2sf2): New insn_and_split pattern.
532 (*mmx_nabsv2sf2): Ditto.
533 (*mmx_andnotv2sf3): New insn pattern.
534 (*mmx_<code>v2sf3): Ditto.
535 * config/i386/i386.md (absneg_op): New code attribute.
536 * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
537 (ix86_build_signbit_mask): Ditto.
539 2020-05-12 Richard Biener <rguenther@suse.de>
541 * tree-ssa-live.c (remove_unused_locals): Remove dead debug
544 2020-05-12 Jozef Lawrynowicz <jozef.l@mittosystems.com>
546 * config/msp430/msp430-protos.h (msp430_output_aligned_decl_common):
547 Update prototype to include "local" argument.
548 * config/msp430/msp430.c (msp430_output_aligned_decl_common): Add
549 "local" argument. Handle local common decls.
550 * config/msp430/msp430.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Adjust
551 msp430_output_aligned_decl_common call with 0 for "local" argument.
552 (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Define.
554 2020-05-12 Richard Biener <rguenther@suse.de>
556 * cfghooks.c (split_edge): Preserve EDGE_DFS_BACK if set.
558 2020-05-12 Martin Liska <mliska@suse.cz>
562 * sanopt.c (sanitize_rewrite_addressable_params):
563 Clear DECL_NOT_GIMPLE_REG_P for argument.
565 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
567 PR tree-optimization/94980
568 * tree-vect-generic.c (expand_vector_comparison): Use
569 vector_element_bits_tree to get the element size in bits,
570 rather than using TYPE_SIZE.
571 (expand_vector_condition, vector_element): Likewise.
573 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
575 PR tree-optimization/94980
576 * tree-vect-generic.c (build_replicated_const): Take the number
577 of bits as a parameter, instead of the type of the elements.
578 (do_plus_minus): Update accordingly, using vector_element_bits
579 to calculate the correct number of bits.
580 (do_negate): Likewise.
582 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
584 PR tree-optimization/94980
585 * tree.h (vector_element_bits, vector_element_bits_tree): Declare.
586 * tree.c (vector_element_bits, vector_element_bits_tree): New.
587 * match.pd: Use the new functions instead of determining the
588 vector element size directly from TYPE_SIZE(_UNIT).
589 * tree-vect-data-refs.c (vect_gather_scatter_fn_p): Likewise.
590 * tree-vect-patterns.c (vect_recog_mask_conversion_pattern): Likewise.
591 * tree-vect-stmts.c (vect_is_simple_cond): Likewise.
592 * tree-vect-generic.c (expand_vector_piecewise): Likewise.
593 (expand_vector_conversion): Likewise.
594 (expand_vector_addition): Likewise for a TYPE_SIZE_UNIT used as
595 a divisor. Convert the dividend to bits to compensate.
596 * tree-vect-loop.c (vectorizable_live_operation): Call
597 vector_element_bits instead of open-coding it.
599 2020-05-12 Jakub Jelinek <jakub@redhat.com>
601 * omp-offload.h (omp_discover_implicit_declare_target): Declare.
602 * omp-offload.c: Include context.h.
603 (omp_declare_target_fn_p, omp_declare_target_var_p,
604 omp_discover_declare_target_fn_r, omp_discover_declare_target_var_r,
605 omp_discover_implicit_declare_target): New functions.
606 * cgraphunit.c (analyze_functions): Call
607 omp_discover_implicit_declare_target.
609 2020-05-12 Richard Biener <rguenther@suse.de>
611 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Canonicalize
612 literal constant &MEM[..] to a constant literal.
614 2020-05-12 Richard Biener <rguenther@suse.de>
616 PR tree-optimization/95045
617 * dbgcnt.def (lim): Add debug-counter.
618 * tree-ssa-loop-im.c: Include dbgcnt.h.
619 (find_refs_for_sm): Use lim debug counter for store motion
621 (do_store_motion): Rename form store_motion. Commit edge
623 (store_motion_loop): ... here.
624 (tree_ssa_lim): Adjust.
626 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
628 * config/rs6000/altivec.h (vec_clzm): Rename to vec_cntlzm.
629 (vec_ctzm): Rename to vec_cnttzm.
630 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
631 Change fourth operand for vec_ternarylogic to require
632 compatibility with unsigned SImode rather than unsigned QImode.
633 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
634 Remove overloaded forms of vec_gnb that are no longer needed.
635 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
636 for a Future Architecture): Replace vec_clzm with vec_cntlzm;
637 replace vec_ctzm with vec_cntlzm; remove four unwanted forms of
638 vec_gnb; move vec_ternarylogic documentation into this section
639 and replace const unsigned char with const unsigned int as its
642 2020-05-11 Carl Love <cel@us.ibm.com>
644 * config/rs6000/altivec.h (vec_genpcvm): New #define.
645 * config/rs6000/rs6000-builtin.def (XXGENPCVM_V16QI): New built-in
647 (XXGENPCVM_V8HI): Likewise.
648 (XXGENPCVM_V4SI): Likewise.
649 (XXGENPCVM_V2DI): Likewise.
650 (XXGENPCVM): New overloaded built-in instantiation.
651 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add
652 entries for FUTURE_BUILTIN_VEC_XXGENPCVM.
653 (altivec_expand_builtin): Add special handling for
654 FUTURE_BUILTIN_VEC_XXGENPCVM.
655 (builtin_function_type): Add handling for
656 FUTURE_BUILTIN_XXGENPCVM_{V16QI,V8HI,V4SI,V2DI}.
657 * config/rs6000/vsx.md (VSX_EXTRACT_I4): New mode iterator.
658 (UNSPEC_XXGENPCV): New constant.
659 (xxgenpcvm_<mode>_internal): New insn.
660 (xxgenpcvm_<mode>): New expansion.
661 * doc/extend.texi: Add documentation for vec_genpcvm built-ins.
663 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
665 * config/rs6000/altivec.h (vec_strir): New #define.
666 (vec_stril): Likewise.
667 (vec_strir_p): Likewise.
668 (vec_stril_p): Likewise.
669 * config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
670 (UNSPEC_VSTRIL): Likewise.
671 (vstrir_<mode>): New expansion.
672 (vstrir_code_<mode>): New insn.
673 (vstrir_p_<mode>): New expansion.
674 (vstrir_p_code_<mode>): New insn.
675 (vstril_<mode>): New expansion.
676 (vstril_code_<mode>): New insn.
677 (vstril_p_<mode>): New expansion.
678 (vstril_p_code_<mode>): New insn.
679 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
680 New built-in function.
681 (__builtin_altivec_vstrihr): Likewise.
682 (__builtin_altivec_vstribl): Likewise.
683 (__builtin_altivec_vstrihl): Likewise.
684 (__builtin_altivec_vstribr_p): Likewise.
685 (__builtin_altivec_vstrihr_p): Likewise.
686 (__builtin_altivec_vstribl_p): Likewise.
687 (__builtin_altivec_vstrihl_p): Likewise.
688 (__builtin_vec_strir): New overloaded built-in function.
689 (__builtin_vec_stril): Likewise.
690 (__builtin_vec_strir_p): Likewise.
691 (__builtin_vec_stril_p): Likewise.
692 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
693 Define overloaded forms of __builtin_vec_strir,
694 __builtin_vec_stril, __builtin_vec_strir_p, and
695 __builtin_vec_stril_p.
696 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
697 for a Future Architecture): Add description of vec_stril,
698 vec_stril_p, vec_strir, and vec_strir_p built-in functions.
700 2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
702 * config/rs6000/altivec.h (vec_ternarylogic): New #define.
703 * config/rs6000/altivec.md (UNSPEC_XXEVAL): New constant.
705 * config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
706 * config/rs6000/rs6000-builtin.def: Add handling of new macro
708 (BU_FUTURE_V_4): New macro. Use it.
709 (BU_FUTURE_OVERLOAD_4): Likewise.
710 * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Add
711 handling for quaternary built-in functions.
712 (altivec_resolve_overloaded_builtin): Add special-case handling
713 for __builtin_vec_xxeval.
714 * config/rs6000/rs6000-call.c: Add handling of new macro
715 RS6000_BUILTIN_4 in initialization of rs6000_builtin_info,
716 bdesc0_arg, bdesc1_arg, bdesc2_arg, bdesc_3arg,
717 bdesc_altivec_preds, bdesc_abs, and bdesc_htm arrays.
718 (altivec_overloaded_builtins): Add definitions for
719 FUTURE_BUILTIN_VEC_XXEVAL.
720 (bdesc_4arg): New array.
721 (htm_expand_builtin): Add handling for quaternary built-in
723 (rs6000_expand_quaternop_builtin): New function.
724 (rs6000_expand_builtin): Add handling for quaternary built-in
726 (rs6000_init_builtins): Initialize builtin_mode_to_type entries
727 for unsigned QImode and unsigned HImode.
728 (builtin_quaternary_function_type): New function.
729 (rs6000_common_init_builtins): Add handling of quaternary
731 * config/rs6000/rs6000.h (RS6000_BTC_QUATERNARY): New defined
733 (RS6000_BTC_PREDICATE): Change value of constant.
734 (RS6000_BTC_ABS): Likewise.
735 (rs6000_builtins): Add support for new macro RS6000_BUILTIN_4.
736 * doc/extend.texi (PowerPC AltiVec Built-In Functions Available
737 for a Future Architecture): Add description of vec_ternarylogic
740 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
742 * config/rs6000/rs6000-builtin.def (__builtin_pdepd): New built-in
744 (__builtin_pextd): Likewise.
745 * config/rs6000/rs6000.md (UNSPEC_PDEPD): New constant.
746 (UNSPEC_PEXTD): Likewise.
749 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
750 a Future Architecture): Add descriptions of __builtin_pdepd and
751 __builtin_pextd functions.
753 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
755 * config/rs6000/altivec.h (vec_clrl): New #define.
756 (vec_clrr): Likewise.
757 * config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
758 (UNSPEC_VCLRRB): Likewise.
761 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
763 (__builtin_altivec_vclrrb): Likewise.
764 (__builtin_vec_clrl): New overloaded built-in function.
765 (__builtin_vec_clrr): Likewise.
766 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
767 Define overloaded forms of __builtin_vec_clrl and
769 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
770 for a Future Architecture): Add descriptions of vec_clrl and
773 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
775 * config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
776 built-in function definition.
777 (__builtin_cnttzdm): Likewise.
778 * config/rs6000/rs6000.md (UNSPEC_CNTLZDM): New constant.
779 (UNSPEC_CNTTZDM): Likewise.
782 * doc/extend.texi (Basic PowerPC Built-in Functions available for
783 a Future Architecture): Add descriptions of __builtin_cntlzdm and
784 __builtin_cnttzdm functions.
786 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
789 * config/i386/mmx.md (sqrtv2sf2): New insn pattern.
791 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
793 * config/rs6000/altivec.h (vec_cfuge): New #define.
794 * config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant.
796 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged):
797 New built-in function.
798 * config/rs6000/rs6000-call.c (builtin_function_type): Add
799 handling for FUTURE_BUILTIN_VCFUGED case.
800 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
801 for a Future Architecture): Add description of vec_cfuge built-in
804 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
806 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New
808 (BU_FUTURE_MISC_1): Likewise.
809 (BU_FUTURE_MISC_2): Likewise.
810 (BU_FUTURE_MISC_3): Likewise.
811 (__builtin_cfuged): New built-in function definition.
812 * config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant.
814 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
815 a Future Architecture): New subsubsection.
817 2020-05-11 Richard Biener <rguenther@suse.de>
819 PR tree-optimization/95049
820 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition
821 between different constants.
823 2020-05-11 Richard Sandiford <richard.sandiford@arm.com>
825 * tree-pretty-print.c (dump_generic_node): Handle BOOLEAN_TYPEs.
827 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
828 Bill Schmidt <wschmidt@linux.ibm.com>
830 * config/rs6000/altivec.h (vec_gnb): New #define.
831 * config/rs6000/altivec.md (UNSPEC_VGNB): New constant.
833 * config/rs6000/rs6000-builtin.def (BU_FUTURE_OVERLOAD_1): New
835 (BU_FUTURE_OVERLOAD_2): Likewise.
836 (BU_FUTURE_OVERLOAD_3): Likewise.
837 (__builtin_altivec_gnb): New built-in function.
838 (__buiiltin_vec_gnb): New overloaded built-in function.
839 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
840 Define overloaded forms of __builtin_vec_gnb.
841 (rs6000_expand_binop_builtin): Add error checking for 2nd argument
842 of __builtin_vec_gnb.
843 (builtin_function_type): Mark return value and arguments unsigned
844 for FUTURE_BUILTIN_VGNB.
845 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
846 for a Future Architecture): Add description of vec_gnb built-in
849 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
850 Bill Schmidt <wschmidt@linux.ibm.com>
852 * config/rs6000/altivec.h (vec_pdep): New macro implementing new
854 (vec_pext): Likewise.
855 * config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant.
856 (UNSPEC_VPEXTD): Likewise.
859 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vpdepd): New
861 (__builtin_altivec_vpextd): Likewise.
862 * config/rs6000/rs6000-call.c (builtin_function_type): Add
863 handling for FUTURE_BUILTIN_VPDEPD and FUTURE_BUILTIN_VPEXTD
865 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
866 for a Future Architecture): Add description of vec_pdep and
867 vec_pext built-in functions.
869 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
870 Bill Schmidt <wschmidt@linux.ibm.com>
872 * config/rs6000/altivec.h (vec_clzm): New macro.
873 (vec_ctzm): Likewise.
874 * config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant.
875 (UNSPEC_VCTZDM): Likewise.
878 * config/rs6000/rs6000-builtin.def (BU_FUTURE_V_0): New macro.
879 (BU_FUTURE_V_1): Likewise.
880 (BU_FUTURE_V_2): Likewise.
881 (BU_FUTURE_V_3): Likewise.
882 (__builtin_altivec_vclzdm): New builtin definition.
883 (__builtin_altivec_vctzdm): Likewise.
884 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Cause
885 _ARCH_PWR_FUTURE macro to be defined if OPTION_MASK_FUTURE flag is
887 * config/rs6000/rs6000-call.c (builtin_function_type): Set return
888 value and parameter types to be unsigned for VCLZDM and VCTZDM.
889 * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
890 support for TARGET_FUTURE flag.
891 * config/rs6000/rs6000.h (RS6000_BTM_FUTURE): New macro constant.
892 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
893 for a Future Architecture): New subsubsection.
895 2020-05-11 Richard Biener <rguenther@suse.de>
897 PR tree-optimization/94988
898 PR tree-optimization/95025
899 * tree-ssa-loop-im.c (seq_entry): Make a struct, add from.
900 (sm_seq_push_down): Take extra parameter denoting where we
902 (execute_sm_exit): Re-issue sm_other stores in the correct
904 (sm_seq_valid_bb): When always executed, allow sm_other to
905 prevail inbetween sm_ord and record their stored value.
906 (hoist_memory_references): Adjust refs_not_supported propagation
907 and prune sm_other from the end of the ordered sequences.
909 2020-05-11 Felix Yang <felix.yang@huawei.com>
912 * config/aarch64/aarch64.md (mov<mode>):
913 Bitcasts to the equivalent integer mode using gen_lowpart
914 instead of doing FAIL for scalar floating point move.
916 2020-05-11 Alex Coplan <alex.coplan@arm.com>
918 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case
919 to correctly calculate cost for new pattern (*csinv3_uxtw_insn3).
920 * config/aarch64/aarch64.md (*csinv3_utxw_insn1): New.
921 (*csinv3_uxtw_insn2): New.
922 (*csinv3_uxtw_insn3): New.
923 * config/aarch64/iterators.md (neg_not_cs): New.
925 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
928 * config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint
929 instead of "Yv" for AVX alternatives. Add "prefix" attribute.
930 (*mmx_addv2sf3): Ditto.
931 (*mmx_subv2sf3): Ditto.
932 (*mmx_mulv2sf3): Ditto.
933 (*mmx_<code>v2sf3): Ditto.
934 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
936 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
939 * config/i386/i386.c (ix86_vector_mode_supported_p):
940 Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
941 * config/i386/mmx.md (*mov<mode>_internal): Do not set
942 mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.
944 (mmx_addv2sf3): Change operand predicates from
945 nonimmediate_operand to register_mmxmem_operand.
946 (addv2sf3): New expander.
947 (*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand
948 predicates from nonimmediate_operand to register_mmxmem_operand.
949 Enable instruction pattern for TARGET_MMX_WITH_SSE.
951 (mmx_subv2sf3): Change operand predicate from
952 nonimmediate_operand to register_mmxmem_operand.
953 (mmx_subrv2sf3): Ditto.
954 (subv2sf3): New expander.
955 (*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand
956 predicates from nonimmediate_operand to register_mmxmem_operand.
957 Enable instruction pattern for TARGET_MMX_WITH_SSE.
959 (mmx_mulv2sf3): Change operand predicates from
960 nonimmediate_operand to register_mmxmem_operand.
961 (mulv2sf3): New expander.
962 (*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand
963 predicates from nonimmediate_operand to register_mmxmem_operand.
964 Enable instruction pattern for TARGET_MMX_WITH_SSE.
966 (mmx_<code>v2sf3): Change operand predicates from
967 nonimmediate_operand to register_mmxmem_operand.
968 (<code>v2sf3): New expander.
969 (*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand
970 predicates from nonimmediate_operand to register_mmxmem_operand.
971 Enable instruction pattern for TARGET_MMX_WITH_SSE.
972 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
974 2020-05-11 Martin Liska <mliska@suse.cz>
977 * common.opt: Fix typo in option description.
979 2020-05-11 Martin Liska <mliska@suse.cz>
981 PR gcov-profile/94928
982 * gcov-io.h: Add caveat about coverage format parsing and
983 possible outdated documentation.
985 2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com>
987 PR tree-optimization/83403
988 * tree-affine.c (expr_to_aff_combination): Replace SSA_NAME with
989 determine_value_range, Add fold conversion of MULT_EXPR, fix the
992 2020-05-10 Gerald Pfeifer <gerald@pfeifer.com>
994 * config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and
995 __ILP32__ for 32-bit targets.
997 2020-05-09 Eric Botcazou <ebotcazou@adacore.com>
999 * tree.h (expr_align): Delete.
1000 * tree.c (expr_align): Likewise.
1002 2020-05-09 Hans-Peter Nilsson <hp@axis.com>
1004 * resource.c (init_resource_info): Filter-out TARGET_FLAGS_REGNUM
1005 from end_of_function_needs.
1007 * config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
1008 * config/cris/t-linux, config/cris/linux.h, config/cris/linux.opt:
1010 * config/cris/t-elfmulti: Remove crisv32 multilib.
1011 * config/cris: Remove shared-library and CRIS v32 support.
1013 Move trivially from cc0 to reg:CC model, removing most optimizations.
1014 * config/cris/cris.md: Remove all side-effect patterns and their
1015 splitters. Remove most peepholes. Add clobbers of CRIS_CC0_REGNUM
1016 to all but post-reload control-flow and movem insns. Remove
1017 constraints on all modified expanders. Remove obsoleted cc0-related
1019 (attr "cc"): Remove alternative "rev".
1020 (mode_iterator BWDD, DI_, SI_): New.
1021 (mode_attr sCC_destc, cmp_op1c, cmp_op2c): New.
1022 ("tst<mode>"): Remove; fold as "M" alternative into compare insn.
1023 ("mstep_shift", "mstep_mul"): Remove patterns.
1024 ("s<rcond>", "s<ocond>", "s<ncond>"): Anonymize.
1025 * config/cris/cris.c: Change all non-condition-code,
1026 non-control-flow emitted insns to add a parallel with clobber of
1027 CRIS_CC0_REGNUM, mostly by changing from gen_rtx_SET with
1028 emit_insn to use of emit_move_insn, gen_add2_insn or
1029 cris_emit_insn, as convenient.
1030 (cris_reg_overlap_mentioned_p)
1031 (cris_normal_notice_update_cc, cris_notice_update_cc): Remove.
1032 (cris_movem_load_rest_p): Don't assume all elements in a
1034 (cris_store_multiple_op_p): Ditto.
1035 (cris_emit_insn): New function.
1036 * cris/cris-protos.h (cris_emit_insn): Declare.
1039 * config/cris/cris.md (zcond): New code_iterator.
1040 ("*cbranch<mode>4_btstq<CC>"): New insn_and_split.
1042 * config/cris/cris.c (TARGET_FLAGS_REGNUM): Define.
1044 * config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.
1046 * config/cris/cris.md ("movsi"): For memory destination
1047 post-reload, generate clobberless variant. Similarly for a
1048 zero-source post-reload.
1049 ("*mov_tomem<mode>_split"): New split.
1050 ("*mov_tomem<mode>"): New insn.
1051 ("enabled", mov_tomem_enabled): Define and use to exclude "x" ->
1052 "Q>m" for less-than-SImode.
1053 ("*mov_fromzero<mode>_split"): New split.
1054 ("*mov_fromzero<mode>"): New insn.
1056 Prepare for cmpelim pass to eliminate redundant compare insns.
1057 * config/cris/cris-modes.def: New file.
1058 * config/cris/cris-protos.h (cris_select_cc_mode): Declare.
1059 (cris_notice_update_cc): Remove left-over declaration.
1060 * config/cris/cris.c (TARGET_CC_MODES_COMPATIBLE): Define.
1061 (cris_select_cc_mode, cris_cc_modes_compatible): New functions.
1062 * config/cris/cris.h (SELECT_CC_MODE): Define.
1063 * config/cris/cris.md (NZSET, NZUSE, NZVCSET, NZVCUSE): New
1065 (cond): New code_iterator.
1066 (nzcond): Replacement for incorrect ncond. All callers changed.
1067 (nzvccond): Replacement for ocond. All callers changed.
1068 (rnzcond): Replacement for rcond. All callers changed.
1069 (xCC): New code_attr.
1070 (cmp_op1c, cmp_op0c): Renumber from cmp_op1c and cmp_op2c. All
1072 ("*cmpdi<NZVCSET:mode>"): Rename from "*cmpdi". Replace
1073 CCmode with iteration over NZVCSET.
1074 ("*cmp_ext<BW:mode><NZVCSET:mode>"): Similarly; rename from
1076 ("*cmpsi<NZVCSET:mode>"): Similarly, from "*cmpsi".
1077 ("*cmp<BW:mode><NZVCSET:mode>"): Similarly from "*cmp<mode>".
1078 ("*btst<mode>"): Similarly, from "*btst".
1079 ("*cbranch<mode><code>4"): Rename from "*cbranch<mode>4",
1080 iterating over cond instead of matching the comparison with
1081 ordered_comparison_operator.
1082 ("*cbranch<mode>4_btstq<CC>"): Correct label operand number.
1083 ("b<zcond:code><mode>"): Rename from "b<ncond:code>", iterating
1085 ("b<nzvccond:code><mode>"): Similarly from "b<ocond:code>", over
1086 NZVCUSE. Remove FIXME.
1087 ("*b<nzcond:code>_reversed<mode>"): Similarly from
1088 "*b<ncond:code>_reversed", over NZUSE.
1089 ("*b<nzvccond:code>_reversed<mode>"): Similarly from
1090 "*b<ocond:code>_reversed", over NZVCUSE. Remove FIXME.
1091 ("b<rnzcond:code><mode>"): Similarly from "b<rcond:code>",
1092 over NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
1093 depending on CC_NZmode vs. CCmode. Remove FIXME.
1094 ("*b<rnzcond:code>_reversed<mode>"): Similarly from
1095 "*b<rcond:code>_reversed", over NZUSE.
1096 ("*cstore<mode><code>4"): Rename from "*cstore<mode>4",
1097 iterating over cond instead of matching the comparison with
1098 ordered_comparison_operator.
1099 ("*s<nzcond:code><mode>"): Rename from "*s<ncond:code>",
1100 iterating over NZUSE.
1101 ("*s<rnzcond:code><mode>"): Similar from "*s<rcond:code>", over
1102 NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
1103 depending on CC_NZmode vs. CCmode.
1104 ("*s<nzvccond:code><mode>"): Simlar from "*s<ocond:code>", over
1105 NZVCUSE. Remove FIXME.
1106 ("cc"): Comment on new use.
1107 ("cc_enabled"): New attribute.
1108 ("enabled"): Make default fall back to cc_enabled.
1109 ("setnz", "ccnz", "setnzvc", "ccnzvc", "setcc", "cccc"): New
1110 default_subst_attrs.
1111 ("setnz_subst", "setnzvc_subst", "setcc_subst"): New default_subst.
1112 ("*movsi_internal<setcc><setnz><setnzvc>"): Rename from
1113 "*movsi_internal". Correct contents of, and rename attribute
1114 "cc" to "cc<cccc><ccnz><ccnzvc>".
1115 ("anz", "anzvc", "acc"): New define_subst_attrs.
1116 ("<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>"): Rename from
1117 "movhi". Rename "cc" attribute to "cc<cccc><ccnz><ccnzvc>".
1118 ("<acc><anz><anzvc>movqi<setcc><setnz><setnzvc>"): Similar from
1119 "movqi". Correct contents of, and rename "cc" attribute to
1120 "cc<cccc><ccnz><ccnzvc>".
1121 ("*b<zcond:code><mode>"): Rename from "b<zcond:code><mode>".
1122 ("*b<nzvccond:code><mode>"): Rename from "b<nzvccond:code><mode>".
1123 ("*b<rnzcond:code><mode>"): Rename from "*b<rnzcond:code><mode>".
1124 ("<acc><anz><anzvc>extend<mode>si2<setcc><setnz><setnzvc>"):
1125 Rename from "extend<mode>si2".
1126 ("<acc><anz><anzvc>zero_extend<mode>si2<setcc><setnz><setnzvc>"):
1127 Similar, from "zero_extend<mode>si2".
1128 ("*adddi3<setnz>"): Rename from "*adddi3".
1129 ("*subdi3<setnz>"): Similarly from "*subdi3".
1130 ("*addsi3<setnz>"): Similarly from "*addsi3".
1131 ("*subsi3<setnz>"): Similarly from "*subsi3".
1132 ("*addhi3<setnz>"): Similarly from "*addhi3" and decorate the
1133 "cc" attribute to "cc<ccnz>".
1134 ("*addqi3<setnz>"): Similarly from "*addqi3".
1135 ("*sub<mode>3<setnz>"): Similarly from "*sub<mode>3".
1136 ("*expanded_andsi<setcc><setnz><setnzvc>"): Rename from
1138 ("*iorsi3<setcc><setnz><setnzvc>"): Similar from "*iorsi3".
1139 Decorate "cc" attribute to make "cc<cccc><ccnz><ccnzvc>".
1140 ("*iorhi3<setcc><setnz><setnzvc>"): Similar from "*iorhi3".
1141 ("*iorqi3<setcc><setnz><setnzvc>"): Similar from "*iorqi3".
1142 ("*expanded_andhi<setcc><setnz><setnzvc>"): Similar from
1143 "*expanded_andhi". Add quick cc-setting alternative for 0..31.
1144 ("*andqi3<setcc><setnz><setnzvc>"): Similar from "*andqi3".
1145 ("<acc><anz><anzvc>xorsi3<setcc><setnz><setnzvc>"): Rename
1147 ("<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"): Rename
1149 ("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename
1151 ("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename
1153 ("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename
1155 ("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".
1157 * config/cris/cris-modes.def (CC_ZnN): New CC_MODE.
1158 * config/cris/cris.c (cris_rtx_costs): Handle pre-split bit-test
1159 * config/cris/cris.md (ZnNNZSET, ZnNNZUSE): New mode_iterators.
1160 (znnCC, rznnCC): New code_attrs.
1161 ("*btst<mode>"): Iterator over ZnNNZSET instead of NZVCSET. Remove
1162 obseolete comment. Add belt-and-suspenders mode-test to condition.
1163 Add fixme regarding remaining matched-but-not-generated case.
1164 ("*cbranch<mode>4_btstrq1_<CC>"): New insn_and_split.
1165 ("*cbranch<mode>4_btstqb0_<CC>"): Rename from
1166 "*cbranch<mode>4_btstq<CC>". Split to CC_NZ instead of CC.
1167 ("*b<zcond:code><mode>"): Iterate over ZnNNZUSE instead of NZUSE.
1168 Handle output of CC_ZnNmode.
1169 ("*b<nzcond:code>_reversed<mode>"): Ditto.
1171 * config/cris/cris.c (cris_select_cc_mode): Return CC_NZmode for
1172 NEG too. Correct comment.
1173 * config/cris/cris.md ("<anz>neg<mode>2<setnz>"): Rename from
1176 2020-05-08 Vladimir Makarov <vmakarov@redhat.com>
1178 * ira-color.c (update_costs_from_allocno): Remove
1179 conflict_cost_update_p argument. Propagate costs only along
1180 threads. Always do conflict cost update. Add printing debugging
1182 (update_costs_from_copies): Add printing debugging info.
1183 (restore_costs_from_copies): Ditto.
1184 (assign_hard_reg): Improve debug info.
1185 (push_only_colorable): Ditto. Call update_costs_from_prefs.
1186 (color_allocnos): Remove update_costs_from_prefs.
1188 2020-05-08 Richard Biener <rguenther@suse.de>
1190 * tree-vectorizer.h (vec_info::slp_loads): New.
1191 (vect_optimize_slp): Declare.
1192 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Do
1193 nothing when there are no loads.
1194 (vect_gather_slp_loads): Gather loads into a vector.
1195 (vect_supported_load_permutation_p): Remove.
1196 (vect_analyze_slp_instance): Do not verify permutation
1198 (vect_analyze_slp): Optimize permutations of reductions
1199 after all SLP instances have been gathered and gather
1201 (vect_optimize_slp): New function split out from
1202 vect_supported_load_permutation_p. Elide some permutations.
1203 (vect_slp_analyze_bb_1): Call vect_optimize_slp.
1204 * tree-vect-loop.c (vect_analyze_loop_2): Likewise.
1205 * tree-vect-stmts.c (vectorizable_load): Check whether
1206 the load can be permuted. When generating code assert we can.
1208 2020-05-08 Richard Biener <rguenther@suse.de>
1210 * tree-ssa-sccvn.c (rpo_avail): Change type to
1211 eliminate_dom_walker *.
1212 (eliminate_with_rpo_vn): Adjust rpo_avail to make vn_valueize
1213 use the DOM walker availability.
1214 (vn_reference_fold_indirect): Use get_addr_base_and_unit_offset_1
1215 with vn_valueize as valueization callback.
1216 (vn_reference_maybe_forwprop_address): Likewise.
1217 * tree-dfa.c (get_addr_base_and_unit_offset_1): Also valueize
1218 array_ref_low_bound.
1220 2020-05-08 Jakub Jelinek <jakub@redhat.com>
1222 PR tree-optimization/94786
1223 * match.pd (A ^ ((A ^ B) & -(C cmp D)) -> (C cmp D) ? B : A): New
1227 * config/i386/i386.md (peephole2 after *add<mode>3_cc_overflow_1): New
1231 * tree.c (get_narrower): Reuse the op temporary instead of
1234 PR tree-optimization/94783
1235 * match.pd ((X + (X >> (prec - 1))) ^ (X >> (prec - 1)) to abs (X)):
1238 PR tree-optimization/94956
1239 * match.pd (FFS): Optimize __builtin_ffs* of non-zero argument into
1240 __builtin_ctz* + 1 if direct IFN_CTZ is supported.
1242 PR tree-optimization/94913
1243 * match.pd (A - B + -1 >= A to B >= A): New simplification.
1244 (A - B > A to A < B): Don't test TYPE_OVERFLOW_WRAPS which is always
1245 true for TYPE_UNSIGNED integral types.
1248 PR rtl-optimization/94516
1249 * rtl.h (remove_reg_equal_equiv_notes): Add a bool argument defaulted
1251 * rtlanal.c (remove_reg_equal_equiv_notes): Add no_rescan argument.
1252 Call df_notes_rescan if that argument is not true and returning true.
1253 * combine.c (adjust_for_new_dest): Pass true as second argument to
1254 remove_reg_equal_equiv_notes.
1255 * postreload.c (reload_combine_recognize_pattern): Don't call
1258 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1260 * config/rs6000/rs6000.md (*setnbc_<un>signed_<GPR:mode>): New
1262 (*setnbcr_<un>signed_<GPR:mode>): New define_insn.
1263 (*neg_eq_<mode>): Avoid for TARGET_FUTURE; add missing && 1.
1264 (*neg_ne_<mode>): Likewise.
1266 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1268 * config/rs6000/rs6000.md (setbc_<un>signed_<GPR:mode>): New
1270 (*setbcr_<un>signed_<GPR:mode>): Likewise.
1271 (cstore<mode>4): Use setbc[r] if available.
1272 (<code><GPR:mode><GPR2:mode>2_isel): Avoid for TARGET_FUTURE.
1273 (eq<mode>3): Use setbc for TARGET_FUTURE.
1274 (*eq<mode>3): Avoid for TARGET_FUTURE.
1275 (ne<mode>3): Replace :P with :GPR; use setbc for TARGET_FUTURE;
1276 else for non-Pmode, use gen_eq and gen_xor.
1277 (*ne<mode>3): Avoid for TARGET_FUTURE.
1278 (*eqsi3_ext<mode>): Avoid for TARGET_FUTURE; fix missing && 1.
1280 2020-05-07 Jeff Law <law@redhat.com>
1282 * config/h8300/h8300.md: Move expanders and patterns into
1283 files based on functionality.
1284 * config/h8300/addsub.md: New file.
1285 * config/h8300/bitfield.md: New file
1286 * config/h8300/combiner.md: New file
1287 * config/h8300/divmod.md: New file
1288 * config/h8300/extensions.md: New file
1289 * config/h8300/jumpcall.md: New file
1290 * config/h8300/logical.md: New file
1291 * config/h8300/movepush.md: New file
1292 * config/h8300/multiply.md: New file
1293 * config/h8300/other.md: New file
1294 * config/h8300/proepi.md: New file
1295 * config/h8300/shiftrotate.md: New file
1296 * config/h8300/testcompare.md: New file
1298 * config/h8300/h8300.md (adds/subs splitters): Merge into single
1300 (negation expanders and patterns): Simplify and combine using
1302 (one_cmpl expanders and patterns): Likewise.
1303 (tablejump, indirect_jump patterns ): Likewise.
1304 (shift and rotate expanders and patterns): Likewise.
1305 (absolute value expander and pattern): Drop expander, rename pattern
1307 (peephole2 patterns): Move into...
1308 * config/h8300/peepholes.md: New file.
1310 * config/h8300/constraints.md (L and N): Simplify now that we're not
1311 longer supporting the original H8/300 chip.
1312 * config/h8300/elf.h (LINK_SPEC): Likewise. Default to H8/300H.
1313 * config/h8300/h8300.c (shift_alg_qi): Drop H8/300 support.
1314 (shift_alg_hi, shift_alg_si): Similarly.
1315 (h8300_option_overrides): Similarly. Default to H8/300H. If
1316 compiling for H8/S, then turn off H8/300H. Do not update the
1317 shift_alg tables for H8/300 port.
1318 (h8300_emit_stack_adjustment): Remove support for H8/300. Simplify
1320 (push, split_adds_subs, h8300_rtx_costs): Likewise.
1321 (h8300_print_operand, compute_mov_length): Likewise.
1322 (output_plussi, compute_plussi_length): Likewise.
1323 (compute_plussi_cc, output_logical_op): Likewise.
1324 (compute_logical_op_length, compute_logical_op_cc): Likewise.
1325 (get_shift_alg, h8300_shift_needs_scratch): Likewise.
1326 (output_a_shift, compute_a_shift_length): Likewise.
1327 (output_a_rotate, compute_a_rotate_length): Likewise.
1328 (output_simode_bld, h8300_hard_regno_mode_ok): Likewise.
1329 (h8300_modes_tieable_p, h8300_return_in_memory): Likewise.
1330 * config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Likewise.
1331 (attr_cpu, TARGET_H8300): Remove.
1332 (TARGET_DEFAULT): Update.
1333 (UNITS_PER_WORD, PARM_BOUNDARY): Simplify where possible.
1334 (BIGGEST_ALIGNMENT, STACK_BOUNDARY): Likewise.
1335 (CONSTANT_ADDRESS_P, MOVE_MAX, Pmode): Likewise.
1336 (SIZE_TYPE, POINTER_SIZE, ASM_WORD_OP): Likewise.
1337 * config/h8300/h8300.md: Simplify patterns throughout.
1338 * config/h8300/t-h8300: Update multilib configuration.
1340 * config/h8300/h8300.h (LINK_SPEC): Remove.
1341 (USER_LABEL_PREFIX): Likewise.
1343 * config/h8300/h8300.c (h8300_asm_named_section): Remove.
1344 (h8300_option_override): Remove remnants of COFF support.
1346 2020-05-07 Alan Modra <amodra@gmail.com>
1348 * tree-ssa-reassoc.c (optimize_range_tests_to_bit_test): Replace
1349 set_rtx_cost with set_src_cost.
1350 * tree-switch-conversion.c (bit_test_cluster::emit): Likewise.
1352 2020-05-07 Kewen Lin <linkw@gcc.gnu.org>
1354 * tree-vect-stmts.c (vectorizable_load): Check alignment to avoid
1355 redundant half vector handlings for no peeling gaps.
1357 2020-05-07 Giuliano Belinassi <giuliano.belinassi@usp.br>
1359 * tree-ssa-operands.c (operands_scanner): New class.
1360 (operands_bitmap_obstack): Remove.
1361 (n_initialized): Remove.
1362 (build_uses): Move to operands_scanner class.
1363 (build_vuse): Same as above.
1364 (build_vdef): Same as above.
1365 (verify_ssa_operands): Same as above.
1366 (finalize_ssa_uses): Same as above.
1367 (cleanup_build_arrays): Same as above.
1368 (finalize_ssa_stmt_operands): Same as above.
1369 (start_ssa_stmt_operands): Same as above.
1370 (append_use): Same as above.
1371 (append_vdef): Same as above.
1372 (add_virtual_operand): Same as above.
1373 (add_stmt_operand): Same as above.
1374 (get_mem_ref_operands): Same as above.
1375 (get_tmr_operands): Same as above.
1376 (maybe_add_call_vops): Same as above.
1377 (get_asm_stmt_operands): Same as above.
1378 (get_expr_operands): Same as above.
1379 (parse_ssa_operands): Same as above.
1380 (finalize_ssa_defs): Same as above.
1381 (build_ssa_operands): Same as above, plus create a C-like wrapper.
1382 (update_stmt_operands): Create an instance of operands_scanner.
1384 2020-05-07 Richard Biener <rguenther@suse.de>
1387 * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use
1388 DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible.
1389 (refered_from_nonlocal_var): Likewise.
1390 (ipa_pta_execute): Likewise.
1392 2020-05-07 Erick Ochoa <erick.ochoa@theobroma-systems.com>
1394 * gcc/tree-ssa-struct-alias.c: Fix comments
1396 2020-05-07 Martin Liska <mliska@suse.cz>
1398 * doc/invoke.texi: Fix 2 optindex entries.
1400 2020-05-07 Richard Biener <rguenther@suse.de>
1403 * tree-core.h (tree_decl_common::gimple_reg_flag): Rename ...
1404 (tree_decl_common::not_gimple_reg_flag): ... to this.
1405 * tree.h (DECL_GIMPLE_REG_P): Rename ...
1406 (DECL_NOT_GIMPLE_REG_P): ... to this.
1407 * gimple-expr.c (copy_var_decl): Copy DECL_NOT_GIMPLE_REG_P.
1408 (create_tmp_reg): Simplify.
1409 (create_tmp_reg_fn): Likewise.
1410 (is_gimple_reg): Check DECL_NOT_GIMPLE_REG_P for all regs.
1411 * gimplify.c (create_tmp_from_val): Simplify.
1412 (gimplify_bind_expr): Likewise.
1413 (gimplify_compound_literal_expr): Likewise.
1414 (gimplify_function_tree): Likewise.
1415 (prepare_gimple_addressable): Set DECL_NOT_GIMPLE_REG_P.
1416 * asan.c (create_odr_indicator): Do not clear DECL_GIMPLE_REG_P.
1417 (asan_add_global): Copy it.
1418 * cgraphunit.c (cgraph_node::expand_thunk): Force args
1420 * function.c (gimplify_parameters): Copy
1421 DECL_NOT_GIMPLE_REG_P.
1422 * ipa-param-manipulation.c
1423 (ipa_param_body_adjustments::common_initialization): Simplify.
1424 (ipa_param_body_adjustments::reset_debug_stmts): Copy
1425 DECL_NOT_GIMPLE_REG_P.
1426 * omp-low.c (lower_omp_for_scan): Do not set DECL_GIMPLE_REG_P.
1427 * sanopt.c (sanitize_rewrite_addressable_params): Likewise.
1428 * tree-cfg.c (make_blocks_1): Simplify.
1429 (verify_address): Do not verify DECL_GIMPLE_REG_P setting.
1430 * tree-eh.c (lower_eh_constructs_2): Simplify.
1431 * tree-inline.c (declare_return_variable): Adjust and
1433 (copy_decl_to_var): Copy DECL_NOT_GIMPLE_REG_P.
1434 (copy_result_decl_to_var): Likewise.
1435 * tree-into-ssa.c (pass_build_ssa::execute): Adjust comment.
1436 * tree-nested.c (create_tmp_var_for): Simplify.
1437 * tree-parloops.c (separate_decls_in_region_name): Copy
1438 DECL_NOT_GIMPLE_REG_P.
1439 * tree-sra.c (create_access_replacement): Adjust and
1440 generalize partial def support.
1441 * tree-ssa-forwprop.c (pass_forwprop::execute): Set
1442 DECL_NOT_GIMPLE_REG_P on decls we introduce partial defs on.
1443 * tree-ssa.c (maybe_optimize_var): Handle clearing of
1444 TREE_ADDRESSABLE and setting/clearing DECL_NOT_GIMPLE_REG_P
1446 * lto-streamer-out.c (hash_tree): Hash DECL_NOT_GIMPLE_REG_P.
1447 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Stream
1448 DECL_NOT_GIMPLE_REG_P.
1449 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
1450 * cfgexpand.c (avoid_type_punning_on_regs): New.
1451 (discover_nonconstant_array_refs): Call
1452 avoid_type_punning_on_regs to avoid unsupported mode punning.
1454 2020-05-07 Alex Coplan <alex.coplan@arm.com>
1456 * config/arm/arm.c (arm_add_stmt_cost): Fix declaration, remove class
1459 2020-05-07 Richard Biener <rguenther@suse.de>
1461 PR tree-optimization/57359
1462 * tree-ssa-loop-im.c (im_mem_ref::indep_loop): Remove.
1463 (in_mem_ref::dep_loop): Repurpose.
1464 (LOOP_DEP_BIT): Remove.
1465 (enum dep_kind): New.
1466 (enum dep_state): Likewise.
1467 (record_loop_dependence): New function to populate the
1469 (query_loop_dependence): New function to query the dependence
1471 (memory_accesses::refs_in_loop): Rename to ...
1472 (memory_accesses::refs_loaded_in_loop): ... this and change to
1474 (outermost_indep_loop): Adjust.
1475 (mem_ref_alloc): Likewise.
1476 (gather_mem_refs_stmt): Likewise.
1477 (mem_refs_may_alias_p): Add tbaa_p parameter and pass it down.
1478 (struct sm_aux): New.
1479 (execute_sm): Split code generation on exits, record state
1481 (enum sm_kind): New.
1482 (execute_sm_exit): Exit code generation part.
1483 (sm_seq_push_down): Helper for sm_seq_valid_bb performing
1484 dependence checking on stores reached from exits.
1485 (sm_seq_valid_bb): New function gathering SM stores on exits.
1486 (hoist_memory_references): Re-implement.
1487 (refs_independent_p): Add tbaa_p parameter and pass it down.
1488 (record_dep_loop): Remove.
1489 (ref_indep_loop_p_1): Fold into ...
1490 (ref_indep_loop_p): ... this and generalize for three kinds
1491 of dependence queries.
1492 (can_sm_ref_p): Adjust according to hoist_memory_references
1494 (store_motion_loop): Don't do anything if the set of SM
1495 candidates is empty.
1496 (tree_ssa_lim_initialize): Adjust.
1497 (tree_ssa_lim_finalize): Likewise.
1499 2020-05-07 Eric Botcazou <ebotcazou@adacore.com>
1500 Pierre-Marie de Rodat <derodat@adacore.com>
1502 * dwarf2out.c (add_data_member_location_attribute): Take into account
1503 the variant part offset in the computation of the data bit offset.
1504 (add_bit_offset_attribute): Remove CTX parameter. Pass a new context
1505 in the call to field_byte_offset.
1506 (gen_field_die): Adjust call to add_bit_offset_attribute and remove
1507 confusing assertion.
1508 (analyze_variant_discr): Deal with boolean subtypes.
1510 2020-05-07 Martin Liska <mliska@suse.cz>
1512 * lto-wrapper.c: Split arguments of MAKE environment
1515 2020-05-07 Uroš Bizjak <ubizjak@gmail.com>
1517 * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use
1518 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
1519 fenv_var and new_fenv_var.
1521 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1524 * config/i386/subst.md (store_mask_constraint, store_mask_predicate):
1526 (avx512dq_vextract<shuffletype>64x2_1_maskm,
1527 avx512f_vextract<shuffletype>32x4_1_maskm,
1528 vec_extract_lo_<mode>_maskm, vec_extract_hi_<mode>_maskm): Remove.
1529 (<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>): Split
1531 (*avx512dq_vextract<shuffletype>64x2_1,
1532 avx512dq_vextract<shuffletype>64x2_1_mask): ... these new
1533 define_insns. Even in the masked variant allow memory output but in
1534 that case use 0 rather than 0C constraint on the source of masked-out
1536 (<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>): Split
1538 (*avx512f_vextract<shuffletype>32x4_1,
1539 avx512f_vextract<shuffletype>32x4_1_mask): ... these new define_insns.
1540 Even in the masked variant allow memory output but in that case use
1541 0 rather than 0C constraint on the source of masked-out elts.
1542 (vec_extract_lo_<mode><mask_name>): Split into ...
1543 (vec_extract_lo_<mode>, vec_extract_lo_<mode>_mask): ... these new
1544 define_insns. Even in the masked variant allow memory output but in
1545 that case use 0 rather than 0C constraint on the source of masked-out
1547 (vec_extract_hi_<mode><mask_name>): Split into ...
1548 (vec_extract_hi_<mode>, vec_extract_hi_<mode>_mask): ... these new
1549 define_insns. Even in the masked variant allow memory output but in
1550 that case use 0 rather than 0C constraint on the source of masked-out
1553 2020-05-06 qing zhao <qing.zhao@oracle.com>
1556 * common.opt: Add -flarge-source-files.
1557 * doc/invoke.texi: Document it.
1558 * toplev.c (process_options): set line_table->default_range_bits
1559 to 0 when flag_large_source_files is true.
1561 2020-05-06 Uroš Bizjak <ubizjak@gmail.com>
1564 * config/i386/predicates.md (add_comparison_operator): New predicate.
1565 * config/i386/i386.md (compare->add splitter): New splitters.
1567 2020-05-06 Richard Biener <rguenther@suse.de>
1569 * tree-vectorizer.h (vect_transform_slp_perm_load): Adjust.
1570 * tree-vect-data-refs.c (vect_slp_analyze_node_dependences):
1571 Remove slp_instance parameter, just iterate over all scalar stmts.
1572 (vect_slp_analyze_instance_dependence): Adjust and likewise.
1573 * tree-vect-slp.c (vect_bb_slp_scalar_cost): Remove unused BB
1575 (vect_schedule_slp): Just iterate over all scalar stmts.
1576 (vect_supported_load_permutation_p): Adjust.
1577 (vect_transform_slp_perm_load): Remove slp_instance parameter,
1578 instead use the number of lanes in the node as group size.
1579 * tree-vect-stmts.c (vect_model_load_cost): Get vectorization
1580 factor instead of slp_instance as parameter.
1581 (vectorizable_load): Adjust.
1583 2020-05-06 Andreas Schwab <schwab@suse.de>
1585 * config/aarch64/driver-aarch64.c: Include "aarch64-protos.h".
1586 (aarch64_get_extension_string_for_isa_flags): Don't declare.
1588 2020-05-06 Richard Biener <rguenther@suse.de>
1591 * cfgloopmanip.c (create_preheader): Require non-complex
1592 preheader edge for CP_SIMPLE_PREHEADERS.
1594 2020-05-06 Richard Biener <rguenther@suse.de>
1596 PR tree-optimization/94963
1597 * tree-ssa-loop-im.c (execute_sm_if_changed): Remove
1598 no-warning marking of the conditional store.
1599 (execute_sm): Instead mark the uninitialized state
1600 on loop entry to be not warned about.
1602 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1604 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET,
1605 OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros.
1606 * config.gcc: Add tsxldtrkintrin.h to extra_headers.
1607 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1609 * config/i386/i386-builtin.def: Add new builtins.
1610 * config/i386/i386-c.c (ix86_target_macros_internal): Define
1612 * config/i386/i386-options.c (ix86_target_string): Add
1614 (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk.
1615 * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P):
1617 * config/i386/i386.md (define_c_enum "unspec"): Add
1618 UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK.
1619 (TSXLDTRK): New define_int_iterator.
1620 ("<tsxldtrk>"): New define_insn.
1621 * config/i386/i386.opt: Add -mtsxldtrk.
1622 * config/i386/immintrin.h: Include tsxldtrkintrin.h.
1623 * config/i386/tsxldtrkintrin.h: New.
1624 * doc/invoke.texi: Document -mtsxldtrk.
1626 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1628 PR tree-optimization/94921
1629 * match.pd (~(~X - Y) -> X + Y, ~(~X + Y) -> X - Y): New
1632 2020-05-06 Richard Biener <rguenther@suse.de>
1634 PR tree-optimization/94965
1635 * tree-vect-stmts.c (vectorizable_load): Fix typo.
1637 2020-05-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1639 * doc/install.texi: Replace Sun with Solaris as appropriate.
1640 (Tools/packages necessary for building GCC, Perl version between
1641 5.6.1 and 5.6.24): Remove Solaris 8 reference.
1642 (Installing GCC: Binaries, Solaris 2 (SPARC, Intel)): Remove
1644 (Specific, i?86-*-solaris2*): Update version references for
1645 Solaris 11.3 and later. Remove gas 2.26 caveat.
1646 (Specific, *-*-solaris2*): Update version references for
1647 Solaris 11.3 and later. Remove boehm-gc reference.
1648 Document GMP, MPFR caveats on Solaris 11.3.
1649 (Specific, sparc-sun-solaris2*): Update Solaris 9 references.
1650 (Specific, sparc64-*-solaris2*): Likewise.
1651 Document --build requirement.
1653 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1656 * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use
1657 TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags.
1659 PR rtl-optimization/94873
1660 * combine.c (combine_instructions): Don't optimize using REG_EQUAL
1661 note if SET_SRC (set) has side-effects.
1663 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1664 Wei Xiao <wei3.xiao@intel.com>
1666 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
1667 OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
1668 (ix86_handle_option): Handle -mserialize.
1669 * config.gcc (serializeintrin.h): New header file.
1670 * config/i386/cpuid.h (bit_SERIALIZE): New bit.
1671 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1673 * config/i386/i386-builtin.def: Add new builtin.
1674 * config/i386/i386-c.c (__SERIALIZE__): New macro.
1675 * config/i386/i386-options.c (ix86_target_opts_isa2_opts):
1677 * (ix86_valid_target_attribute_inner_p): Add target attribute
1679 * config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
1681 * config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
1682 (serialize): New define_insn.
1683 * config/i386/i386.opt (mserialize): New option
1684 * config/i386/immintrin.h: Include serailizeintrin.h.
1685 * config/i386/serializeintrin.h: New header file.
1686 * doc/invoke.texi: Add documents for -mserialize.
1688 2020-05-06 Richard Biener <rguenther@suse.de>
1690 * tree-cfg.c (verify_gimple_assign_unary): Adjust integer
1691 to/from pointer conversion checking.
1693 2020-05-05 Michael Meissner <meissner@linux.ibm.com>
1695 * config/rs6000/rs6000-builtin.def: Delete changes meant for a
1697 * config/rs6000/rs6000-c.c: Likewise.
1698 * config/rs6000/rs6000-call.c: Likewise.
1699 * config/rs6000/rs6000.c: Likewise.
1701 2020-05-05 Sebastian Huber <sebastian.huber@embedded-brains.de>
1703 * config/rtems.h (RTEMS_STARTFILE_SPEC): Define if undefined.
1704 (RTEMS_ENDFILE_SPEC): Likewise.
1705 (STARTFILE_SPEC): Update comment. Add RTEMS_STARTFILE_SPEC.
1706 (ENDFILE_SPEC): Add RTEMS_ENDFILE_SPEC.
1707 (LIB_SPECS): Support -nodefaultlibs option.
1708 * config/or1k/rtems.h (RTEMS_STARTFILE_SPEC): Define.
1709 (RTEMS_ENDFILE_SPEC): Likewise.
1710 * config/rs6000/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
1711 (RTEMS_ENDFILE_SPEC): Likewise.
1712 * config/v850/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
1713 (RTEMS_ENDFILE_SPEC): Likewise.
1715 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1717 * config/pru/pru.c (pru_hard_regno_call_part_clobbered): Remove.
1718 (TARGET_HARD_REGNO_CALL_PART_CLOBBERED): Remove.
1720 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1722 * config/pru/pru.h: Mark R3.w0 as caller saved.
1724 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1726 * config/pru/pru.c (pru_emit_doloop): Use new gen_doloop_end_internal
1727 and gen_doloop_begin_internal.
1728 (pru_reorg_loop): Use gen_pruloop with mode.
1729 * config/pru/pru.md: Use new @insn syntax.
1731 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1733 * config/pru/pru.c (pru_print_operand): Fix fall through comment.
1735 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
1737 * config/i386/i386.md (fixuns_trunc<mode>si2): Use
1738 "clobber (scratch:M)" instad of "clobber (match_scratch:M N)".
1739 (addqi3_cconly_overflow): Ditto.
1740 (umulv<mode>4): Ditto.
1741 (<s>mul<mode>3_highpart): Ditto.
1742 (tls_global_dynamic_32): Ditto.
1743 (tls_local_dynamic_base_32): Ditto.
1750 (*adddi_4): Remove "m" constraint from scratch operand.
1751 (*add<mode>_4): Ditto.
1753 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1755 PR rtl-optimization/94516
1756 * postreload.c (reload_cse_simplify): When replacing sp = sp + const
1757 with sp = reg, add REG_EQUAL note with sp + const.
1758 * combine-stack-adj.c (try_apply_stack_adjustment): Change return
1759 type from int to bool. Add LIVE and OTHER_INSN arguments. Undo
1760 postreload sp = sp + const to sp = reg optimization if needed and
1762 (combine_stack_adjustments_for_block): Add LIVE argument. Handle
1763 reg = sp insn with sp + const REG_EQUAL note. Adjust
1764 try_apply_stack_adjustment caller, call
1765 df_simulate_initialize_forwards and df_simulate_one_insn_forwards.
1766 (combine_stack_adjustments): Allocate and free LIVE bitmap,
1767 adjust combine_stack_adjustments_for_block caller.
1769 2020-05-05 Martin Liska <mliska@suse.cz>
1771 PR gcov-profile/93623
1772 * tree-cfg.c (stmt_can_terminate_bb_p): Update comment to reflect
1775 2020-05-05 Martin Liska <mliska@suse.cz>
1777 * opt-functions.awk (opt_args_non_empty): New function.
1778 * opt-read.awk: Use the function for various option arguments.
1780 2020-05-05 Martin Liska <mliska@suse.cz>
1783 * lto-wrapper.c (run_gcc): When using -flto=jobserver,
1784 report warning when the jobserver is not detected.
1786 2020-05-05 Martin Liska <mliska@suse.cz>
1788 PR gcov-profile/94636
1789 * gcov.c (main): Print total lines summary at the end.
1790 (generate_results): Expect file_name always being non-null.
1791 Print newline after intermediate file is printed in order to align with
1792 what we do for normal files.
1794 2020-05-05 Martin Liska <mliska@suse.cz>
1796 * dumpfile.c (dump_switch_p): Change return type
1797 and print option suggestion.
1798 * dumpfile.h: Change return type.
1799 * opts-global.c (handle_common_deferred_options):
1800 Move error into dump_switch_p function.
1802 2020-05-05 Martin Liska <mliska@suse.cz>
1805 * alloc-pool.h: Use const for some arguments.
1806 * bitmap.h: Likewise.
1807 * mem-stats.h: Likewise.
1808 * sese.h (get_entry_bb): Likewise.
1809 (get_exit_bb): Likewise.
1811 2020-05-05 Richard Biener <rguenther@suse.de>
1813 * tree-vect-slp.c (struct vdhs_data): New.
1814 (vect_detect_hybrid_slp): New walker.
1815 (vect_detect_hybrid_slp): Rewrite.
1817 2020-05-05 Richard Biener <rguenther@suse.de>
1820 * tree-ssa-structalias.c (ipa_pta_execute): Use
1821 varpool_node::externally_visible_p ().
1822 (refered_from_nonlocal_var): Likewise.
1824 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
1826 * gcc.c (LTO_PLUGIN_SPEC): Define if not already.
1827 (LINK_PLUGIN_SPEC): Execute LTO_PLUGIN_SPEC.
1828 * config/vxworks.h (LTO_PLUGIN_SPEC): Define.
1830 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
1832 * gimplify.c (gimplify_init_constructor): Do not put the constructor
1833 into static memory if it is not complete.
1835 2020-05-05 Richard Biener <rguenther@suse.de>
1837 PR tree-optimization/94949
1838 * tree-ssa-loop-im.c (execute_sm): Check whether we use
1839 the multithreaded model or always compute the stored value
1840 before eliding a load.
1842 2020-05-05 Alex Coplan <alex.coplan@arm.com>
1844 * config/aarch64/aarch64.md (*one_cmpl_zero_extend): New.
1846 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1848 PR tree-optimization/94800
1849 * match.pd (X + (X << C) to X * (1 + (1 << C)),
1850 (X << C1) + (X << C2) to X * ((1 << C1) + (1 << C2))): New
1854 * config/i386/mmx.md (*vec_dupv4hi): Use xYw constraints instead of Yv.
1856 PR tree-optimization/94914
1857 * match.pd ((((type)A * B) >> prec) != 0 to .MUL_OVERFLOW(A, B) != 0):
1860 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
1862 * config/i386/i386.md (*testqi_ext_3): Use
1863 int_nonimmediate_operand instead of manual mode checks.
1864 (*x86_mov<SWI48:mode>cc_0_m1_neg_leu<SWI:mode>):
1865 Use int_nonimmediate_operand predicate. Rewrite
1866 define_insn_and_split pattern to a combine pass splitter.
1868 2020-05-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1870 * configure.ac <i[34567]86-*-*>: Add --32 to tls_as_opt on Solaris.
1871 * configure: Regenerate.
1873 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1876 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
1877 ssse3_ph<plusminus_mnemonic>wv8hi3, ssse3_ph<plusminus_mnemonic>wv4hi3,
1878 avx2_ph<plusminus_mnemonic>dv8si3, ssse3_ph<plusminus_mnemonic>dv4si3,
1879 ssse3_ph<plusminus_mnemonic>dv2si3): Simplify RTL patterns.
1881 2020-05-04 Clement Chigot <clement.chigot@atos.net>
1882 David Edelsohn <dje.gcc@gmail.com>
1884 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override explicit
1885 for fmodl, frexpl, ldexpl and modfl builtins.
1887 2020-05-04 Richard Sandiford <richard.sandiford@arm.com>
1890 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the
1891 chosen lhs is different from the gcall lhs.
1892 (expand_mask_load_optab_fn): Likewise.
1893 (expand_gather_load_optab_fn): Likewise.
1895 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
1898 * config/i386/i386.md (*neg<mode>_ccc): New insn pattern.
1899 (EQ compare->LTU compare splitter): New splitter.
1900 (NE compare->NEG splitter): Ditto.
1902 2020-05-04 Marek Polacek <polacek@redhat.com>
1905 2020-04-30 Marek Polacek <polacek@redhat.com>
1908 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
1909 (check_aligned_type): Check if TYPE_USER_ALIGN match.
1911 2020-05-04 Richard Biener <rguenther@suse.de>
1913 PR tree-optimization/93891
1914 * tree-ssa-sccvn.c (vn_reference_lookup_3): Fall back to
1915 the original reference tree for assessing access alignment.
1917 2020-05-04 Richard Biener <rguenther@suse.de>
1919 PR tree-optimization/39612
1920 * tree-ssa-loop-im.c (im_mem_ref::loaded): New member.
1921 (set_ref_loaded_in_loop): New.
1922 (mark_ref_loaded): Likewise.
1923 (gather_mem_refs_stmt): Call mark_ref_loaded for loads.
1924 (execute_sm): Avoid issueing a load when it was not there.
1925 (execute_sm_if_changed): Avoid issueing warnings for the
1928 2020-05-04 Martin Jambor <mjambor@suse.cz>
1931 * tree-inline.c (tree_function_versioning): Leave any type conversion
1932 of replacements to setup_one_parameter and its friend
1933 force_value_to_type.
1935 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
1938 * config/i386/predicates.md (shr_comparison_operator): New predicate.
1939 * config/i386/i386.md (compare->shr splitter): New splitters.
1941 2020-05-04 Jakub Jelinek <jakub@redhat.com>
1943 PR tree-optimization/94718
1944 * match.pd ((X < 0) != (Y < 0) into (X ^ Y) < 0): New simplification.
1946 PR tree-optimization/94718
1947 * match.pd (bitop (convert @0) (convert? @1)): For GIMPLE, if we can,
1948 replace two nop conversions on bit_{and,ior,xor} argument
1949 and result with just one conversion on the result or another argument.
1951 PR tree-optimization/94718
1952 * fold-const.c (fold_binary_loc): Move (X & C) eqne (Y & C)
1953 -> (X ^ Y) & C eqne 0 optimization to ...
1954 * match.pd ((X & C) op (Y & C) into (X ^ Y) & C op 0): ... here.
1956 * opts.c (get_option_html_page): Instead of hardcoding a list of
1957 options common between C/C++ and Fortran only use gfortran/
1958 documentation for warnings that have CL_Fortran set but not
1961 2020-05-03 Uroš Bizjak <ubizjak@gmail.com>
1963 * config/i386/i386-expand.c (ix86_expand_int_movcc):
1964 Use plus_constant instead of gen_rtx_PLUS with GEN_INT.
1965 (emit_memmov): Ditto.
1966 (emit_memset): Ditto.
1967 (ix86_expand_strlensi_unroll_1): Ditto.
1968 (release_scratch_register_on_entry): Ditto.
1969 (gen_frame_set): Ditto.
1970 (ix86_emit_restore_reg_using_pop): Ditto.
1971 (ix86_emit_outlined_ms2sysv_restore): Ditto.
1972 (ix86_expand_epilogue): Ditto.
1973 (ix86_expand_split_stack_prologue): Ditto.
1974 * config/i386/i386.md (push immediate splitter): Ditto.
1978 2020-05-02 Iain Sandoe <iain@sandoe.co.uk>
1980 PR translation/93861
1981 * config/darwin-driver.c (darwin_driver_init): Adjust spelling in
1984 2020-05-02 Jakub Jelinek <jakub@redhat.com>
1986 * config/tilegx/tilegx.md
1987 (insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n>
1988 rather than just <n>.
1990 2020-05-01 H.J. Lu <hongjiu.lu@intel.com>
1993 * cfgexpand.c (pass_expand::execute): Set crtl->patch_area_size
1994 and crtl->patch_area_entry.
1995 * emit-rtl.h (rtl_data): Add patch_area_size and patch_area_entry.
1996 * opts.c (common_handle_option): Limit
1997 function_entry_patch_area_size and function_entry_patch_area_start
1998 to USHRT_MAX. Fix a typo in error message.
1999 * varasm.c (assemble_start_function): Use crtl->patch_area_size
2000 and crtl->patch_area_entry.
2001 * doc/invoke.texi: Document the maximum value for
2002 -fpatchable-function-entry.
2004 2020-05-01 Iain Sandoe <iain@sandoe.co.uk>
2006 * config/i386/darwin.h: Repair SUBTARGET_INIT_BUILTINS.
2007 Override SUBTARGET_SHADOW_OFFSET macro.
2009 2020-05-01 Andreas Tobler <andreast@gcc.gnu.org>
2011 * config/i386/i386.h: Define a new macro: SUBTARGET_SHADOW_OFFSET.
2012 * config/i386/i386.c (ix86_asan_shadow_offset): Use this macro.
2013 * config/i386/darwin.h: Override the SUBTARGET_SHADOW_OFFSET macro.
2014 * config/i386/freebsd.h: Likewise.
2015 * config/freebsd.h (LIBASAN_EARLY_SPEC): Define.
2016 LIBTSAN_EARLY_SPEC): Likewise. (LIBLSAN_EARLY_SPEC): Likewise.
2018 2020-04-30 Alexandre Oliva <oliva@adacore.com>
2020 * doc/sourcebuild.texi (Effective-Target Keywords): Document
2021 the newly-introduced fileio effective target.
2023 2020-04-30 Richard Sandiford <richard.sandiford@arm.com>
2025 PR rtl-optimization/94740
2026 * cse.c (cse_process_notes_1): Replace with...
2027 (cse_process_note_1): ...this new function, acting as a
2028 simplify_replace_fn_rtx callback to process_note. Handle only
2029 REGs and MEMs directly. Validate the MEM if cse_process_note
2030 changes its address.
2031 (cse_process_notes): Replace with...
2032 (cse_process_note): ...this new function.
2033 (cse_extended_basic_block): Update accordingly, iterating over
2034 the register notes and passing individual notes to cse_process_note.
2036 2020-04-30 Carl Love <cel@us.ibm.com>
2038 * config/rs6000/emmintrin.h (_mm_movemask_epi8): Fix comment.
2040 2020-04-30 Martin Jambor <mjambor@suse.cz>
2043 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies
2044 saved by the inliner and thunks which had their call inlined.
2045 * ipa-inline-transform.c (save_inline_function_body): Fill in
2046 former_clone_of of new body holders.
2048 2020-04-30 Jakub Jelinek <jakub@redhat.com>
2050 * BASE-VER: Set to 11.0.0.
2052 2020-04-30 Jonathan Wakely <jwakely@redhat.com>
2054 * pretty-print.c (pp_take_prefix): Fix spelling in comment.
2056 2020-04-30 Marek Polacek <polacek@redhat.com>
2059 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
2060 (check_aligned_type): Check if TYPE_USER_ALIGN match.
2062 2020-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2064 * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define.
2065 * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable.
2066 * doc/invoke.texi (moutline-atomics): Document as on by default.
2068 2020-04-30 Szabolcs Nagy <szabolcs.nagy@arm.com>
2071 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove
2072 the check for NOTE_INSN_DELETED_LABEL.
2074 2020-04-30 Jakub Jelinek <jakub@redhat.com>
2076 * configure.ac (--with-documentation-root-url,
2077 --with-changes-root-url): Diagnose URL not ending with /,
2078 use AC_DEFINE_UNQUOTED instead of AC_SUBST.
2079 * opts.h (get_changes_url): Remove.
2080 * opts.c (get_changes_url): Remove.
2081 * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL
2082 or -DCHANGES_ROOT_URL.
2083 * doc/install.texi (--with-documentation-root-url,
2084 --with-changes-root-url): Document.
2085 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call
2086 get_changes_url and free, change url variable type to const char * and
2087 set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base".
2088 * config/s390/s390.c (s390_function_arg_vector,
2089 s390_function_arg_float): Likewise.
2090 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
2092 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
2094 * config.in: Regenerate.
2095 * configure: Regenerate.
2097 2020-04-30 Christophe Lyon <christophe.lyon@linaro.org>
2100 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries.
2102 2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
2104 * config/s390/constraints.md ("j>f", "jb4"): New constraints.
2105 * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix
2107 * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a
2109 ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst.
2110 Change constraint for vlrl/vstrl to jb4.
2112 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2114 * var-tracking.c (vt_initialize): Move variables pre and post
2115 into inner block and initialize both in order to fix warning
2116 about uninitialized use. Remove unnecessary checks for
2117 frame_pointer_needed.
2119 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2121 * toplev.c (output_stack_usage_1): Ensure that first
2122 argument to fprintf is not null.
2124 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2126 * configure.ac (-with-changes-root-url): New configure option,
2127 defaulting to https://gcc.gnu.org/.
2128 * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for
2130 * pretty-print.c (get_end_url_string): New function.
2131 (pp_format): Handle %{ and %} for URLs.
2132 (pp_begin_url): Use pp_string instead of pp_printf.
2133 (pp_end_url): Use get_end_url_string.
2134 * opts.h (get_changes_url): Declare.
2135 * opts.c (get_changes_url): New function.
2136 * config/rs6000/rs6000-call.c: Include opts.h.
2137 (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead
2138 of just in GCC 10.1 in diagnostics and add URL.
2139 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise.
2140 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
2142 * config/s390/s390.c (s390_function_arg_vector,
2143 s390_function_arg_float): Likewise.
2144 * configure: Regenerated.
2147 * config/s390/s390.c (s390_function_arg_vector,
2148 s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of
2149 cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type
2150 passed to the function rather than the type of the single element.
2151 Rename cxx17_empty_base_seen variable to empty_base_seen, change
2152 type to int, and adjust diagnostics depending on if the field
2153 has [[no_unique_attribute]] or not.
2156 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8,
2157 _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands
2158 used in casts into parens.
2159 * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph,
2160 _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph,
2161 _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph,
2162 _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask,
2163 _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask,
2164 _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask,
2165 _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise.
2166 * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8,
2167 _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8,
2168 _mm256_mask_cmp_epu8_mask): Likewise.
2169 * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph,
2170 _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise.
2171 * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise.
2172 * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise.
2175 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd,
2176 _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd,
2177 _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps,
2178 _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps,
2179 _mm256_mask_i64gather_ps, _mm_i32gather_epi64,
2180 _mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
2181 _mm256_mask_i32gather_epi64, _mm_i64gather_epi64,
2182 _mm_mask_i64gather_epi64, _mm256_i64gather_epi64,
2183 _mm256_mask_i64gather_epi64, _mm_i32gather_epi32,
2184 _mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
2185 _mm256_mask_i32gather_epi32, _mm_i64gather_epi32,
2186 _mm_mask_i64gather_epi32, _mm256_i64gather_epi32,
2187 _mm256_mask_i64gather_epi32): Surround macro parameter uses with
2189 (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd,
2190 _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps,
2191 _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use
2192 as mask vector containing -1.0 or -1.0f elts, but instead vector
2193 with all bits set using _mm*_cmpeq_p? with zero operands.
2194 * config/i386/avx512fintrin.h (_mm512_i32gather_ps,
2195 _mm512_mask_i32gather_ps, _mm512_i32gather_pd,
2196 _mm512_mask_i32gather_pd, _mm512_i64gather_ps,
2197 _mm512_mask_i64gather_ps, _mm512_i64gather_pd,
2198 _mm512_mask_i64gather_pd, _mm512_i32gather_epi32,
2199 _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64,
2200 _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32,
2201 _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64,
2202 _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps,
2203 _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd,
2204 _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps,
2205 _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd,
2206 _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32,
2207 _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64,
2208 _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32,
2209 _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64,
2210 _mm512_mask_i64scatter_epi64): Surround macro parameter uses with
2212 * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd,
2213 _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd,
2214 _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd,
2215 _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd,
2216 _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd,
2217 _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd,
2218 _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd,
2219 _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd,
2220 _mm512_mask_prefetch_i64scatter_ps): Likewise.
2221 * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps,
2222 _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd,
2223 _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps,
2224 _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd,
2225 _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32,
2226 _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64,
2227 _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32,
2228 _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64,
2229 _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps,
2230 _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps,
2231 _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd,
2232 _mm_mask_i32scatter_pd, _mm256_i64scatter_ps,
2233 _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps,
2234 _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd,
2235 _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32,
2236 _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32,
2237 _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64,
2238 _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64,
2239 _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32,
2240 _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32,
2241 _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64,
2242 _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64,
2243 _mm_mask_i64scatter_epi64): Likewise.
2245 2020-04-29 Jeff Law <law@redhat.com>
2247 * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific
2248 division instructions are 4 bytes long.
2250 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2253 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use
2254 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2255 fenv_var, fenv_clear and old_fenv variables. For fenv_addr
2256 take address of TARGET_EXPR of fenv_var with void_node initializer.
2259 2020-04-29 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2261 PR tree-optimization/94774
2262 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize
2265 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2267 * calls.h (cxx17_empty_base_field_p): Turn into a function declaration.
2268 * calls.c (cxx17_empty_base_field_p): New function. Check
2269 DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the
2272 2020-04-29 H.J. Lu <hongjiu.lu@intel.com>
2275 * config/i386/i386-options.c (ix86_set_indirect_branch_type):
2276 Allow -fcf-protection with -mindirect-branch=thunk-extern and
2277 -mfunction-return=thunk-extern.
2278 * doc/invoke.texi: Update notes for -fcf-protection=branch with
2279 -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern.
2281 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2283 * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor.
2285 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2287 * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
2288 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
2289 fenv_var and new_fenv_var.
2291 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2293 * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new
2294 effective-target keyword.
2295 (arm_arch_v8a_hard_multilib): Likewise.
2296 (arm_arch_v8a_hard): Document new dg-add-options keyword.
2297 * config/arm/arm.c (arm_return_in_memory): Note that the APCS
2298 code is deprecated and has not been updated to handle
2299 DECL_FIELD_ABI_IGNORED.
2300 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2301 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2302 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2303 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2304 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2305 something actually is a HFA or HVA. Record whether we see a
2306 [[no_unique_address]] field that previous GCCs would not have
2307 ignored in this way.
2308 (aapcs_vfp_is_call_or_return_candidate): Update the calls to
2309 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2310 [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the
2311 diagnostic messages.
2312 (arm_needs_doubleword_align): Add a comment explaining why we
2313 consider even zero-sized fields.
2315 2020-04-29 Richard Biener <rguenther@suse.de>
2316 Li Zekun <lizekun1@huawei.com>
2319 * tree.c (component_ref_size): Guard against error_mark_node
2320 DECL_INITIAL as it happens with LTO.
2322 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2324 * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a
2325 comment explaining why we consider even zero-sized fields.
2326 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2327 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2328 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2329 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2330 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2331 something actually is a HFA or HVA. Record whether we see a
2332 [[no_unique_address]] field that previous GCCs would not have
2333 ignored in this way.
2334 (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say
2335 whether diagnostics should be suppressed. Update the calls to
2336 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2337 [[no_unique_address]] case.
2338 (aarch64_return_in_msb): Update call accordingly, never silencing
2340 (aarch64_function_value): Likewise.
2341 (aarch64_return_in_memory_1): Likewise.
2342 (aarch64_init_cumulative_args): Likewise.
2343 (aarch64_gimplify_va_arg_expr): Likewise.
2344 (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and
2345 use it to decide whether arch64_vfp_is_call_or_return_candidate
2347 (aarch64_pass_by_reference): Update calls accordingly.
2348 (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument
2349 to decide whether arch64_vfp_is_call_or_return_candidate should be
2352 2020-04-29 Haijian Zhang <z.zhanghaijian@huawei.com>
2355 * config/aarch64/aarch64-builtins.c
2356 (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of
2357 MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and
2360 2020-04-29 Thomas Schwinge <thomas@codesourcery.com>
2362 * configure.ac <$enable_offload_targets>: Do parsing as done
2364 * configure: Regenerate.
2366 * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'.
2367 * configure: Regenerate.
2370 * rtlanal.c (set_noop_p): Handle non-constant selectors.
2373 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New
2375 (TARGET_EXCEPT_UNWIND_INFO): Define.
2377 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2380 * config/gcn/gcn.md (*mov<mode>_insn): Use
2381 'reg_overlap_mentioned_p' to check for overlap.
2384 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED
2385 instead of cxx17_empty_base_field_p.
2388 * tree-core.h (tree_decl_common): Note decl_flag_0 used for
2389 DECL_FIELD_ABI_IGNORED.
2390 * tree.h (DECL_FIELD_ABI_IGNORED): Define.
2391 * calls.h (cxx17_empty_base_field_p): Change into a temporary
2392 macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address"
2394 * calls.c (cxx17_empty_base_field_p): Remove.
2395 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle
2396 DECL_FIELD_ABI_IGNORED.
2397 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
2398 * lto-streamer-out.c (hash_tree): Likewise.
2399 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename
2400 cxx17_empty_base_seen to empty_base_seen, change type to int *,
2401 adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of
2402 cxx17_empty_base_field_p, if "no_unique_address" attribute is
2403 present, propagate that to the caller too.
2404 (rs6000_discover_homogeneous_aggregate): Adjust
2405 rs6000_aggregate_candidate caller, emit different diagnostics
2406 when c++17 empty base fields are present and when empty
2407 [[no_unique_address]] fields are present.
2408 * config/rs6000/rs6000.c (rs6000_special_round_type_align,
2409 darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED
2412 2020-04-29 Richard Biener <rguenther@suse.de>
2414 * tree-ssa-loop-im.c (ref_always_accessed::operator ()):
2415 Just check whether the stmt stores.
2417 2020-04-28 Alexandre Oliva <oliva@adacore.com>
2420 * config/rs6000/rs6000.md (rs6000_mffsl): Copy result to
2421 output operand in emulation. Don't overwrite pseudos.
2423 2020-04-28 Jeff Law <law@redhat.com>
2425 * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific
2426 multiply patterns are 4 bytes long.
2428 2020-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2430 * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option.
2431 * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option.
2433 2020-04-28 Matthew Malcomson <matthew.malcomson@arm.com>
2434 Jakub Jelinek <jakub@redhat.com>
2437 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty
2438 base class artificial fields.
2439 (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI
2440 decision is different after this fix.
2442 2020-04-28 David Malcolm <dmalcolm@redhat.com>
2448 * doc/invoke.texi (Static Analyzer Options): Remove
2449 -Wanalyzer-use-of-uninitialized-value.
2450 (-Wno-analyzer-use-of-uninitialized-value): Remove item.
2452 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2454 PR tree-optimization/94809
2455 * tree.c (build_call_expr_internal_loc_array): Call
2456 process_call_operands.
2458 2020-04-27 Anton Youdkevitch <anton.youdkevitch@bell-sw.com>
2460 * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name.
2461 * config/aarch64/aarch64-tune.md: Regenerate.
2462 * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define.
2463 (thunderx3t110_regmove_cost): Likewise.
2464 (thunderx3t110_vector_cost): Likewise.
2465 (thunderx3t110_prefetch_tune): Likewise.
2466 (thunderx3t110_tunings): Likewise.
2467 * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs):
2469 * config/aarch64/thunderx3t110.md: New file.
2470 * config/aarch64/aarch64.md: Include thunderx3t110.md.
2471 * doc/invoke.texi (AArch64 options): Add thunderx3t110.
2473 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2476 * config/s390/s390.c (s390_function_arg_vector,
2477 s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed.
2479 2020-04-28 Richard Sandiford <richard.sandiford@arm.com>
2481 PR tree-optimization/94727
2482 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison
2483 operands are invariant booleans, use the mask type associated with the
2484 STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP.
2485 (vectorizable_condition): Pass vectype unconditionally to
2486 vect_is_simple_cond.
2488 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2491 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use
2492 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2493 sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var.
2495 2020-04-27 David Malcolm <dmalcolm@redhat.com>
2498 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from
2499 default value, so that it can by supplied by get_option_html_page.
2500 * configure: Regenerate.
2501 * opts.c: Include "selftest.h".
2502 (get_option_html_page): New function.
2503 (get_option_url): Use it. Reformat to place comments next to the
2504 expressions they refer to.
2505 (selftest::test_get_option_html_page): New.
2506 (selftest::opts_c_tests): New.
2507 * selftest-run-tests.c (selftest::run_tests): Call
2508 selftest::opts_c_tests.
2509 * selftest.h (selftest::opts_c_tests): New decl.
2511 2020-04-27 Richard Sandiford <richard.sandiford@arm.com>
2513 * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply
2514 UINTVAL to CONST_INTs.
2516 2020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2518 * config/arm/constraints.md (e): Remove constraint.
2519 (Te): Define constraint.
2520 * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in
2521 operand 0 from "e" to "Te".
2522 (vaddvaq_<supf><mode>): Likewise.
2523 (vaddvq_p_<supf><mode>): Likewise.
2524 (vmladavq_<supf><mode>): Likewise.
2525 (vmladavxq_s<mode>): Likewise.
2526 (vmlsdavq_s<mode>): Likewise.
2527 (vmlsdavxq_s<mode>): Likewise.
2528 (vaddvaq_p_<supf><mode>): Likewise.
2529 (vmladavaq_<supf><mode>): Likewise.
2530 (vmladavq_p_<supf><mode>): Likewise.
2531 (vmladavxq_p_s<mode>): Likewise.
2532 (vmlsdavq_p_s<mode>): Likewise.
2533 (vmlsdavxq_p_s<mode>): Likewise.
2534 (vmlsdavaxq_s<mode>): Likewise.
2535 (vmlsdavaq_s<mode>): Likewise.
2536 (vmladavaxq_s<mode>): Likewise.
2537 (vmladavaq_p_<supf><mode>): Likewise.
2538 (vmladavaxq_p_s<mode>): Likewise.
2539 (vmlsdavaq_p_s<mode>): Likewise.
2540 (vmlsdavaxq_p_s<mode>): Likewise.
2542 2020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com>
2544 * config/arm/arm.c (output_move_neon): Only get the first operand if
2547 2020-04-27 Felix Yang <felix.yang@huawei.com>
2549 PR tree-optimization/94784
2550 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the
2551 assert around so that it checks that the two vectors have equal
2552 TYPE_VECTOR_SUBPARTS and that converting the corresponding element
2553 types is a useless_type_conversion_p.
2555 2020-04-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
2558 * dwarf2cfi.c (struct GTY): Add ra_mangled.
2559 (cfi_row_equal_p): Check ra_mangled.
2560 (dwarf2out_frame_debug_cfa_window_save): Remove the argument,
2561 this only handles the sparc logic now.
2562 (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for
2563 the aarch64 specific logic.
2564 (dwarf2out_frame_debug): Update to use the new subroutines.
2565 (change_cfi_row): Check ra_mangled.
2567 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2570 * config/s390/s390.c (s390_function_arg_vector,
2571 s390_function_arg_float): Ignore cxx17_empty_base_field_p fields.
2573 2020-04-27 Jiufu Guo <guojiufu@cn.ibm.com>
2575 * common/config/rs6000/rs6000-common.c
2576 (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off
2578 * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to
2581 2020-04-27 Martin Liska <mliska@suse.cz>
2584 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p):
2585 Do not remove ifunc_resolvers in remove unreachable nodes in LTO.
2587 2020-04-27 Xiong Hu Luo <luoxhu@linux.ibm.com>
2590 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed):
2592 (rs6000_emit_prologue_components):
2593 Check with frame_pointer_needed_indeed.
2594 (rs6000_emit_epilogue_components): Likewise.
2595 (rs6000_emit_prologue): Likewise.
2596 (rs6000_emit_epilogue): Set frame_pointer_needed_indeed.
2598 2020-04-25 David Edelsohn <dje.gcc@gmail.com>
2600 * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a
2601 stack frame when debugging and flag_compare_debug is enabled.
2603 2020-04-25 Michael Meissner <meissner@linux.ibm.com>
2605 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to
2606 enable PC-relative addressing for -mcpu=future.
2607 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move
2608 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS.
2609 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined,
2610 suppress PC-relative addressing.
2611 (rs6000_option_override_internal): Split up error messages
2612 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target
2615 2020-04-25 Jakub Jelinek <jakub@redhat.com>
2616 Richard Biener <rguenther@suse.de>
2618 PR tree-optimization/94734
2619 PR tree-optimization/89430
2620 * tree-ssa-phiopt.c: Include tree-eh.h.
2621 (cond_store_replacement): Return false if an automatic variable
2622 access could trap. If -fstore-data-races, don't return false
2623 just because an automatic variable is addressable.
2625 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2627 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
2629 (add<mode>_sext_dup2_exec): Likewise.
2631 2020-04-24 Segher Boessenkool <segher@kernel.crashing.org>
2634 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
2635 endian byteshift_val calculation.
2637 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2639 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
2641 2020-04-24 Richard Sandiford <richard.sandiford@arm.com>
2643 * config/aarch64/arm_sve.h: Add a comment.
2645 2020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com>
2647 PR rtl-optimization/94708
2648 * combine.c (simplify_if_then_else): Add check for
2649 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode).
2651 2020-04-23 Martin Sebor <msebor@redhat.com>
2654 * common.opt (-Wno-frame-larger-than): New option.
2655 (-Wno-larger-than, -Wno-stack-usage): Same.
2657 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
2659 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands
2661 (mov<mode>_exec): Likewise.
2662 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec.
2663 (<convop><mode><vndi>2_exec): Likewise.
2665 2019-04-23 Eric Botcazou <ebotcazou@adacore.com>
2667 PR tree-optimization/94717
2668 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one
2669 of the stores doesn't have the same landing pad number as the first.
2670 (coalesce_immediate_stores): Do not try to coalesce the store using
2671 bswap if it doesn't have the same landing pad number as the first.
2673 2020-04-23 Bill Schmidt <wschmidt@linux.ibm.com>
2675 * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
2676 Replace outdated link to ELFv2 ABI.
2678 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2681 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
2685 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs
2686 temporarily with non-final second operand and updating it later,
2687 push COMPOUND_EXPRs into a vector and process it in reverse,
2688 creating COMPOUND_EXPRs with the final operands.
2690 2020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com>
2693 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap
2694 bti c and bti j handling.
2696 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
2697 Thomas Schwinge <thomas@codesourcery.com>
2701 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on
2702 t_async and the wait arguments.
2704 2020-04-23 Richard Sandiford <richard.sandiford@arm.com>
2706 PR tree-optimization/94727
2707 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when
2708 comparing invariant scalar booleans.
2710 2020-04-23 Matthew Malcomson <matthew.malcomson@arm.com>
2711 Jakub Jelinek <jakub@redhat.com>
2714 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17
2715 empty base class artificial fields.
2716 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is
2717 different after this fix.
2719 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2722 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
2723 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check
2724 if the same type has been diagnosed most recently already.
2726 2020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2728 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's
2730 (__arm_vbicq_n_s16): Likewise.
2731 (__arm_vbicq_n_u32): Likewise.
2732 (__arm_vbicq_n_s32): Likewise.
2733 (__arm_vbicq): Likewise.
2734 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype.
2735 (__arm_vbicq_n_s32): Likewise.
2736 (__arm_vbicq_n_u16): Likewise.
2737 (__arm_vbicq_n_u32): Likewise.
2738 (__arm_vdupq_m_n_s8): Likewise.
2739 (__arm_vdupq_m_n_s16): Likewise.
2740 (__arm_vdupq_m_n_s32): Likewise.
2741 (__arm_vdupq_m_n_u8): Likewise.
2742 (__arm_vdupq_m_n_u16): Likewise.
2743 (__arm_vdupq_m_n_u32): Likewise.
2744 (__arm_vdupq_m_n_f16): Likewise.
2745 (__arm_vdupq_m_n_f32): Likewise.
2746 (__arm_vldrhq_gather_offset_s16): Likewise.
2747 (__arm_vldrhq_gather_offset_s32): Likewise.
2748 (__arm_vldrhq_gather_offset_u16): Likewise.
2749 (__arm_vldrhq_gather_offset_u32): Likewise.
2750 (__arm_vldrhq_gather_offset_f16): Likewise.
2751 (__arm_vldrhq_gather_offset_z_s16): Likewise.
2752 (__arm_vldrhq_gather_offset_z_s32): Likewise.
2753 (__arm_vldrhq_gather_offset_z_u16): Likewise.
2754 (__arm_vldrhq_gather_offset_z_u32): Likewise.
2755 (__arm_vldrhq_gather_offset_z_f16): Likewise.
2756 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
2757 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
2758 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
2759 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
2760 (__arm_vldrhq_gather_shifted_offset_f16): Likewise.
2761 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
2762 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
2763 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
2764 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
2765 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise.
2766 (__arm_vldrwq_gather_offset_s32): Likewise.
2767 (__arm_vldrwq_gather_offset_u32): Likewise.
2768 (__arm_vldrwq_gather_offset_f32): Likewise.
2769 (__arm_vldrwq_gather_offset_z_s32): Likewise.
2770 (__arm_vldrwq_gather_offset_z_u32): Likewise.
2771 (__arm_vldrwq_gather_offset_z_f32): Likewise.
2772 (__arm_vldrwq_gather_shifted_offset_s32): Likewise.
2773 (__arm_vldrwq_gather_shifted_offset_u32): Likewise.
2774 (__arm_vldrwq_gather_shifted_offset_f32): Likewise.
2775 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise.
2776 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise.
2777 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise.
2778 (__arm_vdwdupq_x_n_u8): Likewise.
2779 (__arm_vdwdupq_x_n_u16): Likewise.
2780 (__arm_vdwdupq_x_n_u32): Likewise.
2781 (__arm_viwdupq_x_n_u8): Likewise.
2782 (__arm_viwdupq_x_n_u16): Likewise.
2783 (__arm_viwdupq_x_n_u32): Likewise.
2784 (__arm_vidupq_x_n_u8): Likewise.
2785 (__arm_vddupq_x_n_u8): Likewise.
2786 (__arm_vidupq_x_n_u16): Likewise.
2787 (__arm_vddupq_x_n_u16): Likewise.
2788 (__arm_vidupq_x_n_u32): Likewise.
2789 (__arm_vddupq_x_n_u32): Likewise.
2790 (__arm_vldrdq_gather_offset_s64): Likewise.
2791 (__arm_vldrdq_gather_offset_u64): Likewise.
2792 (__arm_vldrdq_gather_offset_z_s64): Likewise.
2793 (__arm_vldrdq_gather_offset_z_u64): Likewise.
2794 (__arm_vldrdq_gather_shifted_offset_s64): Likewise.
2795 (__arm_vldrdq_gather_shifted_offset_u64): Likewise.
2796 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise.
2797 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise.
2798 (__arm_vidupq_m_n_u8): Likewise.
2799 (__arm_vidupq_m_n_u16): Likewise.
2800 (__arm_vidupq_m_n_u32): Likewise.
2801 (__arm_vddupq_m_n_u8): Likewise.
2802 (__arm_vddupq_m_n_u16): Likewise.
2803 (__arm_vddupq_m_n_u32): Likewise.
2804 (__arm_vidupq_n_u16): Likewise.
2805 (__arm_vidupq_n_u32): Likewise.
2806 (__arm_vidupq_n_u8): Likewise.
2807 (__arm_vddupq_n_u16): Likewise.
2808 (__arm_vddupq_n_u32): Likewise.
2809 (__arm_vddupq_n_u8): Likewise.
2811 2020-04-23 Iain Buclaw <ibuclaw@gdcproject.org>
2813 * doc/install.texi (D-Specific Options): Document
2814 --enable-libphobos-checking and --with-libphobos-druntime-only.
2816 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2819 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add
2820 cxx17_empty_base_seen argument. Pass it to recursive calls.
2821 Ignore cxx17_empty_base_field_p fields after setting
2822 *cxx17_empty_base_seen to true.
2823 (rs6000_discover_homogeneous_aggregate): Adjust
2824 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous
2825 aggregates with C++17 empty base fields.
2828 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
2829 if last_decl is error_mark_node or has such a TREE_TYPE.
2832 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
2833 if last_decl is error_mark_node or has such a TREE_TYPE.
2835 2020-04-22 Felix Yang <felix.yang@huawei.com>
2838 * config/aarch64/aarch64.h (TARGET_SVE):
2839 Add && !TARGET_GENERAL_REGS_ONLY.
2840 (TARGET_SVE2): Add && TARGET_SVE.
2841 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3,
2842 TARGET_SVE2_SM4): Add && TARGET_SVE2.
2843 * config/aarch64/aarch64-sve-builtins.h
2844 (sve_switcher::m_old_general_regs_only): New member.
2845 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers):
2847 (reported_missing_registers_p): New variable.
2848 (check_required_extensions): Call check_required_registers before
2849 return if all required extenstions are present.
2850 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in
2851 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in
2852 global_options.x_target_flags.
2853 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in
2854 global_options.x_target_flags if m_old_general_regs_only is true.
2856 2020-04-22 Zackery Spytz <zspytz@gmail.com>
2858 * doc/extend.exi: Add "free" to list of other builtin functions
2861 2020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com>
2864 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed"
2866 (store_quadpti): Ditto.
2867 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as
2868 plq will be used and doesn't need it.
2869 (atomic_store<mode>): Ditto, for pstq.
2871 2020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com>
2873 * doc/invoke.texi: Update flags turned on by -O3.
2875 2020-04-22 Jakub Jelinek <jakub@redhat.com>
2878 * config/ia64/ia64.c (hfa_element_mode): Ignore
2879 cxx17_empty_base_field_p fields.
2882 * calls.h (cxx17_empty_base_field_p): Declare.
2883 * calls.c (cxx17_empty_base_field_p): Define.
2885 2020-04-22 Christophe Lyon <christophe.lyon@linaro.org>
2887 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document.
2889 2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2890 Andre Vieira <andre.simoesdiasvieira@arm.com>
2891 Mihail Ionescu <mihail.ionescu@arm.com>
2893 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
2894 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
2895 (ALL_QUIRKS): Add quirk_no_asmcpu.
2896 (cortex-m55): Define new cpu.
2897 * config/arm/arm-tables.opt: Regenerate.
2898 * config/arm/arm-tune.md: Likewise.
2899 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
2901 2020-04-22 Richard Sandiford <richard.sandiford@arm.com>
2903 PR tree-optimization/94700
2904 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing
2905 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures
2906 of similarly-structured but distinct vector types.
2908 2020-04-21 Martin Sebor <msebor@redhat.com>
2911 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct
2912 the computation of the lower bound of the source access size.
2913 (builtin_access::generic_overlap): Remove a hack for setting ranges
2916 2020-04-21 John David Anglin <danglin@gcc.gnu.org>
2918 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete.
2919 (ASM_WEAKEN_DECL): New define.
2920 (HAVE_GAS_WEAKREF): Undefine.
2922 2020-04-21 Richard Sandiford <richard.sandiford@arm.com>
2924 PR tree-optimization/94683
2925 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a
2926 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured
2927 but distinct vector types.
2929 2020-04-21 Jakub Jelinek <jakub@redhat.com>
2932 * stor-layout.c (place_field, finalize_record_size): Don't emit
2933 -Wpadded warning on TYPE_ARTIFICIAL rli->t.
2934 * ubsan.c (ubsan_get_type_descriptor_type,
2935 ubsan_get_source_location_type, ubsan_create_data): Set
2937 * asan.c (asan_global_struct): Likewise.
2939 2020-04-21 Duan bo <duanbo3@huawei.com>
2942 * config/aarch64/aarch64.c: Add an error message for option conflict.
2943 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is
2944 incompatible with -fpic, -fPIC and -mabi=ilp32.
2946 2020-04-21 Frederik Harwath <frederik@codesourcery.com>
2949 * omp-low.c (new_omp_context): Remove assignments to
2950 ctx->outer_reduction_clauses and ctx->local_reduction_clauses.
2952 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
2954 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
2955 ("popcountv2di2_vx"): Use simplify_gen_subreg.
2957 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
2960 * config/s390/s390-builtin-types.def: Add 3 new function modes.
2961 * config/s390/s390-builtins.def: Add mode dependent low-level
2962 builtin and map the overloaded builtins to these.
2963 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
2964 ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
2966 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
2968 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo
2969 has a variable VF, prefer new_loop_vinfo if it is cheaper for the
2970 estimated VF and is no worse at double the estimated VF.
2972 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
2975 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix
2976 order of arguments to rtx_vector_builder.
2977 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise.
2978 When extending the trailing constants to a full vector, replace any
2979 variables with zeros.
2981 2020-04-20 Jan Hubicka <hubicka@ucw.cz>
2984 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local
2987 2020-04-20 Martin Liska <mliska@suse.cz>
2989 * symtab.c (symtab_node::dump_references): Add space after
2991 (symtab_node::dump_referring): Likewise.
2993 2020-04-18 Jeff Law <law@redhat.com>
2996 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking
2999 2020-04-18 Iain Buclaw <ibuclaw@gdcproject.org>
3001 * doc/sourcebuild.texi (Effective-Target Keywords, Environment
3002 attributes): Document d_runtime_has_std_library.
3004 2020-04-17 Jeff Law <law@redhat.com>
3006 PR rtl-optimization/90275
3007 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels
3008 when the destination has a REG_UNUSED note.
3010 2020-04-17 Tobias Burnus <tobias@codesourcery.com>
3013 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to
3016 2020-04-17 Richard Sandiford <richard.sandiford@arm.com>
3018 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function.
3019 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the
3020 cost of load and store insns if one loop iteration has enough scalar
3021 elements to use an Advanced SIMD LDP or STP.
3022 (aarch64_add_stmt_cost): Update call accordingly.
3024 2020-04-17 Jakub Jelinek <jakub@redhat.com>
3025 Jeff Law <law@redhat.com>
3028 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than
3029 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision,
3030 or pos + len >= 32, or pos + len is equal to operands[2] precision
3031 and operands[2] is not a register operand. During splitting perform
3032 SImode AND if operands[0] doesn't have CCZmode and pos + len is
3033 equal to mode precision.
3035 2020-04-17 Richard Biener <rguenther@suse.de>
3038 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate
3040 * dwarf2out.c (dw_val_equal_p): Fix pasto in
3041 dw_val_class_vms_delta comparison.
3042 * optabs.c (expand_binop_directly): Fix pasto in commutation
3044 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in
3047 2020-04-17 Jakub Jelinek <jakub@redhat.com>
3049 PR rtl-optimization/94618
3050 * cfgrtl.c (delete_insn_and_edges): Set purge not just when
3051 insn is the BB_END of its block, but also when it is only followed
3052 by DEBUG_INSNs in its block.
3054 PR tree-optimization/94621
3055 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN.
3056 Move id->adjust_array_error_bounds check first in the condition.
3058 2020-04-17 Martin Liska <mliska@suse.cz>
3059 Jonathan Yong <10walls@gmail.com>
3061 PR gcov-profile/94570
3062 * coverage.c (coverage_init): Use separator properly.
3064 2020-04-16 Peter Bergner <bergner@linux.ibm.com>
3066 PR rtl-optimization/93974
3067 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
3068 (rs6000_cannot_substitute_mem_equiv_p): New function.
3070 2020-04-16 Martin Jambor <mjambor@suse.cz>
3073 * ipa-inline.h (ipa_saved_clone_sources): Declare.
3074 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable.
3075 (save_inline_function_body): Link the new body holder with the
3077 * cgraph.c: Include ipa-inline.h.
3078 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from
3079 the statement in ipa_saved_clone_sources.
3080 * cgraphunit.c: Include ipa-inline.h.
3081 (expand_all_functions): Free ipa_saved_clone_sources.
3083 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
3086 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
3087 the VNx16BI lowpart of the recursively-generated constant.
3089 2020-04-16 Martin Liska <mliska@suse.cz>
3090 Jakub Jelinek <jakub@redhat.com>
3093 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
3094 DECL_IS_REPLACEABLE_OPERATOR during cloning.
3095 * tree-ssa-dce.c (valid_new_delete_pair_p): New function.
3096 (propagate_necessity): Check operator names.
3098 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
3100 PR rtl-optimization/94605
3101 * early-remat.c (early_remat::process_block): Handle insns that
3102 set multiple candidate registers.
3103 2020-04-16 Jan Hubicka <hubicka@ucw.cz>
3105 PR gcov-profile/93401
3106 * common.opt (profile-prefix-path): New option.
3107 * coverae.c: Include diagnostics.h.
3108 (coverage_init): Strip profile prefix path.
3109 * doc/invoke.texi (-fprofile-prefix-path): Document.
3111 2020-04-16 Richard Biener <rguenther@suse.de>
3114 * expr.c (emit_move_multi_word): Do not generate code when
3115 the destination part is undefined_operand_subword_p.
3116 * lower-subreg.c (resolve_clobber): Look through a paradoxica
3119 2020-04-16 Martin Jambor <mjambor@suse.cz>
3121 PR tree-optimization/94598
3122 * tree-sra.c (verify_sra_access_forest): Fix verification of total
3123 scalarization accesses under access to one-element arrays.
3125 2020-04-16 Jakub Jelinek <jakub@redhat.com>
3128 * function.c (assign_parm_find_data_types): Add workaround for
3129 BROKEN_VALUE_INITIALIZATION compilers.
3131 2020-04-16 Richard Biener <rguenther@suse.de>
3133 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME
3136 2020-04-15 Uroš Bizjak <ubizjak@gmail.com>
3139 * config/i386/i386-builtin.def (__builtin_ia32_movq128):
3140 Require OPTION_MASK_ISA_SSE2.
3142 2020-04-15 Gustavo Romero <gromero@linux.ibm.com>
3145 * dumpfile.c (selftest::temp_dump_context::temp_dump_context):
3146 Don't construct a dump_context temporary to call static method.
3148 2020-04-15 Andrea Corallo <andrea.corallo@arm.com>
3150 * config/aarch64/falkor-tag-collision-avoidance.c
3151 (valid_src_p): Check for aarch64_address_info type before
3152 accessing base field.
3154 2020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
3156 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern.
3157 (V_sz_elem2): Remove unused mode attribute.
3159 2020-04-15 Matthew Malcomson <matthew.malcomson@arm.com>
3161 * config/arm/arm.md (arm_movdi): Disallow for MVE.
3163 2020-04-15 Richard Biener <rguenther@suse.de>
3166 * tree-ssa-alias.c (same_type_for_tbaa): Defer to
3167 alias_sets_conflict_p for pointers.
3169 2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
3172 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
3173 (extendhisi2_internal): Add %v1 before the load instructions.
3175 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
3178 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to
3179 use PC-relative addressing for TLS references.
3181 2020-04-14 Martin Jambor <mjambor@suse.cz>
3184 * ipa-sra.c: Include internal-fn.h.
3185 (enum isra_scan_context): Update comment.
3186 (scan_function): Treat calls to internal_functions like loads or stores.
3188 2020-04-14 Yang Yang <yangyang305@huawei.com>
3190 PR tree-optimization/94574
3191 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
3192 whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
3194 2020-04-14 H.J. Lu <hongjiu.lu@intel.com>
3197 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
3199 2020-04-13 Martin Sebor <msebor@redhat.com>
3201 * doc/extend.texi (-Wall): Mention -Wformat-overflow and
3202 -Wformat-truncation. Move -Wzero-length-bounds last.
3203 (-Wrestrict): Document positive form of option enabled by -Wall.
3205 2020-04-13 Zachary Spytz <zspytz@gmail.com>
3207 * doc/extend.texi: Add realloc to list of built-in functions
3208 are recognized by the compiler.
3210 2020-04-13 H.J. Lu <hongjiu.lu@intel.com>
3213 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
3214 pointer in word_mode for eh_return epilogues.
3216 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3218 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to
3219 memory references in %B, %C and %D operand selectors when the inner
3220 operand is a post increment address.
3222 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3224 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory
3225 reference by 4 bytes, and %D memory reference by 6 bytes.
3227 2020-04-11 Uroš Bizjak <ubizjak@gmail.com>
3230 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2
3231 condition for V4SI, V8HI and V16QI modes.
3233 2020-04-11 Jakub Jelinek <jakub@redhat.com>
3237 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on
3240 2020-04-10 Thomas Schwinge <thomas@codesourcery.com>
3244 * omp-general.c (oacc_verify_routine_clauses): Diagnose if
3245 "#pragma omp declare target" has also been applied.
3247 2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3249 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
3250 when to emit the epilogue_helper insn.
3251 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the
3254 2020-04-09 Jakub Jelinek <jakub@redhat.com>
3257 * cselib.h (cselib_record_sp_cfa_base_equiv,
3258 cselib_sp_derived_value_p): Declare.
3259 * cselib.c (cselib_record_sp_cfa_base_equiv,
3260 cselib_sp_derived_value_p): New functions.
3261 * var-tracking.c (add_stores): Don't record MO_VAL_SET for
3262 cselib_sp_derived_value_p values.
3263 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
3264 start of extended basic blocks other than the first one
3265 for !frame_pointer_needed functions.
3267 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3269 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
3270 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
3271 (aarch64_sve2048_hw): Document.
3272 * config/aarch64/aarch64-protos.h
3273 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
3274 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
3275 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
3276 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
3278 (find_type_suffix_for_scalar_type): Use it instead of comparing
3280 (function_resolver::infer_vector_or_tuple_type): Likewise.
3281 (function_resolver::require_vector_type): Likewise.
3282 (handle_arm_sve_vector_bits_attribute): New function.
3283 * config/aarch64/aarch64.c (pure_scalable_type_info): New class.
3284 (aarch64_attribute_table): Add arm_sve_vector_bits.
3285 (aarch64_return_in_memory_1):
3286 (pure_scalable_type_info::piece::get_rtx): New function.
3287 (pure_scalable_type_info::num_zr): Likewise.
3288 (pure_scalable_type_info::num_pr): Likewise.
3289 (pure_scalable_type_info::get_rtx): Likewise.
3290 (pure_scalable_type_info::analyze): Likewise.
3291 (pure_scalable_type_info::analyze_registers): Likewise.
3292 (pure_scalable_type_info::analyze_array): Likewise.
3293 (pure_scalable_type_info::analyze_record): Likewise.
3294 (pure_scalable_type_info::add_piece): Likewise.
3295 (aarch64_some_values_include_pst_objects_p): Likewise.
3296 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
3297 to analyze whether the type is returned in SVE registers.
3298 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
3299 is passed in SVE registers.
3300 (aarch64_pass_by_reference_1): New function, extracted from...
3301 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
3302 to analyze whether the type is a pure scalable type and, if so,
3303 whether it should be passed by reference.
3304 (aarch64_return_in_msb): Return false for pure scalable types.
3305 (aarch64_function_value_1): Fold back into...
3306 (aarch64_function_value): ...this function. Use
3307 pure_scalable_type_info to analyze whether the type is a pure
3308 scalable type and, if so, which registers it should use. Handle
3309 types that include pure scalable types but are not themselves
3310 pure scalable types.
3311 (aarch64_return_in_memory_1): New function, split out from...
3312 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info
3313 to analyze whether the type is a pure scalable type and, if so,
3314 whether it should be returned by reference.
3315 (aarch64_layout_arg): Remove orig_mode argument. Use
3316 pure_scalable_type_info to analyze whether the type is a pure
3317 scalable type and, if so, which registers it should use. Handle
3318 types that include pure scalable types but are not themselves
3319 pure scalable types.
3320 (aarch64_function_arg): Update call accordingly.
3321 (aarch64_function_arg_advance): Likewise.
3322 (aarch64_pad_reg_upward): On big-endian targets, return false for
3323 pure scalable types that are smaller than 16 bytes.
3324 (aarch64_member_type_forces_blk): New function.
3325 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
3326 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that
3327 correspond to built-in SVE types. Do not rely on a vector mode
3328 if the type includes an pure scalable type. When returning true,
3329 assert that the mode is not an SVE mode.
3330 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
3331 built-in types here. When returning true, assert that the type
3332 does not have an SVE mode.
3333 (aarch64_can_change_mode_class): Don't allow anything to change
3334 between a predicate mode and a non-predicate mode. Also don't
3335 allow changes between SVE vector modes and other modes that
3336 might be bigger than 128 bits.
3337 (aarch64_invalid_binary_op): Reject binary operations that mix
3338 SVE and GNU vector types.
3339 (TARGET_MEMBER_TYPE_FORCES_BLK): Define.
3341 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3343 * config/aarch64/aarch64.c (aarch64_attribute_table): Add
3344 "SVE sizeless type".
3345 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
3346 (sizeless_type_p): New functions.
3347 (register_builtin_types): Apply make_type_sizeless to the type.
3348 (register_tuple_type): Likewise.
3349 (verify_type_context): Use sizeless_type_p instead of builin_type_p.
3351 2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
3353 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for
3356 2020-04-09 Martin Jambor <mjambor@suse.cz>
3357 Richard Biener <rguenther@suse.de>
3359 PR tree-optimization/94482
3360 * tree-sra.c (create_access_replacement): Dump new replacement with
3362 (sra_modify_expr): Fix handling of cases when the original EXPR writes
3363 to only part of the replacement.
3364 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
3365 the first operand of combinations into REAL/IMAGPART_EXPR and
3368 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3370 * doc/sourcebuild.texi (check-function-bodies): Treat the third
3371 parameter as a list of option regexps and require each regexp
3374 2020-04-09 Andrea Corallo <andrea.corallo@arm.com>
3377 * config/aarch64/falkor-tag-collision-avoidance.c
3378 (valid_src_p): Fix missing rtx type check.
3380 2020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com>
3381 Richard Biener <rguenther@suse.de>
3383 PR tree-optimization/93674
3384 * tree-ssa-loop-ivopts.c (langhooks.h): New include.
3385 (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
3386 or non-mode precision type, add candidate in unsigned type with the
3389 2020-04-08 Clement Chigot <clement.chigot@atos.net>
3391 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128.
3392 * config/rs6000/aix71.h (LIB_SPEC): Likewise.
3393 * config/rs6000/aix72.h (LIB_SPEC): Likewise.
3395 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3398 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
3400 * reload1.c (eliminate_regs_1): Avoid creating
3401 (plus (reg) (const_int 0)) in DEBUG_INSNs.
3403 PR tree-optimization/94524
3404 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
3405 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
3406 op1 rather than op1 itself at the end. Punt for signed modulo by
3407 most negative constant.
3408 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
3409 modulo by most negative constant.
3411 2020-04-08 Richard Biener <rguenther@suse.de>
3413 PR rtl-optimization/93946
3414 * cse.c (cse_insn): Record the tabled expression in
3415 src_related. Verify a redundant store removal is valid.
3417 2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
3420 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert
3421 ENDBR at function entry if function will be called indirectly.
3423 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3426 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
3429 2020-04-08 Martin Liska <mliska@suse.cz>
3432 * gimple.c (gimple_call_operator_delete_p): Rename to...
3433 (gimple_call_replaceable_operator_delete_p): ... this.
3434 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3435 * gimple.h (gimple_call_operator_delete_p): Rename to ...
3436 (gimple_call_replaceable_operator_delete_p): ... this.
3437 * tree-core.h (tree_function_decl): Add replaceable_operator
3439 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
3440 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3441 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
3442 (eliminate_unnecessary_stmts): Likewise.
3443 * tree-streamer-in.c (unpack_ts_function_decl_value_fields):
3444 Pack DECL_IS_REPLACEABLE_OPERATOR.
3445 * tree-streamer-out.c (pack_ts_function_decl_value_fields):
3446 Unpack the field here.
3447 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
3448 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
3449 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
3450 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
3451 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
3452 replaceable operator flags.
3454 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3455 Matthew Malcomson <matthew.malcomson@arm.com>
3457 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
3458 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
3459 (CX_TERNARY_QUALIFIERS): Likewise.
3460 (ARM_BUILTIN_CDE_PATTERN_START): Likewise.
3461 (ARM_BUILTIN_CDE_PATTERN_END): Likewise.
3462 (arm_init_acle_builtins): Initialize CDE builtins.
3463 (arm_expand_acle_builtin): Check CDE constant operands.
3464 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
3465 of CDE constant operand.
3466 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
3468 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
3469 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
3470 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
3471 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
3472 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
3473 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
3474 * config/arm/arm_cde_builtins.def: New file.
3475 * config/arm/iterators.md (V_reg): New attribute of SI.
3476 * config/arm/predicates.md (const_int_coproc_operand): New.
3477 (const_int_vcde1_operand, const_int_vcde2_operand): New.
3478 (const_int_vcde3_operand): New.
3479 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
3480 * config/arm/vfp.md (arm_vcx1<mode>): New entry.
3481 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
3482 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
3484 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3486 * config.gcc: Add arm_cde.h.
3487 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
3488 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
3489 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
3490 * config/arm/arm.c (arm_option_reconfigure_globals): Configure
3491 arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
3492 * config/arm/arm.h (TARGET_CDE): New macro.
3493 * config/arm/arm_cde.h: New file.
3494 * doc/invoke.texi: Document CDE options +cdecp[0-7].
3495 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
3497 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
3499 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3501 PR rtl-optimization/94516
3502 * postreload.c: Include rtl-iter.h.
3503 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
3504 looking for all MEMs with RTX_AUTOINC operand.
3505 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
3507 2020-04-08 Tobias Burnus <tobias@codesourcery.com>
3509 * omp-grid.c (grid_eliminate_combined_simd_part): Use
3510 OMP_CLAUSE_CODE to access the omp clause code.
3512 2020-04-07 Jeff Law <law@redhat.com>
3514 PR rtl-optimization/92264
3515 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when
3516 the destination is the stack pointer.
3518 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3520 PR rtl-optimization/94291
3521 PR rtl-optimization/84169
3522 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST
3523 must be a REG or SUBREG of REG; if it is not one of these, don't
3526 2020-04-07 Richard Biener <rguenther@suse.de>
3529 * gimplify.c (gimplify_addr_expr): Also consider generated
3532 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3534 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
3536 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3538 * config/arm/arm_mve.h: Cast some pointers to expected types.
3540 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3542 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
3543 same with '__arm_' prefix.
3545 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3547 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
3549 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3551 * config/arm/arm.c (arm_mve_immediate_check): Removed.
3552 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
3553 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
3554 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
3555 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
3556 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
3557 mve_vqshruntq_m_n_s*): Fixed immediate constraints.
3559 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3561 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
3563 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3565 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
3566 * config/arm/mve/md: Fix v[id]wdup patterns.
3568 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3570 * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
3571 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
3573 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3575 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
3576 and remove const_ptr enums.
3578 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3580 * config/arm/arm_mve.h (vsubq_n): Merge with...
3582 (vmulq_n): Merge with...
3584 (__ARM_mve_typeid): Simplify scalar and constant detection.
3586 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3589 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
3590 for inter-lane permutation for 64-byte modes.
3593 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
3594 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
3595 Assume it is a REG after that instead of testing it and doing FAIL
3596 otherwise. Formatting fix.
3598 2020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
3600 * config/rs6000/t-rtems: Delete mcpu=8540 multilib.
3602 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3605 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
3606 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
3608 2020-04-06 Jakub Jelinek <jakub@redhat.com>
3610 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
3611 + const0_rtx return the SP_DERIVED_VALUE_P.
3613 2020-04-06 Richard Sandiford <richard.sandiford@arm.com>
3615 PR rtl-optimization/92989
3616 * lra-lives.c (process_bb_lives): Do not treat eh_return data
3617 registers as being live at the beginning of the EH receiver.
3619 2020-04-05 Zachary Spytz <zspytz@gmail.com>
3621 * extend.texi: Add free to list of ISO C90 functions that
3622 are recognized by the compiler.
3624 2020-04-05 Nagaraju Mekala <nmekala@xilix.com>
3626 * config/microblaze/microblaze.c (microblaze_must_save_register): Check
3629 * config/microblaze/microblaze.md (trap): Update output pattern.
3631 2020-04-04 Hannes Domani <ssbssa@yahoo.de>
3632 Jakub Jelinek <jakub@redhat.com>
3635 * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
3636 arrays, pointer-to-members, function types and qualifiers when
3637 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
3638 to emit type again on definition.
3640 2020-04-04 Jan Hubicka <hubicka@ucw.cz>
3643 * ipa-fnsummary.c (vrp_will_run_p): New function.
3644 (fre_will_run_p): New function.
3645 (evaluate_properties_for_edge): Use it.
3646 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
3647 !optimize_debug to optimize_debug.
3649 2020-04-04 Jakub Jelinek <jakub@redhat.com>
3651 PR rtl-optimization/94468
3652 * cselib.c (references_value_p): Formatting fix.
3653 (cselib_useless_value_p): New function.
3654 (discard_useless_locs, discard_useless_values,
3655 cselib_invalidate_regno_val, cselib_invalidate_mem,
3656 cselib_record_set): Use it instead of
3657 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).
3660 * tree-iterator.h (expr_single): Declare.
3661 * tree-iterator.c (expr_single): New function.
3662 * tree.h (protected_set_expr_location_if_unset): Declare.
3663 * tree.c (protected_set_expr_location): Use expr_single.
3664 (protected_set_expr_location_if_unset): New function.
3666 2020-04-03 Jeff Law <law@redhat.com>
3668 PR rtl-optimization/92264
3669 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
3670 reloading of auto-increment addressing modes.
3672 2020-04-03 H.J. Lu <hongjiu.lu@intel.com>
3675 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
3678 2020-04-03 Jeff Law <law@redhat.com>
3680 PR rtl-optimization/92264
3681 * config/m32r/m32r.c (m32r_output_block_move): Properly account for
3682 post-increment addressing of source operands as well as residuals
3683 when computing any adjustments to the input pointer.
3685 2020-04-03 Jakub Jelinek <jakub@redhat.com>
3688 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
3689 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
3690 second half of first lane from first lane of second operand and
3691 first half of second lane from second lane of first operand.
3693 2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
3695 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.
3697 2020-04-03 Tamar Christina <tamar.christina@arm.com>
3700 * common/config/aarch64/aarch64-common.c
3701 (aarch64_get_extension_string_for_isa_flags): Handle default flags.
3703 2020-04-03 Richard Biener <rguenther@suse.de>
3706 * tree.c (array_ref_low_bound): Deal with released SSA names
3709 2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>
3711 * config/gcn/gcn.c (print_operand): Handle unordered comparison
3713 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
3714 comparison operators.
3716 2020-04-03 Kewen Lin <linkw@gcc.gnu.org>
3718 PR tree-optimization/94443
3719 * tree-vect-loop.c (vectorizable_live_operation): Use
3720 gsi_insert_seq_before to replace gsi_insert_before.
3722 2020-04-03 Martin Liska <mliska@suse.cz>
3725 * ipa-icf-gimple.c (func_checker::compare_gimple_call):
3726 Compare type attributes for gimple_call_fntypes.
3728 2020-04-02 Sandra Loosemore <sandra@codesourcery.com>
3730 * alias.c (get_alias_set): Fix comment typos.
3732 2020-04-02 Fritz Reese <foreese@gcc.gnu.org>
3735 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
3736 attribute checking used by TYPE.
3738 2020-04-02 Martin Jambor <mjambor@suse.cz>
3741 * ipa-sra.c (struct caller_issues): New fields candidate and
3742 call_from_outside_comdat.
3743 (check_for_caller_issues): Check for calls from outsied of
3744 candidate's same_comdat_group.
3745 (check_all_callers_for_issues): Set up issues.candidate, check result
3747 (mark_callers_calls_comdat_local): New function.
3748 (process_isra_node_results): Set calls_comdat_local of callers if
3751 2020-04-02 Richard Biener <rguenther@suse.de>
3754 * common.opt (ffinite-loops): Initialize to zero.
3755 * opts.c (default_options_table): Remove OPT_ffinite_loops
3757 * cfgloop.h (loop::finite_p): New member.
3758 * cfgloopmanip.c (copy_loop_info): Copy finite_p.
3759 * ipa-icf-gimple.c (func_checker::compare_loops): Compare
3761 * lto-streamer-in.c (input_cfg): Stream finite_p.
3762 * lto-streamer-out.c (output_cfg): Likewise.
3763 * tree-cfg.c (replace_loop_annotate): Initialize finite_p
3764 from flag_finite_loops at CFG build time.
3765 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops
3766 finite_p flag instead of flag_finite_loops.
3767 * doc/invoke.texi (ffinite-loops): Adjust documentation of
3770 2020-04-02 Richard Biener <rguenther@suse.de>
3773 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting
3774 DW_TAG_imported_unit.
3776 2020-04-02 Maciej W. Rozycki <macro@wdc.com>
3778 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
3779 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
3782 2020-04-02 Kewen Lin <linkw@gcc.gnu.org>
3784 PR tree-optimization/94401
3785 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
3786 access type when loading halves of vector to avoid peeling for gaps.
3788 2020-04-02 Jakub Jelinek <jakub@redhat.com>
3790 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
3791 between a string literal and MIPS_SYSVERSION_SPEC macro.
3793 2020-04-02 Martin Jambor <mjambor@suse.cz>
3795 * doc/invoke.texi (Optimize Options): Document sra-max-propagations.
3797 2020-04-02 Jakub Jelinek <jakub@redhat.com>
3799 PR rtl-optimization/92264
3800 * params.opt (-param=max-find-base-term-values=): Decrease default
3803 PR rtl-optimization/92264
3804 * rtl.h (struct rtx_def): Mention that call bit is used as
3805 SP_DERIVED_VALUE_P in cselib.c.
3806 * cselib.c (SP_DERIVED_VALUE_P): Define.
3807 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
3808 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
3809 val_rtx and sp based expression where offsets cancel each other.
3810 (preserve_constants_and_equivs): Formatting fix.
3811 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
3812 locs list for cfa_base_preserved_val if needed. Formatting fix.
3813 (autoinc_split): If the to be returned value is a REG, MEM or
3814 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
3815 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
3816 (rtx_equal_for_cselib_1): Call autoinc_split even if both
3817 expressions are PLUS in Pmode with CONST_INT second operands.
3818 Handle SP_DERIVED_VALUE_P cases.
3819 (cselib_hash_plus_const_int): New function.
3820 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
3821 second operand, as well as for PRE_DEC etc. that ought to be
3822 hashed the same way.
3823 (cselib_subst_to_values): Substitute PLUS with Pmode and
3824 CONST_INT operand if the first operand is a VALUE which has
3825 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
3826 SP_DERIVED_VALUE_P + adjusted offset.
3827 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
3828 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding
3829 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
3830 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
3831 on the sp value before calling cselib_add_permanent_equiv on the
3833 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
3834 in the insn without REG_INC note.
3835 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
3836 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes.
3839 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
3840 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
3842 2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3845 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
3846 (LDRGBWBXU_Z_QUALIFIERS): Likewise.
3847 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
3848 intrinsic defintion by adding a new builtin call to writeback into base
3850 (__arm_vldrdq_gather_base_wb_u64): Likewise.
3851 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
3852 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
3853 (__arm_vldrwq_gather_base_wb_s32): Likewise.
3854 (__arm_vldrwq_gather_base_wb_u32): Likewise.
3855 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
3856 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
3857 (__arm_vldrwq_gather_base_wb_f32): Likewise.
3858 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
3859 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
3860 builtin's qualifier.
3861 (vldrdq_gather_base_wb_z_u): Likewise.
3862 (vldrwq_gather_base_wb_u): Likewise.
3863 (vldrdq_gather_base_wb_u): Likewise.
3864 (vldrwq_gather_base_wb_z_s): Likewise.
3865 (vldrwq_gather_base_wb_z_f): Likewise.
3866 (vldrdq_gather_base_wb_z_s): Likewise.
3867 (vldrwq_gather_base_wb_s): Likewise.
3868 (vldrwq_gather_base_wb_f): Likewise.
3869 (vldrdq_gather_base_wb_s): Likewise.
3870 (vldrwq_gather_base_nowb_z_u): Define builtin.
3871 (vldrdq_gather_base_nowb_z_u): Likewise.
3872 (vldrwq_gather_base_nowb_u): Likewise.
3873 (vldrdq_gather_base_nowb_u): Likewise.
3874 (vldrwq_gather_base_nowb_z_s): Likewise.
3875 (vldrwq_gather_base_nowb_z_f): Likewise.
3876 (vldrdq_gather_base_nowb_z_s): Likewise.
3877 (vldrwq_gather_base_nowb_s): Likewise.
3878 (vldrwq_gather_base_nowb_f): Likewise.
3879 (vldrdq_gather_base_nowb_s): Likewise.
3880 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
3882 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
3883 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
3884 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
3885 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
3886 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
3887 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
3888 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
3889 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
3890 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
3891 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
3892 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
3894 2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
3896 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
3897 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
3898 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
3899 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
3900 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
3901 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
3902 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
3903 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
3904 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
3906 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
3907 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
3908 Remove constraints from expander.
3909 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
3910 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
3911 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
3912 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
3913 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
3914 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
3916 2020-04-01 Peter Bergner <bergner@linux.ibm.com>
3918 PR rtl-optimization/94123
3919 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for
3920 flag_split_wide_types_early.
3922 2020-04-01 Joerg Sonnenberger <joerg@bec.de>
3924 * doc/extend.texi (Common Function Attributes): Fix typo.
3926 2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
3929 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
3932 2020-04-01 Zackery Spytz <zspytz@gmail.com>
3934 * doc/extend.texi: Fix a typo in the documentation of the
3935 copy function attribute.
3937 2020-04-01 Jakub Jelinek <jakub@redhat.com>
3940 * tree-object-size.c (pass_object_sizes::execute): Don't call
3941 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
3942 call replace_call_with_value.
3944 2020-04-01 Kewen Lin <linkw@gcc.gnu.org>
3946 PR tree-optimization/94043
3947 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
3948 phi for vec_lhs and use it for lane extraction.
3950 2020-03-31 Felix Yang <felix.yang@huawei.com>
3952 PR tree-optimization/94398
3953 * tree-vect-stmts.c (vectorizable_store): Instead of calling
3954 vect_supportable_dr_alignment, set alignment_support_scheme to
3955 dr_unaligned_supported for gather-scatter accesses.
3956 (vectorizable_load): Likewise.
3958 2020-03-31 Andrew Stubbs <ams@codesourcery.com>
3960 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
3962 (vnsi, VnSI, vndi, VnDI): New mode attributes.
3963 (mov<mode>): Use <VnDI> in place of V64DI.
3964 (mov<mode>_exec): Likewise.
3965 (mov<mode>_sgprbase): Likewise.
3966 (reload_out<mode>): Likewise.
3967 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
3968 (gather_load<mode>v64si): Rename to ...
3969 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
3970 and <VnDI> in place of V64DI.
3971 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
3972 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
3973 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
3974 (scatter_store<mode>v64si): Rename to ...
3975 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
3976 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
3977 (scatter<mode>_insn_1offset<exec_scatter>): Likewise.
3978 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
3979 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
3980 (ds_bpermute<mode>): Use <VnSI>.
3981 (addv64si3_vcc<exec_vcc>): Rename to ...
3982 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
3983 (addv64si3_vcc_dup<exec_vcc>): Rename to ...
3984 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
3985 (addcv64si3<exec_vcc>): Rename to ...
3986 (addc<mode>3<exec_vcc>): ... this, and use V_SI.
3987 (subv64si3_vcc<exec_vcc>): Rename to ...
3988 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
3989 (subcv64si3<exec_vcc>): Rename to ...
3990 (subc<mode>3<exec_vcc>): ... this, and use V_SI.
3991 (addv64di3): Rename to ...
3992 (add<mode>3): ... this, and use V_DI.
3993 (addv64di3_exec): Rename to ...
3994 (add<mode>3_exec): ... this, and use V_DI.
3995 (subv64di3): Rename to ...
3996 (sub<mode>3): ... this, and use V_DI.
3997 (subv64di3_exec): Rename to ...
3998 (sub<mode>3_exec): ... this, and use V_DI.
3999 (addv64di3_zext): Rename to ...
4000 (add<mode>3_zext): ... this, and use V_DI and <VnSI>.
4001 (addv64di3_zext_exec): Rename to ...
4002 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
4003 (addv64di3_zext_dup): Rename to ...
4004 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
4005 (addv64di3_zext_dup_exec): Rename to ...
4006 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
4007 (addv64di3_zext_dup2): Rename to ...
4008 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
4009 (addv64di3_zext_dup2_exec): Rename to ...
4010 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
4011 (addv64di3_sext_dup2): Rename to ...
4012 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
4013 (addv64di3_sext_dup2_exec): Rename to ...
4014 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
4015 (<su>mulv64si3_highpart<exec>): Rename to ...
4016 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
4017 (mulv64di3): Rename to ...
4018 (mul<mode>3): ... this, and use V_DI and <VnSI>.
4019 (mulv64di3_exec): Rename to ...
4020 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
4021 (mulv64di3_zext): Rename to ...
4022 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
4023 (mulv64di3_zext_exec): Rename to ...
4024 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
4025 (mulv64di3_zext_dup2): Rename to ...
4026 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
4027 (mulv64di3_zext_dup2_exec): Rename to ...
4028 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
4029 (<expander>v64di3): Rename to ...
4030 (<expander><mode>3): ... this, and use V_DI and <VnSI>.
4031 (<expander>v64di3_exec): Rename to ...
4032 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
4033 (<expander>v64si3<exec>): Rename to ...
4034 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
4035 (v<expander>v64si3<exec>): Rename to ...
4036 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
4037 (<expander>v64si3<exec>): Rename to ...
4038 (<expander><vnsi>3<exec>): ... this, and use V_SI.
4039 (subv64df3<exec>): Rename to ...
4040 (sub<mode>3<exec>): ... this, and use V_DF.
4041 (truncv64di<mode>2): Rename to ...
4042 (trunc<vndi><mode>2): ... this, and use <VnDI>.
4043 (truncv64di<mode>2_exec): Rename to ...
4044 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
4045 (<convop><mode>v64di2): Rename to ...
4046 (<convop><mode><vndi>2): ... this, and use <VnDI>.
4047 (<convop><mode>v64di2_exec): Rename to ...
4048 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
4049 (vec_cmp<u>v64qidi): Rename to ...
4050 (vec_cmp<u><mode>di): ... this, and use <VnSI>.
4051 (vec_cmp<u>v64qidi_exec): Rename to ...
4052 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
4053 (vcond_mask_<mode>di): Use <VnDI>.
4054 (maskload<mode>di): Likewise.
4055 (maskstore<mode>di): Likewise.
4056 (mask_gather_load<mode>v64si): Rename to ...
4057 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4058 (mask_scatter_store<mode>v64si): Rename to ...
4059 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4060 (*<reduc_op>_dpp_shr_v64di): Rename to ...
4061 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
4062 (*plus_carry_in_dpp_shr_v64si): Rename to ...
4063 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
4064 (*plus_carry_dpp_shr_v64di): Rename to ...
4065 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
4066 (vec_seriesv64si): Rename to ...
4067 (vec_series<mode>): ... this, and use V_SI.
4068 (vec_seriesv64di): Rename to ...
4069 (vec_series<mode>): ... this, and use V_DI.
4071 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
4073 * config/arc/arc.c (arc_print_operand): Use
4074 HOST_WIDE_INT_PRINT_DEC macro.
4076 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
4078 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
4080 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4082 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
4084 (__arm_vbicq): Likewise.
4086 2020-03-31 Vineet Gupta <vgupta@synopsys.com>
4088 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
4090 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4092 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
4093 common section of both MVE Integer and MVE Floating Point.
4095 (vaddlvq_p): Likewise.
4096 (vaddvaq): Likewise.
4097 (vaddvq_p): Likewise.
4098 (vcmpcsq): Likewise.
4099 (vmlsdavxq): Likewise.
4100 (vmlsdavq): Likewise.
4101 (vmladavxq): Likewise.
4102 (vmladavq): Likewise.
4104 (vminavq): Likewise.
4106 (vmaxavq): Likewise.
4107 (vmlaldavq): Likewise.
4108 (vcmphiq): Likewise.
4109 (vaddlvaq): Likewise.
4110 (vrmlaldavhq): Likewise.
4111 (vrmlaldavhxq): Likewise.
4112 (vrmlsldavhq): Likewise.
4113 (vrmlsldavhxq): Likewise.
4114 (vmlsldavxq): Likewise.
4115 (vmlsldavq): Likewise.
4117 (vrmlaldavhaq): Likewise.
4118 (vcmpgeq_m_n): Likewise.
4119 (vmlsdavxq_p): Likewise.
4120 (vmlsdavq_p): Likewise.
4121 (vmlsdavaxq): Likewise.
4122 (vmlsdavaq): Likewise.
4123 (vaddvaq_p): Likewise.
4124 (vcmpcsq_m_n): Likewise.
4125 (vcmpcsq_m): Likewise.
4126 (vmladavxq_p): Likewise.
4127 (vmladavq_p): Likewise.
4128 (vmladavaxq): Likewise.
4129 (vmladavaq): Likewise.
4130 (vminvq_p): Likewise.
4131 (vminavq_p): Likewise.
4132 (vmaxvq_p): Likewise.
4133 (vmaxavq_p): Likewise.
4134 (vcmphiq_m): Likewise.
4135 (vaddlvaq_p): Likewise.
4136 (vmlaldavaq): Likewise.
4137 (vmlaldavaxq): Likewise.
4138 (vmlaldavq_p): Likewise.
4139 (vmlaldavxq_p): Likewise.
4140 (vmlsldavaq): Likewise.
4141 (vmlsldavaxq): Likewise.
4142 (vmlsldavq_p): Likewise.
4143 (vmlsldavxq_p): Likewise.
4144 (vrmlaldavhaxq): Likewise.
4145 (vrmlaldavhq_p): Likewise.
4146 (vrmlaldavhxq_p): Likewise.
4147 (vrmlsldavhaq): Likewise.
4148 (vrmlsldavhaxq): Likewise.
4149 (vrmlsldavhq_p): Likewise.
4150 (vrmlsldavhxq_p): Likewise.
4151 (vabavq_p): Likewise.
4152 (vmladavaq_p): Likewise.
4153 (vstrbq_scatter_offset): Likewise.
4154 (vstrbq_p): Likewise.
4155 (vstrbq_scatter_offset_p): Likewise.
4156 (vstrdq_scatter_base_p): Likewise.
4157 (vstrdq_scatter_base): Likewise.
4158 (vstrdq_scatter_offset_p): Likewise.
4159 (vstrdq_scatter_offset): Likewise.
4160 (vstrdq_scatter_shifted_offset_p): Likewise.
4161 (vstrdq_scatter_shifted_offset): Likewise.
4162 (vmaxq_x): Likewise.
4163 (vminq_x): Likewise.
4164 (vmovlbq_x): Likewise.
4165 (vmovltq_x): Likewise.
4166 (vmulhq_x): Likewise.
4167 (vmullbq_int_x): Likewise.
4168 (vmullbq_poly_x): Likewise.
4169 (vmulltq_int_x): Likewise.
4170 (vmulltq_poly_x): Likewise.
4173 2020-03-31 Jakub Jelinek <jakub@redhat.com>
4176 * config/aarch64/constraints.md (Uph): New constraint.
4177 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
4178 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
4181 2020-03-31 Marc Glisse <marc.glisse@inria.fr>
4182 Jakub Jelinek <jakub@redhat.com>
4185 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
4186 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
4188 2020-03-31 Jakub Jelinek <jakub@redhat.com>
4190 PR tree-optimization/94403
4191 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
4192 ENUMERAL_TYPE lhs_type.
4194 PR rtl-optimization/94344
4195 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
4196 conversions, either on both operands of |^+ or just one. Handle
4197 also extra same precision conversion on RSHIFT_EXPR first operand
4198 provided RSHIFT_EXPR is performed in unsigned type.
4200 2020-03-30 David Malcolm <dmalcolm@redhat.com>
4202 * lra.c (finish_insn_code_data_once): Set the array elements
4203 to NULL after freeing them.
4205 2020-03-30 Andreas Schwab <schwab@suse.de>
4207 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
4210 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
4212 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
4213 to skip defining builtins based on builtin_mask.
4215 2020-03-30 Jakub Jelinek <jakub@redhat.com>
4218 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
4219 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
4220 operand is a register. Don't enable masked variants for V*[QH]Imode.
4223 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
4224 <store_mask_constraint> instead of m in output operand constraint.
4225 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
4228 2020-03-30 Alan Modra <amodra@gmail.com>
4230 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
4231 (rs6000_indirect_call_template_1): Adjust to suit.
4232 * config/rs6000/rs6000.md (call_local): Merge call_local32,
4233 call_local64, and call_local_aix.
4234 (call_value_local): Simlarly.
4235 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
4236 and disable pattern when CALL_LONG.
4237 (call_indirect_aix, call_value_indirect_aix): Adjust rtl.
4238 (call_indirect_elfv2, call_indirect_pcrel): Likewise.
4239 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
4241 2020-03-29 H.J. Lu <hongjiu.lu@intel.com>
4244 * doc/invoke.texi: Update -falign-functions, -falign-loops and
4245 -falign-jumps documentation.
4247 2020-03-29 Martin Liska <mliska@suse.cz>
4250 * cgraphunit.c (process_function_and_variable_attributes): Remove
4251 double 'attribute' words.
4253 2020-03-29 John David Anglin <dave.anglin@bell.net>
4255 * config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
4258 2020-03-28 Jakub Jelinek <jakub@redhat.com>
4261 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const
4262 to true after setting size to integer_one_node.
4264 PR tree-optimization/94329
4265 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
4266 on the last stmt in a bb, make sure gsi_prev isn't done immediately
4269 2020-03-27 Alan Modra <amodra@gmail.com>
4272 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
4273 for PLT16_LO and PLT_PCREL.
4274 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
4275 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
4276 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
4278 2020-03-27 Martin Sebor <msebor@redhat.com>
4281 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes.
4283 2020-03-27 Andrew Stubbs <ams@codesourcery.com>
4285 * config/gcn/gcn-valu.md:
4286 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
4287 (VEC_1REG_MODE): Delete.
4288 (VEC_1REG_ALT): Delete.
4289 (VEC_ALL1REG_MODE): Rename to V_1REG throughout.
4290 (VEC_1REG_INT_MODE): Delete.
4291 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
4292 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
4293 (VEC_2REG_MODE): Rename to V_2REG throughout.
4294 (VEC_REG_MODE): Rename to V_noHI throughout.
4295 (VEC_ALLREG_MODE): Rename to V_ALL throughout.
4296 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout.
4297 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
4298 (VEC_INT_MODE): Delete.
4299 (VEC_FP_MODE): Rename to V_FP throughout and move to top.
4300 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
4301 (FP_MODE): Delete and replace with FP throughout.
4302 (FP_1REG_MODE): Delete and replace with FP_1REG throughout.
4303 (VCMP_MODE): Rename to V_noQI throughout and move to top.
4304 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
4305 * config/gcn/gcn.md (FP): New mode iterator.
4306 (FP_1REG): New mode iterator.
4308 2020-03-27 David Malcolm <dmalcolm@redhat.com>
4310 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this
4311 now emits two .dot files.
4312 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD.
4313 (graphviz_out::end_tr): Only close a TR, not a TD.
4314 (graphviz_out::begin_td): New.
4315 (graphviz_out::end_td): New.
4316 (graphviz_out::begin_trtd): New, replacing the old implementation
4317 of graphviz_out::begin_tr.
4318 (graphviz_out::end_tdtr): New, replacing the old implementation
4319 of graphviz_out::end_tr.
4320 * graphviz.h (graphviz_out::begin_td): New decl.
4321 (graphviz_out::end_td): New decl.
4322 (graphviz_out::begin_trtd): New decl.
4323 (graphviz_out::end_tdtr): New decl.
4325 2020-03-27 Richard Biener <rguenther@suse.de>
4328 * dwarf2out.c (should_emit_struct_debug): Return false for
4331 2020-03-27 Richard Biener <rguenther@suse.de>
4333 PR tree-optimization/94352
4334 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the
4336 (ssa_propagation_engine::ssa_propagate): ... here after
4337 initializing curr_order.
4339 2020-03-27 Kewen Lin <linkw@gcc.gnu.org>
4341 PR tree-optimization/90332
4342 * tree-vect-stmts.c (vector_vector_composition_type): New function.
4343 (get_group_load_store_type): Adjust to call
4344 vector_vector_composition_type, extend it to construct with scalar
4346 (vectorizable_load): Likewise.
4348 2020-03-27 Roman Zhuykov <zhroma@ispras.ru>
4350 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions.
4351 (create_ddg_dep_no_link): Likewise.
4352 (add_cross_iteration_register_deps): Move debug instruction check.
4353 Other minor refactoring.
4354 (add_intra_loop_mem_dep): Do not check for debug instructions.
4355 (add_inter_loop_mem_dep): Likewise.
4356 (build_intra_loop_deps): Likewise.
4357 (create_ddg): Do not include debug insns into the graph.
4358 * ddg.h (struct ddg): Remove num_debug field.
4359 * modulo-sched.c (doloop_register_get): Adjust condition.
4360 (res_MII): Remove DDG num_debug field usage.
4361 (sms_schedule_by_order): Use assertion against debug insns.
4362 (ps_has_conflicts): Drop debug insn check.
4364 2020-03-26 Jakub Jelinek <jakub@redhat.com>
4367 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST
4368 that contains exactly one non-DEBUG_BEGIN_STMT statement.
4371 * gimple.h (gimple_seq_first_nondebug_stmt): New function.
4372 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains
4373 a single non-debug stmt followed by one or more debug stmts.
4374 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt
4375 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt
4376 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and
4377 gimple_seq_last to check if outer_stmt gbind could be reused and
4378 if yes and it is surrounded by any debug stmts, move them into the
4381 PR rtl-optimization/92264
4382 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even
4383 for sp based values in !frame_pointer_needed
4384 && !ACCUMULATE_OUTGOING_ARGS functions.
4386 2020-03-26 Felix Yang <felix.yang@huawei.com>
4388 PR tree-optimization/94269
4389 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict
4391 operation to single basic block.
4393 2020-03-25 Jeff Law <law@redhat.com>
4395 PR rtl-optimization/90275
4396 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
4399 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4402 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to
4403 mode rather than VOIDmode.
4405 2020-03-25 Martin Sebor <msebor@redhat.com>
4408 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings
4409 even for alloca calls resulting from system macro expansion.
4410 Include inlining context in all warnings.
4412 2020-03-25 Richard Sandiford <richard.sandiford@arm.com>
4415 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
4416 FPRs to change between SDmode and DDmode.
4418 2020-03-25 Martin Sebor <msebor@redhat.com>
4420 PR tree-optimization/94131
4421 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length
4423 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming
4424 types have constant sizes.
4426 2020-03-25 Martin Liska <mliska@suse.cz>
4429 * configure.ac: Report error only when --with-zstd
4431 * configure: Regenerate.
4433 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4436 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
4437 INSN_CODE (insn) to -1 when changing the pattern.
4439 2020-03-25 Martin Liska <mliska@suse.cz>
4443 * config/i386/i386-features.c (make_resolver_func): Drop
4444 public flag for resolver.
4445 * config/rs6000/rs6000.c (make_resolver_func): Add comdat
4446 group for resolver and drop public flag if possible.
4447 * multiple_target.c (create_dispatcher_calls): Drop unique_name
4448 and resolution as we want to enable LTO privatization of the default
4451 2020-03-25 Martin Liska <mliska@suse.cz>
4454 * configure.ac: Respect --without-zstd and report
4455 error when we can't find header file with --with-zstd.
4456 * configure: Regenerate.
4458 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4461 * varasm.c (output_constructor_array_range): If local->index
4462 RANGE_EXPR doesn't start at the current location in the constructor,
4463 skip needed number of bytes using assemble_zeros or assert we don't
4467 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong
4468 counter instead of DECL_UID.
4470 PR tree-optimization/94300
4471 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset
4472 is positive, make sure that off + size isn't larger than needed_len.
4474 2020-03-25 Richard Biener <rguenther@suse.de>
4475 Jakub Jelinek <jakub@redhat.com>
4478 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
4480 2020-03-24 Christophe Lyon <christophe.lyon@linaro.org>
4482 * doc/sourcebuild.texi (ARM-specific attributes): Add
4484 (Features for dg-add-options): Add arm_fp_dp.
4486 2020-03-24 John David Anglin <danglin@gcc.gnu.org>
4489 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
4491 2020-03-24 Tobias Burnus <tobias@codesourcery.com>
4494 * omp-offload.c (omp_finish_file): Fix target-link handling if
4495 targetm_common.have_named_sections is false.
4497 2020-03-24 Jakub Jelinek <jakub@redhat.com>
4500 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
4504 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
4505 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.
4506 If not after and at *incr_pos is a debug stmt, set stmt location to
4507 location of next non-debug stmt after it if any.
4510 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
4511 GF_PLF_2, but don't add them to worklist. Don't add an assigment to
4512 worklist or set GF_PLF_2 just because it is used in a debug stmt in
4513 another bb. Formatting improvements.
4516 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and
4517 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC
4518 regardless of whether TREE_NO_WARNING is set on it or whether
4519 warn_unused_function is true or not.
4521 2020-03-23 Jeff Law <law@redhat.com>
4523 PR rtl-optimization/90275
4526 * simplify-rtx.c (comparison_code_valid_for_mode): New function.
4527 (simplify_logical_relational_operation): Use it.
4529 2020-03-23 Jakub Jelinek <jakub@redhat.com>
4532 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on
4533 ultimate rhs and if returned something different, reconstructing
4536 2020-03-23 Lewis Hyatt <lhyatt@gmail.com>
4538 * opts.c (print_filtered_help): Improve the help text for alias options.
4540 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4541 Andre Vieira <andre.simoesdiasvieira@arm.com>
4542 Mihail Ionescu <mihail.ionescu@arm.com>
4544 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
4545 (vshlcq_m_u8): Likewise.
4546 (vshlcq_m_s16): Likewise.
4547 (vshlcq_m_u16): Likewise.
4548 (vshlcq_m_s32): Likewise.
4549 (vshlcq_m_u32): Likewise.
4550 (__arm_vshlcq_m_s8): Define intrinsic.
4551 (__arm_vshlcq_m_u8): Likewise.
4552 (__arm_vshlcq_m_s16): Likewise.
4553 (__arm_vshlcq_m_u16): Likewise.
4554 (__arm_vshlcq_m_s32): Likewise.
4555 (__arm_vshlcq_m_u32): Likewise.
4556 (vshlcq_m): Define polymorphic variant.
4557 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
4558 Use builtin qualifier.
4559 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
4560 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern.
4561 (mve_vshlcq_m_carry_<supf><mode>): Likewise.
4562 (mve_vshlcq_m_<supf><mode>): Likewise.
4564 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4566 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
4567 (UQSHL_QUALIFIERS): Likewise.
4568 (ASRL_QUALIFIERS): Likewise.
4569 (SQSHL_QUALIFIERS): Likewise.
4570 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
4572 (sqrshr): Define macro.
4573 (sqrshrl): Likewise.
4574 (sqrshrl_sat48): Likewise.
4580 (uqrshll): Likewise.
4581 (uqrshll_sat48): Likewise.
4588 (__arm_lsll): Define intrinsic.
4589 (__arm_asrl): Likewise.
4590 (__arm_uqrshll): Likewise.
4591 (__arm_uqrshll_sat48): Likewise.
4592 (__arm_sqrshrl): Likewise.
4593 (__arm_sqrshrl_sat48): Likewise.
4594 (__arm_uqshll): Likewise.
4595 (__arm_urshrl): Likewise.
4596 (__arm_srshrl): Likewise.
4597 (__arm_sqshll): Likewise.
4598 (__arm_uqrshl): Likewise.
4599 (__arm_sqrshr): Likewise.
4600 (__arm_uqshl): Likewise.
4601 (__arm_urshr): Likewise.
4602 (__arm_sqshl): Likewise.
4603 (__arm_srshr): Likewise.
4604 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
4606 (UQSHL_QUALIFIERS): Likewise.
4607 (ASRL_QUALIFIERS): Likewise.
4608 (SQSHL_QUALIFIERS): Likewise.
4609 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
4610 (mve_sqrshrl_sat<supf>_di): Likewise.
4611 (mve_uqrshl_si): Likewise.
4612 (mve_sqrshr_si): Likewise.
4613 (mve_uqshll_di): Likewise.
4614 (mve_urshrl_di): Likewise.
4615 (mve_uqshl_si): Likewise.
4616 (mve_urshr_si): Likewise.
4617 (mve_sqshl_si): Likewise.
4618 (mve_srshr_si): Likewise.
4619 (mve_srshrl_di): Likewise.
4620 (mve_sqshll_di): Likewise.
4622 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4623 Andre Vieira <andre.simoesdiasvieira@arm.com>
4624 Mihail Ionescu <mihail.ionescu@arm.com>
4626 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro.
4627 (vsetq_lane_f32): Likewise.
4628 (vsetq_lane_s16): Likewise.
4629 (vsetq_lane_s32): Likewise.
4630 (vsetq_lane_s8): Likewise.
4631 (vsetq_lane_s64): Likewise.
4632 (vsetq_lane_u8): Likewise.
4633 (vsetq_lane_u16): Likewise.
4634 (vsetq_lane_u32): Likewise.
4635 (vsetq_lane_u64): Likewise.
4636 (vgetq_lane_f16): Likewise.
4637 (vgetq_lane_f32): Likewise.
4638 (vgetq_lane_s16): Likewise.
4639 (vgetq_lane_s32): Likewise.
4640 (vgetq_lane_s8): Likewise.
4641 (vgetq_lane_s64): Likewise.
4642 (vgetq_lane_u8): Likewise.
4643 (vgetq_lane_u16): Likewise.
4644 (vgetq_lane_u32): Likewise.
4645 (vgetq_lane_u64): Likewise.
4646 (__ARM_NUM_LANES): Likewise.
4647 (__ARM_LANEQ): Likewise.
4648 (__ARM_CHECK_LANEQ): Likewise.
4649 (__arm_vsetq_lane_s16): Define intrinsic.
4650 (__arm_vsetq_lane_s32): Likewise.
4651 (__arm_vsetq_lane_s8): Likewise.
4652 (__arm_vsetq_lane_s64): Likewise.
4653 (__arm_vsetq_lane_u8): Likewise.
4654 (__arm_vsetq_lane_u16): Likewise.
4655 (__arm_vsetq_lane_u32): Likewise.
4656 (__arm_vsetq_lane_u64): Likewise.
4657 (__arm_vgetq_lane_s16): Likewise.
4658 (__arm_vgetq_lane_s32): Likewise.
4659 (__arm_vgetq_lane_s8): Likewise.
4660 (__arm_vgetq_lane_s64): Likewise.
4661 (__arm_vgetq_lane_u8): Likewise.
4662 (__arm_vgetq_lane_u16): Likewise.
4663 (__arm_vgetq_lane_u32): Likewise.
4664 (__arm_vgetq_lane_u64): Likewise.
4665 (__arm_vsetq_lane_f16): Likewise.
4666 (__arm_vsetq_lane_f32): Likewise.
4667 (__arm_vgetq_lane_f16): Likewise.
4668 (__arm_vgetq_lane_f32): Likewise.
4669 (vgetq_lane): Define polymorphic variant.
4670 (vsetq_lane): Likewise.
4671 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL
4673 (mve_vec_extractv2didi): Likewise.
4674 (mve_vec_extract_sext_internal<mode>): Likewise.
4675 (mve_vec_extract_zext_internal<mode>): Likewise.
4676 (mve_vec_set<mode>_internal): Likewise.
4677 (mve_vec_setv2di_internal): Likewise.
4678 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md
4680 (vec_extract<mode><V_elem_l>): Rename to
4681 "neon_vec_extract<mode><V_elem_l>".
4682 (vec_extractv2didi): Rename to "neon_vec_extractv2didi".
4683 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL
4684 pattern common for MVE and NEON.
4685 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both
4688 2020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
4690 * config/arm/mve.md (earlyclobber_32): New mode attribute.
4691 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
4692 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
4694 2020-03-23 Richard Biener <rguenther@suse.de>
4696 PR tree-optimization/94261
4697 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove
4698 IL operand swapping code.
4699 (vect_slp_rearrange_stmts): Do not arrange isomorphic
4700 nodes that would need operation code adjustments.
4702 2020-03-23 Tobias Burnus <tobias@codesourcery.com>
4704 * doc/install.texi (amdgcn-*-amdhsa): Renamed
4705 from amdgcn-unknown-amdhsa; change
4706 amdgcn-unknown-amdhsa to amdgcn-amdhsa.
4708 2020-03-23 Richard Biener <rguenther@suse.de>
4711 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP
4712 directly rather than also folding it via build_fold_addr_expr.
4714 2020-03-23 Richard Biener <rguenther@suse.de>
4716 PR tree-optimization/94266
4717 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate
4718 addresses of TARGET_MEM_REFs.
4720 2020-03-23 Martin Liska <mliska@suse.cz>
4723 * symtab.c (symtab_node::clone_references): Save speculative_id
4724 as ref may be overwritten by create_reference.
4725 (symtab_node::clone_referring): Likewise.
4726 (symtab_node::clone_reference): Likewise.
4728 2020-03-22 Iain Sandoe <iain@sandoe.co.uk>
4730 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
4731 references to Darwin.
4732 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
4733 unconditionally and comment on why.
4735 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
4737 * config/darwin.c (darwin_mergeable_constant_section): Collect
4738 section anchor checks into the caller.
4739 (machopic_select_section): Collect section anchor checks into
4740 the determination of 'effective zero-size' objects. When the
4741 size is unknown, assume it is non-zero, and thus return the
4742 'generic' section for the DECL.
4744 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
4747 * config/darwin.opt: Amend options descriptions.
4749 2020-03-21 Richard Sandiford <richard.sandiford@arm.com>
4751 PR rtl-optimization/94052
4752 * lra-constraints.c (simplify_operand_subreg): Reload the inner
4753 register of a paradoxical subreg if simplify_subreg_regno fails
4754 to give a valid hard register for the outer mode.
4756 2020-03-20 Martin Jambor <mjambor@suse.cz>
4758 PR tree-optimization/93435
4759 * params.opt (sra-max-propagations): New parameter.
4760 * tree-sra.c (propagation_budget): New variable.
4761 (budget_for_propagation_access): New function.
4762 (propagate_subaccesses_from_rhs): Use it.
4763 (propagate_subaccesses_from_lhs): Likewise.
4764 (propagate_all_subaccesses): Set up and destroy propagation_budget.
4766 2020-03-20 Carl Love <cel@us.ibm.com>
4769 * config/rs6000/rs6000.c (rs6000_option_override_internal):
4770 Add check for TARGET_FPRND for Power 7 or newer.
4772 2020-03-20 Jan Hubicka <hubicka@ucw.cz>
4775 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag.
4776 (cgraph_edge::redirect_callee): Move here; likewise.
4777 (cgraph_node::remove_callees): Update calls_comdat_local flag.
4778 (cgraph_node::verify_node): Verify that calls_comdat_local flag match
4780 (cgraph_node::check_calls_comdat_local_p): New member function.
4781 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare.
4782 (cgraph_edge::redirect_callee): Move offline.
4783 * ipa-fnsummary.c (compute_fn_summary): Do not compute
4784 calls_comdat_local flag here.
4785 * ipa-inline-transform.c (inline_call): Fix updating of
4786 calls_comdat_local flag.
4787 * ipa-split.c (split_function): Use true instead of 1 to set the flag.
4788 * symtab.c (symtab_node::add_to_same_comdat_group): Update
4789 calls_comdat_local flag.
4791 2020-03-20 Richard Biener <rguenther@suse.de>
4793 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree
4794 from the possibly modified root.
4796 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4797 Andre Vieira <andre.simoesdiasvieira@arm.com>
4798 Mihail Ionescu <mihail.ionescu@arm.com>
4800 * config/arm/arm_mve.h (vst1q_p_u8): Define macro.
4801 (vst1q_p_s8): Likewise.
4802 (vst2q_s8): Likewise.
4803 (vst2q_u8): Likewise.
4804 (vld1q_z_u8): Likewise.
4805 (vld1q_z_s8): Likewise.
4806 (vld2q_s8): Likewise.
4807 (vld2q_u8): Likewise.
4808 (vld4q_s8): Likewise.
4809 (vld4q_u8): Likewise.
4810 (vst1q_p_u16): Likewise.
4811 (vst1q_p_s16): Likewise.
4812 (vst2q_s16): Likewise.
4813 (vst2q_u16): Likewise.
4814 (vld1q_z_u16): Likewise.
4815 (vld1q_z_s16): Likewise.
4816 (vld2q_s16): Likewise.
4817 (vld2q_u16): Likewise.
4818 (vld4q_s16): Likewise.
4819 (vld4q_u16): Likewise.
4820 (vst1q_p_u32): Likewise.
4821 (vst1q_p_s32): Likewise.
4822 (vst2q_s32): Likewise.
4823 (vst2q_u32): Likewise.
4824 (vld1q_z_u32): Likewise.
4825 (vld1q_z_s32): Likewise.
4826 (vld2q_s32): Likewise.
4827 (vld2q_u32): Likewise.
4828 (vld4q_s32): Likewise.
4829 (vld4q_u32): Likewise.
4830 (vld4q_f16): Likewise.
4831 (vld2q_f16): Likewise.
4832 (vld1q_z_f16): Likewise.
4833 (vst2q_f16): Likewise.
4834 (vst1q_p_f16): Likewise.
4835 (vld4q_f32): Likewise.
4836 (vld2q_f32): Likewise.
4837 (vld1q_z_f32): Likewise.
4838 (vst2q_f32): Likewise.
4839 (vst1q_p_f32): Likewise.
4840 (__arm_vst1q_p_u8): Define intrinsic.
4841 (__arm_vst1q_p_s8): Likewise.
4842 (__arm_vst2q_s8): Likewise.
4843 (__arm_vst2q_u8): Likewise.
4844 (__arm_vld1q_z_u8): Likewise.
4845 (__arm_vld1q_z_s8): Likewise.
4846 (__arm_vld2q_s8): Likewise.
4847 (__arm_vld2q_u8): Likewise.
4848 (__arm_vld4q_s8): Likewise.
4849 (__arm_vld4q_u8): Likewise.
4850 (__arm_vst1q_p_u16): Likewise.
4851 (__arm_vst1q_p_s16): Likewise.
4852 (__arm_vst2q_s16): Likewise.
4853 (__arm_vst2q_u16): Likewise.
4854 (__arm_vld1q_z_u16): Likewise.
4855 (__arm_vld1q_z_s16): Likewise.
4856 (__arm_vld2q_s16): Likewise.
4857 (__arm_vld2q_u16): Likewise.
4858 (__arm_vld4q_s16): Likewise.
4859 (__arm_vld4q_u16): Likewise.
4860 (__arm_vst1q_p_u32): Likewise.
4861 (__arm_vst1q_p_s32): Likewise.
4862 (__arm_vst2q_s32): Likewise.
4863 (__arm_vst2q_u32): Likewise.
4864 (__arm_vld1q_z_u32): Likewise.
4865 (__arm_vld1q_z_s32): Likewise.
4866 (__arm_vld2q_s32): Likewise.
4867 (__arm_vld2q_u32): Likewise.
4868 (__arm_vld4q_s32): Likewise.
4869 (__arm_vld4q_u32): Likewise.
4870 (__arm_vld4q_f16): Likewise.
4871 (__arm_vld2q_f16): Likewise.
4872 (__arm_vld1q_z_f16): Likewise.
4873 (__arm_vst2q_f16): Likewise.
4874 (__arm_vst1q_p_f16): Likewise.
4875 (__arm_vld4q_f32): Likewise.
4876 (__arm_vld2q_f32): Likewise.
4877 (__arm_vld1q_z_f32): Likewise.
4878 (__arm_vst2q_f32): Likewise.
4879 (__arm_vst1q_p_f32): Likewise.
4880 (vld1q_z): Define polymorphic variant.
4883 (vst1q_p): Likewise.
4885 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier.
4887 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern.
4888 (mve_vld2q<mode>): Likewise.
4889 (mve_vld4q<mode>): Likewise.
4891 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4892 Andre Vieira <andre.simoesdiasvieira@arm.com>
4893 Mihail Ionescu <mihail.ionescu@arm.com>
4895 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define.
4896 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise.
4897 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and
4898 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array.
4899 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC
4900 and ARM_BUILTIN_SET_FPSCR_NZCVQC.
4901 * config/arm/arm_mve.h (vadciq_s32): Define macro.
4902 (vadciq_u32): Likewise.
4903 (vadciq_m_s32): Likewise.
4904 (vadciq_m_u32): Likewise.
4905 (vadcq_s32): Likewise.
4906 (vadcq_u32): Likewise.
4907 (vadcq_m_s32): Likewise.
4908 (vadcq_m_u32): Likewise.
4909 (vsbciq_s32): Likewise.
4910 (vsbciq_u32): Likewise.
4911 (vsbciq_m_s32): Likewise.
4912 (vsbciq_m_u32): Likewise.
4913 (vsbcq_s32): Likewise.
4914 (vsbcq_u32): Likewise.
4915 (vsbcq_m_s32): Likewise.
4916 (vsbcq_m_u32): Likewise.
4917 (__arm_vadciq_s32): Define intrinsic.
4918 (__arm_vadciq_u32): Likewise.
4919 (__arm_vadciq_m_s32): Likewise.
4920 (__arm_vadciq_m_u32): Likewise.
4921 (__arm_vadcq_s32): Likewise.
4922 (__arm_vadcq_u32): Likewise.
4923 (__arm_vadcq_m_s32): Likewise.
4924 (__arm_vadcq_m_u32): Likewise.
4925 (__arm_vsbciq_s32): Likewise.
4926 (__arm_vsbciq_u32): Likewise.
4927 (__arm_vsbciq_m_s32): Likewise.
4928 (__arm_vsbciq_m_u32): Likewise.
4929 (__arm_vsbcq_s32): Likewise.
4930 (__arm_vsbcq_u32): Likewise.
4931 (__arm_vsbcq_m_s32): Likewise.
4932 (__arm_vsbcq_m_u32): Likewise.
4933 (vadciq_m): Define polymorphic variant.
4935 (vadcq_m): Likewise.
4937 (vsbciq_m): Likewise.
4939 (vsbcq_m): Likewise.
4941 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin
4943 (BINOP_UNONE_UNONE_UNONE): Likewise.
4944 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
4945 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
4946 * config/arm/mve.md (VADCIQ): Define iterator.
4947 (VADCIQ_M): Likewise.
4949 (VSBCQ_M): Likewise.
4951 (VSBCIQ_M): Likewise.
4953 (VADCQ_M): Likewise.
4954 (mve_vadciq_m_<supf>v4si): Define RTL pattern.
4955 (mve_vadciq_<supf>v4si): Likewise.
4956 (mve_vadcq_m_<supf>v4si): Likewise.
4957 (mve_vadcq_<supf>v4si): Likewise.
4958 (mve_vsbciq_m_<supf>v4si): Likewise.
4959 (mve_vsbciq_<supf>v4si): Likewise.
4960 (mve_vsbcq_m_<supf>v4si): Likewise.
4961 (mve_vsbcq_<supf>v4si): Likewise.
4962 (get_fpscr_nzcvqc): Define isns.
4963 (set_fpscr_nzcvqc): Define isns.
4964 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define.
4965 (UNSPEC_SET_FPSCR_NZCVQC): Define.
4967 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4969 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
4970 (vddupq_x_n_u16): Likewise.
4971 (vddupq_x_n_u32): Likewise.
4972 (vddupq_x_wb_u8): Likewise.
4973 (vddupq_x_wb_u16): Likewise.
4974 (vddupq_x_wb_u32): Likewise.
4975 (vdwdupq_x_n_u8): Likewise.
4976 (vdwdupq_x_n_u16): Likewise.
4977 (vdwdupq_x_n_u32): Likewise.
4978 (vdwdupq_x_wb_u8): Likewise.
4979 (vdwdupq_x_wb_u16): Likewise.
4980 (vdwdupq_x_wb_u32): Likewise.
4981 (vidupq_x_n_u8): Likewise.
4982 (vidupq_x_n_u16): Likewise.
4983 (vidupq_x_n_u32): Likewise.
4984 (vidupq_x_wb_u8): Likewise.
4985 (vidupq_x_wb_u16): Likewise.
4986 (vidupq_x_wb_u32): Likewise.
4987 (viwdupq_x_n_u8): Likewise.
4988 (viwdupq_x_n_u16): Likewise.
4989 (viwdupq_x_n_u32): Likewise.
4990 (viwdupq_x_wb_u8): Likewise.
4991 (viwdupq_x_wb_u16): Likewise.
4992 (viwdupq_x_wb_u32): Likewise.
4993 (vdupq_x_n_s8): Likewise.
4994 (vdupq_x_n_s16): Likewise.
4995 (vdupq_x_n_s32): Likewise.
4996 (vdupq_x_n_u8): Likewise.
4997 (vdupq_x_n_u16): Likewise.
4998 (vdupq_x_n_u32): Likewise.
4999 (vminq_x_s8): Likewise.
5000 (vminq_x_s16): Likewise.
5001 (vminq_x_s32): Likewise.
5002 (vminq_x_u8): Likewise.
5003 (vminq_x_u16): Likewise.
5004 (vminq_x_u32): Likewise.
5005 (vmaxq_x_s8): Likewise.
5006 (vmaxq_x_s16): Likewise.
5007 (vmaxq_x_s32): Likewise.
5008 (vmaxq_x_u8): Likewise.
5009 (vmaxq_x_u16): Likewise.
5010 (vmaxq_x_u32): Likewise.
5011 (vabdq_x_s8): Likewise.
5012 (vabdq_x_s16): Likewise.
5013 (vabdq_x_s32): Likewise.
5014 (vabdq_x_u8): Likewise.
5015 (vabdq_x_u16): Likewise.
5016 (vabdq_x_u32): Likewise.
5017 (vabsq_x_s8): Likewise.
5018 (vabsq_x_s16): Likewise.
5019 (vabsq_x_s32): Likewise.
5020 (vaddq_x_s8): Likewise.
5021 (vaddq_x_s16): Likewise.
5022 (vaddq_x_s32): Likewise.
5023 (vaddq_x_n_s8): Likewise.
5024 (vaddq_x_n_s16): Likewise.
5025 (vaddq_x_n_s32): Likewise.
5026 (vaddq_x_u8): Likewise.
5027 (vaddq_x_u16): Likewise.
5028 (vaddq_x_u32): Likewise.
5029 (vaddq_x_n_u8): Likewise.
5030 (vaddq_x_n_u16): Likewise.
5031 (vaddq_x_n_u32): Likewise.
5032 (vclsq_x_s8): Likewise.
5033 (vclsq_x_s16): Likewise.
5034 (vclsq_x_s32): Likewise.
5035 (vclzq_x_s8): Likewise.
5036 (vclzq_x_s16): Likewise.
5037 (vclzq_x_s32): Likewise.
5038 (vclzq_x_u8): Likewise.
5039 (vclzq_x_u16): Likewise.
5040 (vclzq_x_u32): Likewise.
5041 (vnegq_x_s8): Likewise.
5042 (vnegq_x_s16): Likewise.
5043 (vnegq_x_s32): Likewise.
5044 (vmulhq_x_s8): Likewise.
5045 (vmulhq_x_s16): Likewise.
5046 (vmulhq_x_s32): Likewise.
5047 (vmulhq_x_u8): Likewise.
5048 (vmulhq_x_u16): Likewise.
5049 (vmulhq_x_u32): Likewise.
5050 (vmullbq_poly_x_p8): Likewise.
5051 (vmullbq_poly_x_p16): Likewise.
5052 (vmullbq_int_x_s8): Likewise.
5053 (vmullbq_int_x_s16): Likewise.
5054 (vmullbq_int_x_s32): Likewise.
5055 (vmullbq_int_x_u8): Likewise.
5056 (vmullbq_int_x_u16): Likewise.
5057 (vmullbq_int_x_u32): Likewise.
5058 (vmulltq_poly_x_p8): Likewise.
5059 (vmulltq_poly_x_p16): Likewise.
5060 (vmulltq_int_x_s8): Likewise.
5061 (vmulltq_int_x_s16): Likewise.
5062 (vmulltq_int_x_s32): Likewise.
5063 (vmulltq_int_x_u8): Likewise.
5064 (vmulltq_int_x_u16): Likewise.
5065 (vmulltq_int_x_u32): Likewise.
5066 (vmulq_x_s8): Likewise.
5067 (vmulq_x_s16): Likewise.
5068 (vmulq_x_s32): Likewise.
5069 (vmulq_x_n_s8): Likewise.
5070 (vmulq_x_n_s16): Likewise.
5071 (vmulq_x_n_s32): Likewise.
5072 (vmulq_x_u8): Likewise.
5073 (vmulq_x_u16): Likewise.
5074 (vmulq_x_u32): Likewise.
5075 (vmulq_x_n_u8): Likewise.
5076 (vmulq_x_n_u16): Likewise.
5077 (vmulq_x_n_u32): Likewise.
5078 (vsubq_x_s8): Likewise.
5079 (vsubq_x_s16): Likewise.
5080 (vsubq_x_s32): Likewise.
5081 (vsubq_x_n_s8): Likewise.
5082 (vsubq_x_n_s16): Likewise.
5083 (vsubq_x_n_s32): Likewise.
5084 (vsubq_x_u8): Likewise.
5085 (vsubq_x_u16): Likewise.
5086 (vsubq_x_u32): Likewise.
5087 (vsubq_x_n_u8): Likewise.
5088 (vsubq_x_n_u16): Likewise.
5089 (vsubq_x_n_u32): Likewise.
5090 (vcaddq_rot90_x_s8): Likewise.
5091 (vcaddq_rot90_x_s16): Likewise.
5092 (vcaddq_rot90_x_s32): Likewise.
5093 (vcaddq_rot90_x_u8): Likewise.
5094 (vcaddq_rot90_x_u16): Likewise.
5095 (vcaddq_rot90_x_u32): Likewise.
5096 (vcaddq_rot270_x_s8): Likewise.
5097 (vcaddq_rot270_x_s16): Likewise.
5098 (vcaddq_rot270_x_s32): Likewise.
5099 (vcaddq_rot270_x_u8): Likewise.
5100 (vcaddq_rot270_x_u16): Likewise.
5101 (vcaddq_rot270_x_u32): Likewise.
5102 (vhaddq_x_n_s8): Likewise.
5103 (vhaddq_x_n_s16): Likewise.
5104 (vhaddq_x_n_s32): Likewise.
5105 (vhaddq_x_n_u8): Likewise.
5106 (vhaddq_x_n_u16): Likewise.
5107 (vhaddq_x_n_u32): Likewise.
5108 (vhaddq_x_s8): Likewise.
5109 (vhaddq_x_s16): Likewise.
5110 (vhaddq_x_s32): Likewise.
5111 (vhaddq_x_u8): Likewise.
5112 (vhaddq_x_u16): Likewise.
5113 (vhaddq_x_u32): Likewise.
5114 (vhcaddq_rot90_x_s8): Likewise.
5115 (vhcaddq_rot90_x_s16): Likewise.
5116 (vhcaddq_rot90_x_s32): Likewise.
5117 (vhcaddq_rot270_x_s8): Likewise.
5118 (vhcaddq_rot270_x_s16): Likewise.
5119 (vhcaddq_rot270_x_s32): Likewise.
5120 (vhsubq_x_n_s8): Likewise.
5121 (vhsubq_x_n_s16): Likewise.
5122 (vhsubq_x_n_s32): Likewise.
5123 (vhsubq_x_n_u8): Likewise.
5124 (vhsubq_x_n_u16): Likewise.
5125 (vhsubq_x_n_u32): Likewise.
5126 (vhsubq_x_s8): Likewise.
5127 (vhsubq_x_s16): Likewise.
5128 (vhsubq_x_s32): Likewise.
5129 (vhsubq_x_u8): Likewise.
5130 (vhsubq_x_u16): Likewise.
5131 (vhsubq_x_u32): Likewise.
5132 (vrhaddq_x_s8): Likewise.
5133 (vrhaddq_x_s16): Likewise.
5134 (vrhaddq_x_s32): Likewise.
5135 (vrhaddq_x_u8): Likewise.
5136 (vrhaddq_x_u16): Likewise.
5137 (vrhaddq_x_u32): Likewise.
5138 (vrmulhq_x_s8): Likewise.
5139 (vrmulhq_x_s16): Likewise.
5140 (vrmulhq_x_s32): Likewise.
5141 (vrmulhq_x_u8): Likewise.
5142 (vrmulhq_x_u16): Likewise.
5143 (vrmulhq_x_u32): Likewise.
5144 (vandq_x_s8): Likewise.
5145 (vandq_x_s16): Likewise.
5146 (vandq_x_s32): Likewise.
5147 (vandq_x_u8): Likewise.
5148 (vandq_x_u16): Likewise.
5149 (vandq_x_u32): Likewise.
5150 (vbicq_x_s8): Likewise.
5151 (vbicq_x_s16): Likewise.
5152 (vbicq_x_s32): Likewise.
5153 (vbicq_x_u8): Likewise.
5154 (vbicq_x_u16): Likewise.
5155 (vbicq_x_u32): Likewise.
5156 (vbrsrq_x_n_s8): Likewise.
5157 (vbrsrq_x_n_s16): Likewise.
5158 (vbrsrq_x_n_s32): Likewise.
5159 (vbrsrq_x_n_u8): Likewise.
5160 (vbrsrq_x_n_u16): Likewise.
5161 (vbrsrq_x_n_u32): Likewise.
5162 (veorq_x_s8): Likewise.
5163 (veorq_x_s16): Likewise.
5164 (veorq_x_s32): Likewise.
5165 (veorq_x_u8): Likewise.
5166 (veorq_x_u16): Likewise.
5167 (veorq_x_u32): Likewise.
5168 (vmovlbq_x_s8): Likewise.
5169 (vmovlbq_x_s16): Likewise.
5170 (vmovlbq_x_u8): Likewise.
5171 (vmovlbq_x_u16): Likewise.
5172 (vmovltq_x_s8): Likewise.
5173 (vmovltq_x_s16): Likewise.
5174 (vmovltq_x_u8): Likewise.
5175 (vmovltq_x_u16): Likewise.
5176 (vmvnq_x_s8): Likewise.
5177 (vmvnq_x_s16): Likewise.
5178 (vmvnq_x_s32): Likewise.
5179 (vmvnq_x_u8): Likewise.
5180 (vmvnq_x_u16): Likewise.
5181 (vmvnq_x_u32): Likewise.
5182 (vmvnq_x_n_s16): Likewise.
5183 (vmvnq_x_n_s32): Likewise.
5184 (vmvnq_x_n_u16): Likewise.
5185 (vmvnq_x_n_u32): Likewise.
5186 (vornq_x_s8): Likewise.
5187 (vornq_x_s16): Likewise.
5188 (vornq_x_s32): Likewise.
5189 (vornq_x_u8): Likewise.
5190 (vornq_x_u16): Likewise.
5191 (vornq_x_u32): Likewise.
5192 (vorrq_x_s8): Likewise.
5193 (vorrq_x_s16): Likewise.
5194 (vorrq_x_s32): Likewise.
5195 (vorrq_x_u8): Likewise.
5196 (vorrq_x_u16): Likewise.
5197 (vorrq_x_u32): Likewise.
5198 (vrev16q_x_s8): Likewise.
5199 (vrev16q_x_u8): Likewise.
5200 (vrev32q_x_s8): Likewise.
5201 (vrev32q_x_s16): Likewise.
5202 (vrev32q_x_u8): Likewise.
5203 (vrev32q_x_u16): Likewise.
5204 (vrev64q_x_s8): Likewise.
5205 (vrev64q_x_s16): Likewise.
5206 (vrev64q_x_s32): Likewise.
5207 (vrev64q_x_u8): Likewise.
5208 (vrev64q_x_u16): Likewise.
5209 (vrev64q_x_u32): Likewise.
5210 (vrshlq_x_s8): Likewise.
5211 (vrshlq_x_s16): Likewise.
5212 (vrshlq_x_s32): Likewise.
5213 (vrshlq_x_u8): Likewise.
5214 (vrshlq_x_u16): Likewise.
5215 (vrshlq_x_u32): Likewise.
5216 (vshllbq_x_n_s8): Likewise.
5217 (vshllbq_x_n_s16): Likewise.
5218 (vshllbq_x_n_u8): Likewise.
5219 (vshllbq_x_n_u16): Likewise.
5220 (vshlltq_x_n_s8): Likewise.
5221 (vshlltq_x_n_s16): Likewise.
5222 (vshlltq_x_n_u8): Likewise.
5223 (vshlltq_x_n_u16): Likewise.
5224 (vshlq_x_s8): Likewise.
5225 (vshlq_x_s16): Likewise.
5226 (vshlq_x_s32): Likewise.
5227 (vshlq_x_u8): Likewise.
5228 (vshlq_x_u16): Likewise.
5229 (vshlq_x_u32): Likewise.
5230 (vshlq_x_n_s8): Likewise.
5231 (vshlq_x_n_s16): Likewise.
5232 (vshlq_x_n_s32): Likewise.
5233 (vshlq_x_n_u8): Likewise.
5234 (vshlq_x_n_u16): Likewise.
5235 (vshlq_x_n_u32): Likewise.
5236 (vrshrq_x_n_s8): Likewise.
5237 (vrshrq_x_n_s16): Likewise.
5238 (vrshrq_x_n_s32): Likewise.
5239 (vrshrq_x_n_u8): Likewise.
5240 (vrshrq_x_n_u16): Likewise.
5241 (vrshrq_x_n_u32): Likewise.
5242 (vshrq_x_n_s8): Likewise.
5243 (vshrq_x_n_s16): Likewise.
5244 (vshrq_x_n_s32): Likewise.
5245 (vshrq_x_n_u8): Likewise.
5246 (vshrq_x_n_u16): Likewise.
5247 (vshrq_x_n_u32): Likewise.
5248 (vdupq_x_n_f16): Likewise.
5249 (vdupq_x_n_f32): Likewise.
5250 (vminnmq_x_f16): Likewise.
5251 (vminnmq_x_f32): Likewise.
5252 (vmaxnmq_x_f16): Likewise.
5253 (vmaxnmq_x_f32): Likewise.
5254 (vabdq_x_f16): Likewise.
5255 (vabdq_x_f32): Likewise.
5256 (vabsq_x_f16): Likewise.
5257 (vabsq_x_f32): Likewise.
5258 (vaddq_x_f16): Likewise.
5259 (vaddq_x_f32): Likewise.
5260 (vaddq_x_n_f16): Likewise.
5261 (vaddq_x_n_f32): Likewise.
5262 (vnegq_x_f16): Likewise.
5263 (vnegq_x_f32): Likewise.
5264 (vmulq_x_f16): Likewise.
5265 (vmulq_x_f32): Likewise.
5266 (vmulq_x_n_f16): Likewise.
5267 (vmulq_x_n_f32): Likewise.
5268 (vsubq_x_f16): Likewise.
5269 (vsubq_x_f32): Likewise.
5270 (vsubq_x_n_f16): Likewise.
5271 (vsubq_x_n_f32): Likewise.
5272 (vcaddq_rot90_x_f16): Likewise.
5273 (vcaddq_rot90_x_f32): Likewise.
5274 (vcaddq_rot270_x_f16): Likewise.
5275 (vcaddq_rot270_x_f32): Likewise.
5276 (vcmulq_x_f16): Likewise.
5277 (vcmulq_x_f32): Likewise.
5278 (vcmulq_rot90_x_f16): Likewise.
5279 (vcmulq_rot90_x_f32): Likewise.
5280 (vcmulq_rot180_x_f16): Likewise.
5281 (vcmulq_rot180_x_f32): Likewise.
5282 (vcmulq_rot270_x_f16): Likewise.
5283 (vcmulq_rot270_x_f32): Likewise.
5284 (vcvtaq_x_s16_f16): Likewise.
5285 (vcvtaq_x_s32_f32): Likewise.
5286 (vcvtaq_x_u16_f16): Likewise.
5287 (vcvtaq_x_u32_f32): Likewise.
5288 (vcvtnq_x_s16_f16): Likewise.
5289 (vcvtnq_x_s32_f32): Likewise.
5290 (vcvtnq_x_u16_f16): Likewise.
5291 (vcvtnq_x_u32_f32): Likewise.
5292 (vcvtpq_x_s16_f16): Likewise.
5293 (vcvtpq_x_s32_f32): Likewise.
5294 (vcvtpq_x_u16_f16): Likewise.
5295 (vcvtpq_x_u32_f32): Likewise.
5296 (vcvtmq_x_s16_f16): Likewise.
5297 (vcvtmq_x_s32_f32): Likewise.
5298 (vcvtmq_x_u16_f16): Likewise.
5299 (vcvtmq_x_u32_f32): Likewise.
5300 (vcvtbq_x_f32_f16): Likewise.
5301 (vcvttq_x_f32_f16): Likewise.
5302 (vcvtq_x_f16_u16): Likewise.
5303 (vcvtq_x_f16_s16): Likewise.
5304 (vcvtq_x_f32_s32): Likewise.
5305 (vcvtq_x_f32_u32): Likewise.
5306 (vcvtq_x_n_f16_s16): Likewise.
5307 (vcvtq_x_n_f16_u16): Likewise.
5308 (vcvtq_x_n_f32_s32): Likewise.
5309 (vcvtq_x_n_f32_u32): Likewise.
5310 (vcvtq_x_s16_f16): Likewise.
5311 (vcvtq_x_s32_f32): Likewise.
5312 (vcvtq_x_u16_f16): Likewise.
5313 (vcvtq_x_u32_f32): Likewise.
5314 (vcvtq_x_n_s16_f16): Likewise.
5315 (vcvtq_x_n_s32_f32): Likewise.
5316 (vcvtq_x_n_u16_f16): Likewise.
5317 (vcvtq_x_n_u32_f32): Likewise.
5318 (vrndq_x_f16): Likewise.
5319 (vrndq_x_f32): Likewise.
5320 (vrndnq_x_f16): Likewise.
5321 (vrndnq_x_f32): Likewise.
5322 (vrndmq_x_f16): Likewise.
5323 (vrndmq_x_f32): Likewise.
5324 (vrndpq_x_f16): Likewise.
5325 (vrndpq_x_f32): Likewise.
5326 (vrndaq_x_f16): Likewise.
5327 (vrndaq_x_f32): Likewise.
5328 (vrndxq_x_f16): Likewise.
5329 (vrndxq_x_f32): Likewise.
5330 (vandq_x_f16): Likewise.
5331 (vandq_x_f32): Likewise.
5332 (vbicq_x_f16): Likewise.
5333 (vbicq_x_f32): Likewise.
5334 (vbrsrq_x_n_f16): Likewise.
5335 (vbrsrq_x_n_f32): Likewise.
5336 (veorq_x_f16): Likewise.
5337 (veorq_x_f32): Likewise.
5338 (vornq_x_f16): Likewise.
5339 (vornq_x_f32): Likewise.
5340 (vorrq_x_f16): Likewise.
5341 (vorrq_x_f32): Likewise.
5342 (vrev32q_x_f16): Likewise.
5343 (vrev64q_x_f16): Likewise.
5344 (vrev64q_x_f32): Likewise.
5345 (__arm_vddupq_x_n_u8): Define intrinsic.
5346 (__arm_vddupq_x_n_u16): Likewise.
5347 (__arm_vddupq_x_n_u32): Likewise.
5348 (__arm_vddupq_x_wb_u8): Likewise.
5349 (__arm_vddupq_x_wb_u16): Likewise.
5350 (__arm_vddupq_x_wb_u32): Likewise.
5351 (__arm_vdwdupq_x_n_u8): Likewise.
5352 (__arm_vdwdupq_x_n_u16): Likewise.
5353 (__arm_vdwdupq_x_n_u32): Likewise.
5354 (__arm_vdwdupq_x_wb_u8): Likewise.
5355 (__arm_vdwdupq_x_wb_u16): Likewise.
5356 (__arm_vdwdupq_x_wb_u32): Likewise.
5357 (__arm_vidupq_x_n_u8): Likewise.
5358 (__arm_vidupq_x_n_u16): Likewise.
5359 (__arm_vidupq_x_n_u32): Likewise.
5360 (__arm_vidupq_x_wb_u8): Likewise.
5361 (__arm_vidupq_x_wb_u16): Likewise.
5362 (__arm_vidupq_x_wb_u32): Likewise.
5363 (__arm_viwdupq_x_n_u8): Likewise.
5364 (__arm_viwdupq_x_n_u16): Likewise.
5365 (__arm_viwdupq_x_n_u32): Likewise.
5366 (__arm_viwdupq_x_wb_u8): Likewise.
5367 (__arm_viwdupq_x_wb_u16): Likewise.
5368 (__arm_viwdupq_x_wb_u32): Likewise.
5369 (__arm_vdupq_x_n_s8): Likewise.
5370 (__arm_vdupq_x_n_s16): Likewise.
5371 (__arm_vdupq_x_n_s32): Likewise.
5372 (__arm_vdupq_x_n_u8): Likewise.
5373 (__arm_vdupq_x_n_u16): Likewise.
5374 (__arm_vdupq_x_n_u32): Likewise.
5375 (__arm_vminq_x_s8): Likewise.
5376 (__arm_vminq_x_s16): Likewise.
5377 (__arm_vminq_x_s32): Likewise.
5378 (__arm_vminq_x_u8): Likewise.
5379 (__arm_vminq_x_u16): Likewise.
5380 (__arm_vminq_x_u32): Likewise.
5381 (__arm_vmaxq_x_s8): Likewise.
5382 (__arm_vmaxq_x_s16): Likewise.
5383 (__arm_vmaxq_x_s32): Likewise.
5384 (__arm_vmaxq_x_u8): Likewise.
5385 (__arm_vmaxq_x_u16): Likewise.
5386 (__arm_vmaxq_x_u32): Likewise.
5387 (__arm_vabdq_x_s8): Likewise.
5388 (__arm_vabdq_x_s16): Likewise.
5389 (__arm_vabdq_x_s32): Likewise.
5390 (__arm_vabdq_x_u8): Likewise.
5391 (__arm_vabdq_x_u16): Likewise.
5392 (__arm_vabdq_x_u32): Likewise.
5393 (__arm_vabsq_x_s8): Likewise.
5394 (__arm_vabsq_x_s16): Likewise.
5395 (__arm_vabsq_x_s32): Likewise.
5396 (__arm_vaddq_x_s8): Likewise.
5397 (__arm_vaddq_x_s16): Likewise.
5398 (__arm_vaddq_x_s32): Likewise.
5399 (__arm_vaddq_x_n_s8): Likewise.
5400 (__arm_vaddq_x_n_s16): Likewise.
5401 (__arm_vaddq_x_n_s32): Likewise.
5402 (__arm_vaddq_x_u8): Likewise.
5403 (__arm_vaddq_x_u16): Likewise.
5404 (__arm_vaddq_x_u32): Likewise.
5405 (__arm_vaddq_x_n_u8): Likewise.
5406 (__arm_vaddq_x_n_u16): Likewise.
5407 (__arm_vaddq_x_n_u32): Likewise.
5408 (__arm_vclsq_x_s8): Likewise.
5409 (__arm_vclsq_x_s16): Likewise.
5410 (__arm_vclsq_x_s32): Likewise.
5411 (__arm_vclzq_x_s8): Likewise.
5412 (__arm_vclzq_x_s16): Likewise.
5413 (__arm_vclzq_x_s32): Likewise.
5414 (__arm_vclzq_x_u8): Likewise.
5415 (__arm_vclzq_x_u16): Likewise.
5416 (__arm_vclzq_x_u32): Likewise.
5417 (__arm_vnegq_x_s8): Likewise.
5418 (__arm_vnegq_x_s16): Likewise.
5419 (__arm_vnegq_x_s32): Likewise.
5420 (__arm_vmulhq_x_s8): Likewise.
5421 (__arm_vmulhq_x_s16): Likewise.
5422 (__arm_vmulhq_x_s32): Likewise.
5423 (__arm_vmulhq_x_u8): Likewise.
5424 (__arm_vmulhq_x_u16): Likewise.
5425 (__arm_vmulhq_x_u32): Likewise.
5426 (__arm_vmullbq_poly_x_p8): Likewise.
5427 (__arm_vmullbq_poly_x_p16): Likewise.
5428 (__arm_vmullbq_int_x_s8): Likewise.
5429 (__arm_vmullbq_int_x_s16): Likewise.
5430 (__arm_vmullbq_int_x_s32): Likewise.
5431 (__arm_vmullbq_int_x_u8): Likewise.
5432 (__arm_vmullbq_int_x_u16): Likewise.
5433 (__arm_vmullbq_int_x_u32): Likewise.
5434 (__arm_vmulltq_poly_x_p8): Likewise.
5435 (__arm_vmulltq_poly_x_p16): Likewise.
5436 (__arm_vmulltq_int_x_s8): Likewise.
5437 (__arm_vmulltq_int_x_s16): Likewise.
5438 (__arm_vmulltq_int_x_s32): Likewise.
5439 (__arm_vmulltq_int_x_u8): Likewise.
5440 (__arm_vmulltq_int_x_u16): Likewise.
5441 (__arm_vmulltq_int_x_u32): Likewise.
5442 (__arm_vmulq_x_s8): Likewise.
5443 (__arm_vmulq_x_s16): Likewise.
5444 (__arm_vmulq_x_s32): Likewise.
5445 (__arm_vmulq_x_n_s8): Likewise.
5446 (__arm_vmulq_x_n_s16): Likewise.
5447 (__arm_vmulq_x_n_s32): Likewise.
5448 (__arm_vmulq_x_u8): Likewise.
5449 (__arm_vmulq_x_u16): Likewise.
5450 (__arm_vmulq_x_u32): Likewise.
5451 (__arm_vmulq_x_n_u8): Likewise.
5452 (__arm_vmulq_x_n_u16): Likewise.
5453 (__arm_vmulq_x_n_u32): Likewise.
5454 (__arm_vsubq_x_s8): Likewise.
5455 (__arm_vsubq_x_s16): Likewise.
5456 (__arm_vsubq_x_s32): Likewise.
5457 (__arm_vsubq_x_n_s8): Likewise.
5458 (__arm_vsubq_x_n_s16): Likewise.
5459 (__arm_vsubq_x_n_s32): Likewise.
5460 (__arm_vsubq_x_u8): Likewise.
5461 (__arm_vsubq_x_u16): Likewise.
5462 (__arm_vsubq_x_u32): Likewise.
5463 (__arm_vsubq_x_n_u8): Likewise.
5464 (__arm_vsubq_x_n_u16): Likewise.
5465 (__arm_vsubq_x_n_u32): Likewise.
5466 (__arm_vcaddq_rot90_x_s8): Likewise.
5467 (__arm_vcaddq_rot90_x_s16): Likewise.
5468 (__arm_vcaddq_rot90_x_s32): Likewise.
5469 (__arm_vcaddq_rot90_x_u8): Likewise.
5470 (__arm_vcaddq_rot90_x_u16): Likewise.
5471 (__arm_vcaddq_rot90_x_u32): Likewise.
5472 (__arm_vcaddq_rot270_x_s8): Likewise.
5473 (__arm_vcaddq_rot270_x_s16): Likewise.
5474 (__arm_vcaddq_rot270_x_s32): Likewise.
5475 (__arm_vcaddq_rot270_x_u8): Likewise.
5476 (__arm_vcaddq_rot270_x_u16): Likewise.
5477 (__arm_vcaddq_rot270_x_u32): Likewise.
5478 (__arm_vhaddq_x_n_s8): Likewise.
5479 (__arm_vhaddq_x_n_s16): Likewise.
5480 (__arm_vhaddq_x_n_s32): Likewise.
5481 (__arm_vhaddq_x_n_u8): Likewise.
5482 (__arm_vhaddq_x_n_u16): Likewise.
5483 (__arm_vhaddq_x_n_u32): Likewise.
5484 (__arm_vhaddq_x_s8): Likewise.
5485 (__arm_vhaddq_x_s16): Likewise.
5486 (__arm_vhaddq_x_s32): Likewise.
5487 (__arm_vhaddq_x_u8): Likewise.
5488 (__arm_vhaddq_x_u16): Likewise.
5489 (__arm_vhaddq_x_u32): Likewise.
5490 (__arm_vhcaddq_rot90_x_s8): Likewise.
5491 (__arm_vhcaddq_rot90_x_s16): Likewise.
5492 (__arm_vhcaddq_rot90_x_s32): Likewise.
5493 (__arm_vhcaddq_rot270_x_s8): Likewise.
5494 (__arm_vhcaddq_rot270_x_s16): Likewise.
5495 (__arm_vhcaddq_rot270_x_s32): Likewise.
5496 (__arm_vhsubq_x_n_s8): Likewise.
5497 (__arm_vhsubq_x_n_s16): Likewise.
5498 (__arm_vhsubq_x_n_s32): Likewise.
5499 (__arm_vhsubq_x_n_u8): Likewise.
5500 (__arm_vhsubq_x_n_u16): Likewise.
5501 (__arm_vhsubq_x_n_u32): Likewise.
5502 (__arm_vhsubq_x_s8): Likewise.
5503 (__arm_vhsubq_x_s16): Likewise.
5504 (__arm_vhsubq_x_s32): Likewise.
5505 (__arm_vhsubq_x_u8): Likewise.
5506 (__arm_vhsubq_x_u16): Likewise.
5507 (__arm_vhsubq_x_u32): Likewise.
5508 (__arm_vrhaddq_x_s8): Likewise.
5509 (__arm_vrhaddq_x_s16): Likewise.
5510 (__arm_vrhaddq_x_s32): Likewise.
5511 (__arm_vrhaddq_x_u8): Likewise.
5512 (__arm_vrhaddq_x_u16): Likewise.
5513 (__arm_vrhaddq_x_u32): Likewise.
5514 (__arm_vrmulhq_x_s8): Likewise.
5515 (__arm_vrmulhq_x_s16): Likewise.
5516 (__arm_vrmulhq_x_s32): Likewise.
5517 (__arm_vrmulhq_x_u8): Likewise.
5518 (__arm_vrmulhq_x_u16): Likewise.
5519 (__arm_vrmulhq_x_u32): Likewise.
5520 (__arm_vandq_x_s8): Likewise.
5521 (__arm_vandq_x_s16): Likewise.
5522 (__arm_vandq_x_s32): Likewise.
5523 (__arm_vandq_x_u8): Likewise.
5524 (__arm_vandq_x_u16): Likewise.
5525 (__arm_vandq_x_u32): Likewise.
5526 (__arm_vbicq_x_s8): Likewise.
5527 (__arm_vbicq_x_s16): Likewise.
5528 (__arm_vbicq_x_s32): Likewise.
5529 (__arm_vbicq_x_u8): Likewise.
5530 (__arm_vbicq_x_u16): Likewise.
5531 (__arm_vbicq_x_u32): Likewise.
5532 (__arm_vbrsrq_x_n_s8): Likewise.
5533 (__arm_vbrsrq_x_n_s16): Likewise.
5534 (__arm_vbrsrq_x_n_s32): Likewise.
5535 (__arm_vbrsrq_x_n_u8): Likewise.
5536 (__arm_vbrsrq_x_n_u16): Likewise.
5537 (__arm_vbrsrq_x_n_u32): Likewise.
5538 (__arm_veorq_x_s8): Likewise.
5539 (__arm_veorq_x_s16): Likewise.
5540 (__arm_veorq_x_s32): Likewise.
5541 (__arm_veorq_x_u8): Likewise.
5542 (__arm_veorq_x_u16): Likewise.
5543 (__arm_veorq_x_u32): Likewise.
5544 (__arm_vmovlbq_x_s8): Likewise.
5545 (__arm_vmovlbq_x_s16): Likewise.
5546 (__arm_vmovlbq_x_u8): Likewise.
5547 (__arm_vmovlbq_x_u16): Likewise.
5548 (__arm_vmovltq_x_s8): Likewise.
5549 (__arm_vmovltq_x_s16): Likewise.
5550 (__arm_vmovltq_x_u8): Likewise.
5551 (__arm_vmovltq_x_u16): Likewise.
5552 (__arm_vmvnq_x_s8): Likewise.
5553 (__arm_vmvnq_x_s16): Likewise.
5554 (__arm_vmvnq_x_s32): Likewise.
5555 (__arm_vmvnq_x_u8): Likewise.
5556 (__arm_vmvnq_x_u16): Likewise.
5557 (__arm_vmvnq_x_u32): Likewise.
5558 (__arm_vmvnq_x_n_s16): Likewise.
5559 (__arm_vmvnq_x_n_s32): Likewise.
5560 (__arm_vmvnq_x_n_u16): Likewise.
5561 (__arm_vmvnq_x_n_u32): Likewise.
5562 (__arm_vornq_x_s8): Likewise.
5563 (__arm_vornq_x_s16): Likewise.
5564 (__arm_vornq_x_s32): Likewise.
5565 (__arm_vornq_x_u8): Likewise.
5566 (__arm_vornq_x_u16): Likewise.
5567 (__arm_vornq_x_u32): Likewise.
5568 (__arm_vorrq_x_s8): Likewise.
5569 (__arm_vorrq_x_s16): Likewise.
5570 (__arm_vorrq_x_s32): Likewise.
5571 (__arm_vorrq_x_u8): Likewise.
5572 (__arm_vorrq_x_u16): Likewise.
5573 (__arm_vorrq_x_u32): Likewise.
5574 (__arm_vrev16q_x_s8): Likewise.
5575 (__arm_vrev16q_x_u8): Likewise.
5576 (__arm_vrev32q_x_s8): Likewise.
5577 (__arm_vrev32q_x_s16): Likewise.
5578 (__arm_vrev32q_x_u8): Likewise.
5579 (__arm_vrev32q_x_u16): Likewise.
5580 (__arm_vrev64q_x_s8): Likewise.
5581 (__arm_vrev64q_x_s16): Likewise.
5582 (__arm_vrev64q_x_s32): Likewise.
5583 (__arm_vrev64q_x_u8): Likewise.
5584 (__arm_vrev64q_x_u16): Likewise.
5585 (__arm_vrev64q_x_u32): Likewise.
5586 (__arm_vrshlq_x_s8): Likewise.
5587 (__arm_vrshlq_x_s16): Likewise.
5588 (__arm_vrshlq_x_s32): Likewise.
5589 (__arm_vrshlq_x_u8): Likewise.
5590 (__arm_vrshlq_x_u16): Likewise.
5591 (__arm_vrshlq_x_u32): Likewise.
5592 (__arm_vshllbq_x_n_s8): Likewise.
5593 (__arm_vshllbq_x_n_s16): Likewise.
5594 (__arm_vshllbq_x_n_u8): Likewise.
5595 (__arm_vshllbq_x_n_u16): Likewise.
5596 (__arm_vshlltq_x_n_s8): Likewise.
5597 (__arm_vshlltq_x_n_s16): Likewise.
5598 (__arm_vshlltq_x_n_u8): Likewise.
5599 (__arm_vshlltq_x_n_u16): Likewise.
5600 (__arm_vshlq_x_s8): Likewise.
5601 (__arm_vshlq_x_s16): Likewise.
5602 (__arm_vshlq_x_s32): Likewise.
5603 (__arm_vshlq_x_u8): Likewise.
5604 (__arm_vshlq_x_u16): Likewise.
5605 (__arm_vshlq_x_u32): Likewise.
5606 (__arm_vshlq_x_n_s8): Likewise.
5607 (__arm_vshlq_x_n_s16): Likewise.
5608 (__arm_vshlq_x_n_s32): Likewise.
5609 (__arm_vshlq_x_n_u8): Likewise.
5610 (__arm_vshlq_x_n_u16): Likewise.
5611 (__arm_vshlq_x_n_u32): Likewise.
5612 (__arm_vrshrq_x_n_s8): Likewise.
5613 (__arm_vrshrq_x_n_s16): Likewise.
5614 (__arm_vrshrq_x_n_s32): Likewise.
5615 (__arm_vrshrq_x_n_u8): Likewise.
5616 (__arm_vrshrq_x_n_u16): Likewise.
5617 (__arm_vrshrq_x_n_u32): Likewise.
5618 (__arm_vshrq_x_n_s8): Likewise.
5619 (__arm_vshrq_x_n_s16): Likewise.
5620 (__arm_vshrq_x_n_s32): Likewise.
5621 (__arm_vshrq_x_n_u8): Likewise.
5622 (__arm_vshrq_x_n_u16): Likewise.
5623 (__arm_vshrq_x_n_u32): Likewise.
5624 (__arm_vdupq_x_n_f16): Likewise.
5625 (__arm_vdupq_x_n_f32): Likewise.
5626 (__arm_vminnmq_x_f16): Likewise.
5627 (__arm_vminnmq_x_f32): Likewise.
5628 (__arm_vmaxnmq_x_f16): Likewise.
5629 (__arm_vmaxnmq_x_f32): Likewise.
5630 (__arm_vabdq_x_f16): Likewise.
5631 (__arm_vabdq_x_f32): Likewise.
5632 (__arm_vabsq_x_f16): Likewise.
5633 (__arm_vabsq_x_f32): Likewise.
5634 (__arm_vaddq_x_f16): Likewise.
5635 (__arm_vaddq_x_f32): Likewise.
5636 (__arm_vaddq_x_n_f16): Likewise.
5637 (__arm_vaddq_x_n_f32): Likewise.
5638 (__arm_vnegq_x_f16): Likewise.
5639 (__arm_vnegq_x_f32): Likewise.
5640 (__arm_vmulq_x_f16): Likewise.
5641 (__arm_vmulq_x_f32): Likewise.
5642 (__arm_vmulq_x_n_f16): Likewise.
5643 (__arm_vmulq_x_n_f32): Likewise.
5644 (__arm_vsubq_x_f16): Likewise.
5645 (__arm_vsubq_x_f32): Likewise.
5646 (__arm_vsubq_x_n_f16): Likewise.
5647 (__arm_vsubq_x_n_f32): Likewise.
5648 (__arm_vcaddq_rot90_x_f16): Likewise.
5649 (__arm_vcaddq_rot90_x_f32): Likewise.
5650 (__arm_vcaddq_rot270_x_f16): Likewise.
5651 (__arm_vcaddq_rot270_x_f32): Likewise.
5652 (__arm_vcmulq_x_f16): Likewise.
5653 (__arm_vcmulq_x_f32): Likewise.
5654 (__arm_vcmulq_rot90_x_f16): Likewise.
5655 (__arm_vcmulq_rot90_x_f32): Likewise.
5656 (__arm_vcmulq_rot180_x_f16): Likewise.
5657 (__arm_vcmulq_rot180_x_f32): Likewise.
5658 (__arm_vcmulq_rot270_x_f16): Likewise.
5659 (__arm_vcmulq_rot270_x_f32): Likewise.
5660 (__arm_vcvtaq_x_s16_f16): Likewise.
5661 (__arm_vcvtaq_x_s32_f32): Likewise.
5662 (__arm_vcvtaq_x_u16_f16): Likewise.
5663 (__arm_vcvtaq_x_u32_f32): Likewise.
5664 (__arm_vcvtnq_x_s16_f16): Likewise.
5665 (__arm_vcvtnq_x_s32_f32): Likewise.
5666 (__arm_vcvtnq_x_u16_f16): Likewise.
5667 (__arm_vcvtnq_x_u32_f32): Likewise.
5668 (__arm_vcvtpq_x_s16_f16): Likewise.
5669 (__arm_vcvtpq_x_s32_f32): Likewise.
5670 (__arm_vcvtpq_x_u16_f16): Likewise.
5671 (__arm_vcvtpq_x_u32_f32): Likewise.
5672 (__arm_vcvtmq_x_s16_f16): Likewise.
5673 (__arm_vcvtmq_x_s32_f32): Likewise.
5674 (__arm_vcvtmq_x_u16_f16): Likewise.
5675 (__arm_vcvtmq_x_u32_f32): Likewise.
5676 (__arm_vcvtbq_x_f32_f16): Likewise.
5677 (__arm_vcvttq_x_f32_f16): Likewise.
5678 (__arm_vcvtq_x_f16_u16): Likewise.
5679 (__arm_vcvtq_x_f16_s16): Likewise.
5680 (__arm_vcvtq_x_f32_s32): Likewise.
5681 (__arm_vcvtq_x_f32_u32): Likewise.
5682 (__arm_vcvtq_x_n_f16_s16): Likewise.
5683 (__arm_vcvtq_x_n_f16_u16): Likewise.
5684 (__arm_vcvtq_x_n_f32_s32): Likewise.
5685 (__arm_vcvtq_x_n_f32_u32): Likewise.
5686 (__arm_vcvtq_x_s16_f16): Likewise.
5687 (__arm_vcvtq_x_s32_f32): Likewise.
5688 (__arm_vcvtq_x_u16_f16): Likewise.
5689 (__arm_vcvtq_x_u32_f32): Likewise.
5690 (__arm_vcvtq_x_n_s16_f16): Likewise.
5691 (__arm_vcvtq_x_n_s32_f32): Likewise.
5692 (__arm_vcvtq_x_n_u16_f16): Likewise.
5693 (__arm_vcvtq_x_n_u32_f32): Likewise.
5694 (__arm_vrndq_x_f16): Likewise.
5695 (__arm_vrndq_x_f32): Likewise.
5696 (__arm_vrndnq_x_f16): Likewise.
5697 (__arm_vrndnq_x_f32): Likewise.
5698 (__arm_vrndmq_x_f16): Likewise.
5699 (__arm_vrndmq_x_f32): Likewise.
5700 (__arm_vrndpq_x_f16): Likewise.
5701 (__arm_vrndpq_x_f32): Likewise.
5702 (__arm_vrndaq_x_f16): Likewise.
5703 (__arm_vrndaq_x_f32): Likewise.
5704 (__arm_vrndxq_x_f16): Likewise.
5705 (__arm_vrndxq_x_f32): Likewise.
5706 (__arm_vandq_x_f16): Likewise.
5707 (__arm_vandq_x_f32): Likewise.
5708 (__arm_vbicq_x_f16): Likewise.
5709 (__arm_vbicq_x_f32): Likewise.
5710 (__arm_vbrsrq_x_n_f16): Likewise.
5711 (__arm_vbrsrq_x_n_f32): Likewise.
5712 (__arm_veorq_x_f16): Likewise.
5713 (__arm_veorq_x_f32): Likewise.
5714 (__arm_vornq_x_f16): Likewise.
5715 (__arm_vornq_x_f32): Likewise.
5716 (__arm_vorrq_x_f16): Likewise.
5717 (__arm_vorrq_x_f32): Likewise.
5718 (__arm_vrev32q_x_f16): Likewise.
5719 (__arm_vrev64q_x_f16): Likewise.
5720 (__arm_vrev64q_x_f32): Likewise.
5721 (vabdq_x): Define polymorphic variant.
5722 (vabsq_x): Likewise.
5723 (vaddq_x): Likewise.
5724 (vandq_x): Likewise.
5725 (vbicq_x): Likewise.
5726 (vbrsrq_x): Likewise.
5727 (vcaddq_rot270_x): Likewise.
5728 (vcaddq_rot90_x): Likewise.
5729 (vcmulq_rot180_x): Likewise.
5730 (vcmulq_rot270_x): Likewise.
5731 (vcmulq_x): Likewise.
5732 (vcvtq_x): Likewise.
5733 (vcvtq_x_n): Likewise.
5734 (vcvtnq_m): Likewise.
5735 (veorq_x): Likewise.
5736 (vmaxnmq_x): Likewise.
5737 (vminnmq_x): Likewise.
5738 (vmulq_x): Likewise.
5739 (vnegq_x): Likewise.
5740 (vornq_x): Likewise.
5741 (vorrq_x): Likewise.
5742 (vrev32q_x): Likewise.
5743 (vrev64q_x): Likewise.
5744 (vrndaq_x): Likewise.
5745 (vrndmq_x): Likewise.
5746 (vrndnq_x): Likewise.
5747 (vrndpq_x): Likewise.
5748 (vrndq_x): Likewise.
5749 (vrndxq_x): Likewise.
5750 (vsubq_x): Likewise.
5751 (vcmulq_rot90_x): Likewise.
5753 (vclsq_x): Likewise.
5754 (vclzq_x): Likewise.
5755 (vhaddq_x): Likewise.
5756 (vhcaddq_rot270_x): Likewise.
5757 (vhcaddq_rot90_x): Likewise.
5758 (vhsubq_x): Likewise.
5759 (vmaxq_x): Likewise.
5760 (vminq_x): Likewise.
5761 (vmovlbq_x): Likewise.
5762 (vmovltq_x): Likewise.
5763 (vmulhq_x): Likewise.
5764 (vmullbq_int_x): Likewise.
5765 (vmullbq_poly_x): Likewise.
5766 (vmulltq_int_x): Likewise.
5767 (vmulltq_poly_x): Likewise.
5768 (vmvnq_x): Likewise.
5769 (vrev16q_x): Likewise.
5770 (vrhaddq_x): Likewise.
5771 (vrmulhq_x): Likewise.
5772 (vrshlq_x): Likewise.
5773 (vrshrq_x): Likewise.
5774 (vshllbq_x): Likewise.
5775 (vshlltq_x): Likewise.
5776 (vshlq_x_n): Likewise.
5777 (vshlq_x): Likewise.
5778 (vdwdupq_x_u8): Likewise.
5779 (vdwdupq_x_u16): Likewise.
5780 (vdwdupq_x_u32): Likewise.
5781 (viwdupq_x_u8): Likewise.
5782 (viwdupq_x_u16): Likewise.
5783 (viwdupq_x_u32): Likewise.
5784 (vidupq_x_u8): Likewise.
5785 (vddupq_x_u8): Likewise.
5786 (vidupq_x_u16): Likewise.
5787 (vddupq_x_u16): Likewise.
5788 (vidupq_x_u32): Likewise.
5789 (vddupq_x_u32): Likewise.
5790 (vshrq_x): Likewise.
5792 2020-03-20 Richard Biener <rguenther@suse.de>
5794 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
5795 to vectorize for CTOR defs.
5797 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5798 Andre Vieira <andre.simoesdiasvieira@arm.com>
5799 Mihail Ionescu <mihail.ionescu@arm.com>
5801 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin
5803 (LDRGBWBU_QUALIFIERS): Likewise.
5804 (LDRGBWBS_Z_QUALIFIERS): Likewise.
5805 (LDRGBWBU_Z_QUALIFIERS): Likewise.
5806 (STRSBWBS_QUALIFIERS): Likewise.
5807 (STRSBWBU_QUALIFIERS): Likewise.
5808 (STRSBWBS_P_QUALIFIERS): Likewise.
5809 (STRSBWBU_P_QUALIFIERS): Likewise.
5810 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro.
5811 (vldrdq_gather_base_wb_u64): Likewise.
5812 (vldrdq_gather_base_wb_z_s64): Likewise.
5813 (vldrdq_gather_base_wb_z_u64): Likewise.
5814 (vldrwq_gather_base_wb_f32): Likewise.
5815 (vldrwq_gather_base_wb_s32): Likewise.
5816 (vldrwq_gather_base_wb_u32): Likewise.
5817 (vldrwq_gather_base_wb_z_f32): Likewise.
5818 (vldrwq_gather_base_wb_z_s32): Likewise.
5819 (vldrwq_gather_base_wb_z_u32): Likewise.
5820 (vstrdq_scatter_base_wb_p_s64): Likewise.
5821 (vstrdq_scatter_base_wb_p_u64): Likewise.
5822 (vstrdq_scatter_base_wb_s64): Likewise.
5823 (vstrdq_scatter_base_wb_u64): Likewise.
5824 (vstrwq_scatter_base_wb_p_s32): Likewise.
5825 (vstrwq_scatter_base_wb_p_f32): Likewise.
5826 (vstrwq_scatter_base_wb_p_u32): Likewise.
5827 (vstrwq_scatter_base_wb_s32): Likewise.
5828 (vstrwq_scatter_base_wb_u32): Likewise.
5829 (vstrwq_scatter_base_wb_f32): Likewise.
5830 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic.
5831 (__arm_vldrdq_gather_base_wb_u64): Likewise.
5832 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
5833 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
5834 (__arm_vldrwq_gather_base_wb_s32): Likewise.
5835 (__arm_vldrwq_gather_base_wb_u32): Likewise.
5836 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
5837 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
5838 (__arm_vstrdq_scatter_base_wb_s64): Likewise.
5839 (__arm_vstrdq_scatter_base_wb_u64): Likewise.
5840 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
5841 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
5842 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
5843 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
5844 (__arm_vstrwq_scatter_base_wb_s32): Likewise.
5845 (__arm_vstrwq_scatter_base_wb_u32): Likewise.
5846 (__arm_vldrwq_gather_base_wb_f32): Likewise.
5847 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
5848 (__arm_vstrwq_scatter_base_wb_f32): Likewise.
5849 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
5850 (vstrwq_scatter_base_wb): Define polymorphic variant.
5851 (vstrwq_scatter_base_wb_p): Likewise.
5852 (vstrdq_scatter_base_wb_p): Likewise.
5853 (vstrdq_scatter_base_wb): Likewise.
5854 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin
5856 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL
5858 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
5859 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise.
5860 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
5861 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
5862 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise.
5863 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
5864 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
5865 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise.
5866 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
5867 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
5868 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise.
5869 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
5870 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
5871 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise.
5872 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
5873 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
5874 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise.
5875 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise.
5876 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
5877 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise.
5878 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
5879 (mve_vldrwq_gather_base_wb_fv4sf): Likewise.
5880 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
5881 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise.
5882 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
5883 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise.
5884 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
5885 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise.
5886 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
5888 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5889 Andre Vieira <andre.simoesdiasvieira@arm.com>
5890 Mihail Ionescu <mihail.ionescu@arm.com>
5892 * config/arm/arm-builtins.c
5893 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary
5895 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro.
5896 (vddupq_m_n_u32): Likewise.
5897 (vddupq_m_n_u16): Likewise.
5898 (vddupq_m_wb_u8): Likewise.
5899 (vddupq_m_wb_u16): Likewise.
5900 (vddupq_m_wb_u32): Likewise.
5901 (vddupq_n_u8): Likewise.
5902 (vddupq_n_u32): Likewise.
5903 (vddupq_n_u16): Likewise.
5904 (vddupq_wb_u8): Likewise.
5905 (vddupq_wb_u16): Likewise.
5906 (vddupq_wb_u32): Likewise.
5907 (vdwdupq_m_n_u8): Likewise.
5908 (vdwdupq_m_n_u32): Likewise.
5909 (vdwdupq_m_n_u16): Likewise.
5910 (vdwdupq_m_wb_u8): Likewise.
5911 (vdwdupq_m_wb_u32): Likewise.
5912 (vdwdupq_m_wb_u16): Likewise.
5913 (vdwdupq_n_u8): Likewise.
5914 (vdwdupq_n_u32): Likewise.
5915 (vdwdupq_n_u16): Likewise.
5916 (vdwdupq_wb_u8): Likewise.
5917 (vdwdupq_wb_u32): Likewise.
5918 (vdwdupq_wb_u16): Likewise.
5919 (vidupq_m_n_u8): Likewise.
5920 (vidupq_m_n_u32): Likewise.
5921 (vidupq_m_n_u16): Likewise.
5922 (vidupq_m_wb_u8): Likewise.
5923 (vidupq_m_wb_u16): Likewise.
5924 (vidupq_m_wb_u32): Likewise.
5925 (vidupq_n_u8): Likewise.
5926 (vidupq_n_u32): Likewise.
5927 (vidupq_n_u16): Likewise.
5928 (vidupq_wb_u8): Likewise.
5929 (vidupq_wb_u16): Likewise.
5930 (vidupq_wb_u32): Likewise.
5931 (viwdupq_m_n_u8): Likewise.
5932 (viwdupq_m_n_u32): Likewise.
5933 (viwdupq_m_n_u16): Likewise.
5934 (viwdupq_m_wb_u8): Likewise.
5935 (viwdupq_m_wb_u32): Likewise.
5936 (viwdupq_m_wb_u16): Likewise.
5937 (viwdupq_n_u8): Likewise.
5938 (viwdupq_n_u32): Likewise.
5939 (viwdupq_n_u16): Likewise.
5940 (viwdupq_wb_u8): Likewise.
5941 (viwdupq_wb_u32): Likewise.
5942 (viwdupq_wb_u16): Likewise.
5943 (__arm_vddupq_m_n_u8): Define intrinsic.
5944 (__arm_vddupq_m_n_u32): Likewise.
5945 (__arm_vddupq_m_n_u16): Likewise.
5946 (__arm_vddupq_m_wb_u8): Likewise.
5947 (__arm_vddupq_m_wb_u16): Likewise.
5948 (__arm_vddupq_m_wb_u32): Likewise.
5949 (__arm_vddupq_n_u8): Likewise.
5950 (__arm_vddupq_n_u32): Likewise.
5951 (__arm_vddupq_n_u16): Likewise.
5952 (__arm_vdwdupq_m_n_u8): Likewise.
5953 (__arm_vdwdupq_m_n_u32): Likewise.
5954 (__arm_vdwdupq_m_n_u16): Likewise.
5955 (__arm_vdwdupq_m_wb_u8): Likewise.
5956 (__arm_vdwdupq_m_wb_u32): Likewise.
5957 (__arm_vdwdupq_m_wb_u16): Likewise.
5958 (__arm_vdwdupq_n_u8): Likewise.
5959 (__arm_vdwdupq_n_u32): Likewise.
5960 (__arm_vdwdupq_n_u16): Likewise.
5961 (__arm_vdwdupq_wb_u8): Likewise.
5962 (__arm_vdwdupq_wb_u32): Likewise.
5963 (__arm_vdwdupq_wb_u16): Likewise.
5964 (__arm_vidupq_m_n_u8): Likewise.
5965 (__arm_vidupq_m_n_u32): Likewise.
5966 (__arm_vidupq_m_n_u16): Likewise.
5967 (__arm_vidupq_n_u8): Likewise.
5968 (__arm_vidupq_m_wb_u8): Likewise.
5969 (__arm_vidupq_m_wb_u16): Likewise.
5970 (__arm_vidupq_m_wb_u32): Likewise.
5971 (__arm_vidupq_n_u32): Likewise.
5972 (__arm_vidupq_n_u16): Likewise.
5973 (__arm_vidupq_wb_u8): Likewise.
5974 (__arm_vidupq_wb_u16): Likewise.
5975 (__arm_vidupq_wb_u32): Likewise.
5976 (__arm_vddupq_wb_u8): Likewise.
5977 (__arm_vddupq_wb_u16): Likewise.
5978 (__arm_vddupq_wb_u32): Likewise.
5979 (__arm_viwdupq_m_n_u8): Likewise.
5980 (__arm_viwdupq_m_n_u32): Likewise.
5981 (__arm_viwdupq_m_n_u16): Likewise.
5982 (__arm_viwdupq_m_wb_u8): Likewise.
5983 (__arm_viwdupq_m_wb_u32): Likewise.
5984 (__arm_viwdupq_m_wb_u16): Likewise.
5985 (__arm_viwdupq_n_u8): Likewise.
5986 (__arm_viwdupq_n_u32): Likewise.
5987 (__arm_viwdupq_n_u16): Likewise.
5988 (__arm_viwdupq_wb_u8): Likewise.
5989 (__arm_viwdupq_wb_u32): Likewise.
5990 (__arm_viwdupq_wb_u16): Likewise.
5991 (vidupq_m): Define polymorphic variant.
5992 (vddupq_m): Likewise.
5993 (vidupq_u16): Likewise.
5994 (vidupq_u32): Likewise.
5995 (vidupq_u8): Likewise.
5996 (vddupq_u16): Likewise.
5997 (vddupq_u32): Likewise.
5998 (vddupq_u8): Likewise.
5999 (viwdupq_m): Likewise.
6000 (viwdupq_u16): Likewise.
6001 (viwdupq_u32): Likewise.
6002 (viwdupq_u8): Likewise.
6003 (vdwdupq_m): Likewise.
6004 (vdwdupq_u16): Likewise.
6005 (vdwdupq_u32): Likewise.
6006 (vdwdupq_u8): Likewise.
6007 * config/arm/arm_mve_builtins.def
6008 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin
6010 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern.
6011 (mve_vidupq_u<mode>_insn): Likewise.
6012 (mve_vidupq_m_n_u<mode>): Likewise.
6013 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
6014 (mve_vddupq_n_u<mode>): Likewise.
6015 (mve_vddupq_u<mode>_insn): Likewise.
6016 (mve_vddupq_m_n_u<mode>): Likewise.
6017 (mve_vddupq_m_wb_u<mode>_insn): Likewise.
6018 (mve_vdwdupq_n_u<mode>): Likewise.
6019 (mve_vdwdupq_wb_u<mode>): Likewise.
6020 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
6021 (mve_vdwdupq_m_n_u<mode>): Likewise.
6022 (mve_vdwdupq_m_wb_u<mode>): Likewise.
6023 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
6024 (mve_viwdupq_n_u<mode>): Likewise.
6025 (mve_viwdupq_wb_u<mode>): Likewise.
6026 (mve_viwdupq_wb_u<mode>_insn): Likewise.
6027 (mve_viwdupq_m_n_u<mode>): Likewise.
6028 (mve_viwdupq_m_wb_u<mode>): Likewise.
6029 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
6031 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6033 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro.
6034 (vreinterpretq_s16_s64): Likewise.
6035 (vreinterpretq_s16_s8): Likewise.
6036 (vreinterpretq_s16_u16): Likewise.
6037 (vreinterpretq_s16_u32): Likewise.
6038 (vreinterpretq_s16_u64): Likewise.
6039 (vreinterpretq_s16_u8): Likewise.
6040 (vreinterpretq_s32_s16): Likewise.
6041 (vreinterpretq_s32_s64): Likewise.
6042 (vreinterpretq_s32_s8): Likewise.
6043 (vreinterpretq_s32_u16): Likewise.
6044 (vreinterpretq_s32_u32): Likewise.
6045 (vreinterpretq_s32_u64): Likewise.
6046 (vreinterpretq_s32_u8): Likewise.
6047 (vreinterpretq_s64_s16): Likewise.
6048 (vreinterpretq_s64_s32): Likewise.
6049 (vreinterpretq_s64_s8): Likewise.
6050 (vreinterpretq_s64_u16): Likewise.
6051 (vreinterpretq_s64_u32): Likewise.
6052 (vreinterpretq_s64_u64): Likewise.
6053 (vreinterpretq_s64_u8): Likewise.
6054 (vreinterpretq_s8_s16): Likewise.
6055 (vreinterpretq_s8_s32): Likewise.
6056 (vreinterpretq_s8_s64): Likewise.
6057 (vreinterpretq_s8_u16): Likewise.
6058 (vreinterpretq_s8_u32): Likewise.
6059 (vreinterpretq_s8_u64): Likewise.
6060 (vreinterpretq_s8_u8): Likewise.
6061 (vreinterpretq_u16_s16): Likewise.
6062 (vreinterpretq_u16_s32): Likewise.
6063 (vreinterpretq_u16_s64): Likewise.
6064 (vreinterpretq_u16_s8): Likewise.
6065 (vreinterpretq_u16_u32): Likewise.
6066 (vreinterpretq_u16_u64): Likewise.
6067 (vreinterpretq_u16_u8): Likewise.
6068 (vreinterpretq_u32_s16): Likewise.
6069 (vreinterpretq_u32_s32): Likewise.
6070 (vreinterpretq_u32_s64): Likewise.
6071 (vreinterpretq_u32_s8): Likewise.
6072 (vreinterpretq_u32_u16): Likewise.
6073 (vreinterpretq_u32_u64): Likewise.
6074 (vreinterpretq_u32_u8): Likewise.
6075 (vreinterpretq_u64_s16): Likewise.
6076 (vreinterpretq_u64_s32): Likewise.
6077 (vreinterpretq_u64_s64): Likewise.
6078 (vreinterpretq_u64_s8): Likewise.
6079 (vreinterpretq_u64_u16): Likewise.
6080 (vreinterpretq_u64_u32): Likewise.
6081 (vreinterpretq_u64_u8): Likewise.
6082 (vreinterpretq_u8_s16): Likewise.
6083 (vreinterpretq_u8_s32): Likewise.
6084 (vreinterpretq_u8_s64): Likewise.
6085 (vreinterpretq_u8_s8): Likewise.
6086 (vreinterpretq_u8_u16): Likewise.
6087 (vreinterpretq_u8_u32): Likewise.
6088 (vreinterpretq_u8_u64): Likewise.
6089 (vreinterpretq_s32_f16): Likewise.
6090 (vreinterpretq_s32_f32): Likewise.
6091 (vreinterpretq_u16_f16): Likewise.
6092 (vreinterpretq_u16_f32): Likewise.
6093 (vreinterpretq_u32_f16): Likewise.
6094 (vreinterpretq_u32_f32): Likewise.
6095 (vreinterpretq_u64_f16): Likewise.
6096 (vreinterpretq_u64_f32): Likewise.
6097 (vreinterpretq_u8_f16): Likewise.
6098 (vreinterpretq_u8_f32): Likewise.
6099 (vreinterpretq_f16_f32): Likewise.
6100 (vreinterpretq_f16_s16): Likewise.
6101 (vreinterpretq_f16_s32): Likewise.
6102 (vreinterpretq_f16_s64): Likewise.
6103 (vreinterpretq_f16_s8): Likewise.
6104 (vreinterpretq_f16_u16): Likewise.
6105 (vreinterpretq_f16_u32): Likewise.
6106 (vreinterpretq_f16_u64): Likewise.
6107 (vreinterpretq_f16_u8): Likewise.
6108 (vreinterpretq_f32_f16): Likewise.
6109 (vreinterpretq_f32_s16): Likewise.
6110 (vreinterpretq_f32_s32): Likewise.
6111 (vreinterpretq_f32_s64): Likewise.
6112 (vreinterpretq_f32_s8): Likewise.
6113 (vreinterpretq_f32_u16): Likewise.
6114 (vreinterpretq_f32_u32): Likewise.
6115 (vreinterpretq_f32_u64): Likewise.
6116 (vreinterpretq_f32_u8): Likewise.
6117 (vreinterpretq_s16_f16): Likewise.
6118 (vreinterpretq_s16_f32): Likewise.
6119 (vreinterpretq_s64_f16): Likewise.
6120 (vreinterpretq_s64_f32): Likewise.
6121 (vreinterpretq_s8_f16): Likewise.
6122 (vreinterpretq_s8_f32): Likewise.
6123 (vuninitializedq_u8): Likewise.
6124 (vuninitializedq_u16): Likewise.
6125 (vuninitializedq_u32): Likewise.
6126 (vuninitializedq_u64): Likewise.
6127 (vuninitializedq_s8): Likewise.
6128 (vuninitializedq_s16): Likewise.
6129 (vuninitializedq_s32): Likewise.
6130 (vuninitializedq_s64): Likewise.
6131 (vuninitializedq_f16): Likewise.
6132 (vuninitializedq_f32): Likewise.
6133 (__arm_vuninitializedq_u8): Define intrinsic.
6134 (__arm_vuninitializedq_u16): Likewise.
6135 (__arm_vuninitializedq_u32): Likewise.
6136 (__arm_vuninitializedq_u64): Likewise.
6137 (__arm_vuninitializedq_s8): Likewise.
6138 (__arm_vuninitializedq_s16): Likewise.
6139 (__arm_vuninitializedq_s32): Likewise.
6140 (__arm_vuninitializedq_s64): Likewise.
6141 (__arm_vreinterpretq_s16_s32): Likewise.
6142 (__arm_vreinterpretq_s16_s64): Likewise.
6143 (__arm_vreinterpretq_s16_s8): Likewise.
6144 (__arm_vreinterpretq_s16_u16): Likewise.
6145 (__arm_vreinterpretq_s16_u32): Likewise.
6146 (__arm_vreinterpretq_s16_u64): Likewise.
6147 (__arm_vreinterpretq_s16_u8): Likewise.
6148 (__arm_vreinterpretq_s32_s16): Likewise.
6149 (__arm_vreinterpretq_s32_s64): Likewise.
6150 (__arm_vreinterpretq_s32_s8): Likewise.
6151 (__arm_vreinterpretq_s32_u16): Likewise.
6152 (__arm_vreinterpretq_s32_u32): Likewise.
6153 (__arm_vreinterpretq_s32_u64): Likewise.
6154 (__arm_vreinterpretq_s32_u8): Likewise.
6155 (__arm_vreinterpretq_s64_s16): Likewise.
6156 (__arm_vreinterpretq_s64_s32): Likewise.
6157 (__arm_vreinterpretq_s64_s8): Likewise.
6158 (__arm_vreinterpretq_s64_u16): Likewise.
6159 (__arm_vreinterpretq_s64_u32): Likewise.
6160 (__arm_vreinterpretq_s64_u64): Likewise.
6161 (__arm_vreinterpretq_s64_u8): Likewise.
6162 (__arm_vreinterpretq_s8_s16): Likewise.
6163 (__arm_vreinterpretq_s8_s32): Likewise.
6164 (__arm_vreinterpretq_s8_s64): Likewise.
6165 (__arm_vreinterpretq_s8_u16): Likewise.
6166 (__arm_vreinterpretq_s8_u32): Likewise.
6167 (__arm_vreinterpretq_s8_u64): Likewise.
6168 (__arm_vreinterpretq_s8_u8): Likewise.
6169 (__arm_vreinterpretq_u16_s16): Likewise.
6170 (__arm_vreinterpretq_u16_s32): Likewise.
6171 (__arm_vreinterpretq_u16_s64): Likewise.
6172 (__arm_vreinterpretq_u16_s8): Likewise.
6173 (__arm_vreinterpretq_u16_u32): Likewise.
6174 (__arm_vreinterpretq_u16_u64): Likewise.
6175 (__arm_vreinterpretq_u16_u8): Likewise.
6176 (__arm_vreinterpretq_u32_s16): Likewise.
6177 (__arm_vreinterpretq_u32_s32): Likewise.
6178 (__arm_vreinterpretq_u32_s64): Likewise.
6179 (__arm_vreinterpretq_u32_s8): Likewise.
6180 (__arm_vreinterpretq_u32_u16): Likewise.
6181 (__arm_vreinterpretq_u32_u64): Likewise.
6182 (__arm_vreinterpretq_u32_u8): Likewise.
6183 (__arm_vreinterpretq_u64_s16): Likewise.
6184 (__arm_vreinterpretq_u64_s32): Likewise.
6185 (__arm_vreinterpretq_u64_s64): Likewise.
6186 (__arm_vreinterpretq_u64_s8): Likewise.
6187 (__arm_vreinterpretq_u64_u16): Likewise.
6188 (__arm_vreinterpretq_u64_u32): Likewise.
6189 (__arm_vreinterpretq_u64_u8): Likewise.
6190 (__arm_vreinterpretq_u8_s16): Likewise.
6191 (__arm_vreinterpretq_u8_s32): Likewise.
6192 (__arm_vreinterpretq_u8_s64): Likewise.
6193 (__arm_vreinterpretq_u8_s8): Likewise.
6194 (__arm_vreinterpretq_u8_u16): Likewise.
6195 (__arm_vreinterpretq_u8_u32): Likewise.
6196 (__arm_vreinterpretq_u8_u64): Likewise.
6197 (__arm_vuninitializedq_f16): Likewise.
6198 (__arm_vuninitializedq_f32): Likewise.
6199 (__arm_vreinterpretq_s32_f16): Likewise.
6200 (__arm_vreinterpretq_s32_f32): Likewise.
6201 (__arm_vreinterpretq_s16_f16): Likewise.
6202 (__arm_vreinterpretq_s16_f32): Likewise.
6203 (__arm_vreinterpretq_s64_f16): Likewise.
6204 (__arm_vreinterpretq_s64_f32): Likewise.
6205 (__arm_vreinterpretq_s8_f16): Likewise.
6206 (__arm_vreinterpretq_s8_f32): Likewise.
6207 (__arm_vreinterpretq_u16_f16): Likewise.
6208 (__arm_vreinterpretq_u16_f32): Likewise.
6209 (__arm_vreinterpretq_u32_f16): Likewise.
6210 (__arm_vreinterpretq_u32_f32): Likewise.
6211 (__arm_vreinterpretq_u64_f16): Likewise.
6212 (__arm_vreinterpretq_u64_f32): Likewise.
6213 (__arm_vreinterpretq_u8_f16): Likewise.
6214 (__arm_vreinterpretq_u8_f32): Likewise.
6215 (__arm_vreinterpretq_f16_f32): Likewise.
6216 (__arm_vreinterpretq_f16_s16): Likewise.
6217 (__arm_vreinterpretq_f16_s32): Likewise.
6218 (__arm_vreinterpretq_f16_s64): Likewise.
6219 (__arm_vreinterpretq_f16_s8): Likewise.
6220 (__arm_vreinterpretq_f16_u16): Likewise.
6221 (__arm_vreinterpretq_f16_u32): Likewise.
6222 (__arm_vreinterpretq_f16_u64): Likewise.
6223 (__arm_vreinterpretq_f16_u8): Likewise.
6224 (__arm_vreinterpretq_f32_f16): Likewise.
6225 (__arm_vreinterpretq_f32_s16): Likewise.
6226 (__arm_vreinterpretq_f32_s32): Likewise.
6227 (__arm_vreinterpretq_f32_s64): Likewise.
6228 (__arm_vreinterpretq_f32_s8): Likewise.
6229 (__arm_vreinterpretq_f32_u16): Likewise.
6230 (__arm_vreinterpretq_f32_u32): Likewise.
6231 (__arm_vreinterpretq_f32_u64): Likewise.
6232 (__arm_vreinterpretq_f32_u8): Likewise.
6233 (vuninitializedq): Define polymorphic variant.
6234 (vreinterpretq_f16): Likewise.
6235 (vreinterpretq_f32): Likewise.
6236 (vreinterpretq_s16): Likewise.
6237 (vreinterpretq_s32): Likewise.
6238 (vreinterpretq_s64): Likewise.
6239 (vreinterpretq_s8): Likewise.
6240 (vreinterpretq_u16): Likewise.
6241 (vreinterpretq_u32): Likewise.
6242 (vreinterpretq_u64): Likewise.
6243 (vreinterpretq_u8): Likewise.
6245 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6246 Andre Vieira <andre.simoesdiasvieira@arm.com>
6247 Mihail Ionescu <mihail.ionescu@arm.com>
6249 * config/arm/arm_mve.h (vaddq_s8): Define macro.
6250 (vaddq_s16): Likewise.
6251 (vaddq_s32): Likewise.
6252 (vaddq_u8): Likewise.
6253 (vaddq_u16): Likewise.
6254 (vaddq_u32): Likewise.
6255 (vaddq_f16): Likewise.
6256 (vaddq_f32): Likewise.
6257 (__arm_vaddq_s8): Define intrinsic.
6258 (__arm_vaddq_s16): Likewise.
6259 (__arm_vaddq_s32): Likewise.
6260 (__arm_vaddq_u8): Likewise.
6261 (__arm_vaddq_u16): Likewise.
6262 (__arm_vaddq_u32): Likewise.
6263 (__arm_vaddq_f16): Likewise.
6264 (__arm_vaddq_f32): Likewise.
6265 (vaddq): Define polymorphic variant.
6266 * config/arm/iterators.md (VNIM): Define mode iterator for common types
6267 Neon, IWMMXT and MVE.
6268 (VNINOTM): Likewise.
6269 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
6270 (mve_vaddq_f<mode>): Define RTL pattern.
6271 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
6272 (addv8hf3_neon): Define RTL pattern.
6273 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
6275 (addv8hf3): Define standard RTL pattern for MVE and Neon.
6276 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.
6278 2020-03-20 Martin Liska <mliska@suse.cz>
6281 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously
6282 build_ref_for_offset function was used and it transforms off to bytes
6285 2020-03-20 Richard Biener <rguenther@suse.de>
6287 PR tree-optimization/94266
6288 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the
6289 type of the underlying object to adjust for the containing
6292 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6294 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
6295 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
6296 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
6298 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6300 * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
6302 2020-03-20 Jakub Jelinek <jakub@redhat.com>
6304 PR tree-optimization/94224
6305 * gimple-ssa-store-merging.c
6306 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping
6307 or adjacent INTEGER_CST rhs_code stores as mergeable if they have
6310 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6312 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve.
6314 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6317 * cgraph.c (cgraph_node::function_symbol): Fix availability computation.
6318 (cgraph_node::function_or_virtual_thunk_symbol): Likewise.
6320 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6323 * cgraphunit.c (process_function_and_variable_attributes): warn
6324 for flatten attribute on alias.
6325 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias.
6327 2020-03-19 Martin Liska <mliska@suse.cz>
6329 * lto-section-in.c: Add ext_symtab.
6330 * lto-streamer-out.c (write_symbol_extension_info): New.
6331 (produce_symtab_extension): New.
6332 (produce_asm_for_decls): Stream also produce_symtab_extension.
6333 * lto-streamer.h (enum lto_section_type): New section.
6335 2020-03-19 Jakub Jelinek <jakub@redhat.com>
6337 PR tree-optimization/94211
6338 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
6339 instead of estimate_num_insns for bb_seq (middle_bb). Rename
6340 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
6343 2020-03-19 Richard Biener <rguenther@suse.de>
6346 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr
6347 and build_ref_for_offset.
6349 2020-03-19 Richard Biener <rguenther@suse.de>
6352 * fold-const.c (fold_binary_loc): Avoid using
6353 build_fold_addr_expr when we really want an ADDR_EXPR.
6355 2020-03-18 Segher Boessenkool <segher@kernel.crashing.org>
6357 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented
6360 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
6362 PR rtl-optimization/90275
6363 * cse.c (cse_insn): Delete no-op register moves too.
6365 2020-03-18 Martin Sebor <msebor@redhat.com>
6368 * cgraphunit.c (process_function_and_variable_attributes): Also
6369 complain about weakref function definitions and drop all effects
6372 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6373 Mihail Ionescu <mihail.ionescu@arm.com>
6374 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6376 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
6377 (vstrdq_scatter_base_p_u64): Likewise.
6378 (vstrdq_scatter_base_s64): Likewise.
6379 (vstrdq_scatter_base_u64): Likewise.
6380 (vstrdq_scatter_offset_p_s64): Likewise.
6381 (vstrdq_scatter_offset_p_u64): Likewise.
6382 (vstrdq_scatter_offset_s64): Likewise.
6383 (vstrdq_scatter_offset_u64): Likewise.
6384 (vstrdq_scatter_shifted_offset_p_s64): Likewise.
6385 (vstrdq_scatter_shifted_offset_p_u64): Likewise.
6386 (vstrdq_scatter_shifted_offset_s64): Likewise.
6387 (vstrdq_scatter_shifted_offset_u64): Likewise.
6388 (vstrhq_scatter_offset_f16): Likewise.
6389 (vstrhq_scatter_offset_p_f16): Likewise.
6390 (vstrhq_scatter_shifted_offset_f16): Likewise.
6391 (vstrhq_scatter_shifted_offset_p_f16): Likewise.
6392 (vstrwq_scatter_base_f32): Likewise.
6393 (vstrwq_scatter_base_p_f32): Likewise.
6394 (vstrwq_scatter_offset_f32): Likewise.
6395 (vstrwq_scatter_offset_p_f32): Likewise.
6396 (vstrwq_scatter_offset_p_s32): Likewise.
6397 (vstrwq_scatter_offset_p_u32): Likewise.
6398 (vstrwq_scatter_offset_s32): Likewise.
6399 (vstrwq_scatter_offset_u32): Likewise.
6400 (vstrwq_scatter_shifted_offset_f32): Likewise.
6401 (vstrwq_scatter_shifted_offset_p_f32): Likewise.
6402 (vstrwq_scatter_shifted_offset_p_s32): Likewise.
6403 (vstrwq_scatter_shifted_offset_p_u32): Likewise.
6404 (vstrwq_scatter_shifted_offset_s32): Likewise.
6405 (vstrwq_scatter_shifted_offset_u32): Likewise.
6406 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
6407 (__arm_vstrdq_scatter_base_p_u64): Likewise.
6408 (__arm_vstrdq_scatter_base_s64): Likewise.
6409 (__arm_vstrdq_scatter_base_u64): Likewise.
6410 (__arm_vstrdq_scatter_offset_p_s64): Likewise.
6411 (__arm_vstrdq_scatter_offset_p_u64): Likewise.
6412 (__arm_vstrdq_scatter_offset_s64): Likewise.
6413 (__arm_vstrdq_scatter_offset_u64): Likewise.
6414 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
6415 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
6416 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
6417 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
6418 (__arm_vstrwq_scatter_offset_p_s32): Likewise.
6419 (__arm_vstrwq_scatter_offset_p_u32): Likewise.
6420 (__arm_vstrwq_scatter_offset_s32): Likewise.
6421 (__arm_vstrwq_scatter_offset_u32): Likewise.
6422 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
6423 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
6424 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
6425 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
6426 (__arm_vstrhq_scatter_offset_f16): Likewise.
6427 (__arm_vstrhq_scatter_offset_p_f16): Likewise.
6428 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
6429 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
6430 (__arm_vstrwq_scatter_base_f32): Likewise.
6431 (__arm_vstrwq_scatter_base_p_f32): Likewise.
6432 (__arm_vstrwq_scatter_offset_f32): Likewise.
6433 (__arm_vstrwq_scatter_offset_p_f32): Likewise.
6434 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
6435 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
6436 (vstrhq_scatter_offset): Define polymorphic variant.
6437 (vstrhq_scatter_offset_p): Likewise.
6438 (vstrhq_scatter_shifted_offset): Likewise.
6439 (vstrhq_scatter_shifted_offset_p): Likewise.
6440 (vstrwq_scatter_base): Likewise.
6441 (vstrwq_scatter_base_p): Likewise.
6442 (vstrwq_scatter_offset): Likewise.
6443 (vstrwq_scatter_offset_p): Likewise.
6444 (vstrwq_scatter_shifted_offset): Likewise.
6445 (vstrwq_scatter_shifted_offset_p): Likewise.
6446 (vstrdq_scatter_base_p): Likewise.
6447 (vstrdq_scatter_base): Likewise.
6448 (vstrdq_scatter_offset_p): Likewise.
6449 (vstrdq_scatter_offset): Likewise.
6450 (vstrdq_scatter_shifted_offset_p): Likewise.
6451 (vstrdq_scatter_shifted_offset): Likewise.
6452 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
6453 (STRSBS_P): Likewise.
6455 (STRSBU_P): Likewise.
6457 (STRSS_P): Likewise.
6459 (STRSU_P): Likewise.
6460 * config/arm/constraints.md (Ri): Define.
6461 * config/arm/mve.md (VSTRDSBQ): Define iterator.
6462 (VSTRDSOQ): Likewise.
6463 (VSTRDSSOQ): Likewise.
6464 (VSTRWSOQ): Likewise.
6465 (VSTRWSSOQ): Likewise.
6466 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
6467 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
6468 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
6469 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
6470 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
6471 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
6472 (mve_vstrhq_scatter_offset_fv8hf): Likewise.
6473 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
6474 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
6475 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
6476 (mve_vstrwq_scatter_base_fv4sf): Likewise.
6477 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
6478 (mve_vstrwq_scatter_offset_fv4sf): Likewise.
6479 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
6480 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
6481 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
6482 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
6483 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
6484 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
6485 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
6486 * config/arm/predicates.md (Ri): Define predicate to check immediate
6487 is the range +/-1016 and multiple of 8.
6489 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6490 Mihail Ionescu <mihail.ionescu@arm.com>
6491 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6493 * config/arm/arm_mve.h (vst1q_f32): Define macro.
6494 (vst1q_f16): Likewise.
6495 (vst1q_s8): Likewise.
6496 (vst1q_s32): Likewise.
6497 (vst1q_s16): Likewise.
6498 (vst1q_u8): Likewise.
6499 (vst1q_u32): Likewise.
6500 (vst1q_u16): Likewise.
6501 (vstrhq_f16): Likewise.
6502 (vstrhq_scatter_offset_s32): Likewise.
6503 (vstrhq_scatter_offset_s16): Likewise.
6504 (vstrhq_scatter_offset_u32): Likewise.
6505 (vstrhq_scatter_offset_u16): Likewise.
6506 (vstrhq_scatter_offset_p_s32): Likewise.
6507 (vstrhq_scatter_offset_p_s16): Likewise.
6508 (vstrhq_scatter_offset_p_u32): Likewise.
6509 (vstrhq_scatter_offset_p_u16): Likewise.
6510 (vstrhq_scatter_shifted_offset_s32): Likewise.
6511 (vstrhq_scatter_shifted_offset_s16): Likewise.
6512 (vstrhq_scatter_shifted_offset_u32): Likewise.
6513 (vstrhq_scatter_shifted_offset_u16): Likewise.
6514 (vstrhq_scatter_shifted_offset_p_s32): Likewise.
6515 (vstrhq_scatter_shifted_offset_p_s16): Likewise.
6516 (vstrhq_scatter_shifted_offset_p_u32): Likewise.
6517 (vstrhq_scatter_shifted_offset_p_u16): Likewise.
6518 (vstrhq_s32): Likewise.
6519 (vstrhq_s16): Likewise.
6520 (vstrhq_u32): Likewise.
6521 (vstrhq_u16): Likewise.
6522 (vstrhq_p_f16): Likewise.
6523 (vstrhq_p_s32): Likewise.
6524 (vstrhq_p_s16): Likewise.
6525 (vstrhq_p_u32): Likewise.
6526 (vstrhq_p_u16): Likewise.
6527 (vstrwq_f32): Likewise.
6528 (vstrwq_s32): Likewise.
6529 (vstrwq_u32): Likewise.
6530 (vstrwq_p_f32): Likewise.
6531 (vstrwq_p_s32): Likewise.
6532 (vstrwq_p_u32): Likewise.
6533 (__arm_vst1q_s8): Define intrinsic.
6534 (__arm_vst1q_s32): Likewise.
6535 (__arm_vst1q_s16): Likewise.
6536 (__arm_vst1q_u8): Likewise.
6537 (__arm_vst1q_u32): Likewise.
6538 (__arm_vst1q_u16): Likewise.
6539 (__arm_vstrhq_scatter_offset_s32): Likewise.
6540 (__arm_vstrhq_scatter_offset_s16): Likewise.
6541 (__arm_vstrhq_scatter_offset_u32): Likewise.
6542 (__arm_vstrhq_scatter_offset_u16): Likewise.
6543 (__arm_vstrhq_scatter_offset_p_s32): Likewise.
6544 (__arm_vstrhq_scatter_offset_p_s16): Likewise.
6545 (__arm_vstrhq_scatter_offset_p_u32): Likewise.
6546 (__arm_vstrhq_scatter_offset_p_u16): Likewise.
6547 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
6548 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
6549 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
6550 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
6551 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
6552 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
6553 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
6554 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
6555 (__arm_vstrhq_s32): Likewise.
6556 (__arm_vstrhq_s16): Likewise.
6557 (__arm_vstrhq_u32): Likewise.
6558 (__arm_vstrhq_u16): Likewise.
6559 (__arm_vstrhq_p_s32): Likewise.
6560 (__arm_vstrhq_p_s16): Likewise.
6561 (__arm_vstrhq_p_u32): Likewise.
6562 (__arm_vstrhq_p_u16): Likewise.
6563 (__arm_vstrwq_s32): Likewise.
6564 (__arm_vstrwq_u32): Likewise.
6565 (__arm_vstrwq_p_s32): Likewise.
6566 (__arm_vstrwq_p_u32): Likewise.
6567 (__arm_vstrwq_p_f32): Likewise.
6568 (__arm_vstrwq_f32): Likewise.
6569 (__arm_vst1q_f32): Likewise.
6570 (__arm_vst1q_f16): Likewise.
6571 (__arm_vstrhq_f16): Likewise.
6572 (__arm_vstrhq_p_f16): Likewise.
6573 (vst1q): Define polymorphic variant.
6575 (vstrhq_p): Likewise.
6576 (vstrhq_scatter_offset_p): Likewise.
6577 (vstrhq_scatter_offset): Likewise.
6578 (vstrhq_scatter_shifted_offset_p): Likewise.
6579 (vstrhq_scatter_shifted_offset): Likewise.
6580 (vstrwq_p): Likewise.
6582 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
6585 (STRSS_P): Likewise.
6587 (STRSU_P): Likewise.
6590 * config/arm/mve.md (VST1Q): Define iterator.
6591 (VSTRHSOQ): Likewise.
6592 (VSTRHSSOQ): Likewise.
6595 (mve_vstrhq_fv8hf): Define RTL pattern.
6596 (mve_vstrhq_p_fv8hf): Likewise.
6597 (mve_vstrhq_p_<supf><mode>): Likewise.
6598 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
6599 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
6600 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
6601 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
6602 (mve_vstrhq_<supf><mode>): Likewise.
6603 (mve_vstrwq_fv4sf): Likewise.
6604 (mve_vstrwq_p_fv4sf): Likewise.
6605 (mve_vstrwq_p_<supf>v4si): Likewise.
6606 (mve_vstrwq_<supf>v4si): Likewise.
6607 (mve_vst1q_f<mode>): Define expand.
6608 (mve_vst1q_<supf><mode>): Likewise.
6610 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6611 Mihail Ionescu <mihail.ionescu@arm.com>
6612 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6614 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6615 (vld1q_s32): Likewise.
6616 (vld1q_s16): Likewise.
6617 (vld1q_u8): Likewise.
6618 (vld1q_u32): Likewise.
6619 (vld1q_u16): Likewise.
6620 (vldrhq_gather_offset_s32): Likewise.
6621 (vldrhq_gather_offset_s16): Likewise.
6622 (vldrhq_gather_offset_u32): Likewise.
6623 (vldrhq_gather_offset_u16): Likewise.
6624 (vldrhq_gather_offset_z_s32): Likewise.
6625 (vldrhq_gather_offset_z_s16): Likewise.
6626 (vldrhq_gather_offset_z_u32): Likewise.
6627 (vldrhq_gather_offset_z_u16): Likewise.
6628 (vldrhq_gather_shifted_offset_s32): Likewise.
6629 (vldrhq_gather_shifted_offset_s16): Likewise.
6630 (vldrhq_gather_shifted_offset_u32): Likewise.
6631 (vldrhq_gather_shifted_offset_u16): Likewise.
6632 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6633 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6634 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6635 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6636 (vldrhq_s32): Likewise.
6637 (vldrhq_s16): Likewise.
6638 (vldrhq_u32): Likewise.
6639 (vldrhq_u16): Likewise.
6640 (vldrhq_z_s32): Likewise.
6641 (vldrhq_z_s16): Likewise.
6642 (vldrhq_z_u32): Likewise.
6643 (vldrhq_z_u16): Likewise.
6644 (vldrwq_s32): Likewise.
6645 (vldrwq_u32): Likewise.
6646 (vldrwq_z_s32): Likewise.
6647 (vldrwq_z_u32): Likewise.
6648 (vld1q_f32): Likewise.
6649 (vld1q_f16): Likewise.
6650 (vldrhq_f16): Likewise.
6651 (vldrhq_z_f16): Likewise.
6652 (vldrwq_f32): Likewise.
6653 (vldrwq_z_f32): Likewise.
6654 (__arm_vld1q_s8): Define intrinsic.
6655 (__arm_vld1q_s32): Likewise.
6656 (__arm_vld1q_s16): Likewise.
6657 (__arm_vld1q_u8): Likewise.
6658 (__arm_vld1q_u32): Likewise.
6659 (__arm_vld1q_u16): Likewise.
6660 (__arm_vldrhq_gather_offset_s32): Likewise.
6661 (__arm_vldrhq_gather_offset_s16): Likewise.
6662 (__arm_vldrhq_gather_offset_u32): Likewise.
6663 (__arm_vldrhq_gather_offset_u16): Likewise.
6664 (__arm_vldrhq_gather_offset_z_s32): Likewise.
6665 (__arm_vldrhq_gather_offset_z_s16): Likewise.
6666 (__arm_vldrhq_gather_offset_z_u32): Likewise.
6667 (__arm_vldrhq_gather_offset_z_u16): Likewise.
6668 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
6669 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
6670 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
6671 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
6672 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
6673 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
6674 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
6675 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
6676 (__arm_vldrhq_s32): Likewise.
6677 (__arm_vldrhq_s16): Likewise.
6678 (__arm_vldrhq_u32): Likewise.
6679 (__arm_vldrhq_u16): Likewise.
6680 (__arm_vldrhq_z_s32): Likewise.
6681 (__arm_vldrhq_z_s16): Likewise.
6682 (__arm_vldrhq_z_u32): Likewise.
6683 (__arm_vldrhq_z_u16): Likewise.
6684 (__arm_vldrwq_s32): Likewise.
6685 (__arm_vldrwq_u32): Likewise.
6686 (__arm_vldrwq_z_s32): Likewise.
6687 (__arm_vldrwq_z_u32): Likewise.
6688 (__arm_vld1q_f32): Likewise.
6689 (__arm_vld1q_f16): Likewise.
6690 (__arm_vldrwq_f32): Likewise.
6691 (__arm_vldrwq_z_f32): Likewise.
6692 (__arm_vldrhq_z_f16): Likewise.
6693 (__arm_vldrhq_f16): Likewise.
6694 (vld1q): Define polymorphic variant.
6695 (vldrhq_gather_offset): Likewise.
6696 (vldrhq_gather_offset_z): Likewise.
6697 (vldrhq_gather_shifted_offset): Likewise.
6698 (vldrhq_gather_shifted_offset_z): Likewise.
6699 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
6703 (LDRGU_Z): Likewise.
6705 (LDRGS_Z): Likewise.
6707 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
6708 (V_sz_elem1): Likewise.
6709 (VLD1Q): Define iterator.
6710 (VLDRHGOQ): Likewise.
6711 (VLDRHGSOQ): Likewise.
6714 (mve_vldrhq_fv8hf): Define RTL pattern.
6715 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
6716 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
6717 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
6718 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
6719 (mve_vldrhq_<supf><mode>): Likewise.
6720 (mve_vldrhq_z_fv8hf): Likewise.
6721 (mve_vldrhq_z_<supf><mode>): Likewise.
6722 (mve_vldrwq_fv4sf): Likewise.
6723 (mve_vldrwq_<supf>v4si): Likewise.
6724 (mve_vldrwq_z_fv4sf): Likewise.
6725 (mve_vldrwq_z_<supf>v4si): Likewise.
6726 (mve_vld1q_f<mode>): Define RTL expand pattern.
6727 (mve_vld1q_<supf><mode>): Likewise.
6729 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6730 Mihail Ionescu <mihail.ionescu@arm.com>
6731 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6733 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6734 (vld1q_s32): Likewise.
6735 (vld1q_s16): Likewise.
6736 (vld1q_u8): Likewise.
6737 (vld1q_u32): Likewise.
6738 (vld1q_u16): Likewise.
6739 (vldrhq_gather_offset_s32): Likewise.
6740 (vldrhq_gather_offset_s16): Likewise.
6741 (vldrhq_gather_offset_u32): Likewise.
6742 (vldrhq_gather_offset_u16): Likewise.
6743 (vldrhq_gather_offset_z_s32): Likewise.
6744 (vldrhq_gather_offset_z_s16): Likewise.
6745 (vldrhq_gather_offset_z_u32): Likewise.
6746 (vldrhq_gather_offset_z_u16): Likewise.
6747 (vldrhq_gather_shifted_offset_s32): Likewise.
6748 (vldrhq_gather_shifted_offset_s16): Likewise.
6749 (vldrhq_gather_shifted_offset_u32): Likewise.
6750 (vldrhq_gather_shifted_offset_u16): Likewise.
6751 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6752 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6753 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6754 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6755 (vldrhq_s32): Likewise.
6756 (vldrhq_s16): Likewise.
6757 (vldrhq_u32): Likewise.
6758 (vldrhq_u16): Likewise.
6759 (vldrhq_z_s32): Likewise.
6760 (vldrhq_z_s16): Likewise.
6761 (vldrhq_z_u32): Likewise.
6762 (vldrhq_z_u16): Likewise.
6763 (vldrwq_s32): Likewise.
6764 (vldrwq_u32): Likewise.
6765 (vldrwq_z_s32): Likewise.
6766 (vldrwq_z_u32): Likewise.
6767 (vld1q_f32): Likewise.
6768 (vld1q_f16): Likewise.
6769 (vldrhq_f16): Likewise.
6770 (vldrhq_z_f16): Likewise.
6771 (vldrwq_f32): Likewise.
6772 (vldrwq_z_f32): Likewise.
6773 (__arm_vld1q_s8): Define intrinsic.
6774 (__arm_vld1q_s32): Likewise.
6775 (__arm_vld1q_s16): Likewise.
6776 (__arm_vld1q_u8): Likewise.
6777 (__arm_vld1q_u32): Likewise.
6778 (__arm_vld1q_u16): Likewise.
6779 (__arm_vldrhq_gather_offset_s32): Likewise.
6780 (__arm_vldrhq_gather_offset_s16): Likewise.
6781 (__arm_vldrhq_gather_offset_u32): Likewise.
6782 (__arm_vldrhq_gather_offset_u16): Likewise.
6783 (__arm_vldrhq_gather_offset_z_s32): Likewise.
6784 (__arm_vldrhq_gather_offset_z_s16): Likewise.
6785 (__arm_vldrhq_gather_offset_z_u32): Likewise.
6786 (__arm_vldrhq_gather_offset_z_u16): Likewise.
6787 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
6788 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
6789 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
6790 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
6791 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
6792 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
6793 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
6794 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
6795 (__arm_vldrhq_s32): Likewise.
6796 (__arm_vldrhq_s16): Likewise.
6797 (__arm_vldrhq_u32): Likewise.
6798 (__arm_vldrhq_u16): Likewise.
6799 (__arm_vldrhq_z_s32): Likewise.
6800 (__arm_vldrhq_z_s16): Likewise.
6801 (__arm_vldrhq_z_u32): Likewise.
6802 (__arm_vldrhq_z_u16): Likewise.
6803 (__arm_vldrwq_s32): Likewise.
6804 (__arm_vldrwq_u32): Likewise.
6805 (__arm_vldrwq_z_s32): Likewise.
6806 (__arm_vldrwq_z_u32): Likewise.
6807 (__arm_vld1q_f32): Likewise.
6808 (__arm_vld1q_f16): Likewise.
6809 (__arm_vldrwq_f32): Likewise.
6810 (__arm_vldrwq_z_f32): Likewise.
6811 (__arm_vldrhq_z_f16): Likewise.
6812 (__arm_vldrhq_f16): Likewise.
6813 (vld1q): Define polymorphic variant.
6814 (vldrhq_gather_offset): Likewise.
6815 (vldrhq_gather_offset_z): Likewise.
6816 (vldrhq_gather_shifted_offset): Likewise.
6817 (vldrhq_gather_shifted_offset_z): Likewise.
6818 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
6822 (LDRGU_Z): Likewise.
6824 (LDRGS_Z): Likewise.
6826 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
6827 (V_sz_elem1): Likewise.
6828 (VLD1Q): Define iterator.
6829 (VLDRHGOQ): Likewise.
6830 (VLDRHGSOQ): Likewise.
6833 (mve_vldrhq_fv8hf): Define RTL pattern.
6834 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
6835 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
6836 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
6837 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
6838 (mve_vldrhq_<supf><mode>): Likewise.
6839 (mve_vldrhq_z_fv8hf): Likewise.
6840 (mve_vldrhq_z_<supf><mode>): Likewise.
6841 (mve_vldrwq_fv4sf): Likewise.
6842 (mve_vldrwq_<supf>v4si): Likewise.
6843 (mve_vldrwq_z_fv4sf): Likewise.
6844 (mve_vldrwq_z_<supf>v4si): Likewise.
6845 (mve_vld1q_f<mode>): Define RTL expand pattern.
6846 (mve_vld1q_<supf><mode>): Likewise.
6848 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6849 Mihail Ionescu <mihail.ionescu@arm.com>
6850 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6852 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
6854 (LDRGBU_Z_QUALIFIERS): Likewise.
6855 (LDRGS_Z_QUALIFIERS): Likewise.
6856 (LDRGU_Z_QUALIFIERS): Likewise.
6857 (LDRS_Z_QUALIFIERS): Likewise.
6858 (LDRU_Z_QUALIFIERS): Likewise.
6859 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
6860 (vldrbq_gather_offset_z_u8): Likewise.
6861 (vldrbq_gather_offset_z_s32): Likewise.
6862 (vldrbq_gather_offset_z_u16): Likewise.
6863 (vldrbq_gather_offset_z_u32): Likewise.
6864 (vldrbq_gather_offset_z_s8): Likewise.
6865 (vldrbq_z_s16): Likewise.
6866 (vldrbq_z_u8): Likewise.
6867 (vldrbq_z_s8): Likewise.
6868 (vldrbq_z_s32): Likewise.
6869 (vldrbq_z_u16): Likewise.
6870 (vldrbq_z_u32): Likewise.
6871 (vldrwq_gather_base_z_u32): Likewise.
6872 (vldrwq_gather_base_z_s32): Likewise.
6873 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
6874 (__arm_vldrbq_gather_offset_z_s32): Likewise.
6875 (__arm_vldrbq_gather_offset_z_s16): Likewise.
6876 (__arm_vldrbq_gather_offset_z_u8): Likewise.
6877 (__arm_vldrbq_gather_offset_z_u32): Likewise.
6878 (__arm_vldrbq_gather_offset_z_u16): Likewise.
6879 (__arm_vldrbq_z_s8): Likewise.
6880 (__arm_vldrbq_z_s32): Likewise.
6881 (__arm_vldrbq_z_s16): Likewise.
6882 (__arm_vldrbq_z_u8): Likewise.
6883 (__arm_vldrbq_z_u32): Likewise.
6884 (__arm_vldrbq_z_u16): Likewise.
6885 (__arm_vldrwq_gather_base_z_s32): Likewise.
6886 (__arm_vldrwq_gather_base_z_u32): Likewise.
6887 (vldrbq_gather_offset_z): Define polymorphic variant.
6888 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
6890 (LDRGBU_Z_QUALIFIERS): Likewise.
6891 (LDRGS_Z_QUALIFIERS): Likewise.
6892 (LDRGU_Z_QUALIFIERS): Likewise.
6893 (LDRS_Z_QUALIFIERS): Likewise.
6894 (LDRU_Z_QUALIFIERS): Likewise.
6895 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
6897 (mve_vldrbq_z_<supf><mode>): Likewise.
6898 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
6900 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6901 Mihail Ionescu <mihail.ionescu@arm.com>
6902 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6904 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin
6906 (STRU_P_QUALIFIERS): Likewise.
6907 (STRSU_P_QUALIFIERS): Likewise.
6908 (STRSS_P_QUALIFIERS): Likewise.
6909 (STRSBS_P_QUALIFIERS): Likewise.
6910 (STRSBU_P_QUALIFIERS): Likewise.
6911 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro.
6912 (vstrbq_p_s32): Likewise.
6913 (vstrbq_p_s16): Likewise.
6914 (vstrbq_p_u8): Likewise.
6915 (vstrbq_p_u32): Likewise.
6916 (vstrbq_p_u16): Likewise.
6917 (vstrbq_scatter_offset_p_s8): Likewise.
6918 (vstrbq_scatter_offset_p_s32): Likewise.
6919 (vstrbq_scatter_offset_p_s16): Likewise.
6920 (vstrbq_scatter_offset_p_u8): Likewise.
6921 (vstrbq_scatter_offset_p_u32): Likewise.
6922 (vstrbq_scatter_offset_p_u16): Likewise.
6923 (vstrwq_scatter_base_p_s32): Likewise.
6924 (vstrwq_scatter_base_p_u32): Likewise.
6925 (__arm_vstrbq_p_s8): Define intrinsic.
6926 (__arm_vstrbq_p_s32): Likewise.
6927 (__arm_vstrbq_p_s16): Likewise.
6928 (__arm_vstrbq_p_u8): Likewise.
6929 (__arm_vstrbq_p_u32): Likewise.
6930 (__arm_vstrbq_p_u16): Likewise.
6931 (__arm_vstrbq_scatter_offset_p_s8): Likewise.
6932 (__arm_vstrbq_scatter_offset_p_s32): Likewise.
6933 (__arm_vstrbq_scatter_offset_p_s16): Likewise.
6934 (__arm_vstrbq_scatter_offset_p_u8): Likewise.
6935 (__arm_vstrbq_scatter_offset_p_u32): Likewise.
6936 (__arm_vstrbq_scatter_offset_p_u16): Likewise.
6937 (__arm_vstrwq_scatter_base_p_s32): Likewise.
6938 (__arm_vstrwq_scatter_base_p_u32): Likewise.
6939 (vstrbq_p): Define polymorphic variant.
6940 (vstrbq_scatter_offset_p): Likewise.
6941 (vstrwq_scatter_base_p): Likewise.
6942 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin
6944 (STRU_P_QUALIFIERS): Likewise.
6945 (STRSU_P_QUALIFIERS): Likewise.
6946 (STRSS_P_QUALIFIERS): Likewise.
6947 (STRSBS_P_QUALIFIERS): Likewise.
6948 (STRSBU_P_QUALIFIERS): Likewise.
6949 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define
6951 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
6952 (mve_vstrbq_p_<supf><mode>): Likewise.
6954 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6955 Mihail Ionescu <mihail.ionescu@arm.com>
6956 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6958 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
6960 (LDRGS_QUALIFIERS): Likewise.
6961 (LDRS_QUALIFIERS): Likewise.
6962 (LDRU_QUALIFIERS): Likewise.
6963 (LDRGBS_QUALIFIERS): Likewise.
6964 (LDRGBU_QUALIFIERS): Likewise.
6965 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
6966 (vldrbq_gather_offset_s8): Likewise.
6967 (vldrbq_s8): Likewise.
6968 (vldrbq_u8): Likewise.
6969 (vldrbq_gather_offset_u16): Likewise.
6970 (vldrbq_gather_offset_s16): Likewise.
6971 (vldrbq_s16): Likewise.
6972 (vldrbq_u16): Likewise.
6973 (vldrbq_gather_offset_u32): Likewise.
6974 (vldrbq_gather_offset_s32): Likewise.
6975 (vldrbq_s32): Likewise.
6976 (vldrbq_u32): Likewise.
6977 (vldrwq_gather_base_s32): Likewise.
6978 (vldrwq_gather_base_u32): Likewise.
6979 (__arm_vldrbq_gather_offset_u8): Define intrinsic.
6980 (__arm_vldrbq_gather_offset_s8): Likewise.
6981 (__arm_vldrbq_s8): Likewise.
6982 (__arm_vldrbq_u8): Likewise.
6983 (__arm_vldrbq_gather_offset_u16): Likewise.
6984 (__arm_vldrbq_gather_offset_s16): Likewise.
6985 (__arm_vldrbq_s16): Likewise.
6986 (__arm_vldrbq_u16): Likewise.
6987 (__arm_vldrbq_gather_offset_u32): Likewise.
6988 (__arm_vldrbq_gather_offset_s32): Likewise.
6989 (__arm_vldrbq_s32): Likewise.
6990 (__arm_vldrbq_u32): Likewise.
6991 (__arm_vldrwq_gather_base_s32): Likewise.
6992 (__arm_vldrwq_gather_base_u32): Likewise.
6993 (vldrbq_gather_offset): Define polymorphic variant.
6994 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin
6996 (LDRGS_QUALIFIERS): Likewise.
6997 (LDRS_QUALIFIERS): Likewise.
6998 (LDRU_QUALIFIERS): Likewise.
6999 (LDRGBS_QUALIFIERS): Likewise.
7000 (LDRGBU_QUALIFIERS): Likewise.
7001 * config/arm/mve.md (VLDRBGOQ): Define iterator.
7003 (VLDRWGBQ): Likewise.
7004 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
7005 (mve_vldrbq_<supf><mode>): Likewise.
7006 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
7008 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7009 Mihail Ionescu <mihail.ionescu@arm.com>
7010 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7012 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier.
7013 (STRU_QUALIFIERS): Likewise.
7014 (STRSS_QUALIFIERS): Likewise.
7015 (STRSU_QUALIFIERS): Likewise.
7016 (STRSBS_QUALIFIERS): Likewise.
7017 (STRSBU_QUALIFIERS): Likewise.
7018 * config/arm/arm_mve.h (vstrbq_s8): Define macro.
7019 (vstrbq_u8): Likewise.
7020 (vstrbq_u16): Likewise.
7021 (vstrbq_scatter_offset_s8): Likewise.
7022 (vstrbq_scatter_offset_u8): Likewise.
7023 (vstrbq_scatter_offset_u16): Likewise.
7024 (vstrbq_s16): Likewise.
7025 (vstrbq_u32): Likewise.
7026 (vstrbq_scatter_offset_s16): Likewise.
7027 (vstrbq_scatter_offset_u32): Likewise.
7028 (vstrbq_s32): Likewise.
7029 (vstrbq_scatter_offset_s32): Likewise.
7030 (vstrwq_scatter_base_s32): Likewise.
7031 (vstrwq_scatter_base_u32): Likewise.
7032 (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
7033 (__arm_vstrbq_scatter_offset_s32): Likewise.
7034 (__arm_vstrbq_scatter_offset_s16): Likewise.
7035 (__arm_vstrbq_scatter_offset_u8): Likewise.
7036 (__arm_vstrbq_scatter_offset_u32): Likewise.
7037 (__arm_vstrbq_scatter_offset_u16): Likewise.
7038 (__arm_vstrbq_s8): Likewise.
7039 (__arm_vstrbq_s32): Likewise.
7040 (__arm_vstrbq_s16): Likewise.
7041 (__arm_vstrbq_u8): Likewise.
7042 (__arm_vstrbq_u32): Likewise.
7043 (__arm_vstrbq_u16): Likewise.
7044 (__arm_vstrwq_scatter_base_s32): Likewise.
7045 (__arm_vstrwq_scatter_base_u32): Likewise.
7046 (vstrbq): Define polymorphic variant.
7047 (vstrbq_scatter_offset): Likewise.
7048 (vstrwq_scatter_base): Likewise.
7049 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
7051 (STRU_QUALIFIERS): Likewise.
7052 (STRSS_QUALIFIERS): Likewise.
7053 (STRSU_QUALIFIERS): Likewise.
7054 (STRSBS_QUALIFIERS): Likewise.
7055 (STRSBU_QUALIFIERS): Likewise.
7056 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator.
7057 (VSTRWSBQ): Define iterators.
7058 (VSTRBSOQ): Likewise.
7060 (mve_vstrbq_<supf><mode>): Define RTL pattern.
7061 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
7062 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
7064 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7065 Mihail Ionescu <mihail.ionescu@arm.com>
7066 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7068 * config/arm/arm_mve.h (vabdq_m_f32): Define macro.
7069 (vabdq_m_f16): Likewise.
7070 (vaddq_m_f32): Likewise.
7071 (vaddq_m_f16): Likewise.
7072 (vaddq_m_n_f32): Likewise.
7073 (vaddq_m_n_f16): Likewise.
7074 (vandq_m_f32): Likewise.
7075 (vandq_m_f16): Likewise.
7076 (vbicq_m_f32): Likewise.
7077 (vbicq_m_f16): Likewise.
7078 (vbrsrq_m_n_f32): Likewise.
7079 (vbrsrq_m_n_f16): Likewise.
7080 (vcaddq_rot270_m_f32): Likewise.
7081 (vcaddq_rot270_m_f16): Likewise.
7082 (vcaddq_rot90_m_f32): Likewise.
7083 (vcaddq_rot90_m_f16): Likewise.
7084 (vcmlaq_m_f32): Likewise.
7085 (vcmlaq_m_f16): Likewise.
7086 (vcmlaq_rot180_m_f32): Likewise.
7087 (vcmlaq_rot180_m_f16): Likewise.
7088 (vcmlaq_rot270_m_f32): Likewise.
7089 (vcmlaq_rot270_m_f16): Likewise.
7090 (vcmlaq_rot90_m_f32): Likewise.
7091 (vcmlaq_rot90_m_f16): Likewise.
7092 (vcmulq_m_f32): Likewise.
7093 (vcmulq_m_f16): Likewise.
7094 (vcmulq_rot180_m_f32): Likewise.
7095 (vcmulq_rot180_m_f16): Likewise.
7096 (vcmulq_rot270_m_f32): Likewise.
7097 (vcmulq_rot270_m_f16): Likewise.
7098 (vcmulq_rot90_m_f32): Likewise.
7099 (vcmulq_rot90_m_f16): Likewise.
7100 (vcvtq_m_n_s32_f32): Likewise.
7101 (vcvtq_m_n_s16_f16): Likewise.
7102 (vcvtq_m_n_u32_f32): Likewise.
7103 (vcvtq_m_n_u16_f16): Likewise.
7104 (veorq_m_f32): Likewise.
7105 (veorq_m_f16): Likewise.
7106 (vfmaq_m_f32): Likewise.
7107 (vfmaq_m_f16): Likewise.
7108 (vfmaq_m_n_f32): Likewise.
7109 (vfmaq_m_n_f16): Likewise.
7110 (vfmasq_m_n_f32): Likewise.
7111 (vfmasq_m_n_f16): Likewise.
7112 (vfmsq_m_f32): Likewise.
7113 (vfmsq_m_f16): Likewise.
7114 (vmaxnmq_m_f32): Likewise.
7115 (vmaxnmq_m_f16): Likewise.
7116 (vminnmq_m_f32): Likewise.
7117 (vminnmq_m_f16): Likewise.
7118 (vmulq_m_f32): Likewise.
7119 (vmulq_m_f16): Likewise.
7120 (vmulq_m_n_f32): Likewise.
7121 (vmulq_m_n_f16): Likewise.
7122 (vornq_m_f32): Likewise.
7123 (vornq_m_f16): Likewise.
7124 (vorrq_m_f32): Likewise.
7125 (vorrq_m_f16): Likewise.
7126 (vsubq_m_f32): Likewise.
7127 (vsubq_m_f16): Likewise.
7128 (vsubq_m_n_f32): Likewise.
7129 (vsubq_m_n_f16): Likewise.
7130 (__attribute__): Likewise.
7131 (__arm_vabdq_m_f32): Likewise.
7132 (__arm_vabdq_m_f16): Likewise.
7133 (__arm_vaddq_m_f32): Likewise.
7134 (__arm_vaddq_m_f16): Likewise.
7135 (__arm_vaddq_m_n_f32): Likewise.
7136 (__arm_vaddq_m_n_f16): Likewise.
7137 (__arm_vandq_m_f32): Likewise.
7138 (__arm_vandq_m_f16): Likewise.
7139 (__arm_vbicq_m_f32): Likewise.
7140 (__arm_vbicq_m_f16): Likewise.
7141 (__arm_vbrsrq_m_n_f32): Likewise.
7142 (__arm_vbrsrq_m_n_f16): Likewise.
7143 (__arm_vcaddq_rot270_m_f32): Likewise.
7144 (__arm_vcaddq_rot270_m_f16): Likewise.
7145 (__arm_vcaddq_rot90_m_f32): Likewise.
7146 (__arm_vcaddq_rot90_m_f16): Likewise.
7147 (__arm_vcmlaq_m_f32): Likewise.
7148 (__arm_vcmlaq_m_f16): Likewise.
7149 (__arm_vcmlaq_rot180_m_f32): Likewise.
7150 (__arm_vcmlaq_rot180_m_f16): Likewise.
7151 (__arm_vcmlaq_rot270_m_f32): Likewise.
7152 (__arm_vcmlaq_rot270_m_f16): Likewise.
7153 (__arm_vcmlaq_rot90_m_f32): Likewise.
7154 (__arm_vcmlaq_rot90_m_f16): Likewise.
7155 (__arm_vcmulq_m_f32): Likewise.
7156 (__arm_vcmulq_m_f16): Likewise.
7157 (__arm_vcmulq_rot180_m_f32): Define intrinsic.
7158 (__arm_vcmulq_rot180_m_f16): Likewise.
7159 (__arm_vcmulq_rot270_m_f32): Likewise.
7160 (__arm_vcmulq_rot270_m_f16): Likewise.
7161 (__arm_vcmulq_rot90_m_f32): Likewise.
7162 (__arm_vcmulq_rot90_m_f16): Likewise.
7163 (__arm_vcvtq_m_n_s32_f32): Likewise.
7164 (__arm_vcvtq_m_n_s16_f16): Likewise.
7165 (__arm_vcvtq_m_n_u32_f32): Likewise.
7166 (__arm_vcvtq_m_n_u16_f16): Likewise.
7167 (__arm_veorq_m_f32): Likewise.
7168 (__arm_veorq_m_f16): Likewise.
7169 (__arm_vfmaq_m_f32): Likewise.
7170 (__arm_vfmaq_m_f16): Likewise.
7171 (__arm_vfmaq_m_n_f32): Likewise.
7172 (__arm_vfmaq_m_n_f16): Likewise.
7173 (__arm_vfmasq_m_n_f32): Likewise.
7174 (__arm_vfmasq_m_n_f16): Likewise.
7175 (__arm_vfmsq_m_f32): Likewise.
7176 (__arm_vfmsq_m_f16): Likewise.
7177 (__arm_vmaxnmq_m_f32): Likewise.
7178 (__arm_vmaxnmq_m_f16): Likewise.
7179 (__arm_vminnmq_m_f32): Likewise.
7180 (__arm_vminnmq_m_f16): Likewise.
7181 (__arm_vmulq_m_f32): Likewise.
7182 (__arm_vmulq_m_f16): Likewise.
7183 (__arm_vmulq_m_n_f32): Likewise.
7184 (__arm_vmulq_m_n_f16): Likewise.
7185 (__arm_vornq_m_f32): Likewise.
7186 (__arm_vornq_m_f16): Likewise.
7187 (__arm_vorrq_m_f32): Likewise.
7188 (__arm_vorrq_m_f16): Likewise.
7189 (__arm_vsubq_m_f32): Likewise.
7190 (__arm_vsubq_m_f16): Likewise.
7191 (__arm_vsubq_m_n_f32): Likewise.
7192 (__arm_vsubq_m_n_f16): Likewise.
7193 (vabdq_m): Define polymorphic variant.
7194 (vaddq_m): Likewise.
7195 (vaddq_m_n): Likewise.
7196 (vandq_m): Likewise.
7197 (vbicq_m): Likewise.
7198 (vbrsrq_m_n): Likewise.
7199 (vcaddq_rot270_m): Likewise.
7200 (vcaddq_rot90_m): Likewise.
7201 (vcmlaq_m): Likewise.
7202 (vcmlaq_rot180_m): Likewise.
7203 (vcmlaq_rot270_m): Likewise.
7204 (vcmlaq_rot90_m): Likewise.
7205 (vcmulq_m): Likewise.
7206 (vcmulq_rot180_m): Likewise.
7207 (vcmulq_rot270_m): Likewise.
7208 (vcmulq_rot90_m): Likewise.
7209 (veorq_m): Likewise.
7210 (vfmaq_m): Likewise.
7211 (vfmaq_m_n): Likewise.
7212 (vfmasq_m_n): Likewise.
7213 (vfmsq_m): Likewise.
7214 (vmaxnmq_m): Likewise.
7215 (vminnmq_m): Likewise.
7216 (vmulq_m): Likewise.
7217 (vmulq_m_n): Likewise.
7218 (vornq_m): Likewise.
7219 (vsubq_m): Likewise.
7220 (vsubq_m_n): Likewise.
7221 (vorrq_m): Likewise.
7222 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7224 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7225 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7226 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
7227 (mve_vaddq_m_f<mode>): Likewise.
7228 (mve_vaddq_m_n_f<mode>): Likewise.
7229 (mve_vandq_m_f<mode>): Likewise.
7230 (mve_vbicq_m_f<mode>): Likewise.
7231 (mve_vbrsrq_m_n_f<mode>): Likewise.
7232 (mve_vcaddq_rot270_m_f<mode>): Likewise.
7233 (mve_vcaddq_rot90_m_f<mode>): Likewise.
7234 (mve_vcmlaq_m_f<mode>): Likewise.
7235 (mve_vcmlaq_rot180_m_f<mode>): Likewise.
7236 (mve_vcmlaq_rot270_m_f<mode>): Likewise.
7237 (mve_vcmlaq_rot90_m_f<mode>): Likewise.
7238 (mve_vcmulq_m_f<mode>): Likewise.
7239 (mve_vcmulq_rot180_m_f<mode>): Likewise.
7240 (mve_vcmulq_rot270_m_f<mode>): Likewise.
7241 (mve_vcmulq_rot90_m_f<mode>): Likewise.
7242 (mve_veorq_m_f<mode>): Likewise.
7243 (mve_vfmaq_m_f<mode>): Likewise.
7244 (mve_vfmaq_m_n_f<mode>): Likewise.
7245 (mve_vfmasq_m_n_f<mode>): Likewise.
7246 (mve_vfmsq_m_f<mode>): Likewise.
7247 (mve_vmaxnmq_m_f<mode>): Likewise.
7248 (mve_vminnmq_m_f<mode>): Likewise.
7249 (mve_vmulq_m_f<mode>): Likewise.
7250 (mve_vmulq_m_n_f<mode>): Likewise.
7251 (mve_vornq_m_f<mode>): Likewise.
7252 (mve_vorrq_m_f<mode>): Likewise.
7253 (mve_vsubq_m_f<mode>): Likewise.
7254 (mve_vsubq_m_n_f<mode>): Likewise.
7256 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7257 Mihail Ionescu <mihail.ionescu@arm.com>
7258 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7260 * config/arm/arm-protos.h (arm_mve_immediate_check):
7261 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check
7262 mode and interger value.
7263 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
7264 (vmlaldavaq_p_s16): Likewise.
7265 (vmlaldavaq_p_u32): Likewise.
7266 (vmlaldavaq_p_u16): Likewise.
7267 (vmlaldavaxq_p_s32): Likewise.
7268 (vmlaldavaxq_p_s16): Likewise.
7269 (vmlaldavaxq_p_u32): Likewise.
7270 (vmlaldavaxq_p_u16): Likewise.
7271 (vmlsldavaq_p_s32): Likewise.
7272 (vmlsldavaq_p_s16): Likewise.
7273 (vmlsldavaxq_p_s32): Likewise.
7274 (vmlsldavaxq_p_s16): Likewise.
7275 (vmullbq_poly_m_p8): Likewise.
7276 (vmullbq_poly_m_p16): Likewise.
7277 (vmulltq_poly_m_p8): Likewise.
7278 (vmulltq_poly_m_p16): Likewise.
7279 (vqdmullbq_m_n_s32): Likewise.
7280 (vqdmullbq_m_n_s16): Likewise.
7281 (vqdmullbq_m_s32): Likewise.
7282 (vqdmullbq_m_s16): Likewise.
7283 (vqdmulltq_m_n_s32): Likewise.
7284 (vqdmulltq_m_n_s16): Likewise.
7285 (vqdmulltq_m_s32): Likewise.
7286 (vqdmulltq_m_s16): Likewise.
7287 (vqrshrnbq_m_n_s32): Likewise.
7288 (vqrshrnbq_m_n_s16): Likewise.
7289 (vqrshrnbq_m_n_u32): Likewise.
7290 (vqrshrnbq_m_n_u16): Likewise.
7291 (vqrshrntq_m_n_s32): Likewise.
7292 (vqrshrntq_m_n_s16): Likewise.
7293 (vqrshrntq_m_n_u32): Likewise.
7294 (vqrshrntq_m_n_u16): Likewise.
7295 (vqrshrunbq_m_n_s32): Likewise.
7296 (vqrshrunbq_m_n_s16): Likewise.
7297 (vqrshruntq_m_n_s32): Likewise.
7298 (vqrshruntq_m_n_s16): Likewise.
7299 (vqshrnbq_m_n_s32): Likewise.
7300 (vqshrnbq_m_n_s16): Likewise.
7301 (vqshrnbq_m_n_u32): Likewise.
7302 (vqshrnbq_m_n_u16): Likewise.
7303 (vqshrntq_m_n_s32): Likewise.
7304 (vqshrntq_m_n_s16): Likewise.
7305 (vqshrntq_m_n_u32): Likewise.
7306 (vqshrntq_m_n_u16): Likewise.
7307 (vqshrunbq_m_n_s32): Likewise.
7308 (vqshrunbq_m_n_s16): Likewise.
7309 (vqshruntq_m_n_s32): Likewise.
7310 (vqshruntq_m_n_s16): Likewise.
7311 (vrmlaldavhaq_p_s32): Likewise.
7312 (vrmlaldavhaq_p_u32): Likewise.
7313 (vrmlaldavhaxq_p_s32): Likewise.
7314 (vrmlsldavhaq_p_s32): Likewise.
7315 (vrmlsldavhaxq_p_s32): Likewise.
7316 (vrshrnbq_m_n_s32): Likewise.
7317 (vrshrnbq_m_n_s16): Likewise.
7318 (vrshrnbq_m_n_u32): Likewise.
7319 (vrshrnbq_m_n_u16): Likewise.
7320 (vrshrntq_m_n_s32): Likewise.
7321 (vrshrntq_m_n_s16): Likewise.
7322 (vrshrntq_m_n_u32): Likewise.
7323 (vrshrntq_m_n_u16): Likewise.
7324 (vshllbq_m_n_s8): Likewise.
7325 (vshllbq_m_n_s16): Likewise.
7326 (vshllbq_m_n_u8): Likewise.
7327 (vshllbq_m_n_u16): Likewise.
7328 (vshlltq_m_n_s8): Likewise.
7329 (vshlltq_m_n_s16): Likewise.
7330 (vshlltq_m_n_u8): Likewise.
7331 (vshlltq_m_n_u16): Likewise.
7332 (vshrnbq_m_n_s32): Likewise.
7333 (vshrnbq_m_n_s16): Likewise.
7334 (vshrnbq_m_n_u32): Likewise.
7335 (vshrnbq_m_n_u16): Likewise.
7336 (vshrntq_m_n_s32): Likewise.
7337 (vshrntq_m_n_s16): Likewise.
7338 (vshrntq_m_n_u32): Likewise.
7339 (vshrntq_m_n_u16): Likewise.
7340 (__arm_vmlaldavaq_p_s32): Define intrinsic.
7341 (__arm_vmlaldavaq_p_s16): Likewise.
7342 (__arm_vmlaldavaq_p_u32): Likewise.
7343 (__arm_vmlaldavaq_p_u16): Likewise.
7344 (__arm_vmlaldavaxq_p_s32): Likewise.
7345 (__arm_vmlaldavaxq_p_s16): Likewise.
7346 (__arm_vmlaldavaxq_p_u32): Likewise.
7347 (__arm_vmlaldavaxq_p_u16): Likewise.
7348 (__arm_vmlsldavaq_p_s32): Likewise.
7349 (__arm_vmlsldavaq_p_s16): Likewise.
7350 (__arm_vmlsldavaxq_p_s32): Likewise.
7351 (__arm_vmlsldavaxq_p_s16): Likewise.
7352 (__arm_vmullbq_poly_m_p8): Likewise.
7353 (__arm_vmullbq_poly_m_p16): Likewise.
7354 (__arm_vmulltq_poly_m_p8): Likewise.
7355 (__arm_vmulltq_poly_m_p16): Likewise.
7356 (__arm_vqdmullbq_m_n_s32): Likewise.
7357 (__arm_vqdmullbq_m_n_s16): Likewise.
7358 (__arm_vqdmullbq_m_s32): Likewise.
7359 (__arm_vqdmullbq_m_s16): Likewise.
7360 (__arm_vqdmulltq_m_n_s32): Likewise.
7361 (__arm_vqdmulltq_m_n_s16): Likewise.
7362 (__arm_vqdmulltq_m_s32): Likewise.
7363 (__arm_vqdmulltq_m_s16): Likewise.
7364 (__arm_vqrshrnbq_m_n_s32): Likewise.
7365 (__arm_vqrshrnbq_m_n_s16): Likewise.
7366 (__arm_vqrshrnbq_m_n_u32): Likewise.
7367 (__arm_vqrshrnbq_m_n_u16): Likewise.
7368 (__arm_vqrshrntq_m_n_s32): Likewise.
7369 (__arm_vqrshrntq_m_n_s16): Likewise.
7370 (__arm_vqrshrntq_m_n_u32): Likewise.
7371 (__arm_vqrshrntq_m_n_u16): Likewise.
7372 (__arm_vqrshrunbq_m_n_s32): Likewise.
7373 (__arm_vqrshrunbq_m_n_s16): Likewise.
7374 (__arm_vqrshruntq_m_n_s32): Likewise.
7375 (__arm_vqrshruntq_m_n_s16): Likewise.
7376 (__arm_vqshrnbq_m_n_s32): Likewise.
7377 (__arm_vqshrnbq_m_n_s16): Likewise.
7378 (__arm_vqshrnbq_m_n_u32): Likewise.
7379 (__arm_vqshrnbq_m_n_u16): Likewise.
7380 (__arm_vqshrntq_m_n_s32): Likewise.
7381 (__arm_vqshrntq_m_n_s16): Likewise.
7382 (__arm_vqshrntq_m_n_u32): Likewise.
7383 (__arm_vqshrntq_m_n_u16): Likewise.
7384 (__arm_vqshrunbq_m_n_s32): Likewise.
7385 (__arm_vqshrunbq_m_n_s16): Likewise.
7386 (__arm_vqshruntq_m_n_s32): Likewise.
7387 (__arm_vqshruntq_m_n_s16): Likewise.
7388 (__arm_vrmlaldavhaq_p_s32): Likewise.
7389 (__arm_vrmlaldavhaq_p_u32): Likewise.
7390 (__arm_vrmlaldavhaxq_p_s32): Likewise.
7391 (__arm_vrmlsldavhaq_p_s32): Likewise.
7392 (__arm_vrmlsldavhaxq_p_s32): Likewise.
7393 (__arm_vrshrnbq_m_n_s32): Likewise.
7394 (__arm_vrshrnbq_m_n_s16): Likewise.
7395 (__arm_vrshrnbq_m_n_u32): Likewise.
7396 (__arm_vrshrnbq_m_n_u16): Likewise.
7397 (__arm_vrshrntq_m_n_s32): Likewise.
7398 (__arm_vrshrntq_m_n_s16): Likewise.
7399 (__arm_vrshrntq_m_n_u32): Likewise.
7400 (__arm_vrshrntq_m_n_u16): Likewise.
7401 (__arm_vshllbq_m_n_s8): Likewise.
7402 (__arm_vshllbq_m_n_s16): Likewise.
7403 (__arm_vshllbq_m_n_u8): Likewise.
7404 (__arm_vshllbq_m_n_u16): Likewise.
7405 (__arm_vshlltq_m_n_s8): Likewise.
7406 (__arm_vshlltq_m_n_s16): Likewise.
7407 (__arm_vshlltq_m_n_u8): Likewise.
7408 (__arm_vshlltq_m_n_u16): Likewise.
7409 (__arm_vshrnbq_m_n_s32): Likewise.
7410 (__arm_vshrnbq_m_n_s16): Likewise.
7411 (__arm_vshrnbq_m_n_u32): Likewise.
7412 (__arm_vshrnbq_m_n_u16): Likewise.
7413 (__arm_vshrntq_m_n_s32): Likewise.
7414 (__arm_vshrntq_m_n_s16): Likewise.
7415 (__arm_vshrntq_m_n_u32): Likewise.
7416 (__arm_vshrntq_m_n_u16): Likewise.
7417 (vmullbq_poly_m): Define polymorphic variant.
7418 (vmulltq_poly_m): Likewise.
7419 (vshllbq_m): Likewise.
7420 (vshrntq_m_n): Likewise.
7421 (vshrnbq_m_n): Likewise.
7422 (vshlltq_m_n): Likewise.
7423 (vshllbq_m_n): Likewise.
7424 (vrshrntq_m_n): Likewise.
7425 (vrshrnbq_m_n): Likewise.
7426 (vqshruntq_m_n): Likewise.
7427 (vqshrunbq_m_n): Likewise.
7428 (vqdmullbq_m_n): Likewise.
7429 (vqdmullbq_m): Likewise.
7430 (vqdmulltq_m_n): Likewise.
7431 (vqdmulltq_m): Likewise.
7432 (vqrshrnbq_m_n): Likewise.
7433 (vqrshrntq_m_n): Likewise.
7434 (vqrshrunbq_m_n): Likewise.
7435 (vqrshruntq_m_n): Likewise.
7436 (vqshrnbq_m_n): Likewise.
7437 (vqshrntq_m_n): Likewise.
7438 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7440 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7441 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7442 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
7443 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
7444 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
7445 (VMLALDAVAXQ_P): Likewise.
7446 (VQRSHRNBQ_M_N): Likewise.
7447 (VQRSHRNTQ_M_N): Likewise.
7448 (VQSHRNBQ_M_N): Likewise.
7449 (VQSHRNTQ_M_N): Likewise.
7450 (VRSHRNBQ_M_N): Likewise.
7451 (VRSHRNTQ_M_N): Likewise.
7452 (VSHLLBQ_M_N): Likewise.
7453 (VSHLLTQ_M_N): Likewise.
7454 (VSHRNBQ_M_N): Likewise.
7455 (VSHRNTQ_M_N): Likewise.
7456 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
7457 (mve_vmlaldavaxq_p_<supf><mode>): Likewise.
7458 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
7459 (mve_vqrshrntq_m_n_<supf><mode>): Likewise.
7460 (mve_vqshrnbq_m_n_<supf><mode>): Likewise.
7461 (mve_vqshrntq_m_n_<supf><mode>): Likewise.
7462 (mve_vrmlaldavhaq_p_sv4si): Likewise.
7463 (mve_vrshrnbq_m_n_<supf><mode>): Likewise.
7464 (mve_vrshrntq_m_n_<supf><mode>): Likewise.
7465 (mve_vshllbq_m_n_<supf><mode>): Likewise.
7466 (mve_vshlltq_m_n_<supf><mode>): Likewise.
7467 (mve_vshrnbq_m_n_<supf><mode>): Likewise.
7468 (mve_vshrntq_m_n_<supf><mode>): Likewise.
7469 (mve_vmlsldavaq_p_s<mode>): Likewise.
7470 (mve_vmlsldavaxq_p_s<mode>): Likewise.
7471 (mve_vmullbq_poly_m_p<mode>): Likewise.
7472 (mve_vmulltq_poly_m_p<mode>): Likewise.
7473 (mve_vqdmullbq_m_n_s<mode>): Likewise.
7474 (mve_vqdmullbq_m_s<mode>): Likewise.
7475 (mve_vqdmulltq_m_n_s<mode>): Likewise.
7476 (mve_vqdmulltq_m_s<mode>): Likewise.
7477 (mve_vqrshrunbq_m_n_s<mode>): Likewise.
7478 (mve_vqrshruntq_m_n_s<mode>): Likewise.
7479 (mve_vqshrunbq_m_n_s<mode>): Likewise.
7480 (mve_vqshruntq_m_n_s<mode>): Likewise.
7481 (mve_vrmlaldavhaq_p_uv4si): Likewise.
7482 (mve_vrmlaldavhaxq_p_sv4si): Likewise.
7483 (mve_vrmlsldavhaq_p_sv4si): Likewise.
7484 (mve_vrmlsldavhaxq_p_sv4si): Likewise.
7486 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7487 Mihail Ionescu <mihail.ionescu@arm.com>
7488 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7490 * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
7491 (vabdq_m_s32): Likewise.
7492 (vabdq_m_s16): Likewise.
7493 (vabdq_m_u8): Likewise.
7494 (vabdq_m_u32): Likewise.
7495 (vabdq_m_u16): Likewise.
7496 (vaddq_m_n_s8): Likewise.
7497 (vaddq_m_n_s32): Likewise.
7498 (vaddq_m_n_s16): Likewise.
7499 (vaddq_m_n_u8): Likewise.
7500 (vaddq_m_n_u32): Likewise.
7501 (vaddq_m_n_u16): Likewise.
7502 (vaddq_m_s8): Likewise.
7503 (vaddq_m_s32): Likewise.
7504 (vaddq_m_s16): Likewise.
7505 (vaddq_m_u8): Likewise.
7506 (vaddq_m_u32): Likewise.
7507 (vaddq_m_u16): Likewise.
7508 (vandq_m_s8): Likewise.
7509 (vandq_m_s32): Likewise.
7510 (vandq_m_s16): Likewise.
7511 (vandq_m_u8): Likewise.
7512 (vandq_m_u32): Likewise.
7513 (vandq_m_u16): Likewise.
7514 (vbicq_m_s8): Likewise.
7515 (vbicq_m_s32): Likewise.
7516 (vbicq_m_s16): Likewise.
7517 (vbicq_m_u8): Likewise.
7518 (vbicq_m_u32): Likewise.
7519 (vbicq_m_u16): Likewise.
7520 (vbrsrq_m_n_s8): Likewise.
7521 (vbrsrq_m_n_s32): Likewise.
7522 (vbrsrq_m_n_s16): Likewise.
7523 (vbrsrq_m_n_u8): Likewise.
7524 (vbrsrq_m_n_u32): Likewise.
7525 (vbrsrq_m_n_u16): Likewise.
7526 (vcaddq_rot270_m_s8): Likewise.
7527 (vcaddq_rot270_m_s32): Likewise.
7528 (vcaddq_rot270_m_s16): Likewise.
7529 (vcaddq_rot270_m_u8): Likewise.
7530 (vcaddq_rot270_m_u32): Likewise.
7531 (vcaddq_rot270_m_u16): Likewise.
7532 (vcaddq_rot90_m_s8): Likewise.
7533 (vcaddq_rot90_m_s32): Likewise.
7534 (vcaddq_rot90_m_s16): Likewise.
7535 (vcaddq_rot90_m_u8): Likewise.
7536 (vcaddq_rot90_m_u32): Likewise.
7537 (vcaddq_rot90_m_u16): Likewise.
7538 (veorq_m_s8): Likewise.
7539 (veorq_m_s32): Likewise.
7540 (veorq_m_s16): Likewise.
7541 (veorq_m_u8): Likewise.
7542 (veorq_m_u32): Likewise.
7543 (veorq_m_u16): Likewise.
7544 (vhaddq_m_n_s8): Likewise.
7545 (vhaddq_m_n_s32): Likewise.
7546 (vhaddq_m_n_s16): Likewise.
7547 (vhaddq_m_n_u8): Likewise.
7548 (vhaddq_m_n_u32): Likewise.
7549 (vhaddq_m_n_u16): Likewise.
7550 (vhaddq_m_s8): Likewise.
7551 (vhaddq_m_s32): Likewise.
7552 (vhaddq_m_s16): Likewise.
7553 (vhaddq_m_u8): Likewise.
7554 (vhaddq_m_u32): Likewise.
7555 (vhaddq_m_u16): Likewise.
7556 (vhcaddq_rot270_m_s8): Likewise.
7557 (vhcaddq_rot270_m_s32): Likewise.
7558 (vhcaddq_rot270_m_s16): Likewise.
7559 (vhcaddq_rot90_m_s8): Likewise.
7560 (vhcaddq_rot90_m_s32): Likewise.
7561 (vhcaddq_rot90_m_s16): Likewise.
7562 (vhsubq_m_n_s8): Likewise.
7563 (vhsubq_m_n_s32): Likewise.
7564 (vhsubq_m_n_s16): Likewise.
7565 (vhsubq_m_n_u8): Likewise.
7566 (vhsubq_m_n_u32): Likewise.
7567 (vhsubq_m_n_u16): Likewise.
7568 (vhsubq_m_s8): Likewise.
7569 (vhsubq_m_s32): Likewise.
7570 (vhsubq_m_s16): Likewise.
7571 (vhsubq_m_u8): Likewise.
7572 (vhsubq_m_u32): Likewise.
7573 (vhsubq_m_u16): Likewise.
7574 (vmaxq_m_s8): Likewise.
7575 (vmaxq_m_s32): Likewise.
7576 (vmaxq_m_s16): Likewise.
7577 (vmaxq_m_u8): Likewise.
7578 (vmaxq_m_u32): Likewise.
7579 (vmaxq_m_u16): Likewise.
7580 (vminq_m_s8): Likewise.
7581 (vminq_m_s32): Likewise.
7582 (vminq_m_s16): Likewise.
7583 (vminq_m_u8): Likewise.
7584 (vminq_m_u32): Likewise.
7585 (vminq_m_u16): Likewise.
7586 (vmladavaq_p_s8): Likewise.
7587 (vmladavaq_p_s32): Likewise.
7588 (vmladavaq_p_s16): Likewise.
7589 (vmladavaq_p_u8): Likewise.
7590 (vmladavaq_p_u32): Likewise.
7591 (vmladavaq_p_u16): Likewise.
7592 (vmladavaxq_p_s8): Likewise.
7593 (vmladavaxq_p_s32): Likewise.
7594 (vmladavaxq_p_s16): Likewise.
7595 (vmlaq_m_n_s8): Likewise.
7596 (vmlaq_m_n_s32): Likewise.
7597 (vmlaq_m_n_s16): Likewise.
7598 (vmlaq_m_n_u8): Likewise.
7599 (vmlaq_m_n_u32): Likewise.
7600 (vmlaq_m_n_u16): Likewise.
7601 (vmlasq_m_n_s8): Likewise.
7602 (vmlasq_m_n_s32): Likewise.
7603 (vmlasq_m_n_s16): Likewise.
7604 (vmlasq_m_n_u8): Likewise.
7605 (vmlasq_m_n_u32): Likewise.
7606 (vmlasq_m_n_u16): Likewise.
7607 (vmlsdavaq_p_s8): Likewise.
7608 (vmlsdavaq_p_s32): Likewise.
7609 (vmlsdavaq_p_s16): Likewise.
7610 (vmlsdavaxq_p_s8): Likewise.
7611 (vmlsdavaxq_p_s32): Likewise.
7612 (vmlsdavaxq_p_s16): Likewise.
7613 (vmulhq_m_s8): Likewise.
7614 (vmulhq_m_s32): Likewise.
7615 (vmulhq_m_s16): Likewise.
7616 (vmulhq_m_u8): Likewise.
7617 (vmulhq_m_u32): Likewise.
7618 (vmulhq_m_u16): Likewise.
7619 (vmullbq_int_m_s8): Likewise.
7620 (vmullbq_int_m_s32): Likewise.
7621 (vmullbq_int_m_s16): Likewise.
7622 (vmullbq_int_m_u8): Likewise.
7623 (vmullbq_int_m_u32): Likewise.
7624 (vmullbq_int_m_u16): Likewise.
7625 (vmulltq_int_m_s8): Likewise.
7626 (vmulltq_int_m_s32): Likewise.
7627 (vmulltq_int_m_s16): Likewise.
7628 (vmulltq_int_m_u8): Likewise.
7629 (vmulltq_int_m_u32): Likewise.
7630 (vmulltq_int_m_u16): Likewise.
7631 (vmulq_m_n_s8): Likewise.
7632 (vmulq_m_n_s32): Likewise.
7633 (vmulq_m_n_s16): Likewise.
7634 (vmulq_m_n_u8): Likewise.
7635 (vmulq_m_n_u32): Likewise.
7636 (vmulq_m_n_u16): Likewise.
7637 (vmulq_m_s8): Likewise.
7638 (vmulq_m_s32): Likewise.
7639 (vmulq_m_s16): Likewise.
7640 (vmulq_m_u8): Likewise.
7641 (vmulq_m_u32): Likewise.
7642 (vmulq_m_u16): Likewise.
7643 (vornq_m_s8): Likewise.
7644 (vornq_m_s32): Likewise.
7645 (vornq_m_s16): Likewise.
7646 (vornq_m_u8): Likewise.
7647 (vornq_m_u32): Likewise.
7648 (vornq_m_u16): Likewise.
7649 (vorrq_m_s8): Likewise.
7650 (vorrq_m_s32): Likewise.
7651 (vorrq_m_s16): Likewise.
7652 (vorrq_m_u8): Likewise.
7653 (vorrq_m_u32): Likewise.
7654 (vorrq_m_u16): Likewise.
7655 (vqaddq_m_n_s8): Likewise.
7656 (vqaddq_m_n_s32): Likewise.
7657 (vqaddq_m_n_s16): Likewise.
7658 (vqaddq_m_n_u8): Likewise.
7659 (vqaddq_m_n_u32): Likewise.
7660 (vqaddq_m_n_u16): Likewise.
7661 (vqaddq_m_s8): Likewise.
7662 (vqaddq_m_s32): Likewise.
7663 (vqaddq_m_s16): Likewise.
7664 (vqaddq_m_u8): Likewise.
7665 (vqaddq_m_u32): Likewise.
7666 (vqaddq_m_u16): Likewise.
7667 (vqdmladhq_m_s8): Likewise.
7668 (vqdmladhq_m_s32): Likewise.
7669 (vqdmladhq_m_s16): Likewise.
7670 (vqdmladhxq_m_s8): Likewise.
7671 (vqdmladhxq_m_s32): Likewise.
7672 (vqdmladhxq_m_s16): Likewise.
7673 (vqdmlahq_m_n_s8): Likewise.
7674 (vqdmlahq_m_n_s32): Likewise.
7675 (vqdmlahq_m_n_s16): Likewise.
7676 (vqdmlahq_m_n_u8): Likewise.
7677 (vqdmlahq_m_n_u32): Likewise.
7678 (vqdmlahq_m_n_u16): Likewise.
7679 (vqdmlsdhq_m_s8): Likewise.
7680 (vqdmlsdhq_m_s32): Likewise.
7681 (vqdmlsdhq_m_s16): Likewise.
7682 (vqdmlsdhxq_m_s8): Likewise.
7683 (vqdmlsdhxq_m_s32): Likewise.
7684 (vqdmlsdhxq_m_s16): Likewise.
7685 (vqdmulhq_m_n_s8): Likewise.
7686 (vqdmulhq_m_n_s32): Likewise.
7687 (vqdmulhq_m_n_s16): Likewise.
7688 (vqdmulhq_m_s8): Likewise.
7689 (vqdmulhq_m_s32): Likewise.
7690 (vqdmulhq_m_s16): Likewise.
7691 (vqrdmladhq_m_s8): Likewise.
7692 (vqrdmladhq_m_s32): Likewise.
7693 (vqrdmladhq_m_s16): Likewise.
7694 (vqrdmladhxq_m_s8): Likewise.
7695 (vqrdmladhxq_m_s32): Likewise.
7696 (vqrdmladhxq_m_s16): Likewise.
7697 (vqrdmlahq_m_n_s8): Likewise.
7698 (vqrdmlahq_m_n_s32): Likewise.
7699 (vqrdmlahq_m_n_s16): Likewise.
7700 (vqrdmlahq_m_n_u8): Likewise.
7701 (vqrdmlahq_m_n_u32): Likewise.
7702 (vqrdmlahq_m_n_u16): Likewise.
7703 (vqrdmlashq_m_n_s8): Likewise.
7704 (vqrdmlashq_m_n_s32): Likewise.
7705 (vqrdmlashq_m_n_s16): Likewise.
7706 (vqrdmlashq_m_n_u8): Likewise.
7707 (vqrdmlashq_m_n_u32): Likewise.
7708 (vqrdmlashq_m_n_u16): Likewise.
7709 (vqrdmlsdhq_m_s8): Likewise.
7710 (vqrdmlsdhq_m_s32): Likewise.
7711 (vqrdmlsdhq_m_s16): Likewise.
7712 (vqrdmlsdhxq_m_s8): Likewise.
7713 (vqrdmlsdhxq_m_s32): Likewise.
7714 (vqrdmlsdhxq_m_s16): Likewise.
7715 (vqrdmulhq_m_n_s8): Likewise.
7716 (vqrdmulhq_m_n_s32): Likewise.
7717 (vqrdmulhq_m_n_s16): Likewise.
7718 (vqrdmulhq_m_s8): Likewise.
7719 (vqrdmulhq_m_s32): Likewise.
7720 (vqrdmulhq_m_s16): Likewise.
7721 (vqrshlq_m_s8): Likewise.
7722 (vqrshlq_m_s32): Likewise.
7723 (vqrshlq_m_s16): Likewise.
7724 (vqrshlq_m_u8): Likewise.
7725 (vqrshlq_m_u32): Likewise.
7726 (vqrshlq_m_u16): Likewise.
7727 (vqshlq_m_n_s8): Likewise.
7728 (vqshlq_m_n_s32): Likewise.
7729 (vqshlq_m_n_s16): Likewise.
7730 (vqshlq_m_n_u8): Likewise.
7731 (vqshlq_m_n_u32): Likewise.
7732 (vqshlq_m_n_u16): Likewise.
7733 (vqshlq_m_s8): Likewise.
7734 (vqshlq_m_s32): Likewise.
7735 (vqshlq_m_s16): Likewise.
7736 (vqshlq_m_u8): Likewise.
7737 (vqshlq_m_u32): Likewise.
7738 (vqshlq_m_u16): Likewise.
7739 (vqsubq_m_n_s8): Likewise.
7740 (vqsubq_m_n_s32): Likewise.
7741 (vqsubq_m_n_s16): Likewise.
7742 (vqsubq_m_n_u8): Likewise.
7743 (vqsubq_m_n_u32): Likewise.
7744 (vqsubq_m_n_u16): Likewise.
7745 (vqsubq_m_s8): Likewise.
7746 (vqsubq_m_s32): Likewise.
7747 (vqsubq_m_s16): Likewise.
7748 (vqsubq_m_u8): Likewise.
7749 (vqsubq_m_u32): Likewise.
7750 (vqsubq_m_u16): Likewise.
7751 (vrhaddq_m_s8): Likewise.
7752 (vrhaddq_m_s32): Likewise.
7753 (vrhaddq_m_s16): Likewise.
7754 (vrhaddq_m_u8): Likewise.
7755 (vrhaddq_m_u32): Likewise.
7756 (vrhaddq_m_u16): Likewise.
7757 (vrmulhq_m_s8): Likewise.
7758 (vrmulhq_m_s32): Likewise.
7759 (vrmulhq_m_s16): Likewise.
7760 (vrmulhq_m_u8): Likewise.
7761 (vrmulhq_m_u32): Likewise.
7762 (vrmulhq_m_u16): Likewise.
7763 (vrshlq_m_s8): Likewise.
7764 (vrshlq_m_s32): Likewise.
7765 (vrshlq_m_s16): Likewise.
7766 (vrshlq_m_u8): Likewise.
7767 (vrshlq_m_u32): Likewise.
7768 (vrshlq_m_u16): Likewise.
7769 (vrshrq_m_n_s8): Likewise.
7770 (vrshrq_m_n_s32): Likewise.
7771 (vrshrq_m_n_s16): Likewise.
7772 (vrshrq_m_n_u8): Likewise.
7773 (vrshrq_m_n_u32): Likewise.
7774 (vrshrq_m_n_u16): Likewise.
7775 (vshlq_m_n_s8): Likewise.
7776 (vshlq_m_n_s32): Likewise.
7777 (vshlq_m_n_s16): Likewise.
7778 (vshlq_m_n_u8): Likewise.
7779 (vshlq_m_n_u32): Likewise.
7780 (vshlq_m_n_u16): Likewise.
7781 (vshrq_m_n_s8): Likewise.
7782 (vshrq_m_n_s32): Likewise.
7783 (vshrq_m_n_s16): Likewise.
7784 (vshrq_m_n_u8): Likewise.
7785 (vshrq_m_n_u32): Likewise.
7786 (vshrq_m_n_u16): Likewise.
7787 (vsliq_m_n_s8): Likewise.
7788 (vsliq_m_n_s32): Likewise.
7789 (vsliq_m_n_s16): Likewise.
7790 (vsliq_m_n_u8): Likewise.
7791 (vsliq_m_n_u32): Likewise.
7792 (vsliq_m_n_u16): Likewise.
7793 (vsubq_m_n_s8): Likewise.
7794 (vsubq_m_n_s32): Likewise.
7795 (vsubq_m_n_s16): Likewise.
7796 (vsubq_m_n_u8): Likewise.
7797 (vsubq_m_n_u32): Likewise.
7798 (vsubq_m_n_u16): Likewise.
7799 (__arm_vabdq_m_s8): Define intrinsic.
7800 (__arm_vabdq_m_s32): Likewise.
7801 (__arm_vabdq_m_s16): Likewise.
7802 (__arm_vabdq_m_u8): Likewise.
7803 (__arm_vabdq_m_u32): Likewise.
7804 (__arm_vabdq_m_u16): Likewise.
7805 (__arm_vaddq_m_n_s8): Likewise.
7806 (__arm_vaddq_m_n_s32): Likewise.
7807 (__arm_vaddq_m_n_s16): Likewise.
7808 (__arm_vaddq_m_n_u8): Likewise.
7809 (__arm_vaddq_m_n_u32): Likewise.
7810 (__arm_vaddq_m_n_u16): Likewise.
7811 (__arm_vaddq_m_s8): Likewise.
7812 (__arm_vaddq_m_s32): Likewise.
7813 (__arm_vaddq_m_s16): Likewise.
7814 (__arm_vaddq_m_u8): Likewise.
7815 (__arm_vaddq_m_u32): Likewise.
7816 (__arm_vaddq_m_u16): Likewise.
7817 (__arm_vandq_m_s8): Likewise.
7818 (__arm_vandq_m_s32): Likewise.
7819 (__arm_vandq_m_s16): Likewise.
7820 (__arm_vandq_m_u8): Likewise.
7821 (__arm_vandq_m_u32): Likewise.
7822 (__arm_vandq_m_u16): Likewise.
7823 (__arm_vbicq_m_s8): Likewise.
7824 (__arm_vbicq_m_s32): Likewise.
7825 (__arm_vbicq_m_s16): Likewise.
7826 (__arm_vbicq_m_u8): Likewise.
7827 (__arm_vbicq_m_u32): Likewise.
7828 (__arm_vbicq_m_u16): Likewise.
7829 (__arm_vbrsrq_m_n_s8): Likewise.
7830 (__arm_vbrsrq_m_n_s32): Likewise.
7831 (__arm_vbrsrq_m_n_s16): Likewise.
7832 (__arm_vbrsrq_m_n_u8): Likewise.
7833 (__arm_vbrsrq_m_n_u32): Likewise.
7834 (__arm_vbrsrq_m_n_u16): Likewise.
7835 (__arm_vcaddq_rot270_m_s8): Likewise.
7836 (__arm_vcaddq_rot270_m_s32): Likewise.
7837 (__arm_vcaddq_rot270_m_s16): Likewise.
7838 (__arm_vcaddq_rot270_m_u8): Likewise.
7839 (__arm_vcaddq_rot270_m_u32): Likewise.
7840 (__arm_vcaddq_rot270_m_u16): Likewise.
7841 (__arm_vcaddq_rot90_m_s8): Likewise.
7842 (__arm_vcaddq_rot90_m_s32): Likewise.
7843 (__arm_vcaddq_rot90_m_s16): Likewise.
7844 (__arm_vcaddq_rot90_m_u8): Likewise.
7845 (__arm_vcaddq_rot90_m_u32): Likewise.
7846 (__arm_vcaddq_rot90_m_u16): Likewise.
7847 (__arm_veorq_m_s8): Likewise.
7848 (__arm_veorq_m_s32): Likewise.
7849 (__arm_veorq_m_s16): Likewise.
7850 (__arm_veorq_m_u8): Likewise.
7851 (__arm_veorq_m_u32): Likewise.
7852 (__arm_veorq_m_u16): Likewise.
7853 (__arm_vhaddq_m_n_s8): Likewise.
7854 (__arm_vhaddq_m_n_s32): Likewise.
7855 (__arm_vhaddq_m_n_s16): Likewise.
7856 (__arm_vhaddq_m_n_u8): Likewise.
7857 (__arm_vhaddq_m_n_u32): Likewise.
7858 (__arm_vhaddq_m_n_u16): Likewise.
7859 (__arm_vhaddq_m_s8): Likewise.
7860 (__arm_vhaddq_m_s32): Likewise.
7861 (__arm_vhaddq_m_s16): Likewise.
7862 (__arm_vhaddq_m_u8): Likewise.
7863 (__arm_vhaddq_m_u32): Likewise.
7864 (__arm_vhaddq_m_u16): Likewise.
7865 (__arm_vhcaddq_rot270_m_s8): Likewise.
7866 (__arm_vhcaddq_rot270_m_s32): Likewise.
7867 (__arm_vhcaddq_rot270_m_s16): Likewise.
7868 (__arm_vhcaddq_rot90_m_s8): Likewise.
7869 (__arm_vhcaddq_rot90_m_s32): Likewise.
7870 (__arm_vhcaddq_rot90_m_s16): Likewise.
7871 (__arm_vhsubq_m_n_s8): Likewise.
7872 (__arm_vhsubq_m_n_s32): Likewise.
7873 (__arm_vhsubq_m_n_s16): Likewise.
7874 (__arm_vhsubq_m_n_u8): Likewise.
7875 (__arm_vhsubq_m_n_u32): Likewise.
7876 (__arm_vhsubq_m_n_u16): Likewise.
7877 (__arm_vhsubq_m_s8): Likewise.
7878 (__arm_vhsubq_m_s32): Likewise.
7879 (__arm_vhsubq_m_s16): Likewise.
7880 (__arm_vhsubq_m_u8): Likewise.
7881 (__arm_vhsubq_m_u32): Likewise.
7882 (__arm_vhsubq_m_u16): Likewise.
7883 (__arm_vmaxq_m_s8): Likewise.
7884 (__arm_vmaxq_m_s32): Likewise.
7885 (__arm_vmaxq_m_s16): Likewise.
7886 (__arm_vmaxq_m_u8): Likewise.
7887 (__arm_vmaxq_m_u32): Likewise.
7888 (__arm_vmaxq_m_u16): Likewise.
7889 (__arm_vminq_m_s8): Likewise.
7890 (__arm_vminq_m_s32): Likewise.
7891 (__arm_vminq_m_s16): Likewise.
7892 (__arm_vminq_m_u8): Likewise.
7893 (__arm_vminq_m_u32): Likewise.
7894 (__arm_vminq_m_u16): Likewise.
7895 (__arm_vmladavaq_p_s8): Likewise.
7896 (__arm_vmladavaq_p_s32): Likewise.
7897 (__arm_vmladavaq_p_s16): Likewise.
7898 (__arm_vmladavaq_p_u8): Likewise.
7899 (__arm_vmladavaq_p_u32): Likewise.
7900 (__arm_vmladavaq_p_u16): Likewise.
7901 (__arm_vmladavaxq_p_s8): Likewise.
7902 (__arm_vmladavaxq_p_s32): Likewise.
7903 (__arm_vmladavaxq_p_s16): Likewise.
7904 (__arm_vmlaq_m_n_s8): Likewise.
7905 (__arm_vmlaq_m_n_s32): Likewise.
7906 (__arm_vmlaq_m_n_s16): Likewise.
7907 (__arm_vmlaq_m_n_u8): Likewise.
7908 (__arm_vmlaq_m_n_u32): Likewise.
7909 (__arm_vmlaq_m_n_u16): Likewise.
7910 (__arm_vmlasq_m_n_s8): Likewise.
7911 (__arm_vmlasq_m_n_s32): Likewise.
7912 (__arm_vmlasq_m_n_s16): Likewise.
7913 (__arm_vmlasq_m_n_u8): Likewise.
7914 (__arm_vmlasq_m_n_u32): Likewise.
7915 (__arm_vmlasq_m_n_u16): Likewise.
7916 (__arm_vmlsdavaq_p_s8): Likewise.
7917 (__arm_vmlsdavaq_p_s32): Likewise.
7918 (__arm_vmlsdavaq_p_s16): Likewise.
7919 (__arm_vmlsdavaxq_p_s8): Likewise.
7920 (__arm_vmlsdavaxq_p_s32): Likewise.
7921 (__arm_vmlsdavaxq_p_s16): Likewise.
7922 (__arm_vmulhq_m_s8): Likewise.
7923 (__arm_vmulhq_m_s32): Likewise.
7924 (__arm_vmulhq_m_s16): Likewise.
7925 (__arm_vmulhq_m_u8): Likewise.
7926 (__arm_vmulhq_m_u32): Likewise.
7927 (__arm_vmulhq_m_u16): Likewise.
7928 (__arm_vmullbq_int_m_s8): Likewise.
7929 (__arm_vmullbq_int_m_s32): Likewise.
7930 (__arm_vmullbq_int_m_s16): Likewise.
7931 (__arm_vmullbq_int_m_u8): Likewise.
7932 (__arm_vmullbq_int_m_u32): Likewise.
7933 (__arm_vmullbq_int_m_u16): Likewise.
7934 (__arm_vmulltq_int_m_s8): Likewise.
7935 (__arm_vmulltq_int_m_s32): Likewise.
7936 (__arm_vmulltq_int_m_s16): Likewise.
7937 (__arm_vmulltq_int_m_u8): Likewise.
7938 (__arm_vmulltq_int_m_u32): Likewise.
7939 (__arm_vmulltq_int_m_u16): Likewise.
7940 (__arm_vmulq_m_n_s8): Likewise.
7941 (__arm_vmulq_m_n_s32): Likewise.
7942 (__arm_vmulq_m_n_s16): Likewise.
7943 (__arm_vmulq_m_n_u8): Likewise.
7944 (__arm_vmulq_m_n_u32): Likewise.
7945 (__arm_vmulq_m_n_u16): Likewise.
7946 (__arm_vmulq_m_s8): Likewise.
7947 (__arm_vmulq_m_s32): Likewise.
7948 (__arm_vmulq_m_s16): Likewise.
7949 (__arm_vmulq_m_u8): Likewise.
7950 (__arm_vmulq_m_u32): Likewise.
7951 (__arm_vmulq_m_u16): Likewise.
7952 (__arm_vornq_m_s8): Likewise.
7953 (__arm_vornq_m_s32): Likewise.
7954 (__arm_vornq_m_s16): Likewise.
7955 (__arm_vornq_m_u8): Likewise.
7956 (__arm_vornq_m_u32): Likewise.
7957 (__arm_vornq_m_u16): Likewise.
7958 (__arm_vorrq_m_s8): Likewise.
7959 (__arm_vorrq_m_s32): Likewise.
7960 (__arm_vorrq_m_s16): Likewise.
7961 (__arm_vorrq_m_u8): Likewise.
7962 (__arm_vorrq_m_u32): Likewise.
7963 (__arm_vorrq_m_u16): Likewise.
7964 (__arm_vqaddq_m_n_s8): Likewise.
7965 (__arm_vqaddq_m_n_s32): Likewise.
7966 (__arm_vqaddq_m_n_s16): Likewise.
7967 (__arm_vqaddq_m_n_u8): Likewise.
7968 (__arm_vqaddq_m_n_u32): Likewise.
7969 (__arm_vqaddq_m_n_u16): Likewise.
7970 (__arm_vqaddq_m_s8): Likewise.
7971 (__arm_vqaddq_m_s32): Likewise.
7972 (__arm_vqaddq_m_s16): Likewise.
7973 (__arm_vqaddq_m_u8): Likewise.
7974 (__arm_vqaddq_m_u32): Likewise.
7975 (__arm_vqaddq_m_u16): Likewise.
7976 (__arm_vqdmladhq_m_s8): Likewise.
7977 (__arm_vqdmladhq_m_s32): Likewise.
7978 (__arm_vqdmladhq_m_s16): Likewise.
7979 (__arm_vqdmladhxq_m_s8): Likewise.
7980 (__arm_vqdmladhxq_m_s32): Likewise.
7981 (__arm_vqdmladhxq_m_s16): Likewise.
7982 (__arm_vqdmlahq_m_n_s8): Likewise.
7983 (__arm_vqdmlahq_m_n_s32): Likewise.
7984 (__arm_vqdmlahq_m_n_s16): Likewise.
7985 (__arm_vqdmlahq_m_n_u8): Likewise.
7986 (__arm_vqdmlahq_m_n_u32): Likewise.
7987 (__arm_vqdmlahq_m_n_u16): Likewise.
7988 (__arm_vqdmlsdhq_m_s8): Likewise.
7989 (__arm_vqdmlsdhq_m_s32): Likewise.
7990 (__arm_vqdmlsdhq_m_s16): Likewise.
7991 (__arm_vqdmlsdhxq_m_s8): Likewise.
7992 (__arm_vqdmlsdhxq_m_s32): Likewise.
7993 (__arm_vqdmlsdhxq_m_s16): Likewise.
7994 (__arm_vqdmulhq_m_n_s8): Likewise.
7995 (__arm_vqdmulhq_m_n_s32): Likewise.
7996 (__arm_vqdmulhq_m_n_s16): Likewise.
7997 (__arm_vqdmulhq_m_s8): Likewise.
7998 (__arm_vqdmulhq_m_s32): Likewise.
7999 (__arm_vqdmulhq_m_s16): Likewise.
8000 (__arm_vqrdmladhq_m_s8): Likewise.
8001 (__arm_vqrdmladhq_m_s32): Likewise.
8002 (__arm_vqrdmladhq_m_s16): Likewise.
8003 (__arm_vqrdmladhxq_m_s8): Likewise.
8004 (__arm_vqrdmladhxq_m_s32): Likewise.
8005 (__arm_vqrdmladhxq_m_s16): Likewise.
8006 (__arm_vqrdmlahq_m_n_s8): Likewise.
8007 (__arm_vqrdmlahq_m_n_s32): Likewise.
8008 (__arm_vqrdmlahq_m_n_s16): Likewise.
8009 (__arm_vqrdmlahq_m_n_u8): Likewise.
8010 (__arm_vqrdmlahq_m_n_u32): Likewise.
8011 (__arm_vqrdmlahq_m_n_u16): Likewise.
8012 (__arm_vqrdmlashq_m_n_s8): Likewise.
8013 (__arm_vqrdmlashq_m_n_s32): Likewise.
8014 (__arm_vqrdmlashq_m_n_s16): Likewise.
8015 (__arm_vqrdmlashq_m_n_u8): Likewise.
8016 (__arm_vqrdmlashq_m_n_u32): Likewise.
8017 (__arm_vqrdmlashq_m_n_u16): Likewise.
8018 (__arm_vqrdmlsdhq_m_s8): Likewise.
8019 (__arm_vqrdmlsdhq_m_s32): Likewise.
8020 (__arm_vqrdmlsdhq_m_s16): Likewise.
8021 (__arm_vqrdmlsdhxq_m_s8): Likewise.
8022 (__arm_vqrdmlsdhxq_m_s32): Likewise.
8023 (__arm_vqrdmlsdhxq_m_s16): Likewise.
8024 (__arm_vqrdmulhq_m_n_s8): Likewise.
8025 (__arm_vqrdmulhq_m_n_s32): Likewise.
8026 (__arm_vqrdmulhq_m_n_s16): Likewise.
8027 (__arm_vqrdmulhq_m_s8): Likewise.
8028 (__arm_vqrdmulhq_m_s32): Likewise.
8029 (__arm_vqrdmulhq_m_s16): Likewise.
8030 (__arm_vqrshlq_m_s8): Likewise.
8031 (__arm_vqrshlq_m_s32): Likewise.
8032 (__arm_vqrshlq_m_s16): Likewise.
8033 (__arm_vqrshlq_m_u8): Likewise.
8034 (__arm_vqrshlq_m_u32): Likewise.
8035 (__arm_vqrshlq_m_u16): Likewise.
8036 (__arm_vqshlq_m_n_s8): Likewise.
8037 (__arm_vqshlq_m_n_s32): Likewise.
8038 (__arm_vqshlq_m_n_s16): Likewise.
8039 (__arm_vqshlq_m_n_u8): Likewise.
8040 (__arm_vqshlq_m_n_u32): Likewise.
8041 (__arm_vqshlq_m_n_u16): Likewise.
8042 (__arm_vqshlq_m_s8): Likewise.
8043 (__arm_vqshlq_m_s32): Likewise.
8044 (__arm_vqshlq_m_s16): Likewise.
8045 (__arm_vqshlq_m_u8): Likewise.
8046 (__arm_vqshlq_m_u32): Likewise.
8047 (__arm_vqshlq_m_u16): Likewise.
8048 (__arm_vqsubq_m_n_s8): Likewise.
8049 (__arm_vqsubq_m_n_s32): Likewise.
8050 (__arm_vqsubq_m_n_s16): Likewise.
8051 (__arm_vqsubq_m_n_u8): Likewise.
8052 (__arm_vqsubq_m_n_u32): Likewise.
8053 (__arm_vqsubq_m_n_u16): Likewise.
8054 (__arm_vqsubq_m_s8): Likewise.
8055 (__arm_vqsubq_m_s32): Likewise.
8056 (__arm_vqsubq_m_s16): Likewise.
8057 (__arm_vqsubq_m_u8): Likewise.
8058 (__arm_vqsubq_m_u32): Likewise.
8059 (__arm_vqsubq_m_u16): Likewise.
8060 (__arm_vrhaddq_m_s8): Likewise.
8061 (__arm_vrhaddq_m_s32): Likewise.
8062 (__arm_vrhaddq_m_s16): Likewise.
8063 (__arm_vrhaddq_m_u8): Likewise.
8064 (__arm_vrhaddq_m_u32): Likewise.
8065 (__arm_vrhaddq_m_u16): Likewise.
8066 (__arm_vrmulhq_m_s8): Likewise.
8067 (__arm_vrmulhq_m_s32): Likewise.
8068 (__arm_vrmulhq_m_s16): Likewise.
8069 (__arm_vrmulhq_m_u8): Likewise.
8070 (__arm_vrmulhq_m_u32): Likewise.
8071 (__arm_vrmulhq_m_u16): Likewise.
8072 (__arm_vrshlq_m_s8): Likewise.
8073 (__arm_vrshlq_m_s32): Likewise.
8074 (__arm_vrshlq_m_s16): Likewise.
8075 (__arm_vrshlq_m_u8): Likewise.
8076 (__arm_vrshlq_m_u32): Likewise.
8077 (__arm_vrshlq_m_u16): Likewise.
8078 (__arm_vrshrq_m_n_s8): Likewise.
8079 (__arm_vrshrq_m_n_s32): Likewise.
8080 (__arm_vrshrq_m_n_s16): Likewise.
8081 (__arm_vrshrq_m_n_u8): Likewise.
8082 (__arm_vrshrq_m_n_u32): Likewise.
8083 (__arm_vrshrq_m_n_u16): Likewise.
8084 (__arm_vshlq_m_n_s8): Likewise.
8085 (__arm_vshlq_m_n_s32): Likewise.
8086 (__arm_vshlq_m_n_s16): Likewise.
8087 (__arm_vshlq_m_n_u8): Likewise.
8088 (__arm_vshlq_m_n_u32): Likewise.
8089 (__arm_vshlq_m_n_u16): Likewise.
8090 (__arm_vshrq_m_n_s8): Likewise.
8091 (__arm_vshrq_m_n_s32): Likewise.
8092 (__arm_vshrq_m_n_s16): Likewise.
8093 (__arm_vshrq_m_n_u8): Likewise.
8094 (__arm_vshrq_m_n_u32): Likewise.
8095 (__arm_vshrq_m_n_u16): Likewise.
8096 (__arm_vsliq_m_n_s8): Likewise.
8097 (__arm_vsliq_m_n_s32): Likewise.
8098 (__arm_vsliq_m_n_s16): Likewise.
8099 (__arm_vsliq_m_n_u8): Likewise.
8100 (__arm_vsliq_m_n_u32): Likewise.
8101 (__arm_vsliq_m_n_u16): Likewise.
8102 (__arm_vsubq_m_n_s8): Likewise.
8103 (__arm_vsubq_m_n_s32): Likewise.
8104 (__arm_vsubq_m_n_s16): Likewise.
8105 (__arm_vsubq_m_n_u8): Likewise.
8106 (__arm_vsubq_m_n_u32): Likewise.
8107 (__arm_vsubq_m_n_u16): Likewise.
8108 (vqdmladhq_m): Define polymorphic variant.
8109 (vqdmladhxq_m): Likewise.
8110 (vqdmlsdhq_m): Likewise.
8111 (vqdmlsdhxq_m): Likewise.
8112 (vabdq_m): Likewise.
8113 (vandq_m): Likewise.
8114 (vbicq_m): Likewise.
8115 (vbrsrq_m_n): Likewise.
8116 (vcaddq_rot270_m): Likewise.
8117 (vcaddq_rot90_m): Likewise.
8118 (veorq_m): Likewise.
8119 (vmaxq_m): Likewise.
8120 (vminq_m): Likewise.
8121 (vmladavaq_p): Likewise.
8122 (vmlaq_m_n): Likewise.
8123 (vmlasq_m_n): Likewise.
8124 (vmulhq_m): Likewise.
8125 (vmullbq_int_m): Likewise.
8126 (vmulltq_int_m): Likewise.
8127 (vornq_m): Likewise.
8128 (vorrq_m): Likewise.
8129 (vqdmlahq_m_n): Likewise.
8130 (vqrdmlahq_m_n): Likewise.
8131 (vqrdmlashq_m_n): Likewise.
8132 (vqrshlq_m): Likewise.
8133 (vqshlq_m_n): Likewise.
8134 (vqshlq_m): Likewise.
8135 (vrhaddq_m): Likewise.
8136 (vrmulhq_m): Likewise.
8137 (vrshlq_m): Likewise.
8138 (vrshrq_m_n): Likewise.
8139 (vshlq_m_n): Likewise.
8140 (vshrq_m_n): Likewise.
8141 (vsliq_m): Likewise.
8142 (vaddq_m_n): Likewise.
8143 (vaddq_m): Likewise.
8144 (vhaddq_m_n): Likewise.
8145 (vhaddq_m): Likewise.
8146 (vhcaddq_rot270_m): Likewise.
8147 (vhcaddq_rot90_m): Likewise.
8148 (vhsubq_m): Likewise.
8149 (vhsubq_m_n): Likewise.
8150 (vmulq_m_n): Likewise.
8151 (vmulq_m): Likewise.
8152 (vqaddq_m_n): Likewise.
8153 (vqaddq_m): Likewise.
8154 (vqdmulhq_m_n): Likewise.
8155 (vqdmulhq_m): Likewise.
8156 (vsubq_m_n): Likewise.
8157 (vsliq_m_n): Likewise.
8158 (vqsubq_m_n): Likewise.
8159 (vqsubq_m): Likewise.
8160 (vqrdmulhq_m): Likewise.
8161 (vqrdmulhq_m_n): Likewise.
8162 (vqrdmlsdhxq_m): Likewise.
8163 (vqrdmlsdhq_m): Likewise.
8164 (vqrdmladhq_m): Likewise.
8165 (vqrdmladhxq_m): Likewise.
8166 (vmlsdavaxq_p): Likewise.
8167 (vmlsdavaq_p): Likewise.
8168 (vmladavaxq_p): Likewise.
8169 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
8171 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
8172 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
8173 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
8174 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
8175 * config/arm/mve.md (VHSUBQ_M): Define iterators.
8176 (VSLIQ_M_N): Likewise.
8177 (VQRDMLAHQ_M_N): Likewise.
8178 (VRSHLQ_M): Likewise.
8179 (VMINQ_M): Likewise.
8180 (VMULLBQ_INT_M): Likewise.
8181 (VMULHQ_M): Likewise.
8182 (VMULQ_M): Likewise.
8183 (VHSUBQ_M_N): Likewise.
8184 (VHADDQ_M_N): Likewise.
8185 (VORRQ_M): Likewise.
8186 (VRMULHQ_M): Likewise.
8187 (VQADDQ_M): Likewise.
8188 (VRSHRQ_M_N): Likewise.
8189 (VQSUBQ_M_N): Likewise.
8190 (VADDQ_M): Likewise.
8191 (VORNQ_M): Likewise.
8192 (VQDMLAHQ_M_N): Likewise.
8193 (VRHADDQ_M): Likewise.
8194 (VQSHLQ_M): Likewise.
8195 (VANDQ_M): Likewise.
8196 (VBICQ_M): Likewise.
8197 (VSHLQ_M_N): Likewise.
8198 (VCADDQ_ROT270_M): Likewise.
8199 (VQRSHLQ_M): Likewise.
8200 (VQADDQ_M_N): Likewise.
8201 (VADDQ_M_N): Likewise.
8202 (VMAXQ_M): Likewise.
8203 (VQSUBQ_M): Likewise.
8204 (VMLASQ_M_N): Likewise.
8205 (VMLADAVAQ_P): Likewise.
8206 (VBRSRQ_M_N): Likewise.
8207 (VMULQ_M_N): Likewise.
8208 (VCADDQ_ROT90_M): Likewise.
8209 (VMULLTQ_INT_M): Likewise.
8210 (VEORQ_M): Likewise.
8211 (VSHRQ_M_N): Likewise.
8212 (VSUBQ_M_N): Likewise.
8213 (VHADDQ_M): Likewise.
8214 (VABDQ_M): Likewise.
8215 (VQRDMLASHQ_M_N): Likewise.
8216 (VMLAQ_M_N): Likewise.
8217 (VQSHLQ_M_N): Likewise.
8218 (mve_vabdq_m_<supf><mode>): Define RTL pattern.
8219 (mve_vaddq_m_n_<supf><mode>): Likewise.
8220 (mve_vaddq_m_<supf><mode>): Likewise.
8221 (mve_vandq_m_<supf><mode>): Likewise.
8222 (mve_vbicq_m_<supf><mode>): Likewise.
8223 (mve_vbrsrq_m_n_<supf><mode>): Likewise.
8224 (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
8225 (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
8226 (mve_veorq_m_<supf><mode>): Likewise.
8227 (mve_vhaddq_m_n_<supf><mode>): Likewise.
8228 (mve_vhaddq_m_<supf><mode>): Likewise.
8229 (mve_vhsubq_m_n_<supf><mode>): Likewise.
8230 (mve_vhsubq_m_<supf><mode>): Likewise.
8231 (mve_vmaxq_m_<supf><mode>): Likewise.
8232 (mve_vminq_m_<supf><mode>): Likewise.
8233 (mve_vmladavaq_p_<supf><mode>): Likewise.
8234 (mve_vmlaq_m_n_<supf><mode>): Likewise.
8235 (mve_vmlasq_m_n_<supf><mode>): Likewise.
8236 (mve_vmulhq_m_<supf><mode>): Likewise.
8237 (mve_vmullbq_int_m_<supf><mode>): Likewise.
8238 (mve_vmulltq_int_m_<supf><mode>): Likewise.
8239 (mve_vmulq_m_n_<supf><mode>): Likewise.
8240 (mve_vmulq_m_<supf><mode>): Likewise.
8241 (mve_vornq_m_<supf><mode>): Likewise.
8242 (mve_vorrq_m_<supf><mode>): Likewise.
8243 (mve_vqaddq_m_n_<supf><mode>): Likewise.
8244 (mve_vqaddq_m_<supf><mode>): Likewise.
8245 (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
8246 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
8247 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
8248 (mve_vqrshlq_m_<supf><mode>): Likewise.
8249 (mve_vqshlq_m_n_<supf><mode>): Likewise.
8250 (mve_vqshlq_m_<supf><mode>): Likewise.
8251 (mve_vqsubq_m_n_<supf><mode>): Likewise.
8252 (mve_vqsubq_m_<supf><mode>): Likewise.
8253 (mve_vrhaddq_m_<supf><mode>): Likewise.
8254 (mve_vrmulhq_m_<supf><mode>): Likewise.
8255 (mve_vrshlq_m_<supf><mode>): Likewise.
8256 (mve_vrshrq_m_n_<supf><mode>): Likewise.
8257 (mve_vshlq_m_n_<supf><mode>): Likewise.
8258 (mve_vshrq_m_n_<supf><mode>): Likewise.
8259 (mve_vsliq_m_n_<supf><mode>): Likewise.
8260 (mve_vsubq_m_n_<supf><mode>): Likewise.
8261 (mve_vhcaddq_rot270_m_s<mode>): Likewise.
8262 (mve_vhcaddq_rot90_m_s<mode>): Likewise.
8263 (mve_vmladavaxq_p_s<mode>): Likewise.
8264 (mve_vmlsdavaq_p_s<mode>): Likewise.
8265 (mve_vmlsdavaxq_p_s<mode>): Likewise.
8266 (mve_vqdmladhq_m_s<mode>): Likewise.
8267 (mve_vqdmladhxq_m_s<mode>): Likewise.
8268 (mve_vqdmlsdhq_m_s<mode>): Likewise.
8269 (mve_vqdmlsdhxq_m_s<mode>): Likewise.
8270 (mve_vqdmulhq_m_n_s<mode>): Likewise.
8271 (mve_vqdmulhq_m_s<mode>): Likewise.
8272 (mve_vqrdmladhq_m_s<mode>): Likewise.
8273 (mve_vqrdmladhxq_m_s<mode>): Likewise.
8274 (mve_vqrdmlsdhq_m_s<mode>): Likewise.
8275 (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
8276 (mve_vqrdmulhq_m_n_s<mode>): Likewise.
8277 (mve_vqrdmulhq_m_s<mode>): Likewise.
8279 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8280 Mihail Ionescu <mihail.ionescu@arm.com>
8281 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8283 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
8284 Define builtin qualifier.
8285 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8286 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8287 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8288 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8289 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8290 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8291 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8292 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
8293 (vsubq_m_s8): Likewise.
8294 (vcvtq_m_n_f16_u16): Likewise.
8295 (vqshluq_m_n_s8): Likewise.
8296 (vabavq_p_s8): Likewise.
8297 (vsriq_m_n_u8): Likewise.
8298 (vshlq_m_u8): Likewise.
8299 (vsubq_m_u8): Likewise.
8300 (vabavq_p_u8): Likewise.
8301 (vshlq_m_s8): Likewise.
8302 (vcvtq_m_n_f16_s16): Likewise.
8303 (vsriq_m_n_s16): Likewise.
8304 (vsubq_m_s16): Likewise.
8305 (vcvtq_m_n_f32_u32): Likewise.
8306 (vqshluq_m_n_s16): Likewise.
8307 (vabavq_p_s16): Likewise.
8308 (vsriq_m_n_u16): Likewise.
8309 (vshlq_m_u16): Likewise.
8310 (vsubq_m_u16): Likewise.
8311 (vabavq_p_u16): Likewise.
8312 (vshlq_m_s16): Likewise.
8313 (vcvtq_m_n_f32_s32): Likewise.
8314 (vsriq_m_n_s32): Likewise.
8315 (vsubq_m_s32): Likewise.
8316 (vqshluq_m_n_s32): Likewise.
8317 (vabavq_p_s32): Likewise.
8318 (vsriq_m_n_u32): Likewise.
8319 (vshlq_m_u32): Likewise.
8320 (vsubq_m_u32): Likewise.
8321 (vabavq_p_u32): Likewise.
8322 (vshlq_m_s32): Likewise.
8323 (__arm_vsriq_m_n_s8): Define intrinsic.
8324 (__arm_vsubq_m_s8): Likewise.
8325 (__arm_vqshluq_m_n_s8): Likewise.
8326 (__arm_vabavq_p_s8): Likewise.
8327 (__arm_vsriq_m_n_u8): Likewise.
8328 (__arm_vshlq_m_u8): Likewise.
8329 (__arm_vsubq_m_u8): Likewise.
8330 (__arm_vabavq_p_u8): Likewise.
8331 (__arm_vshlq_m_s8): Likewise.
8332 (__arm_vsriq_m_n_s16): Likewise.
8333 (__arm_vsubq_m_s16): Likewise.
8334 (__arm_vqshluq_m_n_s16): Likewise.
8335 (__arm_vabavq_p_s16): Likewise.
8336 (__arm_vsriq_m_n_u16): Likewise.
8337 (__arm_vshlq_m_u16): Likewise.
8338 (__arm_vsubq_m_u16): Likewise.
8339 (__arm_vabavq_p_u16): Likewise.
8340 (__arm_vshlq_m_s16): Likewise.
8341 (__arm_vsriq_m_n_s32): Likewise.
8342 (__arm_vsubq_m_s32): Likewise.
8343 (__arm_vqshluq_m_n_s32): Likewise.
8344 (__arm_vabavq_p_s32): Likewise.
8345 (__arm_vsriq_m_n_u32): Likewise.
8346 (__arm_vshlq_m_u32): Likewise.
8347 (__arm_vsubq_m_u32): Likewise.
8348 (__arm_vabavq_p_u32): Likewise.
8349 (__arm_vshlq_m_s32): Likewise.
8350 (__arm_vcvtq_m_n_f16_u16): Likewise.
8351 (__arm_vcvtq_m_n_f16_s16): Likewise.
8352 (__arm_vcvtq_m_n_f32_u32): Likewise.
8353 (__arm_vcvtq_m_n_f32_s32): Likewise.
8354 (vcvtq_m_n): Define polymorphic variant.
8355 (vqshluq_m_n): Likewise.
8356 (vshlq_m): Likewise.
8357 (vsriq_m_n): Likewise.
8358 (vsubq_m): Likewise.
8359 (vabavq_p): Likewise.
8360 * config/arm/arm_mve_builtins.def
8361 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
8362 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8363 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8364 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8365 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8366 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8367 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8368 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8369 * config/arm/mve.md (VABAVQ_P): Define iterator.
8370 (VSHLQ_M): Likewise.
8371 (VSRIQ_M_N): Likewise.
8372 (VSUBQ_M): Likewise.
8373 (VCVTQ_M_N_TO_F): Likewise.
8374 (mve_vabavq_p_<supf><mode>): Define RTL pattern.
8375 (mve_vqshluq_m_n_s<mode>): Likewise.
8376 (mve_vshlq_m_<supf><mode>): Likewise.
8377 (mve_vsriq_m_n_<supf><mode>): Likewise.
8378 (mve_vsubq_m_<supf><mode>): Likewise.
8379 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
8381 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8382 Mihail Ionescu <mihail.ionescu@arm.com>
8383 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8385 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
8386 (vrmlsldavhaq_s32): Likewise.
8387 (vrmlsldavhaxq_s32): Likewise.
8388 (vaddlvaq_p_s32): Likewise.
8389 (vcvtbq_m_f16_f32): Likewise.
8390 (vcvtbq_m_f32_f16): Likewise.
8391 (vcvttq_m_f16_f32): Likewise.
8392 (vcvttq_m_f32_f16): Likewise.
8393 (vrev16q_m_s8): Likewise.
8394 (vrev32q_m_f16): Likewise.
8395 (vrmlaldavhq_p_s32): Likewise.
8396 (vrmlaldavhxq_p_s32): Likewise.
8397 (vrmlsldavhq_p_s32): Likewise.
8398 (vrmlsldavhxq_p_s32): Likewise.
8399 (vaddlvaq_p_u32): Likewise.
8400 (vrev16q_m_u8): Likewise.
8401 (vrmlaldavhq_p_u32): Likewise.
8402 (vmvnq_m_n_s16): Likewise.
8403 (vorrq_m_n_s16): Likewise.
8404 (vqrshrntq_n_s16): Likewise.
8405 (vqshrnbq_n_s16): Likewise.
8406 (vqshrntq_n_s16): Likewise.
8407 (vrshrnbq_n_s16): Likewise.
8408 (vrshrntq_n_s16): Likewise.
8409 (vshrnbq_n_s16): Likewise.
8410 (vshrntq_n_s16): Likewise.
8411 (vcmlaq_f16): Likewise.
8412 (vcmlaq_rot180_f16): Likewise.
8413 (vcmlaq_rot270_f16): Likewise.
8414 (vcmlaq_rot90_f16): Likewise.
8415 (vfmaq_f16): Likewise.
8416 (vfmaq_n_f16): Likewise.
8417 (vfmasq_n_f16): Likewise.
8418 (vfmsq_f16): Likewise.
8419 (vmlaldavaq_s16): Likewise.
8420 (vmlaldavaxq_s16): Likewise.
8421 (vmlsldavaq_s16): Likewise.
8422 (vmlsldavaxq_s16): Likewise.
8423 (vabsq_m_f16): Likewise.
8424 (vcvtmq_m_s16_f16): Likewise.
8425 (vcvtnq_m_s16_f16): Likewise.
8426 (vcvtpq_m_s16_f16): Likewise.
8427 (vcvtq_m_s16_f16): Likewise.
8428 (vdupq_m_n_f16): Likewise.
8429 (vmaxnmaq_m_f16): Likewise.
8430 (vmaxnmavq_p_f16): Likewise.
8431 (vmaxnmvq_p_f16): Likewise.
8432 (vminnmaq_m_f16): Likewise.
8433 (vminnmavq_p_f16): Likewise.
8434 (vminnmvq_p_f16): Likewise.
8435 (vmlaldavq_p_s16): Likewise.
8436 (vmlaldavxq_p_s16): Likewise.
8437 (vmlsldavq_p_s16): Likewise.
8438 (vmlsldavxq_p_s16): Likewise.
8439 (vmovlbq_m_s8): Likewise.
8440 (vmovltq_m_s8): Likewise.
8441 (vmovnbq_m_s16): Likewise.
8442 (vmovntq_m_s16): Likewise.
8443 (vnegq_m_f16): Likewise.
8444 (vpselq_f16): Likewise.
8445 (vqmovnbq_m_s16): Likewise.
8446 (vqmovntq_m_s16): Likewise.
8447 (vrev32q_m_s8): Likewise.
8448 (vrev64q_m_f16): Likewise.
8449 (vrndaq_m_f16): Likewise.
8450 (vrndmq_m_f16): Likewise.
8451 (vrndnq_m_f16): Likewise.
8452 (vrndpq_m_f16): Likewise.
8453 (vrndq_m_f16): Likewise.
8454 (vrndxq_m_f16): Likewise.
8455 (vcmpeqq_m_n_f16): Likewise.
8456 (vcmpgeq_m_f16): Likewise.
8457 (vcmpgeq_m_n_f16): Likewise.
8458 (vcmpgtq_m_f16): Likewise.
8459 (vcmpgtq_m_n_f16): Likewise.
8460 (vcmpleq_m_f16): Likewise.
8461 (vcmpleq_m_n_f16): Likewise.
8462 (vcmpltq_m_f16): Likewise.
8463 (vcmpltq_m_n_f16): Likewise.
8464 (vcmpneq_m_f16): Likewise.
8465 (vcmpneq_m_n_f16): Likewise.
8466 (vmvnq_m_n_u16): Likewise.
8467 (vorrq_m_n_u16): Likewise.
8468 (vqrshruntq_n_s16): Likewise.
8469 (vqshrunbq_n_s16): Likewise.
8470 (vqshruntq_n_s16): Likewise.
8471 (vcvtmq_m_u16_f16): Likewise.
8472 (vcvtnq_m_u16_f16): Likewise.
8473 (vcvtpq_m_u16_f16): Likewise.
8474 (vcvtq_m_u16_f16): Likewise.
8475 (vqmovunbq_m_s16): Likewise.
8476 (vqmovuntq_m_s16): Likewise.
8477 (vqrshrntq_n_u16): Likewise.
8478 (vqshrnbq_n_u16): Likewise.
8479 (vqshrntq_n_u16): Likewise.
8480 (vrshrnbq_n_u16): Likewise.
8481 (vrshrntq_n_u16): Likewise.
8482 (vshrnbq_n_u16): Likewise.
8483 (vshrntq_n_u16): Likewise.
8484 (vmlaldavaq_u16): Likewise.
8485 (vmlaldavaxq_u16): Likewise.
8486 (vmlaldavq_p_u16): Likewise.
8487 (vmlaldavxq_p_u16): Likewise.
8488 (vmovlbq_m_u8): Likewise.
8489 (vmovltq_m_u8): Likewise.
8490 (vmovnbq_m_u16): Likewise.
8491 (vmovntq_m_u16): Likewise.
8492 (vqmovnbq_m_u16): Likewise.
8493 (vqmovntq_m_u16): Likewise.
8494 (vrev32q_m_u8): Likewise.
8495 (vmvnq_m_n_s32): Likewise.
8496 (vorrq_m_n_s32): Likewise.
8497 (vqrshrntq_n_s32): Likewise.
8498 (vqshrnbq_n_s32): Likewise.
8499 (vqshrntq_n_s32): Likewise.
8500 (vrshrnbq_n_s32): Likewise.
8501 (vrshrntq_n_s32): Likewise.
8502 (vshrnbq_n_s32): Likewise.
8503 (vshrntq_n_s32): Likewise.
8504 (vcmlaq_f32): Likewise.
8505 (vcmlaq_rot180_f32): Likewise.
8506 (vcmlaq_rot270_f32): Likewise.
8507 (vcmlaq_rot90_f32): Likewise.
8508 (vfmaq_f32): Likewise.
8509 (vfmaq_n_f32): Likewise.
8510 (vfmasq_n_f32): Likewise.
8511 (vfmsq_f32): Likewise.
8512 (vmlaldavaq_s32): Likewise.
8513 (vmlaldavaxq_s32): Likewise.
8514 (vmlsldavaq_s32): Likewise.
8515 (vmlsldavaxq_s32): Likewise.
8516 (vabsq_m_f32): Likewise.
8517 (vcvtmq_m_s32_f32): Likewise.
8518 (vcvtnq_m_s32_f32): Likewise.
8519 (vcvtpq_m_s32_f32): Likewise.
8520 (vcvtq_m_s32_f32): Likewise.
8521 (vdupq_m_n_f32): Likewise.
8522 (vmaxnmaq_m_f32): Likewise.
8523 (vmaxnmavq_p_f32): Likewise.
8524 (vmaxnmvq_p_f32): Likewise.
8525 (vminnmaq_m_f32): Likewise.
8526 (vminnmavq_p_f32): Likewise.
8527 (vminnmvq_p_f32): Likewise.
8528 (vmlaldavq_p_s32): Likewise.
8529 (vmlaldavxq_p_s32): Likewise.
8530 (vmlsldavq_p_s32): Likewise.
8531 (vmlsldavxq_p_s32): Likewise.
8532 (vmovlbq_m_s16): Likewise.
8533 (vmovltq_m_s16): Likewise.
8534 (vmovnbq_m_s32): Likewise.
8535 (vmovntq_m_s32): Likewise.
8536 (vnegq_m_f32): Likewise.
8537 (vpselq_f32): Likewise.
8538 (vqmovnbq_m_s32): Likewise.
8539 (vqmovntq_m_s32): Likewise.
8540 (vrev32q_m_s16): Likewise.
8541 (vrev64q_m_f32): Likewise.
8542 (vrndaq_m_f32): Likewise.
8543 (vrndmq_m_f32): Likewise.
8544 (vrndnq_m_f32): Likewise.
8545 (vrndpq_m_f32): Likewise.
8546 (vrndq_m_f32): Likewise.
8547 (vrndxq_m_f32): Likewise.
8548 (vcmpeqq_m_n_f32): Likewise.
8549 (vcmpgeq_m_f32): Likewise.
8550 (vcmpgeq_m_n_f32): Likewise.
8551 (vcmpgtq_m_f32): Likewise.
8552 (vcmpgtq_m_n_f32): Likewise.
8553 (vcmpleq_m_f32): Likewise.
8554 (vcmpleq_m_n_f32): Likewise.
8555 (vcmpltq_m_f32): Likewise.
8556 (vcmpltq_m_n_f32): Likewise.
8557 (vcmpneq_m_f32): Likewise.
8558 (vcmpneq_m_n_f32): Likewise.
8559 (vmvnq_m_n_u32): Likewise.
8560 (vorrq_m_n_u32): Likewise.
8561 (vqrshruntq_n_s32): Likewise.
8562 (vqshrunbq_n_s32): Likewise.
8563 (vqshruntq_n_s32): Likewise.
8564 (vcvtmq_m_u32_f32): Likewise.
8565 (vcvtnq_m_u32_f32): Likewise.
8566 (vcvtpq_m_u32_f32): Likewise.
8567 (vcvtq_m_u32_f32): Likewise.
8568 (vqmovunbq_m_s32): Likewise.
8569 (vqmovuntq_m_s32): Likewise.
8570 (vqrshrntq_n_u32): Likewise.
8571 (vqshrnbq_n_u32): Likewise.
8572 (vqshrntq_n_u32): Likewise.
8573 (vrshrnbq_n_u32): Likewise.
8574 (vrshrntq_n_u32): Likewise.
8575 (vshrnbq_n_u32): Likewise.
8576 (vshrntq_n_u32): Likewise.
8577 (vmlaldavaq_u32): Likewise.
8578 (vmlaldavaxq_u32): Likewise.
8579 (vmlaldavq_p_u32): Likewise.
8580 (vmlaldavxq_p_u32): Likewise.
8581 (vmovlbq_m_u16): Likewise.
8582 (vmovltq_m_u16): Likewise.
8583 (vmovnbq_m_u32): Likewise.
8584 (vmovntq_m_u32): Likewise.
8585 (vqmovnbq_m_u32): Likewise.
8586 (vqmovntq_m_u32): Likewise.
8587 (vrev32q_m_u16): Likewise.
8588 (__arm_vrmlaldavhaxq_s32): Define intrinsic.
8589 (__arm_vrmlsldavhaq_s32): Likewise.
8590 (__arm_vrmlsldavhaxq_s32): Likewise.
8591 (__arm_vaddlvaq_p_s32): Likewise.
8592 (__arm_vrev16q_m_s8): Likewise.
8593 (__arm_vrmlaldavhq_p_s32): Likewise.
8594 (__arm_vrmlaldavhxq_p_s32): Likewise.
8595 (__arm_vrmlsldavhq_p_s32): Likewise.
8596 (__arm_vrmlsldavhxq_p_s32): Likewise.
8597 (__arm_vaddlvaq_p_u32): Likewise.
8598 (__arm_vrev16q_m_u8): Likewise.
8599 (__arm_vrmlaldavhq_p_u32): Likewise.
8600 (__arm_vmvnq_m_n_s16): Likewise.
8601 (__arm_vorrq_m_n_s16): Likewise.
8602 (__arm_vqrshrntq_n_s16): Likewise.
8603 (__arm_vqshrnbq_n_s16): Likewise.
8604 (__arm_vqshrntq_n_s16): Likewise.
8605 (__arm_vrshrnbq_n_s16): Likewise.
8606 (__arm_vrshrntq_n_s16): Likewise.
8607 (__arm_vshrnbq_n_s16): Likewise.
8608 (__arm_vshrntq_n_s16): Likewise.
8609 (__arm_vmlaldavaq_s16): Likewise.
8610 (__arm_vmlaldavaxq_s16): Likewise.
8611 (__arm_vmlsldavaq_s16): Likewise.
8612 (__arm_vmlsldavaxq_s16): Likewise.
8613 (__arm_vmlaldavq_p_s16): Likewise.
8614 (__arm_vmlaldavxq_p_s16): Likewise.
8615 (__arm_vmlsldavq_p_s16): Likewise.
8616 (__arm_vmlsldavxq_p_s16): Likewise.
8617 (__arm_vmovlbq_m_s8): Likewise.
8618 (__arm_vmovltq_m_s8): Likewise.
8619 (__arm_vmovnbq_m_s16): Likewise.
8620 (__arm_vmovntq_m_s16): Likewise.
8621 (__arm_vqmovnbq_m_s16): Likewise.
8622 (__arm_vqmovntq_m_s16): Likewise.
8623 (__arm_vrev32q_m_s8): Likewise.
8624 (__arm_vmvnq_m_n_u16): Likewise.
8625 (__arm_vorrq_m_n_u16): Likewise.
8626 (__arm_vqrshruntq_n_s16): Likewise.
8627 (__arm_vqshrunbq_n_s16): Likewise.
8628 (__arm_vqshruntq_n_s16): Likewise.
8629 (__arm_vqmovunbq_m_s16): Likewise.
8630 (__arm_vqmovuntq_m_s16): Likewise.
8631 (__arm_vqrshrntq_n_u16): Likewise.
8632 (__arm_vqshrnbq_n_u16): Likewise.
8633 (__arm_vqshrntq_n_u16): Likewise.
8634 (__arm_vrshrnbq_n_u16): Likewise.
8635 (__arm_vrshrntq_n_u16): Likewise.
8636 (__arm_vshrnbq_n_u16): Likewise.
8637 (__arm_vshrntq_n_u16): Likewise.
8638 (__arm_vmlaldavaq_u16): Likewise.
8639 (__arm_vmlaldavaxq_u16): Likewise.
8640 (__arm_vmlaldavq_p_u16): Likewise.
8641 (__arm_vmlaldavxq_p_u16): Likewise.
8642 (__arm_vmovlbq_m_u8): Likewise.
8643 (__arm_vmovltq_m_u8): Likewise.
8644 (__arm_vmovnbq_m_u16): Likewise.
8645 (__arm_vmovntq_m_u16): Likewise.
8646 (__arm_vqmovnbq_m_u16): Likewise.
8647 (__arm_vqmovntq_m_u16): Likewise.
8648 (__arm_vrev32q_m_u8): Likewise.
8649 (__arm_vmvnq_m_n_s32): Likewise.
8650 (__arm_vorrq_m_n_s32): Likewise.
8651 (__arm_vqrshrntq_n_s32): Likewise.
8652 (__arm_vqshrnbq_n_s32): Likewise.
8653 (__arm_vqshrntq_n_s32): Likewise.
8654 (__arm_vrshrnbq_n_s32): Likewise.
8655 (__arm_vrshrntq_n_s32): Likewise.
8656 (__arm_vshrnbq_n_s32): Likewise.
8657 (__arm_vshrntq_n_s32): Likewise.
8658 (__arm_vmlaldavaq_s32): Likewise.
8659 (__arm_vmlaldavaxq_s32): Likewise.
8660 (__arm_vmlsldavaq_s32): Likewise.
8661 (__arm_vmlsldavaxq_s32): Likewise.
8662 (__arm_vmlaldavq_p_s32): Likewise.
8663 (__arm_vmlaldavxq_p_s32): Likewise.
8664 (__arm_vmlsldavq_p_s32): Likewise.
8665 (__arm_vmlsldavxq_p_s32): Likewise.
8666 (__arm_vmovlbq_m_s16): Likewise.
8667 (__arm_vmovltq_m_s16): Likewise.
8668 (__arm_vmovnbq_m_s32): Likewise.
8669 (__arm_vmovntq_m_s32): Likewise.
8670 (__arm_vqmovnbq_m_s32): Likewise.
8671 (__arm_vqmovntq_m_s32): Likewise.
8672 (__arm_vrev32q_m_s16): Likewise.
8673 (__arm_vmvnq_m_n_u32): Likewise.
8674 (__arm_vorrq_m_n_u32): Likewise.
8675 (__arm_vqrshruntq_n_s32): Likewise.
8676 (__arm_vqshrunbq_n_s32): Likewise.
8677 (__arm_vqshruntq_n_s32): Likewise.
8678 (__arm_vqmovunbq_m_s32): Likewise.
8679 (__arm_vqmovuntq_m_s32): Likewise.
8680 (__arm_vqrshrntq_n_u32): Likewise.
8681 (__arm_vqshrnbq_n_u32): Likewise.
8682 (__arm_vqshrntq_n_u32): Likewise.
8683 (__arm_vrshrnbq_n_u32): Likewise.
8684 (__arm_vrshrntq_n_u32): Likewise.
8685 (__arm_vshrnbq_n_u32): Likewise.
8686 (__arm_vshrntq_n_u32): Likewise.
8687 (__arm_vmlaldavaq_u32): Likewise.
8688 (__arm_vmlaldavaxq_u32): Likewise.
8689 (__arm_vmlaldavq_p_u32): Likewise.
8690 (__arm_vmlaldavxq_p_u32): Likewise.
8691 (__arm_vmovlbq_m_u16): Likewise.
8692 (__arm_vmovltq_m_u16): Likewise.
8693 (__arm_vmovnbq_m_u32): Likewise.
8694 (__arm_vmovntq_m_u32): Likewise.
8695 (__arm_vqmovnbq_m_u32): Likewise.
8696 (__arm_vqmovntq_m_u32): Likewise.
8697 (__arm_vrev32q_m_u16): Likewise.
8698 (__arm_vcvtbq_m_f16_f32): Likewise.
8699 (__arm_vcvtbq_m_f32_f16): Likewise.
8700 (__arm_vcvttq_m_f16_f32): Likewise.
8701 (__arm_vcvttq_m_f32_f16): Likewise.
8702 (__arm_vrev32q_m_f16): Likewise.
8703 (__arm_vcmlaq_f16): Likewise.
8704 (__arm_vcmlaq_rot180_f16): Likewise.
8705 (__arm_vcmlaq_rot270_f16): Likewise.
8706 (__arm_vcmlaq_rot90_f16): Likewise.
8707 (__arm_vfmaq_f16): Likewise.
8708 (__arm_vfmaq_n_f16): Likewise.
8709 (__arm_vfmasq_n_f16): Likewise.
8710 (__arm_vfmsq_f16): Likewise.
8711 (__arm_vabsq_m_f16): Likewise.
8712 (__arm_vcvtmq_m_s16_f16): Likewise.
8713 (__arm_vcvtnq_m_s16_f16): Likewise.
8714 (__arm_vcvtpq_m_s16_f16): Likewise.
8715 (__arm_vcvtq_m_s16_f16): Likewise.
8716 (__arm_vdupq_m_n_f16): Likewise.
8717 (__arm_vmaxnmaq_m_f16): Likewise.
8718 (__arm_vmaxnmavq_p_f16): Likewise.
8719 (__arm_vmaxnmvq_p_f16): Likewise.
8720 (__arm_vminnmaq_m_f16): Likewise.
8721 (__arm_vminnmavq_p_f16): Likewise.
8722 (__arm_vminnmvq_p_f16): Likewise.
8723 (__arm_vnegq_m_f16): Likewise.
8724 (__arm_vpselq_f16): Likewise.
8725 (__arm_vrev64q_m_f16): Likewise.
8726 (__arm_vrndaq_m_f16): Likewise.
8727 (__arm_vrndmq_m_f16): Likewise.
8728 (__arm_vrndnq_m_f16): Likewise.
8729 (__arm_vrndpq_m_f16): Likewise.
8730 (__arm_vrndq_m_f16): Likewise.
8731 (__arm_vrndxq_m_f16): Likewise.
8732 (__arm_vcmpeqq_m_n_f16): Likewise.
8733 (__arm_vcmpgeq_m_f16): Likewise.
8734 (__arm_vcmpgeq_m_n_f16): Likewise.
8735 (__arm_vcmpgtq_m_f16): Likewise.
8736 (__arm_vcmpgtq_m_n_f16): Likewise.
8737 (__arm_vcmpleq_m_f16): Likewise.
8738 (__arm_vcmpleq_m_n_f16): Likewise.
8739 (__arm_vcmpltq_m_f16): Likewise.
8740 (__arm_vcmpltq_m_n_f16): Likewise.
8741 (__arm_vcmpneq_m_f16): Likewise.
8742 (__arm_vcmpneq_m_n_f16): Likewise.
8743 (__arm_vcvtmq_m_u16_f16): Likewise.
8744 (__arm_vcvtnq_m_u16_f16): Likewise.
8745 (__arm_vcvtpq_m_u16_f16): Likewise.
8746 (__arm_vcvtq_m_u16_f16): Likewise.
8747 (__arm_vcmlaq_f32): Likewise.
8748 (__arm_vcmlaq_rot180_f32): Likewise.
8749 (__arm_vcmlaq_rot270_f32): Likewise.
8750 (__arm_vcmlaq_rot90_f32): Likewise.
8751 (__arm_vfmaq_f32): Likewise.
8752 (__arm_vfmaq_n_f32): Likewise.
8753 (__arm_vfmasq_n_f32): Likewise.
8754 (__arm_vfmsq_f32): Likewise.
8755 (__arm_vabsq_m_f32): Likewise.
8756 (__arm_vcvtmq_m_s32_f32): Likewise.
8757 (__arm_vcvtnq_m_s32_f32): Likewise.
8758 (__arm_vcvtpq_m_s32_f32): Likewise.
8759 (__arm_vcvtq_m_s32_f32): Likewise.
8760 (__arm_vdupq_m_n_f32): Likewise.
8761 (__arm_vmaxnmaq_m_f32): Likewise.
8762 (__arm_vmaxnmavq_p_f32): Likewise.
8763 (__arm_vmaxnmvq_p_f32): Likewise.
8764 (__arm_vminnmaq_m_f32): Likewise.
8765 (__arm_vminnmavq_p_f32): Likewise.
8766 (__arm_vminnmvq_p_f32): Likewise.
8767 (__arm_vnegq_m_f32): Likewise.
8768 (__arm_vpselq_f32): Likewise.
8769 (__arm_vrev64q_m_f32): Likewise.
8770 (__arm_vrndaq_m_f32): Likewise.
8771 (__arm_vrndmq_m_f32): Likewise.
8772 (__arm_vrndnq_m_f32): Likewise.
8773 (__arm_vrndpq_m_f32): Likewise.
8774 (__arm_vrndq_m_f32): Likewise.
8775 (__arm_vrndxq_m_f32): Likewise.
8776 (__arm_vcmpeqq_m_n_f32): Likewise.
8777 (__arm_vcmpgeq_m_f32): Likewise.
8778 (__arm_vcmpgeq_m_n_f32): Likewise.
8779 (__arm_vcmpgtq_m_f32): Likewise.
8780 (__arm_vcmpgtq_m_n_f32): Likewise.
8781 (__arm_vcmpleq_m_f32): Likewise.
8782 (__arm_vcmpleq_m_n_f32): Likewise.
8783 (__arm_vcmpltq_m_f32): Likewise.
8784 (__arm_vcmpltq_m_n_f32): Likewise.
8785 (__arm_vcmpneq_m_f32): Likewise.
8786 (__arm_vcmpneq_m_n_f32): Likewise.
8787 (__arm_vcvtmq_m_u32_f32): Likewise.
8788 (__arm_vcvtnq_m_u32_f32): Likewise.
8789 (__arm_vcvtpq_m_u32_f32): Likewise.
8790 (__arm_vcvtq_m_u32_f32): Likewise.
8791 (vcvtq_m): Define polymorphic variant.
8792 (vabsq_m): Likewise.
8794 (vcmlaq_rot180): Likewise.
8795 (vcmlaq_rot270): Likewise.
8796 (vcmlaq_rot90): Likewise.
8797 (vcmpeqq_m_n): Likewise.
8798 (vcmpgeq_m_n): Likewise.
8799 (vrndxq_m): Likewise.
8800 (vrndq_m): Likewise.
8801 (vrndpq_m): Likewise.
8802 (vcmpgtq_m_n): Likewise.
8803 (vcmpgtq_m): Likewise.
8804 (vcmpleq_m): Likewise.
8805 (vcmpleq_m_n): Likewise.
8806 (vcmpltq_m_n): Likewise.
8807 (vcmpltq_m): Likewise.
8808 (vcmpneq_m): Likewise.
8809 (vcmpneq_m_n): Likewise.
8810 (vcvtbq_m): Likewise.
8811 (vcvttq_m): Likewise.
8812 (vcvtmq_m): Likewise.
8813 (vcvtnq_m): Likewise.
8814 (vcvtpq_m): Likewise.
8815 (vdupq_m_n): Likewise.
8816 (vfmaq_n): Likewise.
8818 (vfmasq_n): Likewise.
8820 (vmaxnmaq_m): Likewise.
8821 (vmaxnmavq_m): Likewise.
8822 (vmaxnmvq_m): Likewise.
8823 (vmaxnmavq_p): Likewise.
8824 (vmaxnmvq_p): Likewise.
8825 (vminnmaq_m): Likewise.
8826 (vminnmavq_p): Likewise.
8827 (vminnmvq_p): Likewise.
8828 (vrndnq_m): Likewise.
8829 (vrndaq_m): Likewise.
8830 (vrndmq_m): Likewise.
8831 (vrev64q_m): Likewise.
8832 (vrev32q_m): Likewise.
8834 (vnegq_m): Likewise.
8835 (vcmpgeq_m): Likewise.
8836 (vshrntq_n): Likewise.
8837 (vrshrntq_n): Likewise.
8838 (vmovlbq_m): Likewise.
8839 (vmovnbq_m): Likewise.
8840 (vmovntq_m): Likewise.
8841 (vmvnq_m_n): Likewise.
8842 (vmvnq_m): Likewise.
8843 (vshrnbq_n): Likewise.
8844 (vrshrnbq_n): Likewise.
8845 (vqshruntq_n): Likewise.
8846 (vrev16q_m): Likewise.
8847 (vqshrunbq_n): Likewise.
8848 (vqshrntq_n): Likewise.
8849 (vqrshruntq_n): Likewise.
8850 (vqrshrntq_n): Likewise.
8851 (vqshrnbq_n): Likewise.
8852 (vqmovuntq_m): Likewise.
8853 (vqmovntq_m): Likewise.
8854 (vqmovnbq_m): Likewise.
8855 (vorrq_m_n): Likewise.
8856 (vmovltq_m): Likewise.
8857 (vqmovunbq_m): Likewise.
8858 (vaddlvaq_p): Likewise.
8859 (vmlaldavaq): Likewise.
8860 (vmlaldavaxq): Likewise.
8861 (vmlaldavq_p): Likewise.
8862 (vmlaldavxq_p): Likewise.
8863 (vmlsldavaq): Likewise.
8864 (vmlsldavaxq): Likewise.
8865 (vmlsldavq_p): Likewise.
8866 (vmlsldavxq_p): Likewise.
8867 (vrmlaldavhaxq): Likewise.
8868 (vrmlaldavhq_p): Likewise.
8869 (vrmlaldavhxq_p): Likewise.
8870 (vrmlsldavhaq): Likewise.
8871 (vrmlsldavhaxq): Likewise.
8872 (vrmlsldavhq_p): Likewise.
8873 (vrmlsldavhxq_p): Likewise.
8874 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
8876 (TERNOP_NONE_NONE_NONE_IMM): Likewise.
8877 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
8878 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
8879 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
8880 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
8881 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
8882 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
8883 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
8884 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
8885 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
8886 (MVE_pred3): Likewise.
8887 (MVE_constraint1): Likewise.
8888 (MVE_pred1): Likewise.
8889 (VMLALDAVQ_P): Define iterator.
8890 (VQMOVNBQ_M): Likewise.
8891 (VMOVLTQ_M): Likewise.
8892 (VMOVNBQ_M): Likewise.
8893 (VRSHRNTQ_N): Likewise.
8894 (VORRQ_M_N): Likewise.
8895 (VREV32Q_M): Likewise.
8896 (VREV16Q_M): Likewise.
8897 (VQRSHRNTQ_N): Likewise.
8898 (VMOVNTQ_M): Likewise.
8899 (VMOVLBQ_M): Likewise.
8900 (VMLALDAVAQ): Likewise.
8901 (VQSHRNBQ_N): Likewise.
8902 (VSHRNBQ_N): Likewise.
8903 (VRSHRNBQ_N): Likewise.
8904 (VMLALDAVXQ_P): Likewise.
8905 (VQMOVNTQ_M): Likewise.
8906 (VMVNQ_M_N): Likewise.
8907 (VQSHRNTQ_N): Likewise.
8908 (VMLALDAVAXQ): Likewise.
8909 (VSHRNTQ_N): Likewise.
8910 (VCVTMQ_M): Likewise.
8911 (VCVTNQ_M): Likewise.
8912 (VCVTPQ_M): Likewise.
8913 (VCVTQ_M_N_FROM_F): Likewise.
8914 (VCVTQ_M_FROM_F): Likewise.
8915 (VRMLALDAVHQ_P): Likewise.
8916 (VADDLVAQ_P): Likewise.
8917 (mve_vrndq_m_f<mode>): Define RTL pattern.
8918 (mve_vabsq_m_f<mode>): Likewise.
8919 (mve_vaddlvaq_p_<supf>v4si): Likewise.
8920 (mve_vcmlaq_f<mode>): Likewise.
8921 (mve_vcmlaq_rot180_f<mode>): Likewise.
8922 (mve_vcmlaq_rot270_f<mode>): Likewise.
8923 (mve_vcmlaq_rot90_f<mode>): Likewise.
8924 (mve_vcmpeqq_m_n_f<mode>): Likewise.
8925 (mve_vcmpgeq_m_f<mode>): Likewise.
8926 (mve_vcmpgeq_m_n_f<mode>): Likewise.
8927 (mve_vcmpgtq_m_f<mode>): Likewise.
8928 (mve_vcmpgtq_m_n_f<mode>): Likewise.
8929 (mve_vcmpleq_m_f<mode>): Likewise.
8930 (mve_vcmpleq_m_n_f<mode>): Likewise.
8931 (mve_vcmpltq_m_f<mode>): Likewise.
8932 (mve_vcmpltq_m_n_f<mode>): Likewise.
8933 (mve_vcmpneq_m_f<mode>): Likewise.
8934 (mve_vcmpneq_m_n_f<mode>): Likewise.
8935 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
8936 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
8937 (mve_vcvttq_m_f16_f32v8hf): Likewise.
8938 (mve_vcvttq_m_f32_f16v4sf): Likewise.
8939 (mve_vdupq_m_n_f<mode>): Likewise.
8940 (mve_vfmaq_f<mode>): Likewise.
8941 (mve_vfmaq_n_f<mode>): Likewise.
8942 (mve_vfmasq_n_f<mode>): Likewise.
8943 (mve_vfmsq_f<mode>): Likewise.
8944 (mve_vmaxnmaq_m_f<mode>): Likewise.
8945 (mve_vmaxnmavq_p_f<mode>): Likewise.
8946 (mve_vmaxnmvq_p_f<mode>): Likewise.
8947 (mve_vminnmaq_m_f<mode>): Likewise.
8948 (mve_vminnmavq_p_f<mode>): Likewise.
8949 (mve_vminnmvq_p_f<mode>): Likewise.
8950 (mve_vmlaldavaq_<supf><mode>): Likewise.
8951 (mve_vmlaldavaxq_<supf><mode>): Likewise.
8952 (mve_vmlaldavq_p_<supf><mode>): Likewise.
8953 (mve_vmlaldavxq_p_<supf><mode>): Likewise.
8954 (mve_vmlsldavaq_s<mode>): Likewise.
8955 (mve_vmlsldavaxq_s<mode>): Likewise.
8956 (mve_vmlsldavq_p_s<mode>): Likewise.
8957 (mve_vmlsldavxq_p_s<mode>): Likewise.
8958 (mve_vmovlbq_m_<supf><mode>): Likewise.
8959 (mve_vmovltq_m_<supf><mode>): Likewise.
8960 (mve_vmovnbq_m_<supf><mode>): Likewise.
8961 (mve_vmovntq_m_<supf><mode>): Likewise.
8962 (mve_vmvnq_m_n_<supf><mode>): Likewise.
8963 (mve_vnegq_m_f<mode>): Likewise.
8964 (mve_vorrq_m_n_<supf><mode>): Likewise.
8965 (mve_vpselq_f<mode>): Likewise.
8966 (mve_vqmovnbq_m_<supf><mode>): Likewise.
8967 (mve_vqmovntq_m_<supf><mode>): Likewise.
8968 (mve_vqmovunbq_m_s<mode>): Likewise.
8969 (mve_vqmovuntq_m_s<mode>): Likewise.
8970 (mve_vqrshrntq_n_<supf><mode>): Likewise.
8971 (mve_vqrshruntq_n_s<mode>): Likewise.
8972 (mve_vqshrnbq_n_<supf><mode>): Likewise.
8973 (mve_vqshrntq_n_<supf><mode>): Likewise.
8974 (mve_vqshrunbq_n_s<mode>): Likewise.
8975 (mve_vqshruntq_n_s<mode>): Likewise.
8976 (mve_vrev32q_m_fv8hf): Likewise.
8977 (mve_vrev32q_m_<supf><mode>): Likewise.
8978 (mve_vrev64q_m_f<mode>): Likewise.
8979 (mve_vrmlaldavhaxq_sv4si): Likewise.
8980 (mve_vrmlaldavhxq_p_sv4si): Likewise.
8981 (mve_vrmlsldavhaxq_sv4si): Likewise.
8982 (mve_vrmlsldavhq_p_sv4si): Likewise.
8983 (mve_vrmlsldavhxq_p_sv4si): Likewise.
8984 (mve_vrndaq_m_f<mode>): Likewise.
8985 (mve_vrndmq_m_f<mode>): Likewise.
8986 (mve_vrndnq_m_f<mode>): Likewise.
8987 (mve_vrndpq_m_f<mode>): Likewise.
8988 (mve_vrndxq_m_f<mode>): Likewise.
8989 (mve_vrshrnbq_n_<supf><mode>): Likewise.
8990 (mve_vrshrntq_n_<supf><mode>): Likewise.
8991 (mve_vshrnbq_n_<supf><mode>): Likewise.
8992 (mve_vshrntq_n_<supf><mode>): Likewise.
8993 (mve_vcvtmq_m_<supf><mode>): Likewise.
8994 (mve_vcvtpq_m_<supf><mode>): Likewise.
8995 (mve_vcvtnq_m_<supf><mode>): Likewise.
8996 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
8997 (mve_vrev16q_m_<supf>v16qi): Likewise.
8998 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
8999 (mve_vrmlaldavhq_p_<supf>v4si): Likewise.
9000 (mve_vrmlsldavhaq_sv4si): Likewise.
9002 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
9003 Mihail Ionescu <mihail.ionescu@arm.com>
9004 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9006 * config/arm/arm_mve.h (vpselq_u8): Define macro.
9007 (vpselq_s8): Likewise.
9008 (vrev64q_m_u8): Likewise.
9009 (vqrdmlashq_n_u8): Likewise.
9010 (vqrdmlahq_n_u8): Likewise.
9011 (vqdmlahq_n_u8): Likewise.
9012 (vmvnq_m_u8): Likewise.
9013 (vmlasq_n_u8): Likewise.
9014 (vmlaq_n_u8): Likewise.
9015 (vmladavq_p_u8): Likewise.
9016 (vmladavaq_u8): Likewise.
9017 (vminvq_p_u8): Likewise.
9018 (vmaxvq_p_u8): Likewise.
9019 (vdupq_m_n_u8): Likewise.
9020 (vcmpneq_m_u8): Likewise.
9021 (vcmpneq_m_n_u8): Likewise.
9022 (vcmphiq_m_u8): Likewise.
9023 (vcmphiq_m_n_u8): Likewise.
9024 (vcmpeqq_m_u8): Likewise.
9025 (vcmpeqq_m_n_u8): Likewise.
9026 (vcmpcsq_m_u8): Likewise.
9027 (vcmpcsq_m_n_u8): Likewise.
9028 (vclzq_m_u8): Likewise.
9029 (vaddvaq_p_u8): Likewise.
9030 (vsriq_n_u8): Likewise.
9031 (vsliq_n_u8): Likewise.
9032 (vshlq_m_r_u8): Likewise.
9033 (vrshlq_m_n_u8): Likewise.
9034 (vqshlq_m_r_u8): Likewise.
9035 (vqrshlq_m_n_u8): Likewise.
9036 (vminavq_p_s8): Likewise.
9037 (vminaq_m_s8): Likewise.
9038 (vmaxavq_p_s8): Likewise.
9039 (vmaxaq_m_s8): Likewise.
9040 (vcmpneq_m_s8): Likewise.
9041 (vcmpneq_m_n_s8): Likewise.
9042 (vcmpltq_m_s8): Likewise.
9043 (vcmpltq_m_n_s8): Likewise.
9044 (vcmpleq_m_s8): Likewise.
9045 (vcmpleq_m_n_s8): Likewise.
9046 (vcmpgtq_m_s8): Likewise.
9047 (vcmpgtq_m_n_s8): Likewise.
9048 (vcmpgeq_m_s8): Likewise.
9049 (vcmpgeq_m_n_s8): Likewise.
9050 (vcmpeqq_m_s8): Likewise.
9051 (vcmpeqq_m_n_s8): Likewise.
9052 (vshlq_m_r_s8): Likewise.
9053 (vrshlq_m_n_s8): Likewise.
9054 (vrev64q_m_s8): Likewise.
9055 (vqshlq_m_r_s8): Likewise.
9056 (vqrshlq_m_n_s8): Likewise.
9057 (vqnegq_m_s8): Likewise.
9058 (vqabsq_m_s8): Likewise.
9059 (vnegq_m_s8): Likewise.
9060 (vmvnq_m_s8): Likewise.
9061 (vmlsdavxq_p_s8): Likewise.
9062 (vmlsdavq_p_s8): Likewise.
9063 (vmladavxq_p_s8): Likewise.
9064 (vmladavq_p_s8): Likewise.
9065 (vminvq_p_s8): Likewise.
9066 (vmaxvq_p_s8): Likewise.
9067 (vdupq_m_n_s8): Likewise.
9068 (vclzq_m_s8): Likewise.
9069 (vclsq_m_s8): Likewise.
9070 (vaddvaq_p_s8): Likewise.
9071 (vabsq_m_s8): Likewise.
9072 (vqrdmlsdhxq_s8): Likewise.
9073 (vqrdmlsdhq_s8): Likewise.
9074 (vqrdmlashq_n_s8): Likewise.
9075 (vqrdmlahq_n_s8): Likewise.
9076 (vqrdmladhxq_s8): Likewise.
9077 (vqrdmladhq_s8): Likewise.
9078 (vqdmlsdhxq_s8): Likewise.
9079 (vqdmlsdhq_s8): Likewise.
9080 (vqdmlahq_n_s8): Likewise.
9081 (vqdmladhxq_s8): Likewise.
9082 (vqdmladhq_s8): Likewise.
9083 (vmlsdavaxq_s8): Likewise.
9084 (vmlsdavaq_s8): Likewise.
9085 (vmlasq_n_s8): Likewise.
9086 (vmlaq_n_s8): Likewise.
9087 (vmladavaxq_s8): Likewise.
9088 (vmladavaq_s8): Likewise.
9089 (vsriq_n_s8): Likewise.
9090 (vsliq_n_s8): Likewise.
9091 (vpselq_u16): Likewise.
9092 (vpselq_s16): Likewise.
9093 (vrev64q_m_u16): Likewise.
9094 (vqrdmlashq_n_u16): Likewise.
9095 (vqrdmlahq_n_u16): Likewise.
9096 (vqdmlahq_n_u16): Likewise.
9097 (vmvnq_m_u16): Likewise.
9098 (vmlasq_n_u16): Likewise.
9099 (vmlaq_n_u16): Likewise.
9100 (vmladavq_p_u16): Likewise.
9101 (vmladavaq_u16): Likewise.
9102 (vminvq_p_u16): Likewise.
9103 (vmaxvq_p_u16): Likewise.
9104 (vdupq_m_n_u16): Likewise.
9105 (vcmpneq_m_u16): Likewise.
9106 (vcmpneq_m_n_u16): Likewise.
9107 (vcmphiq_m_u16): Likewise.
9108 (vcmphiq_m_n_u16): Likewise.
9109 (vcmpeqq_m_u16): Likewise.
9110 (vcmpeqq_m_n_u16): Likewise.
9111 (vcmpcsq_m_u16): Likewise.
9112 (vcmpcsq_m_n_u16): Likewise.
9113 (vclzq_m_u16): Likewise.
9114 (vaddvaq_p_u16): Likewise.
9115 (vsriq_n_u16): Likewise.
9116 (vsliq_n_u16): Likewise.
9117 (vshlq_m_r_u16): Likewise.
9118 (vrshlq_m_n_u16): Likewise.
9119 (vqshlq_m_r_u16): Likewise.
9120 (vqrshlq_m_n_u16): Likewise.
9121 (vminavq_p_s16): Likewise.
9122 (vminaq_m_s16): Likewise.
9123 (vmaxavq_p_s16): Likewise.
9124 (vmaxaq_m_s16): Likewise.
9125 (vcmpneq_m_s16): Likewise.
9126 (vcmpneq_m_n_s16): Likewise.
9127 (vcmpltq_m_s16): Likewise.
9128 (vcmpltq_m_n_s16): Likewise.
9129 (vcmpleq_m_s16): Likewise.
9130 (vcmpleq_m_n_s16): Likewise.
9131 (vcmpgtq_m_s16): Likewise.
9132 (vcmpgtq_m_n_s16): Likewise.
9133 (vcmpgeq_m_s16): Likewise.
9134 (vcmpgeq_m_n_s16): Likewise.
9135 (vcmpeqq_m_s16): Likewise.
9136 (vcmpeqq_m_n_s16): Likewise.
9137 (vshlq_m_r_s16): Likewise.
9138 (vrshlq_m_n_s16): Likewise.
9139 (vrev64q_m_s16): Likewise.
9140 (vqshlq_m_r_s16): Likewise.
9141 (vqrshlq_m_n_s16): Likewise.
9142 (vqnegq_m_s16): Likewise.
9143 (vqabsq_m_s16): Likewise.
9144 (vnegq_m_s16): Likewise.
9145 (vmvnq_m_s16): Likewise.
9146 (vmlsdavxq_p_s16): Likewise.
9147 (vmlsdavq_p_s16): Likewise.
9148 (vmladavxq_p_s16): Likewise.
9149 (vmladavq_p_s16): Likewise.
9150 (vminvq_p_s16): Likewise.
9151 (vmaxvq_p_s16): Likewise.
9152 (vdupq_m_n_s16): Likewise.
9153 (vclzq_m_s16): Likewise.
9154 (vclsq_m_s16): Likewise.
9155 (vaddvaq_p_s16): Likewise.
9156 (vabsq_m_s16): Likewise.
9157 (vqrdmlsdhxq_s16): Likewise.
9158 (vqrdmlsdhq_s16): Likewise.
9159 (vqrdmlashq_n_s16): Likewise.
9160 (vqrdmlahq_n_s16): Likewise.
9161 (vqrdmladhxq_s16): Likewise.
9162 (vqrdmladhq_s16): Likewise.
9163 (vqdmlsdhxq_s16): Likewise.
9164 (vqdmlsdhq_s16): Likewise.
9165 (vqdmlahq_n_s16): Likewise.
9166 (vqdmladhxq_s16): Likewise.
9167 (vqdmladhq_s16): Likewise.
9168 (vmlsdavaxq_s16): Likewise.
9169 (vmlsdavaq_s16): Likewise.
9170 (vmlasq_n_s16): Likewise.
9171 (vmlaq_n_s16): Likewise.
9172 (vmladavaxq_s16): Likewise.
9173 (vmladavaq_s16): Likewise.
9174 (vsriq_n_s16): Likewise.
9175 (vsliq_n_s16): Likewise.
9176 (vpselq_u32): Likewise.
9177 (vpselq_s32): Likewise.
9178 (vrev64q_m_u32): Likewise.
9179 (vqrdmlashq_n_u32): Likewise.
9180 (vqrdmlahq_n_u32): Likewise.
9181 (vqdmlahq_n_u32): Likewise.
9182 (vmvnq_m_u32): Likewise.
9183 (vmlasq_n_u32): Likewise.
9184 (vmlaq_n_u32): Likewise.
9185 (vmladavq_p_u32): Likewise.
9186 (vmladavaq_u32): Likewise.
9187 (vminvq_p_u32): Likewise.
9188 (vmaxvq_p_u32): Likewise.
9189 (vdupq_m_n_u32): Likewise.
9190 (vcmpneq_m_u32): Likewise.
9191 (vcmpneq_m_n_u32): Likewise.
9192 (vcmphiq_m_u32): Likewise.
9193 (vcmphiq_m_n_u32): Likewise.
9194 (vcmpeqq_m_u32): Likewise.
9195 (vcmpeqq_m_n_u32): Likewise.
9196 (vcmpcsq_m_u32): Likewise.
9197 (vcmpcsq_m_n_u32): Likewise.
9198 (vclzq_m_u32): Likewise.
9199 (vaddvaq_p_u32): Likewise.
9200 (vsriq_n_u32): Likewise.
9201 (vsliq_n_u32): Likewise.
9202 (vshlq_m_r_u32): Likewise.
9203 (vrshlq_m_n_u32): Likewise.
9204 (vqshlq_m_r_u32): Likewise.
9205 (vqrshlq_m_n_u32): Likewise.
9206 (vminavq_p_s32): Likewise.
9207 (vminaq_m_s32): Likewise.
9208 (vmaxavq_p_s32): Likewise.
9209 (vmaxaq_m_s32): Likewise.
9210 (vcmpneq_m_s32): Likewise.
9211 (vcmpneq_m_n_s32): Likewise.
9212 (vcmpltq_m_s32): Likewise.
9213 (vcmpltq_m_n_s32): Likewise.
9214 (vcmpleq_m_s32): Likewise.
9215 (vcmpleq_m_n_s32): Likewise.
9216 (vcmpgtq_m_s32): Likewise.
9217 (vcmpgtq_m_n_s32): Likewise.
9218 (vcmpgeq_m_s32): Likewise.
9219 (vcmpgeq_m_n_s32): Likewise.
9220 (vcmpeqq_m_s32): Likewise.
9221 (vcmpeqq_m_n_s32): Likewise.
9222 (vshlq_m_r_s32): Likewise.
9223 (vrshlq_m_n_s32): Likewise.
9224 (vrev64q_m_s32): Likewise.
9225 (vqshlq_m_r_s32): Likewise.
9226 (vqrshlq_m_n_s32): Likewise.
9227 (vqnegq_m_s32): Likewise.
9228 (vqabsq_m_s32): Likewise.
9229 (vnegq_m_s32): Likewise.
9230 (vmvnq_m_s32): Likewise.
9231 (vmlsdavxq_p_s32): Likewise.
9232 (vmlsdavq_p_s32): Likewise.
9233 (vmladavxq_p_s32): Likewise.
9234 (vmladavq_p_s32): Likewise.
9235 (vminvq_p_s32): Likewise.
9236 (vmaxvq_p_s32): Likewise.
9237 (vdupq_m_n_s32): Likewise.
9238 (vclzq_m_s32): Likewise.
9239 (vclsq_m_s32): Likewise.
9240 (vaddvaq_p_s32): Likewise.
9241 (vabsq_m_s32): Likewise.
9242 (vqrdmlsdhxq_s32): Likewise.
9243 (vqrdmlsdhq_s32): Likewise.
9244 (vqrdmlashq_n_s32): Likewise.
9245 (vqrdmlahq_n_s32): Likewise.
9246 (vqrdmladhxq_s32): Likewise.
9247 (vqrdmladhq_s32): Likewise.
9248 (vqdmlsdhxq_s32): Likewise.
9249 (vqdmlsdhq_s32): Likewise.
9250 (vqdmlahq_n_s32): Likewise.
9251 (vqdmladhxq_s32): Likewise.
9252 (vqdmladhq_s32): Likewise.
9253 (vmlsdavaxq_s32): Likewise.
9254 (vmlsdavaq_s32): Likewise.
9255 (vmlasq_n_s32): Likewise.
9256 (vmlaq_n_s32): Likewise.
9257 (vmladavaxq_s32): Likewise.
9258 (vmladavaq_s32): Likewise.
9259 (vsriq_n_s32): Likewise.
9260 (vsliq_n_s32): Likewise.
9261 (vpselq_u64): Likewise.
9262 (vpselq_s64): Likewise.
9263 (__arm_vpselq_u8): Define intrinsic.
9264 (__arm_vpselq_s8): Likewise.
9265 (__arm_vrev64q_m_u8): Likewise.
9266 (__arm_vqrdmlashq_n_u8): Likewise.
9267 (__arm_vqrdmlahq_n_u8): Likewise.
9268 (__arm_vqdmlahq_n_u8): Likewise.
9269 (__arm_vmvnq_m_u8): Likewise.
9270 (__arm_vmlasq_n_u8): Likewise.
9271 (__arm_vmlaq_n_u8): Likewise.
9272 (__arm_vmladavq_p_u8): Likewise.
9273 (__arm_vmladavaq_u8): Likewise.
9274 (__arm_vminvq_p_u8): Likewise.
9275 (__arm_vmaxvq_p_u8): Likewise.
9276 (__arm_vdupq_m_n_u8): Likewise.
9277 (__arm_vcmpneq_m_u8): Likewise.
9278 (__arm_vcmpneq_m_n_u8): Likewise.
9279 (__arm_vcmphiq_m_u8): Likewise.
9280 (__arm_vcmphiq_m_n_u8): Likewise.
9281 (__arm_vcmpeqq_m_u8): Likewise.
9282 (__arm_vcmpeqq_m_n_u8): Likewise.
9283 (__arm_vcmpcsq_m_u8): Likewise.
9284 (__arm_vcmpcsq_m_n_u8): Likewise.
9285 (__arm_vclzq_m_u8): Likewise.
9286 (__arm_vaddvaq_p_u8): Likewise.
9287 (__arm_vsriq_n_u8): Likewise.
9288 (__arm_vsliq_n_u8): Likewise.
9289 (__arm_vshlq_m_r_u8): Likewise.
9290 (__arm_vrshlq_m_n_u8): Likewise.
9291 (__arm_vqshlq_m_r_u8): Likewise.
9292 (__arm_vqrshlq_m_n_u8): Likewise.
9293 (__arm_vminavq_p_s8): Likewise.
9294 (__arm_vminaq_m_s8): Likewise.
9295 (__arm_vmaxavq_p_s8): Likewise.
9296 (__arm_vmaxaq_m_s8): Likewise.
9297 (__arm_vcmpneq_m_s8): Likewise.
9298 (__arm_vcmpneq_m_n_s8): Likewise.
9299 (__arm_vcmpltq_m_s8): Likewise.
9300 (__arm_vcmpltq_m_n_s8): Likewise.
9301 (__arm_vcmpleq_m_s8): Likewise.
9302 (__arm_vcmpleq_m_n_s8): Likewise.
9303 (__arm_vcmpgtq_m_s8): Likewise.
9304 (__arm_vcmpgtq_m_n_s8): Likewise.
9305 (__arm_vcmpgeq_m_s8): Likewise.
9306 (__arm_vcmpgeq_m_n_s8): Likewise.
9307 (__arm_vcmpeqq_m_s8): Likewise.
9308 (__arm_vcmpeqq_m_n_s8): Likewise.
9309 (__arm_vshlq_m_r_s8): Likewise.
9310 (__arm_vrshlq_m_n_s8): Likewise.
9311 (__arm_vrev64q_m_s8): Likewise.
9312 (__arm_vqshlq_m_r_s8): Likewise.
9313 (__arm_vqrshlq_m_n_s8): Likewise.
9314 (__arm_vqnegq_m_s8): Likewise.
9315 (__arm_vqabsq_m_s8): Likewise.
9316 (__arm_vnegq_m_s8): Likewise.
9317 (__arm_vmvnq_m_s8): Likewise.
9318 (__arm_vmlsdavxq_p_s8): Likewise.
9319 (__arm_vmlsdavq_p_s8): Likewise.
9320 (__arm_vmladavxq_p_s8): Likewise.
9321 (__arm_vmladavq_p_s8): Likewise.
9322 (__arm_vminvq_p_s8): Likewise.
9323 (__arm_vmaxvq_p_s8): Likewise.
9324 (__arm_vdupq_m_n_s8): Likewise.
9325 (__arm_vclzq_m_s8): Likewise.
9326 (__arm_vclsq_m_s8): Likewise.
9327 (__arm_vaddvaq_p_s8): Likewise.
9328 (__arm_vabsq_m_s8): Likewise.
9329 (__arm_vqrdmlsdhxq_s8): Likewise.
9330 (__arm_vqrdmlsdhq_s8): Likewise.
9331 (__arm_vqrdmlashq_n_s8): Likewise.
9332 (__arm_vqrdmlahq_n_s8): Likewise.
9333 (__arm_vqrdmladhxq_s8): Likewise.
9334 (__arm_vqrdmladhq_s8): Likewise.
9335 (__arm_vqdmlsdhxq_s8): Likewise.
9336 (__arm_vqdmlsdhq_s8): Likewise.
9337 (__arm_vqdmlahq_n_s8): Likewise.
9338 (__arm_vqdmladhxq_s8): Likewise.
9339 (__arm_vqdmladhq_s8): Likewise.
9340 (__arm_vmlsdavaxq_s8): Likewise.
9341 (__arm_vmlsdavaq_s8): Likewise.
9342 (__arm_vmlasq_n_s8): Likewise.
9343 (__arm_vmlaq_n_s8): Likewise.
9344 (__arm_vmladavaxq_s8): Likewise.
9345 (__arm_vmladavaq_s8): Likewise.
9346 (__arm_vsriq_n_s8): Likewise.
9347 (__arm_vsliq_n_s8): Likewise.
9348 (__arm_vpselq_u16): Likewise.
9349 (__arm_vpselq_s16): Likewise.
9350 (__arm_vrev64q_m_u16): Likewise.
9351 (__arm_vqrdmlashq_n_u16): Likewise.
9352 (__arm_vqrdmlahq_n_u16): Likewise.
9353 (__arm_vqdmlahq_n_u16): Likewise.
9354 (__arm_vmvnq_m_u16): Likewise.
9355 (__arm_vmlasq_n_u16): Likewise.
9356 (__arm_vmlaq_n_u16): Likewise.
9357 (__arm_vmladavq_p_u16): Likewise.
9358 (__arm_vmladavaq_u16): Likewise.
9359 (__arm_vminvq_p_u16): Likewise.
9360 (__arm_vmaxvq_p_u16): Likewise.
9361 (__arm_vdupq_m_n_u16): Likewise.
9362 (__arm_vcmpneq_m_u16): Likewise.
9363 (__arm_vcmpneq_m_n_u16): Likewise.
9364 (__arm_vcmphiq_m_u16): Likewise.
9365 (__arm_vcmphiq_m_n_u16): Likewise.
9366 (__arm_vcmpeqq_m_u16): Likewise.
9367 (__arm_vcmpeqq_m_n_u16): Likewise.
9368 (__arm_vcmpcsq_m_u16): Likewise.
9369 (__arm_vcmpcsq_m_n_u16): Likewise.
9370 (__arm_vclzq_m_u16): Likewise.
9371 (__arm_vaddvaq_p_u16): Likewise.
9372 (__arm_vsriq_n_u16): Likewise.
9373 (__arm_vsliq_n_u16): Likewise.
9374 (__arm_vshlq_m_r_u16): Likewise.
9375 (__arm_vrshlq_m_n_u16): Likewise.
9376 (__arm_vqshlq_m_r_u16): Likewise.
9377 (__arm_vqrshlq_m_n_u16): Likewise.
9378 (__arm_vminavq_p_s16): Likewise.
9379 (__arm_vminaq_m_s16): Likewise.
9380 (__arm_vmaxavq_p_s16): Likewise.
9381 (__arm_vmaxaq_m_s16): Likewise.
9382 (__arm_vcmpneq_m_s16): Likewise.
9383 (__arm_vcmpneq_m_n_s16): Likewise.
9384 (__arm_vcmpltq_m_s16): Likewise.
9385 (__arm_vcmpltq_m_n_s16): Likewise.
9386 (__arm_vcmpleq_m_s16): Likewise.
9387 (__arm_vcmpleq_m_n_s16): Likewise.
9388 (__arm_vcmpgtq_m_s16): Likewise.
9389 (__arm_vcmpgtq_m_n_s16): Likewise.
9390 (__arm_vcmpgeq_m_s16): Likewise.
9391 (__arm_vcmpgeq_m_n_s16): Likewise.
9392 (__arm_vcmpeqq_m_s16): Likewise.
9393 (__arm_vcmpeqq_m_n_s16): Likewise.
9394 (__arm_vshlq_m_r_s16): Likewise.
9395 (__arm_vrshlq_m_n_s16): Likewise.
9396 (__arm_vrev64q_m_s16): Likewise.
9397 (__arm_vqshlq_m_r_s16): Likewise.
9398 (__arm_vqrshlq_m_n_s16): Likewise.
9399 (__arm_vqnegq_m_s16): Likewise.
9400 (__arm_vqabsq_m_s16): Likewise.
9401 (__arm_vnegq_m_s16): Likewise.
9402 (__arm_vmvnq_m_s16): Likewise.
9403 (__arm_vmlsdavxq_p_s16): Likewise.
9404 (__arm_vmlsdavq_p_s16): Likewise.
9405 (__arm_vmladavxq_p_s16): Likewise.
9406 (__arm_vmladavq_p_s16): Likewise.
9407 (__arm_vminvq_p_s16): Likewise.
9408 (__arm_vmaxvq_p_s16): Likewise.
9409 (__arm_vdupq_m_n_s16): Likewise.
9410 (__arm_vclzq_m_s16): Likewise.
9411 (__arm_vclsq_m_s16): Likewise.
9412 (__arm_vaddvaq_p_s16): Likewise.
9413 (__arm_vabsq_m_s16): Likewise.
9414 (__arm_vqrdmlsdhxq_s16): Likewise.
9415 (__arm_vqrdmlsdhq_s16): Likewise.
9416 (__arm_vqrdmlashq_n_s16): Likewise.
9417 (__arm_vqrdmlahq_n_s16): Likewise.
9418 (__arm_vqrdmladhxq_s16): Likewise.
9419 (__arm_vqrdmladhq_s16): Likewise.
9420 (__arm_vqdmlsdhxq_s16): Likewise.
9421 (__arm_vqdmlsdhq_s16): Likewise.
9422 (__arm_vqdmlahq_n_s16): Likewise.
9423 (__arm_vqdmladhxq_s16): Likewise.
9424 (__arm_vqdmladhq_s16): Likewise.
9425 (__arm_vmlsdavaxq_s16): Likewise.
9426 (__arm_vmlsdavaq_s16): Likewise.
9427 (__arm_vmlasq_n_s16): Likewise.
9428 (__arm_vmlaq_n_s16): Likewise.
9429 (__arm_vmladavaxq_s16): Likewise.
9430 (__arm_vmladavaq_s16): Likewise.
9431 (__arm_vsriq_n_s16): Likewise.
9432 (__arm_vsliq_n_s16): Likewise.
9433 (__arm_vpselq_u32): Likewise.
9434 (__arm_vpselq_s32): Likewise.
9435 (__arm_vrev64q_m_u32): Likewise.
9436 (__arm_vqrdmlashq_n_u32): Likewise.
9437 (__arm_vqrdmlahq_n_u32): Likewise.
9438 (__arm_vqdmlahq_n_u32): Likewise.
9439 (__arm_vmvnq_m_u32): Likewise.
9440 (__arm_vmlasq_n_u32): Likewise.
9441 (__arm_vmlaq_n_u32): Likewise.
9442 (__arm_vmladavq_p_u32): Likewise.
9443 (__arm_vmladavaq_u32): Likewise.
9444 (__arm_vminvq_p_u32): Likewise.
9445 (__arm_vmaxvq_p_u32): Likewise.
9446 (__arm_vdupq_m_n_u32): Likewise.
9447 (__arm_vcmpneq_m_u32): Likewise.
9448 (__arm_vcmpneq_m_n_u32): Likewise.
9449 (__arm_vcmphiq_m_u32): Likewise.
9450 (__arm_vcmphiq_m_n_u32): Likewise.
9451 (__arm_vcmpeqq_m_u32): Likewise.
9452 (__arm_vcmpeqq_m_n_u32): Likewise.
9453 (__arm_vcmpcsq_m_u32): Likewise.
9454 (__arm_vcmpcsq_m_n_u32): Likewise.
9455 (__arm_vclzq_m_u32): Likewise.
9456 (__arm_vaddvaq_p_u32): Likewise.
9457 (__arm_vsriq_n_u32): Likewise.
9458 (__arm_vsliq_n_u32): Likewise.
9459 (__arm_vshlq_m_r_u32): Likewise.
9460 (__arm_vrshlq_m_n_u32): Likewise.
9461 (__arm_vqshlq_m_r_u32): Likewise.
9462 (__arm_vqrshlq_m_n_u32): Likewise.
9463 (__arm_vminavq_p_s32): Likewise.
9464 (__arm_vminaq_m_s32): Likewise.
9465 (__arm_vmaxavq_p_s32): Likewise.
9466 (__arm_vmaxaq_m_s32): Likewise.
9467 (__arm_vcmpneq_m_s32): Likewise.
9468 (__arm_vcmpneq_m_n_s32): Likewise.
9469 (__arm_vcmpltq_m_s32): Likewise.
9470 (__arm_vcmpltq_m_n_s32): Likewise.
9471 (__arm_vcmpleq_m_s32): Likewise.
9472 (__arm_vcmpleq_m_n_s32): Likewise.
9473 (__arm_vcmpgtq_m_s32): Likewise.
9474 (__arm_vcmpgtq_m_n_s32): Likewise.
9475 (__arm_vcmpgeq_m_s32): Likewise.
9476 (__arm_vcmpgeq_m_n_s32): Likewise.
9477 (__arm_vcmpeqq_m_s32): Likewise.
9478 (__arm_vcmpeqq_m_n_s32): Likewise.
9479 (__arm_vshlq_m_r_s32): Likewise.
9480 (__arm_vrshlq_m_n_s32): Likewise.
9481 (__arm_vrev64q_m_s32): Likewise.
9482 (__arm_vqshlq_m_r_s32): Likewise.
9483 (__arm_vqrshlq_m_n_s32): Likewise.
9484 (__arm_vqnegq_m_s32): Likewise.
9485 (__arm_vqabsq_m_s32): Likewise.
9486 (__arm_vnegq_m_s32): Likewise.
9487 (__arm_vmvnq_m_s32): Likewise.
9488 (__arm_vmlsdavxq_p_s32): Likewise.
9489 (__arm_vmlsdavq_p_s32): Likewise.
9490 (__arm_vmladavxq_p_s32): Likewise.
9491 (__arm_vmladavq_p_s32): Likewise.
9492 (__arm_vminvq_p_s32): Likewise.
9493 (__arm_vmaxvq_p_s32): Likewise.
9494 (__arm_vdupq_m_n_s32): Likewise.
9495 (__arm_vclzq_m_s32): Likewise.
9496 (__arm_vclsq_m_s32): Likewise.
9497 (__arm_vaddvaq_p_s32): Likewise.
9498 (__arm_vabsq_m_s32): Likewise.
9499 (__arm_vqrdmlsdhxq_s32): Likewise.
9500 (__arm_vqrdmlsdhq_s32): Likewise.
9501 (__arm_vqrdmlashq_n_s32): Likewise.
9502 (__arm_vqrdmlahq_n_s32): Likewise.
9503 (__arm_vqrdmladhxq_s32): Likewise.
9504 (__arm_vqrdmladhq_s32): Likewise.
9505 (__arm_vqdmlsdhxq_s32): Likewise.
9506 (__arm_vqdmlsdhq_s32): Likewise.
9507 (__arm_vqdmlahq_n_s32): Likewise.
9508 (__arm_vqdmladhxq_s32): Likewise.
9509 (__arm_vqdmladhq_s32): Likewise.
9510 (__arm_vmlsdavaxq_s32): Likewise.
9511 (__arm_vmlsdavaq_s32): Likewise.
9512 (__arm_vmlasq_n_s32): Likewise.
9513 (__arm_vmlaq_n_s32): Likewise.
9514 (__arm_vmladavaxq_s32): Likewise.
9515 (__arm_vmladavaq_s32): Likewise.
9516 (__arm_vsriq_n_s32): Likewise.
9517 (__arm_vsliq_n_s32): Likewise.
9518 (__arm_vpselq_u64): Likewise.
9519 (__arm_vpselq_s64): Likewise.
9520 (vcmpneq_m_n): Define polymorphic variant.
9521 (vcmpneq_m): Likewise.
9522 (vqrdmlsdhq): Likewise.
9523 (vqrdmlsdhxq): Likewise.
9524 (vqrshlq_m_n): Likewise.
9525 (vqshlq_m_r): Likewise.
9526 (vrev64q_m): Likewise.
9527 (vrshlq_m_n): Likewise.
9528 (vshlq_m_r): Likewise.
9529 (vsliq_n): Likewise.
9530 (vsriq_n): Likewise.
9531 (vqrdmlashq_n): Likewise.
9532 (vqrdmlahq): Likewise.
9533 (vqrdmladhxq): Likewise.
9534 (vqrdmladhq): Likewise.
9535 (vqnegq_m): Likewise.
9536 (vqdmlsdhxq): Likewise.
9537 (vabsq_m): Likewise.
9538 (vclsq_m): Likewise.
9539 (vclzq_m): Likewise.
9540 (vcmpgeq_m): Likewise.
9541 (vcmpgeq_m_n): Likewise.
9542 (vdupq_m_n): Likewise.
9543 (vmaxaq_m): Likewise.
9544 (vmlaq_n): Likewise.
9545 (vmlasq_n): Likewise.
9546 (vmvnq_m): Likewise.
9547 (vnegq_m): Likewise.
9549 (vqdmlahq_n): Likewise.
9550 (vqrdmlahq_n): Likewise.
9551 (vqdmlsdhq): Likewise.
9552 (vqdmladhq): Likewise.
9553 (vqabsq_m): Likewise.
9554 (vminaq_m): Likewise.
9555 (vrmlaldavhaq): Likewise.
9556 (vmlsdavxq_p): Likewise.
9557 (vmlsdavq_p): Likewise.
9558 (vmlsdavaxq): Likewise.
9559 (vmlsdavaq): Likewise.
9560 (vaddvaq_p): Likewise.
9561 (vcmpcsq_m_n): Likewise.
9562 (vcmpcsq_m): Likewise.
9563 (vcmpeqq_m_n): Likewise.
9564 (vcmpeqq_m): Likewise.
9565 (vmladavxq_p): Likewise.
9566 (vmladavq_p): Likewise.
9567 (vmladavaxq): Likewise.
9568 (vmladavaq): Likewise.
9569 (vminvq_p): Likewise.
9570 (vminavq_p): Likewise.
9571 (vmaxvq_p): Likewise.
9572 (vmaxavq_p): Likewise.
9573 (vcmpltq_m_n): Likewise.
9574 (vcmpltq_m): Likewise.
9575 (vcmpleq_m): Likewise.
9576 (vcmpleq_m_n): Likewise.
9577 (vcmphiq_m_n): Likewise.
9578 (vcmphiq_m): Likewise.
9579 (vcmpgtq_m_n): Likewise.
9580 (vcmpgtq_m): Likewise.
9581 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
9583 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
9584 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
9585 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
9586 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
9587 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
9588 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
9589 * config/arm/constraints.md (Rc): Define constraint to check constant is
9590 in the range of 0 to 15.
9591 (Re): Define constraint to check constant is in the range of 0 to 31.
9592 * config/arm/mve.md (VADDVAQ_P): Define iterator.
9593 (VCLZQ_M): Likewise.
9594 (VCMPEQQ_M_N): Likewise.
9595 (VCMPEQQ_M): Likewise.
9596 (VCMPNEQ_M_N): Likewise.
9597 (VCMPNEQ_M): Likewise.
9598 (VDUPQ_M_N): Likewise.
9599 (VMAXVQ_P): Likewise.
9600 (VMINVQ_P): Likewise.
9601 (VMLADAVAQ): Likewise.
9602 (VMLADAVQ_P): Likewise.
9603 (VMLAQ_N): Likewise.
9604 (VMLASQ_N): Likewise.
9605 (VMVNQ_M): Likewise.
9607 (VQDMLAHQ_N): Likewise.
9608 (VQRDMLAHQ_N): Likewise.
9609 (VQRDMLASHQ_N): Likewise.
9610 (VQRSHLQ_M_N): Likewise.
9611 (VQSHLQ_M_R): Likewise.
9612 (VREV64Q_M): Likewise.
9613 (VRSHLQ_M_N): Likewise.
9614 (VSHLQ_M_R): Likewise.
9615 (VSLIQ_N): Likewise.
9616 (VSRIQ_N): Likewise.
9617 (mve_vabsq_m_s<mode>): Define RTL pattern.
9618 (mve_vaddvaq_p_<supf><mode>): Likewise.
9619 (mve_vclsq_m_s<mode>): Likewise.
9620 (mve_vclzq_m_<supf><mode>): Likewise.
9621 (mve_vcmpcsq_m_n_u<mode>): Likewise.
9622 (mve_vcmpcsq_m_u<mode>): Likewise.
9623 (mve_vcmpeqq_m_n_<supf><mode>): Likewise.
9624 (mve_vcmpeqq_m_<supf><mode>): Likewise.
9625 (mve_vcmpgeq_m_n_s<mode>): Likewise.
9626 (mve_vcmpgeq_m_s<mode>): Likewise.
9627 (mve_vcmpgtq_m_n_s<mode>): Likewise.
9628 (mve_vcmpgtq_m_s<mode>): Likewise.
9629 (mve_vcmphiq_m_n_u<mode>): Likewise.
9630 (mve_vcmphiq_m_u<mode>): Likewise.
9631 (mve_vcmpleq_m_n_s<mode>): Likewise.
9632 (mve_vcmpleq_m_s<mode>): Likewise.
9633 (mve_vcmpltq_m_n_s<mode>): Likewise.
9634 (mve_vcmpltq_m_s<mode>): Likewise.
9635 (mve_vcmpneq_m_n_<supf><mode>): Likewise.
9636 (mve_vcmpneq_m_<supf><mode>): Likewise.
9637 (mve_vdupq_m_n_<supf><mode>): Likewise.
9638 (mve_vmaxaq_m_s<mode>): Likewise.
9639 (mve_vmaxavq_p_s<mode>): Likewise.
9640 (mve_vmaxvq_p_<supf><mode>): Likewise.
9641 (mve_vminaq_m_s<mode>): Likewise.
9642 (mve_vminavq_p_s<mode>): Likewise.
9643 (mve_vminvq_p_<supf><mode>): Likewise.
9644 (mve_vmladavaq_<supf><mode>): Likewise.
9645 (mve_vmladavq_p_<supf><mode>): Likewise.
9646 (mve_vmladavxq_p_s<mode>): Likewise.
9647 (mve_vmlaq_n_<supf><mode>): Likewise.
9648 (mve_vmlasq_n_<supf><mode>): Likewise.
9649 (mve_vmlsdavq_p_s<mode>): Likewise.
9650 (mve_vmlsdavxq_p_s<mode>): Likewise.
9651 (mve_vmvnq_m_<supf><mode>): Likewise.
9652 (mve_vnegq_m_s<mode>): Likewise.
9653 (mve_vpselq_<supf><mode>): Likewise.
9654 (mve_vqabsq_m_s<mode>): Likewise.
9655 (mve_vqdmlahq_n_<supf><mode>): Likewise.
9656 (mve_vqnegq_m_s<mode>): Likewise.
9657 (mve_vqrdmladhq_s<mode>): Likewise.
9658 (mve_vqrdmladhxq_s<mode>): Likewise.
9659 (mve_vqrdmlahq_n_<supf><mode>): Likewise.
9660 (mve_vqrdmlashq_n_<supf><mode>): Likewise.
9661 (mve_vqrdmlsdhq_s<mode>): Likewise.
9662 (mve_vqrdmlsdhxq_s<mode>): Likewise.
9663 (mve_vqrshlq_m_n_<supf><mode>): Likewise.
9664 (mve_vqshlq_m_r_<supf><mode>): Likewise.
9665 (mve_vrev64q_m_<supf><mode>): Likewise.
9666 (mve_vrshlq_m_n_<supf><mode>): Likewise.
9667 (mve_vshlq_m_r_<supf><mode>): Likewise.
9668 (mve_vsliq_n_<supf><mode>): Likewise.
9669 (mve_vsriq_n_<supf><mode>): Likewise.
9670 (mve_vqdmlsdhxq_s<mode>): Likewise.
9671 (mve_vqdmlsdhq_s<mode>): Likewise.
9672 (mve_vqdmladhxq_s<mode>): Likewise.
9673 (mve_vqdmladhq_s<mode>): Likewise.
9674 (mve_vmlsdavaxq_s<mode>): Likewise.
9675 (mve_vmlsdavaq_s<mode>): Likewise.
9676 (mve_vmladavaxq_s<mode>): Likewise.
9677 * config/arm/predicates.md (mve_imm_15):Define predicate to check the
9678 matching constraint Rc.
9679 (mve_imm_31): Define predicate to check the matching constraint Re.
9681 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
9683 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
9684 (vec_cmp<mode>di_dup): Likewise.
9685 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
9687 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
9689 * config/gcn/gcn-valu.md (COND_MODE): Delete.
9690 (COND_INT_MODE): Delete.
9691 (cond_op): Add "mult".
9692 (cond_<expander><mode>): Use VEC_ALLREG_MODE.
9693 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
9695 2020-03-18 Richard Biener <rguenther@suse.de>
9698 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using
9699 partial int modes or not mode-precision integer types for
9702 2020-03-18 Jakub Jelinek <jakub@redhat.com>
9704 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
9706 * config/arc/arc.c (frame_stack_add): Likewise.
9707 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
9709 * ipa-predicate.c (predicate::remap_after_inlining): Likewise.
9710 * tree-ssa-strlen.h (handle_printf_call): Likewise.
9711 * tree-ssa-strlen.c (is_strlen_related_p): Likewise.
9712 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
9714 2020-03-18 Duan bo <duanbo3@huawei.com>
9717 * config/aarch64/aarch64.md (ldr_got_tiny): Delete.
9718 (@ldr_got_tiny_<mode>): New pattern.
9719 (ldr_got_tiny_sidi): Likewise.
9720 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
9721 them to handle SYMBOL_TINY_GOT for ILP32.
9723 2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
9725 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
9726 call-preserved for SVE PCS functions.
9727 (aarch64_layout_frame): Cope with up to 12 predicate save slots.
9728 Optimize the case in which there are no following vector save slots.
9730 2020-03-18 Richard Biener <rguenther@suse.de>
9733 * fold-const.c (build_fold_addr_expr): Convert address to
9735 * asan.c (maybe_create_ssa_name): Strip useless type conversions.
9736 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
9737 to build the ADDR_EXPR which we don't really want to simplify.
9738 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
9739 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
9740 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
9741 (simplify_builtin_call): Strip useless type conversions.
9742 * tree-ssa-strlen.c (new_strinfo): Likewise.
9744 2020-03-17 Alexey Neyman <stilor@att.net>
9747 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
9748 the debug level is terse and the declaration is public. Do not
9750 (dwarf2out_decl): Same.
9751 (add_type_attribute): Return immediately if debug level is
9754 2020-03-17 Richard Sandiford <richard.sandiford@arm.com>
9756 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.
9758 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9759 Mihail Ionescu <mihail.ionescu@arm.com>
9760 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9762 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
9763 Define qualifier for ternary operands.
9764 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9765 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9766 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9767 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9768 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
9769 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
9770 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9771 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
9772 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9773 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
9774 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9775 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9776 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
9777 * config/arm/arm_mve.h (vabavq_s8): Define macro.
9778 (vabavq_s16): Likewise.
9779 (vabavq_s32): Likewise.
9780 (vbicq_m_n_s16): Likewise.
9781 (vbicq_m_n_s32): Likewise.
9782 (vbicq_m_n_u16): Likewise.
9783 (vbicq_m_n_u32): Likewise.
9784 (vcmpeqq_m_f16): Likewise.
9785 (vcmpeqq_m_f32): Likewise.
9786 (vcvtaq_m_s16_f16): Likewise.
9787 (vcvtaq_m_u16_f16): Likewise.
9788 (vcvtaq_m_s32_f32): Likewise.
9789 (vcvtaq_m_u32_f32): Likewise.
9790 (vcvtq_m_f16_s16): Likewise.
9791 (vcvtq_m_f16_u16): Likewise.
9792 (vcvtq_m_f32_s32): Likewise.
9793 (vcvtq_m_f32_u32): Likewise.
9794 (vqrshrnbq_n_s16): Likewise.
9795 (vqrshrnbq_n_u16): Likewise.
9796 (vqrshrnbq_n_s32): Likewise.
9797 (vqrshrnbq_n_u32): Likewise.
9798 (vqrshrunbq_n_s16): Likewise.
9799 (vqrshrunbq_n_s32): Likewise.
9800 (vrmlaldavhaq_s32): Likewise.
9801 (vrmlaldavhaq_u32): Likewise.
9802 (vshlcq_s8): Likewise.
9803 (vshlcq_u8): Likewise.
9804 (vshlcq_s16): Likewise.
9805 (vshlcq_u16): Likewise.
9806 (vshlcq_s32): Likewise.
9807 (vshlcq_u32): Likewise.
9808 (vabavq_u8): Likewise.
9809 (vabavq_u16): Likewise.
9810 (vabavq_u32): Likewise.
9811 (__arm_vabavq_s8): Define intrinsic.
9812 (__arm_vabavq_s16): Likewise.
9813 (__arm_vabavq_s32): Likewise.
9814 (__arm_vabavq_u8): Likewise.
9815 (__arm_vabavq_u16): Likewise.
9816 (__arm_vabavq_u32): Likewise.
9817 (__arm_vbicq_m_n_s16): Likewise.
9818 (__arm_vbicq_m_n_s32): Likewise.
9819 (__arm_vbicq_m_n_u16): Likewise.
9820 (__arm_vbicq_m_n_u32): Likewise.
9821 (__arm_vqrshrnbq_n_s16): Likewise.
9822 (__arm_vqrshrnbq_n_u16): Likewise.
9823 (__arm_vqrshrnbq_n_s32): Likewise.
9824 (__arm_vqrshrnbq_n_u32): Likewise.
9825 (__arm_vqrshrunbq_n_s16): Likewise.
9826 (__arm_vqrshrunbq_n_s32): Likewise.
9827 (__arm_vrmlaldavhaq_s32): Likewise.
9828 (__arm_vrmlaldavhaq_u32): Likewise.
9829 (__arm_vshlcq_s8): Likewise.
9830 (__arm_vshlcq_u8): Likewise.
9831 (__arm_vshlcq_s16): Likewise.
9832 (__arm_vshlcq_u16): Likewise.
9833 (__arm_vshlcq_s32): Likewise.
9834 (__arm_vshlcq_u32): Likewise.
9835 (__arm_vcmpeqq_m_f16): Likewise.
9836 (__arm_vcmpeqq_m_f32): Likewise.
9837 (__arm_vcvtaq_m_s16_f16): Likewise.
9838 (__arm_vcvtaq_m_u16_f16): Likewise.
9839 (__arm_vcvtaq_m_s32_f32): Likewise.
9840 (__arm_vcvtaq_m_u32_f32): Likewise.
9841 (__arm_vcvtq_m_f16_s16): Likewise.
9842 (__arm_vcvtq_m_f16_u16): Likewise.
9843 (__arm_vcvtq_m_f32_s32): Likewise.
9844 (__arm_vcvtq_m_f32_u32): Likewise.
9845 (vcvtaq_m): Define polymorphic variant.
9846 (vcvtq_m): Likewise.
9849 (vbicq_m_n): Likewise.
9850 (vqrshrnbq_n): Likewise.
9851 (vqrshrunbq_n): Likewise.
9852 * config/arm/arm_mve_builtins.def
9853 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
9854 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9855 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9856 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9857 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9858 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
9859 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
9860 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9861 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
9862 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9863 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
9864 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9865 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9866 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
9867 * config/arm/mve.md (VBICQ_M_N): Define iterator.
9868 (VCVTAQ_M): Likewise.
9869 (VCVTQ_M_TO_F): Likewise.
9870 (VQRSHRNBQ_N): Likewise.
9873 (VRMLALDAVHAQ): Likewise.
9874 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
9875 (mve_vcmpeqq_m_f<mode>): Likewise.
9876 (mve_vcvtaq_m_<supf><mode>): Likewise.
9877 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
9878 (mve_vqrshrnbq_n_<supf><mode>): Likewise.
9879 (mve_vqrshrunbq_n_s<mode>): Likewise.
9880 (mve_vrmlaldavhaq_<supf>v4si): Likewise.
9881 (mve_vabavq_<supf><mode>): Likewise.
9882 (mve_vshlcq_<supf><mode>): Likewise.
9883 (mve_vshlcq_<supf><mode>): Likewise.
9884 (mve_vshlcq_vec_<supf><mode>): Define RTL expand.
9885 (mve_vshlcq_carry_<supf><mode>): Likewise.
9887 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9888 Mihail Ionescu <mihail.ionescu@arm.com>
9889 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9891 * config/arm/arm_mve.h (vqmovntq_u16): Define macro.
9892 (vqmovnbq_u16): Likewise.
9893 (vmulltq_poly_p8): Likewise.
9894 (vmullbq_poly_p8): Likewise.
9895 (vmovntq_u16): Likewise.
9896 (vmovnbq_u16): Likewise.
9897 (vmlaldavxq_u16): Likewise.
9898 (vmlaldavq_u16): Likewise.
9899 (vqmovuntq_s16): Likewise.
9900 (vqmovunbq_s16): Likewise.
9901 (vshlltq_n_u8): Likewise.
9902 (vshllbq_n_u8): Likewise.
9903 (vorrq_n_u16): Likewise.
9904 (vbicq_n_u16): Likewise.
9905 (vcmpneq_n_f16): Likewise.
9906 (vcmpneq_f16): Likewise.
9907 (vcmpltq_n_f16): Likewise.
9908 (vcmpltq_f16): Likewise.
9909 (vcmpleq_n_f16): Likewise.
9910 (vcmpleq_f16): Likewise.
9911 (vcmpgtq_n_f16): Likewise.
9912 (vcmpgtq_f16): Likewise.
9913 (vcmpgeq_n_f16): Likewise.
9914 (vcmpgeq_f16): Likewise.
9915 (vcmpeqq_n_f16): Likewise.
9916 (vcmpeqq_f16): Likewise.
9917 (vsubq_f16): Likewise.
9918 (vqmovntq_s16): Likewise.
9919 (vqmovnbq_s16): Likewise.
9920 (vqdmulltq_s16): Likewise.
9921 (vqdmulltq_n_s16): Likewise.
9922 (vqdmullbq_s16): Likewise.
9923 (vqdmullbq_n_s16): Likewise.
9924 (vorrq_f16): Likewise.
9925 (vornq_f16): Likewise.
9926 (vmulq_n_f16): Likewise.
9927 (vmulq_f16): Likewise.
9928 (vmovntq_s16): Likewise.
9929 (vmovnbq_s16): Likewise.
9930 (vmlsldavxq_s16): Likewise.
9931 (vmlsldavq_s16): Likewise.
9932 (vmlaldavxq_s16): Likewise.
9933 (vmlaldavq_s16): Likewise.
9934 (vminnmvq_f16): Likewise.
9935 (vminnmq_f16): Likewise.
9936 (vminnmavq_f16): Likewise.
9937 (vminnmaq_f16): Likewise.
9938 (vmaxnmvq_f16): Likewise.
9939 (vmaxnmq_f16): Likewise.
9940 (vmaxnmavq_f16): Likewise.
9941 (vmaxnmaq_f16): Likewise.
9942 (veorq_f16): Likewise.
9943 (vcmulq_rot90_f16): Likewise.
9944 (vcmulq_rot270_f16): Likewise.
9945 (vcmulq_rot180_f16): Likewise.
9946 (vcmulq_f16): Likewise.
9947 (vcaddq_rot90_f16): Likewise.
9948 (vcaddq_rot270_f16): Likewise.
9949 (vbicq_f16): Likewise.
9950 (vandq_f16): Likewise.
9951 (vaddq_n_f16): Likewise.
9952 (vabdq_f16): Likewise.
9953 (vshlltq_n_s8): Likewise.
9954 (vshllbq_n_s8): Likewise.
9955 (vorrq_n_s16): Likewise.
9956 (vbicq_n_s16): Likewise.
9957 (vqmovntq_u32): Likewise.
9958 (vqmovnbq_u32): Likewise.
9959 (vmulltq_poly_p16): Likewise.
9960 (vmullbq_poly_p16): Likewise.
9961 (vmovntq_u32): Likewise.
9962 (vmovnbq_u32): Likewise.
9963 (vmlaldavxq_u32): Likewise.
9964 (vmlaldavq_u32): Likewise.
9965 (vqmovuntq_s32): Likewise.
9966 (vqmovunbq_s32): Likewise.
9967 (vshlltq_n_u16): Likewise.
9968 (vshllbq_n_u16): Likewise.
9969 (vorrq_n_u32): Likewise.
9970 (vbicq_n_u32): Likewise.
9971 (vcmpneq_n_f32): Likewise.
9972 (vcmpneq_f32): Likewise.
9973 (vcmpltq_n_f32): Likewise.
9974 (vcmpltq_f32): Likewise.
9975 (vcmpleq_n_f32): Likewise.
9976 (vcmpleq_f32): Likewise.
9977 (vcmpgtq_n_f32): Likewise.
9978 (vcmpgtq_f32): Likewise.
9979 (vcmpgeq_n_f32): Likewise.
9980 (vcmpgeq_f32): Likewise.
9981 (vcmpeqq_n_f32): Likewise.
9982 (vcmpeqq_f32): Likewise.
9983 (vsubq_f32): Likewise.
9984 (vqmovntq_s32): Likewise.
9985 (vqmovnbq_s32): Likewise.
9986 (vqdmulltq_s32): Likewise.
9987 (vqdmulltq_n_s32): Likewise.
9988 (vqdmullbq_s32): Likewise.
9989 (vqdmullbq_n_s32): Likewise.
9990 (vorrq_f32): Likewise.
9991 (vornq_f32): Likewise.
9992 (vmulq_n_f32): Likewise.
9993 (vmulq_f32): Likewise.
9994 (vmovntq_s32): Likewise.
9995 (vmovnbq_s32): Likewise.
9996 (vmlsldavxq_s32): Likewise.
9997 (vmlsldavq_s32): Likewise.
9998 (vmlaldavxq_s32): Likewise.
9999 (vmlaldavq_s32): Likewise.
10000 (vminnmvq_f32): Likewise.
10001 (vminnmq_f32): Likewise.
10002 (vminnmavq_f32): Likewise.
10003 (vminnmaq_f32): Likewise.
10004 (vmaxnmvq_f32): Likewise.
10005 (vmaxnmq_f32): Likewise.
10006 (vmaxnmavq_f32): Likewise.
10007 (vmaxnmaq_f32): Likewise.
10008 (veorq_f32): Likewise.
10009 (vcmulq_rot90_f32): Likewise.
10010 (vcmulq_rot270_f32): Likewise.
10011 (vcmulq_rot180_f32): Likewise.
10012 (vcmulq_f32): Likewise.
10013 (vcaddq_rot90_f32): Likewise.
10014 (vcaddq_rot270_f32): Likewise.
10015 (vbicq_f32): Likewise.
10016 (vandq_f32): Likewise.
10017 (vaddq_n_f32): Likewise.
10018 (vabdq_f32): Likewise.
10019 (vshlltq_n_s16): Likewise.
10020 (vshllbq_n_s16): Likewise.
10021 (vorrq_n_s32): Likewise.
10022 (vbicq_n_s32): Likewise.
10023 (vrmlaldavhq_u32): Likewise.
10024 (vctp8q_m): Likewise.
10025 (vctp64q_m): Likewise.
10026 (vctp32q_m): Likewise.
10027 (vctp16q_m): Likewise.
10028 (vaddlvaq_u32): Likewise.
10029 (vrmlsldavhxq_s32): Likewise.
10030 (vrmlsldavhq_s32): Likewise.
10031 (vrmlaldavhxq_s32): Likewise.
10032 (vrmlaldavhq_s32): Likewise.
10033 (vcvttq_f16_f32): Likewise.
10034 (vcvtbq_f16_f32): Likewise.
10035 (vaddlvaq_s32): Likewise.
10036 (__arm_vqmovntq_u16): Define intrinsic.
10037 (__arm_vqmovnbq_u16): Likewise.
10038 (__arm_vmulltq_poly_p8): Likewise.
10039 (__arm_vmullbq_poly_p8): Likewise.
10040 (__arm_vmovntq_u16): Likewise.
10041 (__arm_vmovnbq_u16): Likewise.
10042 (__arm_vmlaldavxq_u16): Likewise.
10043 (__arm_vmlaldavq_u16): Likewise.
10044 (__arm_vqmovuntq_s16): Likewise.
10045 (__arm_vqmovunbq_s16): Likewise.
10046 (__arm_vshlltq_n_u8): Likewise.
10047 (__arm_vshllbq_n_u8): Likewise.
10048 (__arm_vorrq_n_u16): Likewise.
10049 (__arm_vbicq_n_u16): Likewise.
10050 (__arm_vcmpneq_n_f16): Likewise.
10051 (__arm_vcmpneq_f16): Likewise.
10052 (__arm_vcmpltq_n_f16): Likewise.
10053 (__arm_vcmpltq_f16): Likewise.
10054 (__arm_vcmpleq_n_f16): Likewise.
10055 (__arm_vcmpleq_f16): Likewise.
10056 (__arm_vcmpgtq_n_f16): Likewise.
10057 (__arm_vcmpgtq_f16): Likewise.
10058 (__arm_vcmpgeq_n_f16): Likewise.
10059 (__arm_vcmpgeq_f16): Likewise.
10060 (__arm_vcmpeqq_n_f16): Likewise.
10061 (__arm_vcmpeqq_f16): Likewise.
10062 (__arm_vsubq_f16): Likewise.
10063 (__arm_vqmovntq_s16): Likewise.
10064 (__arm_vqmovnbq_s16): Likewise.
10065 (__arm_vqdmulltq_s16): Likewise.
10066 (__arm_vqdmulltq_n_s16): Likewise.
10067 (__arm_vqdmullbq_s16): Likewise.
10068 (__arm_vqdmullbq_n_s16): Likewise.
10069 (__arm_vorrq_f16): Likewise.
10070 (__arm_vornq_f16): Likewise.
10071 (__arm_vmulq_n_f16): Likewise.
10072 (__arm_vmulq_f16): Likewise.
10073 (__arm_vmovntq_s16): Likewise.
10074 (__arm_vmovnbq_s16): Likewise.
10075 (__arm_vmlsldavxq_s16): Likewise.
10076 (__arm_vmlsldavq_s16): Likewise.
10077 (__arm_vmlaldavxq_s16): Likewise.
10078 (__arm_vmlaldavq_s16): Likewise.
10079 (__arm_vminnmvq_f16): Likewise.
10080 (__arm_vminnmq_f16): Likewise.
10081 (__arm_vminnmavq_f16): Likewise.
10082 (__arm_vminnmaq_f16): Likewise.
10083 (__arm_vmaxnmvq_f16): Likewise.
10084 (__arm_vmaxnmq_f16): Likewise.
10085 (__arm_vmaxnmavq_f16): Likewise.
10086 (__arm_vmaxnmaq_f16): Likewise.
10087 (__arm_veorq_f16): Likewise.
10088 (__arm_vcmulq_rot90_f16): Likewise.
10089 (__arm_vcmulq_rot270_f16): Likewise.
10090 (__arm_vcmulq_rot180_f16): Likewise.
10091 (__arm_vcmulq_f16): Likewise.
10092 (__arm_vcaddq_rot90_f16): Likewise.
10093 (__arm_vcaddq_rot270_f16): Likewise.
10094 (__arm_vbicq_f16): Likewise.
10095 (__arm_vandq_f16): Likewise.
10096 (__arm_vaddq_n_f16): Likewise.
10097 (__arm_vabdq_f16): Likewise.
10098 (__arm_vshlltq_n_s8): Likewise.
10099 (__arm_vshllbq_n_s8): Likewise.
10100 (__arm_vorrq_n_s16): Likewise.
10101 (__arm_vbicq_n_s16): Likewise.
10102 (__arm_vqmovntq_u32): Likewise.
10103 (__arm_vqmovnbq_u32): Likewise.
10104 (__arm_vmulltq_poly_p16): Likewise.
10105 (__arm_vmullbq_poly_p16): Likewise.
10106 (__arm_vmovntq_u32): Likewise.
10107 (__arm_vmovnbq_u32): Likewise.
10108 (__arm_vmlaldavxq_u32): Likewise.
10109 (__arm_vmlaldavq_u32): Likewise.
10110 (__arm_vqmovuntq_s32): Likewise.
10111 (__arm_vqmovunbq_s32): Likewise.
10112 (__arm_vshlltq_n_u16): Likewise.
10113 (__arm_vshllbq_n_u16): Likewise.
10114 (__arm_vorrq_n_u32): Likewise.
10115 (__arm_vbicq_n_u32): Likewise.
10116 (__arm_vcmpneq_n_f32): Likewise.
10117 (__arm_vcmpneq_f32): Likewise.
10118 (__arm_vcmpltq_n_f32): Likewise.
10119 (__arm_vcmpltq_f32): Likewise.
10120 (__arm_vcmpleq_n_f32): Likewise.
10121 (__arm_vcmpleq_f32): Likewise.
10122 (__arm_vcmpgtq_n_f32): Likewise.
10123 (__arm_vcmpgtq_f32): Likewise.
10124 (__arm_vcmpgeq_n_f32): Likewise.
10125 (__arm_vcmpgeq_f32): Likewise.
10126 (__arm_vcmpeqq_n_f32): Likewise.
10127 (__arm_vcmpeqq_f32): Likewise.
10128 (__arm_vsubq_f32): Likewise.
10129 (__arm_vqmovntq_s32): Likewise.
10130 (__arm_vqmovnbq_s32): Likewise.
10131 (__arm_vqdmulltq_s32): Likewise.
10132 (__arm_vqdmulltq_n_s32): Likewise.
10133 (__arm_vqdmullbq_s32): Likewise.
10134 (__arm_vqdmullbq_n_s32): Likewise.
10135 (__arm_vorrq_f32): Likewise.
10136 (__arm_vornq_f32): Likewise.
10137 (__arm_vmulq_n_f32): Likewise.
10138 (__arm_vmulq_f32): Likewise.
10139 (__arm_vmovntq_s32): Likewise.
10140 (__arm_vmovnbq_s32): Likewise.
10141 (__arm_vmlsldavxq_s32): Likewise.
10142 (__arm_vmlsldavq_s32): Likewise.
10143 (__arm_vmlaldavxq_s32): Likewise.
10144 (__arm_vmlaldavq_s32): Likewise.
10145 (__arm_vminnmvq_f32): Likewise.
10146 (__arm_vminnmq_f32): Likewise.
10147 (__arm_vminnmavq_f32): Likewise.
10148 (__arm_vminnmaq_f32): Likewise.
10149 (__arm_vmaxnmvq_f32): Likewise.
10150 (__arm_vmaxnmq_f32): Likewise.
10151 (__arm_vmaxnmavq_f32): Likewise.
10152 (__arm_vmaxnmaq_f32): Likewise.
10153 (__arm_veorq_f32): Likewise.
10154 (__arm_vcmulq_rot90_f32): Likewise.
10155 (__arm_vcmulq_rot270_f32): Likewise.
10156 (__arm_vcmulq_rot180_f32): Likewise.
10157 (__arm_vcmulq_f32): Likewise.
10158 (__arm_vcaddq_rot90_f32): Likewise.
10159 (__arm_vcaddq_rot270_f32): Likewise.
10160 (__arm_vbicq_f32): Likewise.
10161 (__arm_vandq_f32): Likewise.
10162 (__arm_vaddq_n_f32): Likewise.
10163 (__arm_vabdq_f32): Likewise.
10164 (__arm_vshlltq_n_s16): Likewise.
10165 (__arm_vshllbq_n_s16): Likewise.
10166 (__arm_vorrq_n_s32): Likewise.
10167 (__arm_vbicq_n_s32): Likewise.
10168 (__arm_vrmlaldavhq_u32): Likewise.
10169 (__arm_vctp8q_m): Likewise.
10170 (__arm_vctp64q_m): Likewise.
10171 (__arm_vctp32q_m): Likewise.
10172 (__arm_vctp16q_m): Likewise.
10173 (__arm_vaddlvaq_u32): Likewise.
10174 (__arm_vrmlsldavhxq_s32): Likewise.
10175 (__arm_vrmlsldavhq_s32): Likewise.
10176 (__arm_vrmlaldavhxq_s32): Likewise.
10177 (__arm_vrmlaldavhq_s32): Likewise.
10178 (__arm_vcvttq_f16_f32): Likewise.
10179 (__arm_vcvtbq_f16_f32): Likewise.
10180 (__arm_vaddlvaq_s32): Likewise.
10181 (vst4q): Define polymorphic variant.
10182 (vrndxq): Likewise.
10184 (vrndpq): Likewise.
10185 (vrndnq): Likewise.
10186 (vrndmq): Likewise.
10187 (vrndaq): Likewise.
10188 (vrev64q): Likewise.
10190 (vdupq_n): Likewise.
10192 (vrev32q): Likewise.
10193 (vcvtbq_f32): Likewise.
10194 (vcvttq_f32): Likewise.
10196 (vsubq_n): Likewise.
10197 (vbrsrq_n): Likewise.
10198 (vcvtq_n): Likewise.
10202 (vaddq_n): Likewise.
10206 (vmulq_n): Likewise.
10208 (vcaddq_rot270): Likewise.
10209 (vcmpeqq_n): Likewise.
10210 (vcmpeqq): Likewise.
10211 (vcaddq_rot90): Likewise.
10212 (vcmpgeq_n): Likewise.
10213 (vcmpgeq): Likewise.
10214 (vcmpgtq_n): Likewise.
10215 (vcmpgtq): Likewise.
10216 (vcmpgtq): Likewise.
10217 (vcmpleq_n): Likewise.
10218 (vcmpleq_n): Likewise.
10219 (vcmpleq): Likewise.
10220 (vcmpleq): Likewise.
10221 (vcmpltq_n): Likewise.
10222 (vcmpltq_n): Likewise.
10223 (vcmpltq): Likewise.
10224 (vcmpltq): Likewise.
10225 (vcmpneq_n): Likewise.
10226 (vcmpneq_n): Likewise.
10227 (vcmpneq): Likewise.
10228 (vcmpneq): Likewise.
10229 (vcmulq): Likewise.
10230 (vcmulq): Likewise.
10231 (vcmulq_rot180): Likewise.
10232 (vcmulq_rot180): Likewise.
10233 (vcmulq_rot270): Likewise.
10234 (vcmulq_rot270): Likewise.
10235 (vcmulq_rot90): Likewise.
10236 (vcmulq_rot90): Likewise.
10239 (vmaxnmaq): Likewise.
10240 (vmaxnmaq): Likewise.
10241 (vmaxnmavq): Likewise.
10242 (vmaxnmavq): Likewise.
10243 (vmaxnmq): Likewise.
10244 (vmaxnmq): Likewise.
10245 (vmaxnmvq): Likewise.
10246 (vmaxnmvq): Likewise.
10247 (vminnmaq): Likewise.
10248 (vminnmaq): Likewise.
10249 (vminnmavq): Likewise.
10250 (vminnmavq): Likewise.
10251 (vminnmq): Likewise.
10252 (vminnmq): Likewise.
10253 (vminnmvq): Likewise.
10254 (vminnmvq): Likewise.
10255 (vbicq_n): Likewise.
10256 (vqmovntq): Likewise.
10257 (vqmovntq): Likewise.
10258 (vqmovnbq): Likewise.
10259 (vqmovnbq): Likewise.
10260 (vmulltq_poly): Likewise.
10261 (vmulltq_poly): Likewise.
10262 (vmullbq_poly): Likewise.
10263 (vmullbq_poly): Likewise.
10264 (vmovntq): Likewise.
10265 (vmovntq): Likewise.
10266 (vmovnbq): Likewise.
10267 (vmovnbq): Likewise.
10268 (vmlaldavxq): Likewise.
10269 (vmlaldavxq): Likewise.
10270 (vqmovuntq): Likewise.
10271 (vqmovuntq): Likewise.
10272 (vshlltq_n): Likewise.
10273 (vshlltq_n): Likewise.
10274 (vshllbq_n): Likewise.
10275 (vshllbq_n): Likewise.
10276 (vorrq_n): Likewise.
10277 (vorrq_n): Likewise.
10278 (vmlaldavq): Likewise.
10279 (vmlaldavq): Likewise.
10280 (vqmovunbq): Likewise.
10281 (vqmovunbq): Likewise.
10282 (vqdmulltq_n): Likewise.
10283 (vqdmulltq_n): Likewise.
10284 (vqdmulltq): Likewise.
10285 (vqdmulltq): Likewise.
10286 (vqdmullbq_n): Likewise.
10287 (vqdmullbq_n): Likewise.
10288 (vqdmullbq): Likewise.
10289 (vqdmullbq): Likewise.
10290 (vaddlvaq): Likewise.
10291 (vaddlvaq): Likewise.
10292 (vrmlaldavhq): Likewise.
10293 (vrmlaldavhq): Likewise.
10294 (vrmlaldavhxq): Likewise.
10295 (vrmlaldavhxq): Likewise.
10296 (vrmlsldavhq): Likewise.
10297 (vrmlsldavhq): Likewise.
10298 (vrmlsldavhxq): Likewise.
10299 (vrmlsldavhxq): Likewise.
10300 (vmlsldavxq): Likewise.
10301 (vmlsldavxq): Likewise.
10302 (vmlsldavq): Likewise.
10303 (vmlsldavq): Likewise.
10304 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
10305 (BINOP_NONE_NONE_NONE): Likewise.
10306 (BINOP_UNONE_NONE_NONE): Likewise.
10307 (BINOP_UNONE_UNONE_IMM): Likewise.
10308 (BINOP_UNONE_UNONE_NONE): Likewise.
10309 (BINOP_UNONE_UNONE_UNONE): Likewise.
10310 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
10311 (mve_vaddlvaq_<supf>v4si): Likewise.
10312 (mve_vaddq_n_f<mode>): Likewise.
10313 (mve_vandq_f<mode>): Likewise.
10314 (mve_vbicq_f<mode>): Likewise.
10315 (mve_vbicq_n_<supf><mode>): Likewise.
10316 (mve_vcaddq_rot270_f<mode>): Likewise.
10317 (mve_vcaddq_rot90_f<mode>): Likewise.
10318 (mve_vcmpeqq_f<mode>): Likewise.
10319 (mve_vcmpeqq_n_f<mode>): Likewise.
10320 (mve_vcmpgeq_f<mode>): Likewise.
10321 (mve_vcmpgeq_n_f<mode>): Likewise.
10322 (mve_vcmpgtq_f<mode>): Likewise.
10323 (mve_vcmpgtq_n_f<mode>): Likewise.
10324 (mve_vcmpleq_f<mode>): Likewise.
10325 (mve_vcmpleq_n_f<mode>): Likewise.
10326 (mve_vcmpltq_f<mode>): Likewise.
10327 (mve_vcmpltq_n_f<mode>): Likewise.
10328 (mve_vcmpneq_f<mode>): Likewise.
10329 (mve_vcmpneq_n_f<mode>): Likewise.
10330 (mve_vcmulq_f<mode>): Likewise.
10331 (mve_vcmulq_rot180_f<mode>): Likewise.
10332 (mve_vcmulq_rot270_f<mode>): Likewise.
10333 (mve_vcmulq_rot90_f<mode>): Likewise.
10334 (mve_vctp<mode1>q_mhi): Likewise.
10335 (mve_vcvtbq_f16_f32v8hf): Likewise.
10336 (mve_vcvttq_f16_f32v8hf): Likewise.
10337 (mve_veorq_f<mode>): Likewise.
10338 (mve_vmaxnmaq_f<mode>): Likewise.
10339 (mve_vmaxnmavq_f<mode>): Likewise.
10340 (mve_vmaxnmq_f<mode>): Likewise.
10341 (mve_vmaxnmvq_f<mode>): Likewise.
10342 (mve_vminnmaq_f<mode>): Likewise.
10343 (mve_vminnmavq_f<mode>): Likewise.
10344 (mve_vminnmq_f<mode>): Likewise.
10345 (mve_vminnmvq_f<mode>): Likewise.
10346 (mve_vmlaldavq_<supf><mode>): Likewise.
10347 (mve_vmlaldavxq_<supf><mode>): Likewise.
10348 (mve_vmlsldavq_s<mode>): Likewise.
10349 (mve_vmlsldavxq_s<mode>): Likewise.
10350 (mve_vmovnbq_<supf><mode>): Likewise.
10351 (mve_vmovntq_<supf><mode>): Likewise.
10352 (mve_vmulq_f<mode>): Likewise.
10353 (mve_vmulq_n_f<mode>): Likewise.
10354 (mve_vornq_f<mode>): Likewise.
10355 (mve_vorrq_f<mode>): Likewise.
10356 (mve_vorrq_n_<supf><mode>): Likewise.
10357 (mve_vqdmullbq_n_s<mode>): Likewise.
10358 (mve_vqdmullbq_s<mode>): Likewise.
10359 (mve_vqdmulltq_n_s<mode>): Likewise.
10360 (mve_vqdmulltq_s<mode>): Likewise.
10361 (mve_vqmovnbq_<supf><mode>): Likewise.
10362 (mve_vqmovntq_<supf><mode>): Likewise.
10363 (mve_vqmovunbq_s<mode>): Likewise.
10364 (mve_vqmovuntq_s<mode>): Likewise.
10365 (mve_vrmlaldavhxq_sv4si): Likewise.
10366 (mve_vrmlsldavhq_sv4si): Likewise.
10367 (mve_vrmlsldavhxq_sv4si): Likewise.
10368 (mve_vshllbq_n_<supf><mode>): Likewise.
10369 (mve_vshlltq_n_<supf><mode>): Likewise.
10370 (mve_vsubq_f<mode>): Likewise.
10371 (mve_vmulltq_poly_p<mode>): Likewise.
10372 (mve_vmullbq_poly_p<mode>): Likewise.
10373 (mve_vrmlaldavhq_<supf>v4si): Likewise.
10375 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10376 Mihail Ionescu <mihail.ionescu@arm.com>
10377 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10379 * config/arm/arm_mve.h (vsubq_u8): Define macro.
10380 (vsubq_n_u8): Likewise.
10381 (vrmulhq_u8): Likewise.
10382 (vrhaddq_u8): Likewise.
10383 (vqsubq_u8): Likewise.
10384 (vqsubq_n_u8): Likewise.
10385 (vqaddq_u8): Likewise.
10386 (vqaddq_n_u8): Likewise.
10387 (vorrq_u8): Likewise.
10388 (vornq_u8): Likewise.
10389 (vmulq_u8): Likewise.
10390 (vmulq_n_u8): Likewise.
10391 (vmulltq_int_u8): Likewise.
10392 (vmullbq_int_u8): Likewise.
10393 (vmulhq_u8): Likewise.
10394 (vmladavq_u8): Likewise.
10395 (vminvq_u8): Likewise.
10396 (vminq_u8): Likewise.
10397 (vmaxvq_u8): Likewise.
10398 (vmaxq_u8): Likewise.
10399 (vhsubq_u8): Likewise.
10400 (vhsubq_n_u8): Likewise.
10401 (vhaddq_u8): Likewise.
10402 (vhaddq_n_u8): Likewise.
10403 (veorq_u8): Likewise.
10404 (vcmpneq_n_u8): Likewise.
10405 (vcmphiq_u8): Likewise.
10406 (vcmphiq_n_u8): Likewise.
10407 (vcmpeqq_u8): Likewise.
10408 (vcmpeqq_n_u8): Likewise.
10409 (vcmpcsq_u8): Likewise.
10410 (vcmpcsq_n_u8): Likewise.
10411 (vcaddq_rot90_u8): Likewise.
10412 (vcaddq_rot270_u8): Likewise.
10413 (vbicq_u8): Likewise.
10414 (vandq_u8): Likewise.
10415 (vaddvq_p_u8): Likewise.
10416 (vaddvaq_u8): Likewise.
10417 (vaddq_n_u8): Likewise.
10418 (vabdq_u8): Likewise.
10419 (vshlq_r_u8): Likewise.
10420 (vrshlq_u8): Likewise.
10421 (vrshlq_n_u8): Likewise.
10422 (vqshlq_u8): Likewise.
10423 (vqshlq_r_u8): Likewise.
10424 (vqrshlq_u8): Likewise.
10425 (vqrshlq_n_u8): Likewise.
10426 (vminavq_s8): Likewise.
10427 (vminaq_s8): Likewise.
10428 (vmaxavq_s8): Likewise.
10429 (vmaxaq_s8): Likewise.
10430 (vbrsrq_n_u8): Likewise.
10431 (vshlq_n_u8): Likewise.
10432 (vrshrq_n_u8): Likewise.
10433 (vqshlq_n_u8): Likewise.
10434 (vcmpneq_n_s8): Likewise.
10435 (vcmpltq_s8): Likewise.
10436 (vcmpltq_n_s8): Likewise.
10437 (vcmpleq_s8): Likewise.
10438 (vcmpleq_n_s8): Likewise.
10439 (vcmpgtq_s8): Likewise.
10440 (vcmpgtq_n_s8): Likewise.
10441 (vcmpgeq_s8): Likewise.
10442 (vcmpgeq_n_s8): Likewise.
10443 (vcmpeqq_s8): Likewise.
10444 (vcmpeqq_n_s8): Likewise.
10445 (vqshluq_n_s8): Likewise.
10446 (vaddvq_p_s8): Likewise.
10447 (vsubq_s8): Likewise.
10448 (vsubq_n_s8): Likewise.
10449 (vshlq_r_s8): Likewise.
10450 (vrshlq_s8): Likewise.
10451 (vrshlq_n_s8): Likewise.
10452 (vrmulhq_s8): Likewise.
10453 (vrhaddq_s8): Likewise.
10454 (vqsubq_s8): Likewise.
10455 (vqsubq_n_s8): Likewise.
10456 (vqshlq_s8): Likewise.
10457 (vqshlq_r_s8): Likewise.
10458 (vqrshlq_s8): Likewise.
10459 (vqrshlq_n_s8): Likewise.
10460 (vqrdmulhq_s8): Likewise.
10461 (vqrdmulhq_n_s8): Likewise.
10462 (vqdmulhq_s8): Likewise.
10463 (vqdmulhq_n_s8): Likewise.
10464 (vqaddq_s8): Likewise.
10465 (vqaddq_n_s8): Likewise.
10466 (vorrq_s8): Likewise.
10467 (vornq_s8): Likewise.
10468 (vmulq_s8): Likewise.
10469 (vmulq_n_s8): Likewise.
10470 (vmulltq_int_s8): Likewise.
10471 (vmullbq_int_s8): Likewise.
10472 (vmulhq_s8): Likewise.
10473 (vmlsdavxq_s8): Likewise.
10474 (vmlsdavq_s8): Likewise.
10475 (vmladavxq_s8): Likewise.
10476 (vmladavq_s8): Likewise.
10477 (vminvq_s8): Likewise.
10478 (vminq_s8): Likewise.
10479 (vmaxvq_s8): Likewise.
10480 (vmaxq_s8): Likewise.
10481 (vhsubq_s8): Likewise.
10482 (vhsubq_n_s8): Likewise.
10483 (vhcaddq_rot90_s8): Likewise.
10484 (vhcaddq_rot270_s8): Likewise.
10485 (vhaddq_s8): Likewise.
10486 (vhaddq_n_s8): Likewise.
10487 (veorq_s8): Likewise.
10488 (vcaddq_rot90_s8): Likewise.
10489 (vcaddq_rot270_s8): Likewise.
10490 (vbrsrq_n_s8): Likewise.
10491 (vbicq_s8): Likewise.
10492 (vandq_s8): Likewise.
10493 (vaddvaq_s8): Likewise.
10494 (vaddq_n_s8): Likewise.
10495 (vabdq_s8): Likewise.
10496 (vshlq_n_s8): Likewise.
10497 (vrshrq_n_s8): Likewise.
10498 (vqshlq_n_s8): Likewise.
10499 (vsubq_u16): Likewise.
10500 (vsubq_n_u16): Likewise.
10501 (vrmulhq_u16): Likewise.
10502 (vrhaddq_u16): Likewise.
10503 (vqsubq_u16): Likewise.
10504 (vqsubq_n_u16): Likewise.
10505 (vqaddq_u16): Likewise.
10506 (vqaddq_n_u16): Likewise.
10507 (vorrq_u16): Likewise.
10508 (vornq_u16): Likewise.
10509 (vmulq_u16): Likewise.
10510 (vmulq_n_u16): Likewise.
10511 (vmulltq_int_u16): Likewise.
10512 (vmullbq_int_u16): Likewise.
10513 (vmulhq_u16): Likewise.
10514 (vmladavq_u16): Likewise.
10515 (vminvq_u16): Likewise.
10516 (vminq_u16): Likewise.
10517 (vmaxvq_u16): Likewise.
10518 (vmaxq_u16): Likewise.
10519 (vhsubq_u16): Likewise.
10520 (vhsubq_n_u16): Likewise.
10521 (vhaddq_u16): Likewise.
10522 (vhaddq_n_u16): Likewise.
10523 (veorq_u16): Likewise.
10524 (vcmpneq_n_u16): Likewise.
10525 (vcmphiq_u16): Likewise.
10526 (vcmphiq_n_u16): Likewise.
10527 (vcmpeqq_u16): Likewise.
10528 (vcmpeqq_n_u16): Likewise.
10529 (vcmpcsq_u16): Likewise.
10530 (vcmpcsq_n_u16): Likewise.
10531 (vcaddq_rot90_u16): Likewise.
10532 (vcaddq_rot270_u16): Likewise.
10533 (vbicq_u16): Likewise.
10534 (vandq_u16): Likewise.
10535 (vaddvq_p_u16): Likewise.
10536 (vaddvaq_u16): Likewise.
10537 (vaddq_n_u16): Likewise.
10538 (vabdq_u16): Likewise.
10539 (vshlq_r_u16): Likewise.
10540 (vrshlq_u16): Likewise.
10541 (vrshlq_n_u16): Likewise.
10542 (vqshlq_u16): Likewise.
10543 (vqshlq_r_u16): Likewise.
10544 (vqrshlq_u16): Likewise.
10545 (vqrshlq_n_u16): Likewise.
10546 (vminavq_s16): Likewise.
10547 (vminaq_s16): Likewise.
10548 (vmaxavq_s16): Likewise.
10549 (vmaxaq_s16): Likewise.
10550 (vbrsrq_n_u16): Likewise.
10551 (vshlq_n_u16): Likewise.
10552 (vrshrq_n_u16): Likewise.
10553 (vqshlq_n_u16): Likewise.
10554 (vcmpneq_n_s16): Likewise.
10555 (vcmpltq_s16): Likewise.
10556 (vcmpltq_n_s16): Likewise.
10557 (vcmpleq_s16): Likewise.
10558 (vcmpleq_n_s16): Likewise.
10559 (vcmpgtq_s16): Likewise.
10560 (vcmpgtq_n_s16): Likewise.
10561 (vcmpgeq_s16): Likewise.
10562 (vcmpgeq_n_s16): Likewise.
10563 (vcmpeqq_s16): Likewise.
10564 (vcmpeqq_n_s16): Likewise.
10565 (vqshluq_n_s16): Likewise.
10566 (vaddvq_p_s16): Likewise.
10567 (vsubq_s16): Likewise.
10568 (vsubq_n_s16): Likewise.
10569 (vshlq_r_s16): Likewise.
10570 (vrshlq_s16): Likewise.
10571 (vrshlq_n_s16): Likewise.
10572 (vrmulhq_s16): Likewise.
10573 (vrhaddq_s16): Likewise.
10574 (vqsubq_s16): Likewise.
10575 (vqsubq_n_s16): Likewise.
10576 (vqshlq_s16): Likewise.
10577 (vqshlq_r_s16): Likewise.
10578 (vqrshlq_s16): Likewise.
10579 (vqrshlq_n_s16): Likewise.
10580 (vqrdmulhq_s16): Likewise.
10581 (vqrdmulhq_n_s16): Likewise.
10582 (vqdmulhq_s16): Likewise.
10583 (vqdmulhq_n_s16): Likewise.
10584 (vqaddq_s16): Likewise.
10585 (vqaddq_n_s16): Likewise.
10586 (vorrq_s16): Likewise.
10587 (vornq_s16): Likewise.
10588 (vmulq_s16): Likewise.
10589 (vmulq_n_s16): Likewise.
10590 (vmulltq_int_s16): Likewise.
10591 (vmullbq_int_s16): Likewise.
10592 (vmulhq_s16): Likewise.
10593 (vmlsdavxq_s16): Likewise.
10594 (vmlsdavq_s16): Likewise.
10595 (vmladavxq_s16): Likewise.
10596 (vmladavq_s16): Likewise.
10597 (vminvq_s16): Likewise.
10598 (vminq_s16): Likewise.
10599 (vmaxvq_s16): Likewise.
10600 (vmaxq_s16): Likewise.
10601 (vhsubq_s16): Likewise.
10602 (vhsubq_n_s16): Likewise.
10603 (vhcaddq_rot90_s16): Likewise.
10604 (vhcaddq_rot270_s16): Likewise.
10605 (vhaddq_s16): Likewise.
10606 (vhaddq_n_s16): Likewise.
10607 (veorq_s16): Likewise.
10608 (vcaddq_rot90_s16): Likewise.
10609 (vcaddq_rot270_s16): Likewise.
10610 (vbrsrq_n_s16): Likewise.
10611 (vbicq_s16): Likewise.
10612 (vandq_s16): Likewise.
10613 (vaddvaq_s16): Likewise.
10614 (vaddq_n_s16): Likewise.
10615 (vabdq_s16): Likewise.
10616 (vshlq_n_s16): Likewise.
10617 (vrshrq_n_s16): Likewise.
10618 (vqshlq_n_s16): Likewise.
10619 (vsubq_u32): Likewise.
10620 (vsubq_n_u32): Likewise.
10621 (vrmulhq_u32): Likewise.
10622 (vrhaddq_u32): Likewise.
10623 (vqsubq_u32): Likewise.
10624 (vqsubq_n_u32): Likewise.
10625 (vqaddq_u32): Likewise.
10626 (vqaddq_n_u32): Likewise.
10627 (vorrq_u32): Likewise.
10628 (vornq_u32): Likewise.
10629 (vmulq_u32): Likewise.
10630 (vmulq_n_u32): Likewise.
10631 (vmulltq_int_u32): Likewise.
10632 (vmullbq_int_u32): Likewise.
10633 (vmulhq_u32): Likewise.
10634 (vmladavq_u32): Likewise.
10635 (vminvq_u32): Likewise.
10636 (vminq_u32): Likewise.
10637 (vmaxvq_u32): Likewise.
10638 (vmaxq_u32): Likewise.
10639 (vhsubq_u32): Likewise.
10640 (vhsubq_n_u32): Likewise.
10641 (vhaddq_u32): Likewise.
10642 (vhaddq_n_u32): Likewise.
10643 (veorq_u32): Likewise.
10644 (vcmpneq_n_u32): Likewise.
10645 (vcmphiq_u32): Likewise.
10646 (vcmphiq_n_u32): Likewise.
10647 (vcmpeqq_u32): Likewise.
10648 (vcmpeqq_n_u32): Likewise.
10649 (vcmpcsq_u32): Likewise.
10650 (vcmpcsq_n_u32): Likewise.
10651 (vcaddq_rot90_u32): Likewise.
10652 (vcaddq_rot270_u32): Likewise.
10653 (vbicq_u32): Likewise.
10654 (vandq_u32): Likewise.
10655 (vaddvq_p_u32): Likewise.
10656 (vaddvaq_u32): Likewise.
10657 (vaddq_n_u32): Likewise.
10658 (vabdq_u32): Likewise.
10659 (vshlq_r_u32): Likewise.
10660 (vrshlq_u32): Likewise.
10661 (vrshlq_n_u32): Likewise.
10662 (vqshlq_u32): Likewise.
10663 (vqshlq_r_u32): Likewise.
10664 (vqrshlq_u32): Likewise.
10665 (vqrshlq_n_u32): Likewise.
10666 (vminavq_s32): Likewise.
10667 (vminaq_s32): Likewise.
10668 (vmaxavq_s32): Likewise.
10669 (vmaxaq_s32): Likewise.
10670 (vbrsrq_n_u32): Likewise.
10671 (vshlq_n_u32): Likewise.
10672 (vrshrq_n_u32): Likewise.
10673 (vqshlq_n_u32): Likewise.
10674 (vcmpneq_n_s32): Likewise.
10675 (vcmpltq_s32): Likewise.
10676 (vcmpltq_n_s32): Likewise.
10677 (vcmpleq_s32): Likewise.
10678 (vcmpleq_n_s32): Likewise.
10679 (vcmpgtq_s32): Likewise.
10680 (vcmpgtq_n_s32): Likewise.
10681 (vcmpgeq_s32): Likewise.
10682 (vcmpgeq_n_s32): Likewise.
10683 (vcmpeqq_s32): Likewise.
10684 (vcmpeqq_n_s32): Likewise.
10685 (vqshluq_n_s32): Likewise.
10686 (vaddvq_p_s32): Likewise.
10687 (vsubq_s32): Likewise.
10688 (vsubq_n_s32): Likewise.
10689 (vshlq_r_s32): Likewise.
10690 (vrshlq_s32): Likewise.
10691 (vrshlq_n_s32): Likewise.
10692 (vrmulhq_s32): Likewise.
10693 (vrhaddq_s32): Likewise.
10694 (vqsubq_s32): Likewise.
10695 (vqsubq_n_s32): Likewise.
10696 (vqshlq_s32): Likewise.
10697 (vqshlq_r_s32): Likewise.
10698 (vqrshlq_s32): Likewise.
10699 (vqrshlq_n_s32): Likewise.
10700 (vqrdmulhq_s32): Likewise.
10701 (vqrdmulhq_n_s32): Likewise.
10702 (vqdmulhq_s32): Likewise.
10703 (vqdmulhq_n_s32): Likewise.
10704 (vqaddq_s32): Likewise.
10705 (vqaddq_n_s32): Likewise.
10706 (vorrq_s32): Likewise.
10707 (vornq_s32): Likewise.
10708 (vmulq_s32): Likewise.
10709 (vmulq_n_s32): Likewise.
10710 (vmulltq_int_s32): Likewise.
10711 (vmullbq_int_s32): Likewise.
10712 (vmulhq_s32): Likewise.
10713 (vmlsdavxq_s32): Likewise.
10714 (vmlsdavq_s32): Likewise.
10715 (vmladavxq_s32): Likewise.
10716 (vmladavq_s32): Likewise.
10717 (vminvq_s32): Likewise.
10718 (vminq_s32): Likewise.
10719 (vmaxvq_s32): Likewise.
10720 (vmaxq_s32): Likewise.
10721 (vhsubq_s32): Likewise.
10722 (vhsubq_n_s32): Likewise.
10723 (vhcaddq_rot90_s32): Likewise.
10724 (vhcaddq_rot270_s32): Likewise.
10725 (vhaddq_s32): Likewise.
10726 (vhaddq_n_s32): Likewise.
10727 (veorq_s32): Likewise.
10728 (vcaddq_rot90_s32): Likewise.
10729 (vcaddq_rot270_s32): Likewise.
10730 (vbrsrq_n_s32): Likewise.
10731 (vbicq_s32): Likewise.
10732 (vandq_s32): Likewise.
10733 (vaddvaq_s32): Likewise.
10734 (vaddq_n_s32): Likewise.
10735 (vabdq_s32): Likewise.
10736 (vshlq_n_s32): Likewise.
10737 (vrshrq_n_s32): Likewise.
10738 (vqshlq_n_s32): Likewise.
10739 (__arm_vsubq_u8): Define intrinsic.
10740 (__arm_vsubq_n_u8): Likewise.
10741 (__arm_vrmulhq_u8): Likewise.
10742 (__arm_vrhaddq_u8): Likewise.
10743 (__arm_vqsubq_u8): Likewise.
10744 (__arm_vqsubq_n_u8): Likewise.
10745 (__arm_vqaddq_u8): Likewise.
10746 (__arm_vqaddq_n_u8): Likewise.
10747 (__arm_vorrq_u8): Likewise.
10748 (__arm_vornq_u8): Likewise.
10749 (__arm_vmulq_u8): Likewise.
10750 (__arm_vmulq_n_u8): Likewise.
10751 (__arm_vmulltq_int_u8): Likewise.
10752 (__arm_vmullbq_int_u8): Likewise.
10753 (__arm_vmulhq_u8): Likewise.
10754 (__arm_vmladavq_u8): Likewise.
10755 (__arm_vminvq_u8): Likewise.
10756 (__arm_vminq_u8): Likewise.
10757 (__arm_vmaxvq_u8): Likewise.
10758 (__arm_vmaxq_u8): Likewise.
10759 (__arm_vhsubq_u8): Likewise.
10760 (__arm_vhsubq_n_u8): Likewise.
10761 (__arm_vhaddq_u8): Likewise.
10762 (__arm_vhaddq_n_u8): Likewise.
10763 (__arm_veorq_u8): Likewise.
10764 (__arm_vcmpneq_n_u8): Likewise.
10765 (__arm_vcmphiq_u8): Likewise.
10766 (__arm_vcmphiq_n_u8): Likewise.
10767 (__arm_vcmpeqq_u8): Likewise.
10768 (__arm_vcmpeqq_n_u8): Likewise.
10769 (__arm_vcmpcsq_u8): Likewise.
10770 (__arm_vcmpcsq_n_u8): Likewise.
10771 (__arm_vcaddq_rot90_u8): Likewise.
10772 (__arm_vcaddq_rot270_u8): Likewise.
10773 (__arm_vbicq_u8): Likewise.
10774 (__arm_vandq_u8): Likewise.
10775 (__arm_vaddvq_p_u8): Likewise.
10776 (__arm_vaddvaq_u8): Likewise.
10777 (__arm_vaddq_n_u8): Likewise.
10778 (__arm_vabdq_u8): Likewise.
10779 (__arm_vshlq_r_u8): Likewise.
10780 (__arm_vrshlq_u8): Likewise.
10781 (__arm_vrshlq_n_u8): Likewise.
10782 (__arm_vqshlq_u8): Likewise.
10783 (__arm_vqshlq_r_u8): Likewise.
10784 (__arm_vqrshlq_u8): Likewise.
10785 (__arm_vqrshlq_n_u8): Likewise.
10786 (__arm_vminavq_s8): Likewise.
10787 (__arm_vminaq_s8): Likewise.
10788 (__arm_vmaxavq_s8): Likewise.
10789 (__arm_vmaxaq_s8): Likewise.
10790 (__arm_vbrsrq_n_u8): Likewise.
10791 (__arm_vshlq_n_u8): Likewise.
10792 (__arm_vrshrq_n_u8): Likewise.
10793 (__arm_vqshlq_n_u8): Likewise.
10794 (__arm_vcmpneq_n_s8): Likewise.
10795 (__arm_vcmpltq_s8): Likewise.
10796 (__arm_vcmpltq_n_s8): Likewise.
10797 (__arm_vcmpleq_s8): Likewise.
10798 (__arm_vcmpleq_n_s8): Likewise.
10799 (__arm_vcmpgtq_s8): Likewise.
10800 (__arm_vcmpgtq_n_s8): Likewise.
10801 (__arm_vcmpgeq_s8): Likewise.
10802 (__arm_vcmpgeq_n_s8): Likewise.
10803 (__arm_vcmpeqq_s8): Likewise.
10804 (__arm_vcmpeqq_n_s8): Likewise.
10805 (__arm_vqshluq_n_s8): Likewise.
10806 (__arm_vaddvq_p_s8): Likewise.
10807 (__arm_vsubq_s8): Likewise.
10808 (__arm_vsubq_n_s8): Likewise.
10809 (__arm_vshlq_r_s8): Likewise.
10810 (__arm_vrshlq_s8): Likewise.
10811 (__arm_vrshlq_n_s8): Likewise.
10812 (__arm_vrmulhq_s8): Likewise.
10813 (__arm_vrhaddq_s8): Likewise.
10814 (__arm_vqsubq_s8): Likewise.
10815 (__arm_vqsubq_n_s8): Likewise.
10816 (__arm_vqshlq_s8): Likewise.
10817 (__arm_vqshlq_r_s8): Likewise.
10818 (__arm_vqrshlq_s8): Likewise.
10819 (__arm_vqrshlq_n_s8): Likewise.
10820 (__arm_vqrdmulhq_s8): Likewise.
10821 (__arm_vqrdmulhq_n_s8): Likewise.
10822 (__arm_vqdmulhq_s8): Likewise.
10823 (__arm_vqdmulhq_n_s8): Likewise.
10824 (__arm_vqaddq_s8): Likewise.
10825 (__arm_vqaddq_n_s8): Likewise.
10826 (__arm_vorrq_s8): Likewise.
10827 (__arm_vornq_s8): Likewise.
10828 (__arm_vmulq_s8): Likewise.
10829 (__arm_vmulq_n_s8): Likewise.
10830 (__arm_vmulltq_int_s8): Likewise.
10831 (__arm_vmullbq_int_s8): Likewise.
10832 (__arm_vmulhq_s8): Likewise.
10833 (__arm_vmlsdavxq_s8): Likewise.
10834 (__arm_vmlsdavq_s8): Likewise.
10835 (__arm_vmladavxq_s8): Likewise.
10836 (__arm_vmladavq_s8): Likewise.
10837 (__arm_vminvq_s8): Likewise.
10838 (__arm_vminq_s8): Likewise.
10839 (__arm_vmaxvq_s8): Likewise.
10840 (__arm_vmaxq_s8): Likewise.
10841 (__arm_vhsubq_s8): Likewise.
10842 (__arm_vhsubq_n_s8): Likewise.
10843 (__arm_vhcaddq_rot90_s8): Likewise.
10844 (__arm_vhcaddq_rot270_s8): Likewise.
10845 (__arm_vhaddq_s8): Likewise.
10846 (__arm_vhaddq_n_s8): Likewise.
10847 (__arm_veorq_s8): Likewise.
10848 (__arm_vcaddq_rot90_s8): Likewise.
10849 (__arm_vcaddq_rot270_s8): Likewise.
10850 (__arm_vbrsrq_n_s8): Likewise.
10851 (__arm_vbicq_s8): Likewise.
10852 (__arm_vandq_s8): Likewise.
10853 (__arm_vaddvaq_s8): Likewise.
10854 (__arm_vaddq_n_s8): Likewise.
10855 (__arm_vabdq_s8): Likewise.
10856 (__arm_vshlq_n_s8): Likewise.
10857 (__arm_vrshrq_n_s8): Likewise.
10858 (__arm_vqshlq_n_s8): Likewise.
10859 (__arm_vsubq_u16): Likewise.
10860 (__arm_vsubq_n_u16): Likewise.
10861 (__arm_vrmulhq_u16): Likewise.
10862 (__arm_vrhaddq_u16): Likewise.
10863 (__arm_vqsubq_u16): Likewise.
10864 (__arm_vqsubq_n_u16): Likewise.
10865 (__arm_vqaddq_u16): Likewise.
10866 (__arm_vqaddq_n_u16): Likewise.
10867 (__arm_vorrq_u16): Likewise.
10868 (__arm_vornq_u16): Likewise.
10869 (__arm_vmulq_u16): Likewise.
10870 (__arm_vmulq_n_u16): Likewise.
10871 (__arm_vmulltq_int_u16): Likewise.
10872 (__arm_vmullbq_int_u16): Likewise.
10873 (__arm_vmulhq_u16): Likewise.
10874 (__arm_vmladavq_u16): Likewise.
10875 (__arm_vminvq_u16): Likewise.
10876 (__arm_vminq_u16): Likewise.
10877 (__arm_vmaxvq_u16): Likewise.
10878 (__arm_vmaxq_u16): Likewise.
10879 (__arm_vhsubq_u16): Likewise.
10880 (__arm_vhsubq_n_u16): Likewise.
10881 (__arm_vhaddq_u16): Likewise.
10882 (__arm_vhaddq_n_u16): Likewise.
10883 (__arm_veorq_u16): Likewise.
10884 (__arm_vcmpneq_n_u16): Likewise.
10885 (__arm_vcmphiq_u16): Likewise.
10886 (__arm_vcmphiq_n_u16): Likewise.
10887 (__arm_vcmpeqq_u16): Likewise.
10888 (__arm_vcmpeqq_n_u16): Likewise.
10889 (__arm_vcmpcsq_u16): Likewise.
10890 (__arm_vcmpcsq_n_u16): Likewise.
10891 (__arm_vcaddq_rot90_u16): Likewise.
10892 (__arm_vcaddq_rot270_u16): Likewise.
10893 (__arm_vbicq_u16): Likewise.
10894 (__arm_vandq_u16): Likewise.
10895 (__arm_vaddvq_p_u16): Likewise.
10896 (__arm_vaddvaq_u16): Likewise.
10897 (__arm_vaddq_n_u16): Likewise.
10898 (__arm_vabdq_u16): Likewise.
10899 (__arm_vshlq_r_u16): Likewise.
10900 (__arm_vrshlq_u16): Likewise.
10901 (__arm_vrshlq_n_u16): Likewise.
10902 (__arm_vqshlq_u16): Likewise.
10903 (__arm_vqshlq_r_u16): Likewise.
10904 (__arm_vqrshlq_u16): Likewise.
10905 (__arm_vqrshlq_n_u16): Likewise.
10906 (__arm_vminavq_s16): Likewise.
10907 (__arm_vminaq_s16): Likewise.
10908 (__arm_vmaxavq_s16): Likewise.
10909 (__arm_vmaxaq_s16): Likewise.
10910 (__arm_vbrsrq_n_u16): Likewise.
10911 (__arm_vshlq_n_u16): Likewise.
10912 (__arm_vrshrq_n_u16): Likewise.
10913 (__arm_vqshlq_n_u16): Likewise.
10914 (__arm_vcmpneq_n_s16): Likewise.
10915 (__arm_vcmpltq_s16): Likewise.
10916 (__arm_vcmpltq_n_s16): Likewise.
10917 (__arm_vcmpleq_s16): Likewise.
10918 (__arm_vcmpleq_n_s16): Likewise.
10919 (__arm_vcmpgtq_s16): Likewise.
10920 (__arm_vcmpgtq_n_s16): Likewise.
10921 (__arm_vcmpgeq_s16): Likewise.
10922 (__arm_vcmpgeq_n_s16): Likewise.
10923 (__arm_vcmpeqq_s16): Likewise.
10924 (__arm_vcmpeqq_n_s16): Likewise.
10925 (__arm_vqshluq_n_s16): Likewise.
10926 (__arm_vaddvq_p_s16): Likewise.
10927 (__arm_vsubq_s16): Likewise.
10928 (__arm_vsubq_n_s16): Likewise.
10929 (__arm_vshlq_r_s16): Likewise.
10930 (__arm_vrshlq_s16): Likewise.
10931 (__arm_vrshlq_n_s16): Likewise.
10932 (__arm_vrmulhq_s16): Likewise.
10933 (__arm_vrhaddq_s16): Likewise.
10934 (__arm_vqsubq_s16): Likewise.
10935 (__arm_vqsubq_n_s16): Likewise.
10936 (__arm_vqshlq_s16): Likewise.
10937 (__arm_vqshlq_r_s16): Likewise.
10938 (__arm_vqrshlq_s16): Likewise.
10939 (__arm_vqrshlq_n_s16): Likewise.
10940 (__arm_vqrdmulhq_s16): Likewise.
10941 (__arm_vqrdmulhq_n_s16): Likewise.
10942 (__arm_vqdmulhq_s16): Likewise.
10943 (__arm_vqdmulhq_n_s16): Likewise.
10944 (__arm_vqaddq_s16): Likewise.
10945 (__arm_vqaddq_n_s16): Likewise.
10946 (__arm_vorrq_s16): Likewise.
10947 (__arm_vornq_s16): Likewise.
10948 (__arm_vmulq_s16): Likewise.
10949 (__arm_vmulq_n_s16): Likewise.
10950 (__arm_vmulltq_int_s16): Likewise.
10951 (__arm_vmullbq_int_s16): Likewise.
10952 (__arm_vmulhq_s16): Likewise.
10953 (__arm_vmlsdavxq_s16): Likewise.
10954 (__arm_vmlsdavq_s16): Likewise.
10955 (__arm_vmladavxq_s16): Likewise.
10956 (__arm_vmladavq_s16): Likewise.
10957 (__arm_vminvq_s16): Likewise.
10958 (__arm_vminq_s16): Likewise.
10959 (__arm_vmaxvq_s16): Likewise.
10960 (__arm_vmaxq_s16): Likewise.
10961 (__arm_vhsubq_s16): Likewise.
10962 (__arm_vhsubq_n_s16): Likewise.
10963 (__arm_vhcaddq_rot90_s16): Likewise.
10964 (__arm_vhcaddq_rot270_s16): Likewise.
10965 (__arm_vhaddq_s16): Likewise.
10966 (__arm_vhaddq_n_s16): Likewise.
10967 (__arm_veorq_s16): Likewise.
10968 (__arm_vcaddq_rot90_s16): Likewise.
10969 (__arm_vcaddq_rot270_s16): Likewise.
10970 (__arm_vbrsrq_n_s16): Likewise.
10971 (__arm_vbicq_s16): Likewise.
10972 (__arm_vandq_s16): Likewise.
10973 (__arm_vaddvaq_s16): Likewise.
10974 (__arm_vaddq_n_s16): Likewise.
10975 (__arm_vabdq_s16): Likewise.
10976 (__arm_vshlq_n_s16): Likewise.
10977 (__arm_vrshrq_n_s16): Likewise.
10978 (__arm_vqshlq_n_s16): Likewise.
10979 (__arm_vsubq_u32): Likewise.
10980 (__arm_vsubq_n_u32): Likewise.
10981 (__arm_vrmulhq_u32): Likewise.
10982 (__arm_vrhaddq_u32): Likewise.
10983 (__arm_vqsubq_u32): Likewise.
10984 (__arm_vqsubq_n_u32): Likewise.
10985 (__arm_vqaddq_u32): Likewise.
10986 (__arm_vqaddq_n_u32): Likewise.
10987 (__arm_vorrq_u32): Likewise.
10988 (__arm_vornq_u32): Likewise.
10989 (__arm_vmulq_u32): Likewise.
10990 (__arm_vmulq_n_u32): Likewise.
10991 (__arm_vmulltq_int_u32): Likewise.
10992 (__arm_vmullbq_int_u32): Likewise.
10993 (__arm_vmulhq_u32): Likewise.
10994 (__arm_vmladavq_u32): Likewise.
10995 (__arm_vminvq_u32): Likewise.
10996 (__arm_vminq_u32): Likewise.
10997 (__arm_vmaxvq_u32): Likewise.
10998 (__arm_vmaxq_u32): Likewise.
10999 (__arm_vhsubq_u32): Likewise.
11000 (__arm_vhsubq_n_u32): Likewise.
11001 (__arm_vhaddq_u32): Likewise.
11002 (__arm_vhaddq_n_u32): Likewise.
11003 (__arm_veorq_u32): Likewise.
11004 (__arm_vcmpneq_n_u32): Likewise.
11005 (__arm_vcmphiq_u32): Likewise.
11006 (__arm_vcmphiq_n_u32): Likewise.
11007 (__arm_vcmpeqq_u32): Likewise.
11008 (__arm_vcmpeqq_n_u32): Likewise.
11009 (__arm_vcmpcsq_u32): Likewise.
11010 (__arm_vcmpcsq_n_u32): Likewise.
11011 (__arm_vcaddq_rot90_u32): Likewise.
11012 (__arm_vcaddq_rot270_u32): Likewise.
11013 (__arm_vbicq_u32): Likewise.
11014 (__arm_vandq_u32): Likewise.
11015 (__arm_vaddvq_p_u32): Likewise.
11016 (__arm_vaddvaq_u32): Likewise.
11017 (__arm_vaddq_n_u32): Likewise.
11018 (__arm_vabdq_u32): Likewise.
11019 (__arm_vshlq_r_u32): Likewise.
11020 (__arm_vrshlq_u32): Likewise.
11021 (__arm_vrshlq_n_u32): Likewise.
11022 (__arm_vqshlq_u32): Likewise.
11023 (__arm_vqshlq_r_u32): Likewise.
11024 (__arm_vqrshlq_u32): Likewise.
11025 (__arm_vqrshlq_n_u32): Likewise.
11026 (__arm_vminavq_s32): Likewise.
11027 (__arm_vminaq_s32): Likewise.
11028 (__arm_vmaxavq_s32): Likewise.
11029 (__arm_vmaxaq_s32): Likewise.
11030 (__arm_vbrsrq_n_u32): Likewise.
11031 (__arm_vshlq_n_u32): Likewise.
11032 (__arm_vrshrq_n_u32): Likewise.
11033 (__arm_vqshlq_n_u32): Likewise.
11034 (__arm_vcmpneq_n_s32): Likewise.
11035 (__arm_vcmpltq_s32): Likewise.
11036 (__arm_vcmpltq_n_s32): Likewise.
11037 (__arm_vcmpleq_s32): Likewise.
11038 (__arm_vcmpleq_n_s32): Likewise.
11039 (__arm_vcmpgtq_s32): Likewise.
11040 (__arm_vcmpgtq_n_s32): Likewise.
11041 (__arm_vcmpgeq_s32): Likewise.
11042 (__arm_vcmpgeq_n_s32): Likewise.
11043 (__arm_vcmpeqq_s32): Likewise.
11044 (__arm_vcmpeqq_n_s32): Likewise.
11045 (__arm_vqshluq_n_s32): Likewise.
11046 (__arm_vaddvq_p_s32): Likewise.
11047 (__arm_vsubq_s32): Likewise.
11048 (__arm_vsubq_n_s32): Likewise.
11049 (__arm_vshlq_r_s32): Likewise.
11050 (__arm_vrshlq_s32): Likewise.
11051 (__arm_vrshlq_n_s32): Likewise.
11052 (__arm_vrmulhq_s32): Likewise.
11053 (__arm_vrhaddq_s32): Likewise.
11054 (__arm_vqsubq_s32): Likewise.
11055 (__arm_vqsubq_n_s32): Likewise.
11056 (__arm_vqshlq_s32): Likewise.
11057 (__arm_vqshlq_r_s32): Likewise.
11058 (__arm_vqrshlq_s32): Likewise.
11059 (__arm_vqrshlq_n_s32): Likewise.
11060 (__arm_vqrdmulhq_s32): Likewise.
11061 (__arm_vqrdmulhq_n_s32): Likewise.
11062 (__arm_vqdmulhq_s32): Likewise.
11063 (__arm_vqdmulhq_n_s32): Likewise.
11064 (__arm_vqaddq_s32): Likewise.
11065 (__arm_vqaddq_n_s32): Likewise.
11066 (__arm_vorrq_s32): Likewise.
11067 (__arm_vornq_s32): Likewise.
11068 (__arm_vmulq_s32): Likewise.
11069 (__arm_vmulq_n_s32): Likewise.
11070 (__arm_vmulltq_int_s32): Likewise.
11071 (__arm_vmullbq_int_s32): Likewise.
11072 (__arm_vmulhq_s32): Likewise.
11073 (__arm_vmlsdavxq_s32): Likewise.
11074 (__arm_vmlsdavq_s32): Likewise.
11075 (__arm_vmladavxq_s32): Likewise.
11076 (__arm_vmladavq_s32): Likewise.
11077 (__arm_vminvq_s32): Likewise.
11078 (__arm_vminq_s32): Likewise.
11079 (__arm_vmaxvq_s32): Likewise.
11080 (__arm_vmaxq_s32): Likewise.
11081 (__arm_vhsubq_s32): Likewise.
11082 (__arm_vhsubq_n_s32): Likewise.
11083 (__arm_vhcaddq_rot90_s32): Likewise.
11084 (__arm_vhcaddq_rot270_s32): Likewise.
11085 (__arm_vhaddq_s32): Likewise.
11086 (__arm_vhaddq_n_s32): Likewise.
11087 (__arm_veorq_s32): Likewise.
11088 (__arm_vcaddq_rot90_s32): Likewise.
11089 (__arm_vcaddq_rot270_s32): Likewise.
11090 (__arm_vbrsrq_n_s32): Likewise.
11091 (__arm_vbicq_s32): Likewise.
11092 (__arm_vandq_s32): Likewise.
11093 (__arm_vaddvaq_s32): Likewise.
11094 (__arm_vaddq_n_s32): Likewise.
11095 (__arm_vabdq_s32): Likewise.
11096 (__arm_vshlq_n_s32): Likewise.
11097 (__arm_vrshrq_n_s32): Likewise.
11098 (__arm_vqshlq_n_s32): Likewise.
11099 (vsubq): Define polymorphic variant.
11100 (vsubq_n): Likewise.
11101 (vshlq_r): Likewise.
11102 (vrshlq_n): Likewise.
11103 (vrshlq): Likewise.
11104 (vrmulhq): Likewise.
11105 (vrhaddq): Likewise.
11106 (vqsubq_n): Likewise.
11107 (vqsubq): Likewise.
11108 (vqshlq): Likewise.
11109 (vqshlq_r): Likewise.
11110 (vqshluq): Likewise.
11111 (vrshrq_n): Likewise.
11112 (vshlq_n): Likewise.
11113 (vqshluq_n): Likewise.
11114 (vqshlq_n): Likewise.
11115 (vqrshlq_n): Likewise.
11116 (vqrshlq): Likewise.
11117 (vqrdmulhq_n): Likewise.
11118 (vqrdmulhq): Likewise.
11119 (vqdmulhq_n): Likewise.
11120 (vqdmulhq): Likewise.
11121 (vqaddq_n): Likewise.
11122 (vqaddq): Likewise.
11123 (vorrq_n): Likewise.
11126 (vmulq_n): Likewise.
11128 (vmulltq_int): Likewise.
11129 (vmullbq_int): Likewise.
11130 (vmulhq): Likewise.
11132 (vminaq): Likewise.
11134 (vmaxaq): Likewise.
11135 (vhsubq_n): Likewise.
11136 (vhsubq): Likewise.
11137 (vhcaddq_rot90): Likewise.
11138 (vhcaddq_rot270): Likewise.
11139 (vhaddq_n): Likewise.
11140 (vhaddq): Likewise.
11142 (vcaddq_rot90): Likewise.
11143 (vcaddq_rot270): Likewise.
11144 (vbrsrq_n): Likewise.
11145 (vbicq_n): Likewise.
11148 (vaddq_n): Likewise.
11151 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
11152 (BINOP_NONE_NONE_NONE): Likewise.
11153 (BINOP_NONE_NONE_UNONE): Likewise.
11154 (BINOP_UNONE_NONE_IMM): Likewise.
11155 (BINOP_UNONE_NONE_NONE): Likewise.
11156 (BINOP_UNONE_UNONE_IMM): Likewise.
11157 (BINOP_UNONE_UNONE_NONE): Likewise.
11158 (BINOP_UNONE_UNONE_UNONE): Likewise.
11159 * config/arm/constraints.md (Ra): Define constraint to check constant is
11160 in the range of 0 to 7.
11161 (Rg): Define constriant to check the constant is one among 1, 2, 4
11163 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
11164 (mve_vaddq_n_<supf>): Likewise.
11165 (mve_vaddvaq_<supf>): Likewise.
11166 (mve_vaddvq_p_<supf>): Likewise.
11167 (mve_vandq_<supf>): Likewise.
11168 (mve_vbicq_<supf>): Likewise.
11169 (mve_vbrsrq_n_<supf>): Likewise.
11170 (mve_vcaddq_rot270_<supf>): Likewise.
11171 (mve_vcaddq_rot90_<supf>): Likewise.
11172 (mve_vcmpcsq_n_u): Likewise.
11173 (mve_vcmpcsq_u): Likewise.
11174 (mve_vcmpeqq_n_<supf>): Likewise.
11175 (mve_vcmpeqq_<supf>): Likewise.
11176 (mve_vcmpgeq_n_s): Likewise.
11177 (mve_vcmpgeq_s): Likewise.
11178 (mve_vcmpgtq_n_s): Likewise.
11179 (mve_vcmpgtq_s): Likewise.
11180 (mve_vcmphiq_n_u): Likewise.
11181 (mve_vcmphiq_u): Likewise.
11182 (mve_vcmpleq_n_s): Likewise.
11183 (mve_vcmpleq_s): Likewise.
11184 (mve_vcmpltq_n_s): Likewise.
11185 (mve_vcmpltq_s): Likewise.
11186 (mve_vcmpneq_n_<supf>): Likewise.
11187 (mve_vddupq_n_u): Likewise.
11188 (mve_veorq_<supf>): Likewise.
11189 (mve_vhaddq_n_<supf>): Likewise.
11190 (mve_vhaddq_<supf>): Likewise.
11191 (mve_vhcaddq_rot270_s): Likewise.
11192 (mve_vhcaddq_rot90_s): Likewise.
11193 (mve_vhsubq_n_<supf>): Likewise.
11194 (mve_vhsubq_<supf>): Likewise.
11195 (mve_vidupq_n_u): Likewise.
11196 (mve_vmaxaq_s): Likewise.
11197 (mve_vmaxavq_s): Likewise.
11198 (mve_vmaxq_<supf>): Likewise.
11199 (mve_vmaxvq_<supf>): Likewise.
11200 (mve_vminaq_s): Likewise.
11201 (mve_vminavq_s): Likewise.
11202 (mve_vminq_<supf>): Likewise.
11203 (mve_vminvq_<supf>): Likewise.
11204 (mve_vmladavq_<supf>): Likewise.
11205 (mve_vmladavxq_s): Likewise.
11206 (mve_vmlsdavq_s): Likewise.
11207 (mve_vmlsdavxq_s): Likewise.
11208 (mve_vmulhq_<supf>): Likewise.
11209 (mve_vmullbq_int_<supf>): Likewise.
11210 (mve_vmulltq_int_<supf>): Likewise.
11211 (mve_vmulq_n_<supf>): Likewise.
11212 (mve_vmulq_<supf>): Likewise.
11213 (mve_vornq_<supf>): Likewise.
11214 (mve_vorrq_<supf>): Likewise.
11215 (mve_vqaddq_n_<supf>): Likewise.
11216 (mve_vqaddq_<supf>): Likewise.
11217 (mve_vqdmulhq_n_s): Likewise.
11218 (mve_vqdmulhq_s): Likewise.
11219 (mve_vqrdmulhq_n_s): Likewise.
11220 (mve_vqrdmulhq_s): Likewise.
11221 (mve_vqrshlq_n_<supf>): Likewise.
11222 (mve_vqrshlq_<supf>): Likewise.
11223 (mve_vqshlq_n_<supf>): Likewise.
11224 (mve_vqshlq_r_<supf>): Likewise.
11225 (mve_vqshlq_<supf>): Likewise.
11226 (mve_vqshluq_n_s): Likewise.
11227 (mve_vqsubq_n_<supf>): Likewise.
11228 (mve_vqsubq_<supf>): Likewise.
11229 (mve_vrhaddq_<supf>): Likewise.
11230 (mve_vrmulhq_<supf>): Likewise.
11231 (mve_vrshlq_n_<supf>): Likewise.
11232 (mve_vrshlq_<supf>): Likewise.
11233 (mve_vrshrq_n_<supf>): Likewise.
11234 (mve_vshlq_n_<supf>): Likewise.
11235 (mve_vshlq_r_<supf>): Likewise.
11236 (mve_vsubq_n_<supf>): Likewise.
11237 (mve_vsubq_<supf>): Likewise.
11238 * config/arm/predicates.md (mve_imm_7): Define predicate to check
11239 the matching constraint Ra.
11240 (mve_imm_selective_upto_8): Define predicate to check the matching
11243 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11244 Mihail Ionescu <mihail.ionescu@arm.com>
11245 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11247 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
11248 qualifier for binary operands.
11249 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11250 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11251 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
11252 (vaddlvq_p_u32): Likewise.
11253 (vcmpneq_s8): Likewise.
11254 (vcmpneq_s16): Likewise.
11255 (vcmpneq_s32): Likewise.
11256 (vcmpneq_u8): Likewise.
11257 (vcmpneq_u16): Likewise.
11258 (vcmpneq_u32): Likewise.
11259 (vshlq_s8): Likewise.
11260 (vshlq_s16): Likewise.
11261 (vshlq_s32): Likewise.
11262 (vshlq_u8): Likewise.
11263 (vshlq_u16): Likewise.
11264 (vshlq_u32): Likewise.
11265 (__arm_vaddlvq_p_s32): Define intrinsic.
11266 (__arm_vaddlvq_p_u32): Likewise.
11267 (__arm_vcmpneq_s8): Likewise.
11268 (__arm_vcmpneq_s16): Likewise.
11269 (__arm_vcmpneq_s32): Likewise.
11270 (__arm_vcmpneq_u8): Likewise.
11271 (__arm_vcmpneq_u16): Likewise.
11272 (__arm_vcmpneq_u32): Likewise.
11273 (__arm_vshlq_s8): Likewise.
11274 (__arm_vshlq_s16): Likewise.
11275 (__arm_vshlq_s32): Likewise.
11276 (__arm_vshlq_u8): Likewise.
11277 (__arm_vshlq_u16): Likewise.
11278 (__arm_vshlq_u32): Likewise.
11279 (vaddlvq_p): Define polymorphic variant.
11280 (vcmpneq): Likewise.
11282 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
11284 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11285 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11286 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
11287 (mve_vcmpneq_<supf><mode>): Likewise.
11288 (mve_vshlq_<supf><mode>): Likewise.
11290 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11291 Mihail Ionescu <mihail.ionescu@arm.com>
11292 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11294 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
11295 qualifier for binary operands.
11296 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11297 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11298 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
11299 (vcvtq_n_s32_f32): Likewise.
11300 (vcvtq_n_u16_f16): Likewise.
11301 (vcvtq_n_u32_f32): Likewise.
11302 (vcreateq_u8): Likewise.
11303 (vcreateq_u16): Likewise.
11304 (vcreateq_u32): Likewise.
11305 (vcreateq_u64): Likewise.
11306 (vcreateq_s8): Likewise.
11307 (vcreateq_s16): Likewise.
11308 (vcreateq_s32): Likewise.
11309 (vcreateq_s64): Likewise.
11310 (vshrq_n_s8): Likewise.
11311 (vshrq_n_s16): Likewise.
11312 (vshrq_n_s32): Likewise.
11313 (vshrq_n_u8): Likewise.
11314 (vshrq_n_u16): Likewise.
11315 (vshrq_n_u32): Likewise.
11316 (__arm_vcreateq_u8): Define intrinsic.
11317 (__arm_vcreateq_u16): Likewise.
11318 (__arm_vcreateq_u32): Likewise.
11319 (__arm_vcreateq_u64): Likewise.
11320 (__arm_vcreateq_s8): Likewise.
11321 (__arm_vcreateq_s16): Likewise.
11322 (__arm_vcreateq_s32): Likewise.
11323 (__arm_vcreateq_s64): Likewise.
11324 (__arm_vshrq_n_s8): Likewise.
11325 (__arm_vshrq_n_s16): Likewise.
11326 (__arm_vshrq_n_s32): Likewise.
11327 (__arm_vshrq_n_u8): Likewise.
11328 (__arm_vshrq_n_u16): Likewise.
11329 (__arm_vshrq_n_u32): Likewise.
11330 (__arm_vcvtq_n_s16_f16): Likewise.
11331 (__arm_vcvtq_n_s32_f32): Likewise.
11332 (__arm_vcvtq_n_u16_f16): Likewise.
11333 (__arm_vcvtq_n_u32_f32): Likewise.
11334 (vshrq_n): Define polymorphic variant.
11335 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
11337 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11338 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11339 * config/arm/constraints.md (Rb): Define constraint to check constant is
11340 in the range of 1 to 8.
11341 (Rf): Define constraint to check constant is in the range of 1 to 32.
11342 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
11343 (mve_vshrq_n_<supf><mode>): Likewise.
11344 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
11345 * config/arm/predicates.md (mve_imm_8): Define predicate to check
11346 the matching constraint Rb.
11347 (mve_imm_32): Define predicate to check the matching constraint Rf.
11349 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11350 Mihail Ionescu <mihail.ionescu@arm.com>
11351 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11353 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
11354 qualifier for binary operands.
11355 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11356 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11357 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11358 * config/arm/arm_mve.h (vsubq_n_f16): Define macro.
11359 (vsubq_n_f32): Likewise.
11360 (vbrsrq_n_f16): Likewise.
11361 (vbrsrq_n_f32): Likewise.
11362 (vcvtq_n_f16_s16): Likewise.
11363 (vcvtq_n_f32_s32): Likewise.
11364 (vcvtq_n_f16_u16): Likewise.
11365 (vcvtq_n_f32_u32): Likewise.
11366 (vcreateq_f16): Likewise.
11367 (vcreateq_f32): Likewise.
11368 (__arm_vsubq_n_f16): Define intrinsic.
11369 (__arm_vsubq_n_f32): Likewise.
11370 (__arm_vbrsrq_n_f16): Likewise.
11371 (__arm_vbrsrq_n_f32): Likewise.
11372 (__arm_vcvtq_n_f16_s16): Likewise.
11373 (__arm_vcvtq_n_f32_s32): Likewise.
11374 (__arm_vcvtq_n_f16_u16): Likewise.
11375 (__arm_vcvtq_n_f32_u32): Likewise.
11376 (__arm_vcreateq_f16): Likewise.
11377 (__arm_vcreateq_f32): Likewise.
11378 (vsubq): Define polymorphic variant.
11379 (vbrsrq): Likewise.
11380 (vcvtq_n): Likewise.
11381 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
11383 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11384 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11385 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11386 * config/arm/constraints.md (Rd): Define constraint to check constant is
11387 in the range of 1 to 16.
11388 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
11389 mve_vbrsrq_n_f<mode>: Likewise.
11390 mve_vcvtq_n_to_f_<supf><mode>: Likewise.
11391 mve_vcreateq_f<mode>: Likewise.
11392 * config/arm/predicates.md (mve_imm_16): Define predicate to check
11393 the matching constraint Rd.
11395 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11396 Mihail Ionescu <mihail.ionescu@arm.com>
11397 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11399 * config/arm/arm-builtins.c (hi_UP): Define mode.
11400 * config/arm/arm.h (IS_VPR_REGNUM): Move.
11401 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
11402 (APSRQ_REGNUM): Modify.
11403 (APSRGE_REGNUM): Modify.
11404 * config/arm/arm_mve.h (vctp16q): Define macro.
11405 (vctp32q): Likewise.
11406 (vctp64q): Likewise.
11407 (vctp8q): Likewise.
11409 (__arm_vctp16q): Define intrinsic.
11410 (__arm_vctp32q): Likewise.
11411 (__arm_vctp64q): Likewise.
11412 (__arm_vctp8q): Likewise.
11413 (__arm_vpnot): Likewise.
11414 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
11416 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
11417 (mve_vpnothi): Likewise.
11419 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11420 Mihail Ionescu <mihail.ionescu@arm.com>
11421 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11423 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
11424 * config/arm/arm_mve.h (vdupq_n_s8): Define macro.
11425 (vdupq_n_s16): Likewise.
11426 (vdupq_n_s32): Likewise.
11427 (vabsq_s8): Likewise.
11428 (vabsq_s16): Likewise.
11429 (vabsq_s32): Likewise.
11430 (vclsq_s8): Likewise.
11431 (vclsq_s16): Likewise.
11432 (vclsq_s32): Likewise.
11433 (vclzq_s8): Likewise.
11434 (vclzq_s16): Likewise.
11435 (vclzq_s32): Likewise.
11436 (vnegq_s8): Likewise.
11437 (vnegq_s16): Likewise.
11438 (vnegq_s32): Likewise.
11439 (vaddlvq_s32): Likewise.
11440 (vaddvq_s8): Likewise.
11441 (vaddvq_s16): Likewise.
11442 (vaddvq_s32): Likewise.
11443 (vmovlbq_s8): Likewise.
11444 (vmovlbq_s16): Likewise.
11445 (vmovltq_s8): Likewise.
11446 (vmovltq_s16): Likewise.
11447 (vmvnq_s8): Likewise.
11448 (vmvnq_s16): Likewise.
11449 (vmvnq_s32): Likewise.
11450 (vrev16q_s8): Likewise.
11451 (vrev32q_s8): Likewise.
11452 (vrev32q_s16): Likewise.
11453 (vqabsq_s8): Likewise.
11454 (vqabsq_s16): Likewise.
11455 (vqabsq_s32): Likewise.
11456 (vqnegq_s8): Likewise.
11457 (vqnegq_s16): Likewise.
11458 (vqnegq_s32): Likewise.
11459 (vcvtaq_s16_f16): Likewise.
11460 (vcvtaq_s32_f32): Likewise.
11461 (vcvtnq_s16_f16): Likewise.
11462 (vcvtnq_s32_f32): Likewise.
11463 (vcvtpq_s16_f16): Likewise.
11464 (vcvtpq_s32_f32): Likewise.
11465 (vcvtmq_s16_f16): Likewise.
11466 (vcvtmq_s32_f32): Likewise.
11467 (vmvnq_u8): Likewise.
11468 (vmvnq_u16): Likewise.
11469 (vmvnq_u32): Likewise.
11470 (vdupq_n_u8): Likewise.
11471 (vdupq_n_u16): Likewise.
11472 (vdupq_n_u32): Likewise.
11473 (vclzq_u8): Likewise.
11474 (vclzq_u16): Likewise.
11475 (vclzq_u32): Likewise.
11476 (vaddvq_u8): Likewise.
11477 (vaddvq_u16): Likewise.
11478 (vaddvq_u32): Likewise.
11479 (vrev32q_u8): Likewise.
11480 (vrev32q_u16): Likewise.
11481 (vmovltq_u8): Likewise.
11482 (vmovltq_u16): Likewise.
11483 (vmovlbq_u8): Likewise.
11484 (vmovlbq_u16): Likewise.
11485 (vrev16q_u8): Likewise.
11486 (vaddlvq_u32): Likewise.
11487 (vcvtpq_u16_f16): Likewise.
11488 (vcvtpq_u32_f32): Likewise.
11489 (vcvtnq_u16_f16): Likewise.
11490 (vcvtmq_u16_f16): Likewise.
11491 (vcvtmq_u32_f32): Likewise.
11492 (vcvtaq_u16_f16): Likewise.
11493 (vcvtaq_u32_f32): Likewise.
11494 (__arm_vdupq_n_s8): Define intrinsic.
11495 (__arm_vdupq_n_s16): Likewise.
11496 (__arm_vdupq_n_s32): Likewise.
11497 (__arm_vabsq_s8): Likewise.
11498 (__arm_vabsq_s16): Likewise.
11499 (__arm_vabsq_s32): Likewise.
11500 (__arm_vclsq_s8): Likewise.
11501 (__arm_vclsq_s16): Likewise.
11502 (__arm_vclsq_s32): Likewise.
11503 (__arm_vclzq_s8): Likewise.
11504 (__arm_vclzq_s16): Likewise.
11505 (__arm_vclzq_s32): Likewise.
11506 (__arm_vnegq_s8): Likewise.
11507 (__arm_vnegq_s16): Likewise.
11508 (__arm_vnegq_s32): Likewise.
11509 (__arm_vaddlvq_s32): Likewise.
11510 (__arm_vaddvq_s8): Likewise.
11511 (__arm_vaddvq_s16): Likewise.
11512 (__arm_vaddvq_s32): Likewise.
11513 (__arm_vmovlbq_s8): Likewise.
11514 (__arm_vmovlbq_s16): Likewise.
11515 (__arm_vmovltq_s8): Likewise.
11516 (__arm_vmovltq_s16): Likewise.
11517 (__arm_vmvnq_s8): Likewise.
11518 (__arm_vmvnq_s16): Likewise.
11519 (__arm_vmvnq_s32): Likewise.
11520 (__arm_vrev16q_s8): Likewise.
11521 (__arm_vrev32q_s8): Likewise.
11522 (__arm_vrev32q_s16): Likewise.
11523 (__arm_vqabsq_s8): Likewise.
11524 (__arm_vqabsq_s16): Likewise.
11525 (__arm_vqabsq_s32): Likewise.
11526 (__arm_vqnegq_s8): Likewise.
11527 (__arm_vqnegq_s16): Likewise.
11528 (__arm_vqnegq_s32): Likewise.
11529 (__arm_vmvnq_u8): Likewise.
11530 (__arm_vmvnq_u16): Likewise.
11531 (__arm_vmvnq_u32): Likewise.
11532 (__arm_vdupq_n_u8): Likewise.
11533 (__arm_vdupq_n_u16): Likewise.
11534 (__arm_vdupq_n_u32): Likewise.
11535 (__arm_vclzq_u8): Likewise.
11536 (__arm_vclzq_u16): Likewise.
11537 (__arm_vclzq_u32): Likewise.
11538 (__arm_vaddvq_u8): Likewise.
11539 (__arm_vaddvq_u16): Likewise.
11540 (__arm_vaddvq_u32): Likewise.
11541 (__arm_vrev32q_u8): Likewise.
11542 (__arm_vrev32q_u16): Likewise.
11543 (__arm_vmovltq_u8): Likewise.
11544 (__arm_vmovltq_u16): Likewise.
11545 (__arm_vmovlbq_u8): Likewise.
11546 (__arm_vmovlbq_u16): Likewise.
11547 (__arm_vrev16q_u8): Likewise.
11548 (__arm_vaddlvq_u32): Likewise.
11549 (__arm_vcvtpq_u16_f16): Likewise.
11550 (__arm_vcvtpq_u32_f32): Likewise.
11551 (__arm_vcvtnq_u16_f16): Likewise.
11552 (__arm_vcvtmq_u16_f16): Likewise.
11553 (__arm_vcvtmq_u32_f32): Likewise.
11554 (__arm_vcvtaq_u16_f16): Likewise.
11555 (__arm_vcvtaq_u32_f32): Likewise.
11556 (__arm_vcvtaq_s16_f16): Likewise.
11557 (__arm_vcvtaq_s32_f32): Likewise.
11558 (__arm_vcvtnq_s16_f16): Likewise.
11559 (__arm_vcvtnq_s32_f32): Likewise.
11560 (__arm_vcvtpq_s16_f16): Likewise.
11561 (__arm_vcvtpq_s32_f32): Likewise.
11562 (__arm_vcvtmq_s16_f16): Likewise.
11563 (__arm_vcvtmq_s32_f32): Likewise.
11564 (vdupq_n): Define polymorphic variant.
11569 (vaddlvq): Likewise.
11570 (vaddvq): Likewise.
11571 (vmovlbq): Likewise.
11572 (vmovltq): Likewise.
11574 (vrev16q): Likewise.
11575 (vrev32q): Likewise.
11576 (vqabsq): Likewise.
11577 (vqnegq): Likewise.
11578 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11579 (UNOP_SNONE_NONE): Likewise.
11580 (UNOP_UNONE_UNONE): Likewise.
11581 (UNOP_UNONE_NONE): Likewise.
11582 * config/arm/constraints.md (e): Define new constriant to allow only
11584 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
11585 (mve_vnegq_s<mode>): Likewise.
11586 (mve_vmvnq_<supf><mode>): Likewise.
11587 (mve_vdupq_n_<supf><mode>): Likewise.
11588 (mve_vclzq_<supf><mode>): Likewise.
11589 (mve_vclsq_s<mode>): Likewise.
11590 (mve_vaddvq_<supf><mode>): Likewise.
11591 (mve_vabsq_s<mode>): Likewise.
11592 (mve_vrev32q_<supf><mode>): Likewise.
11593 (mve_vmovltq_<supf><mode>): Likewise.
11594 (mve_vmovlbq_<supf><mode>): Likewise.
11595 (mve_vcvtpq_<supf><mode>): Likewise.
11596 (mve_vcvtnq_<supf><mode>): Likewise.
11597 (mve_vcvtmq_<supf><mode>): Likewise.
11598 (mve_vcvtaq_<supf><mode>): Likewise.
11599 (mve_vrev16q_<supf>v16qi): Likewise.
11600 (mve_vaddlvq_<supf>v4si): Likewise.
11602 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11604 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in
11606 * tree-sra.c (create_access_replacement): Fix up duplicated word issue
11608 * read-rtl-function.c (find_param_by_name,
11609 function_reader::parse_enum_value, function_reader::get_insn_by_uid):
11611 * spellcheck.c (get_edit_distance_cutoff): Likewise.
11612 * tree-data-ref.c (create_ifn_alias_checks): Likewise.
11613 * tree.def (SWITCH_EXPR): Likewise.
11614 * selftest.c (assert_str_contains): Likewise.
11615 * ipa-param-manipulation.h (class ipa_param_body_adjustments):
11617 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
11618 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
11619 * langhooks.h (struct lang_hooks_for_decls): Likewise.
11620 * ipa-prop.h (struct ipa_param_descriptor): Likewise.
11621 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
11623 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
11624 * tree-ssa-reassoc.c (reassociate_bb): Likewise.
11625 * tree.c (component_ref_size): Likewise.
11626 * hsa-common.c (hsa_init_compilation_unit_data): Likewise.
11627 * gimple-ssa-sprintf.c (get_string_length, format_string,
11628 format_directive): Likewise.
11629 * omp-grid.c (grid_process_kernel_body_copy): Likewise.
11630 * input.c (string_concat_db::get_string_concatenation,
11631 test_lexer_string_locations_ucn4): Likewise.
11632 * cfgexpand.c (pass_expand::execute): Likewise.
11633 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
11634 maybe_diag_overlap): Likewise.
11635 * rtl.c (RTX_CODE_HWINT_P_1): Likewise.
11636 * shrink-wrap.c (spread_components): Likewise.
11637 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
11639 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
11641 * dwarf2out.c (dwarf2out_early_finish): Likewise.
11642 * gimple-ssa-store-merging.c: Likewise.
11643 * ira-costs.c (record_operand_costs): Likewise.
11644 * tree-vect-loop.c (vectorizable_reduction): Likewise.
11645 * target.def (dispatch): Likewise.
11646 (validate_dims, gen_ccmp_first): Fix up duplicated word issue
11647 in documentation text.
11648 * doc/tm.texi: Regenerated.
11649 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
11650 duplicated word issue in a comment.
11651 * config/i386/i386.c (ix86_test_loading_unspec): Likewise.
11652 * config/i386/i386-features.c (remove_partial_avx_dependency):
11654 * config/msp430/msp430.c (msp430_select_section): Likewise.
11655 * config/gcn/gcn-run.c (load_image): Likewise.
11656 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
11657 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
11658 * config/aarch64/falkor-tag-collision-avoidance.c
11659 (single_dest_per_chain): Likewise.
11660 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
11661 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
11662 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
11663 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
11665 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
11666 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
11667 * config/rs6000/rs6000-logue.c
11668 (rs6000_emit_probe_stack_range_stack_clash): Likewise.
11669 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
11670 Fix various other issues in the comment.
11672 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
11674 * config/arm/t-rmprofile: create new multilib for
11675 armv8.1-m.main+mve hard float and reuse v8-m.main ones for
11678 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11680 PR tree-optimization/94015
11681 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
11682 function where EXP is address of the bytes being stored rather than
11683 the bytes themselves into count_nonzero_bytes_addr. Punt on zero
11684 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
11685 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before
11686 calling native_encode_expr if host or target doesn't have 8-bit
11687 chars. Formatting fixes.
11688 (count_nonzero_bytes_addr): New function.
11690 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11691 Mihail Ionescu <mihail.ionescu@arm.com>
11692 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11694 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
11695 (UNOP_SNONE_NONE_QUALIFIERS): Likewise.
11696 (UNOP_SNONE_IMM_QUALIFIERS): Likewise.
11697 (UNOP_UNONE_NONE_QUALIFIERS): Likewise.
11698 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
11699 (UNOP_UNONE_IMM_QUALIFIERS): Likewise.
11700 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
11701 (vmvnq_n_s32): Likewise.
11702 (vrev64q_s8): Likewise.
11703 (vrev64q_s16): Likewise.
11704 (vrev64q_s32): Likewise.
11705 (vcvtq_s16_f16): Likewise.
11706 (vcvtq_s32_f32): Likewise.
11707 (vrev64q_u8): Likewise.
11708 (vrev64q_u16): Likewise.
11709 (vrev64q_u32): Likewise.
11710 (vmvnq_n_u16): Likewise.
11711 (vmvnq_n_u32): Likewise.
11712 (vcvtq_u16_f16): Likewise.
11713 (vcvtq_u32_f32): Likewise.
11714 (__arm_vmvnq_n_s16): Define intrinsic.
11715 (__arm_vmvnq_n_s32): Likewise.
11716 (__arm_vrev64q_s8): Likewise.
11717 (__arm_vrev64q_s16): Likewise.
11718 (__arm_vrev64q_s32): Likewise.
11719 (__arm_vrev64q_u8): Likewise.
11720 (__arm_vrev64q_u16): Likewise.
11721 (__arm_vrev64q_u32): Likewise.
11722 (__arm_vmvnq_n_u16): Likewise.
11723 (__arm_vmvnq_n_u32): Likewise.
11724 (__arm_vcvtq_s16_f16): Likewise.
11725 (__arm_vcvtq_s32_f32): Likewise.
11726 (__arm_vcvtq_u16_f16): Likewise.
11727 (__arm_vcvtq_u32_f32): Likewise.
11728 (vrev64q): Define polymorphic variant.
11729 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11730 (UNOP_SNONE_NONE): Likewise.
11731 (UNOP_SNONE_IMM): Likewise.
11732 (UNOP_UNONE_UNONE): Likewise.
11733 (UNOP_UNONE_NONE): Likewise.
11734 (UNOP_UNONE_IMM): Likewise.
11735 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
11736 (mve_vcvtq_from_f_<supf><mode>): Likewise.
11737 (mve_vmvnq_n_<supf><mode>): Likewise.
11739 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11740 Mihail Ionescu <mihail.ionescu@arm.com>
11741 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11743 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
11744 (UNOP_NONE_SNONE_QUALIFIERS): Likewise.
11745 (UNOP_NONE_UNONE_QUALIFIERS): Likewise.
11746 * config/arm/arm_mve.h (vrndxq_f16): Define macro.
11747 (vrndxq_f32): Likewise.
11748 (vrndq_f16) Likewise.
11749 (vrndq_f32): Likewise.
11750 (vrndpq_f16): Likewise.
11751 (vrndpq_f32): Likewise.
11752 (vrndnq_f16): Likewise.
11753 (vrndnq_f32): Likewise.
11754 (vrndmq_f16): Likewise.
11755 (vrndmq_f32): Likewise.
11756 (vrndaq_f16): Likewise.
11757 (vrndaq_f32): Likewise.
11758 (vrev64q_f16): Likewise.
11759 (vrev64q_f32): Likewise.
11760 (vnegq_f16): Likewise.
11761 (vnegq_f32): Likewise.
11762 (vdupq_n_f16): Likewise.
11763 (vdupq_n_f32): Likewise.
11764 (vabsq_f16): Likewise.
11765 (vabsq_f32): Likewise.
11766 (vrev32q_f16): Likewise.
11767 (vcvttq_f32_f16): Likewise.
11768 (vcvtbq_f32_f16): Likewise.
11769 (vcvtq_f16_s16): Likewise.
11770 (vcvtq_f32_s32): Likewise.
11771 (vcvtq_f16_u16): Likewise.
11772 (vcvtq_f32_u32): Likewise.
11773 (__arm_vrndxq_f16): Define intrinsic.
11774 (__arm_vrndxq_f32): Likewise.
11775 (__arm_vrndq_f16): Likewise.
11776 (__arm_vrndq_f32): Likewise.
11777 (__arm_vrndpq_f16): Likewise.
11778 (__arm_vrndpq_f32): Likewise.
11779 (__arm_vrndnq_f16): Likewise.
11780 (__arm_vrndnq_f32): Likewise.
11781 (__arm_vrndmq_f16): Likewise.
11782 (__arm_vrndmq_f32): Likewise.
11783 (__arm_vrndaq_f16): Likewise.
11784 (__arm_vrndaq_f32): Likewise.
11785 (__arm_vrev64q_f16): Likewise.
11786 (__arm_vrev64q_f32): Likewise.
11787 (__arm_vnegq_f16): Likewise.
11788 (__arm_vnegq_f32): Likewise.
11789 (__arm_vdupq_n_f16): Likewise.
11790 (__arm_vdupq_n_f32): Likewise.
11791 (__arm_vabsq_f16): Likewise.
11792 (__arm_vabsq_f32): Likewise.
11793 (__arm_vrev32q_f16): Likewise.
11794 (__arm_vcvttq_f32_f16): Likewise.
11795 (__arm_vcvtbq_f32_f16): Likewise.
11796 (__arm_vcvtq_f16_s16): Likewise.
11797 (__arm_vcvtq_f32_s32): Likewise.
11798 (__arm_vcvtq_f16_u16): Likewise.
11799 (__arm_vcvtq_f32_u32): Likewise.
11800 (vrndxq): Define polymorphic variants.
11802 (vrndpq): Likewise.
11803 (vrndnq): Likewise.
11804 (vrndmq): Likewise.
11805 (vrndaq): Likewise.
11806 (vrev64q): Likewise.
11809 (vrev32q): Likewise.
11810 (vcvtbq_f32): Likewise.
11811 (vcvttq_f32): Likewise.
11813 * config/arm/arm_mve_builtins.def (VAR2): Define.
11815 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
11816 (mve_vrndq_f<mode>): Likewise.
11817 (mve_vrndpq_f<mode>): Likewise.
11818 (mve_vrndnq_f<mode>): Likewise.
11819 (mve_vrndmq_f<mode>): Likewise.
11820 (mve_vrndaq_f<mode>): Likewise.
11821 (mve_vrev64q_f<mode>): Likewise.
11822 (mve_vnegq_f<mode>): Likewise.
11823 (mve_vdupq_n_f<mode>): Likewise.
11824 (mve_vabsq_f<mode>): Likewise.
11825 (mve_vrev32q_fv8hf): Likewise.
11826 (mve_vcvttq_f32_f16v4sf): Likewise.
11827 (mve_vcvtbq_f32_f16v4sf): Likewise.
11828 (mve_vcvtq_to_f_<supf><mode>): Likewise.
11830 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11831 Mihail Ionescu <mihail.ionescu@arm.com>
11832 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11834 * config/arm/arm-builtins.c (CF): Define mve_builtin_data.
11836 (ARM_BUILTIN_MVE_PATTERN_START): Define.
11837 (arm_init_mve_builtins): Define function.
11838 (arm_init_builtins): Add TARGET_HAVE_MVE check.
11839 (arm_expand_builtin_1): Check the range of fcode.
11840 (arm_expand_mve_builtin): Define function to expand MVE builtins.
11841 (arm_expand_builtin): Check the range of fcode.
11842 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
11844 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
11845 (vst4q_s8): Define macro.
11846 (vst4q_s16): Likewise.
11847 (vst4q_s32): Likewise.
11848 (vst4q_u8): Likewise.
11849 (vst4q_u16): Likewise.
11850 (vst4q_u32): Likewise.
11851 (vst4q_f16): Likewise.
11852 (vst4q_f32): Likewise.
11853 (__arm_vst4q_s8): Define inline builtin.
11854 (__arm_vst4q_s16): Likewise.
11855 (__arm_vst4q_s32): Likewise.
11856 (__arm_vst4q_u8): Likewise.
11857 (__arm_vst4q_u16): Likewise.
11858 (__arm_vst4q_u32): Likewise.
11859 (__arm_vst4q_f16): Likewise.
11860 (__arm_vst4q_f32): Likewise.
11861 (__ARM_mve_typeid): Define macro with MVE types.
11862 (__ARM_mve_coerce): Define macro with _Generic feature.
11863 (vst4q): Define polymorphic variant for different vst4q builtins.
11864 * config/arm/arm_mve_builtins.def: New file.
11865 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
11867 * config/arm/mve.md (MVE_VLD_ST): Define iterator.
11868 (unspec): Define unspec.
11869 (mve_vst4q<mode>): Define RTL pattern.
11870 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
11872 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
11874 (define_split): Allow OI mode split for MVE after reload.
11875 (define_split): Allow XI mode split for MVE after reload.
11876 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
11877 (arm-builtins.o): Likewise.
11879 2020-03-17 Christophe Lyon <christophe.lyon@linaro.org>
11881 * c-typeck.c (process_init_element): Handle constructor_type with
11882 type size represented by POLY_INT_CST.
11884 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11886 PR tree-optimization/94187
11887 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if
11888 nchars - offset < nbytes.
11890 PR middle-end/94189
11891 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
11892 emit a warning if it was enabled and don't depend on TREE_NO_WARNING
11893 for code-generation.
11895 2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
11898 * lra-spills.c (remove_pseudos): Do not reuse insn alternative
11899 after changing memory subreg.
11901 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11902 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11904 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
11905 emulator calls for dobule precision arithmetic operations for MVE.
11907 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11908 Mihail Ionescu <mihail.ionescu@arm.com>
11909 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11911 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
11912 feature bit is on and -mfpu=auto is passed as compiler option, do not
11913 generate error on not finding any matching fpu. Because in this case
11914 fpu is not required.
11915 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
11916 enabled for MVE and also for all VFP extensions.
11917 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
11919 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
11920 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
11921 along with feature bits mve_float.
11922 (mve): Modify add options in armv8.1-m.main arch for MVE.
11923 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with
11925 * config/arm/arm.c (use_return_insn): Replace the
11926 check with TARGET_VFP_BASE.
11927 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
11929 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
11930 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
11932 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
11933 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
11935 (arm_compute_frame_layout): Likewise.
11936 (arm_save_coproc_regs): Likewise.
11937 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
11939 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
11940 with equivalent macro TARGET_VFP_BASE.
11941 (arm_expand_epilogue_apcs_frame): Likewise.
11942 (arm_expand_epilogue): Likewise.
11943 (arm_conditional_register_usage): Likewise.
11944 (arm_declare_function_name): Add check to skip printing .fpu directive
11945 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
11947 * config/arm/arm.h (TARGET_VFP_BASE): Define.
11948 * config/arm/arm.md (arch): Add "mve" to arch.
11949 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
11950 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
11951 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
11952 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR
11954 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
11955 to not allow for MVE.
11956 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
11958 (VUNSPEC_GET_FPSCR): Define.
11959 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
11960 instructions which move to general-purpose Register from Floating-point
11961 Special register and vice-versa.
11962 (thumb2_movhi_fp16): Likewise.
11963 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
11964 with MCR and MRC instructions which set and get Floating-point Status
11965 and Control Register (FPSCR).
11966 (movdi_vfp): Modify pattern to enable Single-precision scalar float move
11968 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
11969 float move patterns in MVE.
11970 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
11971 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
11972 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
11973 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
11974 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
11975 TARGET_VFP_BASE check.
11976 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
11977 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
11979 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
11980 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
11984 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11985 Mihail Ionescu <mihail.ionescu@arm.com>
11986 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11988 * config.gcc (arm_mve.h): Include mve intrinsics header file.
11989 * config/arm/aout.h (p0): Add new register name for MVE predicated
11991 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
11992 common to Neon and MVE.
11993 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
11994 (arm_init_simd_builtin_types): Disable poly types for MVE.
11995 (arm_init_neon_builtins): Move a check to arm_init_builtins function.
11996 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
11997 ARM_BUILTIN_NEON_LANE_CHECK.
11998 (mve_dereference_pointer): Add function.
11999 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
12001 (arm_expand_neon_builtin): Moved to arm_expand_builtin function.
12002 (arm_expand_builtin): Moved from arm_expand_neon_builtin function.
12003 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
12004 with floating point enabled.
12005 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
12006 simd_immediate_valid_for_move.
12007 (simd_immediate_valid_for_move): Renamed from
12008 neon_immediate_valid_for_move function.
12009 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
12010 error if vfpv2 feature bit is disabled and mve feature bit is also
12011 disabled for HARD_FLOAT_ABI.
12012 (use_return_insn): Check to not push VFP regs for MVE.
12013 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
12015 (aapcs_vfp_allocate_return_reg): Likewise.
12016 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
12017 address operand for MVE.
12018 (arm_rtx_costs_internal): MVE check to determine cost of rtx.
12019 (neon_valid_immediate): Rename to simd_valid_immediate.
12020 (simd_valid_immediate): Rename from neon_valid_immediate.
12021 (simd_valid_immediate): MVE check on size of vector is 128 bits.
12022 (neon_immediate_valid_for_move): Rename to
12023 simd_immediate_valid_for_move.
12024 (simd_immediate_valid_for_move): Rename from
12025 neon_immediate_valid_for_move.
12026 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
12028 (neon_make_constant): Modify call to neon_valid_immediate function.
12029 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
12031 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
12032 (arm_compute_frame_layout): Calculate space for saved VFP registers for
12034 (arm_save_coproc_regs): Save coproc registers for MVE.
12035 (arm_print_operand): Add case 'E' to print memory operands for MVE.
12036 (arm_print_operand_address): Check to print register number for MVE.
12037 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
12038 (arm_modes_tieable_p): Check to allow structure mode for MVE.
12039 (arm_regno_class): Add VPR_REGNUM check.
12040 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
12042 (arm_expand_epilogue): MVE check for enabling pop instructions in
12044 (arm_print_asm_arch_directives): Modify function to disable print of
12045 .arch_extension "mve" and "fp" for cases where MVE is enabled with
12047 (arm_vector_mode_supported_p): Check for modes available in MVE interger
12048 and MVE floating point.
12049 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
12051 (arm_conditional_register_usage): Enable usage of conditional regsiter
12053 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
12054 (arm_declare_function_name): Modify function to disable print of
12055 .arch_extension "mve" and "fp" for cases where MVE is enabled with
12057 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
12058 when target general registers are required.
12059 (TARGET_HAVE_MVE_FLOAT): Likewise.
12060 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
12062 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
12063 which indicate this is not available for across function calls.
12064 (FIRST_PSEUDO_REGISTER): Modify.
12065 (VALID_MVE_MODE): Define valid MVE mode.
12066 (VALID_MVE_SI_MODE): Define valid MVE SI mode.
12067 (VALID_MVE_SF_MODE): Define valid MVE SF mode.
12068 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
12069 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
12071 (IS_VPR_REGNUM): Macro to check for VPR_REG register.
12072 (REG_ALLOC_ORDER): Add VPR_REGNUM entry.
12073 (enum reg_class): Add VPR_REG entry.
12074 (REG_CLASS_NAMES): Add VPR_REG entry.
12075 * config/arm/arm.md (VPR_REGNUM): Define.
12076 (conds): Check is_mve_type attrbiute to differentiate "conditional" and
12077 "unconditional" instructions.
12078 (arm_movsf_soft_insn): Modify RTL to not allow for MVE.
12079 (movdf_soft_insn): Modify RTL to not allow for MVE.
12080 (vfp_pop_multiple_with_writeback): Enable for MVE.
12081 (include "mve.md"): Include mve.md file.
12082 * config/arm/arm_mve.h: Add MVE intrinsics head file.
12083 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
12084 for vector predicated operands.
12085 * config/arm/iterators.md (VNIM1): Define.
12086 (VNINOTM1): Define.
12087 (VHFBF_split): Define
12088 * config/arm/mve.md: New file.
12089 (mve_mov<mode>): Define RTL for move, store and load in MVE.
12090 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
12092 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with
12093 simd_immediate_valid_for_move.
12094 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
12095 is common to MVE and NEON to vec-common.md file.
12096 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
12097 * config/arm/predicates.md (vpr_register_operand): Define.
12098 * config/arm/t-arm: Add mve.md file.
12099 * config/arm/types.md (mve_move): Add MVE instructions mve_move to
12101 (mve_store): Add MVE instructions mve_store to attribute "type".
12102 (mve_load): Add MVE instructions mve_load to attribute "type".
12103 (is_mve_type): Define attribute.
12104 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
12105 standard move patterns in MVE along with NEON and IWMMXT with mode
12107 (mov<mode>): Modify RTL expand to support standard move patterns in NEON
12108 and IWMMXT with mode iterator V8HF.
12109 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in
12111 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
12112 simd_immediate_valid_for_move.
12115 2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
12118 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
12119 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
12121 * config/i386/predicates.md (ext_sse_reg_operand): Removed.
12123 2020-03-16 Jakub Jelinek <jakub@redhat.com>
12126 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
12129 PR tree-optimization/94166
12130 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
12131 as secondary comparison key.
12133 2020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com>
12135 PR tree-optimization/94125
12136 * tree-loop-distribution.c
12137 (loop_distribution::break_alias_scc_partitions): Update post order
12138 number for merged scc.
12140 2020-03-15 H.J. Lu <hongjiu.lu@intel.com>
12143 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
12145 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
12146 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
12147 and ext_sse_reg_operand check.
12149 2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
12151 * common.opt: Avoid redundancy in the help text.
12152 * config/arc/arc.opt: Likewise.
12153 * config/cr16/cr16.opt: Likewise.
12155 2020-03-14 Jakub Jelinek <jakub@redhat.com>
12157 PR middle-end/93566
12158 * tree-nested.c (convert_nonlocal_omp_clauses,
12159 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
12160 with C/C++ array sections.
12162 2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
12165 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
12166 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
12169 2020-03-14 Jakub Jelinek <jakub@redhat.com>
12171 * gimple-fold.c (gimple_fold_builtin_strncpy): Change
12172 "a an" to "an" in a comment.
12173 * hsa-common.h (is_a_helper): Likewise.
12174 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
12175 * config/arc/arc.c (arc600_corereg_hazard): Likewise.
12176 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
12178 2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
12181 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a
12182 64-bit value by 64 bits (UB).
12184 2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
12186 PR rtl-optimization/92303
12187 * lra-spills.c (remove_pseudos): Try to simplify memory subreg.
12189 2020-03-13 Segher Boessenkool <segher@kernel.crashing.org>
12191 PR rtl-optimization/94148
12192 PR rtl-optimization/94042
12193 * df-core.c (BB_LAST_CHANGE_AGE): Delete.
12194 (df_worklist_propagate_forward): New parameter last_change_age, use
12195 that instead of bb->aux.
12196 (df_worklist_propagate_backward): Ditto.
12197 (df_worklist_dataflow_doublequeue): Use a local array last_change_age.
12199 2020-03-13 Richard Biener <rguenther@suse.de>
12201 PR tree-optimization/94163
12202 * tree-ssa-pre.c (create_expression_by_pieces): Check
12203 whether alignment would be zero.
12205 2020-03-13 Martin Liska <mliska@suse.cz>
12208 * lto-wrapper.c (run_gcc): Use concat for appending
12209 to collect_gcc_options.
12211 2020-03-13 Jakub Jelinek <jakub@redhat.com>
12214 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
12215 instead of GEN_INT.
12217 2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
12220 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
12221 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
12222 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
12223 TARGET_AVX512VL and ext_sse_reg_operand check.
12225 2020-03-13 Bu Le <bule1@huawei.com>
12228 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
12229 (-param=aarch64-double-recp-precision=): New options.
12230 * doc/invoke.texi: Document them.
12231 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
12232 instead of hard-coding the choice of 1 for float and 2 for double.
12234 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12236 PR rtl-optimization/94119
12237 * resource.h (clear_hashed_info_until_next_barrier): Declare.
12238 * resource.c (clear_hashed_info_until_next_barrier): New function.
12239 * reorg.c (add_to_delay_list): Fix formatting.
12240 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
12241 the next instruction after removing a BARRIER.
12243 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12245 PR middle-end/92071
12246 * expmed.c (store_integral_bit_field): For fields larger than a word,
12247 call extract_bit_field on the value if the mode is BLKmode. Remove
12248 specific path for big-endian targets and tidy things up a little bit.
12250 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
12252 PR rtl-optimization/90275
12253 * cse.c (cse_insn): Delete no-op register moves too.
12255 2020-03-12 Darius Galis <darius.galis@cyberthorstudios.com>
12257 * config/rx/rx.md (CTRLREG_CPEN): Remove.
12258 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
12260 2020-03-12 Richard Biener <rguenther@suse.de>
12262 PR tree-optimization/94103
12263 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
12264 punning when the mode precision is not sufficient.
12266 2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
12269 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
12270 MODE_V1DF and MODE_V2SF.
12271 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
12272 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
12275 2020-03-12 Jakub Jelinek <jakub@redhat.com>
12277 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
12278 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
12279 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
12280 * doc/tm.texi: Regenerated.
12282 PR tree-optimization/94130
12283 * tree-ssa-dse.c: Include gimplify.h.
12284 (increment_start_addr): If stmt has lhs, drop the lhs from call and
12285 set it after the call to the original value of the first argument.
12287 (decrement_count): Formatting fix.
12289 2020-03-11 Delia Burduv <delia.burduv@arm.com>
12291 * config/arm/arm-builtins.c
12292 (arm_init_simd_builtin_scalar_types): New.
12293 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
12294 (vld2q_bf16): Used new builtin type.
12295 (vld3_bf16): Used new builtin type.
12296 (vld3q_bf16): Used new builtin type.
12297 (vld4_bf16): Used new builtin type.
12298 (vld4q_bf16): Used new builtin type.
12299 (vld2_dup_bf16): Used new builtin type.
12300 (vld2q_dup_bf16): Used new builtin type.
12301 (vld3_dup_bf16): Used new builtin type.
12302 (vld3q_dup_bf16): Used new builtin type.
12303 (vld4_dup_bf16): Used new builtin type.
12304 (vld4q_dup_bf16): Used new builtin type.
12306 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12309 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
12310 at the start to switch to data section. Don't print extra newline if
12311 .globl directive has not been emitted.
12313 2020-03-11 Richard Biener <rguenther@suse.de>
12315 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
12318 2020-03-11 Eric Botcazou <ebotcazou@adacore.com>
12320 PR middle-end/93961
12321 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields
12322 whose type is a qualified union.
12324 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12327 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
12328 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
12331 * value-prof.c (dump_histogram_value): Use abs_hwi instead of
12333 (get_nth_most_common_value): Use abs_hwi instead of abs.
12335 PR middle-end/94111
12336 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
12337 is rvc_normal, otherwise use real_to_decimal to print the number to
12340 PR tree-optimization/94114
12341 * tree-loop-distribution.c (generate_memset_builtin): Call
12342 rewrite_to_non_trapping_overflow even on mem.
12343 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
12346 2020-03-10 Jeff Law <law@redhat.com>
12348 * config/bfin/bfin.md (movsi_insv): Add length attribute.
12350 2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
12353 * config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
12354 NAN and SIGNED_ZEROR for smax/smin.
12356 2020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
12359 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
12360 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
12362 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12364 * loop-iv.c (find_simple_exit): Make it static.
12365 * cfgloop.h: Remove the corresponding prototype.
12367 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12369 * ddg.c (create_ddg): Fix intendation.
12370 (set_recurrence_length): Likewise.
12371 (create_ddg_all_sccs): Likewise.
12373 2020-03-10 Jakub Jelinek <jakub@redhat.com>
12376 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with
12377 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len
12380 2020-03-09 Jason Merrill <jason@redhat.com>
12382 * gdbinit.in (pgs): Fix typo in documentation.
12384 2020-03-09 Vladimir Makarov <vmakarov@redhat.com>
12388 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
12390 PR rtl-optimization/93564
12391 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
12392 do not honor reg alloc order.
12394 2020-03-09 Andrew Pinski <apinski@marvell.com>
12396 PR inline-asm/94095
12397 * doc/extend.texi (x86 Operand Modifiers): Fix column
12400 2020-03-09 Martin Liska <mliska@suse.cz>
12403 * config/rs6000/rs6000.c (rs6000_option_override_internal):
12404 Remove set of str_align_loops and str_align_jumps as these
12405 should be set in previous 2 conditions in the function.
12407 2020-03-09 Jakub Jelinek <jakub@redhat.com>
12409 PR rtl-optimization/94045
12410 * params.opt (-param=max-find-base-term-values=): New option.
12411 * alias.c (find_base_term): Add cut-off for number of visited VALUEs
12412 in a single toplevel find_base_term call.
12414 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12417 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define.
12418 * config/aarch64/aarch64-simd.md
12419 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul.
12420 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
12421 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
12422 * config/aarch64/arm_neon.h:
12423 (vmlal_lane_s16): Expand using intrinsics rather than inline asm.
12424 (vmlal_lane_u16): Likewise.
12425 (vmlal_lane_s32): Likewise.
12426 (vmlal_lane_u32): Likewise.
12427 (vmlal_laneq_s16): Likewise.
12428 (vmlal_laneq_u16): Likewise.
12429 (vmlal_laneq_s32): Likewise.
12430 (vmlal_laneq_u32): Likewise.
12431 (vmull_lane_s16): Likewise.
12432 (vmull_lane_u16): Likewise.
12433 (vmull_lane_s32): Likewise.
12434 (vmull_lane_u32): Likewise.
12435 (vmull_laneq_s16): Likewise.
12436 (vmull_laneq_u16): Likewise.
12437 (vmull_laneq_s32): Likewise.
12438 (vmull_laneq_u32): Likewise.
12439 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul.
12442 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12444 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
12445 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
12446 (aarch64_mls_elt<mode>): Likewise.
12447 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
12448 (aarch64_fma4_elt<mode>): Likewise.
12449 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
12450 (aarch64_fma4_elt_to_64v2df): Likewise.
12451 (aarch64_fnma4_elt<mode>): Likewise.
12452 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
12453 (aarch64_fnma4_elt_to_64v2df): Likewise.
12455 2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
12457 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
12458 Specify movprfx attribute.
12459 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
12461 2020-03-06 David Edelsohn <dje.gcc@gmail.com>
12464 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for
12466 (TARGET_NO_FP_IN_TOC): Same.
12467 * config/rs6000/aix71.h: Same.
12468 * config/rs6000/aix72.h: Same.
12470 2020-03-06 Andrew Pinski <apinski@marvell.com>
12471 Jeff Law <law@redhat.com>
12473 PR rtl-optimization/93996
12474 * haifa-sched.c (remove_notes): Be more careful when adding
12477 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12479 * config/arm/arm_neon.h (vld2_bf16): New.
12485 (vld2_dup_bf16): New.
12486 (vld2q_dup_bf16): New.
12487 (vld3_dup_bf16): New.
12488 (vld3q_dup_bf16): New.
12489 (vld4_dup_bf16): New.
12490 (vld4q_dup_bf16): New.
12491 * config/arm/arm_neon_builtins.def
12492 (vld2): Changed to VAR13 and added v4bf, v8bf
12493 (vld2_dup): Changed to VAR8 and added v4bf, v8bf
12494 (vld3): Changed to VAR13 and added v4bf, v8bf
12495 (vld3_dup): Changed to VAR8 and added v4bf, v8bf
12496 (vld4): Changed to VAR13 and added v4bf, v8bf
12497 (vld4_dup): Changed to VAR8 and added v4bf, v8bf
12498 * config/arm/iterators.md (VDXBF2): New iterator.
12499 *config/arm/neon.md (neon_vld2): Use new iterators.
12500 (neon_vld2_dup<mode): Use new iterators.
12501 (neon_vld3<mode>): Likewise.
12502 (neon_vld3qa<mode>): Likewise.
12503 (neon_vld3qb<mode>): Likewise.
12504 (neon_vld3_dup<mode>): Likewise.
12505 (neon_vld4<mode>): Likewise.
12506 (neon_vld4qa<mode>): Likewise.
12507 (neon_vld4qb<mode>): Likewise.
12508 (neon_vld4_dup<mode>): Likewise.
12509 (neon_vld2_dupv8bf): New.
12510 (neon_vld3_dupv8bf): Likewise.
12511 (neon_vld4_dupv8bf): Likewise.
12513 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12515 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
12516 (bfloat16x8x2_t): New typedef.
12517 (bfloat16x4x3_t): New typedef.
12518 (bfloat16x8x3_t): New typedef.
12519 (bfloat16x4x4_t): New typedef.
12520 (bfloat16x8x4_t): New typedef.
12527 * config/arm/arm-builtins.c (v2bf_UP): Define.
12529 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype.
12530 * config/arm/arm-modes.def (V2BF): New mode.
12531 * config/arm/arm-simd-builtin-types.def
12532 (Bfloat16x2_t): New entry.
12533 * config/arm/arm_neon_builtins.def
12534 (vst2): Changed to VAR13 and added v4bf, v8bf
12535 (vst3): Changed to VAR13 and added v4bf, v8bf
12536 (vst4): Changed to VAR13 and added v4bf, v8bf
12537 * config/arm/iterators.md (VDXBF): New iterator.
12538 (VQ2BF): New iterator.
12539 *config/arm/neon.md (neon_vst2<mode>): Used new iterators.
12540 (neon_vst2<mode>): Used new iterators.
12541 (neon_vst3<mode>): Used new iterators.
12542 (neon_vst3<mode>): Used new iterators.
12543 (neon_vst3qa<mode>): Used new iterators.
12544 (neon_vst3qb<mode>): Used new iterators.
12545 (neon_vst4<mode>): Used new iterators.
12546 (neon_vst4<mode>): Used new iterators.
12547 (neon_vst4qa<mode>): Used new iterators.
12548 (neon_vst4qb<mode>): Used new iterators.
12550 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12552 * config/aarch64/aarch64-simd-builtins.def
12553 (bfcvtn): New built-in function.
12554 (bfcvtn_q): New built-in function.
12555 (bfcvtn2): New built-in function.
12556 (bfcvt): New built-in function.
12557 * config/aarch64/aarch64-simd.md
12558 (aarch64_bfcvtn<q><mode>): New pattern.
12559 (aarch64_bfcvtn2v8bf): New pattern.
12560 (aarch64_bfcvtbf): New pattern.
12561 * config/aarch64/arm_bf16.h (float32_t): New typedef.
12562 (vcvth_bf16_f32): New intrinsic.
12563 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic.
12564 (vcvtq_low_bf16_f32): New intrinsic.
12565 (vcvtq_high_bf16_f32): New intrinsic.
12566 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator.
12567 (UNSPEC_BFCVTN): New UNSPEC.
12568 (UNSPEC_BFCVTN2): New UNSPEC.
12569 (UNSPEC_BFCVT): New UNSPEC.
12570 * config/arm/types.md (bf_cvt): New type.
12572 2020-03-06 Andreas Krebbel <krebbel@linux.ibm.com>
12574 * config/s390/s390.md ("tabort"): Get rid of two consecutive
12575 blanks in format string.
12577 2020-03-05 H.J. Lu <hongjiu.lu@intel.com>
12581 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype.
12582 * config/i386/i386.c (ix86_get_ssemov): New function.
12583 (ix86_output_ssemov): Likewise.
12584 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call
12585 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL
12587 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV.
12588 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV.
12589 Remove ext_sse_reg_operand and TARGET_AVX512VL check.
12590 (*movti_internal): Likewise.
12591 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV.
12593 2020-03-05 Jeff Law <law@redhat.com>
12595 PR tree-optimization/91890
12596 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument.
12597 Use gimple_or_expr_nonartificial_location.
12598 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds.
12599 Use gimple_or_expr_nonartificial_location.
12600 * gimple.c (gimple_or_expr_nonartificial_location): New function.
12601 * gimple.h (gimple_or_expr_nonartificial_location): Declare it.
12602 * tree-ssa-strlen.c (maybe_warn_overflow): Use
12603 gimple_or_expr_nonartificial_location.
12604 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise.
12605 (maybe_warn_pointless_strcmp): Likewise.
12607 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12610 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
12611 SRC and MASK arguments to __m128 from __m128d.
12612 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
12614 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
12616 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
12617 argument to __m128i from __m128d.
12618 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
12620 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
12621 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
12624 2020-03-05 Delia Burduv <delia.burduv@arm.com>
12626 * config/arm/arm_neon.h (vbfmmlaq_f32): New.
12627 (vbfmlalbq_f32): New.
12628 (vbfmlaltq_f32): New.
12629 (vbfmlalbq_lane_f32): New.
12630 (vbfmlaltq_lane_f32): New.
12631 (vbfmlalbq_laneq_f32): New.
12632 (vbfmlaltq_laneq_f32): New.
12633 * config/arm/arm_neon_builtins.def (vmmla): New.
12638 (vfmab_laneq): New.
12639 (vfmat_laneq): New.
12640 * config/arm/iterators.md (BF_MA): New int iterator.
12641 (bt): New int attribute.
12642 (VQXBF): Copy of VQX with V8BF.
12643 * config/arm/neon.md (neon_vmmlav8bf): New insn.
12644 (neon_vfma<bt>v8bf): New insn.
12645 (neon_vfma<bt>_lanev8bf): New insn.
12646 (neon_vfma<bt>_laneqv8bf): New expand.
12647 (neon_vget_high<mode>): Changed iterator to VQXBF.
12648 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
12649 (UNSPEC_BFMAB): New UNSPEC.
12650 (UNSPEC_BFMAT): New UNSPEC.
12652 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12654 PR middle-end/93399
12655 * tree-pretty-print.h (pretty_print_string): Declare.
12656 * tree-pretty-print.c (pretty_print_string): Remove forward
12657 declaration, no longer static. Change nbytes parameter type
12658 from unsigned to size_t.
12659 * print-rtl.c (print_value) <case CONST_STRING>: Use
12660 pretty_print_string and for shrink way too long strings.
12662 2020-03-05 Richard Biener <rguenther@suse.de>
12663 Jakub Jelinek <jakub@redhat.com>
12665 PR tree-optimization/93582
12666 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR
12667 last operand as signed when looking for memset offset. Formatting
12670 2020-03-04 Andrew Pinski <apinski@marvell.com>
12673 * value-prof.c (dump_histogram_value): Use std::abs.
12675 2020-03-04 Martin Sebor <msebor@redhat.com>
12677 PR tree-optimization/93986
12678 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int
12679 operands to the same precision widest_int to avoid ICEs.
12681 2020-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
12684 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define.
12685 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry
12686 for OPTION_MASK_ALTIVEC.
12688 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12690 * config.gcc: Include the glibc-stdint.h header for zTPF.
12692 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12694 * config/s390/s390.c (s390_secondary_memory_needed): Disallow
12695 direct FPR-GPR copies.
12696 (s390_register_info_gprtofpr): Disallow GPR content to be saved in
12699 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12701 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new
12702 operands to the prologue_tpf expander.
12703 (s390_emit_epilogue): Likewise.
12704 (s390_option_override_internal): Do error checking and setup for
12706 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK)
12707 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET)
12708 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET)
12709 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions.
12710 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new
12711 operands for the check flag and the branch target.
12712 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check")
12713 ("mtpf-trace-hook-prologue-target")
12714 ("mtpf-trace-hook-epilogue-check")
12715 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New
12717 * doc/invoke.texi: Document -mtpf-trace-skip option. The other
12718 options are for debugging purposes and will not be documented
12721 2020-03-04 Jakub Jelinek <jakub@redhat.com>
12724 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
12726 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti
12727 argument. Change pd argument so that it can be modified. Turn
12728 constant non-CONSTRUCTOR store into non-constant if it is too large.
12729 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid
12731 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust
12734 2020-02-04 Richard Biener <rguenther@suse.de>
12736 PR tree-optimization/93964
12737 * graphite-isl-ast-to-gimple.c
12738 (gcc_expression_from_isl_ast_expr_id): Add intermediate
12739 conversion for pointer to integer converts.
12740 * graphite-scop-detection.c (assign_parameter_index_in_region):
12743 2020-03-04 Martin Liska <mliska@suse.cz>
12747 * doc/invoke.texi: Clarify --help=language and --help=common
12750 2020-03-04 Jakub Jelinek <jakub@redhat.com>
12752 PR tree-optimization/94001
12753 * tree-tailcall.c (process_assignment): Before comparing op1 to
12754 *ass_var, verify *ass_var is non-NULL.
12756 2020-03-04 Kito Cheng <kito.cheng@sifive.com>
12759 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
12762 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
12764 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
12765 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
12766 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
12767 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
12768 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
12769 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
12770 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
12771 (V_bf_low, V_bf_cvt_m): New mode attributes.
12772 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
12773 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
12774 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
12775 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
12776 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
12778 2020-03-03 Jakub Jelinek <jakub@redhat.com>
12780 PR tree-optimization/93582
12781 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
12782 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
12783 members, initialize them in the constructor and if mask is non-NULL,
12784 artificially push_partial_def {} for the portions of the mask that
12786 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
12787 val and return (void *)-1. Formatting fix.
12788 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
12790 (vn_reference_lookup): Add mask argument. If non-NULL, don't call
12791 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
12793 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
12795 (visit_stmt): Formatting fix.
12797 2020-03-03 Richard Biener <rguenther@suse.de>
12799 PR tree-optimization/93946
12800 * alias.h (refs_same_for_tbaa_p): Declare.
12801 * alias.c (refs_same_for_tbaa_p): New function.
12802 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
12804 * tree-ssa-scopedtables.h
12805 (avail_exprs_stack::lookup_avail_expr): Add output argument
12806 giving access to the hashtable entry.
12807 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
12809 * tree-ssa-dom.c: Include alias.h.
12810 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
12811 removing redundant store.
12812 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
12813 (ao_ref_init_from_vn_reference): Adjust prototype.
12814 (vn_reference_lookup_pieces): Likewise.
12815 (vn_reference_insert_pieces): Likewise.
12816 * tree-ssa-sccvn.c: Track base alias set in addition to alias
12818 (eliminate_dom_walker::eliminate_stmt): Also check base alias
12819 set when removing redundant stores.
12820 (visit_reference_op_store): Likewise.
12821 * dse.c (record_store): Adjust valdity check for redundant
12824 2020-03-03 Jakub Jelinek <jakub@redhat.com>
12827 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
12829 PR rtl-optimization/94002
12830 * explow.c (plus_constant): Punt if cst has VOIDmode and
12831 get_pool_mode is different from mode.
12833 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12835 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
12836 address has an offset which fits the scalling constraint for a
12837 load/store operation.
12838 (legitimate_scaled_address_p): Update use
12839 leigitimate_small_data_address_p.
12840 (arc_print_operand): Likewise.
12841 (arc_legitimate_address_p): Likewise.
12842 (legitimate_small_data_address_p): Likewise.
12844 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12846 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
12847 (fnmasf4_fpu): Likewise.
12849 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12851 * config/arc/arc.md (adddi3): Early expand the 64bit operation into
12853 (subdi3): Likewise.
12854 (adddi3_i): Remove pattern.
12855 (subdi3_i): Likewise.
12857 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12859 * config/arc/arc.md (eh_return): Add length info.
12861 2020-03-02 David Malcolm <dmalcolm@redhat.com>
12863 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
12865 2020-03-02 David Malcolm <dmalcolm@redhat.com>
12867 * doc/invoke.texi (Static Analyzer Options): Add
12868 -Wanalyzer-stale-setjmp-buffer to the list of options enabled
12871 2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
12874 * config/i386/i386.md (movstrict<mode>): Allow only
12875 registers with VALID_INT_MODE_P modes.
12877 2020-03-02 Andrew Stubbs <ams@codesourcery.com>
12879 * config/gcn/gcn-valu.md (dpp_move<mode>): New.
12880 (reduc_insn): Use 'U' and 'B' operand codes.
12881 (reduc_<reduc_op>_scal_<mode>): Allow all types.
12882 (reduc_<reduc_op>_scal_v64di): Delete.
12883 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
12884 (*plus_carry_dpp_shr_v64si): Change to ...
12885 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
12886 (mov_from_lane63_v64di): Change to ...
12887 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
12888 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
12889 Support UNSPEC_MOV_DPP_SHR output formats.
12890 (gcn_expand_reduc_scalar): Add "use_moves" reductions.
12891 Add "use_extends" reductions.
12892 (print_operand_address): Add 'I' and 'U' codes.
12893 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
12895 2020-03-02 Martin Liska <mliska@suse.cz>
12897 * lto-wrapper.c: Fix typo in comment about
12898 C++ standard version.
12900 2020-03-01 Martin Sebor <msebor@redhat.com>
12903 * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
12905 2020-03-01 Martin Sebor <msebor@redhat.com>
12907 PR middle-end/93829
12908 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
12909 of a pointer in the outermost ADDR_EXPRs.
12911 2020-02-28 Jeff Law <law@redhat.com>
12913 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
12914 * config/v850/v850.c (v850_asm_trampoline_template): Update
12917 2020-02-28 Michael Meissner <meissner@linux.ibm.com>
12920 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
12923 2020-02-28 Martin Liska <mliska@suse.cz>
12926 * configure.ac: Improve detection of ld_date by requiring
12927 either two dashes or none.
12928 * configure: Regenerate.
12930 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
12932 PR rtl-optimization/93564
12933 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
12934 do not honor reg alloc order.
12936 2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
12939 * config/aarch64/aarch64.c (aarch64_override_options): Fix
12940 misleading warning string.
12942 2020-02-27 Martin Sebor <msebor@redhat.com>
12944 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
12946 2020-02-27 Michael Meissner <meissner@linux.ibm.com>
12949 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
12950 Split the insn into two parts. This insn only does variable
12951 extract from a register.
12952 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
12953 variable extract from memory.
12954 (vsx_extract_v4sf_var): Split the insn into two parts. This insn
12955 only does variable extract from a register.
12956 (vsx_extract_v4sf_var_load): New insn, do variable extract from
12958 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
12959 into two parts. This insn only does variable extract from a
12961 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
12962 do variable extract from memory.
12964 2020-02-27 Martin Jambor <mjambor@suse.cz>
12965 Feng Xue <fxue@os.amperecomputing.com>
12968 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
12969 new function calls_same_node_or_its_all_contexts_clone_p.
12970 (cgraph_edge_brings_value_p): Use it.
12971 (cgraph_edge_brings_value_p): Likewise.
12972 (self_recursive_pass_through_p): Return false if caller is a clone.
12973 (self_recursive_agg_pass_through_p): Likewise.
12975 2020-02-27 Jan Hubicka <hubicka@ucw.cz>
12977 PR middle-end/92152
12978 * alias.c (ends_tbaa_access_path_p): Break out from ...
12979 (component_uses_parent_alias_set_from): ... here.
12980 * alias.h (ends_tbaa_access_path_p): Declare.
12981 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
12982 handle trailing arrays past end of tbaa access path.
12983 (aliasing_component_refs_p): ... here; likewise.
12984 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
12985 path; disambiguate also past end of it.
12986 (nonoverlapping_component_refs_p): Use only TBAA segment of the access
12989 2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
12991 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
12992 beginning of the file.
12993 (vcreate_bf16, vcombine_bf16): New.
12994 (vdup_n_bf16, vdupq_n_bf16): New.
12995 (vdup_lane_bf16, vdup_laneq_bf16): New.
12996 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
12997 (vduph_lane_bf16, vduph_laneq_bf16): New.
12998 (vset_lane_bf16, vsetq_lane_bf16): New.
12999 (vget_lane_bf16, vgetq_lane_bf16): New.
13000 (vget_high_bf16, vget_low_bf16): New.
13001 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
13002 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
13003 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
13004 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
13005 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
13006 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
13007 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
13008 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
13009 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
13010 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
13011 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
13012 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
13013 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
13014 (vreinterpretq_bf16_p128): New.
13015 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
13016 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
13017 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
13018 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
13019 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
13020 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
13021 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
13022 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
13023 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
13024 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
13025 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
13026 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
13027 (vreinterpretq_p128_bf16): New.
13028 * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
13029 (V_elem): Likewise.
13030 (V_elem_l): Likewise.
13031 (VD_LANE): Likewise.
13033 (V_DOUBLE): Likewise.
13034 (VDQX): Add V4BF and V8BF.
13035 (V_two_elem, V_three_elem, V_four_elem): Likewise.
13037 (V_HALF): Likewise.
13038 (V_double_vector_mode): Likewise.
13039 (V_cmp_result): Likewise.
13040 (V_uf_sclr): Likewise.
13041 (V_sz_elem): Likewise.
13042 (Is_d_reg): Likewise.
13043 (V_mode_nunits): Likewise.
13044 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
13046 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
13048 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
13049 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
13050 (<expander><mode>3<exec>): Likewise.
13051 (<expander><mode>3): New.
13052 (v<expander><mode>3): New.
13053 (<expander><mode>3): New.
13054 (<expander><mode>3<exec>): Rename to ...
13055 (<expander>v64si3<exec>): ... this, and change modes to V64SI.
13056 * config/gcn/gcn.md (mnemonic): Use '%B' for not.
13058 2020-02-27 Alexandre Oliva <oliva@adacore.com>
13060 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
13063 2020-02-27 Richard Biener <rguenther@suse.de>
13065 PR tree-optimization/93508
13066 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
13067 non-_CHK variants. Valueize their length arguments.
13069 2020-02-27 Richard Biener <rguenther@suse.de>
13071 PR tree-optimization/93953
13072 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
13073 to the hash-map entry.
13075 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
13077 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
13079 2020-02-27 Mark Williams <mwilliams@fb.com>
13081 * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
13082 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
13083 -ffile-prefix-map and -fmacro-prefix-map.
13084 * lto-streamer-out.c: Include file-prefix-map.h.
13085 (lto_output_location): Remap the file part of locations.
13087 2020-02-27 Jakub Jelinek <jakub@redhat.com>
13090 * gimplify.c (gimplify_init_constructor): Don't promote readonly
13091 DECL_REGISTER variables to TREE_STATIC.
13093 PR tree-optimization/93582
13094 PR tree-optimization/93945
13095 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
13096 non-zero INTEGER_CST second argument and ref->offset or ref->size
13097 not a multiple of BITS_PER_UNIT.
13099 2020-02-27 Jonathan Wakely <jwakely@redhat.com>
13101 * doc/install.texi (Binaries): Update description of BullFreeware.
13103 2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
13107 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
13108 C++ Language Options, Warning Options, and Static Analyzer
13109 Options lists. Document negative form of options enabled by
13110 default. Move some things around to more accurately sort
13111 warnings by category.
13112 (C++ Dialect Options, Warning Options, Static Analyzer
13113 Options): Document negative form of options when enabled by
13114 default. Move some things around to more accurately sort
13115 warnings by category. Add some missing index entries.
13116 Light copy-editing.
13118 2020-02-26 Carl Love <cel@us.ibm.com>
13121 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
13122 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
13123 for the vector unsigned short arguments. It is also listed as the
13124 name of the built-in for arguments vector unsigned short,
13125 vector unsigned int and vector unsigned long long built-ins. The
13126 name of the builtins for these arguments should be:
13127 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
13128 __builtin_crypto_vpmsumd respectively.
13130 2020-02-26 Richard Biener <rguenther@suse.de>
13132 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
13133 and load permutation.
13135 2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
13137 PR middle-end/93843
13138 * optabs-tree.c (supportable_convert_operation): Reject types with
13141 2020-02-26 David Malcolm <dmalcolm@redhat.com>
13143 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
13145 2020-02-26 Jakub Jelinek <jakub@redhat.com>
13147 PR tree-optimization/93820
13148 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
13149 argument to ALL_INTEGER_CST_P boolean.
13150 (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
13151 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
13152 adjacent INTEGER_CST store into merged_store->only_constants like
13155 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13158 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
13160 * cfghooks.c (verify_flow_info): Likewise.
13161 * predict.c (combine_predictions_for_bb): Likewise.
13162 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
13163 sucessor -> successor.
13164 (find_traces_1_round): Fix comment typo, destinarion -> destination.
13165 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
13167 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
13168 message typo, sucessors -> successors.
13170 2020-02-25 Martin Sebor <msebor@redhat.com>
13172 * doc/extend.texi (attribute access): Correct an example.
13174 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
13176 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
13178 (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
13179 (VAR15, VAR16): New.
13180 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
13181 (VD): Enable for V4BF.
13183 (VQ): Enable for V8BF.
13185 (VQ_NO2E): Likewise.
13186 (VDBL, Vdbl): Add V4BF.
13187 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
13188 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
13189 (bfloat16x8x2_t): Likewise.
13190 (bfloat16x4x3_t): Likewise.
13191 (bfloat16x8x3_t): Likewise.
13192 (bfloat16x4x4_t): Likewise.
13193 (bfloat16x8x4_t): Likewise.
13194 (vcombine_bf16): New.
13195 (vld1_bf16, vld1_bf16_x2): New.
13196 (vld1_bf16_x3, vld1_bf16_x4): New.
13197 (vld1q_bf16, vld1q_bf16_x2): New.
13198 (vld1q_bf16_x3, vld1q_bf16_x4): New.
13199 (vld1_lane_bf16): New.
13200 (vld1q_lane_bf16): New.
13201 (vld1_dup_bf16): New.
13202 (vld1q_dup_bf16): New.
13205 (vld2_dup_bf16): New.
13206 (vld2q_dup_bf16): New.
13209 (vld3_dup_bf16): New.
13210 (vld3q_dup_bf16): New.
13213 (vld4_dup_bf16): New.
13214 (vld4q_dup_bf16): New.
13215 (vst1_bf16, vst1_bf16_x2): New.
13216 (vst1_bf16_x3, vst1_bf16_x4): New.
13217 (vst1q_bf16, vst1q_bf16_x2): New.
13218 (vst1q_bf16_x3, vst1q_bf16_x4): New.
13219 (vst1_lane_bf16): New.
13220 (vst1q_lane_bf16): New.
13228 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
13230 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
13231 (VALL_F16): Likewise.
13232 (VALLDI_F16): Likewise.
13234 (Vetype): Likewise.
13235 (vswap_width_name): Likewise.
13236 (VSWAP_WIDTH): Likewise.
13240 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
13241 (vget_lane_bf16, vgetq_lane_bf16): New.
13242 (vcreate_bf16): New.
13243 (vdup_n_bf16, vdupq_n_bf16): New.
13244 (vdup_lane_bf16, vdup_laneq_bf16): New.
13245 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
13246 (vduph_lane_bf16, vduph_laneq_bf16): New.
13247 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
13248 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
13249 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
13250 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
13251 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
13252 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
13253 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
13254 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
13255 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
13256 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
13257 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
13258 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
13259 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
13260 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
13261 (vreinterpretq_bf16_p128): New.
13262 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
13263 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
13264 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
13265 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
13266 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
13267 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
13268 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
13269 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
13270 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
13271 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
13272 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
13273 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
13274 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
13275 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
13276 (vreinterpretq_p128_bf16): New.
13278 2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
13280 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
13281 (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
13282 (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
13283 * config/arm/arm_neon_builtins.def (vbfdot): New entry.
13284 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
13285 * config/arm/iterators.md (VSF2BF): New attribute.
13286 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
13287 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
13288 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
13290 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
13292 * config/arm/arm.md (required_for_purecode): New attribute.
13293 (enabled): Handle required_for_purecode.
13294 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
13295 work with -mpure-code.
13297 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13299 PR rtl-optimization/93908
13300 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
13303 2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
13305 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
13307 2020-02-25 Roman Zhuykov <zhroma@ispras.ru>
13309 * doc/install.texi (--enable-checking): Adjust wording.
13311 2020-02-25 Richard Biener <rguenther@suse.de>
13313 PR tree-optimization/93868
13314 * tree-vect-slp.c (slp_copy_subtree): New function.
13315 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before
13316 re-arranging stmts in it.
13318 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13320 PR middle-end/93874
13321 * passes.c (pass_manager::dump_passes): Create a cgraph node for the
13322 dummy function and remove it at the end.
13324 PR translation/93864
13325 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo
13326 paramter -> parameter.
13327 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise.
13328 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise.
13330 2020-02-24 Roman Zhuykov <zhroma@ispras.ru>
13332 * doc/install.texi (--enable-checking): Properly document current
13334 (--enable-stage1-checking): Minor clarification about bootstrap.
13336 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13339 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that
13340 -fanalyzer-checker=taint is also required.
13341 (-fanalyzer-checker=): Note that providing this option enables the
13342 given checker, and doing so may be required for checkers that are
13343 disabled by default.
13345 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13347 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows
13348 significant control flow events; add a "3" which shows all
13349 control flow events; the old "3" becomes "4".
13351 2020-02-24 Jakub Jelinek <jakub@redhat.com>
13353 PR tree-optimization/93582
13354 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider
13355 pd.offset and pd.size to be counted in bits rather than bytes, add
13356 support for maxsizei that is not a multiple of BITS_PER_UNIT and
13357 handle bitfield stores and loads.
13358 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with
13359 uncomparable quantities - bytes vs. bits. Allow push_partial_def
13360 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust
13361 pd.offset/pd.size to be counted in bits rather than bytes.
13362 Formatting fix. Rename shadowed len variable to buflen.
13364 2020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
13365 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org>
13368 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function.
13369 (driver::main): Call putenv_COLLECT_AS_OPTIONS.
13370 * opts-common.c (parse_options_from_collect_gcc_options): New function.
13371 (prepend_xassembler_to_collect_as_options): Likewise.
13372 * opts.h (parse_options_from_collect_gcc_options): Declare prototype.
13373 (prepend_xassembler_to_collect_as_options): Likewise.
13374 * lto-opts.c (lto_write_options): Stream assembler options
13375 in COLLECT_AS_OPTIONS.
13376 * lto-wrapper.c (xassembler_options_error): New static variable.
13377 (get_options_from_collect_gcc_options): Move parsing options code to
13378 parse_options_from_collect_gcc_options and call it.
13379 (merge_and_complain): Validate -Xassembler options.
13380 (append_compiler_options): Handle OPT_Xassembler.
13381 (run_gcc): Append command line -Xassembler options to
13382 collect_gcc_options.
13383 * doc/invoke.texi: Add documentation about using Xassembler
13386 2020-02-24 Kito Cheng <kito.cheng@sifive.com>
13388 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen
13390 (riscv_rtx_costs): Update cost model for LTGT.
13392 2020-02-23 Vladimir Makarov <vmakarov@redhat.com>
13394 PR rtl-optimization/93564
13395 * ira-color.c (struct update_cost_queue_elem): New member start.
13396 (queue_update_cost, get_next_update_cost): Add new arg start.
13397 (allocnos_conflict_p): New function.
13398 (update_costs_from_allocno): Add new arg conflict_cost_update_p.
13399 Add checking conflicts with allocnos_conflict_p.
13400 (update_costs_from_prefs, restore_costs_from_copies): Adjust
13401 update_costs_from_allocno calls.
13402 (update_conflict_hard_regno_costs): Add checking conflicts with
13403 allocnos_conflict_p. Adjust calls of queue_update_cost and
13404 get_next_update_cost.
13405 (assign_hard_reg): Adjust calls of queue_update_cost. Add
13407 (bucket_allocno_compare_func): Restore previous version.
13409 2020-02-21 John David Anglin <danglin@gcc.gnu.org>
13411 * config/pa/pa.c (pa_function_value): Fix check for word and
13412 double-word size when handling aggregate return values.
13413 * config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate
13414 that homogeneous SFmode and DFmode aggregates are passed and returned
13415 in general registers.
13417 2020-02-21 Jakub Jelinek <jakub@redhat.com>
13419 PR translation/93759
13420 * opts.c (print_filtered_help): Translate help before appending
13421 messages to it rather than after that.
13423 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13425 PR rtl-optimization/PR92989
13426 * lra-lives.c (process_bb_lives): Restore the original order
13427 of the bb liveness update. Call make_hard_regno_dead for each
13428 register clobbered at the start of an EH receiver.
13430 2020-02-18 Feng Xue <fxue@os.amperecomputing.com>
13433 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as
13434 self-recursively generated.
13436 2020-02-21 Iain Sandoe <iain@sandoe.co.uk>
13439 * config/darwin-c.c (pop_field_alignment): Adjust quoting of
13442 2020-02-21 Mihail Ionescu <mihail.ionescu@arm.com>
13444 * doc/sourcebuild.texi (arm_v8_1m_mve_ok):
13445 Document new target supports option.
13447 2020-02-21 Dennis Zhang <dennis.zhang@arm.com>
13449 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New.
13450 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New.
13451 * config/arm/iterators.md (MATMUL): New iterator.
13452 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US.
13453 (mmla_sfx): New attribute.
13454 * config/arm/neon.md (neon_<sup>mmlav16qi): New.
13455 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New.
13456 (UNSPEC_MATMUL_US): New.
13458 2020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13460 * config/arm/arm.md: Prevent scalar shifts from being used when big
13463 2020-02-21 Jan Hubicka <hubicka@ucw.cz>
13464 Richard Biener <rguenther@suse.de>
13466 PR tree-optimization/93586
13467 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk
13468 after mismatched array refs; do not sure type size information to
13469 recover from unmatched referneces with !flag_strict_aliasing_p.
13471 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13473 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
13474 (gather_load<mode>v64si): ... this and set operand 2 to V64SI.
13475 (scatter_store<mode>): Rename to ...
13476 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
13477 (scatter<mode>_exec): Delete. Move contents ...
13478 (mask_scatter_store<mode>): ... here, and rename that to ...
13479 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
13480 Remove mode conversion.
13481 (mask_gather_load<mode>): Rename to ...
13482 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
13483 Remove mode conversion.
13484 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
13486 2020-02-21 Martin Jambor <mjambor@suse.cz>
13488 PR tree-optimization/93845
13489 * tree-sra.c (verify_sra_access_forest): Only test access size of
13492 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13494 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
13495 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
13496 (addv64di3_exec): Likewise.
13497 (subv64di3): Likewise.
13498 (subv64di3_exec): Likewise.
13499 (addv64di3_zext): Likewise.
13500 (addv64di3_zext_exec): Likewise.
13501 (addv64di3_zext_dup): Likewise.
13502 (addv64di3_zext_dup_exec): Likewise.
13503 (addv64di3_zext_dup2): Likewise.
13504 (addv64di3_zext_dup2_exec): Likewise.
13505 (addv64di3_sext_dup2): Likewise.
13506 (addv64di3_sext_dup2_exec): Likewise.
13507 (<expander>v64di3): Likewise.
13508 (<expander>v64di3_exec): Likewise.
13509 (*<reduc_op>_dpp_shr_v64di): Likewise.
13510 (*plus_carry_dpp_shr_v64di): Likewise.
13511 * config/gcn/gcn.md (adddi3): Likewise.
13512 (addptrdi3): Likewise.
13513 (<expander>di3): Likewise.
13515 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13517 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
13519 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13521 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
13522 support. Use aarch64_emit_mult instead of emitting multiplication
13523 instructions directly.
13524 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2)
13525 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders.
13527 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13529 * config/aarch64/aarch64.c (aarch64_emit_mult): New function.
13530 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult
13531 instead of emitting multiplication instructions directly.
13532 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator.
13533 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>)
13534 (@aarch64_frecps<mode>): New expanders.
13536 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13538 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate
13539 on and produce uint64_ts rather than ints.
13540 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts.
13541 (cpu_approx_modes): Change the fields from unsigned int to uint64_t.
13543 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13545 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create
13546 an unused xmsk register when handling approximate rsqrt.
13548 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13550 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted
13551 flag_finite_math_only condition.
13553 2020-02-20 Uroš Bizjak <ubizjak@gmail.com>
13556 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand
13557 to destination operand for shufps alternative.
13558 (*vec_extractv2si_1): Ditto.
13560 2020-02-20 Peter Bergner <bergner@linux.ibm.com>
13563 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
13566 2020-02-20 Martin Liska <mliska@suse.cz>
13568 PR translation/93831
13569 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode.
13571 2020-02-20 Martin Liska <mliska@suse.cz>
13573 PR translation/93830
13574 * common/config/avr/avr-common.c: Remote trailing "|".
13576 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13578 * collect2.c (maybe_run_lto_and_relink): Fix typo in
13581 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13583 PR tree-optimization/93767
13584 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the
13585 access-size bias from the offset calculations for negative strides.
13587 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13589 * collect2.c (c_file, o_file): Make const again.
13590 (ldout,lderrout, dump_ld_file): Remove.
13591 (tool_cleanup): Avoid calling not signal-safe functions.
13592 (maybe_run_lto_and_relink): Avoid possible signal handler
13593 access to unintialzed memory (lto_o_files).
13594 (main): Avoid leaking temp files in $TMPDIR.
13595 Initialize c_file/o_file with concat, which avoids exposing
13596 uninitialized memory to signal handler, which calls unlink(!).
13597 Avoid calling maybe_unlink when the main function returns,
13598 since the atexit handler is already doing this.
13599 * collect2.h (dump_ld_file, ldout, lderrout): Remove.
13601 2020-02-19 Martin Jambor <mjambor@suse.cz>
13603 PR tree-optimization/93776
13604 * tree-sra.c (create_access): Do not create zero size accesses.
13605 (get_access_for_expr): Do not search for zero sized accesses.
13607 2020-02-19 Martin Jambor <mjambor@suse.cz>
13609 PR tree-optimization/93667
13610 * tree-sra.c (scalarizable_type_p): Return false if record fields
13611 do not follow wach other.
13613 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
13615 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
13616 rather than fmv.x.s/fmv.s.x.
13618 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
13620 * config/aarch64/aarch64-simd-builtins.def
13621 (intrinsic_vec_smult_lo_): New.
13622 (intrinsic_vec_umult_lo_): Likewise.
13623 (vec_widen_smult_hi_): Likewise.
13624 (vec_widen_umult_hi_): Likewise.
13625 * config/aarch64/aarch64-simd.md
13626 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New.
13627 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics.
13628 (vmull_high_s16): Likewise.
13629 (vmull_high_s32): Likewise.
13630 (vmull_high_u8): Likewise.
13631 (vmull_high_u16): Likewise.
13632 (vmull_high_u32): Likewise.
13633 (vmull_s8): Likewise.
13634 (vmull_s16): Likewise.
13635 (vmull_s32): Likewise.
13636 (vmull_u8): Likewise.
13637 (vmull_u16): Likewise.
13638 (vmull_u32): Likewise.
13640 2020-02-18 Martin Liska <mliska@suse.cz>
13642 * value-prof.c (stream_out_histogram_value): Restore LTO PGO
13643 bootstrap by missing removal of invalid sanity check.
13645 2020-02-18 Martin Liska <mliska@suse.cz>
13648 * ipa-icf-gimple.c (func_checker::compare_gimple_assign):
13649 Always compare LHS of gimple_assign.
13651 2020-02-18 Martin Liska <mliska@suse.cz>
13654 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute
13655 and return type of functions.
13656 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl):
13657 Drop MALLOC attribute for void functions.
13658 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop
13659 malloc_state for a new VOID clone.
13661 2020-02-18 Martin Liska <mliska@suse.cz>
13664 * common.opt: Add -fprofile-reproducibility.
13665 * doc/invoke.texi: Document it.
13666 * value-prof.c (dump_histogram_value):
13667 Document and support behavior for counters[0]
13668 being a negative value.
13669 (get_nth_most_common_value): Handle negative
13670 counters[0] in respect to flag_profile_reproducible.
13672 2020-02-18 Jakub Jelinek <jakub@redhat.com>
13675 * cgraph.c (verify_speculative_call): Use speculative_id instead of
13676 speculative_uid in messages. Remove trailing whitespace from error
13677 message. Use num_speculative_call_targets instead of
13678 num_speculative_targets in a message.
13679 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in
13680 edge messages and stmt instead of cal_stmt in reference message.
13682 PR tree-optimization/93780
13683 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p
13684 before calling build_vector_type.
13685 (execute_update_addresses_taken): Likewise.
13688 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help
13689 typo, functoin -> function.
13690 * tree.c (free_lang_data_in_decl): Fix comment typo,
13691 functoin -> function.
13692 * ipa-visibility.c (cgraph_externally_visible_p): Likewise.
13694 2020-02-17 David Malcolm <dmalcolm@redhat.com>
13696 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs
13698 (print_option_information): Don't call get_option_url if URLs
13701 2020-02-17 Alexandre Oliva <oliva@adacore.com>
13703 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete
13704 handling of register_common-less targets.
13706 2020-02-17 Martin Liska <mliska@suse.cz>
13709 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar.
13711 2020-02-17 Martin Liska <mliska@suse.cz>
13713 PR translation/93755
13714 * config/rs6000/rs6000.c (rs6000_option_override_internal):
13717 2020-02-17 Martin Liska <mliska@suse.cz>
13720 * config/rx/elf.opt: Fix typo.
13722 2020-02-17 Richard Biener <rguenther@suse.de>
13725 * opts-global.c (print_ignored_options): Use inform and
13728 2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
13731 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
13733 2020-02-16 Uroš Bizjak <ubizjak@gmail.com>
13736 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2.
13737 (atan2<mode>3): Update operand order in the call to gen_atan2xf3.
13739 2020-02-15 Jason Merrill <jason@redhat.com>
13741 * doc/invoke.texi (C Dialect Options): Add -std=c++20.
13743 2020-02-15 Jakub Jelinek <jakub@redhat.com>
13745 PR tree-optimization/93744
13746 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0,
13747 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A,
13748 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make
13749 sure @2 in the first and @1 in the other patterns has no side-effects.
13751 2020-02-15 David Malcolm <dmalcolm@redhat.com>
13752 Bernd Edlinger <bernd.edlinger@hotmail.de>
13756 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
13757 * configure.ac (--with-diagnostics-urls): New configuration
13758 option, based on --with-diagnostics-color.
13759 (DIAGNOSTICS_URLS_DEFAULT): New define.
13760 * config.h: Regenerate.
13761 * configure: Regenerate.
13762 * diagnostic.c (diagnostic_urls_init): Handle -1 for
13763 DIAGNOSTICS_URLS_DEFAULT from configure-time
13764 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
13765 and TERM_URLS environment variable.
13766 * diagnostic-url.h (diagnostic_url_format): New enum type.
13767 (diagnostic_urls_enabled_p): rename to...
13768 (determine_url_format): ... this, and change return type.
13769 * diagnostic-color.c (parse_env_vars_for_urls): New helper function.
13770 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
13771 the linux console, and mingw.
13772 (diagnostic_urls_enabled_p): rename to...
13773 (determine_url_format): ... this, and adjust.
13774 * pretty-print.h (pretty_printer::show_urls): rename to...
13775 (pretty_printer::url_format): ... this, and change to enum.
13776 * pretty-print.c (pretty_printer::pretty_printer,
13777 pp_begin_url, pp_end_url, test_urls): Adjust.
13778 * doc/install.texi (--with-diagnostics-urls): Document the new
13779 configuration option.
13780 (--with-diagnostics-color): Document the existing interaction
13781 with GCC_COLORS better.
13782 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
13783 vindex reference. Update description of defaults based on the above.
13784 (-fdiagnostics-color): Update description of how -fdiagnostics-color
13785 interacts with GCC_COLORS.
13787 2020-02-14 Eric Botcazou <ebotcazou@adacore.com>
13790 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in
13791 conjunction with TARGET_GNU_TLS in early return.
13793 2020-02-14 Alexander Monakov <amonakov@ispras.ru>
13795 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if
13796 the mode is not wider than UNITS_PER_WORD.
13798 2020-02-14 Martin Jambor <mjambor@suse.cz>
13800 PR tree-optimization/93516
13801 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create
13802 access of the same type as the parent.
13803 (propagate_subaccesses_from_lhs): Likewise.
13805 2020-02-14 Hongtao Liu <hongtao.liu@intel.com>
13808 * config/i386/avx512vbmi2intrin.h
13809 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16,
13810 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32,
13811 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
13812 _m512_shrdi_epi64, _m512_mask_shrdi_epi64,
13813 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16,
13814 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16,
13815 _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
13816 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
13817 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo
13818 of lacking a closing parenthesis.
13819 * config/i386/avx512vbmi2vlintrin.h
13820 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16,
13821 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32,
13822 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32,
13823 _m256_shrdi_epi64, _m256_mask_shrdi_epi64,
13824 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16,
13825 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
13826 _mm256_shldi_epi32, _mm256_mask_shldi_epi32,
13827 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64,
13828 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64,
13829 _mm_shrdi_epi16, _mm_mask_shrdi_epi16,
13830 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32,
13831 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32,
13832 _mm_shrdi_epi64, _mm_mask_shrdi_epi64,
13833 _m_maskz_shrdi_epi64, _mm_shldi_epi16,
13834 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16,
13835 _mm_shldi_epi32, _mm_mask_shldi_epi32,
13836 _mm_maskz_shldi_epi32, _mm_shldi_epi64,
13837 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto.
13839 2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
13842 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
13843 the target function entry.
13845 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13847 * common/config/arc/arc-common.c (arc_option_optimization_table):
13848 Disable if-conversion step when optimized for size.
13850 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13852 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
13853 R12-R15 are always in ARCOMPACT16_REGS register class.
13854 * config/arc/arc.opt (mq-class): Deprecate.
13855 * config/arc/constraint.md ("q"): Remove dependency on mq-class
13857 * doc/invoke.texi (mq-class): Update text.
13858 * common/config/arc/arc-common.c (arc_option_optimization_table):
13861 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13863 * config/arc/arc.c (arc_insn_cost): New function.
13864 (TARGET_INSN_COST): Define.
13865 * config/arc/arc.md (cost): New attribute.
13866 (add_n): Use arc_nonmemory_operand.
13867 (ashlsi3_insn): Likewise, also update constraints.
13868 (ashrsi3_insn): Likewise.
13869 (rotrsi3): Likewise.
13870 (add_shift): Likewise.
13871 * config/arc/predicates.md (arc_nonmemory_operand): New predicate.
13873 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13875 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
13877 (umulsidi_600): Likewise.
13879 2020-02-13 Jakub Jelinek <jakub@redhat.com>
13882 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8,
13883 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8,
13884 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8,
13885 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W,
13886 pass __A to the builtin followed by __W instead of __A followed by
13888 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32,
13889 _mm512_mask_popcnt_epi64): Likewise.
13890 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32,
13891 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64,
13892 _mm256_mask_popcnt_epi64): Likewise.
13894 PR tree-optimization/93582
13895 * fold-const.h (shift_bytes_in_array_left,
13896 shift_bytes_in_array_right): Declare.
13897 * fold-const.c (shift_bytes_in_array_left,
13898 shift_bytes_in_array_right): New function, moved from
13899 gimple-ssa-store-merging.c, no longer static.
13900 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move
13901 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left.
13902 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c.
13903 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of
13904 shift_bytes_in_array.
13905 (verify_shift_bytes_in_array): Rename to ...
13906 (verify_shift_bytes_in_array_left): ... this. Use
13907 shift_bytes_in_array_left instead of shift_bytes_in_array.
13908 (store_merging_c_tests): Call verify_shift_bytes_in_array_left
13909 instead of verify_shift_bytes_in_array.
13910 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr
13911 / native_interpret_expr where the store covers all needed bits,
13912 punt on PDP-endian, otherwise allow all involved offsets and sizes
13913 not to be byte-aligned.
13916 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and
13917 use const_0_to_255_operand predicate instead of immediate_operand.
13918 (avx512dq_fpclass<mode><mask_scalar_merge_name>,
13919 avx512dq_vmfpclass<mode><mask_scalar_merge_name>,
13920 vgf2p8affineinvqb_<mode><mask_name>,
13921 vgf2p8affineqb_<mode><mask_name>): Drop mode from
13922 const_0_to_255_operand predicated operands.
13924 2020-02-12 Jeff Law <law@redhat.com>
13926 * config/h8300/h8300.md (comparison shortening peepholes): Use
13927 a mode iterator to merge the HImode and SImode peepholes.
13929 2020-02-12 Jakub Jelinek <jakub@redhat.com>
13931 PR middle-end/93663
13932 * real.c (is_even): Make static. Function comment fix.
13933 (is_halfway_below): Make static, don't assert R is not inf/nan,
13934 instead return false for those. Small formatting fixes.
13936 2020-02-12 Martin Sebor <msebor@redhat.com>
13938 PR middle-end/93646
13939 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename...
13940 (handle_builtin_stxncpy_strncat): ...to this. Change first argument.
13941 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation.
13942 (strlen_check_and_optimize_call): Adjust callee name.
13944 2020-02-12 Jeff Law <law@redhat.com>
13946 * config/h8300/h8300.md (comparison shortening peepholes): Drop
13947 (and (xor)) variant. Combine other two into single peephole.
13949 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
13951 PR rtl-optimization/93565
13952 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs.
13954 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
13956 * config/aarch64/aarch64-simd.md
13957 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
13958 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
13959 generating separate ADDV and zero_extend patterns.
13960 * config/aarch64/iterators.md (VDQV_E): New iterator.
13962 2020-02-12 Jeff Law <law@redhat.com>
13964 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,
13965 expanders, splits, etc.
13966 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise.
13967 (stpcpy_internal_<mode>, stpcpy splitter): Likewise.
13968 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise.
13969 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function.
13970 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise
13971 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused
13972 function prototype.
13973 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
13975 2020-02-12 Jakub Jelinek <jakub@redhat.com>
13978 * config/i386/sse.md (VI48F_256_DQ): New mode iterator.
13979 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove
13980 TARGET_AVX512DQ from condition.
13981 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition>
13982 instead of <mask_mode512bit_condition> in condition. If
13983 TARGET_AVX512DQ is false, emit vextract*64x4 instead of
13985 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition>
13988 2020-02-12 Kewen Lin <linkw@gcc.gnu.org>
13991 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
13993 2020-02-12 Segher Boessenkool <segher@kernel.crashing.org>
13995 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof
13996 where strlen is more legible.
13997 (rs6000_builtin_vectorized_libmass): Ditto.
13998 (rs6000_print_options_internal): Ditto.
14000 2020-02-11 Martin Sebor <msebor@redhat.com>
14002 PR tree-optimization/93683
14003 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
14005 2020-02-11 Michael Meissner <meissner@linux.ibm.com>
14007 * config/rs6000/predicates.md (cint34_operand): Rename the
14008 -mprefixed-addr option to be -mprefixed.
14009 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
14010 the -mprefixed-addr option to be -mprefixed.
14011 (OTHER_FUTURE_MASKS): Likewise.
14012 (POWERPC_MASKS): Likewise.
14013 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
14014 the -mprefixed-addr option to be -mprefixed. Change error
14015 messages to refer to -mprefixed.
14016 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be
14018 (rs6000_legitimate_offset_address_p): Likewise.
14019 (rs6000_mode_dependent_address): Likewise.
14020 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
14021 "-mprefixed" for target attributes and pragmas.
14022 (address_to_insn_form): Rename the -mprefixed-addr option to be
14024 (rs6000_adjust_insn_length): Likewise.
14025 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
14026 -mprefixed-addr option to be -mprefixed.
14027 (ASM_OUTPUT_OPCODE): Likewise.
14028 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the
14029 -mprefixed-addr option to be -mprefixed.
14030 * config/rs6000/rs6000.opt (-mprefixed): Rename the
14031 -mprefixed-addr option to be prefixed. Change the option from
14032 being undocumented to being documented.
14033 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the
14034 -mprefixed option. Update the -mpcrel documentation to mention
14037 2020-02-11 Hans-Peter Nilsson <hp@axis.com>
14039 * ira-conflicts.c (print_hard_reg_set): Correct output for sets
14040 including FIRST_PSEUDO_REGISTER - 1.
14041 * ira-color.c (print_hard_reg_set): Ditto.
14043 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14045 * config/arm/arm-builtins.c (enum arm_type_qualifiers):
14046 (USTERNOP_QUALIFIERS): New define.
14047 (USMAC_LANE_QUADTUP_QUALIFIERS): New define.
14048 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
14049 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
14050 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
14051 * config/arm/arm_neon.h (vusdot_s32): New.
14052 (vusdot_lane_s32): New.
14053 (vusdotq_lane_s32): New.
14054 (vsudot_lane_s32): New.
14055 (vsudotq_lane_s32): New.
14056 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
14057 * config/arm/iterators.md (DOTPROD_I8MM): New.
14058 (sup, opsuffix): Add <us/su>.
14059 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
14060 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
14062 2020-02-11 Richard Biener <rguenther@suse.de>
14064 PR tree-optimization/93661
14065 PR tree-optimization/93662
14066 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard
14067 tree_to_poly_int64.
14068 * tree-sra.c (get_access_for_expr): Likewise.
14070 2020-02-10 Jakub Jelinek <jakub@redhat.com>
14073 * config/i386/sse.md (VI_256_AVX2): New mode iterator.
14074 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256.
14075 Change condition from TARGET_AVX2 to TARGET_AVX.
14077 2020-02-10 Iain Sandoe <iain@sandoe.co.uk>
14080 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last
14081 argument of strncmp.
14083 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
14085 Try to generate zero-based comparisons.
14086 * config/cris/cris.c (cris_reduce_compare): New function.
14087 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype.
14088 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4")
14089 (cstore<mode>4"): Apply cris_reduce_compare in expanders.
14091 2020-02-10 Richard Earnshaw <rearnsha@arm.com>
14094 * config/arm/arm.md (movsi_compare0): Allow SP as a source register
14095 in Thumb state and also as a destination in Arm state. Add T16
14098 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
14100 * md.texi (Define Subst): Match closing paren in example.
14102 2020-02-10 Jakub Jelinek <jakub@redhat.com>
14106 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last
14107 arguments of strncmp.
14109 2020-02-10 Feng Xue <fxue@os.amperecomputing.com>
14112 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge
14113 but different source value.
14114 (adjust_callers_for_value_intersection): New function.
14115 (gather_edges_for_value): Adjust order of callers to let a
14116 non-self-recursive caller be the first element.
14117 (self_recursive_pass_through_p): Add a new parameter "simple", and
14118 check generalized self-recursive pass-through jump function.
14119 (self_recursive_agg_pass_through_p): Likewise.
14120 (find_more_scalar_values_for_callers_subset): Compute value from
14121 pass-through jump function for self-recursive.
14122 (intersect_with_plats): Cleanup previous implementation code for value
14123 itersection with self-recursive call edge.
14124 (intersect_with_agg_replacements): Likewise.
14125 (intersect_aggregates_with_edge): Deduce value from pass-through jump
14126 function for self-recursive call edge. Cleanup previous implementation
14127 code for value intersection with self-recursive call edge.
14128 (decide_whether_version_node): Remove dead callers and adjust order
14129 to let a non-self-recursive caller be the first element.
14131 2020-02-09 Uroš Bizjak <ubizjak@gmail.com>
14133 * recog.c: Move pass_split_before_sched2 code in front of
14134 pass_split_before_regstack.
14135 (pass_data_split_before_sched2): Rename pass to split3 from split4.
14136 (pass_data_split_before_regstack): Rename pass to split4 from split3.
14137 (rest_of_handle_split_before_sched2): Remove.
14138 (pass_split_before_sched2::execute): Unconditionally call
14140 (enable_split_before_sched2): New function.
14141 (pass_split_before_sched2::gate): Use enable_split_before_sched2.
14142 (pass_split_before_regstack::gate): Ditto.
14143 * config/nds32/nds32.c (nds32_split_double_word_load_store_p):
14144 Update name check for renamed split4 pass.
14145 * config/sh/sh.c (register_sh_passes): Update pass insertion
14146 point for renamed split4 pass.
14148 2020-02-09 Jakub Jelinek <jakub@redhat.com>
14150 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote
14151 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid
14152 copying them around between host and target.
14154 2020-02-08 Andrew Pinski <apinski@marvell.com>
14157 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
14158 STRICT_ALIGNMENT also.
14160 2020-02-08 Jim Wilson <jimw@sifive.com>
14163 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
14165 2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
14166 Jakub Jelinek <jakub@redhat.com>
14169 * config/i386/i386.h (CALL_USED_REGISTERS): Make
14170 xmm16-xmm31 call-used even in 64-bit ms-abi.
14172 2020-02-07 Dennis Zhang <dennis.zhang@arm.com>
14174 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry.
14175 (simd_ummla, simd_usmmla): Likewise.
14176 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New.
14177 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New.
14178 (vusmmlaq_s32): New.
14180 2020-02-07 Richard Biener <rguenther@suse.de>
14182 PR middle-end/93519
14183 * tree-inline.c (fold_marked_statements): Do a PRE walk,
14184 skipping unreachable regions.
14185 (optimize_inline_calls): Skip folding stmts when we didn't
14188 2020-02-07 H.J. Lu <hongjiu.lu@intel.com>
14191 * config/i386/i386.c (function_arg_ms_64): Add a type argument.
14192 Don't return aggregates with only SFmode and DFmode in SSE
14194 (ix86_function_arg): Pass arg.type to function_arg_ms_64.
14196 2020-02-07 Jakub Jelinek <jakub@redhat.com>
14199 * config/rs6000/rs6000-logue.c
14200 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn,
14201 if it fails, move rs into end_addr and retry. Add
14202 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or
14203 the insn pattern doesn't describe well what exactly happens to
14207 * config/i386/predicates.md (avx_identity_operand): Remove.
14208 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove.
14209 (avx_<castmode><avxsizesuffix>_<castmode>,
14210 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to
14211 a VEC_CONCAT of the operand and UNSPEC_CAST.
14212 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to
14213 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with
14217 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear
14218 recog_data.insn if distance_non_agu_define changed it.
14220 2020-02-06 Michael Meissner <meissner@linux.ibm.com>
14223 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
14224 we only had X-FORM (reg+reg) addressing for vectors. Also before
14225 ISA 3.0, we only had X-FORM addressing for scalars in the
14226 traditional Altivec registers.
14228 2020-02-06 <zhongyunde@huawei.com>
14229 Vladimir Makarov <vmakarov@redhat.com>
14231 PR rtl-optimization/93561
14232 * lra-assigns.c (spill_for): Check that tested hard regno is not out of
14233 hard register range.
14235 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14237 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type
14240 2020-02-06 Segher Boessenkool <segher@kernel.crashing.org>
14242 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case
14243 where the low and the high 32 bits are equal to each other specially,
14244 with an rldimi instruction.
14246 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14248 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main.
14250 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14252 * config/arm/arm-tables.opt: Regenerate.
14254 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14257 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
14258 * config/aarch64/aarch64.c (aarch64_movk_shift): New function.
14259 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
14261 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14263 PR rtl-optimization/87763
14264 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
14266 2020-02-06 Delia Burduv <delia.burduv@arm.com>
14268 * config/aarch64/aarch64-simd-builtins.def
14269 (bfmlaq): New built-in function.
14270 (bfmlalb): New built-in function.
14271 (bfmlalt): New built-in function.
14272 (bfmlalb_lane): New built-in function.
14273 (bfmlalt_lane): New built-in function.
14274 * config/aarch64/aarch64-simd.md
14275 (aarch64_bfmmlaqv4sf): New pattern.
14276 (aarch64_bfmlal<bt>v4sf): New pattern.
14277 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern.
14278 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic.
14279 (vbfmlalbq_f32): New intrinsic.
14280 (vbfmlaltq_f32): New intrinsic.
14281 (vbfmlalbq_lane_f32): New intrinsic.
14282 (vbfmlaltq_lane_f32): New intrinsic.
14283 (vbfmlalbq_laneq_f32): New intrinsic.
14284 (vbfmlaltq_laneq_f32): New intrinsic.
14285 * config/aarch64/iterators.md (BF_MLA): New int iterator.
14286 (bt): New int attribute.
14288 2020-02-06 Uroš Bizjak <ubizjak@gmail.com>
14290 * config/i386/i386.md (*pushtf): Emit "#" instead of
14291 calling gcc_unreachable in insn output.
14294 (*pushsf_rex64): Ditto for alternatives other than 1.
14295 (*pushsf): Ditto for alternatives other than 1.
14297 2020-02-06 Martin Liska <mliska@suse.cz>
14299 PR gcov-profile/91971
14300 PR gcov-profile/93466
14301 * coverage.c (coverage_init): Revert mangling of
14302 path into filename. It can lead to huge filename length.
14303 Creation of subfolders seem more natural.
14305 2020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14308 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New.
14309 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs.
14310 Use arm_block_arith_comp_libfuncs_for_mode for HFmode.
14312 2020-02-06 Jakub Jelinek <jakub@redhat.com>
14315 * config/i386/predicates.md (avx_identity_operand): New predicate.
14316 * config/i386/sse.md (*avx_vec_concat<mode>_1): New
14317 define_insn_and_split.
14320 * omp-low.c (use_pointer_for_field): For nested constructs, also
14321 look for map clauses on target construct.
14322 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily
14323 taskreg_nesting_level.
14326 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding
14327 shared clause, call omp_notice_variable on outer context if any.
14329 2020-02-05 Jason Merrill <jason@redhat.com>
14332 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has
14333 non-zero address even if weak and not yet defined.
14335 2020-02-05 Martin Sebor <msebor@redhat.com>
14337 PR tree-optimization/92765
14338 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL.
14339 * tree-ssa-strlen.c (compute_string_length): Remove.
14340 (determine_min_objsize): Remove.
14341 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic.
14342 Avoid using type size as the upper bound on string length.
14343 (handle_builtin_string_cmp): Add an argument. Adjust.
14344 (strlen_check_and_optimize_call): Pass additional argument to
14345 handle_builtin_string_cmp.
14347 2020-02-05 Uroš Bizjak <ubizjak@gmail.com>
14349 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove.
14350 (*pushdi2_rex64 peephole2): Unconditionally split after
14351 epilogue_completed.
14352 (*ashl<mode>3_doubleword): Ditto.
14353 (*<shift_insn><mode>3_doubleword): Ditto.
14355 2020-02-05 Michael Meissner <meissner@linux.ibm.com>
14358 * config/rs6000/rs6000.c (get_vector_offset): Fix
14360 2020-02-05 Andrew Stubbs <ams@codesourcery.com>
14362 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
14364 2020-02-05 David Malcolm <dmalcolm@redhat.com>
14366 * doc/analyzer.texi
14367 (Special Functions for Debugging the Analyzer): Update description
14368 of __analyzer_dump_exploded_nodes.
14370 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14373 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
14374 include sets and not clobbers in the vzeroupper pattern.
14375 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
14376 the parallel has 17 (64-bit) or 9 (32-bit) elts.
14377 (*avx_vzeroupper_1): New define_insn_and_split.
14380 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets,
14381 don't run when !optimize.
14382 (pass_split_before_regstack::gate): For STACK_REGS targets, run even
14385 2020-02-05 Richard Biener <rguenther@suse.de>
14387 PR middle-end/90648
14388 * genmatch.c (dt_node::gen_kids_1): Emit number of argument
14389 checks before matching calls.
14391 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14393 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up
14394 function comment typo.
14396 PR middle-end/93555
14397 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or
14398 simd_clone_create failed when i == 0, adjust clone->nargs by
14401 2020-02-05 Martin Liska <mliska@suse.cz>
14404 * doc/invoke.texi: Document that one should
14405 not combine ASLR and -fpch.
14407 2020-02-04 Richard Biener <rguenther@suse.de>
14409 PR tree-optimization/93538
14410 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr.
14412 2020-02-04 Richard Biener <rguenther@suse.de>
14414 PR tree-optimization/91123
14415 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
14416 (vn_walk_cb_data::last_vuse): New member.
14417 (vn_walk_cb_data::saved_operands): Likewsie.
14418 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
14419 (vn_walk_cb_data::push_partial_def): Use finish.
14420 (vn_reference_lookup_2): Update last_vuse and use finish if
14421 we've saved operands.
14422 (vn_reference_lookup_3): Use finish and update calls to
14423 push_partial_defs everywhere. When translating through
14424 memcpy or aggregate copies save off operands and alias-set.
14425 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
14426 operation for redundant store removal.
14428 2020-02-04 Richard Biener <rguenther@suse.de>
14430 PR tree-optimization/92819
14431 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
14432 generating more stmts than before.
14434 2020-02-04 Martin Liska <mliska@suse.cz>
14436 * config/arm/arm.c (arm_gen_far_branch): Move the function
14437 outside of selftests.
14439 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14441 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
14442 function to adjust PC-relative vector addresses.
14443 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
14444 handle vectors with PC-relative addresses.
14446 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14448 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
14450 (hard_reg_and_mode_to_addr_mask): Delete.
14451 (rs6000_adjust_vec_address): If the original vector address
14452 was REG+REG or REG+OFFSET and the element is not zero, do the add
14453 of the elements in the original address before adding the offset
14454 for the vector element. Use address_to_insn_form to validate the
14455 address using the register being loaded, rather than guessing
14456 whether the address is a DS-FORM or DQ-FORM address.
14458 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14460 * config/rs6000/rs6000.c (get_vector_offset): New helper function
14461 to calculate the offset in memory from the start of a vector of a
14462 particular element. Add code to keep the element number in
14463 bounds if the element number is variable.
14464 (rs6000_adjust_vec_address): Move calculation of offset of the
14465 vector element to get_vector_offset.
14466 (rs6000_split_vec_extract_var): Do not do the initial AND of
14467 element here, move the code to get_vector_offset.
14469 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14471 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
14474 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
14476 * config/rs6000/constraints.md: Improve documentation.
14478 2020-02-03 Richard Earnshaw <rearnsha@arm.com>
14481 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md)
14482 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
14484 2020-02-03 Andrew Stubbs <ams@codesourcery.com>
14486 * config.gcc: Remove "carrizo" support.
14487 * config/gcn/gcn-opts.h (processor_type): Likewise.
14488 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
14489 * config/gcn/gcn.opt (gpu_type): Likewise.
14490 * config/gcn/t-omp-device: Likewise.
14492 2020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14495 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
14496 * config/arm/arm.c (arm_gen_far_branch): New function
14497 arm_gen_far_branch.
14498 * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
14500 2020-02-03 Julian Brown <julian@codesourcery.com>
14501 Tobias Burnus <tobias@codesourcery.com>
14503 * doc/invoke.texi: Update mention of OpenACC version to 2.6.
14505 2020-02-03 Jakub Jelinek <jakub@redhat.com>
14508 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
14509 valid RTL to sum up the lowest and second lowest bytes of the popcnt
14512 2020-02-02 Vladimir Makarov <vmakarov@redhat.com>
14514 PR rtl-optimization/91333
14515 * ira-color.c (struct allocno_color_data): Add member
14517 (init_allocno_threads): Set the member up.
14518 (bucket_allocno_compare_func): Add compare hard reg
14521 2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
14523 nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
14525 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14526 * config.in: Regenerated.
14527 * configure: Regenerated.
14528 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
14529 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14530 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.
14532 2020-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
14534 * configure: Regenerate.
14536 2020-01-31 Vladimir Makarov <vmakarov@redhat.com>
14538 PR rtl-optimization/91333
14539 * ira-color.c (bucket_allocno_compare_func): Move conflict hard
14540 reg preferences comparison up.
14542 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14544 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
14545 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
14546 aarch64-sve-builtins-base.h.
14547 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
14548 aarch64-sve-builtins-base.cc.
14549 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
14550 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14551 (svcvtnt): Declare.
14552 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
14553 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14554 (svcvtnt): New functions.
14555 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
14556 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14557 (svcvtnt): New functions.
14558 (svcvt): Add a form that converts f32 to bf16.
14559 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
14560 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
14562 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
14563 Treat B as bfloat16_t.
14564 (ternary_bfloat_lane_base): New class.
14565 (ternary_bfloat_def): Likewise.
14566 (ternary_bfloat): New shape.
14567 (ternary_bfloat_lane_def): New class.
14568 (ternary_bfloat_lane): New shape.
14569 (ternary_bfloat_lanex2_def): New class.
14570 (ternary_bfloat_lanex2): New shape.
14571 (ternary_bfloat_opt_n_def): New class.
14572 (ternary_bfloat_opt_n): New shape.
14573 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
14574 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
14575 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
14576 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
14577 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14578 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14579 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
14580 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
14581 the pattern off the narrow mode instead of the wider one.
14582 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
14583 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
14584 (sve_fp_op): Handle them.
14585 (SVE_BFLOAT_TERNARY_LONG): New int itertor.
14586 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
14588 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14590 * config/aarch64/arm_sve.h: Include arm_bf16.h.
14591 * config/aarch64/aarch64-modes.def (BF): Move definition before
14592 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF.
14593 (SVE_MODES): Handle BF modes.
14594 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
14596 (aarch64_full_sve_mode): Likewise.
14597 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
14599 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
14600 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
14601 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
14602 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
14604 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
14606 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
14607 (TYPES_all_data): Add bf16.
14608 (TYPES_reinterpret1, TYPES_reinterpret): Likewise.
14609 (register_tuple_type): Increase buffer size.
14610 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
14611 (bf16): New type suffix.
14612 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
14613 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
14614 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
14615 Change type from all_data to all_arith.
14616 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
14617 (svminp): Likewise.
14619 2020-01-31 Dennis Zhang <dennis.zhang@arm.com>
14620 Matthew Malcomson <matthew.malcomson@arm.com>
14621 Richard Sandiford <richard.sandiford@arm.com>
14623 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
14624 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
14625 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
14626 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define
14627 __ARM_FEATURE_MATMUL_FP64.
14628 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
14629 (sve): Add AARCH64_FL_F32MM to the list of extensions that should
14630 be disabled at the same time.
14631 (f32mm): New extension.
14632 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
14633 (AARCH64_FL_F64MM): Bump to the next bit up.
14634 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
14635 (TARGET_SVE_F64MM): New macros.
14636 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
14637 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
14638 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
14639 (UNSPEC_ZIP2Q): New unspeccs.
14640 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
14641 (optab, sur, perm_insn): Handle the new unspecs.
14642 (sve_fp_op): Handle UNSPEC_FMMLA. Resort.
14643 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
14644 TARGET_SVE_F64MM instead of separate tests.
14645 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
14646 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
14647 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
14648 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
14649 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
14650 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
14651 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
14652 (TYPES_s_signed): New macro.
14653 (TYPES_s_integer): Use it.
14654 (TYPES_d_float): New macro.
14655 (TYPES_d_data): Use it.
14656 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
14657 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
14658 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
14659 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
14660 (svmmla): New shape.
14661 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
14662 template parameters.
14663 (ternary_resize2_lane_base): Likewise.
14664 (ternary_resize2_base): New class.
14665 (ternary_qq_lane_base): Likewise.
14666 (ternary_intq_uintq_lane_def): Likewise.
14667 (ternary_intq_uintq_lane): New shape.
14668 (ternary_intq_uintq_opt_n_def): New class
14669 (ternary_intq_uintq_opt_n): New shape.
14670 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
14671 (ternary_uintq_intq_def): New class.
14672 (ternary_uintq_intq): New shape.
14673 (ternary_uintq_intq_lane_def): New class.
14674 (ternary_uintq_intq_lane): New shape.
14675 (ternary_uintq_intq_opt_n_def): New class.
14676 (ternary_uintq_intq_opt_n): New shape.
14677 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
14678 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
14679 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
14680 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
14682 (svdotprod_lane_impl): ...this new class.
14683 (svmmla_impl, svusdot_impl): New classes.
14684 (svdot_lane): Update to use svdotprod_lane_impl.
14685 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
14686 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
14688 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
14689 function, with no types defined.
14690 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
14691 AARCH64_FL_I8MM functions.
14692 (svmmla): New AARCH64_FL_F32MM function.
14693 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
14694 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
14695 AARCH64_FL_F64MM function.
14696 (REQUIRED_EXTENSIONS):
14698 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
14700 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
14703 2020-01-31 Uroš Bizjak <ubizjak@gmail.com>
14705 * config/i386/i386.md (*movoi_internal_avx): Do not check for
14706 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling.
14707 (*movti_internal): Do not check for
14708 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
14709 (*movtf_internal): Move check for TARGET_SSE2 and size optimization
14710 just after check for TARGET_AVX.
14711 (*movdf_internal): Ditto.
14712 * config/i386/mmx.md (*mov<mode>_internal): Do not check for
14713 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
14714 * config/i386/sse.md (mov<mode>_internal): Only check
14715 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check
14716 for TARGET_SSE2 and size optimization just after check for TARGET_AVX.
14717 (<sse>_andnot<mode>3<mask_name>): Move check for
14718 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX.
14719 (<code><mode>3<mask_name>): Ditto.
14720 (*andnot<mode>3): Ditto.
14721 (*andnottf3): Ditto.
14722 (*<code><mode>3): Ditto.
14723 (*<code>tf3): Ditto.
14724 (*andnot<VI:mode>3): Remove
14725 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling.
14726 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto.
14727 (*<code><VI12_AVX_AVX512F:mode>3): Ditto.
14728 (sse4_1_blendv<ssemodesuffix>): Ditto.
14729 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL):
14730 Explain that tune applies to 128bit instructions only.
14732 2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com>
14734 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count
14735 to definition of hsa_kernel_description. Parse assembly to find SGPR
14736 and VGPR count of kernel and store in hsa_kernel_description.
14738 2020-01-31 Tamar Christina <tamar.christina@arm.com>
14740 PR rtl-optimization/91838
14741 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case
14742 to truncate if allowed or reject combination.
14744 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
14746 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step.
14747 (find_inv_vars_cb): Likewise.
14749 2020-01-31 David Malcolm <dmalcolm@redhat.com>
14751 * calls.c (special_function_p): Split out the check for DECL_NAME
14752 being non-NULL and fndecl being extern at file scope into a
14753 new maybe_special_function_p and call it. Drop check for fndecl
14754 being non-NULL that was after a usage of DECL_NAME (fndecl).
14755 * tree.h (maybe_special_function_p): New inline function.
14757 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
14759 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ...
14760 (mask_gather_load<mode>): ... here, and zero-initialize the
14762 (maskload<mode>di): Zero-initialize the destination.
14763 * config/gcn/gcn.c:
14765 2020-01-30 David Malcolm <dmalcolm@redhat.com>
14768 * doc/analyzer.texi (Limitations): Note that constraints on
14769 floating-point values are currently ignored.
14771 2020-01-30 Jakub Jelinek <jakub@redhat.com>
14774 * symtab.c (symtab_node::noninterposable_alias): If localalias
14775 already exists, but is not usable, append numbers after it until
14776 a unique name is found. Formatting fix.
14778 PR middle-end/93505
14779 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range
14782 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
14784 * config/gcn/gcn.c (print_operand): Handle LTGT.
14785 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
14787 2020-01-30 Richard Biener <rguenther@suse.de>
14789 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST
14790 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE.
14792 2020-01-30 John David Anglin <danglin@gcc.gnu.org>
14794 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers
14795 without a DECL in .data.rel.ro.local.
14797 2020-01-30 Jakub Jelinek <jakub@redhat.com>
14800 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4
14804 * config/i386/sse.md
14805 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
14806 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
14807 any_extend code iterator instead of always zero_extend.
14808 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
14809 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
14810 Use any_extend code iterator instead of always zero_extend.
14811 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
14812 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
14813 Use any_extend code iterator instead of always zero_extend.
14814 (*sse2_pmovmskb_ext): New define_insn.
14815 (*sse2_pmovmskb_ext_lt): New define_insn_and_split.
14818 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
14819 (*popcountsi2_zext_falsedep): New define_insn.
14821 2020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
14823 * config.in: Regenerated.
14824 * configure: Regenerated.
14826 2020-01-29 Tobias Burnus <tobias@codesourcery.com>
14829 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as
14830 LLVM's assembler changed the default in version 9.
14832 2020-01-24 Jeff Law <law@redhat.com>
14834 PR tree-optimization/89689
14835 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure.
14837 2020-01-29 Richard Sandiford <richard.sandiford@arm.com>
14841 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14843 PR rtl-optimization/87763
14844 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
14845 simplification to handle subregs as well as bare regs.
14846 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
14848 2020-01-29 Joel Hutton <Joel.Hutton@arm.com>
14851 * ira.c (ira): Revert use of simplified LRA algorithm.
14853 2020-01-29 Martin Jambor <mjambor@suse.cz>
14855 PR tree-optimization/92706
14856 * tree-sra.c (struct access): Fields first_link, last_link,
14857 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link,
14858 next_rhs_queued and grp_rhs_queued respectively, new fields
14859 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued.
14860 (struct assign_link): Field next renamed to next_rhs, new field
14861 next_lhs. Updated comment.
14862 (work_queue_head): Renamed to rhs_work_queue_head.
14863 (lhs_work_queue_head): New variable.
14864 (add_link_to_lhs): New function.
14865 (relink_to_new_repr): Also relink LHS lists.
14866 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue.
14867 (add_access_to_lhs_work_queue): New function.
14868 (pop_access_from_work_queue): Renamed to
14869 pop_access_from_rhs_work_queue.
14870 (pop_access_from_lhs_work_queue): New function.
14871 (build_accesses_from_assign): Also add links to LHS lists and to LHS
14873 (child_would_conflict_in_lacc): Renamed to
14874 child_would_conflict_in_acc. Adjusted parameter names.
14875 (create_artificial_child_access): New parameter set_grp_read, use it.
14876 (subtree_mark_written_and_enqueue): Renamed to
14877 subtree_mark_written_and_rhs_enqueue.
14878 (propagate_subaccesses_across_link): Renamed to
14879 propagate_subaccesses_from_rhs.
14880 (propagate_subaccesses_from_lhs): New function.
14881 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to
14884 2020-01-29 Martin Jambor <mjambor@suse.cz>
14886 PR tree-optimization/92706
14887 * tree-sra.c (struct access): Adjust comment of
14888 grp_total_scalarization.
14889 (find_access_in_subtree): Look for single children spanning an entire
14891 (scalarizable_type_p): Allow register accesses, adjust callers.
14892 (completely_scalarize): Remove function.
14893 (scalarize_elem): Likewise.
14894 (create_total_scalarization_access): Likewise.
14895 (sort_and_splice_var_accesses): Do not track total scalarization
14897 (analyze_access_subtree): New parameter totally, adjust to new meaning
14898 of grp_total_scalarization.
14899 (analyze_access_trees): Pass new parameter to analyze_access_subtree.
14900 (can_totally_scalarize_forest_p): New function.
14901 (create_total_scalarization_access): Likewise.
14902 (create_total_access_and_reshape): Likewise.
14903 (total_should_skip_creating_access): Likewise.
14904 (totally_scalarize_subtree): Likewise.
14905 (analyze_all_variable_accesses): Perform total scalarization after
14906 subaccess propagation using the new functions above.
14907 (initialize_constant_pool_replacements): Output initializers by
14908 traversing the access tree.
14910 2020-01-29 Martin Jambor <mjambor@suse.cz>
14912 * tree-sra.c (verify_sra_access_forest): New function.
14913 (verify_all_sra_access_forests): Likewise.
14914 (create_artificial_child_access): Set parent.
14915 (analyze_all_variable_accesses): Call the verifier.
14917 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14919 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge
14920 if called on indirect edge.
14921 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of
14922 speculative call if needed.
14924 2020-01-29 Richard Biener <rguenther@suse.de>
14926 PR tree-optimization/93428
14927 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load
14928 permutation when the load node is created.
14929 (vect_analyze_slp_instance): Re-use it here.
14931 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14933 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning.
14935 2020-01-28 Vladimir Makarov <vmakarov@redhat.com>
14937 PR rtl-optimization/93272
14938 * ira-lives.c (process_out_of_region_eh_regs): New function.
14939 (process_bb_node_lives): Call it.
14941 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14943 * coverage.c (read_counts_file): Make error message lowercase.
14945 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14947 * profile-count.c (profile_quality_display_names): Fix ordering.
14949 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14952 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site
14953 hash only when edge is first within the sequence.
14954 (cgraph_edge::set_call_stmt): Update handling of speculative calls.
14955 (symbol_table::create_edge): Do not set target_prob.
14956 (cgraph_edge::remove_caller): Watch for speculative calls when updating
14957 the call site hash.
14958 (cgraph_edge::make_speculative): Drop target_prob parameter.
14959 (cgraph_edge::speculative_call_info): Remove.
14960 (cgraph_edge::first_speculative_call_target): New member function.
14961 (update_call_stmt_hash_for_removing_direct_edge): New function.
14962 (cgraph_edge::resolve_speculation): Rewrite to new API.
14963 (cgraph_edge::speculative_call_for_target): New member function.
14964 (cgraph_edge::make_direct): Rewrite to new API; fix handling of
14965 multiple speculation targets.
14966 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating
14968 (verify_speculative_call): Verify that targets form an interval.
14969 * cgraph.h (cgraph_edge::speculative_call_info): Remove.
14970 (cgraph_edge::first_speculative_call_target): New member function.
14971 (cgraph_edge::next_speculative_call_target): New member function.
14972 (cgraph_edge::speculative_call_target_ref): New member function.
14973 (cgraph_edge;:speculative_call_indirect_edge): New member funtion.
14974 (cgraph_edge): Remove target_prob.
14975 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
14976 Fix handling of speculative calls.
14977 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals.
14978 * ipa-fnsummary.c (analyze_function_body): Likewise.
14979 * ipa-inline.c (speculation_useful_p): Use new speculative call API.
14980 * ipa-profile.c (dump_histogram): Fix formating.
14981 (ipa_profile_generate_summary): Watch for overflows.
14982 (ipa_profile): Do not require probablity to be 1/2; update to new API.
14983 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API.
14984 (update_indirect_edges_after_inlining): Update to new API.
14985 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call
14987 * profile-count.h: (profile_probability::adjusted): New.
14988 * tree-inline.c (copy_bb): Update to new speculative call API; fix
14989 updating of profile.
14990 * value-prof.c (gimple_ic_transform): Rename to ...
14991 (dump_ic_profile): ... this one; update dumping.
14992 (stream_in_histogram_value): Fix formating.
14993 (gimple_value_profile_transformations): Update.
14995 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
14998 * config/i386/i386.md (*movoi_internal_avx): Remove
14999 TARGET_SSE_TYPELESS_STORES check.
15000 (*movti_internal): Prefer TARGET_AVX over
15001 TARGET_SSE_TYPELESS_STORES.
15002 (*movtf_internal): Likewise.
15003 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over
15004 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check
15005 from TARGET_SSE_TYPELESS_STORES.
15007 2020-01-28 David Malcolm <dmalcolm@redhat.com>
15009 * diagnostic-core.h (warning_at): Rename overload to...
15010 (warning_meta): ...this.
15011 (emit_diagnostic_valist): Delete decl of overload taking
15012 diagnostic_metadata.
15013 * diagnostic.c (emit_diagnostic_valist): Likewise for defn.
15014 (warning_at): Rename overload taking diagnostic_metadata to...
15015 (warning_meta): ...this.
15017 2020-01-28 Richard Biener <rguenther@suse.de>
15019 PR tree-optimization/93439
15020 * tree-parloops.c (create_loop_fn): Move clique bookkeeping...
15021 * tree-cfg.c (move_sese_region_to_fn): ... here.
15022 (verify_types_in_gimple_reference): Verify used cliques are
15025 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
15028 * config/i386/i386-options.c (set_ix86_tune_features): Add an
15029 argument of a pointer to struct gcc_options and pass it to
15030 parse_mtune_ctrl_str.
15031 (ix86_function_specific_restore): Pass opts to
15032 set_ix86_tune_features.
15033 (ix86_option_override_internal): Likewise.
15034 (parse_mtune_ctrl_str): Add an argument of a pointer to struct
15035 gcc_options and use it for x_ix86_tune_ctrl_string.
15037 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15039 PR rtl-optimization/87763
15040 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
15041 simplification to handle subregs as well as bare regs.
15042 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
15044 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15046 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully
15047 for reduction chains that (now) include a call.
15049 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15051 PR tree-optimization/92822
15052 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling
15053 out the don't-care elements of a vector whose significant elements
15054 are duplicates, make the don't-care elements duplicates too.
15056 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15058 PR tree-optimization/93434
15059 * tree-predcom.c (split_data_refs_to_components): Record which
15060 components have had aliasing loads removed. Prevent store-store
15061 commoning for all such components.
15063 2020-01-28 Jakub Jelinek <jakub@redhat.com>
15066 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not
15067 -1 or is_vshift is true, use new_vector with number of elts npatterns
15068 rather than new_unary_operation.
15070 PR tree-optimization/93454
15071 * gimple-fold.c (fold_array_ctor_reference): Perform
15072 elt_size.to_uhwi () just once, instead of calling it in every
15073 iteration. Punt if that value is above size of the temporary
15074 buffer. Decrease third native_encode_expr argument when
15075 bufoff + elt_sz is above size of buf.
15077 2020-01-27 Joseph Myers <joseph@codesourcery.com>
15079 * config/mips/mips.c (mips_declare_object_name)
15080 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object.
15082 2020-01-27 Martin Liska <mliska@suse.cz>
15084 PR gcov-profile/93403
15085 * tree-profile.c (gimple_init_gcov_profiler): Generate
15086 both __gcov_indirect_call_profiler_v4 and
15087 __gcov_indirect_call_profiler_v4_atomic.
15089 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15092 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
15094 (@aarch64_split_simd_mov<mode>): Use it.
15095 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
15096 Leave the vec_extract patterns to handle 2-element vectors.
15097 (aarch64_simd_mov_from_<mode>high): Likewise.
15098 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
15099 (vec_extractv2dfv1df): Likewise.
15101 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15103 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
15104 jump conditions for *compare_condjump<GPI:mode>.
15106 2020-01-27 David Malcolm <dmalcolm@redhat.com>
15109 * digraph.cc (test_edge::test_edge): Specify template for base
15112 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15114 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
15116 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15118 * config/arc/arc-protos.h (gen_mlo): Remove.
15119 (gen_mhi): Likewise.
15120 * config/arc/arc.c (AUX_MULHI): Define.
15121 (arc_must_save_reister): Special handling for r58/59.
15122 (arc_compute_frame_size): Consider mlo/mhi registers.
15123 (arc_save_callee_saves): Emit fp/sp move only when emit_move
15125 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
15126 mlo/mhi name selection.
15127 (arc_restore_callee_saves): Don't early restore blink when ISR.
15128 (arc_expand_prologue): Add mlo/mhi saving.
15129 (arc_expand_epilogue): Add mlo/mhi restoring.
15132 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
15133 numbering when MUL64 option is used.
15134 (DWARF2_FRAME_REG_OUT): Define.
15135 * config/arc/arc.md (arc600_stall): New pattern.
15136 (VUNSPEC_ARC_ARC600_STALL): Define.
15137 (mulsi64): Use correct mlo/mhi registers.
15138 (mulsi_600): Clean it up.
15139 * config/arc/predicates.md (mlo_operand): Remove any dependency on
15141 (mhi_operand): Likewise.
15143 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15144 Petro Karashchenko <petro.karashchenko@ring.com>
15146 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct
15147 attributes if needed.
15148 (prepare_move_operands): Generate special unspec instruction for
15150 (arc_isuncached_mem_p): Propagate uncached attribute to each
15152 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
15153 (VUNSPEC_ARC_STDI): Likewise.
15154 (ALLI): New mode iterator.
15155 (mALLI): New mode attribute.
15156 (lddi): New instruction pattern.
15158 (stdidi_split): Split instruction for architectures which are not
15159 supporting ll64 option.
15160 (lddidi_split): Likewise.
15162 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15164 PR rtl-optimization/92989
15165 * lra-lives.c (process_bb_lives): Update the live-in set before
15166 processing additional clobbers.
15168 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15170 PR rtl-optimization/93170
15171 * cselib.c (cselib_invalidate_regno_val): New function, split out
15173 (cselib_invalidate_regno): ...here.
15174 (cselib_invalidated_by_call_p): New function.
15175 (cselib_process_insn): Iterate over all the hard-register entries in
15176 REG_VALUES and invalidate any that cross call-clobbered registers.
15178 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15180 * dojump.c (split_comparison): Use HONOR_NANS rather than
15181 HONOR_SNANS when splitting LTGT.
15183 2020-01-27 Martin Liska <mliska@suse.cz>
15186 * opts.c (print_filtered_help): Exclude language-specific
15187 options from --help=common unless enabled in all FEs.
15189 2020-01-27 Martin Liska <mliska@suse.cz>
15191 * opts.c (print_help): Exclude params from
15192 all except --help=param.
15194 2020-01-27 Martin Liska <mliska@suse.cz>
15197 * config/i386/i386-features.c (make_resolver_func):
15198 Align the code with ppc64 target implementation.
15199 Do not generate a unique name for resolver function.
15201 2020-01-27 Richard Biener <rguenther@suse.de>
15203 PR tree-optimization/93397
15204 * tree-vect-slp.c (vect_analyze_slp_instance): Delay
15205 converted reduction chain SLP graph adjustment.
15207 2020-01-26 Marek Polacek <polacek@redhat.com>
15210 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
15213 2020-01-26 Jason Merrill <jason@redhat.com>
15216 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
15219 2020-01-26 Darius Galis <darius.galis@cyberthorstudios.com>
15221 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
15222 (rx_setmem): Likewise.
15224 2020-01-26 Jakub Jelinek <jakub@redhat.com>
15227 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
15228 Use nonimmediate_operand instead of x86_64_hilo_general_operand and
15229 drop <di> from constraint of last operand.
15232 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
15233 TARGET_AVX2 and V4DFmode not in the split condition, but in the
15234 pattern condition, though allow { 0, 0, 0, 0 } broadcast always.
15236 2020-01-25 Feng Xue <fxue@os.amperecomputing.com>
15239 * ipa-cp.c (get_info_about_necessary_edges): Remove value
15242 2020-01-24 Jeff Law <law@redhat.com>
15244 PR tree-optimization/92788
15245 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX
15248 2020-01-24 Jakub Jelinek <jakub@redhat.com>
15251 * config/i386/sse.md (*avx_vperm_broadcast_v4sf,
15252 *avx_vperm_broadcast_<mode>,
15253 <sse2_avx_avx512f>_vpermil<mode><mask_name>,
15254 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>):
15255 Move before avx2_perm<mode>/avx512f_perm<mode>.
15258 * simplify-rtx.c (simplify_const_unary_operation,
15259 simplify_const_binary_operation): Punt for mode precision above
15260 MAX_BITSIZE_MODE_ANY_INT.
15262 2020-01-24 Andrew Pinski <apinski@marvell.com>
15264 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change
15265 alu.shift_reg to 0.
15267 2020-01-24 Jeff Law <law@redhat.com>
15270 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg
15271 for REGs. Call output_operand_lossage to get more reasonable
15274 2020-01-24 Andrew Stubbs <ams@codesourcery.com>
15276 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use
15277 gcn_fp_compare_operator.
15278 (vec_cmpu<mode>di): Use gcn_compare_operator.
15279 (vec_cmp<u>v64qidi): Use gcn_compare_operator.
15280 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator.
15281 (vec_cmpu<mode>di_exec): Use gcn_compare_operator.
15282 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator.
15283 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator.
15284 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator.
15285 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use
15286 gcn_fp_compare_operator.
15287 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use
15288 gcn_fp_compare_operator.
15289 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use
15290 gcn_fp_compare_operator.
15291 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use
15292 gcn_fp_compare_operator.
15294 2020-01-24 Maciej W. Rozycki <macro@wdc.com>
15296 * doc/install.texi (Cross-Compiler-Specific Options): Document
15297 `--with-toolexeclibdir' option.
15299 2020-01-24 Hans-Peter Nilsson <hp@axis.com>
15301 * target.def (flags_regnum): Also mention effect on delay slot filling.
15302 * doc/tm.texi: Regenerate.
15304 2020-01-23 Jeff Law <law@redhat.com>
15306 PR translation/90162
15307 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text.
15309 2020-01-23 Mikael Tillenius <mti-1@tillenius.com>
15312 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of
15315 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15317 PR rtl-optimization/93402
15318 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust
15321 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15323 * config.in: Regenerated.
15324 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
15325 for TARGET_LIBC_GNUSTACK.
15326 * configure: Regenerated.
15327 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
15328 found to be 2.31 or greater.
15330 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15332 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
15334 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
15335 (mips_asm_file_end): New function. Delegate to
15336 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
15337 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
15339 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15342 * config/i386/i386-modes.def (POImode): New mode.
15343 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160.
15344 * config/i386/i386.md (DPWI): New mode attribute.
15345 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>.
15346 (QWI): Rename to...
15347 (QPWI): ... this. Use POI instead of OI for TImode.
15348 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1,
15349 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI>
15352 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15355 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New
15357 (speculation_tracker_rev): New pattern.
15358 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation):
15359 Use speculation_tracker_rev to track the inverse condition.
15361 2020-01-23 Richard Biener <rguenther@suse.de>
15363 PR tree-optimization/93381
15364 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take
15365 alias-set of the def as argument and record the first one.
15366 (vn_walk_cb_data::first_set): New member.
15367 (vn_reference_lookup_3): Pass the alias-set of the current def
15368 to push_partial_def. Fix alias-set used in the aggregate copy
15370 (vn_reference_lookup): Consistently set *last_vuse_ptr.
15371 * real.c (clear_significand_below): Fix out-of-bound access.
15373 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15376 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3):
15377 New define_insn patterns.
15379 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15381 * doc/sourcebuild.texi (check-function-bodies): Add an
15382 optional target/xfail selector.
15384 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15386 PR rtl-optimization/93124
15387 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to
15388 bare USE and CLOBBER insns.
15390 2020-01-22 Andrew Pinski <apinski@marvell.com>
15392 * config/arc/arc.c (output_short_suffix): Check insn for nullness.
15394 2020-01-22 David Malcolm <dmalcolm@redhat.com>
15397 * gdbinit.in (break-on-saved-diagnostic): Update for move of
15398 diagnostic_manager into "ana" namespace.
15399 * selftest-run-tests.c (selftest::run_tests): Update for move of
15400 selftest::run_analyzer_selftests to
15401 ana::selftest::run_analyzer_selftests.
15403 2020-01-22 Richard Sandiford <richard.sandiford@arm.com>
15405 * cfgexpand.c (union_stack_vars): Update the size.
15407 2020-01-22 Richard Biener <rguenther@suse.de>
15409 PR tree-optimization/93381
15410 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting
15411 throughout, handle all conversions the same.
15413 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15416 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use
15417 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate
15418 predicate, not whenever it is CONST_INT. Otherwise, force_reg it.
15419 Call force_reg on high_in2 unconditionally.
15421 2020-01-22 Martin Liska <mliska@suse.cz>
15423 PR tree-optimization/92924
15424 * profile.c (compute_value_histograms): Divide
15425 all counter values.
15427 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15430 * output.h (assemble_name_resolve): Declare.
15431 * varasm.c (assemble_name_resolve): New function.
15432 (assemble_name): Use it.
15433 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define.
15435 2020-01-22 Joseph Myers <joseph@codesourcery.com>
15437 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to
15438 update_web_docs_git instead of update_web_docs_svn.
15440 2020-01-21 Andrew Pinski <apinski@marvell.com>
15443 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
15444 as PTR mode. Have operand 1 as being modeless, it can be P mode.
15445 (*tlsgd_small_<mode>): Likewise.
15446 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
15447 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
15448 register. Convert that register back to dest using convert_mode.
15450 2020-01-21 Jim Wilson <jimw@sifive.com>
15452 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
15455 2020-01-21 H.J. Lu <hongjiu.lu@intel.com>
15456 Uros Bizjak <ubizjak@gmail.com>
15459 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode
15461 (legitimize_tls_address): Do GNU2 TLS address computation in
15462 ptr_mode and zero-extend result to Pmode.
15463 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
15464 :P with :PTR and Pmode with ptr_mode.
15465 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
15466 (*tls_dynamic_gnu2_call_64_<mode>): Likewise.
15467 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise.
15469 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15472 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
15473 the last two operands are CONST_INT_P before using them as such.
15475 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15477 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
15478 to get the integer element types.
15480 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15482 * config/aarch64/aarch64-sve-builtins.h
15483 (function_expander::convert_to_pmode): Declare.
15484 * config/aarch64/aarch64-sve-builtins.cc
15485 (function_expander::convert_to_pmode): New function.
15486 (function_expander::get_contiguous_base): Use it.
15487 (function_expander::prepare_gather_address_operands): Likewise.
15488 * config/aarch64/aarch64-sve-builtins-sve2.cc
15489 (svwhilerw_svwhilewr_impl::expand): Likewise.
15491 2020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com>
15494 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set
15495 cfun->machine->label_is_assembled.
15496 (aarch64_print_patchable_function_entry): New.
15497 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
15498 * config/aarch64/aarch64.h (struct machine_function): New field,
15499 label_is_assembled.
15501 2020-01-21 David Malcolm <dmalcolm@redhat.com>
15504 * ipa-profile.c (ipa_profile): Delete call_sums and set it to
15507 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15510 * cgraph.c (cgraph_edge::resolve_speculation,
15511 cgraph_edge::redirect_call_stmt_to_callee): Fix update of
15512 call_stmt_site_hash.
15514 2020-01-21 Martin Liska <mliska@suse.cz>
15516 * config/rs6000/rs6000.c (common_mode_defined): Remove
15519 2020-01-21 Richard Biener <rguenther@suse.de>
15521 PR tree-optimization/92328
15522 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
15523 type when value-numbering same-sized store by inserting a
15525 (eliminate_dom_walker::eliminate_stmt): When eliminating
15526 a redundant store handle bit-reinterpretation of the same value.
15528 2020-01-21 Andrew Pinski <apinski@marvel.com>
15531 * tree-into-ssa.c (prepare_block_for_update_1): Split out
15533 (prepare_block_for_update): This. Use a worklist instead of
15536 2020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15538 * config/arm/arm.c (clear_operation_p):
15539 Initialise last_regno, skip first iteration
15540 based on the first_set value and use ints instead
15541 of the unnecessary HOST_WIDE_INTs.
15543 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15546 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
15547 compare_mode other than SFmode or DFmode.
15549 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
15552 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
15553 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
15554 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
15556 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15558 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
15560 2020-01-20 Andrew Pinski <apinski@marvell.com>
15562 PR middle-end/93242
15563 * targhooks.c (default_print_patchable_function_entry): Use
15564 output_asm_insn to emit the nop instruction.
15566 2020-01-20 Fangrui Song <maskray@google.com>
15568 PR middle-end/93194
15569 * targhooks.c (default_print_patchable_function_entry): Align to
15572 2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
15575 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to
15576 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode.
15577 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ...
15578 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P.
15579 (*tls_dynamic_gnu2_lea_64): Renamed to ...
15580 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P.
15581 Remove the {q} suffix from lea.
15582 (*tls_dynamic_gnu2_call_64): Renamed to ...
15583 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P.
15584 (*tls_dynamic_gnu2_combine_64): Renamed to ...
15585 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P.
15586 Pass Pmode to gen_tls_dynamic_gnu2_64.
15588 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15590 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
15592 2020-01-20 Richard Sandiford <richard.sandiford@arm.com>
15594 * config/aarch64/aarch64-sve-builtins-base.cc
15595 (svld1ro_impl::memory_vector_mode): Remove parameter name.
15597 2020-01-20 Richard Biener <rguenther@suse.de>
15600 * dwarf2out.c (prune_unused_types): Unconditionally mark
15601 called function DIEs.
15603 2020-01-20 Martin Liska <mliska@suse.cz>
15605 PR tree-optimization/93199
15606 * tree-eh.c (struct leh_state): Add
15607 new field outer_non_cleanup.
15608 (cleanup_is_dead_in): Pass leh_state instead
15609 of eh_region. Add a checking that state->outer_non_cleanup
15610 points to outer non-clean up region.
15611 (lower_try_finally): Record outer_non_cleanup
15613 (lower_catch): Likewise.
15614 (lower_eh_filter): Likewise.
15615 (lower_eh_must_not_throw): Likewise.
15616 (lower_cleanup): Likewise.
15618 2020-01-20 Richard Biener <rguenther@suse.de>
15620 PR tree-optimization/93094
15621 * tree-vectorizer.h (vect_loop_versioning): Adjust.
15622 (vect_transform_loop): Likewise.
15623 * tree-vectorizer.c (try_vectorize_loop_1): Pass down
15624 loop_vectorized_call to vect_transform_loop.
15625 * tree-vect-loop.c (vect_transform_loop): Pass down
15626 loop_vectorized_call to vect_loop_versioning.
15627 * tree-vect-loop-manip.c (vect_loop_versioning): Use
15628 the earlier discovered loop_vectorized_call.
15630 2020-01-19 Eric S. Raymond <esr@thyrsus.com>
15632 * doc/contribute.texi: Update for SVN -> Git transition.
15633 * doc/install.texi: Likewise.
15635 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15638 * cgraph.c (cgraph_edge::make_speculative): Increase number of
15639 speculative targets.
15640 (verify_speculative_call): New function
15641 (cgraph_node::verify_node): Use it.
15642 * ipa-profile.c (ipa_profile): Fix formating; do not set number of
15645 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15648 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting.
15649 (cgraph_edge::make_direct): Remove all indirect targets.
15650 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct..
15651 (cgraph_node::verify_node): Verify that only one call_stmt or
15652 lto_stmt_uid is set.
15653 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or
15655 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt.
15656 (lto_output_ref): Simplify streaming of stmt.
15657 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid.
15659 2020-01-18 Tamar Christina <tamar.christina@arm.com>
15661 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode):
15662 Mark parameter unused.
15664 2020-01-18 Hans-Peter Nilsson <hp@axis.com>
15666 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux*
15668 2019-01-18 Gerald Pfeifer <gerald@pfeifer.com>
15670 * varpool.c (ctor_useable_for_folding_p): Fix grammar.
15672 2020-01-18 Iain Sandoe <iain@sandoe.co.uk>
15674 * Makefile.in: Add coroutine-passes.o.
15675 * builtin-types.def (BT_CONST_SIZE): New.
15676 (BT_FN_BOOL_PTR): New.
15677 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New.
15678 * builtins.def (DEF_COROUTINE_BUILTIN): New.
15679 * coroutine-builtins.def: New file.
15680 * coroutine-passes.cc: New file.
15681 * function.h (struct GTY function): Add a bit to indicate that the
15682 function is a coroutine component.
15683 * internal-fn.c (expand_CO_FRAME): New.
15684 (expand_CO_YIELD): New.
15685 (expand_CO_SUSPN): New.
15686 (expand_CO_ACTOR): New.
15687 * internal-fn.def (CO_ACTOR): New.
15691 * passes.def: Add pass_coroutine_lower_builtins,
15692 pass_coroutine_early_expand_ifns.
15693 * tree-pass.h (make_pass_coroutine_lower_builtins): New.
15694 (make_pass_coroutine_early_expand_ifns): New.
15695 * doc/invoke.texi: Document the fcoroutines command line
15698 2020-01-18 Jakub Jelinek <jakub@redhat.com>
15700 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable.
15703 * config/arm/arm.c (clear_operation_p): Don't use REGNO until
15704 after checking the argument is a REG. Don't use REGNO (reg)
15705 again to set last_regno, reuse regno variable instead.
15707 2020-01-17 David Malcolm <dmalcolm@redhat.com>
15709 * doc/analyzer.texi (Limitations): Add note about NaN.
15711 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15712 Sudakshina Das <sudi.das@arm.com>
15714 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
15715 and valid immediate.
15716 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
15717 (lshrdi3): Generate thumb2_lsrl for valid immediates.
15718 * config/arm/constraints.md (Pg): New.
15719 * config/arm/predicates.md (long_shift_imm): New.
15720 (arm_reg_or_long_shift_imm): Likewise.
15721 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
15722 (thumb2_lsll): Likewise.
15723 (thumb2_lsrl): New.
15725 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15726 Sudakshina Das <sudi.das@arm.com>
15728 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
15729 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
15730 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
15731 register pairs for doubleword quantities for ARMv8.1M-Mainline.
15732 * config/arm/thumb2.md (thumb2_asrl): New.
15733 (thumb2_lsll): Likewise.
15735 2020-01-17 Jakub Jelinek <jakub@redhat.com>
15737 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
15740 2020-01-17 Alexander Monakov <amonakov@ispras.ru>
15742 * gdbinit.in (help-gcc-hooks): New command.
15743 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
15744 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
15747 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15749 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
15750 correct target macro.
15752 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15754 * config/aarch64/aarch64-protos.h
15755 (aarch64_sve_ld1ro_operand_p): New.
15756 * config/aarch64/aarch64-sve-builtins-base.cc
15757 (class load_replicate): New.
15758 (class svld1ro_impl): New.
15759 (class svld1rq_impl): Change to inherit from load_replicate.
15760 (svld1ro): New sve intrinsic function base.
15761 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
15762 New DEF_SVE_FUNCTION.
15763 * config/aarch64/aarch64-sve-builtins-base.h
15764 (svld1ro): New decl.
15765 * config/aarch64/aarch64-sve-builtins.cc
15766 (function_expander::add_mem_operand): Modify assert to allow
15768 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
15770 * config/aarch64/aarch64.c
15771 (aarch64_sve_ld1rq_operand_p): Implement in terms of ...
15772 (aarch64_sve_ld1rq_ld1ro_operand_p): This.
15773 (aarch64_sve_ld1ro_operand_p): New.
15774 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
15775 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
15776 * config/aarch64/predicates.md
15777 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New.
15779 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15781 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
15782 Introduce this ACLE specified predefined macro.
15783 * config/aarch64/aarch64-option-extensions.def (f64mm): New.
15784 (fp): Disabling this disables f64mm.
15785 (simd): Disabling this disables f64mm.
15786 (fp16): Disabling this disables f64mm.
15787 (sve): Disabling this disables f64mm.
15788 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
15789 (AARCH64_ISA_F64MM): New.
15790 (TARGET_F64MM): New.
15791 * doc/invoke.texi (f64mm): Document new option.
15793 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
15795 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
15796 (neoversen1_tunings): Likewise.
15798 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
15801 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
15802 Add assert to ensure prolog has been emitted.
15803 (aarch64_split_atomic_op): Likewise.
15804 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
15805 Use epilogue_completed rather than reload_completed.
15806 (aarch64_atomic_exchange<mode>): Likewise.
15807 (aarch64_atomic_<atomic_optab><mode>): Likewise.
15808 (atomic_nand<mode>): Likewise.
15809 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
15810 (atomic_fetch_nand<mode>): Likewise.
15811 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
15812 (atomic_nand_fetch<mode>): Likewise.
15814 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
15817 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
15819 (REVERSE_CONDITION): Delete.
15820 * config/aarch64/iterators.md (CC_ONLY): New mode iterator.
15821 (CCFP_CCFPE): Likewise.
15822 (e): New mode attribute.
15823 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
15824 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
15825 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
15826 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
15827 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
15828 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
15829 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
15830 name of generator from gen_ccmpdi to gen_ccmpccdi.
15831 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse
15832 the previous comparison but aren't able to, use the new ccmp_rev
15835 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
15837 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
15838 than testing directly for INTEGER_CST.
15839 (gimplify_target_expr, gimplify_omp_depend): Likewise.
15841 2020-01-17 Jakub Jelinek <jakub@redhat.com>
15843 PR tree-optimization/93292
15844 * tree-vect-stmts.c (vectorizable_comparison): Punt also if
15845 get_vectype_for_scalar_type returns NULL.
15847 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
15849 * params.opt (-param=max-predicted-iterations): Increase range from 0.
15850 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.
15852 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
15854 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
15856 * params.opt: (max-predicted-iterations): Set bounds.
15857 * predict.c (real_almost_one, real_br_prob_base,
15858 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
15859 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic
15860 probabilities; do not truncate to reg_br_prob_bases.
15861 (estimate_loops_at_level): Pass max_cyclic_prob.
15862 (estimate_loops): Compute max_cyclic_prob.
15863 (estimate_bb_frequencies): Do not initialize real_*; update calculation
15865 * profile-count.c (profile_probability::to_sreal): New.
15866 * profile-count.h (class sreal): Move up in file.
15867 (profile_probability::to_sreal): Declare.
15869 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15872 (arm_invalid_conversion): New function for target hook.
15873 (arm_invalid_unary_op): New function for target hook.
15874 (arm_invalid_binary_op): New function for target hook.
15876 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15878 * config.gcc: Add arm_bf16.h.
15879 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
15880 (arm_simd_builtin_std_type): Add BFmode.
15881 (arm_init_simd_builtin_types): Define element types for vector types.
15882 (arm_init_bf16_types): New function.
15883 (arm_init_builtins): Add arm_init_bf16_types function call.
15884 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
15885 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
15886 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
15887 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
15888 (arm_vector_mode_supported_p): Add V4BF, V8BF.
15889 (arm_mangle_type): Add __bf16.
15890 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
15891 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
15892 arm_bf16_ptr_type_node.
15893 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
15894 define_split between ARM registers.
15895 * config/arm/arm_bf16.h: New file.
15896 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
15897 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
15898 (VQXMOV): Add V8BF.
15899 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
15900 * config/arm/vfp.md: Add BFmode to movhf patterns.
15902 2020-01-16 Mihail Ionescu <mihail.ionescu@arm.com>
15903 Andre Vieira <andre.simoesdiasvieira@arm.com>
15905 * config/arm/arm-cpus.in (mve, mve_float): New features.
15906 (dsp, mve, mve.fp): New options.
15907 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
15908 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
15909 * doc/invoke.texi: Document the armv8.1-m mve and dps options.
15911 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15912 Thomas Preud'homme <thomas.preudhomme@arm.com>
15914 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
15916 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
15917 error for using -mcmse when targeting Armv8.1-M Mainline.
15919 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15920 Thomas Preud'homme <thomas.preudhomme@arm.com>
15922 * config/arm/arm.md (nonsecure_call_internal): Do not force memory
15923 address in r4 when targeting Armv8.1-M Mainline.
15924 (nonsecure_call_value_internal): Likewise.
15925 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
15926 a register match_operand again. Emit BLXNS when targeting
15927 Armv8.1-M Mainline.
15928 (nonsecure_call_value_reg_thumb2): Likewise.
15930 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15931 Thomas Preud'homme <thomas.preudhomme@arm.com>
15933 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
15934 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
15935 variable as true when floating-point ABI is not hard. Replace
15936 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
15937 Generate VLSTM and VLLDM instruction respectively before and
15938 after a function call to cmse_nonsecure_call function.
15939 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
15940 (VUNSPEC_VLLDM): Likewise.
15941 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
15942 (lazy_load_multiple_insn): Likewise.
15944 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15945 Thomas Preud'homme <thomas.preudhomme@arm.com>
15947 * config/arm/arm.c (vfp_emit_fstmd): Declare early.
15948 (arm_emit_vfp_multi_reg_pop): Likewise.
15949 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
15950 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and
15951 restore callee-saved VFP registers.
15953 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15954 Thomas Preud'homme <thomas.preudhomme@arm.com>
15956 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
15957 (cmse_nonsecure_call_clear_caller_saved): Rename into ...
15958 (cmse_nonsecure_call_inline_register_clear): This. Save and clear
15959 callee-saved GPRs as well as clear ip register before doing a nonsecure
15960 call then restore callee-saved GPRs after it when targeting
15961 Armv8.1-M Mainline.
15962 (arm_reorg): Adapt to function rename.
15964 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15965 Thomas Preud'homme <thomas.preudhomme@arm.com>
15967 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
15968 * config/arm/arm.c (clear_operation_p): Extend to be able to check a
15969 clear_vfp_multiple pattern based on a new vfp parameter.
15970 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
15971 targeting Armv8.1-M Mainline.
15972 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers
15973 unconditionally when targeting Armv8.1-M Mainline architecture. Check
15974 whether VFP registers are available before looking call_used_regs for a
15976 * config/arm/predicates.md (clear_multiple_operation): Adapt to change
15977 of prototype of clear_operation_p.
15978 (clear_vfp_multiple_operation): New predicate.
15979 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
15980 * config/arm/vfp.md (clear_vfp_multiple): New define_insn.
15982 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15983 Thomas Preud'homme <thomas.preudhomme@arm.com>
15985 * config/arm/arm-protos.h (clear_operation_p): Declare.
15986 * config/arm/arm.c (clear_operation_p): New function.
15987 (cmse_clear_registers): Generate clear_multiple instruction pattern if
15988 targeting Armv8.1-M Mainline or successor.
15989 (output_return_instruction): Only output APSR register clearing if
15990 Armv8.1-M Mainline instructions not available.
15991 (thumb_exit): Likewise.
15992 * config/arm/predicates.md (clear_multiple_operation): New predicate.
15993 * config/arm/thumb2.md (clear_apsr): New define_insn.
15994 (clear_multiple): Likewise.
15995 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.
15997 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15998 Thomas Preud'homme <thomas.preudhomme@arm.com>
16000 * config/arm/arm.c (fp_sysreg_names): Declare and define.
16001 (use_return_insn): Also return false for Armv8.1-M Mainline.
16002 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M
16003 Mainline instructions are available.
16004 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS
16005 when targeting Armv8.1-M Mainline Security Extensions.
16006 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
16007 Mainline entry function.
16008 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
16009 targeting Armv8.1-M Mainline or successor.
16010 (arm_expand_epilogue): Fix indentation of caller-saved register
16011 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline
16013 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
16014 (FP_SYSREGS): Likewise.
16015 (enum vfp_sysregs_encoding): Define enum.
16016 (fp_sysreg_names): Declare.
16017 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
16018 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
16019 (pop_fpsysreg_insn): Likewise.
16021 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16022 Thomas Preud'homme <thomas.preudhomme@arm.com>
16024 * config/arm/arm-cpus.in (armv8_1m_main): New feature.
16025 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
16026 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
16027 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
16028 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
16029 (ARMv8_1m_main): New feature group.
16030 (armv8.1-m.main): New architecture.
16031 * config/arm/arm-tables.opt: Regenerate.
16032 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
16033 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
16034 (arm_options_perform_arch_sanity_checks): Error out when targeting
16035 Armv8.1-M Mainline Security Extensions.
16036 * config/arm/arm.h (arm_arch8_1m_main): Declare.
16038 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16040 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
16041 aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
16042 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
16043 aarch64_bfdot_laneq): New.
16044 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
16045 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
16046 vbfdotq_laneq_f32): New.
16047 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
16048 VBFMLA_W, VBF): New.
16049 (isquadop): Add V4BF, V8BF.
16051 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16053 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
16054 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
16055 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
16056 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
16057 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
16058 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
16059 usdot_laneq, sudot_lane,sudot_laneq): New.
16060 * config/aarch64/aarch64-simd.md (aarch64_usdot): New.
16061 (aarch64_<sur>dot_lane): New.
16062 * config/aarch64/arm_neon.h (vusdot_s32): New.
16063 (vusdotq_s32): New.
16064 (vusdot_lane_s32): New.
16065 (vsudot_lane_s32): New.
16066 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
16067 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
16069 2020-01-16 Martin Liska <mliska@suse.cz>
16071 * value-prof.c (dump_histogram_value): Fix
16072 obvious spacing issue.
16074 2020-01-16 Andrew Pinski <apinski@marvell.com>
16076 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
16077 !storage_order_barrier_p.
16079 2020-01-16 Andrew Pinski <apinski@marvell.com>
16081 * sched-int.h (_dep): Add unused bit-field field for the padding.
16082 * sched-deps.c (init_dep_1): Init unused field.
16084 2020-01-16 Andrew Pinski <apinski@marvell.com>
16086 * optabs.h (create_expand_operand): Initialize target field also.
16088 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
16090 PR tree-optimization/92429
16091 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
16092 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
16094 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
16097 2020-01-16 Richard Sandiford <richard.sandiford@arm.com>
16099 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
16100 aarch64_sve_int_mode to each mode.
16102 2020-01-15 David Malcolm <dmalcolm@redhat.com>
16104 * doc/analyzer.texi (Overview): Add note about
16105 -fdump-ipa-analyzer.
16107 2020-01-15 Wilco Dijkstra <wdijkstr@arm.com>
16109 PR tree-optimization/93231
16110 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
16111 input_type is unsigned. Use tree_to_shwi for shift constant.
16112 Check CST_STRING element size is CHAR_TYPE_SIZE bits.
16113 (simplify_count_trailing_zeroes): Add test to handle known non-zero
16114 inputs more efficiently.
16116 2020-01-15 Uroš Bizjak <ubizjak@gmail.com>
16118 * config/i386/i386.md (*movsf_internal): Do not require
16119 SSE2 ISA for alternatives 14 and 15.
16121 2020-01-15 Richard Biener <rguenther@suse.de>
16123 PR middle-end/93273
16124 * tree-eh.c (sink_clobbers): If we already visited the destination
16125 block do not defer insertion.
16126 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
16127 the purpose of defered insertion.
16129 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16131 * BASE-VER: Bump to 10.0.1.
16133 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
16135 PR tree-optimization/93247
16136 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
16137 type of the stmt that we're going to vectorize.
16139 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
16141 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
16142 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
16145 2020-01-15 Martin Liska <mliska@suse.cz>
16147 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
16148 2 calls of streamer_read_hwi in a function call.
16150 2020-01-15 Richard Biener <rguenther@suse.de>
16152 * alias.c (record_alias_subset): Avoid redundant work when
16153 subset is already recorded.
16155 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16157 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
16158 the analyzer options provide CWE identifiers.
16160 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16162 * tree-diagnostic-path.cc (path_summary::event_range::print):
16163 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
16164 using get_pure_location.
16166 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16168 PR tree-optimization/93262
16169 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
16170 perform head trimming only if the last argument is constant,
16171 either all ones, or larger or equal to head trim, in the latter
16172 case decrease the last argument by head_trim.
16174 PR tree-optimization/93249
16175 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
16176 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to
16177 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
16178 perform head trim unless we can prove there are no '\0' chars
16179 from the source among the first head_trim chars.
16181 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16183 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.
16185 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16188 * config/i386/sse.md
16189 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1,
16190 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1,
16191 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1,
16192 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use
16193 just a single alternative instead of two, make operands 1 and 2
16196 2020-01-14 Jan Hubicka <hubicka@ucw.cz>
16199 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
16202 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16204 * Makefile.in (lang_opt_files): Add analyzer.opt.
16205 (ANALYZER_OBJS): New.
16206 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o,
16207 tristate.o and ANALYZER_OBJS.
16208 (TEXI_GCCINT_FILES): Add analyzer.texi.
16209 * common.opt (-fanalyzer): New driver option.
16210 * config.in: Regenerate.
16211 * configure: Regenerate.
16212 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option.
16213 (gccdepdir): Also create depdir for "analyzer" subdir.
16214 * digraph.cc: New file.
16215 * digraph.h: New file.
16216 * doc/analyzer.texi: New file.
16217 * doc/gccint.texi ("Static Analyzer") New menu item.
16218 (analyzer.texi): Include it.
16219 * doc/invoke.texi ("Static Analyzer Options"): New list and new section.
16220 ("Warning Options"): Add static analysis warnings to the list.
16221 (-Wno-analyzer-double-fclose): New option.
16222 (-Wno-analyzer-double-free): New option.
16223 (-Wno-analyzer-exposure-through-output-file): New option.
16224 (-Wno-analyzer-file-leak): New option.
16225 (-Wno-analyzer-free-of-non-heap): New option.
16226 (-Wno-analyzer-malloc-leak): New option.
16227 (-Wno-analyzer-possible-null-argument): New option.
16228 (-Wno-analyzer-possible-null-dereference): New option.
16229 (-Wno-analyzer-null-argument): New option.
16230 (-Wno-analyzer-null-dereference): New option.
16231 (-Wno-analyzer-stale-setjmp-buffer): New option.
16232 (-Wno-analyzer-tainted-array-index): New option.
16233 (-Wno-analyzer-use-after-free): New option.
16234 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option.
16235 (-Wno-analyzer-use-of-uninitialized-value): New option.
16236 (-Wanalyzer-too-complex): New option.
16237 (-fanalyzer-call-summaries): New warning.
16238 (-fanalyzer-checker=): New warning.
16239 (-fanalyzer-fine-grained): New warning.
16240 (-fno-analyzer-state-merge): New warning.
16241 (-fno-analyzer-state-purge): New warning.
16242 (-fanalyzer-transitivity): New warning.
16243 (-fanalyzer-verbose-edges): New warning.
16244 (-fanalyzer-verbose-state-changes): New warning.
16245 (-fanalyzer-verbosity=): New warning.
16246 (-fdump-analyzer): New warning.
16247 (-fdump-analyzer-callgraph): New warning.
16248 (-fdump-analyzer-exploded-graph): New warning.
16249 (-fdump-analyzer-exploded-nodes): New warning.
16250 (-fdump-analyzer-exploded-nodes-2): New warning.
16251 (-fdump-analyzer-exploded-nodes-3): New warning.
16252 (-fdump-analyzer-supergraph): New warning.
16253 * doc/sourcebuild.texi (dg-require-dot): New.
16254 (dg-check-dot): New.
16255 * gdbinit.in (break-on-saved-diagnostic): New command.
16256 * graphviz.cc: New file.
16257 * graphviz.h: New file.
16258 * ordered-hash-map-tests.cc: New file.
16259 * ordered-hash-map.h: New file.
16260 * passes.def (pass_analyzer): Add before
16261 pass_ipa_whole_program_visibility.
16262 * selftest-run-tests.c (selftest::run_tests): Call
16263 selftest::ordered_hash_map_tests_cc_tests.
16264 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New
16266 * shortest-paths.h: New file.
16267 * timevar.def (TV_ANALYZER): New timevar.
16268 (TV_ANALYZER_SUPERGRAPH): Likewise.
16269 (TV_ANALYZER_STATE_PURGE): Likewise.
16270 (TV_ANALYZER_PLAN): Likewise.
16271 (TV_ANALYZER_SCC): Likewise.
16272 (TV_ANALYZER_WORKLIST): Likewise.
16273 (TV_ANALYZER_DUMP): Likewise.
16274 (TV_ANALYZER_DIAGNOSTICS): Likewise.
16275 (TV_ANALYZER_SHORTEST_PATHS): Likewise.
16276 * tree-pass.h (make_pass_analyzer): New decl.
16277 * tristate.cc: New file.
16278 * tristate.h: New file.
16280 2020-01-14 Uroš Bizjak <ubizjak@gmail.com>
16283 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for
16284 alternatives 9 and 10.
16286 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16288 * attribs.c (excl_hash_traits::empty_zero_p): New static constant.
16289 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise.
16290 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise.
16291 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
16292 (selftest::hash_map_tests_c_tests): Call it.
16293 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p):
16294 New static constant, using the value of = H::empty_zero_p.
16295 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value
16296 from default_hash_traits <Value>.
16297 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value
16299 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise.
16300 * hash-table.h (hash_table::alloc_entries): Guard the loop of
16301 calls to mark_empty with !Descriptor::empty_zero_p.
16302 (hash_table::empty_slow): Conditionalize the memset call with a
16303 check that Descriptor::empty_zero_p; otherwise, loop through the
16304 entries calling mark_empty on them.
16305 * hash-traits.h (int_hash::empty_zero_p): New static constant.
16306 (pointer_hash::empty_zero_p): Likewise.
16307 (pair_hash::empty_zero_p): Likewise.
16308 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p):
16310 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise.
16311 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise.
16312 * profile.c (location_triplet_hash::empty_zero_p): Likewise.
16313 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise.
16314 (sanopt_tree_couple_hash::empty_zero_p): Likewise.
16315 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise.
16316 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise.
16317 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise.
16318 * tree-vectorizer.h
16319 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p):
16322 2020-01-14 Kewen Lin <linkw@gcc.gnu.org>
16324 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return,
16325 fix typo on return value.
16327 2020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
16330 * cgraph.c (symbol_table::create_edge): Init speculative_id and
16332 (cgraph_edge::make_speculative): Add param for setting speculative_id
16334 (cgraph_edge::speculative_call_info): Update comments and find reference
16335 by speculative_id for multiple indirect targets.
16336 (cgraph_edge::resolve_speculation): Decrease the speculations
16337 for indirect edge, drop it's speculative if not direct target
16338 left. Update comments.
16339 (cgraph_edge::redirect_call_stmt_to_callee): Likewise.
16340 (cgraph_node::dump): Print num_speculative_call_targets.
16341 (cgraph_node::verify_node): Don't report error if speculative
16342 edge not include statement.
16343 (cgraph_edge::num_speculative_call_targets_p): New function.
16344 * cgraph.h (int common_target_id): Remove.
16345 (int common_target_probability): Remove.
16346 (num_speculative_call_targets): New variable.
16347 (make_speculative): Add param for setting speculative_id.
16348 (cgraph_edge::num_speculative_call_targets_p): New declare.
16349 (target_prob): New variable.
16350 (speculative_id): New variable.
16351 * ipa-fnsummary.c (analyze_function_body): Create and duplicate
16352 call summaries for multiple speculative call targets.
16353 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id.
16354 * ipa-profile.c (struct speculative_call_target): New struct.
16355 (class speculative_call_summary): New class.
16356 (class speculative_call_summaries): New class.
16357 (call_sums): New variable.
16358 (ipa_profile_generate_summary): Generate indirect multiple targets summaries.
16359 (ipa_profile_write_edge_summary): New function.
16360 (ipa_profile_write_summary): Stream out indirect multiple targets summaries.
16361 (ipa_profile_dump_all_summaries): New function.
16362 (ipa_profile_read_edge_summary): New function.
16363 (ipa_profile_read_summary_section): New function.
16364 (ipa_profile_read_summary): Stream in indirect multiple targets summaries.
16365 (ipa_profile): Generate num_speculative_call_targets from
16367 * ipa-ref.h (speculative_id): New variable.
16368 * ipa-utils.c (ipa_merge_profiles): Update with target_prob.
16369 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and
16370 common_target_probability. Stream out speculative_id and
16371 num_speculative_call_targets.
16372 (input_edge): Likewise.
16373 * predict.c (dump_prediction): Remove edges count assert to be
16375 * symtab.c (symtab_node::create_reference): Init speculative_id.
16376 (symtab_node::clone_references): Clone speculative_id.
16377 (symtab_node::clone_referring): Clone speculative_id.
16378 (symtab_node::clone_reference): Clone speculative_id.
16379 (symtab_node::clear_stmts_in_references): Clear speculative_id.
16380 * tree-inline.c (copy_bb): Duplicate all the speculative edges
16381 if indirect call contains multiple speculative targets.
16382 * value-prof.h (check_ic_target): Remove.
16383 * value-prof.c (gimple_value_profile_transformations):
16384 Use void function gimple_ic_transform.
16385 * value-prof.c (gimple_ic_transform): Handle topn case.
16386 Fix comment typos. Change it to a void function.
16388 2020-01-13 Andrew Pinski <apinski@marvell.com>
16390 * config/aarch64/aarch64-cores.def (octeontx2): New define.
16391 (octeontx2t98): New define.
16392 (octeontx2t96): New define.
16393 (octeontx2t93): New define.
16394 (octeontx2f95): New define.
16395 (octeontx2f95n): New define.
16396 (octeontx2f95mm): New define.
16397 * config/aarch64/aarch64-tune.md: Regenerate.
16398 * doc/invoke.texi (-mcpu=): Document the new cpu types.
16400 2020-01-13 Jason Merrill <jason@redhat.com>
16402 PR c++/33799 - destroy return value if local cleanup throws.
16403 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR.
16405 2020-01-13 Martin Liska <mliska@suse.cz>
16407 * ipa-cp.c (get_max_overall_size): Use newly
16408 renamed param param_ipa_cp_unit_growth.
16409 * params.opt: Remove legacy param name.
16411 2020-01-13 Martin Sebor <msebor@redhat.com>
16413 PR tree-optimization/93213
16414 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul
16415 stores to be eliminated.
16417 2020-01-13 Martin Liska <mliska@suse.cz>
16419 * opts.c (print_help): Do not print CL_PARAM
16420 and CL_WARNING for CL_OPTIMIZATION.
16422 2020-01-13 Jonathan Wakely <jwakely@redhat.com>
16425 * doc/invoke.texi (Warning Options): Add caveat about some warnings
16426 depending on optimization settings.
16428 2020-01-13 Jakub Jelinek <jakub@redhat.com>
16430 PR tree-optimization/90838
16431 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16432 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro
16433 argument rather than to initialize temporary for targets that
16434 don't use the mode argument at all. Initialize ctzval to avoid
16437 2020-01-10 Thomas Schwinge <thomas@codesourcery.com>
16439 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition.
16440 * tree-core.h: Document it.
16441 * gimplify.c (gimplify_omp_workshare): Set it.
16442 * omp-low.c (lower_omp_target): Use it.
16443 * tree-pretty-print.c (dump_omp_clause): Print it.
16445 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>:
16446 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'.
16448 2020-01-10 David Malcolm <dmalcolm@redhat.com>
16450 * Makefile.in (OBJS): Add tree-diagnostic-path.o.
16451 * common.opt (fdiagnostics-path-format=): New option.
16452 (diagnostic_path_format): New enum.
16453 (fdiagnostics-show-path-depths): New option.
16454 * coretypes.h (diagnostic_event_id_t): New forward decl.
16455 * diagnostic-color.c (color_dict): Add "path".
16456 * diagnostic-event-id.h: New file.
16457 * diagnostic-format-json.cc (json_from_expanded_location): Make
16459 (json_end_diagnostic): Call context->make_json_for_path if it
16460 exists and the diagnostic has a path.
16461 (diagnostic_output_format_init): Clear context->print_path.
16462 * diagnostic-path.h: New file.
16463 * diagnostic-show-locus.c (colorizer::set_range): Special-case
16464 when printing a run of events in a diagnostic_path so that they
16465 all get the same color.
16466 (layout::m_diagnostic_path_p): New field.
16467 (layout::layout): Initialize it.
16468 (layout::print_any_labels): Don't colorize the label text for an
16469 event in a diagnostic_path.
16470 (gcc_rich_location::add_location_if_nearby): Add
16471 "restrict_to_current_line_spans" and "label" params. Pass the
16472 former to layout.maybe_add_location_range; pass the latter
16473 when calling add_range.
16474 * diagnostic.c: Include "diagnostic-path.h".
16475 (diagnostic_initialize): Initialize context->path_format and
16476 context->show_path_depths.
16477 (diagnostic_show_any_path): New function.
16478 (diagnostic_path::interprocedural_p): New function.
16479 (diagnostic_report_diagnostic): Call diagnostic_show_any_path.
16480 (simple_diagnostic_path::num_events): New function.
16481 (simple_diagnostic_path::get_event): New function.
16482 (simple_diagnostic_path::add_event): New function.
16483 (simple_diagnostic_event::simple_diagnostic_event): New ctor.
16484 (simple_diagnostic_event::~simple_diagnostic_event): New dtor.
16485 (debug): New overload taking a diagnostic_path *.
16486 * diagnostic.def (DK_DIAGNOSTIC_PATH): New.
16487 * diagnostic.h (enum diagnostic_path_format): New enum.
16488 (json::value): New forward decl.
16489 (diagnostic_context::path_format): New field.
16490 (diagnostic_context::show_path_depths): New field.
16491 (diagnostic_context::print_path): New callback field.
16492 (diagnostic_context::make_json_for_path): New callback field.
16493 (diagnostic_show_any_path): New decl.
16494 (json_from_expanded_location): New decl.
16495 * doc/invoke.texi (-fdiagnostics-path-format=): New option.
16496 (-fdiagnostics-show-path-depths): New option.
16497 (-fdiagnostics-color): Add "path" to description of default
16498 GCC_COLORS; describe it.
16499 (-fdiagnostics-format=json): Document how diagnostic paths are
16500 represented in the JSON output format.
16501 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
16502 Add optional params "restrict_to_current_line_spans" and "label".
16503 * opts.c (common_handle_option): Handle
16504 OPT_fdiagnostics_path_format_ and
16505 OPT_fdiagnostics_show_path_depths.
16506 * pretty-print.c: Include "diagnostic-event-id.h".
16507 (pp_format): Implement "%@" format code for printing
16508 diagnostic_event_id_t *.
16509 (selftest::test_pp_format): Add tests for "%@".
16510 * selftest-run-tests.c (selftest::run_tests): Call
16511 selftest::tree_diagnostic_path_cc_tests.
16512 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl.
16513 * toplev.c (general_init): Initialize global_dc->path_format and
16514 global_dc->show_path_depths.
16515 * tree-diagnostic-path.cc: New file.
16516 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make
16517 non-static. Drop "diagnostic" param in favor of storing the
16518 original value of "where" and re-using it.
16519 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of
16520 maybe_unwind_expanded_macro_loc.
16521 (tree_diagnostics_defaults): Initialize context->print_path and
16522 context->make_json_for_path.
16523 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New
16525 (default_tree_make_json_for_path): New decl.
16526 (maybe_unwind_expanded_macro_loc): New decl.
16528 2020-01-10 Jakub Jelinek <jakub@redhat.com>
16530 PR tree-optimization/93210
16531 * fold-const.h (native_encode_initializer,
16532 can_native_interpret_type_p): Declare.
16533 * fold-const.c (native_encode_string): Fix up handling with off != -1,
16535 (native_encode_initializer): New function, moved from dwarf2out.c.
16536 Adjust to native_encode_expr compatible arguments, including dry-run
16537 and partial extraction modes. Don't handle STRING_CST.
16538 (can_native_interpret_type_p): No longer static.
16539 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
16540 offset / BITS_PER_UNIT fits into int and don't call it if
16541 can_native_interpret_type_p fails. If suboff is NULL and for
16542 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
16543 native_encode_initializer.
16544 (fold_const_aggregate_ref_1): Formatting fix.
16545 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
16546 (tree_add_const_value_attribute): Adjust caller.
16548 PR tree-optimization/90838
16549 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16550 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
16551 CTZ_DEFINED_VALUE_AT_ZERO.
16553 2020-01-10 Vladimir Makarov <vmakarov@redhat.com>
16555 PR inline-asm/93027
16556 * lra-constraints.c (match_reload): Permit input operands have the
16557 same mode as output while other input operands have a different
16560 2020-01-10 Wilco Dijkstra <wdijkstr@arm.com>
16562 PR tree-optimization/90838
16563 * tree-ssa-forwprop.c (check_ctz_array): Add new function.
16564 (check_ctz_string): Likewise.
16565 (optimize_count_trailing_zeroes): Likewise.
16566 (simplify_count_trailing_zeroes): Likewise.
16567 (pass_forwprop::execute): Try ctz simplification.
16568 * match.pd: Add matching for ctz idioms.
16570 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16572 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
16574 (aarch64_invalid_unary_op): New function for target hook.
16575 (aarch64_invalid_binary_op): New function for target hook.
16577 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16579 * config.gcc: Add arm_bf16.h.
16580 * config/aarch64/aarch64-builtins.c
16581 (aarch64_simd_builtin_std_type): Add BFmode.
16582 (aarch64_init_simd_builtin_types): Define element types for vector
16584 (aarch64_init_bf16_types): New function.
16585 (aarch64_general_init_builtins): Add arm_init_bf16_types function call.
16586 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
16588 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
16589 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
16591 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
16592 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
16593 * config/aarch64/aarch64.c
16594 (aarch64_classify_vector_mode): Add support for BF types.
16595 (aarch64_gimplify_va_arg_expr): Add support for BF types.
16596 (aarch64_vq_mode): Add support for BF types.
16597 (aarch64_simd_container_mode): Add support for BF types.
16598 (aarch64_mangle_type): Add support for BF scalar type.
16599 * config/aarch64/aarch64.md: Add BFmode to movhf pattern.
16600 * config/aarch64/arm_bf16.h: New file.
16601 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
16602 * config/aarch64/iterators.md: Add BF types to mode attributes.
16603 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
16605 2020-01-10 Jason Merrill <jason@redhat.com>
16607 PR c++/93173 - incorrect tree sharing.
16608 * gimplify.c (copy_if_shared): No longer static.
16609 * gimplify.h: Declare it.
16611 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16613 * doc/invoke.texi (-msve-vector-bits=): Document that
16614 -msve-vector-bits=128 now generates VL-specific code for
16615 little-endian targets.
16616 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
16617 build_vector_type_for_mode to construct the data vector types.
16618 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
16619 VL-specific code for -msve-vector-bits=128 on little-endian targets.
16620 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes
16621 for 128-bit vectors.
16623 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16625 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
16628 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16630 * config/aarch64/aarch64-builtins.c
16631 (aarch64_builtin_vectorized_function): Check for specific vector modes,
16632 rather than checking the number of elements and the element mode.
16634 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16636 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use
16637 get_related_vectype_for_scalar_type rather than build_vector_type
16638 to create the index type for a conditional reduction.
16640 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16642 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
16643 for any type of gather or scatter, including strided accesses.
16645 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16647 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
16650 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16652 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
16653 get_dr_vinfo_offset
16654 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init
16655 parameter and its use to reset DR_OFFSET's.
16656 (vect_transform_loop): Remove orig_drs_init argument.
16657 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
16658 member of dr_vec_info rather than the offset of the associated
16659 data_reference's innermost_loop_behavior.
16660 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
16661 (vect_do_peeling): Remove orig_drs_init parameter and its construction.
16662 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
16663 get_dr_vinfo_offset.
16664 (vectorizable_store): Likewise.
16665 (vectorizable_load): Likewise.
16667 2020-01-10 Richard Biener <rguenther@suse.de>
16669 * gimple-ssa-store-merging
16670 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info.
16672 2020-01-10 Martin Liska <mliska@suse.cz>
16675 * ipa-inline-analysis.c (offline_size): Make proper parenthesis
16676 encapsulation that was there before r280040.
16678 2020-01-10 Richard Biener <rguenther@suse.de>
16680 PR middle-end/93199
16681 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
16682 sequences to avoid walking them again for secondary opportunities.
16683 (pass_lower_eh_dispatch::execute): Instead actually insert
16686 2020-01-10 Richard Biener <rguenther@suse.de>
16688 PR middle-end/93199
16689 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
16690 (cleanup_all_empty_eh): Walk landing pads in reverse order to
16691 avoid quadraticness.
16693 2020-01-10 Martin Jambor <mjambor@suse.cz>
16695 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
16696 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
16697 to get param_ipa_sra_max_replacements.
16698 (param_splitting_across_edge): Pass the caller to
16699 pull_accesses_from_callee.
16701 2020-01-10 Martin Jambor <mjambor@suse.cz>
16703 * params.opt (param_ipcp_unit_growth): Mark as Optimization.
16704 * ipa-cp.c (max_new_size): Removed.
16705 (orig_overall_size): New variable.
16706 (get_max_overall_size): New function.
16707 (estimate_local_effects): Use it. Adjust dump.
16708 (decide_about_value): Likewise.
16709 (ipcp_propagate_stage): Do not calculate max_new_size, just store
16710 orig_overall_size. Adjust dump.
16711 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.
16713 2020-01-10 Martin Jambor <mjambor@suse.cz>
16715 * params.opt (param_ipa_max_agg_items): Mark as Optimization
16716 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
16717 instead of param_ipa_max_agg_items.
16718 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from
16719 optimization info for the callee.
16721 2020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com>
16723 * lto-streamer-in.c (input_function): Remove streamed-in inline debug
16724 markers if debug_inline_points is false.
16726 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16728 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
16730 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
16731 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
16732 aarch64-sve-builtins-sve2.h.
16733 (aarch64-sve-builtins-sve2.o): New rule.
16734 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
16735 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
16736 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
16737 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
16738 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
16739 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
16741 * config/aarch64/aarch64-sve.md: Update comments with SVE2
16742 instructions that are handled here.
16743 (@cond_asrd<mode>): Generalize to...
16744 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
16745 (*cond_asrd<mode>_2): Generalize to...
16746 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
16747 (*cond_asrd<mode>_z): Generalize to...
16748 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
16749 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
16750 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
16751 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
16752 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
16754 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
16755 (@aarch64_scatter_stnt<mode>): Likewise.
16756 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
16757 (@aarch64_mul_lane_<mode>): Likewise.
16758 (@aarch64_sve_suqadd<mode>_const): Likewise.
16759 (*<sur>h<addsub><mode>): Generalize to...
16760 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
16762 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
16763 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
16764 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
16765 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
16766 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
16767 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
16768 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
16769 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
16770 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
16771 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
16772 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
16773 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
16774 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
16775 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
16776 (@aarch64_sve_add_mul_lane_<mode>): Likewise.
16777 (@aarch64_sve_sub_mul_lane_<mode>): Likewise.
16778 (@aarch64_sve2_xar<mode>): Likewise.
16779 (@aarch64_sve2_bcax<mode>): Likewise.
16780 (*aarch64_sve2_eor3<mode>): Rename to...
16781 (@aarch64_sve2_eor3<mode>): ...this.
16782 (@aarch64_sve2_bsl<mode>): New expander.
16783 (@aarch64_sve2_nbsl<mode>): Likewise.
16784 (@aarch64_sve2_bsl1n<mode>): Likewise.
16785 (@aarch64_sve2_bsl2n<mode>): Likewise.
16786 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
16787 (*aarch64_sve2_sra<mode>): Add MOVPRFX support.
16788 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
16789 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
16790 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
16791 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
16792 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
16793 (<su>mull<bt><Vwide>): Generalize to...
16794 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
16796 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
16797 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
16798 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
16799 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16800 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
16801 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16802 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
16803 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16804 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
16805 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16806 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
16807 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
16808 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
16809 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
16810 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
16811 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
16812 (<SHRNB:r>shrnb<mode>): Generalize to...
16813 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
16815 (<SHRNT:r>shrnt<mode>): Generalize to...
16816 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
16818 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
16819 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
16820 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
16821 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
16822 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
16823 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
16824 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
16825 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
16826 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
16827 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
16828 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
16829 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
16830 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
16831 (@aarch64_sve2_cvtnt<mode>): Likewise.
16832 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
16833 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
16834 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
16835 (@aarch64_sve2_cvtxnt<mode>): Likewise.
16836 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
16837 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
16838 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
16839 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
16840 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
16841 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
16842 (@aarch64_sve2_pmul<mode>): Likewise.
16843 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
16844 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
16845 (@aarch64_sve2_tbl2<mode>): Likewise.
16846 (@aarch64_sve2_tbx<mode>): Likewise.
16847 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
16848 (@aarch64_sve2_histcnt<mode>): Likewise.
16849 (@aarch64_sve2_histseg<mode>): Likewise.
16850 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
16851 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
16852 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
16853 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
16854 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
16855 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
16856 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
16857 (<su>mulh<r>s<mode>3): Update after above pattern name changes.
16858 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
16859 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
16860 (SVE2_PMULL_PAIR_I): New mode iterators.
16861 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
16862 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
16863 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
16864 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
16865 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
16866 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
16867 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
16868 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
16869 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
16870 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
16871 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
16872 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
16873 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
16874 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
16875 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
16876 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
16877 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
16878 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
16879 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
16880 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
16881 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
16882 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
16883 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
16884 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
16885 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
16886 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
16887 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
16888 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
16889 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
16890 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
16891 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
16893 (VNARROW, Ventype): New mode attributes.
16894 (Vewtype): Handle VNx2DI. Fix typo in comment.
16895 (VDOUBLE): New mode attribute.
16896 (sve_lane_con): Handle VNx8HI.
16897 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
16898 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
16899 (sve_int_op, sve_int_op_rev): Handle the above codes.
16900 (sve_pred_int_rhs2_operand): Likewise.
16901 (MULLBT, SHRNB, SHRNT): Delete.
16902 (SVE_INT_SHIFT_IMM): New int iterator.
16903 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
16904 and UNSPEC_WHILEHS for TARGET_SVE2.
16905 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
16906 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
16907 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
16908 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
16909 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
16910 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
16911 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
16912 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
16913 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
16914 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
16915 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
16916 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
16917 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
16918 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
16919 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
16920 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
16921 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
16922 (optab): Handle the new unspecs.
16923 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
16925 (lr): Handle the new unspecs.
16927 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
16928 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
16929 (sve_int_qsub_op): New int attributes.
16930 (sve_fp_op, rot): Handle the new unspecs.
16931 * config/aarch64/aarch64-sve-builtins.h
16932 (function_resolver::require_matching_pointer_type): Declare.
16933 (function_resolver::resolve_unary): Add an optional boolean argument.
16934 (function_resolver::finish_opt_n_resolution): Add an optional
16935 type_suffix_index argument.
16936 (gimple_folder::redirect_call): Declare.
16937 (gimple_expander::prepare_gather_address_operands): Add an optional
16939 * config/aarch64/aarch64-sve-builtins.cc: Include
16940 aarch64-sve-builtins-sve2.h.
16941 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
16942 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
16943 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
16944 (TYPES_hsd_integer): Use TYPES_hsd_signed.
16945 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
16946 (TYPES_s_unsigned): Likewise.
16947 (TYPES_s_integer): Use TYPES_s_unsigned.
16948 (TYPES_sd_signed, TYPES_sd_unsigned): New macros.
16949 (TYPES_sd_integer): Use them.
16950 (TYPES_d_unsigned): New macro.
16951 (TYPES_d_integer): Use it.
16952 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
16953 (TYPES_cvt_narrow): Likewise.
16954 (DEF_SVE_TYPES_ARRAY): Include the new types macros above.
16955 (preds_mx): New variable.
16956 (function_builder::add_overloaded_function): Allow the new feature
16957 set to be more restrictive than the original one.
16958 (function_resolver::infer_pointer_type): Remove qualifiers from
16959 the pointer type before printing it.
16960 (function_resolver::require_matching_pointer_type): New function.
16961 (function_resolver::resolve_sv_displacement): Handle functions
16962 that don't support 32-bit vector indices or svint32_t vector offsets.
16963 (function_resolver::finish_opt_n_resolution): Take the inferred type
16964 as a separate argument.
16965 (function_resolver::resolve_unary): Optionally treat all forms in
16966 the same way as normal merging functions.
16967 (gimple_folder::redirect_call): New function.
16968 (function_expander::prepare_gather_address_operands): Add an argument
16969 that says whether scaled forms are available. If they aren't,
16970 handle scaling of vector indices and don't add the extension and
16972 (function_expander::map_to_unspecs): If aarch64_sve isn't available,
16973 fall back to using cond_* instead.
16974 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
16975 Split out the member variables into...
16976 (rtx_code_function_base): ...this new base class.
16977 (rtx_code_function_rotated): Inherit rtx_code_function_base.
16978 (unspec_based_function): Split out the member variables into...
16979 (unspec_based_function_base): ...this new base class.
16980 (unspec_based_function_rotated): Inherit unspec_based_function_base.
16981 (unspec_based_function_exact_insn): New class.
16982 (unspec_based_add_function, unspec_based_add_lane_function)
16983 (unspec_based_lane_function, unspec_based_pred_function)
16984 (unspec_based_qadd_function, unspec_based_qadd_lane_function)
16985 (unspec_based_qsub_function, unspec_based_qsub_lane_function)
16986 (unspec_based_sub_function, unspec_based_sub_lane_function): New
16988 (unspec_based_fused_function): New class.
16989 (unspec_based_mla_function, unspec_based_mls_function): New typedefs.
16990 (unspec_based_fused_lane_function): New class.
16991 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
16993 (CODE_FOR_MODE1): New macro.
16994 (fixed_insn_function): New class.
16995 (while_comparison): Likewise.
16996 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
16997 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
16998 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
16999 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
17000 (load_gather_sv_restricted, shift_left_imm_long): Declare.
17001 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
17002 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
17003 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
17004 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
17005 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
17006 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
17007 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
17008 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
17009 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
17010 Also add an initial argument for unary_convert_narrowt, regardless
17011 of the predication type.
17012 (build_32_64): Allow loads and stores to specify MODE_none.
17013 (build_sv_index64, build_sv_uint_offset): New functions.
17014 (long_type_suffix): New function.
17015 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
17016 (binary_imm_long_base, load_gather_sv_base): Likewise.
17017 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
17018 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
17019 (unary_narrowb_base, unary_narrowt_base): Likewise.
17020 (binary_long_lane_def, binary_long_lane): New shape.
17021 (binary_long_opt_n_def, binary_long_opt_n): Likewise.
17022 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
17023 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
17024 (binary_to_uint_def, binary_to_uint): Likewise.
17025 (binary_wide_def, binary_wide): Likewise.
17026 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
17027 (compare_def, compare): Likewise.
17028 (compare_ptr_def, compare_ptr): Likewise.
17029 (load_ext_gather_index_restricted_def,
17030 load_ext_gather_index_restricted): Likewise.
17031 (load_ext_gather_offset_restricted_def,
17032 load_ext_gather_offset_restricted): Likewise.
17033 (load_gather_sv_def): Inherit from load_gather_sv_base.
17034 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
17035 (shift_left_imm_def, shift_left_imm): Likewise.
17036 (shift_left_imm_long_def, shift_left_imm_long): Likewise.
17037 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
17038 (store_scatter_index_restricted_def,
17039 store_scatter_index_restricted): Likewise.
17040 (store_scatter_offset_restricted_def,
17041 store_scatter_offset_restricted): Likewise.
17042 (tbl_tuple_def, tbl_tuple): Likewise.
17043 (ternary_long_lane_def, ternary_long_lane): Likewise.
17044 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
17045 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
17046 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
17047 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
17048 (ternary_qq_rotate_def, ternary_qq_rotate): New shape.
17049 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
17050 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
17051 (ternary_uint_def, ternary_uint): Likewise.
17052 (unary_convert): Fix typo in comment.
17053 (unary_convert_narrowt_def, unary_convert_narrowt): New shape.
17054 (unary_long_def, unary_long): Likewise.
17055 (unary_narrowb_def, unary_narrowb): Likewise.
17056 (unary_narrowt_def, unary_narrowt): Likewise.
17057 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
17058 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
17059 (unary_to_int_def, unary_to_int): Likewise.
17060 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
17061 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
17062 (svasrd_impl): Delete.
17063 (svcadd_impl::expand): Handle integer operations too.
17064 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
17065 new functions to derive the unspec numbers.
17066 (svmla_svmls_lane_impl): Replace with...
17067 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
17068 integer operations too.
17069 (svwhile_impl): Rename to...
17070 (svwhilelx_impl): ...this and inherit from while_comparison.
17071 (svasrd): Use unspec_based_function.
17072 (svmla_lane): Use svmla_lane_impl.
17073 (svmls_lane): Use svmls_lane_impl.
17074 (svrecpe, svrsqrte): Handle unsigned integer operations too.
17075 (svwhilele, svwhilelt): Use svwhilelx_impl.
17076 * config/aarch64/aarch64-sve-builtins-sve2.h: New file.
17077 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
17078 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
17079 * config/aarch64/aarch64-sve-builtins.def: Include
17080 aarch64-sve-builtins-sve2.def.
17082 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17084 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
17085 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
17086 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
17087 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar
17088 immediates as well as vector ones.
17089 * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
17090 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
17091 (aarch64_sve_qsub_immediate): Update calls accordingly.
17093 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17095 * config/aarch64/aarch64-sve2.md: Add banner comments.
17096 (<su>mulh<r>s<mode>3): Move further up file.
17097 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
17098 (*aarch64_sve2_sra<mode>): Move further down file.
17099 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
17101 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17103 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
17104 and UNSPEC_WHILEWR.
17105 (while_optab_cmp): Handle them.
17106 * config/aarch64/aarch64-sve.md
17107 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public
17108 and add a "@" marker.
17109 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it
17110 instead of gen_aarch64_sve2_while_ptest.
17111 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete.
17113 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17115 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to...
17116 (UNSPEC_WHILELE): ...this.
17117 (UNSPEC_WHILE_LO): Rename to...
17118 (UNSPEC_WHILELO): ...this.
17119 (UNSPEC_WHILE_LS): Rename to...
17120 (UNSPEC_WHILELS): ...this.
17121 (UNSPEC_WHILE_LT): Rename to...
17122 (UNSPEC_WHILELT): ...this.
17123 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly.
17124 (cmp_op, while_optab_cmp): Likewise.
17125 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise.
17126 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise.
17127 (svwhilelt): Likewise.
17129 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17131 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete.
17132 (unary_to_uint): Define.
17133 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def)
17134 (unary_count): Rename to...
17135 (unary_to_uint_def, unary_to_uint): ...this.
17136 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly.
17138 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17140 * config/aarch64/aarch64-sve-builtins-functions.h
17141 (code_for_mode_function): New class.
17142 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros.
17143 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl)
17144 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete.
17145 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0.
17146 (svmul_lane, svtmad): Use CODE_FOR_MODE0.
17148 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17150 * config/aarch64/iterators.md (addsub): New code attribute.
17151 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
17153 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
17154 in the asm string and attributes. Fix indentation.
17155 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
17157 (@aarch64_sve_<optab><mode>): ...this.
17158 * config/aarch64/aarch64-sve-builtins.h
17159 (function_expander::expand_signed_unpred_op): Delete.
17160 * config/aarch64/aarch64-sve-builtins.cc
17161 (function_expander::expand_signed_unpred_op): Likewise.
17162 (function_expander::map_to_rtx_codes): If the optab isn't defined,
17163 try using code_for_aarch64_sve instead.
17164 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
17165 (svqsub_impl): Likewise.
17166 (svqadd, svqsub): Use rtx_code_function instead.
17168 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17170 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete.
17171 (HADDSUB, sur, addsub): Remove them.
17173 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17175 * tree-nrv.c (pass_return_slot::execute): Handle all internal
17176 functions the same way, rather than singling out those that
17177 aren't mapped directly to optabs.
17179 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17181 * target.def (compatible_vector_types_p): New target hook.
17182 * hooks.h (hook_bool_const_tree_const_tree_true): Declare.
17183 * hooks.c (hook_bool_const_tree_const_tree_true): New function.
17184 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook.
17185 * doc/tm.texi: Regenerate.
17186 * gimple-expr.c: Include target.h.
17187 (useless_type_conversion_p): Use targetm.compatible_vector_types_p.
17188 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New
17190 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define.
17191 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred):
17192 Use the original predicate if it already has a suitable type.
17194 2020-01-09 Martin Jambor <mjambor@suse.cz>
17196 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct,
17197 resolve_speculation and redirect_call_stmt_to_callee static. Change
17198 return type of set_call_stmt to cgraph_edge *.
17199 * auto-profile.c (afdo_indirect_call): Adjust call to
17200 redirect_call_stmt_to_callee.
17201 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *,
17202 make the this pointer explicit, adjust self-recursive calls and the
17203 call top make_direct. Return the resulting edge.
17204 (cgraph_edge::remove): Make this pointer explicit.
17205 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove.
17206 (cgraph_edge::make_direct): Likewise, adjust call to
17207 resolve_speculation.
17208 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust
17209 call to set_call_stmt.
17210 (cgraph_update_edges_for_call_stmt_node): Update call to
17211 set_call_stmt and remove.
17212 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
17213 Renamed edge to master_edge. Adjusted calls to set_call_stmt.
17214 (cgraph_node::create_edge_including_clones): Moved "first" definition
17215 of edge to the block where it was used. Adjusted calls to
17217 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to
17218 cgraph_edge::remove.
17219 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to
17220 make_direct and redirect_call_stmt_to_callee.
17221 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to
17222 resolve_speculation and make_direct.
17223 * ipa-inline-transform.c (inline_transform): Adjust call to
17224 redirect_call_stmt_to_callee.
17225 (check_speculations_1):: Adjust call to resolve_speculation.
17226 * ipa-inline.c (resolve_noninline_speculation): Adjust call to
17227 resolve-speculation.
17228 (inline_small_functions): Adjust call to resolve_speculation.
17229 (ipa_inline): Likewise.
17230 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to
17232 * ipa-visibility.c (function_and_variable_visibility): Make iteration
17233 safe with regards to edge removal, adjust calls to
17234 redirect_call_stmt_to_callee.
17235 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct
17236 and redirect_call_stmt_to_callee.
17237 * multiple_target.c (create_dispatcher_calls): Adjust call to
17238 redirect_call_stmt_to_callee
17239 (redirect_to_specific_clone): Likewise.
17240 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph):
17241 Adjust calls to cgraph_edge::remove.
17242 * tree-inline.c (copy_bb): Adjust call to set_call_stmt.
17243 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee.
17244 (expand_call_inline): Adjust call to cgraph_edge::remove.
17246 2020-01-09 Martin Liska <mliska@suse.cz>
17248 * params.opt: Set Optimization for
17249 param_max_speculative_devirt_maydefs.
17251 2020-01-09 Martin Sebor <msebor@redhat.com>
17253 PR middle-end/93200
17255 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type.
17257 2020-01-09 Martin Liska <mliska@suse.cz>
17259 * auto-profile.c (auto_profile): Use opt_for_fn
17261 * ipa-cp.c (ipcp_lattice::add_value): Likewise.
17262 (propagate_vals_across_arith_jfunc): Likewise.
17263 (hint_time_bonus): Likewise.
17264 (incorporate_penalties): Likewise.
17265 (good_cloning_opportunity_p): Likewise.
17266 (perform_estimation_of_a_value): Likewise.
17267 (estimate_local_effects): Likewise.
17268 (ipcp_propagate_stage): Likewise.
17269 * ipa-fnsummary.c (decompose_param_expr): Likewise.
17270 (set_switch_stmt_execution_predicate): Likewise.
17271 (analyze_function_body): Likewise.
17272 * ipa-inline-analysis.c (offline_size): Likewise.
17273 * ipa-inline.c (early_inliner): Likewise.
17274 * ipa-prop.c (ipa_analyze_node): Likewise.
17275 (ipcp_transform_function): Likewise.
17276 * ipa-sra.c (process_scan_results): Likewise.
17277 (ipa_sra_summarize_function): Likewise.
17278 * params.opt: Rename ipcp-unit-growth to
17279 ipa-cp-unit-growth. Add Optimization for various
17280 IPA-related parameters.
17282 2020-01-09 Richard Biener <rguenther@suse.de>
17284 PR middle-end/93054
17285 * gimplify.c (gimplify_expr): Deal with NOP definitions.
17287 2020-01-09 Richard Biener <rguenther@suse.de>
17289 PR tree-optimization/93040
17290 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit.
17292 2020-01-09 Georg-Johann Lay <avr@gjlay.de>
17294 * common/config/avr/avr-common.c (avr_option_optimization_table)
17295 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.
17297 2020-01-09 Martin Liska <mliska@suse.cz>
17299 * cgraphclones.c (symbol_table::materialize_all_clones):
17300 Use cgraph_node::dump_name.
17302 2020-01-09 Jakub Jelinek <jakub@redhat.com>
17304 PR inline-asm/93202
17305 * config/riscv/riscv.c (riscv_print_operand_reloc): Use
17306 output_operand_lossage instead of gcc_unreachable.
17307 * doc/md.texi (riscv f constraint): Fix typo.
17310 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
17311 SWI. Use <general_hilo_operand> instead of <general_operand>. Use
17312 CONST_SCALAR_INT_P instead of CONST_INT_P.
17313 (*subv<mode>4_1): Rename to ...
17314 (subv<mode>4_1): ... this.
17315 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
17316 define_insn_and_split patterns.
17317 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
17320 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17322 * vec.c (class selftest::count_dtor): New class.
17323 (selftest::test_auto_delete_vec): New test.
17324 (selftest::vec_c_tests): Call it.
17325 * vec.h (class auto_delete_vec): New class template.
17326 (auto_delete_vec<T>::~auto_delete_vec): New dtor.
17328 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17330 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap.
17332 2020-01-08 Jim Wilson <jimw@sifive.com>
17334 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out
17335 use of TLS_MODEL_LOCAL_EXEC when not pic.
17337 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17339 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix
17342 2020-01-08 Jakub Jelinek <jakub@redhat.com>
17345 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2,
17346 *stack_protect_set_3 peephole2): Also check that the second
17347 insns source is general_operand.
17350 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand
17351 predicate for output operand instead of register_operand.
17352 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with
17353 memory destination and non-memory operands[2].
17355 2020-01-08 Martin Liska <mliska@suse.cz>
17357 * cgraph.c (cgraph_node::dump): Use ::dump_name or
17358 ::dump_asm_name instead of (::name or ::asm_name).
17359 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise.
17360 * cgraphunit.c (walk_polymorphic_call_targets): Likewise.
17361 (analyze_functions): Likewise.
17362 (expand_all_functions): Likewise.
17363 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise.
17364 (propagate_bits_across_jump_function): Likewise.
17365 (dump_profile_updates): Likewise.
17366 (ipcp_store_bits_results): Likewise.
17367 (ipcp_store_vr_results): Likewise.
17368 * ipa-devirt.c (dump_targets): Likewise.
17369 * ipa-fnsummary.c (analyze_function_body): Likewise.
17370 * ipa-hsa.c (check_warn_node_versionable): Likewise.
17371 (process_hsa_functions): Likewise.
17372 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise.
17373 (set_alias_uids): Likewise.
17374 * ipa-inline-transform.c (save_inline_function_body): Likewise.
17375 * ipa-inline.c (recursive_inlining): Likewise.
17376 (inline_to_all_callers_1): Likewise.
17377 (ipa_inline): Likewise.
17378 * ipa-profile.c (ipa_propagate_frequency_1): Likewise.
17379 (ipa_propagate_frequency): Likewise.
17380 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
17381 (remove_described_reference): Likewise.
17382 * ipa-pure-const.c (worse_state): Likewise.
17383 (check_retval_uses): Likewise.
17384 (analyze_function): Likewise.
17385 (propagate_pure_const): Likewise.
17386 (propagate_nothrow): Likewise.
17387 (dump_malloc_lattice): Likewise.
17388 (propagate_malloc): Likewise.
17389 (pass_local_pure_const::execute): Likewise.
17390 * ipa-visibility.c (optimize_weakref): Likewise.
17391 (function_and_variable_visibility): Likewise.
17392 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise.
17393 (ipa_discover_variable_flags): Likewise.
17394 * lto-streamer-out.c (output_function): Likewise.
17395 (output_constructor): Likewise.
17396 * tree-inline.c (copy_bb): Likewise.
17397 * tree-ssa-structalias.c (ipa_pta_execute): Likewise.
17398 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise.
17400 2020-01-08 Richard Biener <rguenther@suse.de>
17402 PR middle-end/93199
17403 * tree-eh.c (sink_clobbers): Update virtual operands for
17404 the first and last stmt only. Add a dry-run capability.
17405 (pass_lower_eh_dispatch::execute): Perform clobber sinking
17406 after CFG manipulations and in RPO order to catch all
17407 secondary opportunities reliably.
17409 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17412 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17414 2019-01-08 Richard Biener <rguenther@suse.de>
17416 PR middle-end/93199
17417 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
17418 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
17419 virtual operand, also updating SSA use.
17420 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
17421 Update stmt after resetting virtual operand.
17422 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
17423 * gimple-iterator.c (gsi_remove): When not removing the stmt
17424 permanently do not delink immediate uses or mark the stmt modified.
17426 2020-01-08 Martin Liska <mliska@suse.cz>
17428 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
17429 (ipa_call_context::estimate_size_and_time): Likewise.
17430 (inline_analyze_function): Likewise.
17432 2020-01-08 Martin Liska <mliska@suse.cz>
17434 * cgraph.c (cgraph_node::dump): Use systematically
17437 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17439 Add -nodevicespecs option for avr.
17442 * config/avr/avr.opt (-nodevicespecs): New driver option.
17443 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
17444 "-specs=device-specs/..." if that option is not set.
17445 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17447 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17449 Implement 64-bit double functions for avr.
17452 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
17453 --with-double-comparison.
17454 * doc/install.texi: Document them.
17455 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
17456 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
17457 <WITH_DOUBLE_COMPARISON>: New built-in defines.
17458 * doc/invoke.texi (AVR Built-in Macros): Document them.
17459 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
17460 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
17461 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
17463 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
17466 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
17467 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
17468 when only building rm-profile multilibs.
17470 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
17473 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
17474 lattice for a value to check.
17475 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
17476 finite propagation in self-recursive scc.
17478 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
17480 * ipa-inline.c (caller_growth_limits): Restore the AND.
17482 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17484 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
17485 (VEC_ALLREG_ALT): New iterator.
17486 (VEC_ALLREG_INT_MODE): New iterator.
17487 (VCMP_MODE): New iterator.
17488 (VCMP_MODE_INT): New iterator.
17489 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
17490 (vec_cmp<u>v64qidi): New define_expand.
17491 (vec_cmp<mode>di_exec): Use VCMP_MODE.
17492 (vec_cmpu<mode>di_exec): New define_expand.
17493 (vec_cmp<u>v64qidi_exec): New define_expand.
17494 (vec_cmp<mode>di_dup): Use VCMP_MODE.
17495 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
17496 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
17497 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
17498 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
17499 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
17500 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
17501 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
17502 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
17503 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
17505 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
17506 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
17508 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17510 * config/gcn/constraints.md (DA): Update description and match.
17512 (Db): New constraint.
17513 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
17515 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
17516 Implement 'Db' mixed immediate type.
17517 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
17518 (addcv64si3_dup<exec_vcc>): Delete.
17519 (subcv64si3<exec_vcc>): Rework constraints.
17520 (addv64di3): Rework constraints.
17521 (addv64di3_exec): Rework constraints.
17522 (subv64di3): Rework constraints.
17523 (addv64di3_dup): Delete.
17524 (addv64di3_dup_exec): Delete.
17525 (addv64di3_zext): Rework constraints.
17526 (addv64di3_zext_exec): Rework constraints.
17527 (addv64di3_zext_dup): Rework constraints.
17528 (addv64di3_zext_dup_exec): Rework constraints.
17529 (addv64di3_zext_dup2): Rework constraints.
17530 (addv64di3_zext_dup2_exec): Rework constraints.
17531 (addv64di3_sext_dup2): Rework constraints.
17532 (addv64di3_sext_dup2_exec): Rework constraints.
17534 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
17536 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
17537 existing target checks.
17539 2020-01-07 Richard Biener <rguenther@suse.de>
17541 * doc/install.texi: Bump minimal supported MPC version.
17543 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17545 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
17546 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
17547 * langhooks.c: Include stor-layout.h.
17548 (lhd_simulate_enum_decl): New function.
17549 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
17550 handle_arm_sve_h for the LTO frontend.
17551 (register_vector_type): Cope with null returns from pushdecl.
17553 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17555 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
17556 (aarch64_sve::nvectors_if_data_type): Replace with...
17557 (aarch64_sve::builtin_type_p): ...this.
17558 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
17559 (find_vector_type): Delete.
17560 (add_sve_type_attribute): New function.
17561 (lookup_sve_type_attribute): Likewise.
17562 (register_builtin_types): Add an "SVE type" attribute to each type.
17563 (register_tuple_type): Likewise.
17564 (svbool_type_p, nvectors_if_data_type): Delete.
17565 (mangle_builtin_type): Use lookup_sve_type_attribute.
17566 (builtin_type_p): Likewise. Add an overload that returns the
17567 number of constituent vector and predicate registers.
17568 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
17569 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
17570 instead of aarch64_sve_argument_p.
17571 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
17572 (aarch64_pass_by_reference): Likewise.
17573 (aarch64_function_value_1): Likewise.
17574 (aarch64_return_in_memory): Likewise.
17575 (aarch64_layout_arg): Likewise.
17577 2020-01-07 Jakub Jelinek <jakub@redhat.com>
17579 PR tree-optimization/93156
17580 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
17581 least significant bit is always clear.
17583 PR tree-optimization/93118
17584 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
17585 simplifier with two intermediate conversions.
17587 2020-01-07 Martin Liska <mliska@suse.cz>
17589 * params.opt: Add Optimization for various parameters.
17591 2020-01-07 Martin Liska <mliska@suse.cz>
17594 * doc/extend.texi: Explain cloning for target_clone
17597 2020-01-07 Martin Liska <mliska@suse.cz>
17599 PR tree-optimization/92860
17600 * common.opt: Make in Optimization option
17601 as it is affected by -O0, which is an Optimization
17603 * tree-inline.c (tree_inlinable_function_p):
17604 Use opt_for_fn for warn_inline.
17605 (expand_call_inline): Likewise.
17607 2020-01-07 Martin Liska <mliska@suse.cz>
17609 PR tree-optimization/92860
17610 * common.opt: Make flag_ree as optimization
17613 2020-01-07 Martin Liska <mliska@suse.cz>
17615 PR optimization/92860
17616 * params.opt: Mark param_min_crossjump_insns with Optimization
17619 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
17621 * ipa-inline-analysis.c (estimate_growth): Fix typo.
17622 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
17624 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
17626 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
17627 helper function to return the valid addressing formats for a given
17628 hard register and mode.
17629 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
17631 * config/rs6000/constraints.md (Q constraint): Update
17633 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
17636 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
17637 Use 'Q' for doing vector extract from memory.
17638 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
17640 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
17641 doing vector extract from memory.
17642 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
17643 extract from memory.
17645 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
17646 for the offset being 34-bits when -mcpu=future is used.
17648 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
17650 * config/pa/pa.md: Revert change to use ordered_comparison_operator
17651 instead of cmpib_comparison_operator in cmpib patterns.
17652 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
17653 of cmpib_comparison_operator. Revise comment.
17655 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17657 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
17658 in an IFN_DIV_POW2 node to be equal.
17660 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17662 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
17663 (vect_check_scalar_mask): ...this.
17664 (vectorizable_store, vectorizable_load): Update call accordingly.
17665 (vectorizable_call): Use vect_check_scalar_mask to check the mask
17666 argument in calls to conditional internal functions.
17668 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17670 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
17671 '0' matching inputs.
17672 (subv64di3_exec): Likewise.
17674 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
17676 * config/mips/mips.c (vr4130_align_insns): Fix typo.
17677 * doc/md.texi (movstr): Likewise.
17679 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17681 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
17684 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17686 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
17688 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
17689 to a temporary file and use move-if-change to update the real
17690 file where necessary.
17692 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17694 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
17695 rather than Upa for CPY /M.
17697 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17699 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
17702 2020-01-06 Martin Liska <mliska@suse.cz>
17704 PR tree-optimization/92860
17705 * params.opt: Mark param_max_combine_insns with Optimization
17708 2020-01-05 Jakub Jelinek <jakub@redhat.com>
17711 * config/i386/i386.md (SWIDWI): New mode iterator.
17712 (DWI, dwi): Add TImode variants.
17713 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
17714 <general_hilo_operand> instead of <general_operand>. Use
17715 CONST_SCALAR_INT_P instead of CONST_INT_P.
17716 (*addv<mode>4_1): Rename to ...
17717 (addv<mode>4_1): ... this.
17718 (QWI): New mode attribute.
17719 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
17720 define_insn_and_split patterns.
17721 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
17723 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
17724 <general_hilo_operand> instead of <general_operand>.
17725 (*addcarry<mode>_1): New define_insn.
17726 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
17728 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
17730 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
17731 Use "call" instead of "set".
17733 2020-01-03 Martin Jambor <mjambor@suse.cz>
17736 * ipa-cp.c (print_all_lattices): Skip functions without info.
17738 2020-01-03 Jakub Jelinek <jakub@redhat.com>
17741 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
17742 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
17743 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
17744 for 'e' simd clones.
17747 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
17749 (mprefer-vector-width=): Add Save.
17750 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
17751 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
17752 (ix86_debug_options, ix86_function_specific_print): Adjust
17753 ix86_target_string callers.
17754 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
17755 (ix86_valid_target_attribute_tree): Likewise.
17756 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
17757 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
17758 ix86_target_string caller.
17761 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
17762 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
17763 instead of gen_int_shift_amount + convert_modes.
17765 PR rtl-optimization/93088
17766 * loop-iv.c (find_single_def_src): Punt after looking through
17767 128 reg copies for regs with single definitions. Move definitions
17770 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
17772 * config/arm/arm-c.c (arm_cpu_builtins): Define
17773 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
17774 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
17775 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
17776 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
17777 * config/arm/arm-tables.opt: Regenerated.
17778 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
17779 arm_arch_i8mm and arm_arch_bf16 when enabled.
17780 * config/arm/arm.h (TARGET_I8MM): New macro.
17781 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
17782 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
17783 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
17784 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
17785 (v8_6_a_simd_variants): New.
17786 (v8_*_a_simd_variants): Add i8mm and bf16.
17787 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
17789 2020-01-02 Jakub Jelinek <jakub@redhat.com>
17792 * predict.c (compute_function_frequency): Don't call
17793 warn_function_cold on functions that already have cold attribute.
17795 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
17798 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
17799 COMDAT group function labels in .data.rel.ro.local section.
17800 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
17803 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
17804 comparison_operator in B and S integer comparisons. Likewise, use
17805 ordered_comparison_operator instead of cmpib_comparison_operator in
17807 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
17809 2020-01-01 Jakub Jelinek <jakub@redhat.com>
17811 Update copyright years.
17813 * gcc.c (process_command): Update copyright notice dates.
17814 * gcov-dump.c (print_version): Ditto.
17815 * gcov.c (print_version): Ditto.
17816 * gcov-tool.c (print_version): Ditto.
17817 * gengtype.c (create_file): Ditto.
17818 * doc/cpp.texi: Bump @copying's copyright year.
17819 * doc/cppinternals.texi: Ditto.
17820 * doc/gcc.texi: Ditto.
17821 * doc/gccint.texi: Ditto.
17822 * doc/gcov.texi: Ditto.
17823 * doc/install.texi: Ditto.
17824 * doc/invoke.texi: Ditto.
17826 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
17828 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
17831 2020-01-01 Jakub Jelinek <jakub@redhat.com>
17833 PR tree-optimization/93098
17834 * match.pd (popcount): For shift amounts, use integer_onep
17835 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
17836 tests. Make sure that precision is power of two larger than or equal
17837 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
17838 instead of ULL suffixed constants. Formatting fixes.
17840 Copyright (C) 2020 Free Software Foundation, Inc.
17842 Copying and distribution of this file, with or without modification,
17843 are permitted in any medium without royalty provided the copyright
17844 notice and this notice are preserved.