1 2020-05-18 Uroš Bizjak <ubizjak@gmail.com>
3 * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator):
4 Do not emit FLAGS_REG clobber for TFmode.
5 * config/i386/i386.md (*<code>tf2_1): Rewrite as
6 define_insn_and_split. Mark operands 1 and 2 commutative.
8 (absneg SSE splitter): Use MODEF mode iterator instead of SSEMODEF.
9 Do not swap memory operands. Simplify RTX generation.
10 (neg abs SSE splitter): Ditto.
11 * config/i386/sse.md (*<code><mode>2): Mark operands 1 and 2
12 commutative. Do not swap operands. Simplify RTX generation.
13 (*nabs<mode>2): Ditto.
15 2020-05-18 Richard Biener <rguenther@suse.de>
17 * tree-vect-slp.c (vect_slp_bb): Start after labels.
18 (vect_get_constant_vectors): Really place init stmt after scalar defs.
19 * tree-vect-stmts.c (vect_init_vector_1): Insert before
22 2020-05-18 H.J. Lu <hongjiu.lu@intel.com>
24 * config/i386/driver-i386.c (host_detect_local_cpu): Support
25 Intel Airmont, Tremont, Comet Lake, Ice Lake and Tiger Lake
28 2020-05-18 Richard Biener <rguenther@suse.de>
31 * tree-inline.c (remap_gimple_stmt): Split out trapping compares
32 when inlining into a non-call EH function.
34 2020-05-18 Richard Biener <rguenther@suse.de>
36 PR tree-optimization/95172
37 * tree-ssa-loop-im.c (execute_sm): Get flag whether we
38 eventually need the conditional processing.
39 (execute_sm_exit): When processing an orderd sequence
40 avoid doing any conditional processing.
41 (hoist_memory_references): Pass down whether all edges
42 have ordered processing for a ref to execute_sm.
44 2020-05-17 Jeff Law <law@redhat.com>
46 * config/h8300/predicates.md (pc_or_label_operand): New predicate.
47 * config/h8300/jumpcall.md (branch_true, branch_false): Consolidate
48 into a single pattern using pc_or_label_operand.
49 * config/h8300/combiner.md (bit branch patterns): Likewise.
50 * config/h8300/peepholes.md (HImode and SImode branches): Likewise.
52 2020-05-17 H.J. Lu <hongjiu.lu@intel.com>
55 * config/i386/i386-features.c (has_non_address_hard_reg):
57 (pseudo_reg_set): This. Return the SET expression. Ignore
59 (general_scalar_to_vector_candidate_p): Combine single_set and
60 has_non_address_hard_reg calls to pseudo_reg_set.
61 (timode_scalar_to_vector_candidate_p): Likewise.
62 * config/i386/i386.md (*pushv1ti2): New pattern.
64 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
67 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
69 * tree-vrp.c (operand_less_p): Move to...
70 * vr-values.c (operand_less_p): ...here.
71 * tree-vrp.h (operand_less_p): Remove.
73 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
75 * tree-vrp.c (operand_less_p): Move to...
76 * vr-values.c (operand_less_p): ...here.
77 * tree-vrp.h (operand_less_p): Remove.
79 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
81 * tree-vrp.c (class vrp_insert): Remove prototype for
84 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
86 * tree-vrp.c (class live_names): New.
87 (live_on_edge): Move into live_names.
88 (build_assert_expr_for): Move into vrp_insert.
89 (find_assert_locations_in_bb): Rename from
90 find_assert_locations_1.
91 (process_assert_insertions_for): Move into vrp_insert.
92 (compare_assert_loc): Same.
93 (remove_range_assertions): Same.
94 (dump_asserts_for): Rename to vrp_insert::dump.
95 (debug_asserts_for): Rename to vrp_insert::debug.
96 (dump_all_asserts): Rename to vrp_insert::dump.
97 (debug_all_asserts): Rename to vrp_insert::debug.
99 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
101 * tree-vrp.c (class vrp_prop): Move check_all_array_refs,
102 check_array_ref, check_mem_ref, and search_for_addr_array
104 (class array_bounds_checker): ...here.
105 (class check_array_bounds_dom_walker): Adjust to use
106 array_bounds_checker.
107 (check_all_array_refs): Move into array_bounds_checker and rename
109 (class vrp_folder): Make fold_predicate_in private.
111 2020-05-15 Jeff Law <law@redhat.com>
113 * config/h8300/h8300.md (SFI iterator): New iterator for
115 * config/h8300/peepholes.md (memory comparison): Use mode
116 iterator to consolidate 3 patterns into one.
117 (stack allocation and stack store): Handle SFmode. Handle
120 2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
122 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_2): Also require
123 RS6000_BTM_POWERPC64.
125 2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
127 * config/i386/i386.md (SWI48DWI): New mode iterator.
128 (*push<mode>2): Allow XMM registers.
129 (*pushdi2_rex64): Ditto.
130 (*pushsi2_rex64): Ditto.
132 (push XMM reg splitter): New splitter
134 (*pushdf) Change "x" operand constraint to "v".
135 (*pushsf_rex64): Ditto.
138 2020-05-15 Richard Biener <rguenther@suse.de>
140 PR tree-optimization/92260
141 * tree-vect-slp.c (vect_get_constant_vectors): Compute
142 the number of vector stmts in a canonical way.
144 2020-05-15 Martin Liska <mliska@suse.cz>
146 * hsa-gen.c (get_symbol_for_decl): Fix misleading indentation
149 2020-05-15 Andrew Stubbs <ams@codesourcery.com>
151 * config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.
153 2020-05-15 Richard Biener <rguenther@suse.de>
155 PR tree-optimization/95133
156 * gimple-ssa-split-paths.c
157 (find_block_to_duplicate_for_splitting_paths): Check for
160 2020-05-15 Christophe Lyon <christophe.lyon@linaro.org>
162 * config/arm/arm.c (reg_needs_saving_p): Add support for interrupt
164 (arm_compute_save_reg0_reg12_mask): Use reg_needs_saving_p.
166 2020-05-15 Tobias Burnus <tobias@codesourcery.com>
169 * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with
170 OMP_TARGET_EXIT_DATA, use 'release:' unless the associated
173 2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
176 * config/i386/i386.md (isa): Add sse3_noavx.
177 (enabled): Handle sse3_noavx.
179 * config/i386/mmx.md (mmx_haddv2sf3): New expander.
180 (*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX
181 alternatives. Match commutative vec_select selector operands.
182 (*mmx_haddv2sf3_low): New insn pattern.
184 (*mmx_hsubv2sf3): Add SSE/AVX alternatives.
185 (*mmx_hsubv2sf3_low): New insn pattern.
187 2020-05-15 Richard Biener <rguenther@suse.de>
189 PR tree-optimization/33315
190 * tree-ssa-sink.c: Include tree-eh.h.
191 (sink_stats): Add commoned member.
192 (sink_common_stores_to_bb): New function implementing store
193 commoning by sinking to the successor.
194 (sink_code_in_bb): Call it, pass down TODO_cleanup_cfg returned.
195 (pass_sink_code::execute): Likewise. Record commoned stores
198 2020-05-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
200 PR rtl-optimization/37451, part of PR target/61837
201 * loop-doloop.c (doloop_simplify_count): New function. Simplify
202 (add -1; zero_ext; add +1) to zero_ext when not wrapping.
203 (doloop_modify): Call doloop_simplify_count.
205 2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
208 * doc/sourcebuild.texi: Document effective target lgccjit.
210 2020-05-14 Andrew Stubbs <ams@codesourcery.com>
212 * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a
213 define_expand, and rename the original to ...
214 (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand.
215 (add<mode>3_zext_dup_exec): Likewise, with ...
216 (add<mode>3_vcc_zext_dup_exec): ... this.
217 (add<mode>3_zext_dup2): Likewise, with ...
218 (add<mode>3_zext_dup_exec): ... this.
219 (add<mode>3_zext_dup2_exec): Likewise, with ...
220 (add<mode>3_zext_dup2): ... this.
221 * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch
222 addv64di3_zext* calls to use addv64di3_vcc_zext*.
224 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
227 * config/i386/sse.md (truncv2dfv2df2): New insn pattern.
228 (extendv2sfv2df2): Ditto.
230 2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
232 * configure: Regenerated.
234 2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
236 * config/arm/arm.c (reg_needs_saving_p): New function.
237 (use_return_insn): Use reg_needs_saving_p.
238 (arm_get_vfp_saved_size): Likewise.
239 (arm_compute_frame_layout): Likewise.
240 (arm_save_coproc_regs): Likewise.
241 (thumb1_expand_epilogue): Likewise.
242 (arm_expand_epilogue_apcs_frame): Likewise.
243 (arm_expand_epilogue): Likewise.
245 2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
247 * config/arm/arm.c (thumb1_expand_prologue): Update error message.
249 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
252 * config/i386/sse.md (sse2_cvtpi2pd): Add memory to alternative 1.
254 (floatv2siv2df2): New expander.
255 (floatunsv2siv2df2): New insn pattern.
257 (fix_truncv2dfv2si2): New expander.
258 (fixuns_truncv2dfv2si2): New insn pattern.
260 2020-05-14 Richard Sandiford <richard.sandiford@arm.com>
263 * config/aarch64/aarch64-sve-builtins.cc
264 (handle_arm_sve_vector_bits_attribute): Create a copy of the
265 original type's TYPE_MAIN_VARIANT, then reapply all the differences
266 between the original type and its main variant.
268 2020-05-14 Richard Biener <rguenther@suse.de>
271 * real.c (real_to_decimal_for_mode): Make sure we handle
272 a zero with nonzero exponent.
274 2020-05-14 Jakub Jelinek <jakub@redhat.com>
276 * Makefile.in (GTFILES): Add omp-general.c.
277 * cgraph.h (struct cgraph_node): Add declare_variant_alt and
278 calls_declare_variant_alt members and initialize them in the
280 * ipa.c (symbol_table::remove_unreachable_nodes): Handle direct
281 calls to declare_variant_alt nodes.
282 * lto-cgraph.c (lto_output_node): Write declare_variant_alt
283 and calls_declare_variant_alt.
284 (input_overwrite_node): Read them back.
285 * omp-simd-clone.c (simd_clone_create): Copy calls_declare_variant_alt
287 * tree-inline.c (expand_call_inline): Or in calls_declare_variant_alt
289 (tree_function_versioning): Copy calls_declare_variant_alt bit.
290 * omp-offload.c (execute_omp_device_lower): Call
291 omp_resolve_declare_variant on direct function calls.
292 (pass_omp_device_lower::gate): Also enable for
293 calls_declare_variant_alt functions.
294 * omp-general.c (omp_maybe_offloaded): Return false after inlining.
295 (omp_context_selector_matches): Handle the case when
296 cfun->curr_properties has PROP_gimple_any bit set.
297 (struct omp_declare_variant_entry): New type.
298 (struct omp_declare_variant_base_entry): New type.
299 (struct omp_declare_variant_hasher): New type.
300 (omp_declare_variant_hasher::hash, omp_declare_variant_hasher::equal):
302 (omp_declare_variants): New variable.
303 (struct omp_declare_variant_alt_hasher): New type.
304 (omp_declare_variant_alt_hasher::hash,
305 omp_declare_variant_alt_hasher::equal): New methods.
306 (omp_declare_variant_alt): New variables.
307 (omp_resolve_late_declare_variant): New function.
308 (omp_resolve_declare_variant): Call omp_resolve_late_declare_variant
309 when called late. Create a magic declare_variant_alt fndecl and
310 cgraph node and return that if decision needs to be deferred until
311 after gimplification.
312 * cgraph.c (symbol_table::create_edge): Or in calls_declare_variant_alt
316 * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member.
317 (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in
318 entry block if info->after_stmt is NULL, otherwise add after that stmt
319 and update it after adding each stmt.
320 (ipa_simd_modify_function_body): Initialize info.after_stmt.
322 * function.h (struct function): Add has_omp_target bit.
323 * omp-offload.c (omp_discover_declare_target_fn_r): New function,
325 (omp_discover_declare_target_tgt_fn_r): ... this.
326 (omp_discover_declare_target_var_r): Call
327 omp_discover_declare_target_tgt_fn_r instead of
328 omp_discover_declare_target_fn_r.
329 (omp_discover_implicit_declare_target): Also queue functions with
330 has_omp_target bit set, for those walk with
331 omp_discover_declare_target_fn_r, for declare target to functions
332 walk with omp_discover_declare_target_tgt_fn_r.
334 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
337 * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): Rename from mmx_pf2id.
338 Add SSE/AVX alternative. Change operand predicates from
339 nonimmediate_operand to register_mmxmem_operand.
340 Enable instruction pattern for TARGET_MMX_WITH_SSE.
341 (fix_truncv2sfv2si2): New expander.
342 (fixuns_truncv2sfv2si2): New insn pattern.
344 (mmx_floatv2siv2sf2): rename from mmx_floatv2si2.
345 Add SSE/AVX alternative. Change operand predicates from
346 nonimmediate_operand to register_mmxmem_operand.
347 Enable instruction pattern for TARGET_MMX_WITH_SSE.
348 (floatv2siv2sf2): New expander.
349 (floatunsv2siv2sf2): New insn pattern.
351 * config/i386/i386-builtin.def (IX86_BUILTIN_PF2ID):
353 (IX86_BUILTIN_PI2FD): Ditto.
355 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
357 * config/s390/s390.c (s390_emit_stack_probe): Call the probe_stack
359 * config/s390/s390.md ("@probe_stack2<mode>", "probe_stack"): New
362 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
364 * config/s390/s390.c (allocate_stack_space): Add missing updates
365 of last_probe_offset.
367 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
369 * config/s390/s390.md ("allocate_stack"): Call
370 anti_adjust_stack_and_probe_stack_clash when stack clash
371 protection is enabled.
372 * explow.c (anti_adjust_stack_and_probe_stack_clash): Remove
373 prototype. Remove static.
374 * explow.h (anti_adjust_stack_and_probe_stack_clash): Add
377 2020-05-13 Kelvin Nilsen <kelvin@gcc.gnu.org>
379 * config/rs6000/altivec.h (vec_extractl): New #define.
380 (vec_extracth): Likewise.
381 * config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant.
382 (UNSPEC_EXTRACTR): Likewise.
383 (vextractl<mode>): New expansion.
384 (vextractl<mode>_internal): New insn.
385 (vextractr<mode>): New expansion.
386 (vextractr<mode>_internal): New insn.
387 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vextdubvlx):
388 New built-in function.
389 (__builtin_altivec_vextduhvlx): Likewise.
390 (__builtin_altivec_vextduwvlx): Likewise.
391 (__builtin_altivec_vextddvlx): Likewise.
392 (__builtin_altivec_vextdubvhx): Likewise.
393 (__builtin_altivec_vextduhvhx): Likewise.
394 (__builtin_altivec_vextduwvhx): Likewise.
395 (__builtin_altivec_vextddvhx): Likewise.
396 (__builtin_vec_extractl): New overloaded built-in function.
397 (__builtin_vec_extracth): Likewise.
398 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
399 Define overloaded forms of __builtin_vec_extractl and
400 __builtin_vec_extracth.
401 (builtin_function_type): Add cases to mark arguments of new
402 built-in functions as unsigned.
403 (rs6000_common_init_builtins): Add
404 opaque_ftype_opaque_opaque_opaque_opaque.
405 * config/rs6000/rs6000.md (du_or_d): New mode attribute.
406 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
407 for a Future Architecture): Add description of vec_extractl and
408 vec_extractr built-in functions.
410 2020-05-13 Richard Biener <rguenther@suse.de>
412 * target.def (add_stmt_cost): Add new vectype parameter.
413 * targhooks.c (default_add_stmt_cost): Adjust.
414 * targhooks.h (default_add_stmt_cost): Likewise.
415 * config/aarch64/aarch64.c (aarch64_add_stmt_cost): Take new
417 * config/arm/arm.c (arm_add_stmt_cost): Likewise.
418 * config/i386/i386.c (ix86_add_stmt_cost): Likewise.
419 * config/rs6000/rs6000.c (rs6000_add_stmt_cost): Likewise.
421 * tree-vectorizer.h (stmt_info_for_cost::vectype): Add.
422 (dump_stmt_cost): Add new vectype parameter.
423 (add_stmt_cost): Likewise.
424 (record_stmt_cost): Likewise.
425 (record_stmt_cost): Add overload with old signature.
426 * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost):
428 (vect_get_known_peeling_cost): Likewise.
429 (vect_estimate_min_profitable_iters): Likewise.
430 * tree-vectorizer.c (dump_stmt_cost): Add new vectype parameter.
431 * tree-vect-stmts.c (record_stmt_cost): Likewise.
432 (vect_prologue_cost_for_slp_op): Remove stmt_vec_info parameter
433 and pass down correct vectype and NULL stmt_info.
434 (vect_model_simple_cost): Adjust.
435 (vect_model_store_cost): Likewise.
437 2020-05-13 Richard Biener <rguenther@suse.de>
439 * tree-vectorizer.h (SLP_INSTANCE_GROUP_SIZE): Remove.
440 (_slp_instance::group_size): Likewise.
441 * tree-vect-loop.c (vectorizable_reduction): The group size
442 is the number of lanes in the node.
443 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Likewise.
444 (vect_analyze_slp_instance): Do not set SLP_INSTANCE_GROUP_SIZE,
445 verify it matches the instance trees number of lanes.
446 (vect_slp_analyze_node_operations_1): Use the numer of lanes
447 in the node as group size.
448 (vect_bb_vectorization_profitable_p): Use the instance root
449 number of lanes for the size of life.
450 (vect_schedule_slp_instance): Use the number of lanes as
452 * tree-vect-stmts.c (vectorizable_load): Remove SLP instance
453 parameter. Use the number of lanes of the load for the group
454 size in the gap adjustment code.
455 (vect_analyze_stmt): Adjust.
456 (vect_transform_stmt): Likewise.
458 2020-05-13 Jakub Jelinek <jakub@redhat.com>
461 * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even
462 if the last insn is a note.
464 PR tree-optimization/95060
465 * tree-ssa-math-opts.c (convert_mult_to_fma_1): Fold a NEGATE_EXPR
466 if it is the single use of the FMA internal builtin.
468 2020-05-13 Bin Cheng <bin.cheng@linux.alibaba.com>
470 PR tree-optimization/94969
471 * tree-data-dependence.c (constant_access_functions): Rename to...
472 (invariant_access_functions): ...this. Add parameter. Check for
473 invariant access function, rather than constant.
474 (build_classic_dist_vector): Call above function.
475 * tree-loop-distribution.c (pg_add_dependence_edges): Add comment.
477 2020-05-13 Hongtao Liu <hongtao.liu@intel.com>
480 * doc/extend.texi (x86Operandmodifiers): Document more x86
482 * gcc/config/i386/i386.c: Add comment for operand modifier N and I.
484 2020-05-12 Giuliano Belinassi <giuliano.belinassi@usp.br>
486 * tree-vrp.c (class vrp_insert): New.
487 (insert_range_assertions): Move to class vrp_insert.
488 (dump_all_asserts): Same as above.
489 (dump_asserts_for): Same as above.
490 (live): Same as above.
491 (need_assert_for): Same as above.
492 (live_on_edge): Same as above.
493 (finish_register_edge_assert_for): Same as above.
494 (find_switch_asserts): Same as above.
495 (find_assert_locations): Same as above.
496 (find_assert_locations_1): Same as above.
497 (find_conditional_asserts): Same as above.
498 (process_assert_insertions): Same as above.
499 (register_new_assert_for): Same as above.
500 (vrp_prop): New variable fun.
501 (vrp_initialize): New parameter.
502 (identify_jump_threads): Same as above.
503 (execute_vrp): Same as above.
506 2020-05-12 Keith Packard <keith.packard@sifive.com>
508 * config/riscv/riscv.c (riscv_unique_section): New.
509 (TARGET_ASM_UNIQUE_SECTION): New.
511 2020-05-12 Craig Blackmore <craig.blackmore@embecosm.com>
513 * config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv.
514 * config/riscv/riscv-passes.def: New file.
515 * config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare.
516 * config/riscv/riscv-shorten-memrefs.c: New file.
517 * config/riscv/riscv.c (tree-pass.h): New include.
518 (riscv_compressed_reg_p): New Function
519 (riscv_compressed_lw_offset_p): Likewise.
520 (riscv_compressed_lw_address_p): Likewise.
521 (riscv_shorten_lw_offset): Likewise.
522 (riscv_legitimize_address): Attempt to convert base + large_offset
523 to compressible new_base + small_offset.
524 (riscv_address_cost): Make anticipated compressed load/stores
525 cheaper for code size than uncompressed load/stores.
526 (riscv_register_priority): Move compressed register check to
527 riscv_compressed_reg_p.
528 * config/riscv/riscv.h (C_S_BITS): Define.
529 (CSW_MAX_OFFSET): Define.
530 * config/riscv/riscv.opt (mshorten-memefs): New option.
531 * config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule.
532 (PASSES_EXTRA): Add riscv-passes.def.
533 * doc/invoke.texi: Document -mshorten-memrefs.
535 * config/riscv/riscv.c (riscv_new_address_profitable_p): New function.
536 (TARGET_NEW_ADDRESS_PROFITABLE_P): Define.
537 * doc/tm.texi: Regenerate.
538 * doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P): New hook.
539 * sched-deps.c (attempt_change): Use old address if it is cheaper than
541 * target.def (new_address_profitable_p): New hook.
542 * targhooks.c (default_new_address_profitable_p): New function.
543 * targhooks.h (default_new_address_profitable_p): Declare.
545 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
548 * config/i386/mmx.md (copysignv2sf3): New expander.
549 (xorsignv2sf3): Ditto.
550 (signbitv2sf3): Ditto.
552 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
555 * config/i386/mmx.md (fmav2sf4): New insn pattern.
560 2020-05-12 H.J. Lu <hongjiu.lu@intel.com>
562 * Makefile.in (CET_HOST_FLAGS): New.
563 (COMPILER): Add $(CET_HOST_FLAGS).
564 * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and
565 AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't
567 * aclocal.m4: Regenerated.
568 * configure: Likewise.
570 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
573 * config/i386/mmx.md (<code>v2sf2): New insn pattern.
574 (*mmx_<code>v2sf2): New insn_and_split pattern.
575 (*mmx_nabsv2sf2): Ditto.
576 (*mmx_andnotv2sf3): New insn pattern.
577 (*mmx_<code>v2sf3): Ditto.
578 * config/i386/i386.md (absneg_op): New code attribute.
579 * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
580 (ix86_build_signbit_mask): Ditto.
582 2020-05-12 Richard Biener <rguenther@suse.de>
584 * tree-ssa-live.c (remove_unused_locals): Remove dead debug
587 2020-05-12 Jozef Lawrynowicz <jozef.l@mittosystems.com>
589 * config/msp430/msp430-protos.h (msp430_output_aligned_decl_common):
590 Update prototype to include "local" argument.
591 * config/msp430/msp430.c (msp430_output_aligned_decl_common): Add
592 "local" argument. Handle local common decls.
593 * config/msp430/msp430.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Adjust
594 msp430_output_aligned_decl_common call with 0 for "local" argument.
595 (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Define.
597 2020-05-12 Richard Biener <rguenther@suse.de>
599 * cfghooks.c (split_edge): Preserve EDGE_DFS_BACK if set.
601 2020-05-12 Martin Liska <mliska@suse.cz>
605 * sanopt.c (sanitize_rewrite_addressable_params):
606 Clear DECL_NOT_GIMPLE_REG_P for argument.
608 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
610 PR tree-optimization/94980
611 * tree-vect-generic.c (expand_vector_comparison): Use
612 vector_element_bits_tree to get the element size in bits,
613 rather than using TYPE_SIZE.
614 (expand_vector_condition, vector_element): Likewise.
616 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
618 PR tree-optimization/94980
619 * tree-vect-generic.c (build_replicated_const): Take the number
620 of bits as a parameter, instead of the type of the elements.
621 (do_plus_minus): Update accordingly, using vector_element_bits
622 to calculate the correct number of bits.
623 (do_negate): Likewise.
625 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
627 PR tree-optimization/94980
628 * tree.h (vector_element_bits, vector_element_bits_tree): Declare.
629 * tree.c (vector_element_bits, vector_element_bits_tree): New.
630 * match.pd: Use the new functions instead of determining the
631 vector element size directly from TYPE_SIZE(_UNIT).
632 * tree-vect-data-refs.c (vect_gather_scatter_fn_p): Likewise.
633 * tree-vect-patterns.c (vect_recog_mask_conversion_pattern): Likewise.
634 * tree-vect-stmts.c (vect_is_simple_cond): Likewise.
635 * tree-vect-generic.c (expand_vector_piecewise): Likewise.
636 (expand_vector_conversion): Likewise.
637 (expand_vector_addition): Likewise for a TYPE_SIZE_UNIT used as
638 a divisor. Convert the dividend to bits to compensate.
639 * tree-vect-loop.c (vectorizable_live_operation): Call
640 vector_element_bits instead of open-coding it.
642 2020-05-12 Jakub Jelinek <jakub@redhat.com>
644 * omp-offload.h (omp_discover_implicit_declare_target): Declare.
645 * omp-offload.c: Include context.h.
646 (omp_declare_target_fn_p, omp_declare_target_var_p,
647 omp_discover_declare_target_fn_r, omp_discover_declare_target_var_r,
648 omp_discover_implicit_declare_target): New functions.
649 * cgraphunit.c (analyze_functions): Call
650 omp_discover_implicit_declare_target.
652 2020-05-12 Richard Biener <rguenther@suse.de>
654 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Canonicalize
655 literal constant &MEM[..] to a constant literal.
657 2020-05-12 Richard Biener <rguenther@suse.de>
659 PR tree-optimization/95045
660 * dbgcnt.def (lim): Add debug-counter.
661 * tree-ssa-loop-im.c: Include dbgcnt.h.
662 (find_refs_for_sm): Use lim debug counter for store motion
664 (do_store_motion): Rename form store_motion. Commit edge
666 (store_motion_loop): ... here.
667 (tree_ssa_lim): Adjust.
669 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
671 * config/rs6000/altivec.h (vec_clzm): Rename to vec_cntlzm.
672 (vec_ctzm): Rename to vec_cnttzm.
673 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
674 Change fourth operand for vec_ternarylogic to require
675 compatibility with unsigned SImode rather than unsigned QImode.
676 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
677 Remove overloaded forms of vec_gnb that are no longer needed.
678 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
679 for a Future Architecture): Replace vec_clzm with vec_cntlzm;
680 replace vec_ctzm with vec_cntlzm; remove four unwanted forms of
681 vec_gnb; move vec_ternarylogic documentation into this section
682 and replace const unsigned char with const unsigned int as its
685 2020-05-11 Carl Love <cel@us.ibm.com>
687 * config/rs6000/altivec.h (vec_genpcvm): New #define.
688 * config/rs6000/rs6000-builtin.def (XXGENPCVM_V16QI): New built-in
690 (XXGENPCVM_V8HI): Likewise.
691 (XXGENPCVM_V4SI): Likewise.
692 (XXGENPCVM_V2DI): Likewise.
693 (XXGENPCVM): New overloaded built-in instantiation.
694 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add
695 entries for FUTURE_BUILTIN_VEC_XXGENPCVM.
696 (altivec_expand_builtin): Add special handling for
697 FUTURE_BUILTIN_VEC_XXGENPCVM.
698 (builtin_function_type): Add handling for
699 FUTURE_BUILTIN_XXGENPCVM_{V16QI,V8HI,V4SI,V2DI}.
700 * config/rs6000/vsx.md (VSX_EXTRACT_I4): New mode iterator.
701 (UNSPEC_XXGENPCV): New constant.
702 (xxgenpcvm_<mode>_internal): New insn.
703 (xxgenpcvm_<mode>): New expansion.
704 * doc/extend.texi: Add documentation for vec_genpcvm built-ins.
706 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
708 * config/rs6000/altivec.h (vec_strir): New #define.
709 (vec_stril): Likewise.
710 (vec_strir_p): Likewise.
711 (vec_stril_p): Likewise.
712 * config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
713 (UNSPEC_VSTRIL): Likewise.
714 (vstrir_<mode>): New expansion.
715 (vstrir_code_<mode>): New insn.
716 (vstrir_p_<mode>): New expansion.
717 (vstrir_p_code_<mode>): New insn.
718 (vstril_<mode>): New expansion.
719 (vstril_code_<mode>): New insn.
720 (vstril_p_<mode>): New expansion.
721 (vstril_p_code_<mode>): New insn.
722 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
723 New built-in function.
724 (__builtin_altivec_vstrihr): Likewise.
725 (__builtin_altivec_vstribl): Likewise.
726 (__builtin_altivec_vstrihl): Likewise.
727 (__builtin_altivec_vstribr_p): Likewise.
728 (__builtin_altivec_vstrihr_p): Likewise.
729 (__builtin_altivec_vstribl_p): Likewise.
730 (__builtin_altivec_vstrihl_p): Likewise.
731 (__builtin_vec_strir): New overloaded built-in function.
732 (__builtin_vec_stril): Likewise.
733 (__builtin_vec_strir_p): Likewise.
734 (__builtin_vec_stril_p): Likewise.
735 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
736 Define overloaded forms of __builtin_vec_strir,
737 __builtin_vec_stril, __builtin_vec_strir_p, and
738 __builtin_vec_stril_p.
739 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
740 for a Future Architecture): Add description of vec_stril,
741 vec_stril_p, vec_strir, and vec_strir_p built-in functions.
743 2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
745 * config/rs6000/altivec.h (vec_ternarylogic): New #define.
746 * config/rs6000/altivec.md (UNSPEC_XXEVAL): New constant.
748 * config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
749 * config/rs6000/rs6000-builtin.def: Add handling of new macro
751 (BU_FUTURE_V_4): New macro. Use it.
752 (BU_FUTURE_OVERLOAD_4): Likewise.
753 * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Add
754 handling for quaternary built-in functions.
755 (altivec_resolve_overloaded_builtin): Add special-case handling
756 for __builtin_vec_xxeval.
757 * config/rs6000/rs6000-call.c: Add handling of new macro
758 RS6000_BUILTIN_4 in initialization of rs6000_builtin_info,
759 bdesc0_arg, bdesc1_arg, bdesc2_arg, bdesc_3arg,
760 bdesc_altivec_preds, bdesc_abs, and bdesc_htm arrays.
761 (altivec_overloaded_builtins): Add definitions for
762 FUTURE_BUILTIN_VEC_XXEVAL.
763 (bdesc_4arg): New array.
764 (htm_expand_builtin): Add handling for quaternary built-in
766 (rs6000_expand_quaternop_builtin): New function.
767 (rs6000_expand_builtin): Add handling for quaternary built-in
769 (rs6000_init_builtins): Initialize builtin_mode_to_type entries
770 for unsigned QImode and unsigned HImode.
771 (builtin_quaternary_function_type): New function.
772 (rs6000_common_init_builtins): Add handling of quaternary
774 * config/rs6000/rs6000.h (RS6000_BTC_QUATERNARY): New defined
776 (RS6000_BTC_PREDICATE): Change value of constant.
777 (RS6000_BTC_ABS): Likewise.
778 (rs6000_builtins): Add support for new macro RS6000_BUILTIN_4.
779 * doc/extend.texi (PowerPC AltiVec Built-In Functions Available
780 for a Future Architecture): Add description of vec_ternarylogic
783 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
785 * config/rs6000/rs6000-builtin.def (__builtin_pdepd): New built-in
787 (__builtin_pextd): Likewise.
788 * config/rs6000/rs6000.md (UNSPEC_PDEPD): New constant.
789 (UNSPEC_PEXTD): Likewise.
792 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
793 a Future Architecture): Add descriptions of __builtin_pdepd and
794 __builtin_pextd functions.
796 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
798 * config/rs6000/altivec.h (vec_clrl): New #define.
799 (vec_clrr): Likewise.
800 * config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
801 (UNSPEC_VCLRRB): Likewise.
804 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
806 (__builtin_altivec_vclrrb): Likewise.
807 (__builtin_vec_clrl): New overloaded built-in function.
808 (__builtin_vec_clrr): Likewise.
809 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
810 Define overloaded forms of __builtin_vec_clrl and
812 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
813 for a Future Architecture): Add descriptions of vec_clrl and
816 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
818 * config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
819 built-in function definition.
820 (__builtin_cnttzdm): Likewise.
821 * config/rs6000/rs6000.md (UNSPEC_CNTLZDM): New constant.
822 (UNSPEC_CNTTZDM): Likewise.
825 * doc/extend.texi (Basic PowerPC Built-in Functions available for
826 a Future Architecture): Add descriptions of __builtin_cntlzdm and
827 __builtin_cnttzdm functions.
829 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
832 * config/i386/mmx.md (sqrtv2sf2): New insn pattern.
834 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
836 * config/rs6000/altivec.h (vec_cfuge): New #define.
837 * config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant.
839 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged):
840 New built-in function.
841 * config/rs6000/rs6000-call.c (builtin_function_type): Add
842 handling for FUTURE_BUILTIN_VCFUGED case.
843 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
844 for a Future Architecture): Add description of vec_cfuge built-in
847 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
849 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New
851 (BU_FUTURE_MISC_1): Likewise.
852 (BU_FUTURE_MISC_2): Likewise.
853 (BU_FUTURE_MISC_3): Likewise.
854 (__builtin_cfuged): New built-in function definition.
855 * config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant.
857 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
858 a Future Architecture): New subsubsection.
860 2020-05-11 Richard Biener <rguenther@suse.de>
862 PR tree-optimization/95049
863 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition
864 between different constants.
866 2020-05-11 Richard Sandiford <richard.sandiford@arm.com>
868 * tree-pretty-print.c (dump_generic_node): Handle BOOLEAN_TYPEs.
870 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
871 Bill Schmidt <wschmidt@linux.ibm.com>
873 * config/rs6000/altivec.h (vec_gnb): New #define.
874 * config/rs6000/altivec.md (UNSPEC_VGNB): New constant.
876 * config/rs6000/rs6000-builtin.def (BU_FUTURE_OVERLOAD_1): New
878 (BU_FUTURE_OVERLOAD_2): Likewise.
879 (BU_FUTURE_OVERLOAD_3): Likewise.
880 (__builtin_altivec_gnb): New built-in function.
881 (__buiiltin_vec_gnb): New overloaded built-in function.
882 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
883 Define overloaded forms of __builtin_vec_gnb.
884 (rs6000_expand_binop_builtin): Add error checking for 2nd argument
885 of __builtin_vec_gnb.
886 (builtin_function_type): Mark return value and arguments unsigned
887 for FUTURE_BUILTIN_VGNB.
888 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
889 for a Future Architecture): Add description of vec_gnb built-in
892 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
893 Bill Schmidt <wschmidt@linux.ibm.com>
895 * config/rs6000/altivec.h (vec_pdep): New macro implementing new
897 (vec_pext): Likewise.
898 * config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant.
899 (UNSPEC_VPEXTD): Likewise.
902 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vpdepd): New
904 (__builtin_altivec_vpextd): Likewise.
905 * config/rs6000/rs6000-call.c (builtin_function_type): Add
906 handling for FUTURE_BUILTIN_VPDEPD and FUTURE_BUILTIN_VPEXTD
908 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
909 for a Future Architecture): Add description of vec_pdep and
910 vec_pext built-in functions.
912 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
913 Bill Schmidt <wschmidt@linux.ibm.com>
915 * config/rs6000/altivec.h (vec_clzm): New macro.
916 (vec_ctzm): Likewise.
917 * config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant.
918 (UNSPEC_VCTZDM): Likewise.
921 * config/rs6000/rs6000-builtin.def (BU_FUTURE_V_0): New macro.
922 (BU_FUTURE_V_1): Likewise.
923 (BU_FUTURE_V_2): Likewise.
924 (BU_FUTURE_V_3): Likewise.
925 (__builtin_altivec_vclzdm): New builtin definition.
926 (__builtin_altivec_vctzdm): Likewise.
927 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Cause
928 _ARCH_PWR_FUTURE macro to be defined if OPTION_MASK_FUTURE flag is
930 * config/rs6000/rs6000-call.c (builtin_function_type): Set return
931 value and parameter types to be unsigned for VCLZDM and VCTZDM.
932 * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
933 support for TARGET_FUTURE flag.
934 * config/rs6000/rs6000.h (RS6000_BTM_FUTURE): New macro constant.
935 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
936 for a Future Architecture): New subsubsection.
938 2020-05-11 Richard Biener <rguenther@suse.de>
940 PR tree-optimization/94988
941 PR tree-optimization/95025
942 * tree-ssa-loop-im.c (seq_entry): Make a struct, add from.
943 (sm_seq_push_down): Take extra parameter denoting where we
945 (execute_sm_exit): Re-issue sm_other stores in the correct
947 (sm_seq_valid_bb): When always executed, allow sm_other to
948 prevail inbetween sm_ord and record their stored value.
949 (hoist_memory_references): Adjust refs_not_supported propagation
950 and prune sm_other from the end of the ordered sequences.
952 2020-05-11 Felix Yang <felix.yang@huawei.com>
955 * config/aarch64/aarch64.md (mov<mode>):
956 Bitcasts to the equivalent integer mode using gen_lowpart
957 instead of doing FAIL for scalar floating point move.
959 2020-05-11 Alex Coplan <alex.coplan@arm.com>
961 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case
962 to correctly calculate cost for new pattern (*csinv3_uxtw_insn3).
963 * config/aarch64/aarch64.md (*csinv3_utxw_insn1): New.
964 (*csinv3_uxtw_insn2): New.
965 (*csinv3_uxtw_insn3): New.
966 * config/aarch64/iterators.md (neg_not_cs): New.
968 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
971 * config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint
972 instead of "Yv" for AVX alternatives. Add "prefix" attribute.
973 (*mmx_addv2sf3): Ditto.
974 (*mmx_subv2sf3): Ditto.
975 (*mmx_mulv2sf3): Ditto.
976 (*mmx_<code>v2sf3): Ditto.
977 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
979 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
982 * config/i386/i386.c (ix86_vector_mode_supported_p):
983 Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
984 * config/i386/mmx.md (*mov<mode>_internal): Do not set
985 mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.
987 (mmx_addv2sf3): Change operand predicates from
988 nonimmediate_operand to register_mmxmem_operand.
989 (addv2sf3): New expander.
990 (*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand
991 predicates from nonimmediate_operand to register_mmxmem_operand.
992 Enable instruction pattern for TARGET_MMX_WITH_SSE.
994 (mmx_subv2sf3): Change operand predicate from
995 nonimmediate_operand to register_mmxmem_operand.
996 (mmx_subrv2sf3): Ditto.
997 (subv2sf3): New expander.
998 (*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand
999 predicates from nonimmediate_operand to register_mmxmem_operand.
1000 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1002 (mmx_mulv2sf3): Change operand predicates from
1003 nonimmediate_operand to register_mmxmem_operand.
1004 (mulv2sf3): New expander.
1005 (*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand
1006 predicates from nonimmediate_operand to register_mmxmem_operand.
1007 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1009 (mmx_<code>v2sf3): Change operand predicates from
1010 nonimmediate_operand to register_mmxmem_operand.
1011 (<code>v2sf3): New expander.
1012 (*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand
1013 predicates from nonimmediate_operand to register_mmxmem_operand.
1014 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1015 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
1017 2020-05-11 Martin Liska <mliska@suse.cz>
1020 * common.opt: Fix typo in option description.
1022 2020-05-11 Martin Liska <mliska@suse.cz>
1024 PR gcov-profile/94928
1025 * gcov-io.h: Add caveat about coverage format parsing and
1026 possible outdated documentation.
1028 2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com>
1030 PR tree-optimization/83403
1031 * tree-affine.c (expr_to_aff_combination): Replace SSA_NAME with
1032 determine_value_range, Add fold conversion of MULT_EXPR, fix the
1035 2020-05-10 Gerald Pfeifer <gerald@pfeifer.com>
1037 * config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and
1038 __ILP32__ for 32-bit targets.
1040 2020-05-09 Eric Botcazou <ebotcazou@adacore.com>
1042 * tree.h (expr_align): Delete.
1043 * tree.c (expr_align): Likewise.
1045 2020-05-09 Hans-Peter Nilsson <hp@axis.com>
1047 * resource.c (init_resource_info): Filter-out TARGET_FLAGS_REGNUM
1048 from end_of_function_needs.
1050 * config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
1051 * config/cris/t-linux, config/cris/linux.h, config/cris/linux.opt:
1053 * config/cris/t-elfmulti: Remove crisv32 multilib.
1054 * config/cris: Remove shared-library and CRIS v32 support.
1056 Move trivially from cc0 to reg:CC model, removing most optimizations.
1057 * config/cris/cris.md: Remove all side-effect patterns and their
1058 splitters. Remove most peepholes. Add clobbers of CRIS_CC0_REGNUM
1059 to all but post-reload control-flow and movem insns. Remove
1060 constraints on all modified expanders. Remove obsoleted cc0-related
1062 (attr "cc"): Remove alternative "rev".
1063 (mode_iterator BWDD, DI_, SI_): New.
1064 (mode_attr sCC_destc, cmp_op1c, cmp_op2c): New.
1065 ("tst<mode>"): Remove; fold as "M" alternative into compare insn.
1066 ("mstep_shift", "mstep_mul"): Remove patterns.
1067 ("s<rcond>", "s<ocond>", "s<ncond>"): Anonymize.
1068 * config/cris/cris.c: Change all non-condition-code,
1069 non-control-flow emitted insns to add a parallel with clobber of
1070 CRIS_CC0_REGNUM, mostly by changing from gen_rtx_SET with
1071 emit_insn to use of emit_move_insn, gen_add2_insn or
1072 cris_emit_insn, as convenient.
1073 (cris_reg_overlap_mentioned_p)
1074 (cris_normal_notice_update_cc, cris_notice_update_cc): Remove.
1075 (cris_movem_load_rest_p): Don't assume all elements in a
1077 (cris_store_multiple_op_p): Ditto.
1078 (cris_emit_insn): New function.
1079 * cris/cris-protos.h (cris_emit_insn): Declare.
1082 * config/cris/cris.md (zcond): New code_iterator.
1083 ("*cbranch<mode>4_btstq<CC>"): New insn_and_split.
1085 * config/cris/cris.c (TARGET_FLAGS_REGNUM): Define.
1087 * config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.
1089 * config/cris/cris.md ("movsi"): For memory destination
1090 post-reload, generate clobberless variant. Similarly for a
1091 zero-source post-reload.
1092 ("*mov_tomem<mode>_split"): New split.
1093 ("*mov_tomem<mode>"): New insn.
1094 ("enabled", mov_tomem_enabled): Define and use to exclude "x" ->
1095 "Q>m" for less-than-SImode.
1096 ("*mov_fromzero<mode>_split"): New split.
1097 ("*mov_fromzero<mode>"): New insn.
1099 Prepare for cmpelim pass to eliminate redundant compare insns.
1100 * config/cris/cris-modes.def: New file.
1101 * config/cris/cris-protos.h (cris_select_cc_mode): Declare.
1102 (cris_notice_update_cc): Remove left-over declaration.
1103 * config/cris/cris.c (TARGET_CC_MODES_COMPATIBLE): Define.
1104 (cris_select_cc_mode, cris_cc_modes_compatible): New functions.
1105 * config/cris/cris.h (SELECT_CC_MODE): Define.
1106 * config/cris/cris.md (NZSET, NZUSE, NZVCSET, NZVCUSE): New
1108 (cond): New code_iterator.
1109 (nzcond): Replacement for incorrect ncond. All callers changed.
1110 (nzvccond): Replacement for ocond. All callers changed.
1111 (rnzcond): Replacement for rcond. All callers changed.
1112 (xCC): New code_attr.
1113 (cmp_op1c, cmp_op0c): Renumber from cmp_op1c and cmp_op2c. All
1115 ("*cmpdi<NZVCSET:mode>"): Rename from "*cmpdi". Replace
1116 CCmode with iteration over NZVCSET.
1117 ("*cmp_ext<BW:mode><NZVCSET:mode>"): Similarly; rename from
1119 ("*cmpsi<NZVCSET:mode>"): Similarly, from "*cmpsi".
1120 ("*cmp<BW:mode><NZVCSET:mode>"): Similarly from "*cmp<mode>".
1121 ("*btst<mode>"): Similarly, from "*btst".
1122 ("*cbranch<mode><code>4"): Rename from "*cbranch<mode>4",
1123 iterating over cond instead of matching the comparison with
1124 ordered_comparison_operator.
1125 ("*cbranch<mode>4_btstq<CC>"): Correct label operand number.
1126 ("b<zcond:code><mode>"): Rename from "b<ncond:code>", iterating
1128 ("b<nzvccond:code><mode>"): Similarly from "b<ocond:code>", over
1129 NZVCUSE. Remove FIXME.
1130 ("*b<nzcond:code>_reversed<mode>"): Similarly from
1131 "*b<ncond:code>_reversed", over NZUSE.
1132 ("*b<nzvccond:code>_reversed<mode>"): Similarly from
1133 "*b<ocond:code>_reversed", over NZVCUSE. Remove FIXME.
1134 ("b<rnzcond:code><mode>"): Similarly from "b<rcond:code>",
1135 over NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
1136 depending on CC_NZmode vs. CCmode. Remove FIXME.
1137 ("*b<rnzcond:code>_reversed<mode>"): Similarly from
1138 "*b<rcond:code>_reversed", over NZUSE.
1139 ("*cstore<mode><code>4"): Rename from "*cstore<mode>4",
1140 iterating over cond instead of matching the comparison with
1141 ordered_comparison_operator.
1142 ("*s<nzcond:code><mode>"): Rename from "*s<ncond:code>",
1143 iterating over NZUSE.
1144 ("*s<rnzcond:code><mode>"): Similar from "*s<rcond:code>", over
1145 NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
1146 depending on CC_NZmode vs. CCmode.
1147 ("*s<nzvccond:code><mode>"): Simlar from "*s<ocond:code>", over
1148 NZVCUSE. Remove FIXME.
1149 ("cc"): Comment on new use.
1150 ("cc_enabled"): New attribute.
1151 ("enabled"): Make default fall back to cc_enabled.
1152 ("setnz", "ccnz", "setnzvc", "ccnzvc", "setcc", "cccc"): New
1153 default_subst_attrs.
1154 ("setnz_subst", "setnzvc_subst", "setcc_subst"): New default_subst.
1155 ("*movsi_internal<setcc><setnz><setnzvc>"): Rename from
1156 "*movsi_internal". Correct contents of, and rename attribute
1157 "cc" to "cc<cccc><ccnz><ccnzvc>".
1158 ("anz", "anzvc", "acc"): New define_subst_attrs.
1159 ("<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>"): Rename from
1160 "movhi". Rename "cc" attribute to "cc<cccc><ccnz><ccnzvc>".
1161 ("<acc><anz><anzvc>movqi<setcc><setnz><setnzvc>"): Similar from
1162 "movqi". Correct contents of, and rename "cc" attribute to
1163 "cc<cccc><ccnz><ccnzvc>".
1164 ("*b<zcond:code><mode>"): Rename from "b<zcond:code><mode>".
1165 ("*b<nzvccond:code><mode>"): Rename from "b<nzvccond:code><mode>".
1166 ("*b<rnzcond:code><mode>"): Rename from "*b<rnzcond:code><mode>".
1167 ("<acc><anz><anzvc>extend<mode>si2<setcc><setnz><setnzvc>"):
1168 Rename from "extend<mode>si2".
1169 ("<acc><anz><anzvc>zero_extend<mode>si2<setcc><setnz><setnzvc>"):
1170 Similar, from "zero_extend<mode>si2".
1171 ("*adddi3<setnz>"): Rename from "*adddi3".
1172 ("*subdi3<setnz>"): Similarly from "*subdi3".
1173 ("*addsi3<setnz>"): Similarly from "*addsi3".
1174 ("*subsi3<setnz>"): Similarly from "*subsi3".
1175 ("*addhi3<setnz>"): Similarly from "*addhi3" and decorate the
1176 "cc" attribute to "cc<ccnz>".
1177 ("*addqi3<setnz>"): Similarly from "*addqi3".
1178 ("*sub<mode>3<setnz>"): Similarly from "*sub<mode>3".
1179 ("*expanded_andsi<setcc><setnz><setnzvc>"): Rename from
1181 ("*iorsi3<setcc><setnz><setnzvc>"): Similar from "*iorsi3".
1182 Decorate "cc" attribute to make "cc<cccc><ccnz><ccnzvc>".
1183 ("*iorhi3<setcc><setnz><setnzvc>"): Similar from "*iorhi3".
1184 ("*iorqi3<setcc><setnz><setnzvc>"): Similar from "*iorqi3".
1185 ("*expanded_andhi<setcc><setnz><setnzvc>"): Similar from
1186 "*expanded_andhi". Add quick cc-setting alternative for 0..31.
1187 ("*andqi3<setcc><setnz><setnzvc>"): Similar from "*andqi3".
1188 ("<acc><anz><anzvc>xorsi3<setcc><setnz><setnzvc>"): Rename
1190 ("<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"): Rename
1192 ("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename
1194 ("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename
1196 ("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename
1198 ("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".
1200 * config/cris/cris-modes.def (CC_ZnN): New CC_MODE.
1201 * config/cris/cris.c (cris_rtx_costs): Handle pre-split bit-test
1202 * config/cris/cris.md (ZnNNZSET, ZnNNZUSE): New mode_iterators.
1203 (znnCC, rznnCC): New code_attrs.
1204 ("*btst<mode>"): Iterator over ZnNNZSET instead of NZVCSET. Remove
1205 obseolete comment. Add belt-and-suspenders mode-test to condition.
1206 Add fixme regarding remaining matched-but-not-generated case.
1207 ("*cbranch<mode>4_btstrq1_<CC>"): New insn_and_split.
1208 ("*cbranch<mode>4_btstqb0_<CC>"): Rename from
1209 "*cbranch<mode>4_btstq<CC>". Split to CC_NZ instead of CC.
1210 ("*b<zcond:code><mode>"): Iterate over ZnNNZUSE instead of NZUSE.
1211 Handle output of CC_ZnNmode.
1212 ("*b<nzcond:code>_reversed<mode>"): Ditto.
1214 * config/cris/cris.c (cris_select_cc_mode): Return CC_NZmode for
1215 NEG too. Correct comment.
1216 * config/cris/cris.md ("<anz>neg<mode>2<setnz>"): Rename from
1219 2020-05-08 Vladimir Makarov <vmakarov@redhat.com>
1221 * ira-color.c (update_costs_from_allocno): Remove
1222 conflict_cost_update_p argument. Propagate costs only along
1223 threads. Always do conflict cost update. Add printing debugging
1225 (update_costs_from_copies): Add printing debugging info.
1226 (restore_costs_from_copies): Ditto.
1227 (assign_hard_reg): Improve debug info.
1228 (push_only_colorable): Ditto. Call update_costs_from_prefs.
1229 (color_allocnos): Remove update_costs_from_prefs.
1231 2020-05-08 Richard Biener <rguenther@suse.de>
1233 * tree-vectorizer.h (vec_info::slp_loads): New.
1234 (vect_optimize_slp): Declare.
1235 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Do
1236 nothing when there are no loads.
1237 (vect_gather_slp_loads): Gather loads into a vector.
1238 (vect_supported_load_permutation_p): Remove.
1239 (vect_analyze_slp_instance): Do not verify permutation
1241 (vect_analyze_slp): Optimize permutations of reductions
1242 after all SLP instances have been gathered and gather
1244 (vect_optimize_slp): New function split out from
1245 vect_supported_load_permutation_p. Elide some permutations.
1246 (vect_slp_analyze_bb_1): Call vect_optimize_slp.
1247 * tree-vect-loop.c (vect_analyze_loop_2): Likewise.
1248 * tree-vect-stmts.c (vectorizable_load): Check whether
1249 the load can be permuted. When generating code assert we can.
1251 2020-05-08 Richard Biener <rguenther@suse.de>
1253 * tree-ssa-sccvn.c (rpo_avail): Change type to
1254 eliminate_dom_walker *.
1255 (eliminate_with_rpo_vn): Adjust rpo_avail to make vn_valueize
1256 use the DOM walker availability.
1257 (vn_reference_fold_indirect): Use get_addr_base_and_unit_offset_1
1258 with vn_valueize as valueization callback.
1259 (vn_reference_maybe_forwprop_address): Likewise.
1260 * tree-dfa.c (get_addr_base_and_unit_offset_1): Also valueize
1261 array_ref_low_bound.
1263 2020-05-08 Jakub Jelinek <jakub@redhat.com>
1265 PR tree-optimization/94786
1266 * match.pd (A ^ ((A ^ B) & -(C cmp D)) -> (C cmp D) ? B : A): New
1270 * config/i386/i386.md (peephole2 after *add<mode>3_cc_overflow_1): New
1274 * tree.c (get_narrower): Reuse the op temporary instead of
1277 PR tree-optimization/94783
1278 * match.pd ((X + (X >> (prec - 1))) ^ (X >> (prec - 1)) to abs (X)):
1281 PR tree-optimization/94956
1282 * match.pd (FFS): Optimize __builtin_ffs* of non-zero argument into
1283 __builtin_ctz* + 1 if direct IFN_CTZ is supported.
1285 PR tree-optimization/94913
1286 * match.pd (A - B + -1 >= A to B >= A): New simplification.
1287 (A - B > A to A < B): Don't test TYPE_OVERFLOW_WRAPS which is always
1288 true for TYPE_UNSIGNED integral types.
1291 PR rtl-optimization/94516
1292 * rtl.h (remove_reg_equal_equiv_notes): Add a bool argument defaulted
1294 * rtlanal.c (remove_reg_equal_equiv_notes): Add no_rescan argument.
1295 Call df_notes_rescan if that argument is not true and returning true.
1296 * combine.c (adjust_for_new_dest): Pass true as second argument to
1297 remove_reg_equal_equiv_notes.
1298 * postreload.c (reload_combine_recognize_pattern): Don't call
1301 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1303 * config/rs6000/rs6000.md (*setnbc_<un>signed_<GPR:mode>): New
1305 (*setnbcr_<un>signed_<GPR:mode>): New define_insn.
1306 (*neg_eq_<mode>): Avoid for TARGET_FUTURE; add missing && 1.
1307 (*neg_ne_<mode>): Likewise.
1309 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1311 * config/rs6000/rs6000.md (setbc_<un>signed_<GPR:mode>): New
1313 (*setbcr_<un>signed_<GPR:mode>): Likewise.
1314 (cstore<mode>4): Use setbc[r] if available.
1315 (<code><GPR:mode><GPR2:mode>2_isel): Avoid for TARGET_FUTURE.
1316 (eq<mode>3): Use setbc for TARGET_FUTURE.
1317 (*eq<mode>3): Avoid for TARGET_FUTURE.
1318 (ne<mode>3): Replace :P with :GPR; use setbc for TARGET_FUTURE;
1319 else for non-Pmode, use gen_eq and gen_xor.
1320 (*ne<mode>3): Avoid for TARGET_FUTURE.
1321 (*eqsi3_ext<mode>): Avoid for TARGET_FUTURE; fix missing && 1.
1323 2020-05-07 Jeff Law <law@redhat.com>
1325 * config/h8300/h8300.md: Move expanders and patterns into
1326 files based on functionality.
1327 * config/h8300/addsub.md: New file.
1328 * config/h8300/bitfield.md: New file
1329 * config/h8300/combiner.md: New file
1330 * config/h8300/divmod.md: New file
1331 * config/h8300/extensions.md: New file
1332 * config/h8300/jumpcall.md: New file
1333 * config/h8300/logical.md: New file
1334 * config/h8300/movepush.md: New file
1335 * config/h8300/multiply.md: New file
1336 * config/h8300/other.md: New file
1337 * config/h8300/proepi.md: New file
1338 * config/h8300/shiftrotate.md: New file
1339 * config/h8300/testcompare.md: New file
1341 * config/h8300/h8300.md (adds/subs splitters): Merge into single
1343 (negation expanders and patterns): Simplify and combine using
1345 (one_cmpl expanders and patterns): Likewise.
1346 (tablejump, indirect_jump patterns ): Likewise.
1347 (shift and rotate expanders and patterns): Likewise.
1348 (absolute value expander and pattern): Drop expander, rename pattern
1350 (peephole2 patterns): Move into...
1351 * config/h8300/peepholes.md: New file.
1353 * config/h8300/constraints.md (L and N): Simplify now that we're not
1354 longer supporting the original H8/300 chip.
1355 * config/h8300/elf.h (LINK_SPEC): Likewise. Default to H8/300H.
1356 * config/h8300/h8300.c (shift_alg_qi): Drop H8/300 support.
1357 (shift_alg_hi, shift_alg_si): Similarly.
1358 (h8300_option_overrides): Similarly. Default to H8/300H. If
1359 compiling for H8/S, then turn off H8/300H. Do not update the
1360 shift_alg tables for H8/300 port.
1361 (h8300_emit_stack_adjustment): Remove support for H8/300. Simplify
1363 (push, split_adds_subs, h8300_rtx_costs): Likewise.
1364 (h8300_print_operand, compute_mov_length): Likewise.
1365 (output_plussi, compute_plussi_length): Likewise.
1366 (compute_plussi_cc, output_logical_op): Likewise.
1367 (compute_logical_op_length, compute_logical_op_cc): Likewise.
1368 (get_shift_alg, h8300_shift_needs_scratch): Likewise.
1369 (output_a_shift, compute_a_shift_length): Likewise.
1370 (output_a_rotate, compute_a_rotate_length): Likewise.
1371 (output_simode_bld, h8300_hard_regno_mode_ok): Likewise.
1372 (h8300_modes_tieable_p, h8300_return_in_memory): Likewise.
1373 * config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Likewise.
1374 (attr_cpu, TARGET_H8300): Remove.
1375 (TARGET_DEFAULT): Update.
1376 (UNITS_PER_WORD, PARM_BOUNDARY): Simplify where possible.
1377 (BIGGEST_ALIGNMENT, STACK_BOUNDARY): Likewise.
1378 (CONSTANT_ADDRESS_P, MOVE_MAX, Pmode): Likewise.
1379 (SIZE_TYPE, POINTER_SIZE, ASM_WORD_OP): Likewise.
1380 * config/h8300/h8300.md: Simplify patterns throughout.
1381 * config/h8300/t-h8300: Update multilib configuration.
1383 * config/h8300/h8300.h (LINK_SPEC): Remove.
1384 (USER_LABEL_PREFIX): Likewise.
1386 * config/h8300/h8300.c (h8300_asm_named_section): Remove.
1387 (h8300_option_override): Remove remnants of COFF support.
1389 2020-05-07 Alan Modra <amodra@gmail.com>
1391 * tree-ssa-reassoc.c (optimize_range_tests_to_bit_test): Replace
1392 set_rtx_cost with set_src_cost.
1393 * tree-switch-conversion.c (bit_test_cluster::emit): Likewise.
1395 2020-05-07 Kewen Lin <linkw@gcc.gnu.org>
1397 * tree-vect-stmts.c (vectorizable_load): Check alignment to avoid
1398 redundant half vector handlings for no peeling gaps.
1400 2020-05-07 Giuliano Belinassi <giuliano.belinassi@usp.br>
1402 * tree-ssa-operands.c (operands_scanner): New class.
1403 (operands_bitmap_obstack): Remove.
1404 (n_initialized): Remove.
1405 (build_uses): Move to operands_scanner class.
1406 (build_vuse): Same as above.
1407 (build_vdef): Same as above.
1408 (verify_ssa_operands): Same as above.
1409 (finalize_ssa_uses): Same as above.
1410 (cleanup_build_arrays): Same as above.
1411 (finalize_ssa_stmt_operands): Same as above.
1412 (start_ssa_stmt_operands): Same as above.
1413 (append_use): Same as above.
1414 (append_vdef): Same as above.
1415 (add_virtual_operand): Same as above.
1416 (add_stmt_operand): Same as above.
1417 (get_mem_ref_operands): Same as above.
1418 (get_tmr_operands): Same as above.
1419 (maybe_add_call_vops): Same as above.
1420 (get_asm_stmt_operands): Same as above.
1421 (get_expr_operands): Same as above.
1422 (parse_ssa_operands): Same as above.
1423 (finalize_ssa_defs): Same as above.
1424 (build_ssa_operands): Same as above, plus create a C-like wrapper.
1425 (update_stmt_operands): Create an instance of operands_scanner.
1427 2020-05-07 Richard Biener <rguenther@suse.de>
1430 * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use
1431 DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible.
1432 (refered_from_nonlocal_var): Likewise.
1433 (ipa_pta_execute): Likewise.
1435 2020-05-07 Erick Ochoa <erick.ochoa@theobroma-systems.com>
1437 * gcc/tree-ssa-struct-alias.c: Fix comments
1439 2020-05-07 Martin Liska <mliska@suse.cz>
1441 * doc/invoke.texi: Fix 2 optindex entries.
1443 2020-05-07 Richard Biener <rguenther@suse.de>
1446 * tree-core.h (tree_decl_common::gimple_reg_flag): Rename ...
1447 (tree_decl_common::not_gimple_reg_flag): ... to this.
1448 * tree.h (DECL_GIMPLE_REG_P): Rename ...
1449 (DECL_NOT_GIMPLE_REG_P): ... to this.
1450 * gimple-expr.c (copy_var_decl): Copy DECL_NOT_GIMPLE_REG_P.
1451 (create_tmp_reg): Simplify.
1452 (create_tmp_reg_fn): Likewise.
1453 (is_gimple_reg): Check DECL_NOT_GIMPLE_REG_P for all regs.
1454 * gimplify.c (create_tmp_from_val): Simplify.
1455 (gimplify_bind_expr): Likewise.
1456 (gimplify_compound_literal_expr): Likewise.
1457 (gimplify_function_tree): Likewise.
1458 (prepare_gimple_addressable): Set DECL_NOT_GIMPLE_REG_P.
1459 * asan.c (create_odr_indicator): Do not clear DECL_GIMPLE_REG_P.
1460 (asan_add_global): Copy it.
1461 * cgraphunit.c (cgraph_node::expand_thunk): Force args
1463 * function.c (gimplify_parameters): Copy
1464 DECL_NOT_GIMPLE_REG_P.
1465 * ipa-param-manipulation.c
1466 (ipa_param_body_adjustments::common_initialization): Simplify.
1467 (ipa_param_body_adjustments::reset_debug_stmts): Copy
1468 DECL_NOT_GIMPLE_REG_P.
1469 * omp-low.c (lower_omp_for_scan): Do not set DECL_GIMPLE_REG_P.
1470 * sanopt.c (sanitize_rewrite_addressable_params): Likewise.
1471 * tree-cfg.c (make_blocks_1): Simplify.
1472 (verify_address): Do not verify DECL_GIMPLE_REG_P setting.
1473 * tree-eh.c (lower_eh_constructs_2): Simplify.
1474 * tree-inline.c (declare_return_variable): Adjust and
1476 (copy_decl_to_var): Copy DECL_NOT_GIMPLE_REG_P.
1477 (copy_result_decl_to_var): Likewise.
1478 * tree-into-ssa.c (pass_build_ssa::execute): Adjust comment.
1479 * tree-nested.c (create_tmp_var_for): Simplify.
1480 * tree-parloops.c (separate_decls_in_region_name): Copy
1481 DECL_NOT_GIMPLE_REG_P.
1482 * tree-sra.c (create_access_replacement): Adjust and
1483 generalize partial def support.
1484 * tree-ssa-forwprop.c (pass_forwprop::execute): Set
1485 DECL_NOT_GIMPLE_REG_P on decls we introduce partial defs on.
1486 * tree-ssa.c (maybe_optimize_var): Handle clearing of
1487 TREE_ADDRESSABLE and setting/clearing DECL_NOT_GIMPLE_REG_P
1489 * lto-streamer-out.c (hash_tree): Hash DECL_NOT_GIMPLE_REG_P.
1490 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Stream
1491 DECL_NOT_GIMPLE_REG_P.
1492 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
1493 * cfgexpand.c (avoid_type_punning_on_regs): New.
1494 (discover_nonconstant_array_refs): Call
1495 avoid_type_punning_on_regs to avoid unsupported mode punning.
1497 2020-05-07 Alex Coplan <alex.coplan@arm.com>
1499 * config/arm/arm.c (arm_add_stmt_cost): Fix declaration, remove class
1502 2020-05-07 Richard Biener <rguenther@suse.de>
1504 PR tree-optimization/57359
1505 * tree-ssa-loop-im.c (im_mem_ref::indep_loop): Remove.
1506 (in_mem_ref::dep_loop): Repurpose.
1507 (LOOP_DEP_BIT): Remove.
1508 (enum dep_kind): New.
1509 (enum dep_state): Likewise.
1510 (record_loop_dependence): New function to populate the
1512 (query_loop_dependence): New function to query the dependence
1514 (memory_accesses::refs_in_loop): Rename to ...
1515 (memory_accesses::refs_loaded_in_loop): ... this and change to
1517 (outermost_indep_loop): Adjust.
1518 (mem_ref_alloc): Likewise.
1519 (gather_mem_refs_stmt): Likewise.
1520 (mem_refs_may_alias_p): Add tbaa_p parameter and pass it down.
1521 (struct sm_aux): New.
1522 (execute_sm): Split code generation on exits, record state
1524 (enum sm_kind): New.
1525 (execute_sm_exit): Exit code generation part.
1526 (sm_seq_push_down): Helper for sm_seq_valid_bb performing
1527 dependence checking on stores reached from exits.
1528 (sm_seq_valid_bb): New function gathering SM stores on exits.
1529 (hoist_memory_references): Re-implement.
1530 (refs_independent_p): Add tbaa_p parameter and pass it down.
1531 (record_dep_loop): Remove.
1532 (ref_indep_loop_p_1): Fold into ...
1533 (ref_indep_loop_p): ... this and generalize for three kinds
1534 of dependence queries.
1535 (can_sm_ref_p): Adjust according to hoist_memory_references
1537 (store_motion_loop): Don't do anything if the set of SM
1538 candidates is empty.
1539 (tree_ssa_lim_initialize): Adjust.
1540 (tree_ssa_lim_finalize): Likewise.
1542 2020-05-07 Eric Botcazou <ebotcazou@adacore.com>
1543 Pierre-Marie de Rodat <derodat@adacore.com>
1545 * dwarf2out.c (add_data_member_location_attribute): Take into account
1546 the variant part offset in the computation of the data bit offset.
1547 (add_bit_offset_attribute): Remove CTX parameter. Pass a new context
1548 in the call to field_byte_offset.
1549 (gen_field_die): Adjust call to add_bit_offset_attribute and remove
1550 confusing assertion.
1551 (analyze_variant_discr): Deal with boolean subtypes.
1553 2020-05-07 Martin Liska <mliska@suse.cz>
1555 * lto-wrapper.c: Split arguments of MAKE environment
1558 2020-05-07 Uroš Bizjak <ubizjak@gmail.com>
1560 * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use
1561 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
1562 fenv_var and new_fenv_var.
1564 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1567 * config/i386/subst.md (store_mask_constraint, store_mask_predicate):
1569 (avx512dq_vextract<shuffletype>64x2_1_maskm,
1570 avx512f_vextract<shuffletype>32x4_1_maskm,
1571 vec_extract_lo_<mode>_maskm, vec_extract_hi_<mode>_maskm): Remove.
1572 (<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>): Split
1574 (*avx512dq_vextract<shuffletype>64x2_1,
1575 avx512dq_vextract<shuffletype>64x2_1_mask): ... these new
1576 define_insns. Even in the masked variant allow memory output but in
1577 that case use 0 rather than 0C constraint on the source of masked-out
1579 (<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>): Split
1581 (*avx512f_vextract<shuffletype>32x4_1,
1582 avx512f_vextract<shuffletype>32x4_1_mask): ... these new define_insns.
1583 Even in the masked variant allow memory output but in that case use
1584 0 rather than 0C constraint on the source of masked-out elts.
1585 (vec_extract_lo_<mode><mask_name>): Split into ...
1586 (vec_extract_lo_<mode>, vec_extract_lo_<mode>_mask): ... these new
1587 define_insns. Even in the masked variant allow memory output but in
1588 that case use 0 rather than 0C constraint on the source of masked-out
1590 (vec_extract_hi_<mode><mask_name>): Split into ...
1591 (vec_extract_hi_<mode>, vec_extract_hi_<mode>_mask): ... these new
1592 define_insns. Even in the masked variant allow memory output but in
1593 that case use 0 rather than 0C constraint on the source of masked-out
1596 2020-05-06 qing zhao <qing.zhao@oracle.com>
1599 * common.opt: Add -flarge-source-files.
1600 * doc/invoke.texi: Document it.
1601 * toplev.c (process_options): set line_table->default_range_bits
1602 to 0 when flag_large_source_files is true.
1604 2020-05-06 Uroš Bizjak <ubizjak@gmail.com>
1607 * config/i386/predicates.md (add_comparison_operator): New predicate.
1608 * config/i386/i386.md (compare->add splitter): New splitters.
1610 2020-05-06 Richard Biener <rguenther@suse.de>
1612 * tree-vectorizer.h (vect_transform_slp_perm_load): Adjust.
1613 * tree-vect-data-refs.c (vect_slp_analyze_node_dependences):
1614 Remove slp_instance parameter, just iterate over all scalar stmts.
1615 (vect_slp_analyze_instance_dependence): Adjust and likewise.
1616 * tree-vect-slp.c (vect_bb_slp_scalar_cost): Remove unused BB
1618 (vect_schedule_slp): Just iterate over all scalar stmts.
1619 (vect_supported_load_permutation_p): Adjust.
1620 (vect_transform_slp_perm_load): Remove slp_instance parameter,
1621 instead use the number of lanes in the node as group size.
1622 * tree-vect-stmts.c (vect_model_load_cost): Get vectorization
1623 factor instead of slp_instance as parameter.
1624 (vectorizable_load): Adjust.
1626 2020-05-06 Andreas Schwab <schwab@suse.de>
1628 * config/aarch64/driver-aarch64.c: Include "aarch64-protos.h".
1629 (aarch64_get_extension_string_for_isa_flags): Don't declare.
1631 2020-05-06 Richard Biener <rguenther@suse.de>
1634 * cfgloopmanip.c (create_preheader): Require non-complex
1635 preheader edge for CP_SIMPLE_PREHEADERS.
1637 2020-05-06 Richard Biener <rguenther@suse.de>
1639 PR tree-optimization/94963
1640 * tree-ssa-loop-im.c (execute_sm_if_changed): Remove
1641 no-warning marking of the conditional store.
1642 (execute_sm): Instead mark the uninitialized state
1643 on loop entry to be not warned about.
1645 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1647 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET,
1648 OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros.
1649 * config.gcc: Add tsxldtrkintrin.h to extra_headers.
1650 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1652 * config/i386/i386-builtin.def: Add new builtins.
1653 * config/i386/i386-c.c (ix86_target_macros_internal): Define
1655 * config/i386/i386-options.c (ix86_target_string): Add
1657 (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk.
1658 * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P):
1660 * config/i386/i386.md (define_c_enum "unspec"): Add
1661 UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK.
1662 (TSXLDTRK): New define_int_iterator.
1663 ("<tsxldtrk>"): New define_insn.
1664 * config/i386/i386.opt: Add -mtsxldtrk.
1665 * config/i386/immintrin.h: Include tsxldtrkintrin.h.
1666 * config/i386/tsxldtrkintrin.h: New.
1667 * doc/invoke.texi: Document -mtsxldtrk.
1669 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1671 PR tree-optimization/94921
1672 * match.pd (~(~X - Y) -> X + Y, ~(~X + Y) -> X - Y): New
1675 2020-05-06 Richard Biener <rguenther@suse.de>
1677 PR tree-optimization/94965
1678 * tree-vect-stmts.c (vectorizable_load): Fix typo.
1680 2020-05-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1682 * doc/install.texi: Replace Sun with Solaris as appropriate.
1683 (Tools/packages necessary for building GCC, Perl version between
1684 5.6.1 and 5.6.24): Remove Solaris 8 reference.
1685 (Installing GCC: Binaries, Solaris 2 (SPARC, Intel)): Remove
1687 (Specific, i?86-*-solaris2*): Update version references for
1688 Solaris 11.3 and later. Remove gas 2.26 caveat.
1689 (Specific, *-*-solaris2*): Update version references for
1690 Solaris 11.3 and later. Remove boehm-gc reference.
1691 Document GMP, MPFR caveats on Solaris 11.3.
1692 (Specific, sparc-sun-solaris2*): Update Solaris 9 references.
1693 (Specific, sparc64-*-solaris2*): Likewise.
1694 Document --build requirement.
1696 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1699 * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use
1700 TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags.
1702 PR rtl-optimization/94873
1703 * combine.c (combine_instructions): Don't optimize using REG_EQUAL
1704 note if SET_SRC (set) has side-effects.
1706 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1707 Wei Xiao <wei3.xiao@intel.com>
1709 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
1710 OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
1711 (ix86_handle_option): Handle -mserialize.
1712 * config.gcc (serializeintrin.h): New header file.
1713 * config/i386/cpuid.h (bit_SERIALIZE): New bit.
1714 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1716 * config/i386/i386-builtin.def: Add new builtin.
1717 * config/i386/i386-c.c (__SERIALIZE__): New macro.
1718 * config/i386/i386-options.c (ix86_target_opts_isa2_opts):
1720 * (ix86_valid_target_attribute_inner_p): Add target attribute
1722 * config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
1724 * config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
1725 (serialize): New define_insn.
1726 * config/i386/i386.opt (mserialize): New option
1727 * config/i386/immintrin.h: Include serailizeintrin.h.
1728 * config/i386/serializeintrin.h: New header file.
1729 * doc/invoke.texi: Add documents for -mserialize.
1731 2020-05-06 Richard Biener <rguenther@suse.de>
1733 * tree-cfg.c (verify_gimple_assign_unary): Adjust integer
1734 to/from pointer conversion checking.
1736 2020-05-05 Michael Meissner <meissner@linux.ibm.com>
1738 * config/rs6000/rs6000-builtin.def: Delete changes meant for a
1740 * config/rs6000/rs6000-c.c: Likewise.
1741 * config/rs6000/rs6000-call.c: Likewise.
1742 * config/rs6000/rs6000.c: Likewise.
1744 2020-05-05 Sebastian Huber <sebastian.huber@embedded-brains.de>
1746 * config/rtems.h (RTEMS_STARTFILE_SPEC): Define if undefined.
1747 (RTEMS_ENDFILE_SPEC): Likewise.
1748 (STARTFILE_SPEC): Update comment. Add RTEMS_STARTFILE_SPEC.
1749 (ENDFILE_SPEC): Add RTEMS_ENDFILE_SPEC.
1750 (LIB_SPECS): Support -nodefaultlibs option.
1751 * config/or1k/rtems.h (RTEMS_STARTFILE_SPEC): Define.
1752 (RTEMS_ENDFILE_SPEC): Likewise.
1753 * config/rs6000/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
1754 (RTEMS_ENDFILE_SPEC): Likewise.
1755 * config/v850/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
1756 (RTEMS_ENDFILE_SPEC): Likewise.
1758 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1760 * config/pru/pru.c (pru_hard_regno_call_part_clobbered): Remove.
1761 (TARGET_HARD_REGNO_CALL_PART_CLOBBERED): Remove.
1763 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1765 * config/pru/pru.h: Mark R3.w0 as caller saved.
1767 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1769 * config/pru/pru.c (pru_emit_doloop): Use new gen_doloop_end_internal
1770 and gen_doloop_begin_internal.
1771 (pru_reorg_loop): Use gen_pruloop with mode.
1772 * config/pru/pru.md: Use new @insn syntax.
1774 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
1776 * config/pru/pru.c (pru_print_operand): Fix fall through comment.
1778 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
1780 * config/i386/i386.md (fixuns_trunc<mode>si2): Use
1781 "clobber (scratch:M)" instad of "clobber (match_scratch:M N)".
1782 (addqi3_cconly_overflow): Ditto.
1783 (umulv<mode>4): Ditto.
1784 (<s>mul<mode>3_highpart): Ditto.
1785 (tls_global_dynamic_32): Ditto.
1786 (tls_local_dynamic_base_32): Ditto.
1793 (*adddi_4): Remove "m" constraint from scratch operand.
1794 (*add<mode>_4): Ditto.
1796 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1798 PR rtl-optimization/94516
1799 * postreload.c (reload_cse_simplify): When replacing sp = sp + const
1800 with sp = reg, add REG_EQUAL note with sp + const.
1801 * combine-stack-adj.c (try_apply_stack_adjustment): Change return
1802 type from int to bool. Add LIVE and OTHER_INSN arguments. Undo
1803 postreload sp = sp + const to sp = reg optimization if needed and
1805 (combine_stack_adjustments_for_block): Add LIVE argument. Handle
1806 reg = sp insn with sp + const REG_EQUAL note. Adjust
1807 try_apply_stack_adjustment caller, call
1808 df_simulate_initialize_forwards and df_simulate_one_insn_forwards.
1809 (combine_stack_adjustments): Allocate and free LIVE bitmap,
1810 adjust combine_stack_adjustments_for_block caller.
1812 2020-05-05 Martin Liska <mliska@suse.cz>
1814 PR gcov-profile/93623
1815 * tree-cfg.c (stmt_can_terminate_bb_p): Update comment to reflect
1818 2020-05-05 Martin Liska <mliska@suse.cz>
1820 * opt-functions.awk (opt_args_non_empty): New function.
1821 * opt-read.awk: Use the function for various option arguments.
1823 2020-05-05 Martin Liska <mliska@suse.cz>
1826 * lto-wrapper.c (run_gcc): When using -flto=jobserver,
1827 report warning when the jobserver is not detected.
1829 2020-05-05 Martin Liska <mliska@suse.cz>
1831 PR gcov-profile/94636
1832 * gcov.c (main): Print total lines summary at the end.
1833 (generate_results): Expect file_name always being non-null.
1834 Print newline after intermediate file is printed in order to align with
1835 what we do for normal files.
1837 2020-05-05 Martin Liska <mliska@suse.cz>
1839 * dumpfile.c (dump_switch_p): Change return type
1840 and print option suggestion.
1841 * dumpfile.h: Change return type.
1842 * opts-global.c (handle_common_deferred_options):
1843 Move error into dump_switch_p function.
1845 2020-05-05 Martin Liska <mliska@suse.cz>
1848 * alloc-pool.h: Use const for some arguments.
1849 * bitmap.h: Likewise.
1850 * mem-stats.h: Likewise.
1851 * sese.h (get_entry_bb): Likewise.
1852 (get_exit_bb): Likewise.
1854 2020-05-05 Richard Biener <rguenther@suse.de>
1856 * tree-vect-slp.c (struct vdhs_data): New.
1857 (vect_detect_hybrid_slp): New walker.
1858 (vect_detect_hybrid_slp): Rewrite.
1860 2020-05-05 Richard Biener <rguenther@suse.de>
1863 * tree-ssa-structalias.c (ipa_pta_execute): Use
1864 varpool_node::externally_visible_p ().
1865 (refered_from_nonlocal_var): Likewise.
1867 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
1869 * gcc.c (LTO_PLUGIN_SPEC): Define if not already.
1870 (LINK_PLUGIN_SPEC): Execute LTO_PLUGIN_SPEC.
1871 * config/vxworks.h (LTO_PLUGIN_SPEC): Define.
1873 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
1875 * gimplify.c (gimplify_init_constructor): Do not put the constructor
1876 into static memory if it is not complete.
1878 2020-05-05 Richard Biener <rguenther@suse.de>
1880 PR tree-optimization/94949
1881 * tree-ssa-loop-im.c (execute_sm): Check whether we use
1882 the multithreaded model or always compute the stored value
1883 before eliding a load.
1885 2020-05-05 Alex Coplan <alex.coplan@arm.com>
1887 * config/aarch64/aarch64.md (*one_cmpl_zero_extend): New.
1889 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1891 PR tree-optimization/94800
1892 * match.pd (X + (X << C) to X * (1 + (1 << C)),
1893 (X << C1) + (X << C2) to X * ((1 << C1) + (1 << C2))): New
1897 * config/i386/mmx.md (*vec_dupv4hi): Use xYw constraints instead of Yv.
1899 PR tree-optimization/94914
1900 * match.pd ((((type)A * B) >> prec) != 0 to .MUL_OVERFLOW(A, B) != 0):
1903 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
1905 * config/i386/i386.md (*testqi_ext_3): Use
1906 int_nonimmediate_operand instead of manual mode checks.
1907 (*x86_mov<SWI48:mode>cc_0_m1_neg_leu<SWI:mode>):
1908 Use int_nonimmediate_operand predicate. Rewrite
1909 define_insn_and_split pattern to a combine pass splitter.
1911 2020-05-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1913 * configure.ac <i[34567]86-*-*>: Add --32 to tls_as_opt on Solaris.
1914 * configure: Regenerate.
1916 2020-05-05 Jakub Jelinek <jakub@redhat.com>
1919 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
1920 ssse3_ph<plusminus_mnemonic>wv8hi3, ssse3_ph<plusminus_mnemonic>wv4hi3,
1921 avx2_ph<plusminus_mnemonic>dv8si3, ssse3_ph<plusminus_mnemonic>dv4si3,
1922 ssse3_ph<plusminus_mnemonic>dv2si3): Simplify RTL patterns.
1924 2020-05-04 Clement Chigot <clement.chigot@atos.net>
1925 David Edelsohn <dje.gcc@gmail.com>
1927 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override explicit
1928 for fmodl, frexpl, ldexpl and modfl builtins.
1930 2020-05-04 Richard Sandiford <richard.sandiford@arm.com>
1933 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the
1934 chosen lhs is different from the gcall lhs.
1935 (expand_mask_load_optab_fn): Likewise.
1936 (expand_gather_load_optab_fn): Likewise.
1938 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
1941 * config/i386/i386.md (*neg<mode>_ccc): New insn pattern.
1942 (EQ compare->LTU compare splitter): New splitter.
1943 (NE compare->NEG splitter): Ditto.
1945 2020-05-04 Marek Polacek <polacek@redhat.com>
1948 2020-04-30 Marek Polacek <polacek@redhat.com>
1951 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
1952 (check_aligned_type): Check if TYPE_USER_ALIGN match.
1954 2020-05-04 Richard Biener <rguenther@suse.de>
1956 PR tree-optimization/93891
1957 * tree-ssa-sccvn.c (vn_reference_lookup_3): Fall back to
1958 the original reference tree for assessing access alignment.
1960 2020-05-04 Richard Biener <rguenther@suse.de>
1962 PR tree-optimization/39612
1963 * tree-ssa-loop-im.c (im_mem_ref::loaded): New member.
1964 (set_ref_loaded_in_loop): New.
1965 (mark_ref_loaded): Likewise.
1966 (gather_mem_refs_stmt): Call mark_ref_loaded for loads.
1967 (execute_sm): Avoid issueing a load when it was not there.
1968 (execute_sm_if_changed): Avoid issueing warnings for the
1971 2020-05-04 Martin Jambor <mjambor@suse.cz>
1974 * tree-inline.c (tree_function_versioning): Leave any type conversion
1975 of replacements to setup_one_parameter and its friend
1976 force_value_to_type.
1978 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
1981 * config/i386/predicates.md (shr_comparison_operator): New predicate.
1982 * config/i386/i386.md (compare->shr splitter): New splitters.
1984 2020-05-04 Jakub Jelinek <jakub@redhat.com>
1986 PR tree-optimization/94718
1987 * match.pd ((X < 0) != (Y < 0) into (X ^ Y) < 0): New simplification.
1989 PR tree-optimization/94718
1990 * match.pd (bitop (convert @0) (convert? @1)): For GIMPLE, if we can,
1991 replace two nop conversions on bit_{and,ior,xor} argument
1992 and result with just one conversion on the result or another argument.
1994 PR tree-optimization/94718
1995 * fold-const.c (fold_binary_loc): Move (X & C) eqne (Y & C)
1996 -> (X ^ Y) & C eqne 0 optimization to ...
1997 * match.pd ((X & C) op (Y & C) into (X ^ Y) & C op 0): ... here.
1999 * opts.c (get_option_html_page): Instead of hardcoding a list of
2000 options common between C/C++ and Fortran only use gfortran/
2001 documentation for warnings that have CL_Fortran set but not
2004 2020-05-03 Uroš Bizjak <ubizjak@gmail.com>
2006 * config/i386/i386-expand.c (ix86_expand_int_movcc):
2007 Use plus_constant instead of gen_rtx_PLUS with GEN_INT.
2008 (emit_memmov): Ditto.
2009 (emit_memset): Ditto.
2010 (ix86_expand_strlensi_unroll_1): Ditto.
2011 (release_scratch_register_on_entry): Ditto.
2012 (gen_frame_set): Ditto.
2013 (ix86_emit_restore_reg_using_pop): Ditto.
2014 (ix86_emit_outlined_ms2sysv_restore): Ditto.
2015 (ix86_expand_epilogue): Ditto.
2016 (ix86_expand_split_stack_prologue): Ditto.
2017 * config/i386/i386.md (push immediate splitter): Ditto.
2021 2020-05-02 Iain Sandoe <iain@sandoe.co.uk>
2023 PR translation/93861
2024 * config/darwin-driver.c (darwin_driver_init): Adjust spelling in
2027 2020-05-02 Jakub Jelinek <jakub@redhat.com>
2029 * config/tilegx/tilegx.md
2030 (insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n>
2031 rather than just <n>.
2033 2020-05-01 H.J. Lu <hongjiu.lu@intel.com>
2036 * cfgexpand.c (pass_expand::execute): Set crtl->patch_area_size
2037 and crtl->patch_area_entry.
2038 * emit-rtl.h (rtl_data): Add patch_area_size and patch_area_entry.
2039 * opts.c (common_handle_option): Limit
2040 function_entry_patch_area_size and function_entry_patch_area_start
2041 to USHRT_MAX. Fix a typo in error message.
2042 * varasm.c (assemble_start_function): Use crtl->patch_area_size
2043 and crtl->patch_area_entry.
2044 * doc/invoke.texi: Document the maximum value for
2045 -fpatchable-function-entry.
2047 2020-05-01 Iain Sandoe <iain@sandoe.co.uk>
2049 * config/i386/darwin.h: Repair SUBTARGET_INIT_BUILTINS.
2050 Override SUBTARGET_SHADOW_OFFSET macro.
2052 2020-05-01 Andreas Tobler <andreast@gcc.gnu.org>
2054 * config/i386/i386.h: Define a new macro: SUBTARGET_SHADOW_OFFSET.
2055 * config/i386/i386.c (ix86_asan_shadow_offset): Use this macro.
2056 * config/i386/darwin.h: Override the SUBTARGET_SHADOW_OFFSET macro.
2057 * config/i386/freebsd.h: Likewise.
2058 * config/freebsd.h (LIBASAN_EARLY_SPEC): Define.
2059 LIBTSAN_EARLY_SPEC): Likewise. (LIBLSAN_EARLY_SPEC): Likewise.
2061 2020-04-30 Alexandre Oliva <oliva@adacore.com>
2063 * doc/sourcebuild.texi (Effective-Target Keywords): Document
2064 the newly-introduced fileio effective target.
2066 2020-04-30 Richard Sandiford <richard.sandiford@arm.com>
2068 PR rtl-optimization/94740
2069 * cse.c (cse_process_notes_1): Replace with...
2070 (cse_process_note_1): ...this new function, acting as a
2071 simplify_replace_fn_rtx callback to process_note. Handle only
2072 REGs and MEMs directly. Validate the MEM if cse_process_note
2073 changes its address.
2074 (cse_process_notes): Replace with...
2075 (cse_process_note): ...this new function.
2076 (cse_extended_basic_block): Update accordingly, iterating over
2077 the register notes and passing individual notes to cse_process_note.
2079 2020-04-30 Carl Love <cel@us.ibm.com>
2081 * config/rs6000/emmintrin.h (_mm_movemask_epi8): Fix comment.
2083 2020-04-30 Martin Jambor <mjambor@suse.cz>
2086 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies
2087 saved by the inliner and thunks which had their call inlined.
2088 * ipa-inline-transform.c (save_inline_function_body): Fill in
2089 former_clone_of of new body holders.
2091 2020-04-30 Jakub Jelinek <jakub@redhat.com>
2093 * BASE-VER: Set to 11.0.0.
2095 2020-04-30 Jonathan Wakely <jwakely@redhat.com>
2097 * pretty-print.c (pp_take_prefix): Fix spelling in comment.
2099 2020-04-30 Marek Polacek <polacek@redhat.com>
2102 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
2103 (check_aligned_type): Check if TYPE_USER_ALIGN match.
2105 2020-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2107 * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define.
2108 * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable.
2109 * doc/invoke.texi (moutline-atomics): Document as on by default.
2111 2020-04-30 Szabolcs Nagy <szabolcs.nagy@arm.com>
2114 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove
2115 the check for NOTE_INSN_DELETED_LABEL.
2117 2020-04-30 Jakub Jelinek <jakub@redhat.com>
2119 * configure.ac (--with-documentation-root-url,
2120 --with-changes-root-url): Diagnose URL not ending with /,
2121 use AC_DEFINE_UNQUOTED instead of AC_SUBST.
2122 * opts.h (get_changes_url): Remove.
2123 * opts.c (get_changes_url): Remove.
2124 * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL
2125 or -DCHANGES_ROOT_URL.
2126 * doc/install.texi (--with-documentation-root-url,
2127 --with-changes-root-url): Document.
2128 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call
2129 get_changes_url and free, change url variable type to const char * and
2130 set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base".
2131 * config/s390/s390.c (s390_function_arg_vector,
2132 s390_function_arg_float): Likewise.
2133 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
2135 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
2137 * config.in: Regenerate.
2138 * configure: Regenerate.
2140 2020-04-30 Christophe Lyon <christophe.lyon@linaro.org>
2143 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries.
2145 2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
2147 * config/s390/constraints.md ("j>f", "jb4"): New constraints.
2148 * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix
2150 * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a
2152 ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst.
2153 Change constraint for vlrl/vstrl to jb4.
2155 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2157 * var-tracking.c (vt_initialize): Move variables pre and post
2158 into inner block and initialize both in order to fix warning
2159 about uninitialized use. Remove unnecessary checks for
2160 frame_pointer_needed.
2162 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2164 * toplev.c (output_stack_usage_1): Ensure that first
2165 argument to fprintf is not null.
2167 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2169 * configure.ac (-with-changes-root-url): New configure option,
2170 defaulting to https://gcc.gnu.org/.
2171 * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for
2173 * pretty-print.c (get_end_url_string): New function.
2174 (pp_format): Handle %{ and %} for URLs.
2175 (pp_begin_url): Use pp_string instead of pp_printf.
2176 (pp_end_url): Use get_end_url_string.
2177 * opts.h (get_changes_url): Declare.
2178 * opts.c (get_changes_url): New function.
2179 * config/rs6000/rs6000-call.c: Include opts.h.
2180 (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead
2181 of just in GCC 10.1 in diagnostics and add URL.
2182 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise.
2183 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
2185 * config/s390/s390.c (s390_function_arg_vector,
2186 s390_function_arg_float): Likewise.
2187 * configure: Regenerated.
2190 * config/s390/s390.c (s390_function_arg_vector,
2191 s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of
2192 cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type
2193 passed to the function rather than the type of the single element.
2194 Rename cxx17_empty_base_seen variable to empty_base_seen, change
2195 type to int, and adjust diagnostics depending on if the field
2196 has [[no_unique_attribute]] or not.
2199 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8,
2200 _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands
2201 used in casts into parens.
2202 * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph,
2203 _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph,
2204 _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph,
2205 _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask,
2206 _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask,
2207 _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask,
2208 _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise.
2209 * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8,
2210 _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8,
2211 _mm256_mask_cmp_epu8_mask): Likewise.
2212 * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph,
2213 _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise.
2214 * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise.
2215 * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise.
2218 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd,
2219 _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd,
2220 _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps,
2221 _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps,
2222 _mm256_mask_i64gather_ps, _mm_i32gather_epi64,
2223 _mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
2224 _mm256_mask_i32gather_epi64, _mm_i64gather_epi64,
2225 _mm_mask_i64gather_epi64, _mm256_i64gather_epi64,
2226 _mm256_mask_i64gather_epi64, _mm_i32gather_epi32,
2227 _mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
2228 _mm256_mask_i32gather_epi32, _mm_i64gather_epi32,
2229 _mm_mask_i64gather_epi32, _mm256_i64gather_epi32,
2230 _mm256_mask_i64gather_epi32): Surround macro parameter uses with
2232 (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd,
2233 _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps,
2234 _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use
2235 as mask vector containing -1.0 or -1.0f elts, but instead vector
2236 with all bits set using _mm*_cmpeq_p? with zero operands.
2237 * config/i386/avx512fintrin.h (_mm512_i32gather_ps,
2238 _mm512_mask_i32gather_ps, _mm512_i32gather_pd,
2239 _mm512_mask_i32gather_pd, _mm512_i64gather_ps,
2240 _mm512_mask_i64gather_ps, _mm512_i64gather_pd,
2241 _mm512_mask_i64gather_pd, _mm512_i32gather_epi32,
2242 _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64,
2243 _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32,
2244 _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64,
2245 _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps,
2246 _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd,
2247 _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps,
2248 _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd,
2249 _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32,
2250 _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64,
2251 _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32,
2252 _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64,
2253 _mm512_mask_i64scatter_epi64): Surround macro parameter uses with
2255 * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd,
2256 _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd,
2257 _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd,
2258 _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd,
2259 _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd,
2260 _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd,
2261 _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd,
2262 _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd,
2263 _mm512_mask_prefetch_i64scatter_ps): Likewise.
2264 * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps,
2265 _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd,
2266 _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps,
2267 _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd,
2268 _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32,
2269 _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64,
2270 _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32,
2271 _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64,
2272 _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps,
2273 _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps,
2274 _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd,
2275 _mm_mask_i32scatter_pd, _mm256_i64scatter_ps,
2276 _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps,
2277 _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd,
2278 _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32,
2279 _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32,
2280 _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64,
2281 _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64,
2282 _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32,
2283 _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32,
2284 _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64,
2285 _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64,
2286 _mm_mask_i64scatter_epi64): Likewise.
2288 2020-04-29 Jeff Law <law@redhat.com>
2290 * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific
2291 division instructions are 4 bytes long.
2293 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2296 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use
2297 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2298 fenv_var, fenv_clear and old_fenv variables. For fenv_addr
2299 take address of TARGET_EXPR of fenv_var with void_node initializer.
2302 2020-04-29 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2304 PR tree-optimization/94774
2305 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize
2308 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2310 * calls.h (cxx17_empty_base_field_p): Turn into a function declaration.
2311 * calls.c (cxx17_empty_base_field_p): New function. Check
2312 DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the
2315 2020-04-29 H.J. Lu <hongjiu.lu@intel.com>
2318 * config/i386/i386-options.c (ix86_set_indirect_branch_type):
2319 Allow -fcf-protection with -mindirect-branch=thunk-extern and
2320 -mfunction-return=thunk-extern.
2321 * doc/invoke.texi: Update notes for -fcf-protection=branch with
2322 -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern.
2324 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2326 * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor.
2328 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2330 * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
2331 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
2332 fenv_var and new_fenv_var.
2334 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2336 * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new
2337 effective-target keyword.
2338 (arm_arch_v8a_hard_multilib): Likewise.
2339 (arm_arch_v8a_hard): Document new dg-add-options keyword.
2340 * config/arm/arm.c (arm_return_in_memory): Note that the APCS
2341 code is deprecated and has not been updated to handle
2342 DECL_FIELD_ABI_IGNORED.
2343 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2344 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2345 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2346 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2347 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2348 something actually is a HFA or HVA. Record whether we see a
2349 [[no_unique_address]] field that previous GCCs would not have
2350 ignored in this way.
2351 (aapcs_vfp_is_call_or_return_candidate): Update the calls to
2352 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2353 [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the
2354 diagnostic messages.
2355 (arm_needs_doubleword_align): Add a comment explaining why we
2356 consider even zero-sized fields.
2358 2020-04-29 Richard Biener <rguenther@suse.de>
2359 Li Zekun <lizekun1@huawei.com>
2362 * tree.c (component_ref_size): Guard against error_mark_node
2363 DECL_INITIAL as it happens with LTO.
2365 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2367 * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a
2368 comment explaining why we consider even zero-sized fields.
2369 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2370 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2371 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2372 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2373 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2374 something actually is a HFA or HVA. Record whether we see a
2375 [[no_unique_address]] field that previous GCCs would not have
2376 ignored in this way.
2377 (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say
2378 whether diagnostics should be suppressed. Update the calls to
2379 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2380 [[no_unique_address]] case.
2381 (aarch64_return_in_msb): Update call accordingly, never silencing
2383 (aarch64_function_value): Likewise.
2384 (aarch64_return_in_memory_1): Likewise.
2385 (aarch64_init_cumulative_args): Likewise.
2386 (aarch64_gimplify_va_arg_expr): Likewise.
2387 (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and
2388 use it to decide whether arch64_vfp_is_call_or_return_candidate
2390 (aarch64_pass_by_reference): Update calls accordingly.
2391 (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument
2392 to decide whether arch64_vfp_is_call_or_return_candidate should be
2395 2020-04-29 Haijian Zhang <z.zhanghaijian@huawei.com>
2398 * config/aarch64/aarch64-builtins.c
2399 (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of
2400 MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and
2403 2020-04-29 Thomas Schwinge <thomas@codesourcery.com>
2405 * configure.ac <$enable_offload_targets>: Do parsing as done
2407 * configure: Regenerate.
2409 * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'.
2410 * configure: Regenerate.
2413 * rtlanal.c (set_noop_p): Handle non-constant selectors.
2416 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New
2418 (TARGET_EXCEPT_UNWIND_INFO): Define.
2420 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2423 * config/gcn/gcn.md (*mov<mode>_insn): Use
2424 'reg_overlap_mentioned_p' to check for overlap.
2427 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED
2428 instead of cxx17_empty_base_field_p.
2431 * tree-core.h (tree_decl_common): Note decl_flag_0 used for
2432 DECL_FIELD_ABI_IGNORED.
2433 * tree.h (DECL_FIELD_ABI_IGNORED): Define.
2434 * calls.h (cxx17_empty_base_field_p): Change into a temporary
2435 macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address"
2437 * calls.c (cxx17_empty_base_field_p): Remove.
2438 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle
2439 DECL_FIELD_ABI_IGNORED.
2440 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
2441 * lto-streamer-out.c (hash_tree): Likewise.
2442 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename
2443 cxx17_empty_base_seen to empty_base_seen, change type to int *,
2444 adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of
2445 cxx17_empty_base_field_p, if "no_unique_address" attribute is
2446 present, propagate that to the caller too.
2447 (rs6000_discover_homogeneous_aggregate): Adjust
2448 rs6000_aggregate_candidate caller, emit different diagnostics
2449 when c++17 empty base fields are present and when empty
2450 [[no_unique_address]] fields are present.
2451 * config/rs6000/rs6000.c (rs6000_special_round_type_align,
2452 darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED
2455 2020-04-29 Richard Biener <rguenther@suse.de>
2457 * tree-ssa-loop-im.c (ref_always_accessed::operator ()):
2458 Just check whether the stmt stores.
2460 2020-04-28 Alexandre Oliva <oliva@adacore.com>
2463 * config/rs6000/rs6000.md (rs6000_mffsl): Copy result to
2464 output operand in emulation. Don't overwrite pseudos.
2466 2020-04-28 Jeff Law <law@redhat.com>
2468 * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific
2469 multiply patterns are 4 bytes long.
2471 2020-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2473 * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option.
2474 * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option.
2476 2020-04-28 Matthew Malcomson <matthew.malcomson@arm.com>
2477 Jakub Jelinek <jakub@redhat.com>
2480 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty
2481 base class artificial fields.
2482 (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI
2483 decision is different after this fix.
2485 2020-04-28 David Malcolm <dmalcolm@redhat.com>
2491 * doc/invoke.texi (Static Analyzer Options): Remove
2492 -Wanalyzer-use-of-uninitialized-value.
2493 (-Wno-analyzer-use-of-uninitialized-value): Remove item.
2495 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2497 PR tree-optimization/94809
2498 * tree.c (build_call_expr_internal_loc_array): Call
2499 process_call_operands.
2501 2020-04-27 Anton Youdkevitch <anton.youdkevitch@bell-sw.com>
2503 * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name.
2504 * config/aarch64/aarch64-tune.md: Regenerate.
2505 * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define.
2506 (thunderx3t110_regmove_cost): Likewise.
2507 (thunderx3t110_vector_cost): Likewise.
2508 (thunderx3t110_prefetch_tune): Likewise.
2509 (thunderx3t110_tunings): Likewise.
2510 * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs):
2512 * config/aarch64/thunderx3t110.md: New file.
2513 * config/aarch64/aarch64.md: Include thunderx3t110.md.
2514 * doc/invoke.texi (AArch64 options): Add thunderx3t110.
2516 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2519 * config/s390/s390.c (s390_function_arg_vector,
2520 s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed.
2522 2020-04-28 Richard Sandiford <richard.sandiford@arm.com>
2524 PR tree-optimization/94727
2525 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison
2526 operands are invariant booleans, use the mask type associated with the
2527 STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP.
2528 (vectorizable_condition): Pass vectype unconditionally to
2529 vect_is_simple_cond.
2531 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2534 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use
2535 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2536 sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var.
2538 2020-04-27 David Malcolm <dmalcolm@redhat.com>
2541 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from
2542 default value, so that it can by supplied by get_option_html_page.
2543 * configure: Regenerate.
2544 * opts.c: Include "selftest.h".
2545 (get_option_html_page): New function.
2546 (get_option_url): Use it. Reformat to place comments next to the
2547 expressions they refer to.
2548 (selftest::test_get_option_html_page): New.
2549 (selftest::opts_c_tests): New.
2550 * selftest-run-tests.c (selftest::run_tests): Call
2551 selftest::opts_c_tests.
2552 * selftest.h (selftest::opts_c_tests): New decl.
2554 2020-04-27 Richard Sandiford <richard.sandiford@arm.com>
2556 * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply
2557 UINTVAL to CONST_INTs.
2559 2020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2561 * config/arm/constraints.md (e): Remove constraint.
2562 (Te): Define constraint.
2563 * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in
2564 operand 0 from "e" to "Te".
2565 (vaddvaq_<supf><mode>): Likewise.
2566 (vaddvq_p_<supf><mode>): Likewise.
2567 (vmladavq_<supf><mode>): Likewise.
2568 (vmladavxq_s<mode>): Likewise.
2569 (vmlsdavq_s<mode>): Likewise.
2570 (vmlsdavxq_s<mode>): Likewise.
2571 (vaddvaq_p_<supf><mode>): Likewise.
2572 (vmladavaq_<supf><mode>): Likewise.
2573 (vmladavq_p_<supf><mode>): Likewise.
2574 (vmladavxq_p_s<mode>): Likewise.
2575 (vmlsdavq_p_s<mode>): Likewise.
2576 (vmlsdavxq_p_s<mode>): Likewise.
2577 (vmlsdavaxq_s<mode>): Likewise.
2578 (vmlsdavaq_s<mode>): Likewise.
2579 (vmladavaxq_s<mode>): Likewise.
2580 (vmladavaq_p_<supf><mode>): Likewise.
2581 (vmladavaxq_p_s<mode>): Likewise.
2582 (vmlsdavaq_p_s<mode>): Likewise.
2583 (vmlsdavaxq_p_s<mode>): Likewise.
2585 2020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com>
2587 * config/arm/arm.c (output_move_neon): Only get the first operand if
2590 2020-04-27 Felix Yang <felix.yang@huawei.com>
2592 PR tree-optimization/94784
2593 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the
2594 assert around so that it checks that the two vectors have equal
2595 TYPE_VECTOR_SUBPARTS and that converting the corresponding element
2596 types is a useless_type_conversion_p.
2598 2020-04-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
2601 * dwarf2cfi.c (struct GTY): Add ra_mangled.
2602 (cfi_row_equal_p): Check ra_mangled.
2603 (dwarf2out_frame_debug_cfa_window_save): Remove the argument,
2604 this only handles the sparc logic now.
2605 (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for
2606 the aarch64 specific logic.
2607 (dwarf2out_frame_debug): Update to use the new subroutines.
2608 (change_cfi_row): Check ra_mangled.
2610 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2613 * config/s390/s390.c (s390_function_arg_vector,
2614 s390_function_arg_float): Ignore cxx17_empty_base_field_p fields.
2616 2020-04-27 Jiufu Guo <guojiufu@cn.ibm.com>
2618 * common/config/rs6000/rs6000-common.c
2619 (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off
2621 * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to
2624 2020-04-27 Martin Liska <mliska@suse.cz>
2627 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p):
2628 Do not remove ifunc_resolvers in remove unreachable nodes in LTO.
2630 2020-04-27 Xiong Hu Luo <luoxhu@linux.ibm.com>
2633 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed):
2635 (rs6000_emit_prologue_components):
2636 Check with frame_pointer_needed_indeed.
2637 (rs6000_emit_epilogue_components): Likewise.
2638 (rs6000_emit_prologue): Likewise.
2639 (rs6000_emit_epilogue): Set frame_pointer_needed_indeed.
2641 2020-04-25 David Edelsohn <dje.gcc@gmail.com>
2643 * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a
2644 stack frame when debugging and flag_compare_debug is enabled.
2646 2020-04-25 Michael Meissner <meissner@linux.ibm.com>
2648 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to
2649 enable PC-relative addressing for -mcpu=future.
2650 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move
2651 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS.
2652 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined,
2653 suppress PC-relative addressing.
2654 (rs6000_option_override_internal): Split up error messages
2655 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target
2658 2020-04-25 Jakub Jelinek <jakub@redhat.com>
2659 Richard Biener <rguenther@suse.de>
2661 PR tree-optimization/94734
2662 PR tree-optimization/89430
2663 * tree-ssa-phiopt.c: Include tree-eh.h.
2664 (cond_store_replacement): Return false if an automatic variable
2665 access could trap. If -fstore-data-races, don't return false
2666 just because an automatic variable is addressable.
2668 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2670 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
2672 (add<mode>_sext_dup2_exec): Likewise.
2674 2020-04-24 Segher Boessenkool <segher@kernel.crashing.org>
2677 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
2678 endian byteshift_val calculation.
2680 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2682 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
2684 2020-04-24 Richard Sandiford <richard.sandiford@arm.com>
2686 * config/aarch64/arm_sve.h: Add a comment.
2688 2020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com>
2690 PR rtl-optimization/94708
2691 * combine.c (simplify_if_then_else): Add check for
2692 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode).
2694 2020-04-23 Martin Sebor <msebor@redhat.com>
2697 * common.opt (-Wno-frame-larger-than): New option.
2698 (-Wno-larger-than, -Wno-stack-usage): Same.
2700 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
2702 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands
2704 (mov<mode>_exec): Likewise.
2705 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec.
2706 (<convop><mode><vndi>2_exec): Likewise.
2708 2019-04-23 Eric Botcazou <ebotcazou@adacore.com>
2710 PR tree-optimization/94717
2711 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one
2712 of the stores doesn't have the same landing pad number as the first.
2713 (coalesce_immediate_stores): Do not try to coalesce the store using
2714 bswap if it doesn't have the same landing pad number as the first.
2716 2020-04-23 Bill Schmidt <wschmidt@linux.ibm.com>
2718 * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
2719 Replace outdated link to ELFv2 ABI.
2721 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2724 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
2728 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs
2729 temporarily with non-final second operand and updating it later,
2730 push COMPOUND_EXPRs into a vector and process it in reverse,
2731 creating COMPOUND_EXPRs with the final operands.
2733 2020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com>
2736 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap
2737 bti c and bti j handling.
2739 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
2740 Thomas Schwinge <thomas@codesourcery.com>
2744 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on
2745 t_async and the wait arguments.
2747 2020-04-23 Richard Sandiford <richard.sandiford@arm.com>
2749 PR tree-optimization/94727
2750 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when
2751 comparing invariant scalar booleans.
2753 2020-04-23 Matthew Malcomson <matthew.malcomson@arm.com>
2754 Jakub Jelinek <jakub@redhat.com>
2757 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17
2758 empty base class artificial fields.
2759 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is
2760 different after this fix.
2762 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2765 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
2766 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check
2767 if the same type has been diagnosed most recently already.
2769 2020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2771 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's
2773 (__arm_vbicq_n_s16): Likewise.
2774 (__arm_vbicq_n_u32): Likewise.
2775 (__arm_vbicq_n_s32): Likewise.
2776 (__arm_vbicq): Likewise.
2777 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype.
2778 (__arm_vbicq_n_s32): Likewise.
2779 (__arm_vbicq_n_u16): Likewise.
2780 (__arm_vbicq_n_u32): Likewise.
2781 (__arm_vdupq_m_n_s8): Likewise.
2782 (__arm_vdupq_m_n_s16): Likewise.
2783 (__arm_vdupq_m_n_s32): Likewise.
2784 (__arm_vdupq_m_n_u8): Likewise.
2785 (__arm_vdupq_m_n_u16): Likewise.
2786 (__arm_vdupq_m_n_u32): Likewise.
2787 (__arm_vdupq_m_n_f16): Likewise.
2788 (__arm_vdupq_m_n_f32): Likewise.
2789 (__arm_vldrhq_gather_offset_s16): Likewise.
2790 (__arm_vldrhq_gather_offset_s32): Likewise.
2791 (__arm_vldrhq_gather_offset_u16): Likewise.
2792 (__arm_vldrhq_gather_offset_u32): Likewise.
2793 (__arm_vldrhq_gather_offset_f16): Likewise.
2794 (__arm_vldrhq_gather_offset_z_s16): Likewise.
2795 (__arm_vldrhq_gather_offset_z_s32): Likewise.
2796 (__arm_vldrhq_gather_offset_z_u16): Likewise.
2797 (__arm_vldrhq_gather_offset_z_u32): Likewise.
2798 (__arm_vldrhq_gather_offset_z_f16): Likewise.
2799 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
2800 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
2801 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
2802 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
2803 (__arm_vldrhq_gather_shifted_offset_f16): Likewise.
2804 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
2805 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
2806 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
2807 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
2808 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise.
2809 (__arm_vldrwq_gather_offset_s32): Likewise.
2810 (__arm_vldrwq_gather_offset_u32): Likewise.
2811 (__arm_vldrwq_gather_offset_f32): Likewise.
2812 (__arm_vldrwq_gather_offset_z_s32): Likewise.
2813 (__arm_vldrwq_gather_offset_z_u32): Likewise.
2814 (__arm_vldrwq_gather_offset_z_f32): Likewise.
2815 (__arm_vldrwq_gather_shifted_offset_s32): Likewise.
2816 (__arm_vldrwq_gather_shifted_offset_u32): Likewise.
2817 (__arm_vldrwq_gather_shifted_offset_f32): Likewise.
2818 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise.
2819 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise.
2820 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise.
2821 (__arm_vdwdupq_x_n_u8): Likewise.
2822 (__arm_vdwdupq_x_n_u16): Likewise.
2823 (__arm_vdwdupq_x_n_u32): Likewise.
2824 (__arm_viwdupq_x_n_u8): Likewise.
2825 (__arm_viwdupq_x_n_u16): Likewise.
2826 (__arm_viwdupq_x_n_u32): Likewise.
2827 (__arm_vidupq_x_n_u8): Likewise.
2828 (__arm_vddupq_x_n_u8): Likewise.
2829 (__arm_vidupq_x_n_u16): Likewise.
2830 (__arm_vddupq_x_n_u16): Likewise.
2831 (__arm_vidupq_x_n_u32): Likewise.
2832 (__arm_vddupq_x_n_u32): Likewise.
2833 (__arm_vldrdq_gather_offset_s64): Likewise.
2834 (__arm_vldrdq_gather_offset_u64): Likewise.
2835 (__arm_vldrdq_gather_offset_z_s64): Likewise.
2836 (__arm_vldrdq_gather_offset_z_u64): Likewise.
2837 (__arm_vldrdq_gather_shifted_offset_s64): Likewise.
2838 (__arm_vldrdq_gather_shifted_offset_u64): Likewise.
2839 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise.
2840 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise.
2841 (__arm_vidupq_m_n_u8): Likewise.
2842 (__arm_vidupq_m_n_u16): Likewise.
2843 (__arm_vidupq_m_n_u32): Likewise.
2844 (__arm_vddupq_m_n_u8): Likewise.
2845 (__arm_vddupq_m_n_u16): Likewise.
2846 (__arm_vddupq_m_n_u32): Likewise.
2847 (__arm_vidupq_n_u16): Likewise.
2848 (__arm_vidupq_n_u32): Likewise.
2849 (__arm_vidupq_n_u8): Likewise.
2850 (__arm_vddupq_n_u16): Likewise.
2851 (__arm_vddupq_n_u32): Likewise.
2852 (__arm_vddupq_n_u8): Likewise.
2854 2020-04-23 Iain Buclaw <ibuclaw@gdcproject.org>
2856 * doc/install.texi (D-Specific Options): Document
2857 --enable-libphobos-checking and --with-libphobos-druntime-only.
2859 2020-04-23 Jakub Jelinek <jakub@redhat.com>
2862 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add
2863 cxx17_empty_base_seen argument. Pass it to recursive calls.
2864 Ignore cxx17_empty_base_field_p fields after setting
2865 *cxx17_empty_base_seen to true.
2866 (rs6000_discover_homogeneous_aggregate): Adjust
2867 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous
2868 aggregates with C++17 empty base fields.
2871 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
2872 if last_decl is error_mark_node or has such a TREE_TYPE.
2875 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
2876 if last_decl is error_mark_node or has such a TREE_TYPE.
2878 2020-04-22 Felix Yang <felix.yang@huawei.com>
2881 * config/aarch64/aarch64.h (TARGET_SVE):
2882 Add && !TARGET_GENERAL_REGS_ONLY.
2883 (TARGET_SVE2): Add && TARGET_SVE.
2884 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3,
2885 TARGET_SVE2_SM4): Add && TARGET_SVE2.
2886 * config/aarch64/aarch64-sve-builtins.h
2887 (sve_switcher::m_old_general_regs_only): New member.
2888 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers):
2890 (reported_missing_registers_p): New variable.
2891 (check_required_extensions): Call check_required_registers before
2892 return if all required extenstions are present.
2893 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in
2894 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in
2895 global_options.x_target_flags.
2896 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in
2897 global_options.x_target_flags if m_old_general_regs_only is true.
2899 2020-04-22 Zackery Spytz <zspytz@gmail.com>
2901 * doc/extend.exi: Add "free" to list of other builtin functions
2904 2020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com>
2907 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed"
2909 (store_quadpti): Ditto.
2910 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as
2911 plq will be used and doesn't need it.
2912 (atomic_store<mode>): Ditto, for pstq.
2914 2020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com>
2916 * doc/invoke.texi: Update flags turned on by -O3.
2918 2020-04-22 Jakub Jelinek <jakub@redhat.com>
2921 * config/ia64/ia64.c (hfa_element_mode): Ignore
2922 cxx17_empty_base_field_p fields.
2925 * calls.h (cxx17_empty_base_field_p): Declare.
2926 * calls.c (cxx17_empty_base_field_p): Define.
2928 2020-04-22 Christophe Lyon <christophe.lyon@linaro.org>
2930 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document.
2932 2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2933 Andre Vieira <andre.simoesdiasvieira@arm.com>
2934 Mihail Ionescu <mihail.ionescu@arm.com>
2936 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
2937 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
2938 (ALL_QUIRKS): Add quirk_no_asmcpu.
2939 (cortex-m55): Define new cpu.
2940 * config/arm/arm-tables.opt: Regenerate.
2941 * config/arm/arm-tune.md: Likewise.
2942 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
2944 2020-04-22 Richard Sandiford <richard.sandiford@arm.com>
2946 PR tree-optimization/94700
2947 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing
2948 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures
2949 of similarly-structured but distinct vector types.
2951 2020-04-21 Martin Sebor <msebor@redhat.com>
2954 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct
2955 the computation of the lower bound of the source access size.
2956 (builtin_access::generic_overlap): Remove a hack for setting ranges
2959 2020-04-21 John David Anglin <danglin@gcc.gnu.org>
2961 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete.
2962 (ASM_WEAKEN_DECL): New define.
2963 (HAVE_GAS_WEAKREF): Undefine.
2965 2020-04-21 Richard Sandiford <richard.sandiford@arm.com>
2967 PR tree-optimization/94683
2968 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a
2969 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured
2970 but distinct vector types.
2972 2020-04-21 Jakub Jelinek <jakub@redhat.com>
2975 * stor-layout.c (place_field, finalize_record_size): Don't emit
2976 -Wpadded warning on TYPE_ARTIFICIAL rli->t.
2977 * ubsan.c (ubsan_get_type_descriptor_type,
2978 ubsan_get_source_location_type, ubsan_create_data): Set
2980 * asan.c (asan_global_struct): Likewise.
2982 2020-04-21 Duan bo <duanbo3@huawei.com>
2985 * config/aarch64/aarch64.c: Add an error message for option conflict.
2986 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is
2987 incompatible with -fpic, -fPIC and -mabi=ilp32.
2989 2020-04-21 Frederik Harwath <frederik@codesourcery.com>
2992 * omp-low.c (new_omp_context): Remove assignments to
2993 ctx->outer_reduction_clauses and ctx->local_reduction_clauses.
2995 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
2997 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
2998 ("popcountv2di2_vx"): Use simplify_gen_subreg.
3000 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
3003 * config/s390/s390-builtin-types.def: Add 3 new function modes.
3004 * config/s390/s390-builtins.def: Add mode dependent low-level
3005 builtin and map the overloaded builtins to these.
3006 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
3007 ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
3009 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
3011 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo
3012 has a variable VF, prefer new_loop_vinfo if it is cheaper for the
3013 estimated VF and is no worse at double the estimated VF.
3015 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
3018 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix
3019 order of arguments to rtx_vector_builder.
3020 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise.
3021 When extending the trailing constants to a full vector, replace any
3022 variables with zeros.
3024 2020-04-20 Jan Hubicka <hubicka@ucw.cz>
3027 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local
3030 2020-04-20 Martin Liska <mliska@suse.cz>
3032 * symtab.c (symtab_node::dump_references): Add space after
3034 (symtab_node::dump_referring): Likewise.
3036 2020-04-18 Jeff Law <law@redhat.com>
3039 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking
3042 2020-04-18 Iain Buclaw <ibuclaw@gdcproject.org>
3044 * doc/sourcebuild.texi (Effective-Target Keywords, Environment
3045 attributes): Document d_runtime_has_std_library.
3047 2020-04-17 Jeff Law <law@redhat.com>
3049 PR rtl-optimization/90275
3050 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels
3051 when the destination has a REG_UNUSED note.
3053 2020-04-17 Tobias Burnus <tobias@codesourcery.com>
3056 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to
3059 2020-04-17 Richard Sandiford <richard.sandiford@arm.com>
3061 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function.
3062 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the
3063 cost of load and store insns if one loop iteration has enough scalar
3064 elements to use an Advanced SIMD LDP or STP.
3065 (aarch64_add_stmt_cost): Update call accordingly.
3067 2020-04-17 Jakub Jelinek <jakub@redhat.com>
3068 Jeff Law <law@redhat.com>
3071 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than
3072 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision,
3073 or pos + len >= 32, or pos + len is equal to operands[2] precision
3074 and operands[2] is not a register operand. During splitting perform
3075 SImode AND if operands[0] doesn't have CCZmode and pos + len is
3076 equal to mode precision.
3078 2020-04-17 Richard Biener <rguenther@suse.de>
3081 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate
3083 * dwarf2out.c (dw_val_equal_p): Fix pasto in
3084 dw_val_class_vms_delta comparison.
3085 * optabs.c (expand_binop_directly): Fix pasto in commutation
3087 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in
3090 2020-04-17 Jakub Jelinek <jakub@redhat.com>
3092 PR rtl-optimization/94618
3093 * cfgrtl.c (delete_insn_and_edges): Set purge not just when
3094 insn is the BB_END of its block, but also when it is only followed
3095 by DEBUG_INSNs in its block.
3097 PR tree-optimization/94621
3098 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN.
3099 Move id->adjust_array_error_bounds check first in the condition.
3101 2020-04-17 Martin Liska <mliska@suse.cz>
3102 Jonathan Yong <10walls@gmail.com>
3104 PR gcov-profile/94570
3105 * coverage.c (coverage_init): Use separator properly.
3107 2020-04-16 Peter Bergner <bergner@linux.ibm.com>
3109 PR rtl-optimization/93974
3110 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
3111 (rs6000_cannot_substitute_mem_equiv_p): New function.
3113 2020-04-16 Martin Jambor <mjambor@suse.cz>
3116 * ipa-inline.h (ipa_saved_clone_sources): Declare.
3117 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable.
3118 (save_inline_function_body): Link the new body holder with the
3120 * cgraph.c: Include ipa-inline.h.
3121 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from
3122 the statement in ipa_saved_clone_sources.
3123 * cgraphunit.c: Include ipa-inline.h.
3124 (expand_all_functions): Free ipa_saved_clone_sources.
3126 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
3129 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
3130 the VNx16BI lowpart of the recursively-generated constant.
3132 2020-04-16 Martin Liska <mliska@suse.cz>
3133 Jakub Jelinek <jakub@redhat.com>
3136 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
3137 DECL_IS_REPLACEABLE_OPERATOR during cloning.
3138 * tree-ssa-dce.c (valid_new_delete_pair_p): New function.
3139 (propagate_necessity): Check operator names.
3141 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
3143 PR rtl-optimization/94605
3144 * early-remat.c (early_remat::process_block): Handle insns that
3145 set multiple candidate registers.
3146 2020-04-16 Jan Hubicka <hubicka@ucw.cz>
3148 PR gcov-profile/93401
3149 * common.opt (profile-prefix-path): New option.
3150 * coverae.c: Include diagnostics.h.
3151 (coverage_init): Strip profile prefix path.
3152 * doc/invoke.texi (-fprofile-prefix-path): Document.
3154 2020-04-16 Richard Biener <rguenther@suse.de>
3157 * expr.c (emit_move_multi_word): Do not generate code when
3158 the destination part is undefined_operand_subword_p.
3159 * lower-subreg.c (resolve_clobber): Look through a paradoxica
3162 2020-04-16 Martin Jambor <mjambor@suse.cz>
3164 PR tree-optimization/94598
3165 * tree-sra.c (verify_sra_access_forest): Fix verification of total
3166 scalarization accesses under access to one-element arrays.
3168 2020-04-16 Jakub Jelinek <jakub@redhat.com>
3171 * function.c (assign_parm_find_data_types): Add workaround for
3172 BROKEN_VALUE_INITIALIZATION compilers.
3174 2020-04-16 Richard Biener <rguenther@suse.de>
3176 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME
3179 2020-04-15 Uroš Bizjak <ubizjak@gmail.com>
3182 * config/i386/i386-builtin.def (__builtin_ia32_movq128):
3183 Require OPTION_MASK_ISA_SSE2.
3185 2020-04-15 Gustavo Romero <gromero@linux.ibm.com>
3188 * dumpfile.c (selftest::temp_dump_context::temp_dump_context):
3189 Don't construct a dump_context temporary to call static method.
3191 2020-04-15 Andrea Corallo <andrea.corallo@arm.com>
3193 * config/aarch64/falkor-tag-collision-avoidance.c
3194 (valid_src_p): Check for aarch64_address_info type before
3195 accessing base field.
3197 2020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
3199 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern.
3200 (V_sz_elem2): Remove unused mode attribute.
3202 2020-04-15 Matthew Malcomson <matthew.malcomson@arm.com>
3204 * config/arm/arm.md (arm_movdi): Disallow for MVE.
3206 2020-04-15 Richard Biener <rguenther@suse.de>
3209 * tree-ssa-alias.c (same_type_for_tbaa): Defer to
3210 alias_sets_conflict_p for pointers.
3212 2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
3215 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
3216 (extendhisi2_internal): Add %v1 before the load instructions.
3218 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
3221 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to
3222 use PC-relative addressing for TLS references.
3224 2020-04-14 Martin Jambor <mjambor@suse.cz>
3227 * ipa-sra.c: Include internal-fn.h.
3228 (enum isra_scan_context): Update comment.
3229 (scan_function): Treat calls to internal_functions like loads or stores.
3231 2020-04-14 Yang Yang <yangyang305@huawei.com>
3233 PR tree-optimization/94574
3234 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
3235 whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
3237 2020-04-14 H.J. Lu <hongjiu.lu@intel.com>
3240 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
3242 2020-04-13 Martin Sebor <msebor@redhat.com>
3244 * doc/extend.texi (-Wall): Mention -Wformat-overflow and
3245 -Wformat-truncation. Move -Wzero-length-bounds last.
3246 (-Wrestrict): Document positive form of option enabled by -Wall.
3248 2020-04-13 Zachary Spytz <zspytz@gmail.com>
3250 * doc/extend.texi: Add realloc to list of built-in functions
3251 are recognized by the compiler.
3253 2020-04-13 H.J. Lu <hongjiu.lu@intel.com>
3256 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
3257 pointer in word_mode for eh_return epilogues.
3259 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3261 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to
3262 memory references in %B, %C and %D operand selectors when the inner
3263 operand is a post increment address.
3265 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3267 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory
3268 reference by 4 bytes, and %D memory reference by 6 bytes.
3270 2020-04-11 Uroš Bizjak <ubizjak@gmail.com>
3273 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2
3274 condition for V4SI, V8HI and V16QI modes.
3276 2020-04-11 Jakub Jelinek <jakub@redhat.com>
3280 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on
3283 2020-04-10 Thomas Schwinge <thomas@codesourcery.com>
3287 * omp-general.c (oacc_verify_routine_clauses): Diagnose if
3288 "#pragma omp declare target" has also been applied.
3290 2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3292 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
3293 when to emit the epilogue_helper insn.
3294 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the
3297 2020-04-09 Jakub Jelinek <jakub@redhat.com>
3300 * cselib.h (cselib_record_sp_cfa_base_equiv,
3301 cselib_sp_derived_value_p): Declare.
3302 * cselib.c (cselib_record_sp_cfa_base_equiv,
3303 cselib_sp_derived_value_p): New functions.
3304 * var-tracking.c (add_stores): Don't record MO_VAL_SET for
3305 cselib_sp_derived_value_p values.
3306 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
3307 start of extended basic blocks other than the first one
3308 for !frame_pointer_needed functions.
3310 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3312 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
3313 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
3314 (aarch64_sve2048_hw): Document.
3315 * config/aarch64/aarch64-protos.h
3316 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
3317 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
3318 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
3319 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
3321 (find_type_suffix_for_scalar_type): Use it instead of comparing
3323 (function_resolver::infer_vector_or_tuple_type): Likewise.
3324 (function_resolver::require_vector_type): Likewise.
3325 (handle_arm_sve_vector_bits_attribute): New function.
3326 * config/aarch64/aarch64.c (pure_scalable_type_info): New class.
3327 (aarch64_attribute_table): Add arm_sve_vector_bits.
3328 (aarch64_return_in_memory_1):
3329 (pure_scalable_type_info::piece::get_rtx): New function.
3330 (pure_scalable_type_info::num_zr): Likewise.
3331 (pure_scalable_type_info::num_pr): Likewise.
3332 (pure_scalable_type_info::get_rtx): Likewise.
3333 (pure_scalable_type_info::analyze): Likewise.
3334 (pure_scalable_type_info::analyze_registers): Likewise.
3335 (pure_scalable_type_info::analyze_array): Likewise.
3336 (pure_scalable_type_info::analyze_record): Likewise.
3337 (pure_scalable_type_info::add_piece): Likewise.
3338 (aarch64_some_values_include_pst_objects_p): Likewise.
3339 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
3340 to analyze whether the type is returned in SVE registers.
3341 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
3342 is passed in SVE registers.
3343 (aarch64_pass_by_reference_1): New function, extracted from...
3344 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
3345 to analyze whether the type is a pure scalable type and, if so,
3346 whether it should be passed by reference.
3347 (aarch64_return_in_msb): Return false for pure scalable types.
3348 (aarch64_function_value_1): Fold back into...
3349 (aarch64_function_value): ...this function. Use
3350 pure_scalable_type_info to analyze whether the type is a pure
3351 scalable type and, if so, which registers it should use. Handle
3352 types that include pure scalable types but are not themselves
3353 pure scalable types.
3354 (aarch64_return_in_memory_1): New function, split out from...
3355 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info
3356 to analyze whether the type is a pure scalable type and, if so,
3357 whether it should be returned by reference.
3358 (aarch64_layout_arg): Remove orig_mode argument. Use
3359 pure_scalable_type_info to analyze whether the type is a pure
3360 scalable type and, if so, which registers it should use. Handle
3361 types that include pure scalable types but are not themselves
3362 pure scalable types.
3363 (aarch64_function_arg): Update call accordingly.
3364 (aarch64_function_arg_advance): Likewise.
3365 (aarch64_pad_reg_upward): On big-endian targets, return false for
3366 pure scalable types that are smaller than 16 bytes.
3367 (aarch64_member_type_forces_blk): New function.
3368 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
3369 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that
3370 correspond to built-in SVE types. Do not rely on a vector mode
3371 if the type includes an pure scalable type. When returning true,
3372 assert that the mode is not an SVE mode.
3373 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
3374 built-in types here. When returning true, assert that the type
3375 does not have an SVE mode.
3376 (aarch64_can_change_mode_class): Don't allow anything to change
3377 between a predicate mode and a non-predicate mode. Also don't
3378 allow changes between SVE vector modes and other modes that
3379 might be bigger than 128 bits.
3380 (aarch64_invalid_binary_op): Reject binary operations that mix
3381 SVE and GNU vector types.
3382 (TARGET_MEMBER_TYPE_FORCES_BLK): Define.
3384 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3386 * config/aarch64/aarch64.c (aarch64_attribute_table): Add
3387 "SVE sizeless type".
3388 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
3389 (sizeless_type_p): New functions.
3390 (register_builtin_types): Apply make_type_sizeless to the type.
3391 (register_tuple_type): Likewise.
3392 (verify_type_context): Use sizeless_type_p instead of builin_type_p.
3394 2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
3396 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for
3399 2020-04-09 Martin Jambor <mjambor@suse.cz>
3400 Richard Biener <rguenther@suse.de>
3402 PR tree-optimization/94482
3403 * tree-sra.c (create_access_replacement): Dump new replacement with
3405 (sra_modify_expr): Fix handling of cases when the original EXPR writes
3406 to only part of the replacement.
3407 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
3408 the first operand of combinations into REAL/IMAGPART_EXPR and
3411 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3413 * doc/sourcebuild.texi (check-function-bodies): Treat the third
3414 parameter as a list of option regexps and require each regexp
3417 2020-04-09 Andrea Corallo <andrea.corallo@arm.com>
3420 * config/aarch64/falkor-tag-collision-avoidance.c
3421 (valid_src_p): Fix missing rtx type check.
3423 2020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com>
3424 Richard Biener <rguenther@suse.de>
3426 PR tree-optimization/93674
3427 * tree-ssa-loop-ivopts.c (langhooks.h): New include.
3428 (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
3429 or non-mode precision type, add candidate in unsigned type with the
3432 2020-04-08 Clement Chigot <clement.chigot@atos.net>
3434 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128.
3435 * config/rs6000/aix71.h (LIB_SPEC): Likewise.
3436 * config/rs6000/aix72.h (LIB_SPEC): Likewise.
3438 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3441 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
3443 * reload1.c (eliminate_regs_1): Avoid creating
3444 (plus (reg) (const_int 0)) in DEBUG_INSNs.
3446 PR tree-optimization/94524
3447 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
3448 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
3449 op1 rather than op1 itself at the end. Punt for signed modulo by
3450 most negative constant.
3451 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
3452 modulo by most negative constant.
3454 2020-04-08 Richard Biener <rguenther@suse.de>
3456 PR rtl-optimization/93946
3457 * cse.c (cse_insn): Record the tabled expression in
3458 src_related. Verify a redundant store removal is valid.
3460 2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
3463 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert
3464 ENDBR at function entry if function will be called indirectly.
3466 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3469 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
3472 2020-04-08 Martin Liska <mliska@suse.cz>
3475 * gimple.c (gimple_call_operator_delete_p): Rename to...
3476 (gimple_call_replaceable_operator_delete_p): ... this.
3477 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3478 * gimple.h (gimple_call_operator_delete_p): Rename to ...
3479 (gimple_call_replaceable_operator_delete_p): ... this.
3480 * tree-core.h (tree_function_decl): Add replaceable_operator
3482 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
3483 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3484 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
3485 (eliminate_unnecessary_stmts): Likewise.
3486 * tree-streamer-in.c (unpack_ts_function_decl_value_fields):
3487 Pack DECL_IS_REPLACEABLE_OPERATOR.
3488 * tree-streamer-out.c (pack_ts_function_decl_value_fields):
3489 Unpack the field here.
3490 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
3491 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
3492 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
3493 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
3494 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
3495 replaceable operator flags.
3497 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3498 Matthew Malcomson <matthew.malcomson@arm.com>
3500 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
3501 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
3502 (CX_TERNARY_QUALIFIERS): Likewise.
3503 (ARM_BUILTIN_CDE_PATTERN_START): Likewise.
3504 (ARM_BUILTIN_CDE_PATTERN_END): Likewise.
3505 (arm_init_acle_builtins): Initialize CDE builtins.
3506 (arm_expand_acle_builtin): Check CDE constant operands.
3507 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
3508 of CDE constant operand.
3509 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
3511 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
3512 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
3513 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
3514 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
3515 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
3516 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
3517 * config/arm/arm_cde_builtins.def: New file.
3518 * config/arm/iterators.md (V_reg): New attribute of SI.
3519 * config/arm/predicates.md (const_int_coproc_operand): New.
3520 (const_int_vcde1_operand, const_int_vcde2_operand): New.
3521 (const_int_vcde3_operand): New.
3522 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
3523 * config/arm/vfp.md (arm_vcx1<mode>): New entry.
3524 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
3525 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
3527 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3529 * config.gcc: Add arm_cde.h.
3530 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
3531 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
3532 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
3533 * config/arm/arm.c (arm_option_reconfigure_globals): Configure
3534 arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
3535 * config/arm/arm.h (TARGET_CDE): New macro.
3536 * config/arm/arm_cde.h: New file.
3537 * doc/invoke.texi: Document CDE options +cdecp[0-7].
3538 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
3540 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
3542 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3544 PR rtl-optimization/94516
3545 * postreload.c: Include rtl-iter.h.
3546 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
3547 looking for all MEMs with RTX_AUTOINC operand.
3548 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
3550 2020-04-08 Tobias Burnus <tobias@codesourcery.com>
3552 * omp-grid.c (grid_eliminate_combined_simd_part): Use
3553 OMP_CLAUSE_CODE to access the omp clause code.
3555 2020-04-07 Jeff Law <law@redhat.com>
3557 PR rtl-optimization/92264
3558 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when
3559 the destination is the stack pointer.
3561 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3563 PR rtl-optimization/94291
3564 PR rtl-optimization/84169
3565 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST
3566 must be a REG or SUBREG of REG; if it is not one of these, don't
3569 2020-04-07 Richard Biener <rguenther@suse.de>
3572 * gimplify.c (gimplify_addr_expr): Also consider generated
3575 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3577 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
3579 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3581 * config/arm/arm_mve.h: Cast some pointers to expected types.
3583 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3585 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
3586 same with '__arm_' prefix.
3588 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3590 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
3592 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3594 * config/arm/arm.c (arm_mve_immediate_check): Removed.
3595 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
3596 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
3597 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
3598 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
3599 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
3600 mve_vqshruntq_m_n_s*): Fixed immediate constraints.
3602 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3604 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
3606 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3608 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
3609 * config/arm/mve/md: Fix v[id]wdup patterns.
3611 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3613 * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
3614 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
3616 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3618 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
3619 and remove const_ptr enums.
3621 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3623 * config/arm/arm_mve.h (vsubq_n): Merge with...
3625 (vmulq_n): Merge with...
3627 (__ARM_mve_typeid): Simplify scalar and constant detection.
3629 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3632 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
3633 for inter-lane permutation for 64-byte modes.
3636 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
3637 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
3638 Assume it is a REG after that instead of testing it and doing FAIL
3639 otherwise. Formatting fix.
3641 2020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
3643 * config/rs6000/t-rtems: Delete mcpu=8540 multilib.
3645 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3648 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
3649 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
3651 2020-04-06 Jakub Jelinek <jakub@redhat.com>
3653 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
3654 + const0_rtx return the SP_DERIVED_VALUE_P.
3656 2020-04-06 Richard Sandiford <richard.sandiford@arm.com>
3658 PR rtl-optimization/92989
3659 * lra-lives.c (process_bb_lives): Do not treat eh_return data
3660 registers as being live at the beginning of the EH receiver.
3662 2020-04-05 Zachary Spytz <zspytz@gmail.com>
3664 * extend.texi: Add free to list of ISO C90 functions that
3665 are recognized by the compiler.
3667 2020-04-05 Nagaraju Mekala <nmekala@xilix.com>
3669 * config/microblaze/microblaze.c (microblaze_must_save_register): Check
3672 * config/microblaze/microblaze.md (trap): Update output pattern.
3674 2020-04-04 Hannes Domani <ssbssa@yahoo.de>
3675 Jakub Jelinek <jakub@redhat.com>
3678 * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
3679 arrays, pointer-to-members, function types and qualifiers when
3680 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
3681 to emit type again on definition.
3683 2020-04-04 Jan Hubicka <hubicka@ucw.cz>
3686 * ipa-fnsummary.c (vrp_will_run_p): New function.
3687 (fre_will_run_p): New function.
3688 (evaluate_properties_for_edge): Use it.
3689 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
3690 !optimize_debug to optimize_debug.
3692 2020-04-04 Jakub Jelinek <jakub@redhat.com>
3694 PR rtl-optimization/94468
3695 * cselib.c (references_value_p): Formatting fix.
3696 (cselib_useless_value_p): New function.
3697 (discard_useless_locs, discard_useless_values,
3698 cselib_invalidate_regno_val, cselib_invalidate_mem,
3699 cselib_record_set): Use it instead of
3700 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).
3703 * tree-iterator.h (expr_single): Declare.
3704 * tree-iterator.c (expr_single): New function.
3705 * tree.h (protected_set_expr_location_if_unset): Declare.
3706 * tree.c (protected_set_expr_location): Use expr_single.
3707 (protected_set_expr_location_if_unset): New function.
3709 2020-04-03 Jeff Law <law@redhat.com>
3711 PR rtl-optimization/92264
3712 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
3713 reloading of auto-increment addressing modes.
3715 2020-04-03 H.J. Lu <hongjiu.lu@intel.com>
3718 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
3721 2020-04-03 Jeff Law <law@redhat.com>
3723 PR rtl-optimization/92264
3724 * config/m32r/m32r.c (m32r_output_block_move): Properly account for
3725 post-increment addressing of source operands as well as residuals
3726 when computing any adjustments to the input pointer.
3728 2020-04-03 Jakub Jelinek <jakub@redhat.com>
3731 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
3732 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
3733 second half of first lane from first lane of second operand and
3734 first half of second lane from second lane of first operand.
3736 2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
3738 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.
3740 2020-04-03 Tamar Christina <tamar.christina@arm.com>
3743 * common/config/aarch64/aarch64-common.c
3744 (aarch64_get_extension_string_for_isa_flags): Handle default flags.
3746 2020-04-03 Richard Biener <rguenther@suse.de>
3749 * tree.c (array_ref_low_bound): Deal with released SSA names
3752 2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>
3754 * config/gcn/gcn.c (print_operand): Handle unordered comparison
3756 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
3757 comparison operators.
3759 2020-04-03 Kewen Lin <linkw@gcc.gnu.org>
3761 PR tree-optimization/94443
3762 * tree-vect-loop.c (vectorizable_live_operation): Use
3763 gsi_insert_seq_before to replace gsi_insert_before.
3765 2020-04-03 Martin Liska <mliska@suse.cz>
3768 * ipa-icf-gimple.c (func_checker::compare_gimple_call):
3769 Compare type attributes for gimple_call_fntypes.
3771 2020-04-02 Sandra Loosemore <sandra@codesourcery.com>
3773 * alias.c (get_alias_set): Fix comment typos.
3775 2020-04-02 Fritz Reese <foreese@gcc.gnu.org>
3778 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
3779 attribute checking used by TYPE.
3781 2020-04-02 Martin Jambor <mjambor@suse.cz>
3784 * ipa-sra.c (struct caller_issues): New fields candidate and
3785 call_from_outside_comdat.
3786 (check_for_caller_issues): Check for calls from outsied of
3787 candidate's same_comdat_group.
3788 (check_all_callers_for_issues): Set up issues.candidate, check result
3790 (mark_callers_calls_comdat_local): New function.
3791 (process_isra_node_results): Set calls_comdat_local of callers if
3794 2020-04-02 Richard Biener <rguenther@suse.de>
3797 * common.opt (ffinite-loops): Initialize to zero.
3798 * opts.c (default_options_table): Remove OPT_ffinite_loops
3800 * cfgloop.h (loop::finite_p): New member.
3801 * cfgloopmanip.c (copy_loop_info): Copy finite_p.
3802 * ipa-icf-gimple.c (func_checker::compare_loops): Compare
3804 * lto-streamer-in.c (input_cfg): Stream finite_p.
3805 * lto-streamer-out.c (output_cfg): Likewise.
3806 * tree-cfg.c (replace_loop_annotate): Initialize finite_p
3807 from flag_finite_loops at CFG build time.
3808 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops
3809 finite_p flag instead of flag_finite_loops.
3810 * doc/invoke.texi (ffinite-loops): Adjust documentation of
3813 2020-04-02 Richard Biener <rguenther@suse.de>
3816 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting
3817 DW_TAG_imported_unit.
3819 2020-04-02 Maciej W. Rozycki <macro@wdc.com>
3821 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
3822 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
3825 2020-04-02 Kewen Lin <linkw@gcc.gnu.org>
3827 PR tree-optimization/94401
3828 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
3829 access type when loading halves of vector to avoid peeling for gaps.
3831 2020-04-02 Jakub Jelinek <jakub@redhat.com>
3833 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
3834 between a string literal and MIPS_SYSVERSION_SPEC macro.
3836 2020-04-02 Martin Jambor <mjambor@suse.cz>
3838 * doc/invoke.texi (Optimize Options): Document sra-max-propagations.
3840 2020-04-02 Jakub Jelinek <jakub@redhat.com>
3842 PR rtl-optimization/92264
3843 * params.opt (-param=max-find-base-term-values=): Decrease default
3846 PR rtl-optimization/92264
3847 * rtl.h (struct rtx_def): Mention that call bit is used as
3848 SP_DERIVED_VALUE_P in cselib.c.
3849 * cselib.c (SP_DERIVED_VALUE_P): Define.
3850 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
3851 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
3852 val_rtx and sp based expression where offsets cancel each other.
3853 (preserve_constants_and_equivs): Formatting fix.
3854 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
3855 locs list for cfa_base_preserved_val if needed. Formatting fix.
3856 (autoinc_split): If the to be returned value is a REG, MEM or
3857 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
3858 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
3859 (rtx_equal_for_cselib_1): Call autoinc_split even if both
3860 expressions are PLUS in Pmode with CONST_INT second operands.
3861 Handle SP_DERIVED_VALUE_P cases.
3862 (cselib_hash_plus_const_int): New function.
3863 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
3864 second operand, as well as for PRE_DEC etc. that ought to be
3865 hashed the same way.
3866 (cselib_subst_to_values): Substitute PLUS with Pmode and
3867 CONST_INT operand if the first operand is a VALUE which has
3868 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
3869 SP_DERIVED_VALUE_P + adjusted offset.
3870 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
3871 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding
3872 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
3873 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
3874 on the sp value before calling cselib_add_permanent_equiv on the
3876 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
3877 in the insn without REG_INC note.
3878 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
3879 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes.
3882 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
3883 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
3885 2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3888 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
3889 (LDRGBWBXU_Z_QUALIFIERS): Likewise.
3890 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
3891 intrinsic defintion by adding a new builtin call to writeback into base
3893 (__arm_vldrdq_gather_base_wb_u64): Likewise.
3894 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
3895 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
3896 (__arm_vldrwq_gather_base_wb_s32): Likewise.
3897 (__arm_vldrwq_gather_base_wb_u32): Likewise.
3898 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
3899 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
3900 (__arm_vldrwq_gather_base_wb_f32): Likewise.
3901 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
3902 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
3903 builtin's qualifier.
3904 (vldrdq_gather_base_wb_z_u): Likewise.
3905 (vldrwq_gather_base_wb_u): Likewise.
3906 (vldrdq_gather_base_wb_u): Likewise.
3907 (vldrwq_gather_base_wb_z_s): Likewise.
3908 (vldrwq_gather_base_wb_z_f): Likewise.
3909 (vldrdq_gather_base_wb_z_s): Likewise.
3910 (vldrwq_gather_base_wb_s): Likewise.
3911 (vldrwq_gather_base_wb_f): Likewise.
3912 (vldrdq_gather_base_wb_s): Likewise.
3913 (vldrwq_gather_base_nowb_z_u): Define builtin.
3914 (vldrdq_gather_base_nowb_z_u): Likewise.
3915 (vldrwq_gather_base_nowb_u): Likewise.
3916 (vldrdq_gather_base_nowb_u): Likewise.
3917 (vldrwq_gather_base_nowb_z_s): Likewise.
3918 (vldrwq_gather_base_nowb_z_f): Likewise.
3919 (vldrdq_gather_base_nowb_z_s): Likewise.
3920 (vldrwq_gather_base_nowb_s): Likewise.
3921 (vldrwq_gather_base_nowb_f): Likewise.
3922 (vldrdq_gather_base_nowb_s): Likewise.
3923 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
3925 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
3926 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
3927 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
3928 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
3929 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
3930 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
3931 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
3932 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
3933 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
3934 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
3935 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
3937 2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
3939 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
3940 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
3941 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
3942 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
3943 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
3944 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
3945 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
3946 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
3947 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
3949 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
3950 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
3951 Remove constraints from expander.
3952 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
3953 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
3954 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
3955 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
3956 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
3957 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
3959 2020-04-01 Peter Bergner <bergner@linux.ibm.com>
3961 PR rtl-optimization/94123
3962 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for
3963 flag_split_wide_types_early.
3965 2020-04-01 Joerg Sonnenberger <joerg@bec.de>
3967 * doc/extend.texi (Common Function Attributes): Fix typo.
3969 2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
3972 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
3975 2020-04-01 Zackery Spytz <zspytz@gmail.com>
3977 * doc/extend.texi: Fix a typo in the documentation of the
3978 copy function attribute.
3980 2020-04-01 Jakub Jelinek <jakub@redhat.com>
3983 * tree-object-size.c (pass_object_sizes::execute): Don't call
3984 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
3985 call replace_call_with_value.
3987 2020-04-01 Kewen Lin <linkw@gcc.gnu.org>
3989 PR tree-optimization/94043
3990 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
3991 phi for vec_lhs and use it for lane extraction.
3993 2020-03-31 Felix Yang <felix.yang@huawei.com>
3995 PR tree-optimization/94398
3996 * tree-vect-stmts.c (vectorizable_store): Instead of calling
3997 vect_supportable_dr_alignment, set alignment_support_scheme to
3998 dr_unaligned_supported for gather-scatter accesses.
3999 (vectorizable_load): Likewise.
4001 2020-03-31 Andrew Stubbs <ams@codesourcery.com>
4003 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
4005 (vnsi, VnSI, vndi, VnDI): New mode attributes.
4006 (mov<mode>): Use <VnDI> in place of V64DI.
4007 (mov<mode>_exec): Likewise.
4008 (mov<mode>_sgprbase): Likewise.
4009 (reload_out<mode>): Likewise.
4010 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
4011 (gather_load<mode>v64si): Rename to ...
4012 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
4013 and <VnDI> in place of V64DI.
4014 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
4015 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
4016 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
4017 (scatter_store<mode>v64si): Rename to ...
4018 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4019 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
4020 (scatter<mode>_insn_1offset<exec_scatter>): Likewise.
4021 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
4022 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
4023 (ds_bpermute<mode>): Use <VnSI>.
4024 (addv64si3_vcc<exec_vcc>): Rename to ...
4025 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
4026 (addv64si3_vcc_dup<exec_vcc>): Rename to ...
4027 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
4028 (addcv64si3<exec_vcc>): Rename to ...
4029 (addc<mode>3<exec_vcc>): ... this, and use V_SI.
4030 (subv64si3_vcc<exec_vcc>): Rename to ...
4031 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
4032 (subcv64si3<exec_vcc>): Rename to ...
4033 (subc<mode>3<exec_vcc>): ... this, and use V_SI.
4034 (addv64di3): Rename to ...
4035 (add<mode>3): ... this, and use V_DI.
4036 (addv64di3_exec): Rename to ...
4037 (add<mode>3_exec): ... this, and use V_DI.
4038 (subv64di3): Rename to ...
4039 (sub<mode>3): ... this, and use V_DI.
4040 (subv64di3_exec): Rename to ...
4041 (sub<mode>3_exec): ... this, and use V_DI.
4042 (addv64di3_zext): Rename to ...
4043 (add<mode>3_zext): ... this, and use V_DI and <VnSI>.
4044 (addv64di3_zext_exec): Rename to ...
4045 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
4046 (addv64di3_zext_dup): Rename to ...
4047 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
4048 (addv64di3_zext_dup_exec): Rename to ...
4049 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
4050 (addv64di3_zext_dup2): Rename to ...
4051 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
4052 (addv64di3_zext_dup2_exec): Rename to ...
4053 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
4054 (addv64di3_sext_dup2): Rename to ...
4055 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
4056 (addv64di3_sext_dup2_exec): Rename to ...
4057 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
4058 (<su>mulv64si3_highpart<exec>): Rename to ...
4059 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
4060 (mulv64di3): Rename to ...
4061 (mul<mode>3): ... this, and use V_DI and <VnSI>.
4062 (mulv64di3_exec): Rename to ...
4063 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
4064 (mulv64di3_zext): Rename to ...
4065 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
4066 (mulv64di3_zext_exec): Rename to ...
4067 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
4068 (mulv64di3_zext_dup2): Rename to ...
4069 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
4070 (mulv64di3_zext_dup2_exec): Rename to ...
4071 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
4072 (<expander>v64di3): Rename to ...
4073 (<expander><mode>3): ... this, and use V_DI and <VnSI>.
4074 (<expander>v64di3_exec): Rename to ...
4075 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
4076 (<expander>v64si3<exec>): Rename to ...
4077 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
4078 (v<expander>v64si3<exec>): Rename to ...
4079 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
4080 (<expander>v64si3<exec>): Rename to ...
4081 (<expander><vnsi>3<exec>): ... this, and use V_SI.
4082 (subv64df3<exec>): Rename to ...
4083 (sub<mode>3<exec>): ... this, and use V_DF.
4084 (truncv64di<mode>2): Rename to ...
4085 (trunc<vndi><mode>2): ... this, and use <VnDI>.
4086 (truncv64di<mode>2_exec): Rename to ...
4087 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
4088 (<convop><mode>v64di2): Rename to ...
4089 (<convop><mode><vndi>2): ... this, and use <VnDI>.
4090 (<convop><mode>v64di2_exec): Rename to ...
4091 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
4092 (vec_cmp<u>v64qidi): Rename to ...
4093 (vec_cmp<u><mode>di): ... this, and use <VnSI>.
4094 (vec_cmp<u>v64qidi_exec): Rename to ...
4095 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
4096 (vcond_mask_<mode>di): Use <VnDI>.
4097 (maskload<mode>di): Likewise.
4098 (maskstore<mode>di): Likewise.
4099 (mask_gather_load<mode>v64si): Rename to ...
4100 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4101 (mask_scatter_store<mode>v64si): Rename to ...
4102 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4103 (*<reduc_op>_dpp_shr_v64di): Rename to ...
4104 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
4105 (*plus_carry_in_dpp_shr_v64si): Rename to ...
4106 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
4107 (*plus_carry_dpp_shr_v64di): Rename to ...
4108 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
4109 (vec_seriesv64si): Rename to ...
4110 (vec_series<mode>): ... this, and use V_SI.
4111 (vec_seriesv64di): Rename to ...
4112 (vec_series<mode>): ... this, and use V_DI.
4114 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
4116 * config/arc/arc.c (arc_print_operand): Use
4117 HOST_WIDE_INT_PRINT_DEC macro.
4119 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
4121 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
4123 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4125 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
4127 (__arm_vbicq): Likewise.
4129 2020-03-31 Vineet Gupta <vgupta@synopsys.com>
4131 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
4133 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4135 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
4136 common section of both MVE Integer and MVE Floating Point.
4138 (vaddlvq_p): Likewise.
4139 (vaddvaq): Likewise.
4140 (vaddvq_p): Likewise.
4141 (vcmpcsq): Likewise.
4142 (vmlsdavxq): Likewise.
4143 (vmlsdavq): Likewise.
4144 (vmladavxq): Likewise.
4145 (vmladavq): Likewise.
4147 (vminavq): Likewise.
4149 (vmaxavq): Likewise.
4150 (vmlaldavq): Likewise.
4151 (vcmphiq): Likewise.
4152 (vaddlvaq): Likewise.
4153 (vrmlaldavhq): Likewise.
4154 (vrmlaldavhxq): Likewise.
4155 (vrmlsldavhq): Likewise.
4156 (vrmlsldavhxq): Likewise.
4157 (vmlsldavxq): Likewise.
4158 (vmlsldavq): Likewise.
4160 (vrmlaldavhaq): Likewise.
4161 (vcmpgeq_m_n): Likewise.
4162 (vmlsdavxq_p): Likewise.
4163 (vmlsdavq_p): Likewise.
4164 (vmlsdavaxq): Likewise.
4165 (vmlsdavaq): Likewise.
4166 (vaddvaq_p): Likewise.
4167 (vcmpcsq_m_n): Likewise.
4168 (vcmpcsq_m): Likewise.
4169 (vmladavxq_p): Likewise.
4170 (vmladavq_p): Likewise.
4171 (vmladavaxq): Likewise.
4172 (vmladavaq): Likewise.
4173 (vminvq_p): Likewise.
4174 (vminavq_p): Likewise.
4175 (vmaxvq_p): Likewise.
4176 (vmaxavq_p): Likewise.
4177 (vcmphiq_m): Likewise.
4178 (vaddlvaq_p): Likewise.
4179 (vmlaldavaq): Likewise.
4180 (vmlaldavaxq): Likewise.
4181 (vmlaldavq_p): Likewise.
4182 (vmlaldavxq_p): Likewise.
4183 (vmlsldavaq): Likewise.
4184 (vmlsldavaxq): Likewise.
4185 (vmlsldavq_p): Likewise.
4186 (vmlsldavxq_p): Likewise.
4187 (vrmlaldavhaxq): Likewise.
4188 (vrmlaldavhq_p): Likewise.
4189 (vrmlaldavhxq_p): Likewise.
4190 (vrmlsldavhaq): Likewise.
4191 (vrmlsldavhaxq): Likewise.
4192 (vrmlsldavhq_p): Likewise.
4193 (vrmlsldavhxq_p): Likewise.
4194 (vabavq_p): Likewise.
4195 (vmladavaq_p): Likewise.
4196 (vstrbq_scatter_offset): Likewise.
4197 (vstrbq_p): Likewise.
4198 (vstrbq_scatter_offset_p): Likewise.
4199 (vstrdq_scatter_base_p): Likewise.
4200 (vstrdq_scatter_base): Likewise.
4201 (vstrdq_scatter_offset_p): Likewise.
4202 (vstrdq_scatter_offset): Likewise.
4203 (vstrdq_scatter_shifted_offset_p): Likewise.
4204 (vstrdq_scatter_shifted_offset): Likewise.
4205 (vmaxq_x): Likewise.
4206 (vminq_x): Likewise.
4207 (vmovlbq_x): Likewise.
4208 (vmovltq_x): Likewise.
4209 (vmulhq_x): Likewise.
4210 (vmullbq_int_x): Likewise.
4211 (vmullbq_poly_x): Likewise.
4212 (vmulltq_int_x): Likewise.
4213 (vmulltq_poly_x): Likewise.
4216 2020-03-31 Jakub Jelinek <jakub@redhat.com>
4219 * config/aarch64/constraints.md (Uph): New constraint.
4220 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
4221 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
4224 2020-03-31 Marc Glisse <marc.glisse@inria.fr>
4225 Jakub Jelinek <jakub@redhat.com>
4228 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
4229 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
4231 2020-03-31 Jakub Jelinek <jakub@redhat.com>
4233 PR tree-optimization/94403
4234 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
4235 ENUMERAL_TYPE lhs_type.
4237 PR rtl-optimization/94344
4238 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
4239 conversions, either on both operands of |^+ or just one. Handle
4240 also extra same precision conversion on RSHIFT_EXPR first operand
4241 provided RSHIFT_EXPR is performed in unsigned type.
4243 2020-03-30 David Malcolm <dmalcolm@redhat.com>
4245 * lra.c (finish_insn_code_data_once): Set the array elements
4246 to NULL after freeing them.
4248 2020-03-30 Andreas Schwab <schwab@suse.de>
4250 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
4253 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
4255 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
4256 to skip defining builtins based on builtin_mask.
4258 2020-03-30 Jakub Jelinek <jakub@redhat.com>
4261 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
4262 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
4263 operand is a register. Don't enable masked variants for V*[QH]Imode.
4266 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
4267 <store_mask_constraint> instead of m in output operand constraint.
4268 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
4271 2020-03-30 Alan Modra <amodra@gmail.com>
4273 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
4274 (rs6000_indirect_call_template_1): Adjust to suit.
4275 * config/rs6000/rs6000.md (call_local): Merge call_local32,
4276 call_local64, and call_local_aix.
4277 (call_value_local): Simlarly.
4278 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
4279 and disable pattern when CALL_LONG.
4280 (call_indirect_aix, call_value_indirect_aix): Adjust rtl.
4281 (call_indirect_elfv2, call_indirect_pcrel): Likewise.
4282 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
4284 2020-03-29 H.J. Lu <hongjiu.lu@intel.com>
4287 * doc/invoke.texi: Update -falign-functions, -falign-loops and
4288 -falign-jumps documentation.
4290 2020-03-29 Martin Liska <mliska@suse.cz>
4293 * cgraphunit.c (process_function_and_variable_attributes): Remove
4294 double 'attribute' words.
4296 2020-03-29 John David Anglin <dave.anglin@bell.net>
4298 * config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
4301 2020-03-28 Jakub Jelinek <jakub@redhat.com>
4304 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const
4305 to true after setting size to integer_one_node.
4307 PR tree-optimization/94329
4308 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
4309 on the last stmt in a bb, make sure gsi_prev isn't done immediately
4312 2020-03-27 Alan Modra <amodra@gmail.com>
4315 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
4316 for PLT16_LO and PLT_PCREL.
4317 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
4318 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
4319 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
4321 2020-03-27 Martin Sebor <msebor@redhat.com>
4324 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes.
4326 2020-03-27 Andrew Stubbs <ams@codesourcery.com>
4328 * config/gcn/gcn-valu.md:
4329 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
4330 (VEC_1REG_MODE): Delete.
4331 (VEC_1REG_ALT): Delete.
4332 (VEC_ALL1REG_MODE): Rename to V_1REG throughout.
4333 (VEC_1REG_INT_MODE): Delete.
4334 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
4335 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
4336 (VEC_2REG_MODE): Rename to V_2REG throughout.
4337 (VEC_REG_MODE): Rename to V_noHI throughout.
4338 (VEC_ALLREG_MODE): Rename to V_ALL throughout.
4339 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout.
4340 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
4341 (VEC_INT_MODE): Delete.
4342 (VEC_FP_MODE): Rename to V_FP throughout and move to top.
4343 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
4344 (FP_MODE): Delete and replace with FP throughout.
4345 (FP_1REG_MODE): Delete and replace with FP_1REG throughout.
4346 (VCMP_MODE): Rename to V_noQI throughout and move to top.
4347 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
4348 * config/gcn/gcn.md (FP): New mode iterator.
4349 (FP_1REG): New mode iterator.
4351 2020-03-27 David Malcolm <dmalcolm@redhat.com>
4353 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this
4354 now emits two .dot files.
4355 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD.
4356 (graphviz_out::end_tr): Only close a TR, not a TD.
4357 (graphviz_out::begin_td): New.
4358 (graphviz_out::end_td): New.
4359 (graphviz_out::begin_trtd): New, replacing the old implementation
4360 of graphviz_out::begin_tr.
4361 (graphviz_out::end_tdtr): New, replacing the old implementation
4362 of graphviz_out::end_tr.
4363 * graphviz.h (graphviz_out::begin_td): New decl.
4364 (graphviz_out::end_td): New decl.
4365 (graphviz_out::begin_trtd): New decl.
4366 (graphviz_out::end_tdtr): New decl.
4368 2020-03-27 Richard Biener <rguenther@suse.de>
4371 * dwarf2out.c (should_emit_struct_debug): Return false for
4374 2020-03-27 Richard Biener <rguenther@suse.de>
4376 PR tree-optimization/94352
4377 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the
4379 (ssa_propagation_engine::ssa_propagate): ... here after
4380 initializing curr_order.
4382 2020-03-27 Kewen Lin <linkw@gcc.gnu.org>
4384 PR tree-optimization/90332
4385 * tree-vect-stmts.c (vector_vector_composition_type): New function.
4386 (get_group_load_store_type): Adjust to call
4387 vector_vector_composition_type, extend it to construct with scalar
4389 (vectorizable_load): Likewise.
4391 2020-03-27 Roman Zhuykov <zhroma@ispras.ru>
4393 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions.
4394 (create_ddg_dep_no_link): Likewise.
4395 (add_cross_iteration_register_deps): Move debug instruction check.
4396 Other minor refactoring.
4397 (add_intra_loop_mem_dep): Do not check for debug instructions.
4398 (add_inter_loop_mem_dep): Likewise.
4399 (build_intra_loop_deps): Likewise.
4400 (create_ddg): Do not include debug insns into the graph.
4401 * ddg.h (struct ddg): Remove num_debug field.
4402 * modulo-sched.c (doloop_register_get): Adjust condition.
4403 (res_MII): Remove DDG num_debug field usage.
4404 (sms_schedule_by_order): Use assertion against debug insns.
4405 (ps_has_conflicts): Drop debug insn check.
4407 2020-03-26 Jakub Jelinek <jakub@redhat.com>
4410 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST
4411 that contains exactly one non-DEBUG_BEGIN_STMT statement.
4414 * gimple.h (gimple_seq_first_nondebug_stmt): New function.
4415 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains
4416 a single non-debug stmt followed by one or more debug stmts.
4417 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt
4418 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt
4419 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and
4420 gimple_seq_last to check if outer_stmt gbind could be reused and
4421 if yes and it is surrounded by any debug stmts, move them into the
4424 PR rtl-optimization/92264
4425 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even
4426 for sp based values in !frame_pointer_needed
4427 && !ACCUMULATE_OUTGOING_ARGS functions.
4429 2020-03-26 Felix Yang <felix.yang@huawei.com>
4431 PR tree-optimization/94269
4432 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict
4434 operation to single basic block.
4436 2020-03-25 Jeff Law <law@redhat.com>
4438 PR rtl-optimization/90275
4439 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
4442 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4445 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to
4446 mode rather than VOIDmode.
4448 2020-03-25 Martin Sebor <msebor@redhat.com>
4451 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings
4452 even for alloca calls resulting from system macro expansion.
4453 Include inlining context in all warnings.
4455 2020-03-25 Richard Sandiford <richard.sandiford@arm.com>
4458 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
4459 FPRs to change between SDmode and DDmode.
4461 2020-03-25 Martin Sebor <msebor@redhat.com>
4463 PR tree-optimization/94131
4464 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length
4466 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming
4467 types have constant sizes.
4469 2020-03-25 Martin Liska <mliska@suse.cz>
4472 * configure.ac: Report error only when --with-zstd
4474 * configure: Regenerate.
4476 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4479 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
4480 INSN_CODE (insn) to -1 when changing the pattern.
4482 2020-03-25 Martin Liska <mliska@suse.cz>
4486 * config/i386/i386-features.c (make_resolver_func): Drop
4487 public flag for resolver.
4488 * config/rs6000/rs6000.c (make_resolver_func): Add comdat
4489 group for resolver and drop public flag if possible.
4490 * multiple_target.c (create_dispatcher_calls): Drop unique_name
4491 and resolution as we want to enable LTO privatization of the default
4494 2020-03-25 Martin Liska <mliska@suse.cz>
4497 * configure.ac: Respect --without-zstd and report
4498 error when we can't find header file with --with-zstd.
4499 * configure: Regenerate.
4501 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4504 * varasm.c (output_constructor_array_range): If local->index
4505 RANGE_EXPR doesn't start at the current location in the constructor,
4506 skip needed number of bytes using assemble_zeros or assert we don't
4510 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong
4511 counter instead of DECL_UID.
4513 PR tree-optimization/94300
4514 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset
4515 is positive, make sure that off + size isn't larger than needed_len.
4517 2020-03-25 Richard Biener <rguenther@suse.de>
4518 Jakub Jelinek <jakub@redhat.com>
4521 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
4523 2020-03-24 Christophe Lyon <christophe.lyon@linaro.org>
4525 * doc/sourcebuild.texi (ARM-specific attributes): Add
4527 (Features for dg-add-options): Add arm_fp_dp.
4529 2020-03-24 John David Anglin <danglin@gcc.gnu.org>
4532 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
4534 2020-03-24 Tobias Burnus <tobias@codesourcery.com>
4537 * omp-offload.c (omp_finish_file): Fix target-link handling if
4538 targetm_common.have_named_sections is false.
4540 2020-03-24 Jakub Jelinek <jakub@redhat.com>
4543 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
4547 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
4548 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.
4549 If not after and at *incr_pos is a debug stmt, set stmt location to
4550 location of next non-debug stmt after it if any.
4553 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
4554 GF_PLF_2, but don't add them to worklist. Don't add an assigment to
4555 worklist or set GF_PLF_2 just because it is used in a debug stmt in
4556 another bb. Formatting improvements.
4559 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and
4560 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC
4561 regardless of whether TREE_NO_WARNING is set on it or whether
4562 warn_unused_function is true or not.
4564 2020-03-23 Jeff Law <law@redhat.com>
4566 PR rtl-optimization/90275
4569 * simplify-rtx.c (comparison_code_valid_for_mode): New function.
4570 (simplify_logical_relational_operation): Use it.
4572 2020-03-23 Jakub Jelinek <jakub@redhat.com>
4575 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on
4576 ultimate rhs and if returned something different, reconstructing
4579 2020-03-23 Lewis Hyatt <lhyatt@gmail.com>
4581 * opts.c (print_filtered_help): Improve the help text for alias options.
4583 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4584 Andre Vieira <andre.simoesdiasvieira@arm.com>
4585 Mihail Ionescu <mihail.ionescu@arm.com>
4587 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
4588 (vshlcq_m_u8): Likewise.
4589 (vshlcq_m_s16): Likewise.
4590 (vshlcq_m_u16): Likewise.
4591 (vshlcq_m_s32): Likewise.
4592 (vshlcq_m_u32): Likewise.
4593 (__arm_vshlcq_m_s8): Define intrinsic.
4594 (__arm_vshlcq_m_u8): Likewise.
4595 (__arm_vshlcq_m_s16): Likewise.
4596 (__arm_vshlcq_m_u16): Likewise.
4597 (__arm_vshlcq_m_s32): Likewise.
4598 (__arm_vshlcq_m_u32): Likewise.
4599 (vshlcq_m): Define polymorphic variant.
4600 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
4601 Use builtin qualifier.
4602 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
4603 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern.
4604 (mve_vshlcq_m_carry_<supf><mode>): Likewise.
4605 (mve_vshlcq_m_<supf><mode>): Likewise.
4607 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4609 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
4610 (UQSHL_QUALIFIERS): Likewise.
4611 (ASRL_QUALIFIERS): Likewise.
4612 (SQSHL_QUALIFIERS): Likewise.
4613 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
4615 (sqrshr): Define macro.
4616 (sqrshrl): Likewise.
4617 (sqrshrl_sat48): Likewise.
4623 (uqrshll): Likewise.
4624 (uqrshll_sat48): Likewise.
4631 (__arm_lsll): Define intrinsic.
4632 (__arm_asrl): Likewise.
4633 (__arm_uqrshll): Likewise.
4634 (__arm_uqrshll_sat48): Likewise.
4635 (__arm_sqrshrl): Likewise.
4636 (__arm_sqrshrl_sat48): Likewise.
4637 (__arm_uqshll): Likewise.
4638 (__arm_urshrl): Likewise.
4639 (__arm_srshrl): Likewise.
4640 (__arm_sqshll): Likewise.
4641 (__arm_uqrshl): Likewise.
4642 (__arm_sqrshr): Likewise.
4643 (__arm_uqshl): Likewise.
4644 (__arm_urshr): Likewise.
4645 (__arm_sqshl): Likewise.
4646 (__arm_srshr): Likewise.
4647 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
4649 (UQSHL_QUALIFIERS): Likewise.
4650 (ASRL_QUALIFIERS): Likewise.
4651 (SQSHL_QUALIFIERS): Likewise.
4652 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
4653 (mve_sqrshrl_sat<supf>_di): Likewise.
4654 (mve_uqrshl_si): Likewise.
4655 (mve_sqrshr_si): Likewise.
4656 (mve_uqshll_di): Likewise.
4657 (mve_urshrl_di): Likewise.
4658 (mve_uqshl_si): Likewise.
4659 (mve_urshr_si): Likewise.
4660 (mve_sqshl_si): Likewise.
4661 (mve_srshr_si): Likewise.
4662 (mve_srshrl_di): Likewise.
4663 (mve_sqshll_di): Likewise.
4665 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4666 Andre Vieira <andre.simoesdiasvieira@arm.com>
4667 Mihail Ionescu <mihail.ionescu@arm.com>
4669 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro.
4670 (vsetq_lane_f32): Likewise.
4671 (vsetq_lane_s16): Likewise.
4672 (vsetq_lane_s32): Likewise.
4673 (vsetq_lane_s8): Likewise.
4674 (vsetq_lane_s64): Likewise.
4675 (vsetq_lane_u8): Likewise.
4676 (vsetq_lane_u16): Likewise.
4677 (vsetq_lane_u32): Likewise.
4678 (vsetq_lane_u64): Likewise.
4679 (vgetq_lane_f16): Likewise.
4680 (vgetq_lane_f32): Likewise.
4681 (vgetq_lane_s16): Likewise.
4682 (vgetq_lane_s32): Likewise.
4683 (vgetq_lane_s8): Likewise.
4684 (vgetq_lane_s64): Likewise.
4685 (vgetq_lane_u8): Likewise.
4686 (vgetq_lane_u16): Likewise.
4687 (vgetq_lane_u32): Likewise.
4688 (vgetq_lane_u64): Likewise.
4689 (__ARM_NUM_LANES): Likewise.
4690 (__ARM_LANEQ): Likewise.
4691 (__ARM_CHECK_LANEQ): Likewise.
4692 (__arm_vsetq_lane_s16): Define intrinsic.
4693 (__arm_vsetq_lane_s32): Likewise.
4694 (__arm_vsetq_lane_s8): Likewise.
4695 (__arm_vsetq_lane_s64): Likewise.
4696 (__arm_vsetq_lane_u8): Likewise.
4697 (__arm_vsetq_lane_u16): Likewise.
4698 (__arm_vsetq_lane_u32): Likewise.
4699 (__arm_vsetq_lane_u64): Likewise.
4700 (__arm_vgetq_lane_s16): Likewise.
4701 (__arm_vgetq_lane_s32): Likewise.
4702 (__arm_vgetq_lane_s8): Likewise.
4703 (__arm_vgetq_lane_s64): Likewise.
4704 (__arm_vgetq_lane_u8): Likewise.
4705 (__arm_vgetq_lane_u16): Likewise.
4706 (__arm_vgetq_lane_u32): Likewise.
4707 (__arm_vgetq_lane_u64): Likewise.
4708 (__arm_vsetq_lane_f16): Likewise.
4709 (__arm_vsetq_lane_f32): Likewise.
4710 (__arm_vgetq_lane_f16): Likewise.
4711 (__arm_vgetq_lane_f32): Likewise.
4712 (vgetq_lane): Define polymorphic variant.
4713 (vsetq_lane): Likewise.
4714 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL
4716 (mve_vec_extractv2didi): Likewise.
4717 (mve_vec_extract_sext_internal<mode>): Likewise.
4718 (mve_vec_extract_zext_internal<mode>): Likewise.
4719 (mve_vec_set<mode>_internal): Likewise.
4720 (mve_vec_setv2di_internal): Likewise.
4721 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md
4723 (vec_extract<mode><V_elem_l>): Rename to
4724 "neon_vec_extract<mode><V_elem_l>".
4725 (vec_extractv2didi): Rename to "neon_vec_extractv2didi".
4726 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL
4727 pattern common for MVE and NEON.
4728 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both
4731 2020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
4733 * config/arm/mve.md (earlyclobber_32): New mode attribute.
4734 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
4735 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
4737 2020-03-23 Richard Biener <rguenther@suse.de>
4739 PR tree-optimization/94261
4740 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove
4741 IL operand swapping code.
4742 (vect_slp_rearrange_stmts): Do not arrange isomorphic
4743 nodes that would need operation code adjustments.
4745 2020-03-23 Tobias Burnus <tobias@codesourcery.com>
4747 * doc/install.texi (amdgcn-*-amdhsa): Renamed
4748 from amdgcn-unknown-amdhsa; change
4749 amdgcn-unknown-amdhsa to amdgcn-amdhsa.
4751 2020-03-23 Richard Biener <rguenther@suse.de>
4754 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP
4755 directly rather than also folding it via build_fold_addr_expr.
4757 2020-03-23 Richard Biener <rguenther@suse.de>
4759 PR tree-optimization/94266
4760 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate
4761 addresses of TARGET_MEM_REFs.
4763 2020-03-23 Martin Liska <mliska@suse.cz>
4766 * symtab.c (symtab_node::clone_references): Save speculative_id
4767 as ref may be overwritten by create_reference.
4768 (symtab_node::clone_referring): Likewise.
4769 (symtab_node::clone_reference): Likewise.
4771 2020-03-22 Iain Sandoe <iain@sandoe.co.uk>
4773 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
4774 references to Darwin.
4775 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
4776 unconditionally and comment on why.
4778 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
4780 * config/darwin.c (darwin_mergeable_constant_section): Collect
4781 section anchor checks into the caller.
4782 (machopic_select_section): Collect section anchor checks into
4783 the determination of 'effective zero-size' objects. When the
4784 size is unknown, assume it is non-zero, and thus return the
4785 'generic' section for the DECL.
4787 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
4790 * config/darwin.opt: Amend options descriptions.
4792 2020-03-21 Richard Sandiford <richard.sandiford@arm.com>
4794 PR rtl-optimization/94052
4795 * lra-constraints.c (simplify_operand_subreg): Reload the inner
4796 register of a paradoxical subreg if simplify_subreg_regno fails
4797 to give a valid hard register for the outer mode.
4799 2020-03-20 Martin Jambor <mjambor@suse.cz>
4801 PR tree-optimization/93435
4802 * params.opt (sra-max-propagations): New parameter.
4803 * tree-sra.c (propagation_budget): New variable.
4804 (budget_for_propagation_access): New function.
4805 (propagate_subaccesses_from_rhs): Use it.
4806 (propagate_subaccesses_from_lhs): Likewise.
4807 (propagate_all_subaccesses): Set up and destroy propagation_budget.
4809 2020-03-20 Carl Love <cel@us.ibm.com>
4812 * config/rs6000/rs6000.c (rs6000_option_override_internal):
4813 Add check for TARGET_FPRND for Power 7 or newer.
4815 2020-03-20 Jan Hubicka <hubicka@ucw.cz>
4818 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag.
4819 (cgraph_edge::redirect_callee): Move here; likewise.
4820 (cgraph_node::remove_callees): Update calls_comdat_local flag.
4821 (cgraph_node::verify_node): Verify that calls_comdat_local flag match
4823 (cgraph_node::check_calls_comdat_local_p): New member function.
4824 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare.
4825 (cgraph_edge::redirect_callee): Move offline.
4826 * ipa-fnsummary.c (compute_fn_summary): Do not compute
4827 calls_comdat_local flag here.
4828 * ipa-inline-transform.c (inline_call): Fix updating of
4829 calls_comdat_local flag.
4830 * ipa-split.c (split_function): Use true instead of 1 to set the flag.
4831 * symtab.c (symtab_node::add_to_same_comdat_group): Update
4832 calls_comdat_local flag.
4834 2020-03-20 Richard Biener <rguenther@suse.de>
4836 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree
4837 from the possibly modified root.
4839 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4840 Andre Vieira <andre.simoesdiasvieira@arm.com>
4841 Mihail Ionescu <mihail.ionescu@arm.com>
4843 * config/arm/arm_mve.h (vst1q_p_u8): Define macro.
4844 (vst1q_p_s8): Likewise.
4845 (vst2q_s8): Likewise.
4846 (vst2q_u8): Likewise.
4847 (vld1q_z_u8): Likewise.
4848 (vld1q_z_s8): Likewise.
4849 (vld2q_s8): Likewise.
4850 (vld2q_u8): Likewise.
4851 (vld4q_s8): Likewise.
4852 (vld4q_u8): Likewise.
4853 (vst1q_p_u16): Likewise.
4854 (vst1q_p_s16): Likewise.
4855 (vst2q_s16): Likewise.
4856 (vst2q_u16): Likewise.
4857 (vld1q_z_u16): Likewise.
4858 (vld1q_z_s16): Likewise.
4859 (vld2q_s16): Likewise.
4860 (vld2q_u16): Likewise.
4861 (vld4q_s16): Likewise.
4862 (vld4q_u16): Likewise.
4863 (vst1q_p_u32): Likewise.
4864 (vst1q_p_s32): Likewise.
4865 (vst2q_s32): Likewise.
4866 (vst2q_u32): Likewise.
4867 (vld1q_z_u32): Likewise.
4868 (vld1q_z_s32): Likewise.
4869 (vld2q_s32): Likewise.
4870 (vld2q_u32): Likewise.
4871 (vld4q_s32): Likewise.
4872 (vld4q_u32): Likewise.
4873 (vld4q_f16): Likewise.
4874 (vld2q_f16): Likewise.
4875 (vld1q_z_f16): Likewise.
4876 (vst2q_f16): Likewise.
4877 (vst1q_p_f16): Likewise.
4878 (vld4q_f32): Likewise.
4879 (vld2q_f32): Likewise.
4880 (vld1q_z_f32): Likewise.
4881 (vst2q_f32): Likewise.
4882 (vst1q_p_f32): Likewise.
4883 (__arm_vst1q_p_u8): Define intrinsic.
4884 (__arm_vst1q_p_s8): Likewise.
4885 (__arm_vst2q_s8): Likewise.
4886 (__arm_vst2q_u8): Likewise.
4887 (__arm_vld1q_z_u8): Likewise.
4888 (__arm_vld1q_z_s8): Likewise.
4889 (__arm_vld2q_s8): Likewise.
4890 (__arm_vld2q_u8): Likewise.
4891 (__arm_vld4q_s8): Likewise.
4892 (__arm_vld4q_u8): Likewise.
4893 (__arm_vst1q_p_u16): Likewise.
4894 (__arm_vst1q_p_s16): Likewise.
4895 (__arm_vst2q_s16): Likewise.
4896 (__arm_vst2q_u16): Likewise.
4897 (__arm_vld1q_z_u16): Likewise.
4898 (__arm_vld1q_z_s16): Likewise.
4899 (__arm_vld2q_s16): Likewise.
4900 (__arm_vld2q_u16): Likewise.
4901 (__arm_vld4q_s16): Likewise.
4902 (__arm_vld4q_u16): Likewise.
4903 (__arm_vst1q_p_u32): Likewise.
4904 (__arm_vst1q_p_s32): Likewise.
4905 (__arm_vst2q_s32): Likewise.
4906 (__arm_vst2q_u32): Likewise.
4907 (__arm_vld1q_z_u32): Likewise.
4908 (__arm_vld1q_z_s32): Likewise.
4909 (__arm_vld2q_s32): Likewise.
4910 (__arm_vld2q_u32): Likewise.
4911 (__arm_vld4q_s32): Likewise.
4912 (__arm_vld4q_u32): Likewise.
4913 (__arm_vld4q_f16): Likewise.
4914 (__arm_vld2q_f16): Likewise.
4915 (__arm_vld1q_z_f16): Likewise.
4916 (__arm_vst2q_f16): Likewise.
4917 (__arm_vst1q_p_f16): Likewise.
4918 (__arm_vld4q_f32): Likewise.
4919 (__arm_vld2q_f32): Likewise.
4920 (__arm_vld1q_z_f32): Likewise.
4921 (__arm_vst2q_f32): Likewise.
4922 (__arm_vst1q_p_f32): Likewise.
4923 (vld1q_z): Define polymorphic variant.
4926 (vst1q_p): Likewise.
4928 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier.
4930 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern.
4931 (mve_vld2q<mode>): Likewise.
4932 (mve_vld4q<mode>): Likewise.
4934 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4935 Andre Vieira <andre.simoesdiasvieira@arm.com>
4936 Mihail Ionescu <mihail.ionescu@arm.com>
4938 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define.
4939 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise.
4940 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and
4941 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array.
4942 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC
4943 and ARM_BUILTIN_SET_FPSCR_NZCVQC.
4944 * config/arm/arm_mve.h (vadciq_s32): Define macro.
4945 (vadciq_u32): Likewise.
4946 (vadciq_m_s32): Likewise.
4947 (vadciq_m_u32): Likewise.
4948 (vadcq_s32): Likewise.
4949 (vadcq_u32): Likewise.
4950 (vadcq_m_s32): Likewise.
4951 (vadcq_m_u32): Likewise.
4952 (vsbciq_s32): Likewise.
4953 (vsbciq_u32): Likewise.
4954 (vsbciq_m_s32): Likewise.
4955 (vsbciq_m_u32): Likewise.
4956 (vsbcq_s32): Likewise.
4957 (vsbcq_u32): Likewise.
4958 (vsbcq_m_s32): Likewise.
4959 (vsbcq_m_u32): Likewise.
4960 (__arm_vadciq_s32): Define intrinsic.
4961 (__arm_vadciq_u32): Likewise.
4962 (__arm_vadciq_m_s32): Likewise.
4963 (__arm_vadciq_m_u32): Likewise.
4964 (__arm_vadcq_s32): Likewise.
4965 (__arm_vadcq_u32): Likewise.
4966 (__arm_vadcq_m_s32): Likewise.
4967 (__arm_vadcq_m_u32): Likewise.
4968 (__arm_vsbciq_s32): Likewise.
4969 (__arm_vsbciq_u32): Likewise.
4970 (__arm_vsbciq_m_s32): Likewise.
4971 (__arm_vsbciq_m_u32): Likewise.
4972 (__arm_vsbcq_s32): Likewise.
4973 (__arm_vsbcq_u32): Likewise.
4974 (__arm_vsbcq_m_s32): Likewise.
4975 (__arm_vsbcq_m_u32): Likewise.
4976 (vadciq_m): Define polymorphic variant.
4978 (vadcq_m): Likewise.
4980 (vsbciq_m): Likewise.
4982 (vsbcq_m): Likewise.
4984 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin
4986 (BINOP_UNONE_UNONE_UNONE): Likewise.
4987 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
4988 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
4989 * config/arm/mve.md (VADCIQ): Define iterator.
4990 (VADCIQ_M): Likewise.
4992 (VSBCQ_M): Likewise.
4994 (VSBCIQ_M): Likewise.
4996 (VADCQ_M): Likewise.
4997 (mve_vadciq_m_<supf>v4si): Define RTL pattern.
4998 (mve_vadciq_<supf>v4si): Likewise.
4999 (mve_vadcq_m_<supf>v4si): Likewise.
5000 (mve_vadcq_<supf>v4si): Likewise.
5001 (mve_vsbciq_m_<supf>v4si): Likewise.
5002 (mve_vsbciq_<supf>v4si): Likewise.
5003 (mve_vsbcq_m_<supf>v4si): Likewise.
5004 (mve_vsbcq_<supf>v4si): Likewise.
5005 (get_fpscr_nzcvqc): Define isns.
5006 (set_fpscr_nzcvqc): Define isns.
5007 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define.
5008 (UNSPEC_SET_FPSCR_NZCVQC): Define.
5010 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5012 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
5013 (vddupq_x_n_u16): Likewise.
5014 (vddupq_x_n_u32): Likewise.
5015 (vddupq_x_wb_u8): Likewise.
5016 (vddupq_x_wb_u16): Likewise.
5017 (vddupq_x_wb_u32): Likewise.
5018 (vdwdupq_x_n_u8): Likewise.
5019 (vdwdupq_x_n_u16): Likewise.
5020 (vdwdupq_x_n_u32): Likewise.
5021 (vdwdupq_x_wb_u8): Likewise.
5022 (vdwdupq_x_wb_u16): Likewise.
5023 (vdwdupq_x_wb_u32): Likewise.
5024 (vidupq_x_n_u8): Likewise.
5025 (vidupq_x_n_u16): Likewise.
5026 (vidupq_x_n_u32): Likewise.
5027 (vidupq_x_wb_u8): Likewise.
5028 (vidupq_x_wb_u16): Likewise.
5029 (vidupq_x_wb_u32): Likewise.
5030 (viwdupq_x_n_u8): Likewise.
5031 (viwdupq_x_n_u16): Likewise.
5032 (viwdupq_x_n_u32): Likewise.
5033 (viwdupq_x_wb_u8): Likewise.
5034 (viwdupq_x_wb_u16): Likewise.
5035 (viwdupq_x_wb_u32): Likewise.
5036 (vdupq_x_n_s8): Likewise.
5037 (vdupq_x_n_s16): Likewise.
5038 (vdupq_x_n_s32): Likewise.
5039 (vdupq_x_n_u8): Likewise.
5040 (vdupq_x_n_u16): Likewise.
5041 (vdupq_x_n_u32): Likewise.
5042 (vminq_x_s8): Likewise.
5043 (vminq_x_s16): Likewise.
5044 (vminq_x_s32): Likewise.
5045 (vminq_x_u8): Likewise.
5046 (vminq_x_u16): Likewise.
5047 (vminq_x_u32): Likewise.
5048 (vmaxq_x_s8): Likewise.
5049 (vmaxq_x_s16): Likewise.
5050 (vmaxq_x_s32): Likewise.
5051 (vmaxq_x_u8): Likewise.
5052 (vmaxq_x_u16): Likewise.
5053 (vmaxq_x_u32): Likewise.
5054 (vabdq_x_s8): Likewise.
5055 (vabdq_x_s16): Likewise.
5056 (vabdq_x_s32): Likewise.
5057 (vabdq_x_u8): Likewise.
5058 (vabdq_x_u16): Likewise.
5059 (vabdq_x_u32): Likewise.
5060 (vabsq_x_s8): Likewise.
5061 (vabsq_x_s16): Likewise.
5062 (vabsq_x_s32): Likewise.
5063 (vaddq_x_s8): Likewise.
5064 (vaddq_x_s16): Likewise.
5065 (vaddq_x_s32): Likewise.
5066 (vaddq_x_n_s8): Likewise.
5067 (vaddq_x_n_s16): Likewise.
5068 (vaddq_x_n_s32): Likewise.
5069 (vaddq_x_u8): Likewise.
5070 (vaddq_x_u16): Likewise.
5071 (vaddq_x_u32): Likewise.
5072 (vaddq_x_n_u8): Likewise.
5073 (vaddq_x_n_u16): Likewise.
5074 (vaddq_x_n_u32): Likewise.
5075 (vclsq_x_s8): Likewise.
5076 (vclsq_x_s16): Likewise.
5077 (vclsq_x_s32): Likewise.
5078 (vclzq_x_s8): Likewise.
5079 (vclzq_x_s16): Likewise.
5080 (vclzq_x_s32): Likewise.
5081 (vclzq_x_u8): Likewise.
5082 (vclzq_x_u16): Likewise.
5083 (vclzq_x_u32): Likewise.
5084 (vnegq_x_s8): Likewise.
5085 (vnegq_x_s16): Likewise.
5086 (vnegq_x_s32): Likewise.
5087 (vmulhq_x_s8): Likewise.
5088 (vmulhq_x_s16): Likewise.
5089 (vmulhq_x_s32): Likewise.
5090 (vmulhq_x_u8): Likewise.
5091 (vmulhq_x_u16): Likewise.
5092 (vmulhq_x_u32): Likewise.
5093 (vmullbq_poly_x_p8): Likewise.
5094 (vmullbq_poly_x_p16): Likewise.
5095 (vmullbq_int_x_s8): Likewise.
5096 (vmullbq_int_x_s16): Likewise.
5097 (vmullbq_int_x_s32): Likewise.
5098 (vmullbq_int_x_u8): Likewise.
5099 (vmullbq_int_x_u16): Likewise.
5100 (vmullbq_int_x_u32): Likewise.
5101 (vmulltq_poly_x_p8): Likewise.
5102 (vmulltq_poly_x_p16): Likewise.
5103 (vmulltq_int_x_s8): Likewise.
5104 (vmulltq_int_x_s16): Likewise.
5105 (vmulltq_int_x_s32): Likewise.
5106 (vmulltq_int_x_u8): Likewise.
5107 (vmulltq_int_x_u16): Likewise.
5108 (vmulltq_int_x_u32): Likewise.
5109 (vmulq_x_s8): Likewise.
5110 (vmulq_x_s16): Likewise.
5111 (vmulq_x_s32): Likewise.
5112 (vmulq_x_n_s8): Likewise.
5113 (vmulq_x_n_s16): Likewise.
5114 (vmulq_x_n_s32): Likewise.
5115 (vmulq_x_u8): Likewise.
5116 (vmulq_x_u16): Likewise.
5117 (vmulq_x_u32): Likewise.
5118 (vmulq_x_n_u8): Likewise.
5119 (vmulq_x_n_u16): Likewise.
5120 (vmulq_x_n_u32): Likewise.
5121 (vsubq_x_s8): Likewise.
5122 (vsubq_x_s16): Likewise.
5123 (vsubq_x_s32): Likewise.
5124 (vsubq_x_n_s8): Likewise.
5125 (vsubq_x_n_s16): Likewise.
5126 (vsubq_x_n_s32): Likewise.
5127 (vsubq_x_u8): Likewise.
5128 (vsubq_x_u16): Likewise.
5129 (vsubq_x_u32): Likewise.
5130 (vsubq_x_n_u8): Likewise.
5131 (vsubq_x_n_u16): Likewise.
5132 (vsubq_x_n_u32): Likewise.
5133 (vcaddq_rot90_x_s8): Likewise.
5134 (vcaddq_rot90_x_s16): Likewise.
5135 (vcaddq_rot90_x_s32): Likewise.
5136 (vcaddq_rot90_x_u8): Likewise.
5137 (vcaddq_rot90_x_u16): Likewise.
5138 (vcaddq_rot90_x_u32): Likewise.
5139 (vcaddq_rot270_x_s8): Likewise.
5140 (vcaddq_rot270_x_s16): Likewise.
5141 (vcaddq_rot270_x_s32): Likewise.
5142 (vcaddq_rot270_x_u8): Likewise.
5143 (vcaddq_rot270_x_u16): Likewise.
5144 (vcaddq_rot270_x_u32): Likewise.
5145 (vhaddq_x_n_s8): Likewise.
5146 (vhaddq_x_n_s16): Likewise.
5147 (vhaddq_x_n_s32): Likewise.
5148 (vhaddq_x_n_u8): Likewise.
5149 (vhaddq_x_n_u16): Likewise.
5150 (vhaddq_x_n_u32): Likewise.
5151 (vhaddq_x_s8): Likewise.
5152 (vhaddq_x_s16): Likewise.
5153 (vhaddq_x_s32): Likewise.
5154 (vhaddq_x_u8): Likewise.
5155 (vhaddq_x_u16): Likewise.
5156 (vhaddq_x_u32): Likewise.
5157 (vhcaddq_rot90_x_s8): Likewise.
5158 (vhcaddq_rot90_x_s16): Likewise.
5159 (vhcaddq_rot90_x_s32): Likewise.
5160 (vhcaddq_rot270_x_s8): Likewise.
5161 (vhcaddq_rot270_x_s16): Likewise.
5162 (vhcaddq_rot270_x_s32): Likewise.
5163 (vhsubq_x_n_s8): Likewise.
5164 (vhsubq_x_n_s16): Likewise.
5165 (vhsubq_x_n_s32): Likewise.
5166 (vhsubq_x_n_u8): Likewise.
5167 (vhsubq_x_n_u16): Likewise.
5168 (vhsubq_x_n_u32): Likewise.
5169 (vhsubq_x_s8): Likewise.
5170 (vhsubq_x_s16): Likewise.
5171 (vhsubq_x_s32): Likewise.
5172 (vhsubq_x_u8): Likewise.
5173 (vhsubq_x_u16): Likewise.
5174 (vhsubq_x_u32): Likewise.
5175 (vrhaddq_x_s8): Likewise.
5176 (vrhaddq_x_s16): Likewise.
5177 (vrhaddq_x_s32): Likewise.
5178 (vrhaddq_x_u8): Likewise.
5179 (vrhaddq_x_u16): Likewise.
5180 (vrhaddq_x_u32): Likewise.
5181 (vrmulhq_x_s8): Likewise.
5182 (vrmulhq_x_s16): Likewise.
5183 (vrmulhq_x_s32): Likewise.
5184 (vrmulhq_x_u8): Likewise.
5185 (vrmulhq_x_u16): Likewise.
5186 (vrmulhq_x_u32): Likewise.
5187 (vandq_x_s8): Likewise.
5188 (vandq_x_s16): Likewise.
5189 (vandq_x_s32): Likewise.
5190 (vandq_x_u8): Likewise.
5191 (vandq_x_u16): Likewise.
5192 (vandq_x_u32): Likewise.
5193 (vbicq_x_s8): Likewise.
5194 (vbicq_x_s16): Likewise.
5195 (vbicq_x_s32): Likewise.
5196 (vbicq_x_u8): Likewise.
5197 (vbicq_x_u16): Likewise.
5198 (vbicq_x_u32): Likewise.
5199 (vbrsrq_x_n_s8): Likewise.
5200 (vbrsrq_x_n_s16): Likewise.
5201 (vbrsrq_x_n_s32): Likewise.
5202 (vbrsrq_x_n_u8): Likewise.
5203 (vbrsrq_x_n_u16): Likewise.
5204 (vbrsrq_x_n_u32): Likewise.
5205 (veorq_x_s8): Likewise.
5206 (veorq_x_s16): Likewise.
5207 (veorq_x_s32): Likewise.
5208 (veorq_x_u8): Likewise.
5209 (veorq_x_u16): Likewise.
5210 (veorq_x_u32): Likewise.
5211 (vmovlbq_x_s8): Likewise.
5212 (vmovlbq_x_s16): Likewise.
5213 (vmovlbq_x_u8): Likewise.
5214 (vmovlbq_x_u16): Likewise.
5215 (vmovltq_x_s8): Likewise.
5216 (vmovltq_x_s16): Likewise.
5217 (vmovltq_x_u8): Likewise.
5218 (vmovltq_x_u16): Likewise.
5219 (vmvnq_x_s8): Likewise.
5220 (vmvnq_x_s16): Likewise.
5221 (vmvnq_x_s32): Likewise.
5222 (vmvnq_x_u8): Likewise.
5223 (vmvnq_x_u16): Likewise.
5224 (vmvnq_x_u32): Likewise.
5225 (vmvnq_x_n_s16): Likewise.
5226 (vmvnq_x_n_s32): Likewise.
5227 (vmvnq_x_n_u16): Likewise.
5228 (vmvnq_x_n_u32): Likewise.
5229 (vornq_x_s8): Likewise.
5230 (vornq_x_s16): Likewise.
5231 (vornq_x_s32): Likewise.
5232 (vornq_x_u8): Likewise.
5233 (vornq_x_u16): Likewise.
5234 (vornq_x_u32): Likewise.
5235 (vorrq_x_s8): Likewise.
5236 (vorrq_x_s16): Likewise.
5237 (vorrq_x_s32): Likewise.
5238 (vorrq_x_u8): Likewise.
5239 (vorrq_x_u16): Likewise.
5240 (vorrq_x_u32): Likewise.
5241 (vrev16q_x_s8): Likewise.
5242 (vrev16q_x_u8): Likewise.
5243 (vrev32q_x_s8): Likewise.
5244 (vrev32q_x_s16): Likewise.
5245 (vrev32q_x_u8): Likewise.
5246 (vrev32q_x_u16): Likewise.
5247 (vrev64q_x_s8): Likewise.
5248 (vrev64q_x_s16): Likewise.
5249 (vrev64q_x_s32): Likewise.
5250 (vrev64q_x_u8): Likewise.
5251 (vrev64q_x_u16): Likewise.
5252 (vrev64q_x_u32): Likewise.
5253 (vrshlq_x_s8): Likewise.
5254 (vrshlq_x_s16): Likewise.
5255 (vrshlq_x_s32): Likewise.
5256 (vrshlq_x_u8): Likewise.
5257 (vrshlq_x_u16): Likewise.
5258 (vrshlq_x_u32): Likewise.
5259 (vshllbq_x_n_s8): Likewise.
5260 (vshllbq_x_n_s16): Likewise.
5261 (vshllbq_x_n_u8): Likewise.
5262 (vshllbq_x_n_u16): Likewise.
5263 (vshlltq_x_n_s8): Likewise.
5264 (vshlltq_x_n_s16): Likewise.
5265 (vshlltq_x_n_u8): Likewise.
5266 (vshlltq_x_n_u16): Likewise.
5267 (vshlq_x_s8): Likewise.
5268 (vshlq_x_s16): Likewise.
5269 (vshlq_x_s32): Likewise.
5270 (vshlq_x_u8): Likewise.
5271 (vshlq_x_u16): Likewise.
5272 (vshlq_x_u32): Likewise.
5273 (vshlq_x_n_s8): Likewise.
5274 (vshlq_x_n_s16): Likewise.
5275 (vshlq_x_n_s32): Likewise.
5276 (vshlq_x_n_u8): Likewise.
5277 (vshlq_x_n_u16): Likewise.
5278 (vshlq_x_n_u32): Likewise.
5279 (vrshrq_x_n_s8): Likewise.
5280 (vrshrq_x_n_s16): Likewise.
5281 (vrshrq_x_n_s32): Likewise.
5282 (vrshrq_x_n_u8): Likewise.
5283 (vrshrq_x_n_u16): Likewise.
5284 (vrshrq_x_n_u32): Likewise.
5285 (vshrq_x_n_s8): Likewise.
5286 (vshrq_x_n_s16): Likewise.
5287 (vshrq_x_n_s32): Likewise.
5288 (vshrq_x_n_u8): Likewise.
5289 (vshrq_x_n_u16): Likewise.
5290 (vshrq_x_n_u32): Likewise.
5291 (vdupq_x_n_f16): Likewise.
5292 (vdupq_x_n_f32): Likewise.
5293 (vminnmq_x_f16): Likewise.
5294 (vminnmq_x_f32): Likewise.
5295 (vmaxnmq_x_f16): Likewise.
5296 (vmaxnmq_x_f32): Likewise.
5297 (vabdq_x_f16): Likewise.
5298 (vabdq_x_f32): Likewise.
5299 (vabsq_x_f16): Likewise.
5300 (vabsq_x_f32): Likewise.
5301 (vaddq_x_f16): Likewise.
5302 (vaddq_x_f32): Likewise.
5303 (vaddq_x_n_f16): Likewise.
5304 (vaddq_x_n_f32): Likewise.
5305 (vnegq_x_f16): Likewise.
5306 (vnegq_x_f32): Likewise.
5307 (vmulq_x_f16): Likewise.
5308 (vmulq_x_f32): Likewise.
5309 (vmulq_x_n_f16): Likewise.
5310 (vmulq_x_n_f32): Likewise.
5311 (vsubq_x_f16): Likewise.
5312 (vsubq_x_f32): Likewise.
5313 (vsubq_x_n_f16): Likewise.
5314 (vsubq_x_n_f32): Likewise.
5315 (vcaddq_rot90_x_f16): Likewise.
5316 (vcaddq_rot90_x_f32): Likewise.
5317 (vcaddq_rot270_x_f16): Likewise.
5318 (vcaddq_rot270_x_f32): Likewise.
5319 (vcmulq_x_f16): Likewise.
5320 (vcmulq_x_f32): Likewise.
5321 (vcmulq_rot90_x_f16): Likewise.
5322 (vcmulq_rot90_x_f32): Likewise.
5323 (vcmulq_rot180_x_f16): Likewise.
5324 (vcmulq_rot180_x_f32): Likewise.
5325 (vcmulq_rot270_x_f16): Likewise.
5326 (vcmulq_rot270_x_f32): Likewise.
5327 (vcvtaq_x_s16_f16): Likewise.
5328 (vcvtaq_x_s32_f32): Likewise.
5329 (vcvtaq_x_u16_f16): Likewise.
5330 (vcvtaq_x_u32_f32): Likewise.
5331 (vcvtnq_x_s16_f16): Likewise.
5332 (vcvtnq_x_s32_f32): Likewise.
5333 (vcvtnq_x_u16_f16): Likewise.
5334 (vcvtnq_x_u32_f32): Likewise.
5335 (vcvtpq_x_s16_f16): Likewise.
5336 (vcvtpq_x_s32_f32): Likewise.
5337 (vcvtpq_x_u16_f16): Likewise.
5338 (vcvtpq_x_u32_f32): Likewise.
5339 (vcvtmq_x_s16_f16): Likewise.
5340 (vcvtmq_x_s32_f32): Likewise.
5341 (vcvtmq_x_u16_f16): Likewise.
5342 (vcvtmq_x_u32_f32): Likewise.
5343 (vcvtbq_x_f32_f16): Likewise.
5344 (vcvttq_x_f32_f16): Likewise.
5345 (vcvtq_x_f16_u16): Likewise.
5346 (vcvtq_x_f16_s16): Likewise.
5347 (vcvtq_x_f32_s32): Likewise.
5348 (vcvtq_x_f32_u32): Likewise.
5349 (vcvtq_x_n_f16_s16): Likewise.
5350 (vcvtq_x_n_f16_u16): Likewise.
5351 (vcvtq_x_n_f32_s32): Likewise.
5352 (vcvtq_x_n_f32_u32): Likewise.
5353 (vcvtq_x_s16_f16): Likewise.
5354 (vcvtq_x_s32_f32): Likewise.
5355 (vcvtq_x_u16_f16): Likewise.
5356 (vcvtq_x_u32_f32): Likewise.
5357 (vcvtq_x_n_s16_f16): Likewise.
5358 (vcvtq_x_n_s32_f32): Likewise.
5359 (vcvtq_x_n_u16_f16): Likewise.
5360 (vcvtq_x_n_u32_f32): Likewise.
5361 (vrndq_x_f16): Likewise.
5362 (vrndq_x_f32): Likewise.
5363 (vrndnq_x_f16): Likewise.
5364 (vrndnq_x_f32): Likewise.
5365 (vrndmq_x_f16): Likewise.
5366 (vrndmq_x_f32): Likewise.
5367 (vrndpq_x_f16): Likewise.
5368 (vrndpq_x_f32): Likewise.
5369 (vrndaq_x_f16): Likewise.
5370 (vrndaq_x_f32): Likewise.
5371 (vrndxq_x_f16): Likewise.
5372 (vrndxq_x_f32): Likewise.
5373 (vandq_x_f16): Likewise.
5374 (vandq_x_f32): Likewise.
5375 (vbicq_x_f16): Likewise.
5376 (vbicq_x_f32): Likewise.
5377 (vbrsrq_x_n_f16): Likewise.
5378 (vbrsrq_x_n_f32): Likewise.
5379 (veorq_x_f16): Likewise.
5380 (veorq_x_f32): Likewise.
5381 (vornq_x_f16): Likewise.
5382 (vornq_x_f32): Likewise.
5383 (vorrq_x_f16): Likewise.
5384 (vorrq_x_f32): Likewise.
5385 (vrev32q_x_f16): Likewise.
5386 (vrev64q_x_f16): Likewise.
5387 (vrev64q_x_f32): Likewise.
5388 (__arm_vddupq_x_n_u8): Define intrinsic.
5389 (__arm_vddupq_x_n_u16): Likewise.
5390 (__arm_vddupq_x_n_u32): Likewise.
5391 (__arm_vddupq_x_wb_u8): Likewise.
5392 (__arm_vddupq_x_wb_u16): Likewise.
5393 (__arm_vddupq_x_wb_u32): Likewise.
5394 (__arm_vdwdupq_x_n_u8): Likewise.
5395 (__arm_vdwdupq_x_n_u16): Likewise.
5396 (__arm_vdwdupq_x_n_u32): Likewise.
5397 (__arm_vdwdupq_x_wb_u8): Likewise.
5398 (__arm_vdwdupq_x_wb_u16): Likewise.
5399 (__arm_vdwdupq_x_wb_u32): Likewise.
5400 (__arm_vidupq_x_n_u8): Likewise.
5401 (__arm_vidupq_x_n_u16): Likewise.
5402 (__arm_vidupq_x_n_u32): Likewise.
5403 (__arm_vidupq_x_wb_u8): Likewise.
5404 (__arm_vidupq_x_wb_u16): Likewise.
5405 (__arm_vidupq_x_wb_u32): Likewise.
5406 (__arm_viwdupq_x_n_u8): Likewise.
5407 (__arm_viwdupq_x_n_u16): Likewise.
5408 (__arm_viwdupq_x_n_u32): Likewise.
5409 (__arm_viwdupq_x_wb_u8): Likewise.
5410 (__arm_viwdupq_x_wb_u16): Likewise.
5411 (__arm_viwdupq_x_wb_u32): Likewise.
5412 (__arm_vdupq_x_n_s8): Likewise.
5413 (__arm_vdupq_x_n_s16): Likewise.
5414 (__arm_vdupq_x_n_s32): Likewise.
5415 (__arm_vdupq_x_n_u8): Likewise.
5416 (__arm_vdupq_x_n_u16): Likewise.
5417 (__arm_vdupq_x_n_u32): Likewise.
5418 (__arm_vminq_x_s8): Likewise.
5419 (__arm_vminq_x_s16): Likewise.
5420 (__arm_vminq_x_s32): Likewise.
5421 (__arm_vminq_x_u8): Likewise.
5422 (__arm_vminq_x_u16): Likewise.
5423 (__arm_vminq_x_u32): Likewise.
5424 (__arm_vmaxq_x_s8): Likewise.
5425 (__arm_vmaxq_x_s16): Likewise.
5426 (__arm_vmaxq_x_s32): Likewise.
5427 (__arm_vmaxq_x_u8): Likewise.
5428 (__arm_vmaxq_x_u16): Likewise.
5429 (__arm_vmaxq_x_u32): Likewise.
5430 (__arm_vabdq_x_s8): Likewise.
5431 (__arm_vabdq_x_s16): Likewise.
5432 (__arm_vabdq_x_s32): Likewise.
5433 (__arm_vabdq_x_u8): Likewise.
5434 (__arm_vabdq_x_u16): Likewise.
5435 (__arm_vabdq_x_u32): Likewise.
5436 (__arm_vabsq_x_s8): Likewise.
5437 (__arm_vabsq_x_s16): Likewise.
5438 (__arm_vabsq_x_s32): Likewise.
5439 (__arm_vaddq_x_s8): Likewise.
5440 (__arm_vaddq_x_s16): Likewise.
5441 (__arm_vaddq_x_s32): Likewise.
5442 (__arm_vaddq_x_n_s8): Likewise.
5443 (__arm_vaddq_x_n_s16): Likewise.
5444 (__arm_vaddq_x_n_s32): Likewise.
5445 (__arm_vaddq_x_u8): Likewise.
5446 (__arm_vaddq_x_u16): Likewise.
5447 (__arm_vaddq_x_u32): Likewise.
5448 (__arm_vaddq_x_n_u8): Likewise.
5449 (__arm_vaddq_x_n_u16): Likewise.
5450 (__arm_vaddq_x_n_u32): Likewise.
5451 (__arm_vclsq_x_s8): Likewise.
5452 (__arm_vclsq_x_s16): Likewise.
5453 (__arm_vclsq_x_s32): Likewise.
5454 (__arm_vclzq_x_s8): Likewise.
5455 (__arm_vclzq_x_s16): Likewise.
5456 (__arm_vclzq_x_s32): Likewise.
5457 (__arm_vclzq_x_u8): Likewise.
5458 (__arm_vclzq_x_u16): Likewise.
5459 (__arm_vclzq_x_u32): Likewise.
5460 (__arm_vnegq_x_s8): Likewise.
5461 (__arm_vnegq_x_s16): Likewise.
5462 (__arm_vnegq_x_s32): Likewise.
5463 (__arm_vmulhq_x_s8): Likewise.
5464 (__arm_vmulhq_x_s16): Likewise.
5465 (__arm_vmulhq_x_s32): Likewise.
5466 (__arm_vmulhq_x_u8): Likewise.
5467 (__arm_vmulhq_x_u16): Likewise.
5468 (__arm_vmulhq_x_u32): Likewise.
5469 (__arm_vmullbq_poly_x_p8): Likewise.
5470 (__arm_vmullbq_poly_x_p16): Likewise.
5471 (__arm_vmullbq_int_x_s8): Likewise.
5472 (__arm_vmullbq_int_x_s16): Likewise.
5473 (__arm_vmullbq_int_x_s32): Likewise.
5474 (__arm_vmullbq_int_x_u8): Likewise.
5475 (__arm_vmullbq_int_x_u16): Likewise.
5476 (__arm_vmullbq_int_x_u32): Likewise.
5477 (__arm_vmulltq_poly_x_p8): Likewise.
5478 (__arm_vmulltq_poly_x_p16): Likewise.
5479 (__arm_vmulltq_int_x_s8): Likewise.
5480 (__arm_vmulltq_int_x_s16): Likewise.
5481 (__arm_vmulltq_int_x_s32): Likewise.
5482 (__arm_vmulltq_int_x_u8): Likewise.
5483 (__arm_vmulltq_int_x_u16): Likewise.
5484 (__arm_vmulltq_int_x_u32): Likewise.
5485 (__arm_vmulq_x_s8): Likewise.
5486 (__arm_vmulq_x_s16): Likewise.
5487 (__arm_vmulq_x_s32): Likewise.
5488 (__arm_vmulq_x_n_s8): Likewise.
5489 (__arm_vmulq_x_n_s16): Likewise.
5490 (__arm_vmulq_x_n_s32): Likewise.
5491 (__arm_vmulq_x_u8): Likewise.
5492 (__arm_vmulq_x_u16): Likewise.
5493 (__arm_vmulq_x_u32): Likewise.
5494 (__arm_vmulq_x_n_u8): Likewise.
5495 (__arm_vmulq_x_n_u16): Likewise.
5496 (__arm_vmulq_x_n_u32): Likewise.
5497 (__arm_vsubq_x_s8): Likewise.
5498 (__arm_vsubq_x_s16): Likewise.
5499 (__arm_vsubq_x_s32): Likewise.
5500 (__arm_vsubq_x_n_s8): Likewise.
5501 (__arm_vsubq_x_n_s16): Likewise.
5502 (__arm_vsubq_x_n_s32): Likewise.
5503 (__arm_vsubq_x_u8): Likewise.
5504 (__arm_vsubq_x_u16): Likewise.
5505 (__arm_vsubq_x_u32): Likewise.
5506 (__arm_vsubq_x_n_u8): Likewise.
5507 (__arm_vsubq_x_n_u16): Likewise.
5508 (__arm_vsubq_x_n_u32): Likewise.
5509 (__arm_vcaddq_rot90_x_s8): Likewise.
5510 (__arm_vcaddq_rot90_x_s16): Likewise.
5511 (__arm_vcaddq_rot90_x_s32): Likewise.
5512 (__arm_vcaddq_rot90_x_u8): Likewise.
5513 (__arm_vcaddq_rot90_x_u16): Likewise.
5514 (__arm_vcaddq_rot90_x_u32): Likewise.
5515 (__arm_vcaddq_rot270_x_s8): Likewise.
5516 (__arm_vcaddq_rot270_x_s16): Likewise.
5517 (__arm_vcaddq_rot270_x_s32): Likewise.
5518 (__arm_vcaddq_rot270_x_u8): Likewise.
5519 (__arm_vcaddq_rot270_x_u16): Likewise.
5520 (__arm_vcaddq_rot270_x_u32): Likewise.
5521 (__arm_vhaddq_x_n_s8): Likewise.
5522 (__arm_vhaddq_x_n_s16): Likewise.
5523 (__arm_vhaddq_x_n_s32): Likewise.
5524 (__arm_vhaddq_x_n_u8): Likewise.
5525 (__arm_vhaddq_x_n_u16): Likewise.
5526 (__arm_vhaddq_x_n_u32): Likewise.
5527 (__arm_vhaddq_x_s8): Likewise.
5528 (__arm_vhaddq_x_s16): Likewise.
5529 (__arm_vhaddq_x_s32): Likewise.
5530 (__arm_vhaddq_x_u8): Likewise.
5531 (__arm_vhaddq_x_u16): Likewise.
5532 (__arm_vhaddq_x_u32): Likewise.
5533 (__arm_vhcaddq_rot90_x_s8): Likewise.
5534 (__arm_vhcaddq_rot90_x_s16): Likewise.
5535 (__arm_vhcaddq_rot90_x_s32): Likewise.
5536 (__arm_vhcaddq_rot270_x_s8): Likewise.
5537 (__arm_vhcaddq_rot270_x_s16): Likewise.
5538 (__arm_vhcaddq_rot270_x_s32): Likewise.
5539 (__arm_vhsubq_x_n_s8): Likewise.
5540 (__arm_vhsubq_x_n_s16): Likewise.
5541 (__arm_vhsubq_x_n_s32): Likewise.
5542 (__arm_vhsubq_x_n_u8): Likewise.
5543 (__arm_vhsubq_x_n_u16): Likewise.
5544 (__arm_vhsubq_x_n_u32): Likewise.
5545 (__arm_vhsubq_x_s8): Likewise.
5546 (__arm_vhsubq_x_s16): Likewise.
5547 (__arm_vhsubq_x_s32): Likewise.
5548 (__arm_vhsubq_x_u8): Likewise.
5549 (__arm_vhsubq_x_u16): Likewise.
5550 (__arm_vhsubq_x_u32): Likewise.
5551 (__arm_vrhaddq_x_s8): Likewise.
5552 (__arm_vrhaddq_x_s16): Likewise.
5553 (__arm_vrhaddq_x_s32): Likewise.
5554 (__arm_vrhaddq_x_u8): Likewise.
5555 (__arm_vrhaddq_x_u16): Likewise.
5556 (__arm_vrhaddq_x_u32): Likewise.
5557 (__arm_vrmulhq_x_s8): Likewise.
5558 (__arm_vrmulhq_x_s16): Likewise.
5559 (__arm_vrmulhq_x_s32): Likewise.
5560 (__arm_vrmulhq_x_u8): Likewise.
5561 (__arm_vrmulhq_x_u16): Likewise.
5562 (__arm_vrmulhq_x_u32): Likewise.
5563 (__arm_vandq_x_s8): Likewise.
5564 (__arm_vandq_x_s16): Likewise.
5565 (__arm_vandq_x_s32): Likewise.
5566 (__arm_vandq_x_u8): Likewise.
5567 (__arm_vandq_x_u16): Likewise.
5568 (__arm_vandq_x_u32): Likewise.
5569 (__arm_vbicq_x_s8): Likewise.
5570 (__arm_vbicq_x_s16): Likewise.
5571 (__arm_vbicq_x_s32): Likewise.
5572 (__arm_vbicq_x_u8): Likewise.
5573 (__arm_vbicq_x_u16): Likewise.
5574 (__arm_vbicq_x_u32): Likewise.
5575 (__arm_vbrsrq_x_n_s8): Likewise.
5576 (__arm_vbrsrq_x_n_s16): Likewise.
5577 (__arm_vbrsrq_x_n_s32): Likewise.
5578 (__arm_vbrsrq_x_n_u8): Likewise.
5579 (__arm_vbrsrq_x_n_u16): Likewise.
5580 (__arm_vbrsrq_x_n_u32): Likewise.
5581 (__arm_veorq_x_s8): Likewise.
5582 (__arm_veorq_x_s16): Likewise.
5583 (__arm_veorq_x_s32): Likewise.
5584 (__arm_veorq_x_u8): Likewise.
5585 (__arm_veorq_x_u16): Likewise.
5586 (__arm_veorq_x_u32): Likewise.
5587 (__arm_vmovlbq_x_s8): Likewise.
5588 (__arm_vmovlbq_x_s16): Likewise.
5589 (__arm_vmovlbq_x_u8): Likewise.
5590 (__arm_vmovlbq_x_u16): Likewise.
5591 (__arm_vmovltq_x_s8): Likewise.
5592 (__arm_vmovltq_x_s16): Likewise.
5593 (__arm_vmovltq_x_u8): Likewise.
5594 (__arm_vmovltq_x_u16): Likewise.
5595 (__arm_vmvnq_x_s8): Likewise.
5596 (__arm_vmvnq_x_s16): Likewise.
5597 (__arm_vmvnq_x_s32): Likewise.
5598 (__arm_vmvnq_x_u8): Likewise.
5599 (__arm_vmvnq_x_u16): Likewise.
5600 (__arm_vmvnq_x_u32): Likewise.
5601 (__arm_vmvnq_x_n_s16): Likewise.
5602 (__arm_vmvnq_x_n_s32): Likewise.
5603 (__arm_vmvnq_x_n_u16): Likewise.
5604 (__arm_vmvnq_x_n_u32): Likewise.
5605 (__arm_vornq_x_s8): Likewise.
5606 (__arm_vornq_x_s16): Likewise.
5607 (__arm_vornq_x_s32): Likewise.
5608 (__arm_vornq_x_u8): Likewise.
5609 (__arm_vornq_x_u16): Likewise.
5610 (__arm_vornq_x_u32): Likewise.
5611 (__arm_vorrq_x_s8): Likewise.
5612 (__arm_vorrq_x_s16): Likewise.
5613 (__arm_vorrq_x_s32): Likewise.
5614 (__arm_vorrq_x_u8): Likewise.
5615 (__arm_vorrq_x_u16): Likewise.
5616 (__arm_vorrq_x_u32): Likewise.
5617 (__arm_vrev16q_x_s8): Likewise.
5618 (__arm_vrev16q_x_u8): Likewise.
5619 (__arm_vrev32q_x_s8): Likewise.
5620 (__arm_vrev32q_x_s16): Likewise.
5621 (__arm_vrev32q_x_u8): Likewise.
5622 (__arm_vrev32q_x_u16): Likewise.
5623 (__arm_vrev64q_x_s8): Likewise.
5624 (__arm_vrev64q_x_s16): Likewise.
5625 (__arm_vrev64q_x_s32): Likewise.
5626 (__arm_vrev64q_x_u8): Likewise.
5627 (__arm_vrev64q_x_u16): Likewise.
5628 (__arm_vrev64q_x_u32): Likewise.
5629 (__arm_vrshlq_x_s8): Likewise.
5630 (__arm_vrshlq_x_s16): Likewise.
5631 (__arm_vrshlq_x_s32): Likewise.
5632 (__arm_vrshlq_x_u8): Likewise.
5633 (__arm_vrshlq_x_u16): Likewise.
5634 (__arm_vrshlq_x_u32): Likewise.
5635 (__arm_vshllbq_x_n_s8): Likewise.
5636 (__arm_vshllbq_x_n_s16): Likewise.
5637 (__arm_vshllbq_x_n_u8): Likewise.
5638 (__arm_vshllbq_x_n_u16): Likewise.
5639 (__arm_vshlltq_x_n_s8): Likewise.
5640 (__arm_vshlltq_x_n_s16): Likewise.
5641 (__arm_vshlltq_x_n_u8): Likewise.
5642 (__arm_vshlltq_x_n_u16): Likewise.
5643 (__arm_vshlq_x_s8): Likewise.
5644 (__arm_vshlq_x_s16): Likewise.
5645 (__arm_vshlq_x_s32): Likewise.
5646 (__arm_vshlq_x_u8): Likewise.
5647 (__arm_vshlq_x_u16): Likewise.
5648 (__arm_vshlq_x_u32): Likewise.
5649 (__arm_vshlq_x_n_s8): Likewise.
5650 (__arm_vshlq_x_n_s16): Likewise.
5651 (__arm_vshlq_x_n_s32): Likewise.
5652 (__arm_vshlq_x_n_u8): Likewise.
5653 (__arm_vshlq_x_n_u16): Likewise.
5654 (__arm_vshlq_x_n_u32): Likewise.
5655 (__arm_vrshrq_x_n_s8): Likewise.
5656 (__arm_vrshrq_x_n_s16): Likewise.
5657 (__arm_vrshrq_x_n_s32): Likewise.
5658 (__arm_vrshrq_x_n_u8): Likewise.
5659 (__arm_vrshrq_x_n_u16): Likewise.
5660 (__arm_vrshrq_x_n_u32): Likewise.
5661 (__arm_vshrq_x_n_s8): Likewise.
5662 (__arm_vshrq_x_n_s16): Likewise.
5663 (__arm_vshrq_x_n_s32): Likewise.
5664 (__arm_vshrq_x_n_u8): Likewise.
5665 (__arm_vshrq_x_n_u16): Likewise.
5666 (__arm_vshrq_x_n_u32): Likewise.
5667 (__arm_vdupq_x_n_f16): Likewise.
5668 (__arm_vdupq_x_n_f32): Likewise.
5669 (__arm_vminnmq_x_f16): Likewise.
5670 (__arm_vminnmq_x_f32): Likewise.
5671 (__arm_vmaxnmq_x_f16): Likewise.
5672 (__arm_vmaxnmq_x_f32): Likewise.
5673 (__arm_vabdq_x_f16): Likewise.
5674 (__arm_vabdq_x_f32): Likewise.
5675 (__arm_vabsq_x_f16): Likewise.
5676 (__arm_vabsq_x_f32): Likewise.
5677 (__arm_vaddq_x_f16): Likewise.
5678 (__arm_vaddq_x_f32): Likewise.
5679 (__arm_vaddq_x_n_f16): Likewise.
5680 (__arm_vaddq_x_n_f32): Likewise.
5681 (__arm_vnegq_x_f16): Likewise.
5682 (__arm_vnegq_x_f32): Likewise.
5683 (__arm_vmulq_x_f16): Likewise.
5684 (__arm_vmulq_x_f32): Likewise.
5685 (__arm_vmulq_x_n_f16): Likewise.
5686 (__arm_vmulq_x_n_f32): Likewise.
5687 (__arm_vsubq_x_f16): Likewise.
5688 (__arm_vsubq_x_f32): Likewise.
5689 (__arm_vsubq_x_n_f16): Likewise.
5690 (__arm_vsubq_x_n_f32): Likewise.
5691 (__arm_vcaddq_rot90_x_f16): Likewise.
5692 (__arm_vcaddq_rot90_x_f32): Likewise.
5693 (__arm_vcaddq_rot270_x_f16): Likewise.
5694 (__arm_vcaddq_rot270_x_f32): Likewise.
5695 (__arm_vcmulq_x_f16): Likewise.
5696 (__arm_vcmulq_x_f32): Likewise.
5697 (__arm_vcmulq_rot90_x_f16): Likewise.
5698 (__arm_vcmulq_rot90_x_f32): Likewise.
5699 (__arm_vcmulq_rot180_x_f16): Likewise.
5700 (__arm_vcmulq_rot180_x_f32): Likewise.
5701 (__arm_vcmulq_rot270_x_f16): Likewise.
5702 (__arm_vcmulq_rot270_x_f32): Likewise.
5703 (__arm_vcvtaq_x_s16_f16): Likewise.
5704 (__arm_vcvtaq_x_s32_f32): Likewise.
5705 (__arm_vcvtaq_x_u16_f16): Likewise.
5706 (__arm_vcvtaq_x_u32_f32): Likewise.
5707 (__arm_vcvtnq_x_s16_f16): Likewise.
5708 (__arm_vcvtnq_x_s32_f32): Likewise.
5709 (__arm_vcvtnq_x_u16_f16): Likewise.
5710 (__arm_vcvtnq_x_u32_f32): Likewise.
5711 (__arm_vcvtpq_x_s16_f16): Likewise.
5712 (__arm_vcvtpq_x_s32_f32): Likewise.
5713 (__arm_vcvtpq_x_u16_f16): Likewise.
5714 (__arm_vcvtpq_x_u32_f32): Likewise.
5715 (__arm_vcvtmq_x_s16_f16): Likewise.
5716 (__arm_vcvtmq_x_s32_f32): Likewise.
5717 (__arm_vcvtmq_x_u16_f16): Likewise.
5718 (__arm_vcvtmq_x_u32_f32): Likewise.
5719 (__arm_vcvtbq_x_f32_f16): Likewise.
5720 (__arm_vcvttq_x_f32_f16): Likewise.
5721 (__arm_vcvtq_x_f16_u16): Likewise.
5722 (__arm_vcvtq_x_f16_s16): Likewise.
5723 (__arm_vcvtq_x_f32_s32): Likewise.
5724 (__arm_vcvtq_x_f32_u32): Likewise.
5725 (__arm_vcvtq_x_n_f16_s16): Likewise.
5726 (__arm_vcvtq_x_n_f16_u16): Likewise.
5727 (__arm_vcvtq_x_n_f32_s32): Likewise.
5728 (__arm_vcvtq_x_n_f32_u32): Likewise.
5729 (__arm_vcvtq_x_s16_f16): Likewise.
5730 (__arm_vcvtq_x_s32_f32): Likewise.
5731 (__arm_vcvtq_x_u16_f16): Likewise.
5732 (__arm_vcvtq_x_u32_f32): Likewise.
5733 (__arm_vcvtq_x_n_s16_f16): Likewise.
5734 (__arm_vcvtq_x_n_s32_f32): Likewise.
5735 (__arm_vcvtq_x_n_u16_f16): Likewise.
5736 (__arm_vcvtq_x_n_u32_f32): Likewise.
5737 (__arm_vrndq_x_f16): Likewise.
5738 (__arm_vrndq_x_f32): Likewise.
5739 (__arm_vrndnq_x_f16): Likewise.
5740 (__arm_vrndnq_x_f32): Likewise.
5741 (__arm_vrndmq_x_f16): Likewise.
5742 (__arm_vrndmq_x_f32): Likewise.
5743 (__arm_vrndpq_x_f16): Likewise.
5744 (__arm_vrndpq_x_f32): Likewise.
5745 (__arm_vrndaq_x_f16): Likewise.
5746 (__arm_vrndaq_x_f32): Likewise.
5747 (__arm_vrndxq_x_f16): Likewise.
5748 (__arm_vrndxq_x_f32): Likewise.
5749 (__arm_vandq_x_f16): Likewise.
5750 (__arm_vandq_x_f32): Likewise.
5751 (__arm_vbicq_x_f16): Likewise.
5752 (__arm_vbicq_x_f32): Likewise.
5753 (__arm_vbrsrq_x_n_f16): Likewise.
5754 (__arm_vbrsrq_x_n_f32): Likewise.
5755 (__arm_veorq_x_f16): Likewise.
5756 (__arm_veorq_x_f32): Likewise.
5757 (__arm_vornq_x_f16): Likewise.
5758 (__arm_vornq_x_f32): Likewise.
5759 (__arm_vorrq_x_f16): Likewise.
5760 (__arm_vorrq_x_f32): Likewise.
5761 (__arm_vrev32q_x_f16): Likewise.
5762 (__arm_vrev64q_x_f16): Likewise.
5763 (__arm_vrev64q_x_f32): Likewise.
5764 (vabdq_x): Define polymorphic variant.
5765 (vabsq_x): Likewise.
5766 (vaddq_x): Likewise.
5767 (vandq_x): Likewise.
5768 (vbicq_x): Likewise.
5769 (vbrsrq_x): Likewise.
5770 (vcaddq_rot270_x): Likewise.
5771 (vcaddq_rot90_x): Likewise.
5772 (vcmulq_rot180_x): Likewise.
5773 (vcmulq_rot270_x): Likewise.
5774 (vcmulq_x): Likewise.
5775 (vcvtq_x): Likewise.
5776 (vcvtq_x_n): Likewise.
5777 (vcvtnq_m): Likewise.
5778 (veorq_x): Likewise.
5779 (vmaxnmq_x): Likewise.
5780 (vminnmq_x): Likewise.
5781 (vmulq_x): Likewise.
5782 (vnegq_x): Likewise.
5783 (vornq_x): Likewise.
5784 (vorrq_x): Likewise.
5785 (vrev32q_x): Likewise.
5786 (vrev64q_x): Likewise.
5787 (vrndaq_x): Likewise.
5788 (vrndmq_x): Likewise.
5789 (vrndnq_x): Likewise.
5790 (vrndpq_x): Likewise.
5791 (vrndq_x): Likewise.
5792 (vrndxq_x): Likewise.
5793 (vsubq_x): Likewise.
5794 (vcmulq_rot90_x): Likewise.
5796 (vclsq_x): Likewise.
5797 (vclzq_x): Likewise.
5798 (vhaddq_x): Likewise.
5799 (vhcaddq_rot270_x): Likewise.
5800 (vhcaddq_rot90_x): Likewise.
5801 (vhsubq_x): Likewise.
5802 (vmaxq_x): Likewise.
5803 (vminq_x): Likewise.
5804 (vmovlbq_x): Likewise.
5805 (vmovltq_x): Likewise.
5806 (vmulhq_x): Likewise.
5807 (vmullbq_int_x): Likewise.
5808 (vmullbq_poly_x): Likewise.
5809 (vmulltq_int_x): Likewise.
5810 (vmulltq_poly_x): Likewise.
5811 (vmvnq_x): Likewise.
5812 (vrev16q_x): Likewise.
5813 (vrhaddq_x): Likewise.
5814 (vrmulhq_x): Likewise.
5815 (vrshlq_x): Likewise.
5816 (vrshrq_x): Likewise.
5817 (vshllbq_x): Likewise.
5818 (vshlltq_x): Likewise.
5819 (vshlq_x_n): Likewise.
5820 (vshlq_x): Likewise.
5821 (vdwdupq_x_u8): Likewise.
5822 (vdwdupq_x_u16): Likewise.
5823 (vdwdupq_x_u32): Likewise.
5824 (viwdupq_x_u8): Likewise.
5825 (viwdupq_x_u16): Likewise.
5826 (viwdupq_x_u32): Likewise.
5827 (vidupq_x_u8): Likewise.
5828 (vddupq_x_u8): Likewise.
5829 (vidupq_x_u16): Likewise.
5830 (vddupq_x_u16): Likewise.
5831 (vidupq_x_u32): Likewise.
5832 (vddupq_x_u32): Likewise.
5833 (vshrq_x): Likewise.
5835 2020-03-20 Richard Biener <rguenther@suse.de>
5837 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
5838 to vectorize for CTOR defs.
5840 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5841 Andre Vieira <andre.simoesdiasvieira@arm.com>
5842 Mihail Ionescu <mihail.ionescu@arm.com>
5844 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin
5846 (LDRGBWBU_QUALIFIERS): Likewise.
5847 (LDRGBWBS_Z_QUALIFIERS): Likewise.
5848 (LDRGBWBU_Z_QUALIFIERS): Likewise.
5849 (STRSBWBS_QUALIFIERS): Likewise.
5850 (STRSBWBU_QUALIFIERS): Likewise.
5851 (STRSBWBS_P_QUALIFIERS): Likewise.
5852 (STRSBWBU_P_QUALIFIERS): Likewise.
5853 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro.
5854 (vldrdq_gather_base_wb_u64): Likewise.
5855 (vldrdq_gather_base_wb_z_s64): Likewise.
5856 (vldrdq_gather_base_wb_z_u64): Likewise.
5857 (vldrwq_gather_base_wb_f32): Likewise.
5858 (vldrwq_gather_base_wb_s32): Likewise.
5859 (vldrwq_gather_base_wb_u32): Likewise.
5860 (vldrwq_gather_base_wb_z_f32): Likewise.
5861 (vldrwq_gather_base_wb_z_s32): Likewise.
5862 (vldrwq_gather_base_wb_z_u32): Likewise.
5863 (vstrdq_scatter_base_wb_p_s64): Likewise.
5864 (vstrdq_scatter_base_wb_p_u64): Likewise.
5865 (vstrdq_scatter_base_wb_s64): Likewise.
5866 (vstrdq_scatter_base_wb_u64): Likewise.
5867 (vstrwq_scatter_base_wb_p_s32): Likewise.
5868 (vstrwq_scatter_base_wb_p_f32): Likewise.
5869 (vstrwq_scatter_base_wb_p_u32): Likewise.
5870 (vstrwq_scatter_base_wb_s32): Likewise.
5871 (vstrwq_scatter_base_wb_u32): Likewise.
5872 (vstrwq_scatter_base_wb_f32): Likewise.
5873 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic.
5874 (__arm_vldrdq_gather_base_wb_u64): Likewise.
5875 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
5876 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
5877 (__arm_vldrwq_gather_base_wb_s32): Likewise.
5878 (__arm_vldrwq_gather_base_wb_u32): Likewise.
5879 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
5880 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
5881 (__arm_vstrdq_scatter_base_wb_s64): Likewise.
5882 (__arm_vstrdq_scatter_base_wb_u64): Likewise.
5883 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
5884 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
5885 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
5886 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
5887 (__arm_vstrwq_scatter_base_wb_s32): Likewise.
5888 (__arm_vstrwq_scatter_base_wb_u32): Likewise.
5889 (__arm_vldrwq_gather_base_wb_f32): Likewise.
5890 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
5891 (__arm_vstrwq_scatter_base_wb_f32): Likewise.
5892 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
5893 (vstrwq_scatter_base_wb): Define polymorphic variant.
5894 (vstrwq_scatter_base_wb_p): Likewise.
5895 (vstrdq_scatter_base_wb_p): Likewise.
5896 (vstrdq_scatter_base_wb): Likewise.
5897 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin
5899 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL
5901 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
5902 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise.
5903 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
5904 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
5905 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise.
5906 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
5907 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
5908 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise.
5909 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
5910 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
5911 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise.
5912 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
5913 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
5914 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise.
5915 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
5916 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
5917 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise.
5918 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise.
5919 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
5920 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise.
5921 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
5922 (mve_vldrwq_gather_base_wb_fv4sf): Likewise.
5923 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
5924 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise.
5925 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
5926 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise.
5927 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
5928 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise.
5929 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
5931 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5932 Andre Vieira <andre.simoesdiasvieira@arm.com>
5933 Mihail Ionescu <mihail.ionescu@arm.com>
5935 * config/arm/arm-builtins.c
5936 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary
5938 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro.
5939 (vddupq_m_n_u32): Likewise.
5940 (vddupq_m_n_u16): Likewise.
5941 (vddupq_m_wb_u8): Likewise.
5942 (vddupq_m_wb_u16): Likewise.
5943 (vddupq_m_wb_u32): Likewise.
5944 (vddupq_n_u8): Likewise.
5945 (vddupq_n_u32): Likewise.
5946 (vddupq_n_u16): Likewise.
5947 (vddupq_wb_u8): Likewise.
5948 (vddupq_wb_u16): Likewise.
5949 (vddupq_wb_u32): Likewise.
5950 (vdwdupq_m_n_u8): Likewise.
5951 (vdwdupq_m_n_u32): Likewise.
5952 (vdwdupq_m_n_u16): Likewise.
5953 (vdwdupq_m_wb_u8): Likewise.
5954 (vdwdupq_m_wb_u32): Likewise.
5955 (vdwdupq_m_wb_u16): Likewise.
5956 (vdwdupq_n_u8): Likewise.
5957 (vdwdupq_n_u32): Likewise.
5958 (vdwdupq_n_u16): Likewise.
5959 (vdwdupq_wb_u8): Likewise.
5960 (vdwdupq_wb_u32): Likewise.
5961 (vdwdupq_wb_u16): Likewise.
5962 (vidupq_m_n_u8): Likewise.
5963 (vidupq_m_n_u32): Likewise.
5964 (vidupq_m_n_u16): Likewise.
5965 (vidupq_m_wb_u8): Likewise.
5966 (vidupq_m_wb_u16): Likewise.
5967 (vidupq_m_wb_u32): Likewise.
5968 (vidupq_n_u8): Likewise.
5969 (vidupq_n_u32): Likewise.
5970 (vidupq_n_u16): Likewise.
5971 (vidupq_wb_u8): Likewise.
5972 (vidupq_wb_u16): Likewise.
5973 (vidupq_wb_u32): Likewise.
5974 (viwdupq_m_n_u8): Likewise.
5975 (viwdupq_m_n_u32): Likewise.
5976 (viwdupq_m_n_u16): Likewise.
5977 (viwdupq_m_wb_u8): Likewise.
5978 (viwdupq_m_wb_u32): Likewise.
5979 (viwdupq_m_wb_u16): Likewise.
5980 (viwdupq_n_u8): Likewise.
5981 (viwdupq_n_u32): Likewise.
5982 (viwdupq_n_u16): Likewise.
5983 (viwdupq_wb_u8): Likewise.
5984 (viwdupq_wb_u32): Likewise.
5985 (viwdupq_wb_u16): Likewise.
5986 (__arm_vddupq_m_n_u8): Define intrinsic.
5987 (__arm_vddupq_m_n_u32): Likewise.
5988 (__arm_vddupq_m_n_u16): Likewise.
5989 (__arm_vddupq_m_wb_u8): Likewise.
5990 (__arm_vddupq_m_wb_u16): Likewise.
5991 (__arm_vddupq_m_wb_u32): Likewise.
5992 (__arm_vddupq_n_u8): Likewise.
5993 (__arm_vddupq_n_u32): Likewise.
5994 (__arm_vddupq_n_u16): Likewise.
5995 (__arm_vdwdupq_m_n_u8): Likewise.
5996 (__arm_vdwdupq_m_n_u32): Likewise.
5997 (__arm_vdwdupq_m_n_u16): Likewise.
5998 (__arm_vdwdupq_m_wb_u8): Likewise.
5999 (__arm_vdwdupq_m_wb_u32): Likewise.
6000 (__arm_vdwdupq_m_wb_u16): Likewise.
6001 (__arm_vdwdupq_n_u8): Likewise.
6002 (__arm_vdwdupq_n_u32): Likewise.
6003 (__arm_vdwdupq_n_u16): Likewise.
6004 (__arm_vdwdupq_wb_u8): Likewise.
6005 (__arm_vdwdupq_wb_u32): Likewise.
6006 (__arm_vdwdupq_wb_u16): Likewise.
6007 (__arm_vidupq_m_n_u8): Likewise.
6008 (__arm_vidupq_m_n_u32): Likewise.
6009 (__arm_vidupq_m_n_u16): Likewise.
6010 (__arm_vidupq_n_u8): Likewise.
6011 (__arm_vidupq_m_wb_u8): Likewise.
6012 (__arm_vidupq_m_wb_u16): Likewise.
6013 (__arm_vidupq_m_wb_u32): Likewise.
6014 (__arm_vidupq_n_u32): Likewise.
6015 (__arm_vidupq_n_u16): Likewise.
6016 (__arm_vidupq_wb_u8): Likewise.
6017 (__arm_vidupq_wb_u16): Likewise.
6018 (__arm_vidupq_wb_u32): Likewise.
6019 (__arm_vddupq_wb_u8): Likewise.
6020 (__arm_vddupq_wb_u16): Likewise.
6021 (__arm_vddupq_wb_u32): Likewise.
6022 (__arm_viwdupq_m_n_u8): Likewise.
6023 (__arm_viwdupq_m_n_u32): Likewise.
6024 (__arm_viwdupq_m_n_u16): Likewise.
6025 (__arm_viwdupq_m_wb_u8): Likewise.
6026 (__arm_viwdupq_m_wb_u32): Likewise.
6027 (__arm_viwdupq_m_wb_u16): Likewise.
6028 (__arm_viwdupq_n_u8): Likewise.
6029 (__arm_viwdupq_n_u32): Likewise.
6030 (__arm_viwdupq_n_u16): Likewise.
6031 (__arm_viwdupq_wb_u8): Likewise.
6032 (__arm_viwdupq_wb_u32): Likewise.
6033 (__arm_viwdupq_wb_u16): Likewise.
6034 (vidupq_m): Define polymorphic variant.
6035 (vddupq_m): Likewise.
6036 (vidupq_u16): Likewise.
6037 (vidupq_u32): Likewise.
6038 (vidupq_u8): Likewise.
6039 (vddupq_u16): Likewise.
6040 (vddupq_u32): Likewise.
6041 (vddupq_u8): Likewise.
6042 (viwdupq_m): Likewise.
6043 (viwdupq_u16): Likewise.
6044 (viwdupq_u32): Likewise.
6045 (viwdupq_u8): Likewise.
6046 (vdwdupq_m): Likewise.
6047 (vdwdupq_u16): Likewise.
6048 (vdwdupq_u32): Likewise.
6049 (vdwdupq_u8): Likewise.
6050 * config/arm/arm_mve_builtins.def
6051 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin
6053 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern.
6054 (mve_vidupq_u<mode>_insn): Likewise.
6055 (mve_vidupq_m_n_u<mode>): Likewise.
6056 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
6057 (mve_vddupq_n_u<mode>): Likewise.
6058 (mve_vddupq_u<mode>_insn): Likewise.
6059 (mve_vddupq_m_n_u<mode>): Likewise.
6060 (mve_vddupq_m_wb_u<mode>_insn): Likewise.
6061 (mve_vdwdupq_n_u<mode>): Likewise.
6062 (mve_vdwdupq_wb_u<mode>): Likewise.
6063 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
6064 (mve_vdwdupq_m_n_u<mode>): Likewise.
6065 (mve_vdwdupq_m_wb_u<mode>): Likewise.
6066 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
6067 (mve_viwdupq_n_u<mode>): Likewise.
6068 (mve_viwdupq_wb_u<mode>): Likewise.
6069 (mve_viwdupq_wb_u<mode>_insn): Likewise.
6070 (mve_viwdupq_m_n_u<mode>): Likewise.
6071 (mve_viwdupq_m_wb_u<mode>): Likewise.
6072 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
6074 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6076 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro.
6077 (vreinterpretq_s16_s64): Likewise.
6078 (vreinterpretq_s16_s8): Likewise.
6079 (vreinterpretq_s16_u16): Likewise.
6080 (vreinterpretq_s16_u32): Likewise.
6081 (vreinterpretq_s16_u64): Likewise.
6082 (vreinterpretq_s16_u8): Likewise.
6083 (vreinterpretq_s32_s16): Likewise.
6084 (vreinterpretq_s32_s64): Likewise.
6085 (vreinterpretq_s32_s8): Likewise.
6086 (vreinterpretq_s32_u16): Likewise.
6087 (vreinterpretq_s32_u32): Likewise.
6088 (vreinterpretq_s32_u64): Likewise.
6089 (vreinterpretq_s32_u8): Likewise.
6090 (vreinterpretq_s64_s16): Likewise.
6091 (vreinterpretq_s64_s32): Likewise.
6092 (vreinterpretq_s64_s8): Likewise.
6093 (vreinterpretq_s64_u16): Likewise.
6094 (vreinterpretq_s64_u32): Likewise.
6095 (vreinterpretq_s64_u64): Likewise.
6096 (vreinterpretq_s64_u8): Likewise.
6097 (vreinterpretq_s8_s16): Likewise.
6098 (vreinterpretq_s8_s32): Likewise.
6099 (vreinterpretq_s8_s64): Likewise.
6100 (vreinterpretq_s8_u16): Likewise.
6101 (vreinterpretq_s8_u32): Likewise.
6102 (vreinterpretq_s8_u64): Likewise.
6103 (vreinterpretq_s8_u8): Likewise.
6104 (vreinterpretq_u16_s16): Likewise.
6105 (vreinterpretq_u16_s32): Likewise.
6106 (vreinterpretq_u16_s64): Likewise.
6107 (vreinterpretq_u16_s8): Likewise.
6108 (vreinterpretq_u16_u32): Likewise.
6109 (vreinterpretq_u16_u64): Likewise.
6110 (vreinterpretq_u16_u8): Likewise.
6111 (vreinterpretq_u32_s16): Likewise.
6112 (vreinterpretq_u32_s32): Likewise.
6113 (vreinterpretq_u32_s64): Likewise.
6114 (vreinterpretq_u32_s8): Likewise.
6115 (vreinterpretq_u32_u16): Likewise.
6116 (vreinterpretq_u32_u64): Likewise.
6117 (vreinterpretq_u32_u8): Likewise.
6118 (vreinterpretq_u64_s16): Likewise.
6119 (vreinterpretq_u64_s32): Likewise.
6120 (vreinterpretq_u64_s64): Likewise.
6121 (vreinterpretq_u64_s8): Likewise.
6122 (vreinterpretq_u64_u16): Likewise.
6123 (vreinterpretq_u64_u32): Likewise.
6124 (vreinterpretq_u64_u8): Likewise.
6125 (vreinterpretq_u8_s16): Likewise.
6126 (vreinterpretq_u8_s32): Likewise.
6127 (vreinterpretq_u8_s64): Likewise.
6128 (vreinterpretq_u8_s8): Likewise.
6129 (vreinterpretq_u8_u16): Likewise.
6130 (vreinterpretq_u8_u32): Likewise.
6131 (vreinterpretq_u8_u64): Likewise.
6132 (vreinterpretq_s32_f16): Likewise.
6133 (vreinterpretq_s32_f32): Likewise.
6134 (vreinterpretq_u16_f16): Likewise.
6135 (vreinterpretq_u16_f32): Likewise.
6136 (vreinterpretq_u32_f16): Likewise.
6137 (vreinterpretq_u32_f32): Likewise.
6138 (vreinterpretq_u64_f16): Likewise.
6139 (vreinterpretq_u64_f32): Likewise.
6140 (vreinterpretq_u8_f16): Likewise.
6141 (vreinterpretq_u8_f32): Likewise.
6142 (vreinterpretq_f16_f32): Likewise.
6143 (vreinterpretq_f16_s16): Likewise.
6144 (vreinterpretq_f16_s32): Likewise.
6145 (vreinterpretq_f16_s64): Likewise.
6146 (vreinterpretq_f16_s8): Likewise.
6147 (vreinterpretq_f16_u16): Likewise.
6148 (vreinterpretq_f16_u32): Likewise.
6149 (vreinterpretq_f16_u64): Likewise.
6150 (vreinterpretq_f16_u8): Likewise.
6151 (vreinterpretq_f32_f16): Likewise.
6152 (vreinterpretq_f32_s16): Likewise.
6153 (vreinterpretq_f32_s32): Likewise.
6154 (vreinterpretq_f32_s64): Likewise.
6155 (vreinterpretq_f32_s8): Likewise.
6156 (vreinterpretq_f32_u16): Likewise.
6157 (vreinterpretq_f32_u32): Likewise.
6158 (vreinterpretq_f32_u64): Likewise.
6159 (vreinterpretq_f32_u8): Likewise.
6160 (vreinterpretq_s16_f16): Likewise.
6161 (vreinterpretq_s16_f32): Likewise.
6162 (vreinterpretq_s64_f16): Likewise.
6163 (vreinterpretq_s64_f32): Likewise.
6164 (vreinterpretq_s8_f16): Likewise.
6165 (vreinterpretq_s8_f32): Likewise.
6166 (vuninitializedq_u8): Likewise.
6167 (vuninitializedq_u16): Likewise.
6168 (vuninitializedq_u32): Likewise.
6169 (vuninitializedq_u64): Likewise.
6170 (vuninitializedq_s8): Likewise.
6171 (vuninitializedq_s16): Likewise.
6172 (vuninitializedq_s32): Likewise.
6173 (vuninitializedq_s64): Likewise.
6174 (vuninitializedq_f16): Likewise.
6175 (vuninitializedq_f32): Likewise.
6176 (__arm_vuninitializedq_u8): Define intrinsic.
6177 (__arm_vuninitializedq_u16): Likewise.
6178 (__arm_vuninitializedq_u32): Likewise.
6179 (__arm_vuninitializedq_u64): Likewise.
6180 (__arm_vuninitializedq_s8): Likewise.
6181 (__arm_vuninitializedq_s16): Likewise.
6182 (__arm_vuninitializedq_s32): Likewise.
6183 (__arm_vuninitializedq_s64): Likewise.
6184 (__arm_vreinterpretq_s16_s32): Likewise.
6185 (__arm_vreinterpretq_s16_s64): Likewise.
6186 (__arm_vreinterpretq_s16_s8): Likewise.
6187 (__arm_vreinterpretq_s16_u16): Likewise.
6188 (__arm_vreinterpretq_s16_u32): Likewise.
6189 (__arm_vreinterpretq_s16_u64): Likewise.
6190 (__arm_vreinterpretq_s16_u8): Likewise.
6191 (__arm_vreinterpretq_s32_s16): Likewise.
6192 (__arm_vreinterpretq_s32_s64): Likewise.
6193 (__arm_vreinterpretq_s32_s8): Likewise.
6194 (__arm_vreinterpretq_s32_u16): Likewise.
6195 (__arm_vreinterpretq_s32_u32): Likewise.
6196 (__arm_vreinterpretq_s32_u64): Likewise.
6197 (__arm_vreinterpretq_s32_u8): Likewise.
6198 (__arm_vreinterpretq_s64_s16): Likewise.
6199 (__arm_vreinterpretq_s64_s32): Likewise.
6200 (__arm_vreinterpretq_s64_s8): Likewise.
6201 (__arm_vreinterpretq_s64_u16): Likewise.
6202 (__arm_vreinterpretq_s64_u32): Likewise.
6203 (__arm_vreinterpretq_s64_u64): Likewise.
6204 (__arm_vreinterpretq_s64_u8): Likewise.
6205 (__arm_vreinterpretq_s8_s16): Likewise.
6206 (__arm_vreinterpretq_s8_s32): Likewise.
6207 (__arm_vreinterpretq_s8_s64): Likewise.
6208 (__arm_vreinterpretq_s8_u16): Likewise.
6209 (__arm_vreinterpretq_s8_u32): Likewise.
6210 (__arm_vreinterpretq_s8_u64): Likewise.
6211 (__arm_vreinterpretq_s8_u8): Likewise.
6212 (__arm_vreinterpretq_u16_s16): Likewise.
6213 (__arm_vreinterpretq_u16_s32): Likewise.
6214 (__arm_vreinterpretq_u16_s64): Likewise.
6215 (__arm_vreinterpretq_u16_s8): Likewise.
6216 (__arm_vreinterpretq_u16_u32): Likewise.
6217 (__arm_vreinterpretq_u16_u64): Likewise.
6218 (__arm_vreinterpretq_u16_u8): Likewise.
6219 (__arm_vreinterpretq_u32_s16): Likewise.
6220 (__arm_vreinterpretq_u32_s32): Likewise.
6221 (__arm_vreinterpretq_u32_s64): Likewise.
6222 (__arm_vreinterpretq_u32_s8): Likewise.
6223 (__arm_vreinterpretq_u32_u16): Likewise.
6224 (__arm_vreinterpretq_u32_u64): Likewise.
6225 (__arm_vreinterpretq_u32_u8): Likewise.
6226 (__arm_vreinterpretq_u64_s16): Likewise.
6227 (__arm_vreinterpretq_u64_s32): Likewise.
6228 (__arm_vreinterpretq_u64_s64): Likewise.
6229 (__arm_vreinterpretq_u64_s8): Likewise.
6230 (__arm_vreinterpretq_u64_u16): Likewise.
6231 (__arm_vreinterpretq_u64_u32): Likewise.
6232 (__arm_vreinterpretq_u64_u8): Likewise.
6233 (__arm_vreinterpretq_u8_s16): Likewise.
6234 (__arm_vreinterpretq_u8_s32): Likewise.
6235 (__arm_vreinterpretq_u8_s64): Likewise.
6236 (__arm_vreinterpretq_u8_s8): Likewise.
6237 (__arm_vreinterpretq_u8_u16): Likewise.
6238 (__arm_vreinterpretq_u8_u32): Likewise.
6239 (__arm_vreinterpretq_u8_u64): Likewise.
6240 (__arm_vuninitializedq_f16): Likewise.
6241 (__arm_vuninitializedq_f32): Likewise.
6242 (__arm_vreinterpretq_s32_f16): Likewise.
6243 (__arm_vreinterpretq_s32_f32): Likewise.
6244 (__arm_vreinterpretq_s16_f16): Likewise.
6245 (__arm_vreinterpretq_s16_f32): Likewise.
6246 (__arm_vreinterpretq_s64_f16): Likewise.
6247 (__arm_vreinterpretq_s64_f32): Likewise.
6248 (__arm_vreinterpretq_s8_f16): Likewise.
6249 (__arm_vreinterpretq_s8_f32): Likewise.
6250 (__arm_vreinterpretq_u16_f16): Likewise.
6251 (__arm_vreinterpretq_u16_f32): Likewise.
6252 (__arm_vreinterpretq_u32_f16): Likewise.
6253 (__arm_vreinterpretq_u32_f32): Likewise.
6254 (__arm_vreinterpretq_u64_f16): Likewise.
6255 (__arm_vreinterpretq_u64_f32): Likewise.
6256 (__arm_vreinterpretq_u8_f16): Likewise.
6257 (__arm_vreinterpretq_u8_f32): Likewise.
6258 (__arm_vreinterpretq_f16_f32): Likewise.
6259 (__arm_vreinterpretq_f16_s16): Likewise.
6260 (__arm_vreinterpretq_f16_s32): Likewise.
6261 (__arm_vreinterpretq_f16_s64): Likewise.
6262 (__arm_vreinterpretq_f16_s8): Likewise.
6263 (__arm_vreinterpretq_f16_u16): Likewise.
6264 (__arm_vreinterpretq_f16_u32): Likewise.
6265 (__arm_vreinterpretq_f16_u64): Likewise.
6266 (__arm_vreinterpretq_f16_u8): Likewise.
6267 (__arm_vreinterpretq_f32_f16): Likewise.
6268 (__arm_vreinterpretq_f32_s16): Likewise.
6269 (__arm_vreinterpretq_f32_s32): Likewise.
6270 (__arm_vreinterpretq_f32_s64): Likewise.
6271 (__arm_vreinterpretq_f32_s8): Likewise.
6272 (__arm_vreinterpretq_f32_u16): Likewise.
6273 (__arm_vreinterpretq_f32_u32): Likewise.
6274 (__arm_vreinterpretq_f32_u64): Likewise.
6275 (__arm_vreinterpretq_f32_u8): Likewise.
6276 (vuninitializedq): Define polymorphic variant.
6277 (vreinterpretq_f16): Likewise.
6278 (vreinterpretq_f32): Likewise.
6279 (vreinterpretq_s16): Likewise.
6280 (vreinterpretq_s32): Likewise.
6281 (vreinterpretq_s64): Likewise.
6282 (vreinterpretq_s8): Likewise.
6283 (vreinterpretq_u16): Likewise.
6284 (vreinterpretq_u32): Likewise.
6285 (vreinterpretq_u64): Likewise.
6286 (vreinterpretq_u8): Likewise.
6288 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6289 Andre Vieira <andre.simoesdiasvieira@arm.com>
6290 Mihail Ionescu <mihail.ionescu@arm.com>
6292 * config/arm/arm_mve.h (vaddq_s8): Define macro.
6293 (vaddq_s16): Likewise.
6294 (vaddq_s32): Likewise.
6295 (vaddq_u8): Likewise.
6296 (vaddq_u16): Likewise.
6297 (vaddq_u32): Likewise.
6298 (vaddq_f16): Likewise.
6299 (vaddq_f32): Likewise.
6300 (__arm_vaddq_s8): Define intrinsic.
6301 (__arm_vaddq_s16): Likewise.
6302 (__arm_vaddq_s32): Likewise.
6303 (__arm_vaddq_u8): Likewise.
6304 (__arm_vaddq_u16): Likewise.
6305 (__arm_vaddq_u32): Likewise.
6306 (__arm_vaddq_f16): Likewise.
6307 (__arm_vaddq_f32): Likewise.
6308 (vaddq): Define polymorphic variant.
6309 * config/arm/iterators.md (VNIM): Define mode iterator for common types
6310 Neon, IWMMXT and MVE.
6311 (VNINOTM): Likewise.
6312 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
6313 (mve_vaddq_f<mode>): Define RTL pattern.
6314 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
6315 (addv8hf3_neon): Define RTL pattern.
6316 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
6318 (addv8hf3): Define standard RTL pattern for MVE and Neon.
6319 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.
6321 2020-03-20 Martin Liska <mliska@suse.cz>
6324 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously
6325 build_ref_for_offset function was used and it transforms off to bytes
6328 2020-03-20 Richard Biener <rguenther@suse.de>
6330 PR tree-optimization/94266
6331 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the
6332 type of the underlying object to adjust for the containing
6335 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6337 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
6338 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
6339 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
6341 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6343 * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
6345 2020-03-20 Jakub Jelinek <jakub@redhat.com>
6347 PR tree-optimization/94224
6348 * gimple-ssa-store-merging.c
6349 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping
6350 or adjacent INTEGER_CST rhs_code stores as mergeable if they have
6353 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6355 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve.
6357 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6360 * cgraph.c (cgraph_node::function_symbol): Fix availability computation.
6361 (cgraph_node::function_or_virtual_thunk_symbol): Likewise.
6363 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6366 * cgraphunit.c (process_function_and_variable_attributes): warn
6367 for flatten attribute on alias.
6368 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias.
6370 2020-03-19 Martin Liska <mliska@suse.cz>
6372 * lto-section-in.c: Add ext_symtab.
6373 * lto-streamer-out.c (write_symbol_extension_info): New.
6374 (produce_symtab_extension): New.
6375 (produce_asm_for_decls): Stream also produce_symtab_extension.
6376 * lto-streamer.h (enum lto_section_type): New section.
6378 2020-03-19 Jakub Jelinek <jakub@redhat.com>
6380 PR tree-optimization/94211
6381 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
6382 instead of estimate_num_insns for bb_seq (middle_bb). Rename
6383 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
6386 2020-03-19 Richard Biener <rguenther@suse.de>
6389 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr
6390 and build_ref_for_offset.
6392 2020-03-19 Richard Biener <rguenther@suse.de>
6395 * fold-const.c (fold_binary_loc): Avoid using
6396 build_fold_addr_expr when we really want an ADDR_EXPR.
6398 2020-03-18 Segher Boessenkool <segher@kernel.crashing.org>
6400 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented
6403 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
6405 PR rtl-optimization/90275
6406 * cse.c (cse_insn): Delete no-op register moves too.
6408 2020-03-18 Martin Sebor <msebor@redhat.com>
6411 * cgraphunit.c (process_function_and_variable_attributes): Also
6412 complain about weakref function definitions and drop all effects
6415 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6416 Mihail Ionescu <mihail.ionescu@arm.com>
6417 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6419 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
6420 (vstrdq_scatter_base_p_u64): Likewise.
6421 (vstrdq_scatter_base_s64): Likewise.
6422 (vstrdq_scatter_base_u64): Likewise.
6423 (vstrdq_scatter_offset_p_s64): Likewise.
6424 (vstrdq_scatter_offset_p_u64): Likewise.
6425 (vstrdq_scatter_offset_s64): Likewise.
6426 (vstrdq_scatter_offset_u64): Likewise.
6427 (vstrdq_scatter_shifted_offset_p_s64): Likewise.
6428 (vstrdq_scatter_shifted_offset_p_u64): Likewise.
6429 (vstrdq_scatter_shifted_offset_s64): Likewise.
6430 (vstrdq_scatter_shifted_offset_u64): Likewise.
6431 (vstrhq_scatter_offset_f16): Likewise.
6432 (vstrhq_scatter_offset_p_f16): Likewise.
6433 (vstrhq_scatter_shifted_offset_f16): Likewise.
6434 (vstrhq_scatter_shifted_offset_p_f16): Likewise.
6435 (vstrwq_scatter_base_f32): Likewise.
6436 (vstrwq_scatter_base_p_f32): Likewise.
6437 (vstrwq_scatter_offset_f32): Likewise.
6438 (vstrwq_scatter_offset_p_f32): Likewise.
6439 (vstrwq_scatter_offset_p_s32): Likewise.
6440 (vstrwq_scatter_offset_p_u32): Likewise.
6441 (vstrwq_scatter_offset_s32): Likewise.
6442 (vstrwq_scatter_offset_u32): Likewise.
6443 (vstrwq_scatter_shifted_offset_f32): Likewise.
6444 (vstrwq_scatter_shifted_offset_p_f32): Likewise.
6445 (vstrwq_scatter_shifted_offset_p_s32): Likewise.
6446 (vstrwq_scatter_shifted_offset_p_u32): Likewise.
6447 (vstrwq_scatter_shifted_offset_s32): Likewise.
6448 (vstrwq_scatter_shifted_offset_u32): Likewise.
6449 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
6450 (__arm_vstrdq_scatter_base_p_u64): Likewise.
6451 (__arm_vstrdq_scatter_base_s64): Likewise.
6452 (__arm_vstrdq_scatter_base_u64): Likewise.
6453 (__arm_vstrdq_scatter_offset_p_s64): Likewise.
6454 (__arm_vstrdq_scatter_offset_p_u64): Likewise.
6455 (__arm_vstrdq_scatter_offset_s64): Likewise.
6456 (__arm_vstrdq_scatter_offset_u64): Likewise.
6457 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
6458 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
6459 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
6460 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
6461 (__arm_vstrwq_scatter_offset_p_s32): Likewise.
6462 (__arm_vstrwq_scatter_offset_p_u32): Likewise.
6463 (__arm_vstrwq_scatter_offset_s32): Likewise.
6464 (__arm_vstrwq_scatter_offset_u32): Likewise.
6465 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
6466 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
6467 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
6468 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
6469 (__arm_vstrhq_scatter_offset_f16): Likewise.
6470 (__arm_vstrhq_scatter_offset_p_f16): Likewise.
6471 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
6472 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
6473 (__arm_vstrwq_scatter_base_f32): Likewise.
6474 (__arm_vstrwq_scatter_base_p_f32): Likewise.
6475 (__arm_vstrwq_scatter_offset_f32): Likewise.
6476 (__arm_vstrwq_scatter_offset_p_f32): Likewise.
6477 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
6478 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
6479 (vstrhq_scatter_offset): Define polymorphic variant.
6480 (vstrhq_scatter_offset_p): Likewise.
6481 (vstrhq_scatter_shifted_offset): Likewise.
6482 (vstrhq_scatter_shifted_offset_p): Likewise.
6483 (vstrwq_scatter_base): Likewise.
6484 (vstrwq_scatter_base_p): Likewise.
6485 (vstrwq_scatter_offset): Likewise.
6486 (vstrwq_scatter_offset_p): Likewise.
6487 (vstrwq_scatter_shifted_offset): Likewise.
6488 (vstrwq_scatter_shifted_offset_p): Likewise.
6489 (vstrdq_scatter_base_p): Likewise.
6490 (vstrdq_scatter_base): Likewise.
6491 (vstrdq_scatter_offset_p): Likewise.
6492 (vstrdq_scatter_offset): Likewise.
6493 (vstrdq_scatter_shifted_offset_p): Likewise.
6494 (vstrdq_scatter_shifted_offset): Likewise.
6495 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
6496 (STRSBS_P): Likewise.
6498 (STRSBU_P): Likewise.
6500 (STRSS_P): Likewise.
6502 (STRSU_P): Likewise.
6503 * config/arm/constraints.md (Ri): Define.
6504 * config/arm/mve.md (VSTRDSBQ): Define iterator.
6505 (VSTRDSOQ): Likewise.
6506 (VSTRDSSOQ): Likewise.
6507 (VSTRWSOQ): Likewise.
6508 (VSTRWSSOQ): Likewise.
6509 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
6510 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
6511 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
6512 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
6513 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
6514 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
6515 (mve_vstrhq_scatter_offset_fv8hf): Likewise.
6516 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
6517 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
6518 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
6519 (mve_vstrwq_scatter_base_fv4sf): Likewise.
6520 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
6521 (mve_vstrwq_scatter_offset_fv4sf): Likewise.
6522 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
6523 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
6524 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
6525 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
6526 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
6527 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
6528 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
6529 * config/arm/predicates.md (Ri): Define predicate to check immediate
6530 is the range +/-1016 and multiple of 8.
6532 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6533 Mihail Ionescu <mihail.ionescu@arm.com>
6534 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6536 * config/arm/arm_mve.h (vst1q_f32): Define macro.
6537 (vst1q_f16): Likewise.
6538 (vst1q_s8): Likewise.
6539 (vst1q_s32): Likewise.
6540 (vst1q_s16): Likewise.
6541 (vst1q_u8): Likewise.
6542 (vst1q_u32): Likewise.
6543 (vst1q_u16): Likewise.
6544 (vstrhq_f16): Likewise.
6545 (vstrhq_scatter_offset_s32): Likewise.
6546 (vstrhq_scatter_offset_s16): Likewise.
6547 (vstrhq_scatter_offset_u32): Likewise.
6548 (vstrhq_scatter_offset_u16): Likewise.
6549 (vstrhq_scatter_offset_p_s32): Likewise.
6550 (vstrhq_scatter_offset_p_s16): Likewise.
6551 (vstrhq_scatter_offset_p_u32): Likewise.
6552 (vstrhq_scatter_offset_p_u16): Likewise.
6553 (vstrhq_scatter_shifted_offset_s32): Likewise.
6554 (vstrhq_scatter_shifted_offset_s16): Likewise.
6555 (vstrhq_scatter_shifted_offset_u32): Likewise.
6556 (vstrhq_scatter_shifted_offset_u16): Likewise.
6557 (vstrhq_scatter_shifted_offset_p_s32): Likewise.
6558 (vstrhq_scatter_shifted_offset_p_s16): Likewise.
6559 (vstrhq_scatter_shifted_offset_p_u32): Likewise.
6560 (vstrhq_scatter_shifted_offset_p_u16): Likewise.
6561 (vstrhq_s32): Likewise.
6562 (vstrhq_s16): Likewise.
6563 (vstrhq_u32): Likewise.
6564 (vstrhq_u16): Likewise.
6565 (vstrhq_p_f16): Likewise.
6566 (vstrhq_p_s32): Likewise.
6567 (vstrhq_p_s16): Likewise.
6568 (vstrhq_p_u32): Likewise.
6569 (vstrhq_p_u16): Likewise.
6570 (vstrwq_f32): Likewise.
6571 (vstrwq_s32): Likewise.
6572 (vstrwq_u32): Likewise.
6573 (vstrwq_p_f32): Likewise.
6574 (vstrwq_p_s32): Likewise.
6575 (vstrwq_p_u32): Likewise.
6576 (__arm_vst1q_s8): Define intrinsic.
6577 (__arm_vst1q_s32): Likewise.
6578 (__arm_vst1q_s16): Likewise.
6579 (__arm_vst1q_u8): Likewise.
6580 (__arm_vst1q_u32): Likewise.
6581 (__arm_vst1q_u16): Likewise.
6582 (__arm_vstrhq_scatter_offset_s32): Likewise.
6583 (__arm_vstrhq_scatter_offset_s16): Likewise.
6584 (__arm_vstrhq_scatter_offset_u32): Likewise.
6585 (__arm_vstrhq_scatter_offset_u16): Likewise.
6586 (__arm_vstrhq_scatter_offset_p_s32): Likewise.
6587 (__arm_vstrhq_scatter_offset_p_s16): Likewise.
6588 (__arm_vstrhq_scatter_offset_p_u32): Likewise.
6589 (__arm_vstrhq_scatter_offset_p_u16): Likewise.
6590 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
6591 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
6592 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
6593 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
6594 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
6595 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
6596 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
6597 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
6598 (__arm_vstrhq_s32): Likewise.
6599 (__arm_vstrhq_s16): Likewise.
6600 (__arm_vstrhq_u32): Likewise.
6601 (__arm_vstrhq_u16): Likewise.
6602 (__arm_vstrhq_p_s32): Likewise.
6603 (__arm_vstrhq_p_s16): Likewise.
6604 (__arm_vstrhq_p_u32): Likewise.
6605 (__arm_vstrhq_p_u16): Likewise.
6606 (__arm_vstrwq_s32): Likewise.
6607 (__arm_vstrwq_u32): Likewise.
6608 (__arm_vstrwq_p_s32): Likewise.
6609 (__arm_vstrwq_p_u32): Likewise.
6610 (__arm_vstrwq_p_f32): Likewise.
6611 (__arm_vstrwq_f32): Likewise.
6612 (__arm_vst1q_f32): Likewise.
6613 (__arm_vst1q_f16): Likewise.
6614 (__arm_vstrhq_f16): Likewise.
6615 (__arm_vstrhq_p_f16): Likewise.
6616 (vst1q): Define polymorphic variant.
6618 (vstrhq_p): Likewise.
6619 (vstrhq_scatter_offset_p): Likewise.
6620 (vstrhq_scatter_offset): Likewise.
6621 (vstrhq_scatter_shifted_offset_p): Likewise.
6622 (vstrhq_scatter_shifted_offset): Likewise.
6623 (vstrwq_p): Likewise.
6625 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
6628 (STRSS_P): Likewise.
6630 (STRSU_P): Likewise.
6633 * config/arm/mve.md (VST1Q): Define iterator.
6634 (VSTRHSOQ): Likewise.
6635 (VSTRHSSOQ): Likewise.
6638 (mve_vstrhq_fv8hf): Define RTL pattern.
6639 (mve_vstrhq_p_fv8hf): Likewise.
6640 (mve_vstrhq_p_<supf><mode>): Likewise.
6641 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
6642 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
6643 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
6644 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
6645 (mve_vstrhq_<supf><mode>): Likewise.
6646 (mve_vstrwq_fv4sf): Likewise.
6647 (mve_vstrwq_p_fv4sf): Likewise.
6648 (mve_vstrwq_p_<supf>v4si): Likewise.
6649 (mve_vstrwq_<supf>v4si): Likewise.
6650 (mve_vst1q_f<mode>): Define expand.
6651 (mve_vst1q_<supf><mode>): Likewise.
6653 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6654 Mihail Ionescu <mihail.ionescu@arm.com>
6655 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6657 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6658 (vld1q_s32): Likewise.
6659 (vld1q_s16): Likewise.
6660 (vld1q_u8): Likewise.
6661 (vld1q_u32): Likewise.
6662 (vld1q_u16): Likewise.
6663 (vldrhq_gather_offset_s32): Likewise.
6664 (vldrhq_gather_offset_s16): Likewise.
6665 (vldrhq_gather_offset_u32): Likewise.
6666 (vldrhq_gather_offset_u16): Likewise.
6667 (vldrhq_gather_offset_z_s32): Likewise.
6668 (vldrhq_gather_offset_z_s16): Likewise.
6669 (vldrhq_gather_offset_z_u32): Likewise.
6670 (vldrhq_gather_offset_z_u16): Likewise.
6671 (vldrhq_gather_shifted_offset_s32): Likewise.
6672 (vldrhq_gather_shifted_offset_s16): Likewise.
6673 (vldrhq_gather_shifted_offset_u32): Likewise.
6674 (vldrhq_gather_shifted_offset_u16): Likewise.
6675 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6676 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6677 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6678 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6679 (vldrhq_s32): Likewise.
6680 (vldrhq_s16): Likewise.
6681 (vldrhq_u32): Likewise.
6682 (vldrhq_u16): Likewise.
6683 (vldrhq_z_s32): Likewise.
6684 (vldrhq_z_s16): Likewise.
6685 (vldrhq_z_u32): Likewise.
6686 (vldrhq_z_u16): Likewise.
6687 (vldrwq_s32): Likewise.
6688 (vldrwq_u32): Likewise.
6689 (vldrwq_z_s32): Likewise.
6690 (vldrwq_z_u32): Likewise.
6691 (vld1q_f32): Likewise.
6692 (vld1q_f16): Likewise.
6693 (vldrhq_f16): Likewise.
6694 (vldrhq_z_f16): Likewise.
6695 (vldrwq_f32): Likewise.
6696 (vldrwq_z_f32): Likewise.
6697 (__arm_vld1q_s8): Define intrinsic.
6698 (__arm_vld1q_s32): Likewise.
6699 (__arm_vld1q_s16): Likewise.
6700 (__arm_vld1q_u8): Likewise.
6701 (__arm_vld1q_u32): Likewise.
6702 (__arm_vld1q_u16): Likewise.
6703 (__arm_vldrhq_gather_offset_s32): Likewise.
6704 (__arm_vldrhq_gather_offset_s16): Likewise.
6705 (__arm_vldrhq_gather_offset_u32): Likewise.
6706 (__arm_vldrhq_gather_offset_u16): Likewise.
6707 (__arm_vldrhq_gather_offset_z_s32): Likewise.
6708 (__arm_vldrhq_gather_offset_z_s16): Likewise.
6709 (__arm_vldrhq_gather_offset_z_u32): Likewise.
6710 (__arm_vldrhq_gather_offset_z_u16): Likewise.
6711 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
6712 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
6713 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
6714 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
6715 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
6716 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
6717 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
6718 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
6719 (__arm_vldrhq_s32): Likewise.
6720 (__arm_vldrhq_s16): Likewise.
6721 (__arm_vldrhq_u32): Likewise.
6722 (__arm_vldrhq_u16): Likewise.
6723 (__arm_vldrhq_z_s32): Likewise.
6724 (__arm_vldrhq_z_s16): Likewise.
6725 (__arm_vldrhq_z_u32): Likewise.
6726 (__arm_vldrhq_z_u16): Likewise.
6727 (__arm_vldrwq_s32): Likewise.
6728 (__arm_vldrwq_u32): Likewise.
6729 (__arm_vldrwq_z_s32): Likewise.
6730 (__arm_vldrwq_z_u32): Likewise.
6731 (__arm_vld1q_f32): Likewise.
6732 (__arm_vld1q_f16): Likewise.
6733 (__arm_vldrwq_f32): Likewise.
6734 (__arm_vldrwq_z_f32): Likewise.
6735 (__arm_vldrhq_z_f16): Likewise.
6736 (__arm_vldrhq_f16): Likewise.
6737 (vld1q): Define polymorphic variant.
6738 (vldrhq_gather_offset): Likewise.
6739 (vldrhq_gather_offset_z): Likewise.
6740 (vldrhq_gather_shifted_offset): Likewise.
6741 (vldrhq_gather_shifted_offset_z): Likewise.
6742 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
6746 (LDRGU_Z): Likewise.
6748 (LDRGS_Z): Likewise.
6750 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
6751 (V_sz_elem1): Likewise.
6752 (VLD1Q): Define iterator.
6753 (VLDRHGOQ): Likewise.
6754 (VLDRHGSOQ): Likewise.
6757 (mve_vldrhq_fv8hf): Define RTL pattern.
6758 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
6759 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
6760 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
6761 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
6762 (mve_vldrhq_<supf><mode>): Likewise.
6763 (mve_vldrhq_z_fv8hf): Likewise.
6764 (mve_vldrhq_z_<supf><mode>): Likewise.
6765 (mve_vldrwq_fv4sf): Likewise.
6766 (mve_vldrwq_<supf>v4si): Likewise.
6767 (mve_vldrwq_z_fv4sf): Likewise.
6768 (mve_vldrwq_z_<supf>v4si): Likewise.
6769 (mve_vld1q_f<mode>): Define RTL expand pattern.
6770 (mve_vld1q_<supf><mode>): Likewise.
6772 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6773 Mihail Ionescu <mihail.ionescu@arm.com>
6774 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6776 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6777 (vld1q_s32): Likewise.
6778 (vld1q_s16): Likewise.
6779 (vld1q_u8): Likewise.
6780 (vld1q_u32): Likewise.
6781 (vld1q_u16): Likewise.
6782 (vldrhq_gather_offset_s32): Likewise.
6783 (vldrhq_gather_offset_s16): Likewise.
6784 (vldrhq_gather_offset_u32): Likewise.
6785 (vldrhq_gather_offset_u16): Likewise.
6786 (vldrhq_gather_offset_z_s32): Likewise.
6787 (vldrhq_gather_offset_z_s16): Likewise.
6788 (vldrhq_gather_offset_z_u32): Likewise.
6789 (vldrhq_gather_offset_z_u16): Likewise.
6790 (vldrhq_gather_shifted_offset_s32): Likewise.
6791 (vldrhq_gather_shifted_offset_s16): Likewise.
6792 (vldrhq_gather_shifted_offset_u32): Likewise.
6793 (vldrhq_gather_shifted_offset_u16): Likewise.
6794 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6795 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6796 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6797 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6798 (vldrhq_s32): Likewise.
6799 (vldrhq_s16): Likewise.
6800 (vldrhq_u32): Likewise.
6801 (vldrhq_u16): Likewise.
6802 (vldrhq_z_s32): Likewise.
6803 (vldrhq_z_s16): Likewise.
6804 (vldrhq_z_u32): Likewise.
6805 (vldrhq_z_u16): Likewise.
6806 (vldrwq_s32): Likewise.
6807 (vldrwq_u32): Likewise.
6808 (vldrwq_z_s32): Likewise.
6809 (vldrwq_z_u32): Likewise.
6810 (vld1q_f32): Likewise.
6811 (vld1q_f16): Likewise.
6812 (vldrhq_f16): Likewise.
6813 (vldrhq_z_f16): Likewise.
6814 (vldrwq_f32): Likewise.
6815 (vldrwq_z_f32): Likewise.
6816 (__arm_vld1q_s8): Define intrinsic.
6817 (__arm_vld1q_s32): Likewise.
6818 (__arm_vld1q_s16): Likewise.
6819 (__arm_vld1q_u8): Likewise.
6820 (__arm_vld1q_u32): Likewise.
6821 (__arm_vld1q_u16): Likewise.
6822 (__arm_vldrhq_gather_offset_s32): Likewise.
6823 (__arm_vldrhq_gather_offset_s16): Likewise.
6824 (__arm_vldrhq_gather_offset_u32): Likewise.
6825 (__arm_vldrhq_gather_offset_u16): Likewise.
6826 (__arm_vldrhq_gather_offset_z_s32): Likewise.
6827 (__arm_vldrhq_gather_offset_z_s16): Likewise.
6828 (__arm_vldrhq_gather_offset_z_u32): Likewise.
6829 (__arm_vldrhq_gather_offset_z_u16): Likewise.
6830 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
6831 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
6832 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
6833 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
6834 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
6835 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
6836 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
6837 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
6838 (__arm_vldrhq_s32): Likewise.
6839 (__arm_vldrhq_s16): Likewise.
6840 (__arm_vldrhq_u32): Likewise.
6841 (__arm_vldrhq_u16): Likewise.
6842 (__arm_vldrhq_z_s32): Likewise.
6843 (__arm_vldrhq_z_s16): Likewise.
6844 (__arm_vldrhq_z_u32): Likewise.
6845 (__arm_vldrhq_z_u16): Likewise.
6846 (__arm_vldrwq_s32): Likewise.
6847 (__arm_vldrwq_u32): Likewise.
6848 (__arm_vldrwq_z_s32): Likewise.
6849 (__arm_vldrwq_z_u32): Likewise.
6850 (__arm_vld1q_f32): Likewise.
6851 (__arm_vld1q_f16): Likewise.
6852 (__arm_vldrwq_f32): Likewise.
6853 (__arm_vldrwq_z_f32): Likewise.
6854 (__arm_vldrhq_z_f16): Likewise.
6855 (__arm_vldrhq_f16): Likewise.
6856 (vld1q): Define polymorphic variant.
6857 (vldrhq_gather_offset): Likewise.
6858 (vldrhq_gather_offset_z): Likewise.
6859 (vldrhq_gather_shifted_offset): Likewise.
6860 (vldrhq_gather_shifted_offset_z): Likewise.
6861 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
6865 (LDRGU_Z): Likewise.
6867 (LDRGS_Z): Likewise.
6869 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
6870 (V_sz_elem1): Likewise.
6871 (VLD1Q): Define iterator.
6872 (VLDRHGOQ): Likewise.
6873 (VLDRHGSOQ): Likewise.
6876 (mve_vldrhq_fv8hf): Define RTL pattern.
6877 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
6878 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
6879 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
6880 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
6881 (mve_vldrhq_<supf><mode>): Likewise.
6882 (mve_vldrhq_z_fv8hf): Likewise.
6883 (mve_vldrhq_z_<supf><mode>): Likewise.
6884 (mve_vldrwq_fv4sf): Likewise.
6885 (mve_vldrwq_<supf>v4si): Likewise.
6886 (mve_vldrwq_z_fv4sf): Likewise.
6887 (mve_vldrwq_z_<supf>v4si): Likewise.
6888 (mve_vld1q_f<mode>): Define RTL expand pattern.
6889 (mve_vld1q_<supf><mode>): Likewise.
6891 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6892 Mihail Ionescu <mihail.ionescu@arm.com>
6893 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6895 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
6897 (LDRGBU_Z_QUALIFIERS): Likewise.
6898 (LDRGS_Z_QUALIFIERS): Likewise.
6899 (LDRGU_Z_QUALIFIERS): Likewise.
6900 (LDRS_Z_QUALIFIERS): Likewise.
6901 (LDRU_Z_QUALIFIERS): Likewise.
6902 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
6903 (vldrbq_gather_offset_z_u8): Likewise.
6904 (vldrbq_gather_offset_z_s32): Likewise.
6905 (vldrbq_gather_offset_z_u16): Likewise.
6906 (vldrbq_gather_offset_z_u32): Likewise.
6907 (vldrbq_gather_offset_z_s8): Likewise.
6908 (vldrbq_z_s16): Likewise.
6909 (vldrbq_z_u8): Likewise.
6910 (vldrbq_z_s8): Likewise.
6911 (vldrbq_z_s32): Likewise.
6912 (vldrbq_z_u16): Likewise.
6913 (vldrbq_z_u32): Likewise.
6914 (vldrwq_gather_base_z_u32): Likewise.
6915 (vldrwq_gather_base_z_s32): Likewise.
6916 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
6917 (__arm_vldrbq_gather_offset_z_s32): Likewise.
6918 (__arm_vldrbq_gather_offset_z_s16): Likewise.
6919 (__arm_vldrbq_gather_offset_z_u8): Likewise.
6920 (__arm_vldrbq_gather_offset_z_u32): Likewise.
6921 (__arm_vldrbq_gather_offset_z_u16): Likewise.
6922 (__arm_vldrbq_z_s8): Likewise.
6923 (__arm_vldrbq_z_s32): Likewise.
6924 (__arm_vldrbq_z_s16): Likewise.
6925 (__arm_vldrbq_z_u8): Likewise.
6926 (__arm_vldrbq_z_u32): Likewise.
6927 (__arm_vldrbq_z_u16): Likewise.
6928 (__arm_vldrwq_gather_base_z_s32): Likewise.
6929 (__arm_vldrwq_gather_base_z_u32): Likewise.
6930 (vldrbq_gather_offset_z): Define polymorphic variant.
6931 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
6933 (LDRGBU_Z_QUALIFIERS): Likewise.
6934 (LDRGS_Z_QUALIFIERS): Likewise.
6935 (LDRGU_Z_QUALIFIERS): Likewise.
6936 (LDRS_Z_QUALIFIERS): Likewise.
6937 (LDRU_Z_QUALIFIERS): Likewise.
6938 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
6940 (mve_vldrbq_z_<supf><mode>): Likewise.
6941 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
6943 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6944 Mihail Ionescu <mihail.ionescu@arm.com>
6945 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6947 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin
6949 (STRU_P_QUALIFIERS): Likewise.
6950 (STRSU_P_QUALIFIERS): Likewise.
6951 (STRSS_P_QUALIFIERS): Likewise.
6952 (STRSBS_P_QUALIFIERS): Likewise.
6953 (STRSBU_P_QUALIFIERS): Likewise.
6954 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro.
6955 (vstrbq_p_s32): Likewise.
6956 (vstrbq_p_s16): Likewise.
6957 (vstrbq_p_u8): Likewise.
6958 (vstrbq_p_u32): Likewise.
6959 (vstrbq_p_u16): Likewise.
6960 (vstrbq_scatter_offset_p_s8): Likewise.
6961 (vstrbq_scatter_offset_p_s32): Likewise.
6962 (vstrbq_scatter_offset_p_s16): Likewise.
6963 (vstrbq_scatter_offset_p_u8): Likewise.
6964 (vstrbq_scatter_offset_p_u32): Likewise.
6965 (vstrbq_scatter_offset_p_u16): Likewise.
6966 (vstrwq_scatter_base_p_s32): Likewise.
6967 (vstrwq_scatter_base_p_u32): Likewise.
6968 (__arm_vstrbq_p_s8): Define intrinsic.
6969 (__arm_vstrbq_p_s32): Likewise.
6970 (__arm_vstrbq_p_s16): Likewise.
6971 (__arm_vstrbq_p_u8): Likewise.
6972 (__arm_vstrbq_p_u32): Likewise.
6973 (__arm_vstrbq_p_u16): Likewise.
6974 (__arm_vstrbq_scatter_offset_p_s8): Likewise.
6975 (__arm_vstrbq_scatter_offset_p_s32): Likewise.
6976 (__arm_vstrbq_scatter_offset_p_s16): Likewise.
6977 (__arm_vstrbq_scatter_offset_p_u8): Likewise.
6978 (__arm_vstrbq_scatter_offset_p_u32): Likewise.
6979 (__arm_vstrbq_scatter_offset_p_u16): Likewise.
6980 (__arm_vstrwq_scatter_base_p_s32): Likewise.
6981 (__arm_vstrwq_scatter_base_p_u32): Likewise.
6982 (vstrbq_p): Define polymorphic variant.
6983 (vstrbq_scatter_offset_p): Likewise.
6984 (vstrwq_scatter_base_p): Likewise.
6985 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin
6987 (STRU_P_QUALIFIERS): Likewise.
6988 (STRSU_P_QUALIFIERS): Likewise.
6989 (STRSS_P_QUALIFIERS): Likewise.
6990 (STRSBS_P_QUALIFIERS): Likewise.
6991 (STRSBU_P_QUALIFIERS): Likewise.
6992 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define
6994 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
6995 (mve_vstrbq_p_<supf><mode>): Likewise.
6997 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6998 Mihail Ionescu <mihail.ionescu@arm.com>
6999 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7001 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
7003 (LDRGS_QUALIFIERS): Likewise.
7004 (LDRS_QUALIFIERS): Likewise.
7005 (LDRU_QUALIFIERS): Likewise.
7006 (LDRGBS_QUALIFIERS): Likewise.
7007 (LDRGBU_QUALIFIERS): Likewise.
7008 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
7009 (vldrbq_gather_offset_s8): Likewise.
7010 (vldrbq_s8): Likewise.
7011 (vldrbq_u8): Likewise.
7012 (vldrbq_gather_offset_u16): Likewise.
7013 (vldrbq_gather_offset_s16): Likewise.
7014 (vldrbq_s16): Likewise.
7015 (vldrbq_u16): Likewise.
7016 (vldrbq_gather_offset_u32): Likewise.
7017 (vldrbq_gather_offset_s32): Likewise.
7018 (vldrbq_s32): Likewise.
7019 (vldrbq_u32): Likewise.
7020 (vldrwq_gather_base_s32): Likewise.
7021 (vldrwq_gather_base_u32): Likewise.
7022 (__arm_vldrbq_gather_offset_u8): Define intrinsic.
7023 (__arm_vldrbq_gather_offset_s8): Likewise.
7024 (__arm_vldrbq_s8): Likewise.
7025 (__arm_vldrbq_u8): Likewise.
7026 (__arm_vldrbq_gather_offset_u16): Likewise.
7027 (__arm_vldrbq_gather_offset_s16): Likewise.
7028 (__arm_vldrbq_s16): Likewise.
7029 (__arm_vldrbq_u16): Likewise.
7030 (__arm_vldrbq_gather_offset_u32): Likewise.
7031 (__arm_vldrbq_gather_offset_s32): Likewise.
7032 (__arm_vldrbq_s32): Likewise.
7033 (__arm_vldrbq_u32): Likewise.
7034 (__arm_vldrwq_gather_base_s32): Likewise.
7035 (__arm_vldrwq_gather_base_u32): Likewise.
7036 (vldrbq_gather_offset): Define polymorphic variant.
7037 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin
7039 (LDRGS_QUALIFIERS): Likewise.
7040 (LDRS_QUALIFIERS): Likewise.
7041 (LDRU_QUALIFIERS): Likewise.
7042 (LDRGBS_QUALIFIERS): Likewise.
7043 (LDRGBU_QUALIFIERS): Likewise.
7044 * config/arm/mve.md (VLDRBGOQ): Define iterator.
7046 (VLDRWGBQ): Likewise.
7047 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
7048 (mve_vldrbq_<supf><mode>): Likewise.
7049 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
7051 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7052 Mihail Ionescu <mihail.ionescu@arm.com>
7053 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7055 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier.
7056 (STRU_QUALIFIERS): Likewise.
7057 (STRSS_QUALIFIERS): Likewise.
7058 (STRSU_QUALIFIERS): Likewise.
7059 (STRSBS_QUALIFIERS): Likewise.
7060 (STRSBU_QUALIFIERS): Likewise.
7061 * config/arm/arm_mve.h (vstrbq_s8): Define macro.
7062 (vstrbq_u8): Likewise.
7063 (vstrbq_u16): Likewise.
7064 (vstrbq_scatter_offset_s8): Likewise.
7065 (vstrbq_scatter_offset_u8): Likewise.
7066 (vstrbq_scatter_offset_u16): Likewise.
7067 (vstrbq_s16): Likewise.
7068 (vstrbq_u32): Likewise.
7069 (vstrbq_scatter_offset_s16): Likewise.
7070 (vstrbq_scatter_offset_u32): Likewise.
7071 (vstrbq_s32): Likewise.
7072 (vstrbq_scatter_offset_s32): Likewise.
7073 (vstrwq_scatter_base_s32): Likewise.
7074 (vstrwq_scatter_base_u32): Likewise.
7075 (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
7076 (__arm_vstrbq_scatter_offset_s32): Likewise.
7077 (__arm_vstrbq_scatter_offset_s16): Likewise.
7078 (__arm_vstrbq_scatter_offset_u8): Likewise.
7079 (__arm_vstrbq_scatter_offset_u32): Likewise.
7080 (__arm_vstrbq_scatter_offset_u16): Likewise.
7081 (__arm_vstrbq_s8): Likewise.
7082 (__arm_vstrbq_s32): Likewise.
7083 (__arm_vstrbq_s16): Likewise.
7084 (__arm_vstrbq_u8): Likewise.
7085 (__arm_vstrbq_u32): Likewise.
7086 (__arm_vstrbq_u16): Likewise.
7087 (__arm_vstrwq_scatter_base_s32): Likewise.
7088 (__arm_vstrwq_scatter_base_u32): Likewise.
7089 (vstrbq): Define polymorphic variant.
7090 (vstrbq_scatter_offset): Likewise.
7091 (vstrwq_scatter_base): Likewise.
7092 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
7094 (STRU_QUALIFIERS): Likewise.
7095 (STRSS_QUALIFIERS): Likewise.
7096 (STRSU_QUALIFIERS): Likewise.
7097 (STRSBS_QUALIFIERS): Likewise.
7098 (STRSBU_QUALIFIERS): Likewise.
7099 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator.
7100 (VSTRWSBQ): Define iterators.
7101 (VSTRBSOQ): Likewise.
7103 (mve_vstrbq_<supf><mode>): Define RTL pattern.
7104 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
7105 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
7107 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7108 Mihail Ionescu <mihail.ionescu@arm.com>
7109 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7111 * config/arm/arm_mve.h (vabdq_m_f32): Define macro.
7112 (vabdq_m_f16): Likewise.
7113 (vaddq_m_f32): Likewise.
7114 (vaddq_m_f16): Likewise.
7115 (vaddq_m_n_f32): Likewise.
7116 (vaddq_m_n_f16): Likewise.
7117 (vandq_m_f32): Likewise.
7118 (vandq_m_f16): Likewise.
7119 (vbicq_m_f32): Likewise.
7120 (vbicq_m_f16): Likewise.
7121 (vbrsrq_m_n_f32): Likewise.
7122 (vbrsrq_m_n_f16): Likewise.
7123 (vcaddq_rot270_m_f32): Likewise.
7124 (vcaddq_rot270_m_f16): Likewise.
7125 (vcaddq_rot90_m_f32): Likewise.
7126 (vcaddq_rot90_m_f16): Likewise.
7127 (vcmlaq_m_f32): Likewise.
7128 (vcmlaq_m_f16): Likewise.
7129 (vcmlaq_rot180_m_f32): Likewise.
7130 (vcmlaq_rot180_m_f16): Likewise.
7131 (vcmlaq_rot270_m_f32): Likewise.
7132 (vcmlaq_rot270_m_f16): Likewise.
7133 (vcmlaq_rot90_m_f32): Likewise.
7134 (vcmlaq_rot90_m_f16): Likewise.
7135 (vcmulq_m_f32): Likewise.
7136 (vcmulq_m_f16): Likewise.
7137 (vcmulq_rot180_m_f32): Likewise.
7138 (vcmulq_rot180_m_f16): Likewise.
7139 (vcmulq_rot270_m_f32): Likewise.
7140 (vcmulq_rot270_m_f16): Likewise.
7141 (vcmulq_rot90_m_f32): Likewise.
7142 (vcmulq_rot90_m_f16): Likewise.
7143 (vcvtq_m_n_s32_f32): Likewise.
7144 (vcvtq_m_n_s16_f16): Likewise.
7145 (vcvtq_m_n_u32_f32): Likewise.
7146 (vcvtq_m_n_u16_f16): Likewise.
7147 (veorq_m_f32): Likewise.
7148 (veorq_m_f16): Likewise.
7149 (vfmaq_m_f32): Likewise.
7150 (vfmaq_m_f16): Likewise.
7151 (vfmaq_m_n_f32): Likewise.
7152 (vfmaq_m_n_f16): Likewise.
7153 (vfmasq_m_n_f32): Likewise.
7154 (vfmasq_m_n_f16): Likewise.
7155 (vfmsq_m_f32): Likewise.
7156 (vfmsq_m_f16): Likewise.
7157 (vmaxnmq_m_f32): Likewise.
7158 (vmaxnmq_m_f16): Likewise.
7159 (vminnmq_m_f32): Likewise.
7160 (vminnmq_m_f16): Likewise.
7161 (vmulq_m_f32): Likewise.
7162 (vmulq_m_f16): Likewise.
7163 (vmulq_m_n_f32): Likewise.
7164 (vmulq_m_n_f16): Likewise.
7165 (vornq_m_f32): Likewise.
7166 (vornq_m_f16): Likewise.
7167 (vorrq_m_f32): Likewise.
7168 (vorrq_m_f16): Likewise.
7169 (vsubq_m_f32): Likewise.
7170 (vsubq_m_f16): Likewise.
7171 (vsubq_m_n_f32): Likewise.
7172 (vsubq_m_n_f16): Likewise.
7173 (__attribute__): Likewise.
7174 (__arm_vabdq_m_f32): Likewise.
7175 (__arm_vabdq_m_f16): Likewise.
7176 (__arm_vaddq_m_f32): Likewise.
7177 (__arm_vaddq_m_f16): Likewise.
7178 (__arm_vaddq_m_n_f32): Likewise.
7179 (__arm_vaddq_m_n_f16): Likewise.
7180 (__arm_vandq_m_f32): Likewise.
7181 (__arm_vandq_m_f16): Likewise.
7182 (__arm_vbicq_m_f32): Likewise.
7183 (__arm_vbicq_m_f16): Likewise.
7184 (__arm_vbrsrq_m_n_f32): Likewise.
7185 (__arm_vbrsrq_m_n_f16): Likewise.
7186 (__arm_vcaddq_rot270_m_f32): Likewise.
7187 (__arm_vcaddq_rot270_m_f16): Likewise.
7188 (__arm_vcaddq_rot90_m_f32): Likewise.
7189 (__arm_vcaddq_rot90_m_f16): Likewise.
7190 (__arm_vcmlaq_m_f32): Likewise.
7191 (__arm_vcmlaq_m_f16): Likewise.
7192 (__arm_vcmlaq_rot180_m_f32): Likewise.
7193 (__arm_vcmlaq_rot180_m_f16): Likewise.
7194 (__arm_vcmlaq_rot270_m_f32): Likewise.
7195 (__arm_vcmlaq_rot270_m_f16): Likewise.
7196 (__arm_vcmlaq_rot90_m_f32): Likewise.
7197 (__arm_vcmlaq_rot90_m_f16): Likewise.
7198 (__arm_vcmulq_m_f32): Likewise.
7199 (__arm_vcmulq_m_f16): Likewise.
7200 (__arm_vcmulq_rot180_m_f32): Define intrinsic.
7201 (__arm_vcmulq_rot180_m_f16): Likewise.
7202 (__arm_vcmulq_rot270_m_f32): Likewise.
7203 (__arm_vcmulq_rot270_m_f16): Likewise.
7204 (__arm_vcmulq_rot90_m_f32): Likewise.
7205 (__arm_vcmulq_rot90_m_f16): Likewise.
7206 (__arm_vcvtq_m_n_s32_f32): Likewise.
7207 (__arm_vcvtq_m_n_s16_f16): Likewise.
7208 (__arm_vcvtq_m_n_u32_f32): Likewise.
7209 (__arm_vcvtq_m_n_u16_f16): Likewise.
7210 (__arm_veorq_m_f32): Likewise.
7211 (__arm_veorq_m_f16): Likewise.
7212 (__arm_vfmaq_m_f32): Likewise.
7213 (__arm_vfmaq_m_f16): Likewise.
7214 (__arm_vfmaq_m_n_f32): Likewise.
7215 (__arm_vfmaq_m_n_f16): Likewise.
7216 (__arm_vfmasq_m_n_f32): Likewise.
7217 (__arm_vfmasq_m_n_f16): Likewise.
7218 (__arm_vfmsq_m_f32): Likewise.
7219 (__arm_vfmsq_m_f16): Likewise.
7220 (__arm_vmaxnmq_m_f32): Likewise.
7221 (__arm_vmaxnmq_m_f16): Likewise.
7222 (__arm_vminnmq_m_f32): Likewise.
7223 (__arm_vminnmq_m_f16): Likewise.
7224 (__arm_vmulq_m_f32): Likewise.
7225 (__arm_vmulq_m_f16): Likewise.
7226 (__arm_vmulq_m_n_f32): Likewise.
7227 (__arm_vmulq_m_n_f16): Likewise.
7228 (__arm_vornq_m_f32): Likewise.
7229 (__arm_vornq_m_f16): Likewise.
7230 (__arm_vorrq_m_f32): Likewise.
7231 (__arm_vorrq_m_f16): Likewise.
7232 (__arm_vsubq_m_f32): Likewise.
7233 (__arm_vsubq_m_f16): Likewise.
7234 (__arm_vsubq_m_n_f32): Likewise.
7235 (__arm_vsubq_m_n_f16): Likewise.
7236 (vabdq_m): Define polymorphic variant.
7237 (vaddq_m): Likewise.
7238 (vaddq_m_n): Likewise.
7239 (vandq_m): Likewise.
7240 (vbicq_m): Likewise.
7241 (vbrsrq_m_n): Likewise.
7242 (vcaddq_rot270_m): Likewise.
7243 (vcaddq_rot90_m): Likewise.
7244 (vcmlaq_m): Likewise.
7245 (vcmlaq_rot180_m): Likewise.
7246 (vcmlaq_rot270_m): Likewise.
7247 (vcmlaq_rot90_m): Likewise.
7248 (vcmulq_m): Likewise.
7249 (vcmulq_rot180_m): Likewise.
7250 (vcmulq_rot270_m): Likewise.
7251 (vcmulq_rot90_m): Likewise.
7252 (veorq_m): Likewise.
7253 (vfmaq_m): Likewise.
7254 (vfmaq_m_n): Likewise.
7255 (vfmasq_m_n): Likewise.
7256 (vfmsq_m): Likewise.
7257 (vmaxnmq_m): Likewise.
7258 (vminnmq_m): Likewise.
7259 (vmulq_m): Likewise.
7260 (vmulq_m_n): Likewise.
7261 (vornq_m): Likewise.
7262 (vsubq_m): Likewise.
7263 (vsubq_m_n): Likewise.
7264 (vorrq_m): Likewise.
7265 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7267 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7268 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7269 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
7270 (mve_vaddq_m_f<mode>): Likewise.
7271 (mve_vaddq_m_n_f<mode>): Likewise.
7272 (mve_vandq_m_f<mode>): Likewise.
7273 (mve_vbicq_m_f<mode>): Likewise.
7274 (mve_vbrsrq_m_n_f<mode>): Likewise.
7275 (mve_vcaddq_rot270_m_f<mode>): Likewise.
7276 (mve_vcaddq_rot90_m_f<mode>): Likewise.
7277 (mve_vcmlaq_m_f<mode>): Likewise.
7278 (mve_vcmlaq_rot180_m_f<mode>): Likewise.
7279 (mve_vcmlaq_rot270_m_f<mode>): Likewise.
7280 (mve_vcmlaq_rot90_m_f<mode>): Likewise.
7281 (mve_vcmulq_m_f<mode>): Likewise.
7282 (mve_vcmulq_rot180_m_f<mode>): Likewise.
7283 (mve_vcmulq_rot270_m_f<mode>): Likewise.
7284 (mve_vcmulq_rot90_m_f<mode>): Likewise.
7285 (mve_veorq_m_f<mode>): Likewise.
7286 (mve_vfmaq_m_f<mode>): Likewise.
7287 (mve_vfmaq_m_n_f<mode>): Likewise.
7288 (mve_vfmasq_m_n_f<mode>): Likewise.
7289 (mve_vfmsq_m_f<mode>): Likewise.
7290 (mve_vmaxnmq_m_f<mode>): Likewise.
7291 (mve_vminnmq_m_f<mode>): Likewise.
7292 (mve_vmulq_m_f<mode>): Likewise.
7293 (mve_vmulq_m_n_f<mode>): Likewise.
7294 (mve_vornq_m_f<mode>): Likewise.
7295 (mve_vorrq_m_f<mode>): Likewise.
7296 (mve_vsubq_m_f<mode>): Likewise.
7297 (mve_vsubq_m_n_f<mode>): Likewise.
7299 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7300 Mihail Ionescu <mihail.ionescu@arm.com>
7301 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7303 * config/arm/arm-protos.h (arm_mve_immediate_check):
7304 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check
7305 mode and interger value.
7306 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
7307 (vmlaldavaq_p_s16): Likewise.
7308 (vmlaldavaq_p_u32): Likewise.
7309 (vmlaldavaq_p_u16): Likewise.
7310 (vmlaldavaxq_p_s32): Likewise.
7311 (vmlaldavaxq_p_s16): Likewise.
7312 (vmlaldavaxq_p_u32): Likewise.
7313 (vmlaldavaxq_p_u16): Likewise.
7314 (vmlsldavaq_p_s32): Likewise.
7315 (vmlsldavaq_p_s16): Likewise.
7316 (vmlsldavaxq_p_s32): Likewise.
7317 (vmlsldavaxq_p_s16): Likewise.
7318 (vmullbq_poly_m_p8): Likewise.
7319 (vmullbq_poly_m_p16): Likewise.
7320 (vmulltq_poly_m_p8): Likewise.
7321 (vmulltq_poly_m_p16): Likewise.
7322 (vqdmullbq_m_n_s32): Likewise.
7323 (vqdmullbq_m_n_s16): Likewise.
7324 (vqdmullbq_m_s32): Likewise.
7325 (vqdmullbq_m_s16): Likewise.
7326 (vqdmulltq_m_n_s32): Likewise.
7327 (vqdmulltq_m_n_s16): Likewise.
7328 (vqdmulltq_m_s32): Likewise.
7329 (vqdmulltq_m_s16): Likewise.
7330 (vqrshrnbq_m_n_s32): Likewise.
7331 (vqrshrnbq_m_n_s16): Likewise.
7332 (vqrshrnbq_m_n_u32): Likewise.
7333 (vqrshrnbq_m_n_u16): Likewise.
7334 (vqrshrntq_m_n_s32): Likewise.
7335 (vqrshrntq_m_n_s16): Likewise.
7336 (vqrshrntq_m_n_u32): Likewise.
7337 (vqrshrntq_m_n_u16): Likewise.
7338 (vqrshrunbq_m_n_s32): Likewise.
7339 (vqrshrunbq_m_n_s16): Likewise.
7340 (vqrshruntq_m_n_s32): Likewise.
7341 (vqrshruntq_m_n_s16): Likewise.
7342 (vqshrnbq_m_n_s32): Likewise.
7343 (vqshrnbq_m_n_s16): Likewise.
7344 (vqshrnbq_m_n_u32): Likewise.
7345 (vqshrnbq_m_n_u16): Likewise.
7346 (vqshrntq_m_n_s32): Likewise.
7347 (vqshrntq_m_n_s16): Likewise.
7348 (vqshrntq_m_n_u32): Likewise.
7349 (vqshrntq_m_n_u16): Likewise.
7350 (vqshrunbq_m_n_s32): Likewise.
7351 (vqshrunbq_m_n_s16): Likewise.
7352 (vqshruntq_m_n_s32): Likewise.
7353 (vqshruntq_m_n_s16): Likewise.
7354 (vrmlaldavhaq_p_s32): Likewise.
7355 (vrmlaldavhaq_p_u32): Likewise.
7356 (vrmlaldavhaxq_p_s32): Likewise.
7357 (vrmlsldavhaq_p_s32): Likewise.
7358 (vrmlsldavhaxq_p_s32): Likewise.
7359 (vrshrnbq_m_n_s32): Likewise.
7360 (vrshrnbq_m_n_s16): Likewise.
7361 (vrshrnbq_m_n_u32): Likewise.
7362 (vrshrnbq_m_n_u16): Likewise.
7363 (vrshrntq_m_n_s32): Likewise.
7364 (vrshrntq_m_n_s16): Likewise.
7365 (vrshrntq_m_n_u32): Likewise.
7366 (vrshrntq_m_n_u16): Likewise.
7367 (vshllbq_m_n_s8): Likewise.
7368 (vshllbq_m_n_s16): Likewise.
7369 (vshllbq_m_n_u8): Likewise.
7370 (vshllbq_m_n_u16): Likewise.
7371 (vshlltq_m_n_s8): Likewise.
7372 (vshlltq_m_n_s16): Likewise.
7373 (vshlltq_m_n_u8): Likewise.
7374 (vshlltq_m_n_u16): Likewise.
7375 (vshrnbq_m_n_s32): Likewise.
7376 (vshrnbq_m_n_s16): Likewise.
7377 (vshrnbq_m_n_u32): Likewise.
7378 (vshrnbq_m_n_u16): Likewise.
7379 (vshrntq_m_n_s32): Likewise.
7380 (vshrntq_m_n_s16): Likewise.
7381 (vshrntq_m_n_u32): Likewise.
7382 (vshrntq_m_n_u16): Likewise.
7383 (__arm_vmlaldavaq_p_s32): Define intrinsic.
7384 (__arm_vmlaldavaq_p_s16): Likewise.
7385 (__arm_vmlaldavaq_p_u32): Likewise.
7386 (__arm_vmlaldavaq_p_u16): Likewise.
7387 (__arm_vmlaldavaxq_p_s32): Likewise.
7388 (__arm_vmlaldavaxq_p_s16): Likewise.
7389 (__arm_vmlaldavaxq_p_u32): Likewise.
7390 (__arm_vmlaldavaxq_p_u16): Likewise.
7391 (__arm_vmlsldavaq_p_s32): Likewise.
7392 (__arm_vmlsldavaq_p_s16): Likewise.
7393 (__arm_vmlsldavaxq_p_s32): Likewise.
7394 (__arm_vmlsldavaxq_p_s16): Likewise.
7395 (__arm_vmullbq_poly_m_p8): Likewise.
7396 (__arm_vmullbq_poly_m_p16): Likewise.
7397 (__arm_vmulltq_poly_m_p8): Likewise.
7398 (__arm_vmulltq_poly_m_p16): Likewise.
7399 (__arm_vqdmullbq_m_n_s32): Likewise.
7400 (__arm_vqdmullbq_m_n_s16): Likewise.
7401 (__arm_vqdmullbq_m_s32): Likewise.
7402 (__arm_vqdmullbq_m_s16): Likewise.
7403 (__arm_vqdmulltq_m_n_s32): Likewise.
7404 (__arm_vqdmulltq_m_n_s16): Likewise.
7405 (__arm_vqdmulltq_m_s32): Likewise.
7406 (__arm_vqdmulltq_m_s16): Likewise.
7407 (__arm_vqrshrnbq_m_n_s32): Likewise.
7408 (__arm_vqrshrnbq_m_n_s16): Likewise.
7409 (__arm_vqrshrnbq_m_n_u32): Likewise.
7410 (__arm_vqrshrnbq_m_n_u16): Likewise.
7411 (__arm_vqrshrntq_m_n_s32): Likewise.
7412 (__arm_vqrshrntq_m_n_s16): Likewise.
7413 (__arm_vqrshrntq_m_n_u32): Likewise.
7414 (__arm_vqrshrntq_m_n_u16): Likewise.
7415 (__arm_vqrshrunbq_m_n_s32): Likewise.
7416 (__arm_vqrshrunbq_m_n_s16): Likewise.
7417 (__arm_vqrshruntq_m_n_s32): Likewise.
7418 (__arm_vqrshruntq_m_n_s16): Likewise.
7419 (__arm_vqshrnbq_m_n_s32): Likewise.
7420 (__arm_vqshrnbq_m_n_s16): Likewise.
7421 (__arm_vqshrnbq_m_n_u32): Likewise.
7422 (__arm_vqshrnbq_m_n_u16): Likewise.
7423 (__arm_vqshrntq_m_n_s32): Likewise.
7424 (__arm_vqshrntq_m_n_s16): Likewise.
7425 (__arm_vqshrntq_m_n_u32): Likewise.
7426 (__arm_vqshrntq_m_n_u16): Likewise.
7427 (__arm_vqshrunbq_m_n_s32): Likewise.
7428 (__arm_vqshrunbq_m_n_s16): Likewise.
7429 (__arm_vqshruntq_m_n_s32): Likewise.
7430 (__arm_vqshruntq_m_n_s16): Likewise.
7431 (__arm_vrmlaldavhaq_p_s32): Likewise.
7432 (__arm_vrmlaldavhaq_p_u32): Likewise.
7433 (__arm_vrmlaldavhaxq_p_s32): Likewise.
7434 (__arm_vrmlsldavhaq_p_s32): Likewise.
7435 (__arm_vrmlsldavhaxq_p_s32): Likewise.
7436 (__arm_vrshrnbq_m_n_s32): Likewise.
7437 (__arm_vrshrnbq_m_n_s16): Likewise.
7438 (__arm_vrshrnbq_m_n_u32): Likewise.
7439 (__arm_vrshrnbq_m_n_u16): Likewise.
7440 (__arm_vrshrntq_m_n_s32): Likewise.
7441 (__arm_vrshrntq_m_n_s16): Likewise.
7442 (__arm_vrshrntq_m_n_u32): Likewise.
7443 (__arm_vrshrntq_m_n_u16): Likewise.
7444 (__arm_vshllbq_m_n_s8): Likewise.
7445 (__arm_vshllbq_m_n_s16): Likewise.
7446 (__arm_vshllbq_m_n_u8): Likewise.
7447 (__arm_vshllbq_m_n_u16): Likewise.
7448 (__arm_vshlltq_m_n_s8): Likewise.
7449 (__arm_vshlltq_m_n_s16): Likewise.
7450 (__arm_vshlltq_m_n_u8): Likewise.
7451 (__arm_vshlltq_m_n_u16): Likewise.
7452 (__arm_vshrnbq_m_n_s32): Likewise.
7453 (__arm_vshrnbq_m_n_s16): Likewise.
7454 (__arm_vshrnbq_m_n_u32): Likewise.
7455 (__arm_vshrnbq_m_n_u16): Likewise.
7456 (__arm_vshrntq_m_n_s32): Likewise.
7457 (__arm_vshrntq_m_n_s16): Likewise.
7458 (__arm_vshrntq_m_n_u32): Likewise.
7459 (__arm_vshrntq_m_n_u16): Likewise.
7460 (vmullbq_poly_m): Define polymorphic variant.
7461 (vmulltq_poly_m): Likewise.
7462 (vshllbq_m): Likewise.
7463 (vshrntq_m_n): Likewise.
7464 (vshrnbq_m_n): Likewise.
7465 (vshlltq_m_n): Likewise.
7466 (vshllbq_m_n): Likewise.
7467 (vrshrntq_m_n): Likewise.
7468 (vrshrnbq_m_n): Likewise.
7469 (vqshruntq_m_n): Likewise.
7470 (vqshrunbq_m_n): Likewise.
7471 (vqdmullbq_m_n): Likewise.
7472 (vqdmullbq_m): Likewise.
7473 (vqdmulltq_m_n): Likewise.
7474 (vqdmulltq_m): Likewise.
7475 (vqrshrnbq_m_n): Likewise.
7476 (vqrshrntq_m_n): Likewise.
7477 (vqrshrunbq_m_n): Likewise.
7478 (vqrshruntq_m_n): Likewise.
7479 (vqshrnbq_m_n): Likewise.
7480 (vqshrntq_m_n): Likewise.
7481 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7483 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7484 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7485 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
7486 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
7487 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
7488 (VMLALDAVAXQ_P): Likewise.
7489 (VQRSHRNBQ_M_N): Likewise.
7490 (VQRSHRNTQ_M_N): Likewise.
7491 (VQSHRNBQ_M_N): Likewise.
7492 (VQSHRNTQ_M_N): Likewise.
7493 (VRSHRNBQ_M_N): Likewise.
7494 (VRSHRNTQ_M_N): Likewise.
7495 (VSHLLBQ_M_N): Likewise.
7496 (VSHLLTQ_M_N): Likewise.
7497 (VSHRNBQ_M_N): Likewise.
7498 (VSHRNTQ_M_N): Likewise.
7499 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
7500 (mve_vmlaldavaxq_p_<supf><mode>): Likewise.
7501 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
7502 (mve_vqrshrntq_m_n_<supf><mode>): Likewise.
7503 (mve_vqshrnbq_m_n_<supf><mode>): Likewise.
7504 (mve_vqshrntq_m_n_<supf><mode>): Likewise.
7505 (mve_vrmlaldavhaq_p_sv4si): Likewise.
7506 (mve_vrshrnbq_m_n_<supf><mode>): Likewise.
7507 (mve_vrshrntq_m_n_<supf><mode>): Likewise.
7508 (mve_vshllbq_m_n_<supf><mode>): Likewise.
7509 (mve_vshlltq_m_n_<supf><mode>): Likewise.
7510 (mve_vshrnbq_m_n_<supf><mode>): Likewise.
7511 (mve_vshrntq_m_n_<supf><mode>): Likewise.
7512 (mve_vmlsldavaq_p_s<mode>): Likewise.
7513 (mve_vmlsldavaxq_p_s<mode>): Likewise.
7514 (mve_vmullbq_poly_m_p<mode>): Likewise.
7515 (mve_vmulltq_poly_m_p<mode>): Likewise.
7516 (mve_vqdmullbq_m_n_s<mode>): Likewise.
7517 (mve_vqdmullbq_m_s<mode>): Likewise.
7518 (mve_vqdmulltq_m_n_s<mode>): Likewise.
7519 (mve_vqdmulltq_m_s<mode>): Likewise.
7520 (mve_vqrshrunbq_m_n_s<mode>): Likewise.
7521 (mve_vqrshruntq_m_n_s<mode>): Likewise.
7522 (mve_vqshrunbq_m_n_s<mode>): Likewise.
7523 (mve_vqshruntq_m_n_s<mode>): Likewise.
7524 (mve_vrmlaldavhaq_p_uv4si): Likewise.
7525 (mve_vrmlaldavhaxq_p_sv4si): Likewise.
7526 (mve_vrmlsldavhaq_p_sv4si): Likewise.
7527 (mve_vrmlsldavhaxq_p_sv4si): Likewise.
7529 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7530 Mihail Ionescu <mihail.ionescu@arm.com>
7531 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7533 * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
7534 (vabdq_m_s32): Likewise.
7535 (vabdq_m_s16): Likewise.
7536 (vabdq_m_u8): Likewise.
7537 (vabdq_m_u32): Likewise.
7538 (vabdq_m_u16): Likewise.
7539 (vaddq_m_n_s8): Likewise.
7540 (vaddq_m_n_s32): Likewise.
7541 (vaddq_m_n_s16): Likewise.
7542 (vaddq_m_n_u8): Likewise.
7543 (vaddq_m_n_u32): Likewise.
7544 (vaddq_m_n_u16): Likewise.
7545 (vaddq_m_s8): Likewise.
7546 (vaddq_m_s32): Likewise.
7547 (vaddq_m_s16): Likewise.
7548 (vaddq_m_u8): Likewise.
7549 (vaddq_m_u32): Likewise.
7550 (vaddq_m_u16): Likewise.
7551 (vandq_m_s8): Likewise.
7552 (vandq_m_s32): Likewise.
7553 (vandq_m_s16): Likewise.
7554 (vandq_m_u8): Likewise.
7555 (vandq_m_u32): Likewise.
7556 (vandq_m_u16): Likewise.
7557 (vbicq_m_s8): Likewise.
7558 (vbicq_m_s32): Likewise.
7559 (vbicq_m_s16): Likewise.
7560 (vbicq_m_u8): Likewise.
7561 (vbicq_m_u32): Likewise.
7562 (vbicq_m_u16): Likewise.
7563 (vbrsrq_m_n_s8): Likewise.
7564 (vbrsrq_m_n_s32): Likewise.
7565 (vbrsrq_m_n_s16): Likewise.
7566 (vbrsrq_m_n_u8): Likewise.
7567 (vbrsrq_m_n_u32): Likewise.
7568 (vbrsrq_m_n_u16): Likewise.
7569 (vcaddq_rot270_m_s8): Likewise.
7570 (vcaddq_rot270_m_s32): Likewise.
7571 (vcaddq_rot270_m_s16): Likewise.
7572 (vcaddq_rot270_m_u8): Likewise.
7573 (vcaddq_rot270_m_u32): Likewise.
7574 (vcaddq_rot270_m_u16): Likewise.
7575 (vcaddq_rot90_m_s8): Likewise.
7576 (vcaddq_rot90_m_s32): Likewise.
7577 (vcaddq_rot90_m_s16): Likewise.
7578 (vcaddq_rot90_m_u8): Likewise.
7579 (vcaddq_rot90_m_u32): Likewise.
7580 (vcaddq_rot90_m_u16): Likewise.
7581 (veorq_m_s8): Likewise.
7582 (veorq_m_s32): Likewise.
7583 (veorq_m_s16): Likewise.
7584 (veorq_m_u8): Likewise.
7585 (veorq_m_u32): Likewise.
7586 (veorq_m_u16): Likewise.
7587 (vhaddq_m_n_s8): Likewise.
7588 (vhaddq_m_n_s32): Likewise.
7589 (vhaddq_m_n_s16): Likewise.
7590 (vhaddq_m_n_u8): Likewise.
7591 (vhaddq_m_n_u32): Likewise.
7592 (vhaddq_m_n_u16): Likewise.
7593 (vhaddq_m_s8): Likewise.
7594 (vhaddq_m_s32): Likewise.
7595 (vhaddq_m_s16): Likewise.
7596 (vhaddq_m_u8): Likewise.
7597 (vhaddq_m_u32): Likewise.
7598 (vhaddq_m_u16): Likewise.
7599 (vhcaddq_rot270_m_s8): Likewise.
7600 (vhcaddq_rot270_m_s32): Likewise.
7601 (vhcaddq_rot270_m_s16): Likewise.
7602 (vhcaddq_rot90_m_s8): Likewise.
7603 (vhcaddq_rot90_m_s32): Likewise.
7604 (vhcaddq_rot90_m_s16): Likewise.
7605 (vhsubq_m_n_s8): Likewise.
7606 (vhsubq_m_n_s32): Likewise.
7607 (vhsubq_m_n_s16): Likewise.
7608 (vhsubq_m_n_u8): Likewise.
7609 (vhsubq_m_n_u32): Likewise.
7610 (vhsubq_m_n_u16): Likewise.
7611 (vhsubq_m_s8): Likewise.
7612 (vhsubq_m_s32): Likewise.
7613 (vhsubq_m_s16): Likewise.
7614 (vhsubq_m_u8): Likewise.
7615 (vhsubq_m_u32): Likewise.
7616 (vhsubq_m_u16): Likewise.
7617 (vmaxq_m_s8): Likewise.
7618 (vmaxq_m_s32): Likewise.
7619 (vmaxq_m_s16): Likewise.
7620 (vmaxq_m_u8): Likewise.
7621 (vmaxq_m_u32): Likewise.
7622 (vmaxq_m_u16): Likewise.
7623 (vminq_m_s8): Likewise.
7624 (vminq_m_s32): Likewise.
7625 (vminq_m_s16): Likewise.
7626 (vminq_m_u8): Likewise.
7627 (vminq_m_u32): Likewise.
7628 (vminq_m_u16): Likewise.
7629 (vmladavaq_p_s8): Likewise.
7630 (vmladavaq_p_s32): Likewise.
7631 (vmladavaq_p_s16): Likewise.
7632 (vmladavaq_p_u8): Likewise.
7633 (vmladavaq_p_u32): Likewise.
7634 (vmladavaq_p_u16): Likewise.
7635 (vmladavaxq_p_s8): Likewise.
7636 (vmladavaxq_p_s32): Likewise.
7637 (vmladavaxq_p_s16): Likewise.
7638 (vmlaq_m_n_s8): Likewise.
7639 (vmlaq_m_n_s32): Likewise.
7640 (vmlaq_m_n_s16): Likewise.
7641 (vmlaq_m_n_u8): Likewise.
7642 (vmlaq_m_n_u32): Likewise.
7643 (vmlaq_m_n_u16): Likewise.
7644 (vmlasq_m_n_s8): Likewise.
7645 (vmlasq_m_n_s32): Likewise.
7646 (vmlasq_m_n_s16): Likewise.
7647 (vmlasq_m_n_u8): Likewise.
7648 (vmlasq_m_n_u32): Likewise.
7649 (vmlasq_m_n_u16): Likewise.
7650 (vmlsdavaq_p_s8): Likewise.
7651 (vmlsdavaq_p_s32): Likewise.
7652 (vmlsdavaq_p_s16): Likewise.
7653 (vmlsdavaxq_p_s8): Likewise.
7654 (vmlsdavaxq_p_s32): Likewise.
7655 (vmlsdavaxq_p_s16): Likewise.
7656 (vmulhq_m_s8): Likewise.
7657 (vmulhq_m_s32): Likewise.
7658 (vmulhq_m_s16): Likewise.
7659 (vmulhq_m_u8): Likewise.
7660 (vmulhq_m_u32): Likewise.
7661 (vmulhq_m_u16): Likewise.
7662 (vmullbq_int_m_s8): Likewise.
7663 (vmullbq_int_m_s32): Likewise.
7664 (vmullbq_int_m_s16): Likewise.
7665 (vmullbq_int_m_u8): Likewise.
7666 (vmullbq_int_m_u32): Likewise.
7667 (vmullbq_int_m_u16): Likewise.
7668 (vmulltq_int_m_s8): Likewise.
7669 (vmulltq_int_m_s32): Likewise.
7670 (vmulltq_int_m_s16): Likewise.
7671 (vmulltq_int_m_u8): Likewise.
7672 (vmulltq_int_m_u32): Likewise.
7673 (vmulltq_int_m_u16): Likewise.
7674 (vmulq_m_n_s8): Likewise.
7675 (vmulq_m_n_s32): Likewise.
7676 (vmulq_m_n_s16): Likewise.
7677 (vmulq_m_n_u8): Likewise.
7678 (vmulq_m_n_u32): Likewise.
7679 (vmulq_m_n_u16): Likewise.
7680 (vmulq_m_s8): Likewise.
7681 (vmulq_m_s32): Likewise.
7682 (vmulq_m_s16): Likewise.
7683 (vmulq_m_u8): Likewise.
7684 (vmulq_m_u32): Likewise.
7685 (vmulq_m_u16): Likewise.
7686 (vornq_m_s8): Likewise.
7687 (vornq_m_s32): Likewise.
7688 (vornq_m_s16): Likewise.
7689 (vornq_m_u8): Likewise.
7690 (vornq_m_u32): Likewise.
7691 (vornq_m_u16): Likewise.
7692 (vorrq_m_s8): Likewise.
7693 (vorrq_m_s32): Likewise.
7694 (vorrq_m_s16): Likewise.
7695 (vorrq_m_u8): Likewise.
7696 (vorrq_m_u32): Likewise.
7697 (vorrq_m_u16): Likewise.
7698 (vqaddq_m_n_s8): Likewise.
7699 (vqaddq_m_n_s32): Likewise.
7700 (vqaddq_m_n_s16): Likewise.
7701 (vqaddq_m_n_u8): Likewise.
7702 (vqaddq_m_n_u32): Likewise.
7703 (vqaddq_m_n_u16): Likewise.
7704 (vqaddq_m_s8): Likewise.
7705 (vqaddq_m_s32): Likewise.
7706 (vqaddq_m_s16): Likewise.
7707 (vqaddq_m_u8): Likewise.
7708 (vqaddq_m_u32): Likewise.
7709 (vqaddq_m_u16): Likewise.
7710 (vqdmladhq_m_s8): Likewise.
7711 (vqdmladhq_m_s32): Likewise.
7712 (vqdmladhq_m_s16): Likewise.
7713 (vqdmladhxq_m_s8): Likewise.
7714 (vqdmladhxq_m_s32): Likewise.
7715 (vqdmladhxq_m_s16): Likewise.
7716 (vqdmlahq_m_n_s8): Likewise.
7717 (vqdmlahq_m_n_s32): Likewise.
7718 (vqdmlahq_m_n_s16): Likewise.
7719 (vqdmlahq_m_n_u8): Likewise.
7720 (vqdmlahq_m_n_u32): Likewise.
7721 (vqdmlahq_m_n_u16): Likewise.
7722 (vqdmlsdhq_m_s8): Likewise.
7723 (vqdmlsdhq_m_s32): Likewise.
7724 (vqdmlsdhq_m_s16): Likewise.
7725 (vqdmlsdhxq_m_s8): Likewise.
7726 (vqdmlsdhxq_m_s32): Likewise.
7727 (vqdmlsdhxq_m_s16): Likewise.
7728 (vqdmulhq_m_n_s8): Likewise.
7729 (vqdmulhq_m_n_s32): Likewise.
7730 (vqdmulhq_m_n_s16): Likewise.
7731 (vqdmulhq_m_s8): Likewise.
7732 (vqdmulhq_m_s32): Likewise.
7733 (vqdmulhq_m_s16): Likewise.
7734 (vqrdmladhq_m_s8): Likewise.
7735 (vqrdmladhq_m_s32): Likewise.
7736 (vqrdmladhq_m_s16): Likewise.
7737 (vqrdmladhxq_m_s8): Likewise.
7738 (vqrdmladhxq_m_s32): Likewise.
7739 (vqrdmladhxq_m_s16): Likewise.
7740 (vqrdmlahq_m_n_s8): Likewise.
7741 (vqrdmlahq_m_n_s32): Likewise.
7742 (vqrdmlahq_m_n_s16): Likewise.
7743 (vqrdmlahq_m_n_u8): Likewise.
7744 (vqrdmlahq_m_n_u32): Likewise.
7745 (vqrdmlahq_m_n_u16): Likewise.
7746 (vqrdmlashq_m_n_s8): Likewise.
7747 (vqrdmlashq_m_n_s32): Likewise.
7748 (vqrdmlashq_m_n_s16): Likewise.
7749 (vqrdmlashq_m_n_u8): Likewise.
7750 (vqrdmlashq_m_n_u32): Likewise.
7751 (vqrdmlashq_m_n_u16): Likewise.
7752 (vqrdmlsdhq_m_s8): Likewise.
7753 (vqrdmlsdhq_m_s32): Likewise.
7754 (vqrdmlsdhq_m_s16): Likewise.
7755 (vqrdmlsdhxq_m_s8): Likewise.
7756 (vqrdmlsdhxq_m_s32): Likewise.
7757 (vqrdmlsdhxq_m_s16): Likewise.
7758 (vqrdmulhq_m_n_s8): Likewise.
7759 (vqrdmulhq_m_n_s32): Likewise.
7760 (vqrdmulhq_m_n_s16): Likewise.
7761 (vqrdmulhq_m_s8): Likewise.
7762 (vqrdmulhq_m_s32): Likewise.
7763 (vqrdmulhq_m_s16): Likewise.
7764 (vqrshlq_m_s8): Likewise.
7765 (vqrshlq_m_s32): Likewise.
7766 (vqrshlq_m_s16): Likewise.
7767 (vqrshlq_m_u8): Likewise.
7768 (vqrshlq_m_u32): Likewise.
7769 (vqrshlq_m_u16): Likewise.
7770 (vqshlq_m_n_s8): Likewise.
7771 (vqshlq_m_n_s32): Likewise.
7772 (vqshlq_m_n_s16): Likewise.
7773 (vqshlq_m_n_u8): Likewise.
7774 (vqshlq_m_n_u32): Likewise.
7775 (vqshlq_m_n_u16): Likewise.
7776 (vqshlq_m_s8): Likewise.
7777 (vqshlq_m_s32): Likewise.
7778 (vqshlq_m_s16): Likewise.
7779 (vqshlq_m_u8): Likewise.
7780 (vqshlq_m_u32): Likewise.
7781 (vqshlq_m_u16): Likewise.
7782 (vqsubq_m_n_s8): Likewise.
7783 (vqsubq_m_n_s32): Likewise.
7784 (vqsubq_m_n_s16): Likewise.
7785 (vqsubq_m_n_u8): Likewise.
7786 (vqsubq_m_n_u32): Likewise.
7787 (vqsubq_m_n_u16): Likewise.
7788 (vqsubq_m_s8): Likewise.
7789 (vqsubq_m_s32): Likewise.
7790 (vqsubq_m_s16): Likewise.
7791 (vqsubq_m_u8): Likewise.
7792 (vqsubq_m_u32): Likewise.
7793 (vqsubq_m_u16): Likewise.
7794 (vrhaddq_m_s8): Likewise.
7795 (vrhaddq_m_s32): Likewise.
7796 (vrhaddq_m_s16): Likewise.
7797 (vrhaddq_m_u8): Likewise.
7798 (vrhaddq_m_u32): Likewise.
7799 (vrhaddq_m_u16): Likewise.
7800 (vrmulhq_m_s8): Likewise.
7801 (vrmulhq_m_s32): Likewise.
7802 (vrmulhq_m_s16): Likewise.
7803 (vrmulhq_m_u8): Likewise.
7804 (vrmulhq_m_u32): Likewise.
7805 (vrmulhq_m_u16): Likewise.
7806 (vrshlq_m_s8): Likewise.
7807 (vrshlq_m_s32): Likewise.
7808 (vrshlq_m_s16): Likewise.
7809 (vrshlq_m_u8): Likewise.
7810 (vrshlq_m_u32): Likewise.
7811 (vrshlq_m_u16): Likewise.
7812 (vrshrq_m_n_s8): Likewise.
7813 (vrshrq_m_n_s32): Likewise.
7814 (vrshrq_m_n_s16): Likewise.
7815 (vrshrq_m_n_u8): Likewise.
7816 (vrshrq_m_n_u32): Likewise.
7817 (vrshrq_m_n_u16): Likewise.
7818 (vshlq_m_n_s8): Likewise.
7819 (vshlq_m_n_s32): Likewise.
7820 (vshlq_m_n_s16): Likewise.
7821 (vshlq_m_n_u8): Likewise.
7822 (vshlq_m_n_u32): Likewise.
7823 (vshlq_m_n_u16): Likewise.
7824 (vshrq_m_n_s8): Likewise.
7825 (vshrq_m_n_s32): Likewise.
7826 (vshrq_m_n_s16): Likewise.
7827 (vshrq_m_n_u8): Likewise.
7828 (vshrq_m_n_u32): Likewise.
7829 (vshrq_m_n_u16): Likewise.
7830 (vsliq_m_n_s8): Likewise.
7831 (vsliq_m_n_s32): Likewise.
7832 (vsliq_m_n_s16): Likewise.
7833 (vsliq_m_n_u8): Likewise.
7834 (vsliq_m_n_u32): Likewise.
7835 (vsliq_m_n_u16): Likewise.
7836 (vsubq_m_n_s8): Likewise.
7837 (vsubq_m_n_s32): Likewise.
7838 (vsubq_m_n_s16): Likewise.
7839 (vsubq_m_n_u8): Likewise.
7840 (vsubq_m_n_u32): Likewise.
7841 (vsubq_m_n_u16): Likewise.
7842 (__arm_vabdq_m_s8): Define intrinsic.
7843 (__arm_vabdq_m_s32): Likewise.
7844 (__arm_vabdq_m_s16): Likewise.
7845 (__arm_vabdq_m_u8): Likewise.
7846 (__arm_vabdq_m_u32): Likewise.
7847 (__arm_vabdq_m_u16): Likewise.
7848 (__arm_vaddq_m_n_s8): Likewise.
7849 (__arm_vaddq_m_n_s32): Likewise.
7850 (__arm_vaddq_m_n_s16): Likewise.
7851 (__arm_vaddq_m_n_u8): Likewise.
7852 (__arm_vaddq_m_n_u32): Likewise.
7853 (__arm_vaddq_m_n_u16): Likewise.
7854 (__arm_vaddq_m_s8): Likewise.
7855 (__arm_vaddq_m_s32): Likewise.
7856 (__arm_vaddq_m_s16): Likewise.
7857 (__arm_vaddq_m_u8): Likewise.
7858 (__arm_vaddq_m_u32): Likewise.
7859 (__arm_vaddq_m_u16): Likewise.
7860 (__arm_vandq_m_s8): Likewise.
7861 (__arm_vandq_m_s32): Likewise.
7862 (__arm_vandq_m_s16): Likewise.
7863 (__arm_vandq_m_u8): Likewise.
7864 (__arm_vandq_m_u32): Likewise.
7865 (__arm_vandq_m_u16): Likewise.
7866 (__arm_vbicq_m_s8): Likewise.
7867 (__arm_vbicq_m_s32): Likewise.
7868 (__arm_vbicq_m_s16): Likewise.
7869 (__arm_vbicq_m_u8): Likewise.
7870 (__arm_vbicq_m_u32): Likewise.
7871 (__arm_vbicq_m_u16): Likewise.
7872 (__arm_vbrsrq_m_n_s8): Likewise.
7873 (__arm_vbrsrq_m_n_s32): Likewise.
7874 (__arm_vbrsrq_m_n_s16): Likewise.
7875 (__arm_vbrsrq_m_n_u8): Likewise.
7876 (__arm_vbrsrq_m_n_u32): Likewise.
7877 (__arm_vbrsrq_m_n_u16): Likewise.
7878 (__arm_vcaddq_rot270_m_s8): Likewise.
7879 (__arm_vcaddq_rot270_m_s32): Likewise.
7880 (__arm_vcaddq_rot270_m_s16): Likewise.
7881 (__arm_vcaddq_rot270_m_u8): Likewise.
7882 (__arm_vcaddq_rot270_m_u32): Likewise.
7883 (__arm_vcaddq_rot270_m_u16): Likewise.
7884 (__arm_vcaddq_rot90_m_s8): Likewise.
7885 (__arm_vcaddq_rot90_m_s32): Likewise.
7886 (__arm_vcaddq_rot90_m_s16): Likewise.
7887 (__arm_vcaddq_rot90_m_u8): Likewise.
7888 (__arm_vcaddq_rot90_m_u32): Likewise.
7889 (__arm_vcaddq_rot90_m_u16): Likewise.
7890 (__arm_veorq_m_s8): Likewise.
7891 (__arm_veorq_m_s32): Likewise.
7892 (__arm_veorq_m_s16): Likewise.
7893 (__arm_veorq_m_u8): Likewise.
7894 (__arm_veorq_m_u32): Likewise.
7895 (__arm_veorq_m_u16): Likewise.
7896 (__arm_vhaddq_m_n_s8): Likewise.
7897 (__arm_vhaddq_m_n_s32): Likewise.
7898 (__arm_vhaddq_m_n_s16): Likewise.
7899 (__arm_vhaddq_m_n_u8): Likewise.
7900 (__arm_vhaddq_m_n_u32): Likewise.
7901 (__arm_vhaddq_m_n_u16): Likewise.
7902 (__arm_vhaddq_m_s8): Likewise.
7903 (__arm_vhaddq_m_s32): Likewise.
7904 (__arm_vhaddq_m_s16): Likewise.
7905 (__arm_vhaddq_m_u8): Likewise.
7906 (__arm_vhaddq_m_u32): Likewise.
7907 (__arm_vhaddq_m_u16): Likewise.
7908 (__arm_vhcaddq_rot270_m_s8): Likewise.
7909 (__arm_vhcaddq_rot270_m_s32): Likewise.
7910 (__arm_vhcaddq_rot270_m_s16): Likewise.
7911 (__arm_vhcaddq_rot90_m_s8): Likewise.
7912 (__arm_vhcaddq_rot90_m_s32): Likewise.
7913 (__arm_vhcaddq_rot90_m_s16): Likewise.
7914 (__arm_vhsubq_m_n_s8): Likewise.
7915 (__arm_vhsubq_m_n_s32): Likewise.
7916 (__arm_vhsubq_m_n_s16): Likewise.
7917 (__arm_vhsubq_m_n_u8): Likewise.
7918 (__arm_vhsubq_m_n_u32): Likewise.
7919 (__arm_vhsubq_m_n_u16): Likewise.
7920 (__arm_vhsubq_m_s8): Likewise.
7921 (__arm_vhsubq_m_s32): Likewise.
7922 (__arm_vhsubq_m_s16): Likewise.
7923 (__arm_vhsubq_m_u8): Likewise.
7924 (__arm_vhsubq_m_u32): Likewise.
7925 (__arm_vhsubq_m_u16): Likewise.
7926 (__arm_vmaxq_m_s8): Likewise.
7927 (__arm_vmaxq_m_s32): Likewise.
7928 (__arm_vmaxq_m_s16): Likewise.
7929 (__arm_vmaxq_m_u8): Likewise.
7930 (__arm_vmaxq_m_u32): Likewise.
7931 (__arm_vmaxq_m_u16): Likewise.
7932 (__arm_vminq_m_s8): Likewise.
7933 (__arm_vminq_m_s32): Likewise.
7934 (__arm_vminq_m_s16): Likewise.
7935 (__arm_vminq_m_u8): Likewise.
7936 (__arm_vminq_m_u32): Likewise.
7937 (__arm_vminq_m_u16): Likewise.
7938 (__arm_vmladavaq_p_s8): Likewise.
7939 (__arm_vmladavaq_p_s32): Likewise.
7940 (__arm_vmladavaq_p_s16): Likewise.
7941 (__arm_vmladavaq_p_u8): Likewise.
7942 (__arm_vmladavaq_p_u32): Likewise.
7943 (__arm_vmladavaq_p_u16): Likewise.
7944 (__arm_vmladavaxq_p_s8): Likewise.
7945 (__arm_vmladavaxq_p_s32): Likewise.
7946 (__arm_vmladavaxq_p_s16): Likewise.
7947 (__arm_vmlaq_m_n_s8): Likewise.
7948 (__arm_vmlaq_m_n_s32): Likewise.
7949 (__arm_vmlaq_m_n_s16): Likewise.
7950 (__arm_vmlaq_m_n_u8): Likewise.
7951 (__arm_vmlaq_m_n_u32): Likewise.
7952 (__arm_vmlaq_m_n_u16): Likewise.
7953 (__arm_vmlasq_m_n_s8): Likewise.
7954 (__arm_vmlasq_m_n_s32): Likewise.
7955 (__arm_vmlasq_m_n_s16): Likewise.
7956 (__arm_vmlasq_m_n_u8): Likewise.
7957 (__arm_vmlasq_m_n_u32): Likewise.
7958 (__arm_vmlasq_m_n_u16): Likewise.
7959 (__arm_vmlsdavaq_p_s8): Likewise.
7960 (__arm_vmlsdavaq_p_s32): Likewise.
7961 (__arm_vmlsdavaq_p_s16): Likewise.
7962 (__arm_vmlsdavaxq_p_s8): Likewise.
7963 (__arm_vmlsdavaxq_p_s32): Likewise.
7964 (__arm_vmlsdavaxq_p_s16): Likewise.
7965 (__arm_vmulhq_m_s8): Likewise.
7966 (__arm_vmulhq_m_s32): Likewise.
7967 (__arm_vmulhq_m_s16): Likewise.
7968 (__arm_vmulhq_m_u8): Likewise.
7969 (__arm_vmulhq_m_u32): Likewise.
7970 (__arm_vmulhq_m_u16): Likewise.
7971 (__arm_vmullbq_int_m_s8): Likewise.
7972 (__arm_vmullbq_int_m_s32): Likewise.
7973 (__arm_vmullbq_int_m_s16): Likewise.
7974 (__arm_vmullbq_int_m_u8): Likewise.
7975 (__arm_vmullbq_int_m_u32): Likewise.
7976 (__arm_vmullbq_int_m_u16): Likewise.
7977 (__arm_vmulltq_int_m_s8): Likewise.
7978 (__arm_vmulltq_int_m_s32): Likewise.
7979 (__arm_vmulltq_int_m_s16): Likewise.
7980 (__arm_vmulltq_int_m_u8): Likewise.
7981 (__arm_vmulltq_int_m_u32): Likewise.
7982 (__arm_vmulltq_int_m_u16): Likewise.
7983 (__arm_vmulq_m_n_s8): Likewise.
7984 (__arm_vmulq_m_n_s32): Likewise.
7985 (__arm_vmulq_m_n_s16): Likewise.
7986 (__arm_vmulq_m_n_u8): Likewise.
7987 (__arm_vmulq_m_n_u32): Likewise.
7988 (__arm_vmulq_m_n_u16): Likewise.
7989 (__arm_vmulq_m_s8): Likewise.
7990 (__arm_vmulq_m_s32): Likewise.
7991 (__arm_vmulq_m_s16): Likewise.
7992 (__arm_vmulq_m_u8): Likewise.
7993 (__arm_vmulq_m_u32): Likewise.
7994 (__arm_vmulq_m_u16): Likewise.
7995 (__arm_vornq_m_s8): Likewise.
7996 (__arm_vornq_m_s32): Likewise.
7997 (__arm_vornq_m_s16): Likewise.
7998 (__arm_vornq_m_u8): Likewise.
7999 (__arm_vornq_m_u32): Likewise.
8000 (__arm_vornq_m_u16): Likewise.
8001 (__arm_vorrq_m_s8): Likewise.
8002 (__arm_vorrq_m_s32): Likewise.
8003 (__arm_vorrq_m_s16): Likewise.
8004 (__arm_vorrq_m_u8): Likewise.
8005 (__arm_vorrq_m_u32): Likewise.
8006 (__arm_vorrq_m_u16): Likewise.
8007 (__arm_vqaddq_m_n_s8): Likewise.
8008 (__arm_vqaddq_m_n_s32): Likewise.
8009 (__arm_vqaddq_m_n_s16): Likewise.
8010 (__arm_vqaddq_m_n_u8): Likewise.
8011 (__arm_vqaddq_m_n_u32): Likewise.
8012 (__arm_vqaddq_m_n_u16): Likewise.
8013 (__arm_vqaddq_m_s8): Likewise.
8014 (__arm_vqaddq_m_s32): Likewise.
8015 (__arm_vqaddq_m_s16): Likewise.
8016 (__arm_vqaddq_m_u8): Likewise.
8017 (__arm_vqaddq_m_u32): Likewise.
8018 (__arm_vqaddq_m_u16): Likewise.
8019 (__arm_vqdmladhq_m_s8): Likewise.
8020 (__arm_vqdmladhq_m_s32): Likewise.
8021 (__arm_vqdmladhq_m_s16): Likewise.
8022 (__arm_vqdmladhxq_m_s8): Likewise.
8023 (__arm_vqdmladhxq_m_s32): Likewise.
8024 (__arm_vqdmladhxq_m_s16): Likewise.
8025 (__arm_vqdmlahq_m_n_s8): Likewise.
8026 (__arm_vqdmlahq_m_n_s32): Likewise.
8027 (__arm_vqdmlahq_m_n_s16): Likewise.
8028 (__arm_vqdmlahq_m_n_u8): Likewise.
8029 (__arm_vqdmlahq_m_n_u32): Likewise.
8030 (__arm_vqdmlahq_m_n_u16): Likewise.
8031 (__arm_vqdmlsdhq_m_s8): Likewise.
8032 (__arm_vqdmlsdhq_m_s32): Likewise.
8033 (__arm_vqdmlsdhq_m_s16): Likewise.
8034 (__arm_vqdmlsdhxq_m_s8): Likewise.
8035 (__arm_vqdmlsdhxq_m_s32): Likewise.
8036 (__arm_vqdmlsdhxq_m_s16): Likewise.
8037 (__arm_vqdmulhq_m_n_s8): Likewise.
8038 (__arm_vqdmulhq_m_n_s32): Likewise.
8039 (__arm_vqdmulhq_m_n_s16): Likewise.
8040 (__arm_vqdmulhq_m_s8): Likewise.
8041 (__arm_vqdmulhq_m_s32): Likewise.
8042 (__arm_vqdmulhq_m_s16): Likewise.
8043 (__arm_vqrdmladhq_m_s8): Likewise.
8044 (__arm_vqrdmladhq_m_s32): Likewise.
8045 (__arm_vqrdmladhq_m_s16): Likewise.
8046 (__arm_vqrdmladhxq_m_s8): Likewise.
8047 (__arm_vqrdmladhxq_m_s32): Likewise.
8048 (__arm_vqrdmladhxq_m_s16): Likewise.
8049 (__arm_vqrdmlahq_m_n_s8): Likewise.
8050 (__arm_vqrdmlahq_m_n_s32): Likewise.
8051 (__arm_vqrdmlahq_m_n_s16): Likewise.
8052 (__arm_vqrdmlahq_m_n_u8): Likewise.
8053 (__arm_vqrdmlahq_m_n_u32): Likewise.
8054 (__arm_vqrdmlahq_m_n_u16): Likewise.
8055 (__arm_vqrdmlashq_m_n_s8): Likewise.
8056 (__arm_vqrdmlashq_m_n_s32): Likewise.
8057 (__arm_vqrdmlashq_m_n_s16): Likewise.
8058 (__arm_vqrdmlashq_m_n_u8): Likewise.
8059 (__arm_vqrdmlashq_m_n_u32): Likewise.
8060 (__arm_vqrdmlashq_m_n_u16): Likewise.
8061 (__arm_vqrdmlsdhq_m_s8): Likewise.
8062 (__arm_vqrdmlsdhq_m_s32): Likewise.
8063 (__arm_vqrdmlsdhq_m_s16): Likewise.
8064 (__arm_vqrdmlsdhxq_m_s8): Likewise.
8065 (__arm_vqrdmlsdhxq_m_s32): Likewise.
8066 (__arm_vqrdmlsdhxq_m_s16): Likewise.
8067 (__arm_vqrdmulhq_m_n_s8): Likewise.
8068 (__arm_vqrdmulhq_m_n_s32): Likewise.
8069 (__arm_vqrdmulhq_m_n_s16): Likewise.
8070 (__arm_vqrdmulhq_m_s8): Likewise.
8071 (__arm_vqrdmulhq_m_s32): Likewise.
8072 (__arm_vqrdmulhq_m_s16): Likewise.
8073 (__arm_vqrshlq_m_s8): Likewise.
8074 (__arm_vqrshlq_m_s32): Likewise.
8075 (__arm_vqrshlq_m_s16): Likewise.
8076 (__arm_vqrshlq_m_u8): Likewise.
8077 (__arm_vqrshlq_m_u32): Likewise.
8078 (__arm_vqrshlq_m_u16): Likewise.
8079 (__arm_vqshlq_m_n_s8): Likewise.
8080 (__arm_vqshlq_m_n_s32): Likewise.
8081 (__arm_vqshlq_m_n_s16): Likewise.
8082 (__arm_vqshlq_m_n_u8): Likewise.
8083 (__arm_vqshlq_m_n_u32): Likewise.
8084 (__arm_vqshlq_m_n_u16): Likewise.
8085 (__arm_vqshlq_m_s8): Likewise.
8086 (__arm_vqshlq_m_s32): Likewise.
8087 (__arm_vqshlq_m_s16): Likewise.
8088 (__arm_vqshlq_m_u8): Likewise.
8089 (__arm_vqshlq_m_u32): Likewise.
8090 (__arm_vqshlq_m_u16): Likewise.
8091 (__arm_vqsubq_m_n_s8): Likewise.
8092 (__arm_vqsubq_m_n_s32): Likewise.
8093 (__arm_vqsubq_m_n_s16): Likewise.
8094 (__arm_vqsubq_m_n_u8): Likewise.
8095 (__arm_vqsubq_m_n_u32): Likewise.
8096 (__arm_vqsubq_m_n_u16): Likewise.
8097 (__arm_vqsubq_m_s8): Likewise.
8098 (__arm_vqsubq_m_s32): Likewise.
8099 (__arm_vqsubq_m_s16): Likewise.
8100 (__arm_vqsubq_m_u8): Likewise.
8101 (__arm_vqsubq_m_u32): Likewise.
8102 (__arm_vqsubq_m_u16): Likewise.
8103 (__arm_vrhaddq_m_s8): Likewise.
8104 (__arm_vrhaddq_m_s32): Likewise.
8105 (__arm_vrhaddq_m_s16): Likewise.
8106 (__arm_vrhaddq_m_u8): Likewise.
8107 (__arm_vrhaddq_m_u32): Likewise.
8108 (__arm_vrhaddq_m_u16): Likewise.
8109 (__arm_vrmulhq_m_s8): Likewise.
8110 (__arm_vrmulhq_m_s32): Likewise.
8111 (__arm_vrmulhq_m_s16): Likewise.
8112 (__arm_vrmulhq_m_u8): Likewise.
8113 (__arm_vrmulhq_m_u32): Likewise.
8114 (__arm_vrmulhq_m_u16): Likewise.
8115 (__arm_vrshlq_m_s8): Likewise.
8116 (__arm_vrshlq_m_s32): Likewise.
8117 (__arm_vrshlq_m_s16): Likewise.
8118 (__arm_vrshlq_m_u8): Likewise.
8119 (__arm_vrshlq_m_u32): Likewise.
8120 (__arm_vrshlq_m_u16): Likewise.
8121 (__arm_vrshrq_m_n_s8): Likewise.
8122 (__arm_vrshrq_m_n_s32): Likewise.
8123 (__arm_vrshrq_m_n_s16): Likewise.
8124 (__arm_vrshrq_m_n_u8): Likewise.
8125 (__arm_vrshrq_m_n_u32): Likewise.
8126 (__arm_vrshrq_m_n_u16): Likewise.
8127 (__arm_vshlq_m_n_s8): Likewise.
8128 (__arm_vshlq_m_n_s32): Likewise.
8129 (__arm_vshlq_m_n_s16): Likewise.
8130 (__arm_vshlq_m_n_u8): Likewise.
8131 (__arm_vshlq_m_n_u32): Likewise.
8132 (__arm_vshlq_m_n_u16): Likewise.
8133 (__arm_vshrq_m_n_s8): Likewise.
8134 (__arm_vshrq_m_n_s32): Likewise.
8135 (__arm_vshrq_m_n_s16): Likewise.
8136 (__arm_vshrq_m_n_u8): Likewise.
8137 (__arm_vshrq_m_n_u32): Likewise.
8138 (__arm_vshrq_m_n_u16): Likewise.
8139 (__arm_vsliq_m_n_s8): Likewise.
8140 (__arm_vsliq_m_n_s32): Likewise.
8141 (__arm_vsliq_m_n_s16): Likewise.
8142 (__arm_vsliq_m_n_u8): Likewise.
8143 (__arm_vsliq_m_n_u32): Likewise.
8144 (__arm_vsliq_m_n_u16): Likewise.
8145 (__arm_vsubq_m_n_s8): Likewise.
8146 (__arm_vsubq_m_n_s32): Likewise.
8147 (__arm_vsubq_m_n_s16): Likewise.
8148 (__arm_vsubq_m_n_u8): Likewise.
8149 (__arm_vsubq_m_n_u32): Likewise.
8150 (__arm_vsubq_m_n_u16): Likewise.
8151 (vqdmladhq_m): Define polymorphic variant.
8152 (vqdmladhxq_m): Likewise.
8153 (vqdmlsdhq_m): Likewise.
8154 (vqdmlsdhxq_m): Likewise.
8155 (vabdq_m): Likewise.
8156 (vandq_m): Likewise.
8157 (vbicq_m): Likewise.
8158 (vbrsrq_m_n): Likewise.
8159 (vcaddq_rot270_m): Likewise.
8160 (vcaddq_rot90_m): Likewise.
8161 (veorq_m): Likewise.
8162 (vmaxq_m): Likewise.
8163 (vminq_m): Likewise.
8164 (vmladavaq_p): Likewise.
8165 (vmlaq_m_n): Likewise.
8166 (vmlasq_m_n): Likewise.
8167 (vmulhq_m): Likewise.
8168 (vmullbq_int_m): Likewise.
8169 (vmulltq_int_m): Likewise.
8170 (vornq_m): Likewise.
8171 (vorrq_m): Likewise.
8172 (vqdmlahq_m_n): Likewise.
8173 (vqrdmlahq_m_n): Likewise.
8174 (vqrdmlashq_m_n): Likewise.
8175 (vqrshlq_m): Likewise.
8176 (vqshlq_m_n): Likewise.
8177 (vqshlq_m): Likewise.
8178 (vrhaddq_m): Likewise.
8179 (vrmulhq_m): Likewise.
8180 (vrshlq_m): Likewise.
8181 (vrshrq_m_n): Likewise.
8182 (vshlq_m_n): Likewise.
8183 (vshrq_m_n): Likewise.
8184 (vsliq_m): Likewise.
8185 (vaddq_m_n): Likewise.
8186 (vaddq_m): Likewise.
8187 (vhaddq_m_n): Likewise.
8188 (vhaddq_m): Likewise.
8189 (vhcaddq_rot270_m): Likewise.
8190 (vhcaddq_rot90_m): Likewise.
8191 (vhsubq_m): Likewise.
8192 (vhsubq_m_n): Likewise.
8193 (vmulq_m_n): Likewise.
8194 (vmulq_m): Likewise.
8195 (vqaddq_m_n): Likewise.
8196 (vqaddq_m): Likewise.
8197 (vqdmulhq_m_n): Likewise.
8198 (vqdmulhq_m): Likewise.
8199 (vsubq_m_n): Likewise.
8200 (vsliq_m_n): Likewise.
8201 (vqsubq_m_n): Likewise.
8202 (vqsubq_m): Likewise.
8203 (vqrdmulhq_m): Likewise.
8204 (vqrdmulhq_m_n): Likewise.
8205 (vqrdmlsdhxq_m): Likewise.
8206 (vqrdmlsdhq_m): Likewise.
8207 (vqrdmladhq_m): Likewise.
8208 (vqrdmladhxq_m): Likewise.
8209 (vmlsdavaxq_p): Likewise.
8210 (vmlsdavaq_p): Likewise.
8211 (vmladavaxq_p): Likewise.
8212 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
8214 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
8215 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
8216 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
8217 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
8218 * config/arm/mve.md (VHSUBQ_M): Define iterators.
8219 (VSLIQ_M_N): Likewise.
8220 (VQRDMLAHQ_M_N): Likewise.
8221 (VRSHLQ_M): Likewise.
8222 (VMINQ_M): Likewise.
8223 (VMULLBQ_INT_M): Likewise.
8224 (VMULHQ_M): Likewise.
8225 (VMULQ_M): Likewise.
8226 (VHSUBQ_M_N): Likewise.
8227 (VHADDQ_M_N): Likewise.
8228 (VORRQ_M): Likewise.
8229 (VRMULHQ_M): Likewise.
8230 (VQADDQ_M): Likewise.
8231 (VRSHRQ_M_N): Likewise.
8232 (VQSUBQ_M_N): Likewise.
8233 (VADDQ_M): Likewise.
8234 (VORNQ_M): Likewise.
8235 (VQDMLAHQ_M_N): Likewise.
8236 (VRHADDQ_M): Likewise.
8237 (VQSHLQ_M): Likewise.
8238 (VANDQ_M): Likewise.
8239 (VBICQ_M): Likewise.
8240 (VSHLQ_M_N): Likewise.
8241 (VCADDQ_ROT270_M): Likewise.
8242 (VQRSHLQ_M): Likewise.
8243 (VQADDQ_M_N): Likewise.
8244 (VADDQ_M_N): Likewise.
8245 (VMAXQ_M): Likewise.
8246 (VQSUBQ_M): Likewise.
8247 (VMLASQ_M_N): Likewise.
8248 (VMLADAVAQ_P): Likewise.
8249 (VBRSRQ_M_N): Likewise.
8250 (VMULQ_M_N): Likewise.
8251 (VCADDQ_ROT90_M): Likewise.
8252 (VMULLTQ_INT_M): Likewise.
8253 (VEORQ_M): Likewise.
8254 (VSHRQ_M_N): Likewise.
8255 (VSUBQ_M_N): Likewise.
8256 (VHADDQ_M): Likewise.
8257 (VABDQ_M): Likewise.
8258 (VQRDMLASHQ_M_N): Likewise.
8259 (VMLAQ_M_N): Likewise.
8260 (VQSHLQ_M_N): Likewise.
8261 (mve_vabdq_m_<supf><mode>): Define RTL pattern.
8262 (mve_vaddq_m_n_<supf><mode>): Likewise.
8263 (mve_vaddq_m_<supf><mode>): Likewise.
8264 (mve_vandq_m_<supf><mode>): Likewise.
8265 (mve_vbicq_m_<supf><mode>): Likewise.
8266 (mve_vbrsrq_m_n_<supf><mode>): Likewise.
8267 (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
8268 (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
8269 (mve_veorq_m_<supf><mode>): Likewise.
8270 (mve_vhaddq_m_n_<supf><mode>): Likewise.
8271 (mve_vhaddq_m_<supf><mode>): Likewise.
8272 (mve_vhsubq_m_n_<supf><mode>): Likewise.
8273 (mve_vhsubq_m_<supf><mode>): Likewise.
8274 (mve_vmaxq_m_<supf><mode>): Likewise.
8275 (mve_vminq_m_<supf><mode>): Likewise.
8276 (mve_vmladavaq_p_<supf><mode>): Likewise.
8277 (mve_vmlaq_m_n_<supf><mode>): Likewise.
8278 (mve_vmlasq_m_n_<supf><mode>): Likewise.
8279 (mve_vmulhq_m_<supf><mode>): Likewise.
8280 (mve_vmullbq_int_m_<supf><mode>): Likewise.
8281 (mve_vmulltq_int_m_<supf><mode>): Likewise.
8282 (mve_vmulq_m_n_<supf><mode>): Likewise.
8283 (mve_vmulq_m_<supf><mode>): Likewise.
8284 (mve_vornq_m_<supf><mode>): Likewise.
8285 (mve_vorrq_m_<supf><mode>): Likewise.
8286 (mve_vqaddq_m_n_<supf><mode>): Likewise.
8287 (mve_vqaddq_m_<supf><mode>): Likewise.
8288 (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
8289 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
8290 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
8291 (mve_vqrshlq_m_<supf><mode>): Likewise.
8292 (mve_vqshlq_m_n_<supf><mode>): Likewise.
8293 (mve_vqshlq_m_<supf><mode>): Likewise.
8294 (mve_vqsubq_m_n_<supf><mode>): Likewise.
8295 (mve_vqsubq_m_<supf><mode>): Likewise.
8296 (mve_vrhaddq_m_<supf><mode>): Likewise.
8297 (mve_vrmulhq_m_<supf><mode>): Likewise.
8298 (mve_vrshlq_m_<supf><mode>): Likewise.
8299 (mve_vrshrq_m_n_<supf><mode>): Likewise.
8300 (mve_vshlq_m_n_<supf><mode>): Likewise.
8301 (mve_vshrq_m_n_<supf><mode>): Likewise.
8302 (mve_vsliq_m_n_<supf><mode>): Likewise.
8303 (mve_vsubq_m_n_<supf><mode>): Likewise.
8304 (mve_vhcaddq_rot270_m_s<mode>): Likewise.
8305 (mve_vhcaddq_rot90_m_s<mode>): Likewise.
8306 (mve_vmladavaxq_p_s<mode>): Likewise.
8307 (mve_vmlsdavaq_p_s<mode>): Likewise.
8308 (mve_vmlsdavaxq_p_s<mode>): Likewise.
8309 (mve_vqdmladhq_m_s<mode>): Likewise.
8310 (mve_vqdmladhxq_m_s<mode>): Likewise.
8311 (mve_vqdmlsdhq_m_s<mode>): Likewise.
8312 (mve_vqdmlsdhxq_m_s<mode>): Likewise.
8313 (mve_vqdmulhq_m_n_s<mode>): Likewise.
8314 (mve_vqdmulhq_m_s<mode>): Likewise.
8315 (mve_vqrdmladhq_m_s<mode>): Likewise.
8316 (mve_vqrdmladhxq_m_s<mode>): Likewise.
8317 (mve_vqrdmlsdhq_m_s<mode>): Likewise.
8318 (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
8319 (mve_vqrdmulhq_m_n_s<mode>): Likewise.
8320 (mve_vqrdmulhq_m_s<mode>): Likewise.
8322 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8323 Mihail Ionescu <mihail.ionescu@arm.com>
8324 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8326 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
8327 Define builtin qualifier.
8328 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8329 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8330 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8331 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8332 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8333 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8334 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8335 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
8336 (vsubq_m_s8): Likewise.
8337 (vcvtq_m_n_f16_u16): Likewise.
8338 (vqshluq_m_n_s8): Likewise.
8339 (vabavq_p_s8): Likewise.
8340 (vsriq_m_n_u8): Likewise.
8341 (vshlq_m_u8): Likewise.
8342 (vsubq_m_u8): Likewise.
8343 (vabavq_p_u8): Likewise.
8344 (vshlq_m_s8): Likewise.
8345 (vcvtq_m_n_f16_s16): Likewise.
8346 (vsriq_m_n_s16): Likewise.
8347 (vsubq_m_s16): Likewise.
8348 (vcvtq_m_n_f32_u32): Likewise.
8349 (vqshluq_m_n_s16): Likewise.
8350 (vabavq_p_s16): Likewise.
8351 (vsriq_m_n_u16): Likewise.
8352 (vshlq_m_u16): Likewise.
8353 (vsubq_m_u16): Likewise.
8354 (vabavq_p_u16): Likewise.
8355 (vshlq_m_s16): Likewise.
8356 (vcvtq_m_n_f32_s32): Likewise.
8357 (vsriq_m_n_s32): Likewise.
8358 (vsubq_m_s32): Likewise.
8359 (vqshluq_m_n_s32): Likewise.
8360 (vabavq_p_s32): Likewise.
8361 (vsriq_m_n_u32): Likewise.
8362 (vshlq_m_u32): Likewise.
8363 (vsubq_m_u32): Likewise.
8364 (vabavq_p_u32): Likewise.
8365 (vshlq_m_s32): Likewise.
8366 (__arm_vsriq_m_n_s8): Define intrinsic.
8367 (__arm_vsubq_m_s8): Likewise.
8368 (__arm_vqshluq_m_n_s8): Likewise.
8369 (__arm_vabavq_p_s8): Likewise.
8370 (__arm_vsriq_m_n_u8): Likewise.
8371 (__arm_vshlq_m_u8): Likewise.
8372 (__arm_vsubq_m_u8): Likewise.
8373 (__arm_vabavq_p_u8): Likewise.
8374 (__arm_vshlq_m_s8): Likewise.
8375 (__arm_vsriq_m_n_s16): Likewise.
8376 (__arm_vsubq_m_s16): Likewise.
8377 (__arm_vqshluq_m_n_s16): Likewise.
8378 (__arm_vabavq_p_s16): Likewise.
8379 (__arm_vsriq_m_n_u16): Likewise.
8380 (__arm_vshlq_m_u16): Likewise.
8381 (__arm_vsubq_m_u16): Likewise.
8382 (__arm_vabavq_p_u16): Likewise.
8383 (__arm_vshlq_m_s16): Likewise.
8384 (__arm_vsriq_m_n_s32): Likewise.
8385 (__arm_vsubq_m_s32): Likewise.
8386 (__arm_vqshluq_m_n_s32): Likewise.
8387 (__arm_vabavq_p_s32): Likewise.
8388 (__arm_vsriq_m_n_u32): Likewise.
8389 (__arm_vshlq_m_u32): Likewise.
8390 (__arm_vsubq_m_u32): Likewise.
8391 (__arm_vabavq_p_u32): Likewise.
8392 (__arm_vshlq_m_s32): Likewise.
8393 (__arm_vcvtq_m_n_f16_u16): Likewise.
8394 (__arm_vcvtq_m_n_f16_s16): Likewise.
8395 (__arm_vcvtq_m_n_f32_u32): Likewise.
8396 (__arm_vcvtq_m_n_f32_s32): Likewise.
8397 (vcvtq_m_n): Define polymorphic variant.
8398 (vqshluq_m_n): Likewise.
8399 (vshlq_m): Likewise.
8400 (vsriq_m_n): Likewise.
8401 (vsubq_m): Likewise.
8402 (vabavq_p): Likewise.
8403 * config/arm/arm_mve_builtins.def
8404 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
8405 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8406 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8407 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8408 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8409 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8410 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8411 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8412 * config/arm/mve.md (VABAVQ_P): Define iterator.
8413 (VSHLQ_M): Likewise.
8414 (VSRIQ_M_N): Likewise.
8415 (VSUBQ_M): Likewise.
8416 (VCVTQ_M_N_TO_F): Likewise.
8417 (mve_vabavq_p_<supf><mode>): Define RTL pattern.
8418 (mve_vqshluq_m_n_s<mode>): Likewise.
8419 (mve_vshlq_m_<supf><mode>): Likewise.
8420 (mve_vsriq_m_n_<supf><mode>): Likewise.
8421 (mve_vsubq_m_<supf><mode>): Likewise.
8422 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
8424 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8425 Mihail Ionescu <mihail.ionescu@arm.com>
8426 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8428 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
8429 (vrmlsldavhaq_s32): Likewise.
8430 (vrmlsldavhaxq_s32): Likewise.
8431 (vaddlvaq_p_s32): Likewise.
8432 (vcvtbq_m_f16_f32): Likewise.
8433 (vcvtbq_m_f32_f16): Likewise.
8434 (vcvttq_m_f16_f32): Likewise.
8435 (vcvttq_m_f32_f16): Likewise.
8436 (vrev16q_m_s8): Likewise.
8437 (vrev32q_m_f16): Likewise.
8438 (vrmlaldavhq_p_s32): Likewise.
8439 (vrmlaldavhxq_p_s32): Likewise.
8440 (vrmlsldavhq_p_s32): Likewise.
8441 (vrmlsldavhxq_p_s32): Likewise.
8442 (vaddlvaq_p_u32): Likewise.
8443 (vrev16q_m_u8): Likewise.
8444 (vrmlaldavhq_p_u32): Likewise.
8445 (vmvnq_m_n_s16): Likewise.
8446 (vorrq_m_n_s16): Likewise.
8447 (vqrshrntq_n_s16): Likewise.
8448 (vqshrnbq_n_s16): Likewise.
8449 (vqshrntq_n_s16): Likewise.
8450 (vrshrnbq_n_s16): Likewise.
8451 (vrshrntq_n_s16): Likewise.
8452 (vshrnbq_n_s16): Likewise.
8453 (vshrntq_n_s16): Likewise.
8454 (vcmlaq_f16): Likewise.
8455 (vcmlaq_rot180_f16): Likewise.
8456 (vcmlaq_rot270_f16): Likewise.
8457 (vcmlaq_rot90_f16): Likewise.
8458 (vfmaq_f16): Likewise.
8459 (vfmaq_n_f16): Likewise.
8460 (vfmasq_n_f16): Likewise.
8461 (vfmsq_f16): Likewise.
8462 (vmlaldavaq_s16): Likewise.
8463 (vmlaldavaxq_s16): Likewise.
8464 (vmlsldavaq_s16): Likewise.
8465 (vmlsldavaxq_s16): Likewise.
8466 (vabsq_m_f16): Likewise.
8467 (vcvtmq_m_s16_f16): Likewise.
8468 (vcvtnq_m_s16_f16): Likewise.
8469 (vcvtpq_m_s16_f16): Likewise.
8470 (vcvtq_m_s16_f16): Likewise.
8471 (vdupq_m_n_f16): Likewise.
8472 (vmaxnmaq_m_f16): Likewise.
8473 (vmaxnmavq_p_f16): Likewise.
8474 (vmaxnmvq_p_f16): Likewise.
8475 (vminnmaq_m_f16): Likewise.
8476 (vminnmavq_p_f16): Likewise.
8477 (vminnmvq_p_f16): Likewise.
8478 (vmlaldavq_p_s16): Likewise.
8479 (vmlaldavxq_p_s16): Likewise.
8480 (vmlsldavq_p_s16): Likewise.
8481 (vmlsldavxq_p_s16): Likewise.
8482 (vmovlbq_m_s8): Likewise.
8483 (vmovltq_m_s8): Likewise.
8484 (vmovnbq_m_s16): Likewise.
8485 (vmovntq_m_s16): Likewise.
8486 (vnegq_m_f16): Likewise.
8487 (vpselq_f16): Likewise.
8488 (vqmovnbq_m_s16): Likewise.
8489 (vqmovntq_m_s16): Likewise.
8490 (vrev32q_m_s8): Likewise.
8491 (vrev64q_m_f16): Likewise.
8492 (vrndaq_m_f16): Likewise.
8493 (vrndmq_m_f16): Likewise.
8494 (vrndnq_m_f16): Likewise.
8495 (vrndpq_m_f16): Likewise.
8496 (vrndq_m_f16): Likewise.
8497 (vrndxq_m_f16): Likewise.
8498 (vcmpeqq_m_n_f16): Likewise.
8499 (vcmpgeq_m_f16): Likewise.
8500 (vcmpgeq_m_n_f16): Likewise.
8501 (vcmpgtq_m_f16): Likewise.
8502 (vcmpgtq_m_n_f16): Likewise.
8503 (vcmpleq_m_f16): Likewise.
8504 (vcmpleq_m_n_f16): Likewise.
8505 (vcmpltq_m_f16): Likewise.
8506 (vcmpltq_m_n_f16): Likewise.
8507 (vcmpneq_m_f16): Likewise.
8508 (vcmpneq_m_n_f16): Likewise.
8509 (vmvnq_m_n_u16): Likewise.
8510 (vorrq_m_n_u16): Likewise.
8511 (vqrshruntq_n_s16): Likewise.
8512 (vqshrunbq_n_s16): Likewise.
8513 (vqshruntq_n_s16): Likewise.
8514 (vcvtmq_m_u16_f16): Likewise.
8515 (vcvtnq_m_u16_f16): Likewise.
8516 (vcvtpq_m_u16_f16): Likewise.
8517 (vcvtq_m_u16_f16): Likewise.
8518 (vqmovunbq_m_s16): Likewise.
8519 (vqmovuntq_m_s16): Likewise.
8520 (vqrshrntq_n_u16): Likewise.
8521 (vqshrnbq_n_u16): Likewise.
8522 (vqshrntq_n_u16): Likewise.
8523 (vrshrnbq_n_u16): Likewise.
8524 (vrshrntq_n_u16): Likewise.
8525 (vshrnbq_n_u16): Likewise.
8526 (vshrntq_n_u16): Likewise.
8527 (vmlaldavaq_u16): Likewise.
8528 (vmlaldavaxq_u16): Likewise.
8529 (vmlaldavq_p_u16): Likewise.
8530 (vmlaldavxq_p_u16): Likewise.
8531 (vmovlbq_m_u8): Likewise.
8532 (vmovltq_m_u8): Likewise.
8533 (vmovnbq_m_u16): Likewise.
8534 (vmovntq_m_u16): Likewise.
8535 (vqmovnbq_m_u16): Likewise.
8536 (vqmovntq_m_u16): Likewise.
8537 (vrev32q_m_u8): Likewise.
8538 (vmvnq_m_n_s32): Likewise.
8539 (vorrq_m_n_s32): Likewise.
8540 (vqrshrntq_n_s32): Likewise.
8541 (vqshrnbq_n_s32): Likewise.
8542 (vqshrntq_n_s32): Likewise.
8543 (vrshrnbq_n_s32): Likewise.
8544 (vrshrntq_n_s32): Likewise.
8545 (vshrnbq_n_s32): Likewise.
8546 (vshrntq_n_s32): Likewise.
8547 (vcmlaq_f32): Likewise.
8548 (vcmlaq_rot180_f32): Likewise.
8549 (vcmlaq_rot270_f32): Likewise.
8550 (vcmlaq_rot90_f32): Likewise.
8551 (vfmaq_f32): Likewise.
8552 (vfmaq_n_f32): Likewise.
8553 (vfmasq_n_f32): Likewise.
8554 (vfmsq_f32): Likewise.
8555 (vmlaldavaq_s32): Likewise.
8556 (vmlaldavaxq_s32): Likewise.
8557 (vmlsldavaq_s32): Likewise.
8558 (vmlsldavaxq_s32): Likewise.
8559 (vabsq_m_f32): Likewise.
8560 (vcvtmq_m_s32_f32): Likewise.
8561 (vcvtnq_m_s32_f32): Likewise.
8562 (vcvtpq_m_s32_f32): Likewise.
8563 (vcvtq_m_s32_f32): Likewise.
8564 (vdupq_m_n_f32): Likewise.
8565 (vmaxnmaq_m_f32): Likewise.
8566 (vmaxnmavq_p_f32): Likewise.
8567 (vmaxnmvq_p_f32): Likewise.
8568 (vminnmaq_m_f32): Likewise.
8569 (vminnmavq_p_f32): Likewise.
8570 (vminnmvq_p_f32): Likewise.
8571 (vmlaldavq_p_s32): Likewise.
8572 (vmlaldavxq_p_s32): Likewise.
8573 (vmlsldavq_p_s32): Likewise.
8574 (vmlsldavxq_p_s32): Likewise.
8575 (vmovlbq_m_s16): Likewise.
8576 (vmovltq_m_s16): Likewise.
8577 (vmovnbq_m_s32): Likewise.
8578 (vmovntq_m_s32): Likewise.
8579 (vnegq_m_f32): Likewise.
8580 (vpselq_f32): Likewise.
8581 (vqmovnbq_m_s32): Likewise.
8582 (vqmovntq_m_s32): Likewise.
8583 (vrev32q_m_s16): Likewise.
8584 (vrev64q_m_f32): Likewise.
8585 (vrndaq_m_f32): Likewise.
8586 (vrndmq_m_f32): Likewise.
8587 (vrndnq_m_f32): Likewise.
8588 (vrndpq_m_f32): Likewise.
8589 (vrndq_m_f32): Likewise.
8590 (vrndxq_m_f32): Likewise.
8591 (vcmpeqq_m_n_f32): Likewise.
8592 (vcmpgeq_m_f32): Likewise.
8593 (vcmpgeq_m_n_f32): Likewise.
8594 (vcmpgtq_m_f32): Likewise.
8595 (vcmpgtq_m_n_f32): Likewise.
8596 (vcmpleq_m_f32): Likewise.
8597 (vcmpleq_m_n_f32): Likewise.
8598 (vcmpltq_m_f32): Likewise.
8599 (vcmpltq_m_n_f32): Likewise.
8600 (vcmpneq_m_f32): Likewise.
8601 (vcmpneq_m_n_f32): Likewise.
8602 (vmvnq_m_n_u32): Likewise.
8603 (vorrq_m_n_u32): Likewise.
8604 (vqrshruntq_n_s32): Likewise.
8605 (vqshrunbq_n_s32): Likewise.
8606 (vqshruntq_n_s32): Likewise.
8607 (vcvtmq_m_u32_f32): Likewise.
8608 (vcvtnq_m_u32_f32): Likewise.
8609 (vcvtpq_m_u32_f32): Likewise.
8610 (vcvtq_m_u32_f32): Likewise.
8611 (vqmovunbq_m_s32): Likewise.
8612 (vqmovuntq_m_s32): Likewise.
8613 (vqrshrntq_n_u32): Likewise.
8614 (vqshrnbq_n_u32): Likewise.
8615 (vqshrntq_n_u32): Likewise.
8616 (vrshrnbq_n_u32): Likewise.
8617 (vrshrntq_n_u32): Likewise.
8618 (vshrnbq_n_u32): Likewise.
8619 (vshrntq_n_u32): Likewise.
8620 (vmlaldavaq_u32): Likewise.
8621 (vmlaldavaxq_u32): Likewise.
8622 (vmlaldavq_p_u32): Likewise.
8623 (vmlaldavxq_p_u32): Likewise.
8624 (vmovlbq_m_u16): Likewise.
8625 (vmovltq_m_u16): Likewise.
8626 (vmovnbq_m_u32): Likewise.
8627 (vmovntq_m_u32): Likewise.
8628 (vqmovnbq_m_u32): Likewise.
8629 (vqmovntq_m_u32): Likewise.
8630 (vrev32q_m_u16): Likewise.
8631 (__arm_vrmlaldavhaxq_s32): Define intrinsic.
8632 (__arm_vrmlsldavhaq_s32): Likewise.
8633 (__arm_vrmlsldavhaxq_s32): Likewise.
8634 (__arm_vaddlvaq_p_s32): Likewise.
8635 (__arm_vrev16q_m_s8): Likewise.
8636 (__arm_vrmlaldavhq_p_s32): Likewise.
8637 (__arm_vrmlaldavhxq_p_s32): Likewise.
8638 (__arm_vrmlsldavhq_p_s32): Likewise.
8639 (__arm_vrmlsldavhxq_p_s32): Likewise.
8640 (__arm_vaddlvaq_p_u32): Likewise.
8641 (__arm_vrev16q_m_u8): Likewise.
8642 (__arm_vrmlaldavhq_p_u32): Likewise.
8643 (__arm_vmvnq_m_n_s16): Likewise.
8644 (__arm_vorrq_m_n_s16): Likewise.
8645 (__arm_vqrshrntq_n_s16): Likewise.
8646 (__arm_vqshrnbq_n_s16): Likewise.
8647 (__arm_vqshrntq_n_s16): Likewise.
8648 (__arm_vrshrnbq_n_s16): Likewise.
8649 (__arm_vrshrntq_n_s16): Likewise.
8650 (__arm_vshrnbq_n_s16): Likewise.
8651 (__arm_vshrntq_n_s16): Likewise.
8652 (__arm_vmlaldavaq_s16): Likewise.
8653 (__arm_vmlaldavaxq_s16): Likewise.
8654 (__arm_vmlsldavaq_s16): Likewise.
8655 (__arm_vmlsldavaxq_s16): Likewise.
8656 (__arm_vmlaldavq_p_s16): Likewise.
8657 (__arm_vmlaldavxq_p_s16): Likewise.
8658 (__arm_vmlsldavq_p_s16): Likewise.
8659 (__arm_vmlsldavxq_p_s16): Likewise.
8660 (__arm_vmovlbq_m_s8): Likewise.
8661 (__arm_vmovltq_m_s8): Likewise.
8662 (__arm_vmovnbq_m_s16): Likewise.
8663 (__arm_vmovntq_m_s16): Likewise.
8664 (__arm_vqmovnbq_m_s16): Likewise.
8665 (__arm_vqmovntq_m_s16): Likewise.
8666 (__arm_vrev32q_m_s8): Likewise.
8667 (__arm_vmvnq_m_n_u16): Likewise.
8668 (__arm_vorrq_m_n_u16): Likewise.
8669 (__arm_vqrshruntq_n_s16): Likewise.
8670 (__arm_vqshrunbq_n_s16): Likewise.
8671 (__arm_vqshruntq_n_s16): Likewise.
8672 (__arm_vqmovunbq_m_s16): Likewise.
8673 (__arm_vqmovuntq_m_s16): Likewise.
8674 (__arm_vqrshrntq_n_u16): Likewise.
8675 (__arm_vqshrnbq_n_u16): Likewise.
8676 (__arm_vqshrntq_n_u16): Likewise.
8677 (__arm_vrshrnbq_n_u16): Likewise.
8678 (__arm_vrshrntq_n_u16): Likewise.
8679 (__arm_vshrnbq_n_u16): Likewise.
8680 (__arm_vshrntq_n_u16): Likewise.
8681 (__arm_vmlaldavaq_u16): Likewise.
8682 (__arm_vmlaldavaxq_u16): Likewise.
8683 (__arm_vmlaldavq_p_u16): Likewise.
8684 (__arm_vmlaldavxq_p_u16): Likewise.
8685 (__arm_vmovlbq_m_u8): Likewise.
8686 (__arm_vmovltq_m_u8): Likewise.
8687 (__arm_vmovnbq_m_u16): Likewise.
8688 (__arm_vmovntq_m_u16): Likewise.
8689 (__arm_vqmovnbq_m_u16): Likewise.
8690 (__arm_vqmovntq_m_u16): Likewise.
8691 (__arm_vrev32q_m_u8): Likewise.
8692 (__arm_vmvnq_m_n_s32): Likewise.
8693 (__arm_vorrq_m_n_s32): Likewise.
8694 (__arm_vqrshrntq_n_s32): Likewise.
8695 (__arm_vqshrnbq_n_s32): Likewise.
8696 (__arm_vqshrntq_n_s32): Likewise.
8697 (__arm_vrshrnbq_n_s32): Likewise.
8698 (__arm_vrshrntq_n_s32): Likewise.
8699 (__arm_vshrnbq_n_s32): Likewise.
8700 (__arm_vshrntq_n_s32): Likewise.
8701 (__arm_vmlaldavaq_s32): Likewise.
8702 (__arm_vmlaldavaxq_s32): Likewise.
8703 (__arm_vmlsldavaq_s32): Likewise.
8704 (__arm_vmlsldavaxq_s32): Likewise.
8705 (__arm_vmlaldavq_p_s32): Likewise.
8706 (__arm_vmlaldavxq_p_s32): Likewise.
8707 (__arm_vmlsldavq_p_s32): Likewise.
8708 (__arm_vmlsldavxq_p_s32): Likewise.
8709 (__arm_vmovlbq_m_s16): Likewise.
8710 (__arm_vmovltq_m_s16): Likewise.
8711 (__arm_vmovnbq_m_s32): Likewise.
8712 (__arm_vmovntq_m_s32): Likewise.
8713 (__arm_vqmovnbq_m_s32): Likewise.
8714 (__arm_vqmovntq_m_s32): Likewise.
8715 (__arm_vrev32q_m_s16): Likewise.
8716 (__arm_vmvnq_m_n_u32): Likewise.
8717 (__arm_vorrq_m_n_u32): Likewise.
8718 (__arm_vqrshruntq_n_s32): Likewise.
8719 (__arm_vqshrunbq_n_s32): Likewise.
8720 (__arm_vqshruntq_n_s32): Likewise.
8721 (__arm_vqmovunbq_m_s32): Likewise.
8722 (__arm_vqmovuntq_m_s32): Likewise.
8723 (__arm_vqrshrntq_n_u32): Likewise.
8724 (__arm_vqshrnbq_n_u32): Likewise.
8725 (__arm_vqshrntq_n_u32): Likewise.
8726 (__arm_vrshrnbq_n_u32): Likewise.
8727 (__arm_vrshrntq_n_u32): Likewise.
8728 (__arm_vshrnbq_n_u32): Likewise.
8729 (__arm_vshrntq_n_u32): Likewise.
8730 (__arm_vmlaldavaq_u32): Likewise.
8731 (__arm_vmlaldavaxq_u32): Likewise.
8732 (__arm_vmlaldavq_p_u32): Likewise.
8733 (__arm_vmlaldavxq_p_u32): Likewise.
8734 (__arm_vmovlbq_m_u16): Likewise.
8735 (__arm_vmovltq_m_u16): Likewise.
8736 (__arm_vmovnbq_m_u32): Likewise.
8737 (__arm_vmovntq_m_u32): Likewise.
8738 (__arm_vqmovnbq_m_u32): Likewise.
8739 (__arm_vqmovntq_m_u32): Likewise.
8740 (__arm_vrev32q_m_u16): Likewise.
8741 (__arm_vcvtbq_m_f16_f32): Likewise.
8742 (__arm_vcvtbq_m_f32_f16): Likewise.
8743 (__arm_vcvttq_m_f16_f32): Likewise.
8744 (__arm_vcvttq_m_f32_f16): Likewise.
8745 (__arm_vrev32q_m_f16): Likewise.
8746 (__arm_vcmlaq_f16): Likewise.
8747 (__arm_vcmlaq_rot180_f16): Likewise.
8748 (__arm_vcmlaq_rot270_f16): Likewise.
8749 (__arm_vcmlaq_rot90_f16): Likewise.
8750 (__arm_vfmaq_f16): Likewise.
8751 (__arm_vfmaq_n_f16): Likewise.
8752 (__arm_vfmasq_n_f16): Likewise.
8753 (__arm_vfmsq_f16): Likewise.
8754 (__arm_vabsq_m_f16): Likewise.
8755 (__arm_vcvtmq_m_s16_f16): Likewise.
8756 (__arm_vcvtnq_m_s16_f16): Likewise.
8757 (__arm_vcvtpq_m_s16_f16): Likewise.
8758 (__arm_vcvtq_m_s16_f16): Likewise.
8759 (__arm_vdupq_m_n_f16): Likewise.
8760 (__arm_vmaxnmaq_m_f16): Likewise.
8761 (__arm_vmaxnmavq_p_f16): Likewise.
8762 (__arm_vmaxnmvq_p_f16): Likewise.
8763 (__arm_vminnmaq_m_f16): Likewise.
8764 (__arm_vminnmavq_p_f16): Likewise.
8765 (__arm_vminnmvq_p_f16): Likewise.
8766 (__arm_vnegq_m_f16): Likewise.
8767 (__arm_vpselq_f16): Likewise.
8768 (__arm_vrev64q_m_f16): Likewise.
8769 (__arm_vrndaq_m_f16): Likewise.
8770 (__arm_vrndmq_m_f16): Likewise.
8771 (__arm_vrndnq_m_f16): Likewise.
8772 (__arm_vrndpq_m_f16): Likewise.
8773 (__arm_vrndq_m_f16): Likewise.
8774 (__arm_vrndxq_m_f16): Likewise.
8775 (__arm_vcmpeqq_m_n_f16): Likewise.
8776 (__arm_vcmpgeq_m_f16): Likewise.
8777 (__arm_vcmpgeq_m_n_f16): Likewise.
8778 (__arm_vcmpgtq_m_f16): Likewise.
8779 (__arm_vcmpgtq_m_n_f16): Likewise.
8780 (__arm_vcmpleq_m_f16): Likewise.
8781 (__arm_vcmpleq_m_n_f16): Likewise.
8782 (__arm_vcmpltq_m_f16): Likewise.
8783 (__arm_vcmpltq_m_n_f16): Likewise.
8784 (__arm_vcmpneq_m_f16): Likewise.
8785 (__arm_vcmpneq_m_n_f16): Likewise.
8786 (__arm_vcvtmq_m_u16_f16): Likewise.
8787 (__arm_vcvtnq_m_u16_f16): Likewise.
8788 (__arm_vcvtpq_m_u16_f16): Likewise.
8789 (__arm_vcvtq_m_u16_f16): Likewise.
8790 (__arm_vcmlaq_f32): Likewise.
8791 (__arm_vcmlaq_rot180_f32): Likewise.
8792 (__arm_vcmlaq_rot270_f32): Likewise.
8793 (__arm_vcmlaq_rot90_f32): Likewise.
8794 (__arm_vfmaq_f32): Likewise.
8795 (__arm_vfmaq_n_f32): Likewise.
8796 (__arm_vfmasq_n_f32): Likewise.
8797 (__arm_vfmsq_f32): Likewise.
8798 (__arm_vabsq_m_f32): Likewise.
8799 (__arm_vcvtmq_m_s32_f32): Likewise.
8800 (__arm_vcvtnq_m_s32_f32): Likewise.
8801 (__arm_vcvtpq_m_s32_f32): Likewise.
8802 (__arm_vcvtq_m_s32_f32): Likewise.
8803 (__arm_vdupq_m_n_f32): Likewise.
8804 (__arm_vmaxnmaq_m_f32): Likewise.
8805 (__arm_vmaxnmavq_p_f32): Likewise.
8806 (__arm_vmaxnmvq_p_f32): Likewise.
8807 (__arm_vminnmaq_m_f32): Likewise.
8808 (__arm_vminnmavq_p_f32): Likewise.
8809 (__arm_vminnmvq_p_f32): Likewise.
8810 (__arm_vnegq_m_f32): Likewise.
8811 (__arm_vpselq_f32): Likewise.
8812 (__arm_vrev64q_m_f32): Likewise.
8813 (__arm_vrndaq_m_f32): Likewise.
8814 (__arm_vrndmq_m_f32): Likewise.
8815 (__arm_vrndnq_m_f32): Likewise.
8816 (__arm_vrndpq_m_f32): Likewise.
8817 (__arm_vrndq_m_f32): Likewise.
8818 (__arm_vrndxq_m_f32): Likewise.
8819 (__arm_vcmpeqq_m_n_f32): Likewise.
8820 (__arm_vcmpgeq_m_f32): Likewise.
8821 (__arm_vcmpgeq_m_n_f32): Likewise.
8822 (__arm_vcmpgtq_m_f32): Likewise.
8823 (__arm_vcmpgtq_m_n_f32): Likewise.
8824 (__arm_vcmpleq_m_f32): Likewise.
8825 (__arm_vcmpleq_m_n_f32): Likewise.
8826 (__arm_vcmpltq_m_f32): Likewise.
8827 (__arm_vcmpltq_m_n_f32): Likewise.
8828 (__arm_vcmpneq_m_f32): Likewise.
8829 (__arm_vcmpneq_m_n_f32): Likewise.
8830 (__arm_vcvtmq_m_u32_f32): Likewise.
8831 (__arm_vcvtnq_m_u32_f32): Likewise.
8832 (__arm_vcvtpq_m_u32_f32): Likewise.
8833 (__arm_vcvtq_m_u32_f32): Likewise.
8834 (vcvtq_m): Define polymorphic variant.
8835 (vabsq_m): Likewise.
8837 (vcmlaq_rot180): Likewise.
8838 (vcmlaq_rot270): Likewise.
8839 (vcmlaq_rot90): Likewise.
8840 (vcmpeqq_m_n): Likewise.
8841 (vcmpgeq_m_n): Likewise.
8842 (vrndxq_m): Likewise.
8843 (vrndq_m): Likewise.
8844 (vrndpq_m): Likewise.
8845 (vcmpgtq_m_n): Likewise.
8846 (vcmpgtq_m): Likewise.
8847 (vcmpleq_m): Likewise.
8848 (vcmpleq_m_n): Likewise.
8849 (vcmpltq_m_n): Likewise.
8850 (vcmpltq_m): Likewise.
8851 (vcmpneq_m): Likewise.
8852 (vcmpneq_m_n): Likewise.
8853 (vcvtbq_m): Likewise.
8854 (vcvttq_m): Likewise.
8855 (vcvtmq_m): Likewise.
8856 (vcvtnq_m): Likewise.
8857 (vcvtpq_m): Likewise.
8858 (vdupq_m_n): Likewise.
8859 (vfmaq_n): Likewise.
8861 (vfmasq_n): Likewise.
8863 (vmaxnmaq_m): Likewise.
8864 (vmaxnmavq_m): Likewise.
8865 (vmaxnmvq_m): Likewise.
8866 (vmaxnmavq_p): Likewise.
8867 (vmaxnmvq_p): Likewise.
8868 (vminnmaq_m): Likewise.
8869 (vminnmavq_p): Likewise.
8870 (vminnmvq_p): Likewise.
8871 (vrndnq_m): Likewise.
8872 (vrndaq_m): Likewise.
8873 (vrndmq_m): Likewise.
8874 (vrev64q_m): Likewise.
8875 (vrev32q_m): Likewise.
8877 (vnegq_m): Likewise.
8878 (vcmpgeq_m): Likewise.
8879 (vshrntq_n): Likewise.
8880 (vrshrntq_n): Likewise.
8881 (vmovlbq_m): Likewise.
8882 (vmovnbq_m): Likewise.
8883 (vmovntq_m): Likewise.
8884 (vmvnq_m_n): Likewise.
8885 (vmvnq_m): Likewise.
8886 (vshrnbq_n): Likewise.
8887 (vrshrnbq_n): Likewise.
8888 (vqshruntq_n): Likewise.
8889 (vrev16q_m): Likewise.
8890 (vqshrunbq_n): Likewise.
8891 (vqshrntq_n): Likewise.
8892 (vqrshruntq_n): Likewise.
8893 (vqrshrntq_n): Likewise.
8894 (vqshrnbq_n): Likewise.
8895 (vqmovuntq_m): Likewise.
8896 (vqmovntq_m): Likewise.
8897 (vqmovnbq_m): Likewise.
8898 (vorrq_m_n): Likewise.
8899 (vmovltq_m): Likewise.
8900 (vqmovunbq_m): Likewise.
8901 (vaddlvaq_p): Likewise.
8902 (vmlaldavaq): Likewise.
8903 (vmlaldavaxq): Likewise.
8904 (vmlaldavq_p): Likewise.
8905 (vmlaldavxq_p): Likewise.
8906 (vmlsldavaq): Likewise.
8907 (vmlsldavaxq): Likewise.
8908 (vmlsldavq_p): Likewise.
8909 (vmlsldavxq_p): Likewise.
8910 (vrmlaldavhaxq): Likewise.
8911 (vrmlaldavhq_p): Likewise.
8912 (vrmlaldavhxq_p): Likewise.
8913 (vrmlsldavhaq): Likewise.
8914 (vrmlsldavhaxq): Likewise.
8915 (vrmlsldavhq_p): Likewise.
8916 (vrmlsldavhxq_p): Likewise.
8917 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
8919 (TERNOP_NONE_NONE_NONE_IMM): Likewise.
8920 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
8921 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
8922 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
8923 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
8924 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
8925 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
8926 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
8927 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
8928 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
8929 (MVE_pred3): Likewise.
8930 (MVE_constraint1): Likewise.
8931 (MVE_pred1): Likewise.
8932 (VMLALDAVQ_P): Define iterator.
8933 (VQMOVNBQ_M): Likewise.
8934 (VMOVLTQ_M): Likewise.
8935 (VMOVNBQ_M): Likewise.
8936 (VRSHRNTQ_N): Likewise.
8937 (VORRQ_M_N): Likewise.
8938 (VREV32Q_M): Likewise.
8939 (VREV16Q_M): Likewise.
8940 (VQRSHRNTQ_N): Likewise.
8941 (VMOVNTQ_M): Likewise.
8942 (VMOVLBQ_M): Likewise.
8943 (VMLALDAVAQ): Likewise.
8944 (VQSHRNBQ_N): Likewise.
8945 (VSHRNBQ_N): Likewise.
8946 (VRSHRNBQ_N): Likewise.
8947 (VMLALDAVXQ_P): Likewise.
8948 (VQMOVNTQ_M): Likewise.
8949 (VMVNQ_M_N): Likewise.
8950 (VQSHRNTQ_N): Likewise.
8951 (VMLALDAVAXQ): Likewise.
8952 (VSHRNTQ_N): Likewise.
8953 (VCVTMQ_M): Likewise.
8954 (VCVTNQ_M): Likewise.
8955 (VCVTPQ_M): Likewise.
8956 (VCVTQ_M_N_FROM_F): Likewise.
8957 (VCVTQ_M_FROM_F): Likewise.
8958 (VRMLALDAVHQ_P): Likewise.
8959 (VADDLVAQ_P): Likewise.
8960 (mve_vrndq_m_f<mode>): Define RTL pattern.
8961 (mve_vabsq_m_f<mode>): Likewise.
8962 (mve_vaddlvaq_p_<supf>v4si): Likewise.
8963 (mve_vcmlaq_f<mode>): Likewise.
8964 (mve_vcmlaq_rot180_f<mode>): Likewise.
8965 (mve_vcmlaq_rot270_f<mode>): Likewise.
8966 (mve_vcmlaq_rot90_f<mode>): Likewise.
8967 (mve_vcmpeqq_m_n_f<mode>): Likewise.
8968 (mve_vcmpgeq_m_f<mode>): Likewise.
8969 (mve_vcmpgeq_m_n_f<mode>): Likewise.
8970 (mve_vcmpgtq_m_f<mode>): Likewise.
8971 (mve_vcmpgtq_m_n_f<mode>): Likewise.
8972 (mve_vcmpleq_m_f<mode>): Likewise.
8973 (mve_vcmpleq_m_n_f<mode>): Likewise.
8974 (mve_vcmpltq_m_f<mode>): Likewise.
8975 (mve_vcmpltq_m_n_f<mode>): Likewise.
8976 (mve_vcmpneq_m_f<mode>): Likewise.
8977 (mve_vcmpneq_m_n_f<mode>): Likewise.
8978 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
8979 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
8980 (mve_vcvttq_m_f16_f32v8hf): Likewise.
8981 (mve_vcvttq_m_f32_f16v4sf): Likewise.
8982 (mve_vdupq_m_n_f<mode>): Likewise.
8983 (mve_vfmaq_f<mode>): Likewise.
8984 (mve_vfmaq_n_f<mode>): Likewise.
8985 (mve_vfmasq_n_f<mode>): Likewise.
8986 (mve_vfmsq_f<mode>): Likewise.
8987 (mve_vmaxnmaq_m_f<mode>): Likewise.
8988 (mve_vmaxnmavq_p_f<mode>): Likewise.
8989 (mve_vmaxnmvq_p_f<mode>): Likewise.
8990 (mve_vminnmaq_m_f<mode>): Likewise.
8991 (mve_vminnmavq_p_f<mode>): Likewise.
8992 (mve_vminnmvq_p_f<mode>): Likewise.
8993 (mve_vmlaldavaq_<supf><mode>): Likewise.
8994 (mve_vmlaldavaxq_<supf><mode>): Likewise.
8995 (mve_vmlaldavq_p_<supf><mode>): Likewise.
8996 (mve_vmlaldavxq_p_<supf><mode>): Likewise.
8997 (mve_vmlsldavaq_s<mode>): Likewise.
8998 (mve_vmlsldavaxq_s<mode>): Likewise.
8999 (mve_vmlsldavq_p_s<mode>): Likewise.
9000 (mve_vmlsldavxq_p_s<mode>): Likewise.
9001 (mve_vmovlbq_m_<supf><mode>): Likewise.
9002 (mve_vmovltq_m_<supf><mode>): Likewise.
9003 (mve_vmovnbq_m_<supf><mode>): Likewise.
9004 (mve_vmovntq_m_<supf><mode>): Likewise.
9005 (mve_vmvnq_m_n_<supf><mode>): Likewise.
9006 (mve_vnegq_m_f<mode>): Likewise.
9007 (mve_vorrq_m_n_<supf><mode>): Likewise.
9008 (mve_vpselq_f<mode>): Likewise.
9009 (mve_vqmovnbq_m_<supf><mode>): Likewise.
9010 (mve_vqmovntq_m_<supf><mode>): Likewise.
9011 (mve_vqmovunbq_m_s<mode>): Likewise.
9012 (mve_vqmovuntq_m_s<mode>): Likewise.
9013 (mve_vqrshrntq_n_<supf><mode>): Likewise.
9014 (mve_vqrshruntq_n_s<mode>): Likewise.
9015 (mve_vqshrnbq_n_<supf><mode>): Likewise.
9016 (mve_vqshrntq_n_<supf><mode>): Likewise.
9017 (mve_vqshrunbq_n_s<mode>): Likewise.
9018 (mve_vqshruntq_n_s<mode>): Likewise.
9019 (mve_vrev32q_m_fv8hf): Likewise.
9020 (mve_vrev32q_m_<supf><mode>): Likewise.
9021 (mve_vrev64q_m_f<mode>): Likewise.
9022 (mve_vrmlaldavhaxq_sv4si): Likewise.
9023 (mve_vrmlaldavhxq_p_sv4si): Likewise.
9024 (mve_vrmlsldavhaxq_sv4si): Likewise.
9025 (mve_vrmlsldavhq_p_sv4si): Likewise.
9026 (mve_vrmlsldavhxq_p_sv4si): Likewise.
9027 (mve_vrndaq_m_f<mode>): Likewise.
9028 (mve_vrndmq_m_f<mode>): Likewise.
9029 (mve_vrndnq_m_f<mode>): Likewise.
9030 (mve_vrndpq_m_f<mode>): Likewise.
9031 (mve_vrndxq_m_f<mode>): Likewise.
9032 (mve_vrshrnbq_n_<supf><mode>): Likewise.
9033 (mve_vrshrntq_n_<supf><mode>): Likewise.
9034 (mve_vshrnbq_n_<supf><mode>): Likewise.
9035 (mve_vshrntq_n_<supf><mode>): Likewise.
9036 (mve_vcvtmq_m_<supf><mode>): Likewise.
9037 (mve_vcvtpq_m_<supf><mode>): Likewise.
9038 (mve_vcvtnq_m_<supf><mode>): Likewise.
9039 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
9040 (mve_vrev16q_m_<supf>v16qi): Likewise.
9041 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
9042 (mve_vrmlaldavhq_p_<supf>v4si): Likewise.
9043 (mve_vrmlsldavhaq_sv4si): Likewise.
9045 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
9046 Mihail Ionescu <mihail.ionescu@arm.com>
9047 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9049 * config/arm/arm_mve.h (vpselq_u8): Define macro.
9050 (vpselq_s8): Likewise.
9051 (vrev64q_m_u8): Likewise.
9052 (vqrdmlashq_n_u8): Likewise.
9053 (vqrdmlahq_n_u8): Likewise.
9054 (vqdmlahq_n_u8): Likewise.
9055 (vmvnq_m_u8): Likewise.
9056 (vmlasq_n_u8): Likewise.
9057 (vmlaq_n_u8): Likewise.
9058 (vmladavq_p_u8): Likewise.
9059 (vmladavaq_u8): Likewise.
9060 (vminvq_p_u8): Likewise.
9061 (vmaxvq_p_u8): Likewise.
9062 (vdupq_m_n_u8): Likewise.
9063 (vcmpneq_m_u8): Likewise.
9064 (vcmpneq_m_n_u8): Likewise.
9065 (vcmphiq_m_u8): Likewise.
9066 (vcmphiq_m_n_u8): Likewise.
9067 (vcmpeqq_m_u8): Likewise.
9068 (vcmpeqq_m_n_u8): Likewise.
9069 (vcmpcsq_m_u8): Likewise.
9070 (vcmpcsq_m_n_u8): Likewise.
9071 (vclzq_m_u8): Likewise.
9072 (vaddvaq_p_u8): Likewise.
9073 (vsriq_n_u8): Likewise.
9074 (vsliq_n_u8): Likewise.
9075 (vshlq_m_r_u8): Likewise.
9076 (vrshlq_m_n_u8): Likewise.
9077 (vqshlq_m_r_u8): Likewise.
9078 (vqrshlq_m_n_u8): Likewise.
9079 (vminavq_p_s8): Likewise.
9080 (vminaq_m_s8): Likewise.
9081 (vmaxavq_p_s8): Likewise.
9082 (vmaxaq_m_s8): Likewise.
9083 (vcmpneq_m_s8): Likewise.
9084 (vcmpneq_m_n_s8): Likewise.
9085 (vcmpltq_m_s8): Likewise.
9086 (vcmpltq_m_n_s8): Likewise.
9087 (vcmpleq_m_s8): Likewise.
9088 (vcmpleq_m_n_s8): Likewise.
9089 (vcmpgtq_m_s8): Likewise.
9090 (vcmpgtq_m_n_s8): Likewise.
9091 (vcmpgeq_m_s8): Likewise.
9092 (vcmpgeq_m_n_s8): Likewise.
9093 (vcmpeqq_m_s8): Likewise.
9094 (vcmpeqq_m_n_s8): Likewise.
9095 (vshlq_m_r_s8): Likewise.
9096 (vrshlq_m_n_s8): Likewise.
9097 (vrev64q_m_s8): Likewise.
9098 (vqshlq_m_r_s8): Likewise.
9099 (vqrshlq_m_n_s8): Likewise.
9100 (vqnegq_m_s8): Likewise.
9101 (vqabsq_m_s8): Likewise.
9102 (vnegq_m_s8): Likewise.
9103 (vmvnq_m_s8): Likewise.
9104 (vmlsdavxq_p_s8): Likewise.
9105 (vmlsdavq_p_s8): Likewise.
9106 (vmladavxq_p_s8): Likewise.
9107 (vmladavq_p_s8): Likewise.
9108 (vminvq_p_s8): Likewise.
9109 (vmaxvq_p_s8): Likewise.
9110 (vdupq_m_n_s8): Likewise.
9111 (vclzq_m_s8): Likewise.
9112 (vclsq_m_s8): Likewise.
9113 (vaddvaq_p_s8): Likewise.
9114 (vabsq_m_s8): Likewise.
9115 (vqrdmlsdhxq_s8): Likewise.
9116 (vqrdmlsdhq_s8): Likewise.
9117 (vqrdmlashq_n_s8): Likewise.
9118 (vqrdmlahq_n_s8): Likewise.
9119 (vqrdmladhxq_s8): Likewise.
9120 (vqrdmladhq_s8): Likewise.
9121 (vqdmlsdhxq_s8): Likewise.
9122 (vqdmlsdhq_s8): Likewise.
9123 (vqdmlahq_n_s8): Likewise.
9124 (vqdmladhxq_s8): Likewise.
9125 (vqdmladhq_s8): Likewise.
9126 (vmlsdavaxq_s8): Likewise.
9127 (vmlsdavaq_s8): Likewise.
9128 (vmlasq_n_s8): Likewise.
9129 (vmlaq_n_s8): Likewise.
9130 (vmladavaxq_s8): Likewise.
9131 (vmladavaq_s8): Likewise.
9132 (vsriq_n_s8): Likewise.
9133 (vsliq_n_s8): Likewise.
9134 (vpselq_u16): Likewise.
9135 (vpselq_s16): Likewise.
9136 (vrev64q_m_u16): Likewise.
9137 (vqrdmlashq_n_u16): Likewise.
9138 (vqrdmlahq_n_u16): Likewise.
9139 (vqdmlahq_n_u16): Likewise.
9140 (vmvnq_m_u16): Likewise.
9141 (vmlasq_n_u16): Likewise.
9142 (vmlaq_n_u16): Likewise.
9143 (vmladavq_p_u16): Likewise.
9144 (vmladavaq_u16): Likewise.
9145 (vminvq_p_u16): Likewise.
9146 (vmaxvq_p_u16): Likewise.
9147 (vdupq_m_n_u16): Likewise.
9148 (vcmpneq_m_u16): Likewise.
9149 (vcmpneq_m_n_u16): Likewise.
9150 (vcmphiq_m_u16): Likewise.
9151 (vcmphiq_m_n_u16): Likewise.
9152 (vcmpeqq_m_u16): Likewise.
9153 (vcmpeqq_m_n_u16): Likewise.
9154 (vcmpcsq_m_u16): Likewise.
9155 (vcmpcsq_m_n_u16): Likewise.
9156 (vclzq_m_u16): Likewise.
9157 (vaddvaq_p_u16): Likewise.
9158 (vsriq_n_u16): Likewise.
9159 (vsliq_n_u16): Likewise.
9160 (vshlq_m_r_u16): Likewise.
9161 (vrshlq_m_n_u16): Likewise.
9162 (vqshlq_m_r_u16): Likewise.
9163 (vqrshlq_m_n_u16): Likewise.
9164 (vminavq_p_s16): Likewise.
9165 (vminaq_m_s16): Likewise.
9166 (vmaxavq_p_s16): Likewise.
9167 (vmaxaq_m_s16): Likewise.
9168 (vcmpneq_m_s16): Likewise.
9169 (vcmpneq_m_n_s16): Likewise.
9170 (vcmpltq_m_s16): Likewise.
9171 (vcmpltq_m_n_s16): Likewise.
9172 (vcmpleq_m_s16): Likewise.
9173 (vcmpleq_m_n_s16): Likewise.
9174 (vcmpgtq_m_s16): Likewise.
9175 (vcmpgtq_m_n_s16): Likewise.
9176 (vcmpgeq_m_s16): Likewise.
9177 (vcmpgeq_m_n_s16): Likewise.
9178 (vcmpeqq_m_s16): Likewise.
9179 (vcmpeqq_m_n_s16): Likewise.
9180 (vshlq_m_r_s16): Likewise.
9181 (vrshlq_m_n_s16): Likewise.
9182 (vrev64q_m_s16): Likewise.
9183 (vqshlq_m_r_s16): Likewise.
9184 (vqrshlq_m_n_s16): Likewise.
9185 (vqnegq_m_s16): Likewise.
9186 (vqabsq_m_s16): Likewise.
9187 (vnegq_m_s16): Likewise.
9188 (vmvnq_m_s16): Likewise.
9189 (vmlsdavxq_p_s16): Likewise.
9190 (vmlsdavq_p_s16): Likewise.
9191 (vmladavxq_p_s16): Likewise.
9192 (vmladavq_p_s16): Likewise.
9193 (vminvq_p_s16): Likewise.
9194 (vmaxvq_p_s16): Likewise.
9195 (vdupq_m_n_s16): Likewise.
9196 (vclzq_m_s16): Likewise.
9197 (vclsq_m_s16): Likewise.
9198 (vaddvaq_p_s16): Likewise.
9199 (vabsq_m_s16): Likewise.
9200 (vqrdmlsdhxq_s16): Likewise.
9201 (vqrdmlsdhq_s16): Likewise.
9202 (vqrdmlashq_n_s16): Likewise.
9203 (vqrdmlahq_n_s16): Likewise.
9204 (vqrdmladhxq_s16): Likewise.
9205 (vqrdmladhq_s16): Likewise.
9206 (vqdmlsdhxq_s16): Likewise.
9207 (vqdmlsdhq_s16): Likewise.
9208 (vqdmlahq_n_s16): Likewise.
9209 (vqdmladhxq_s16): Likewise.
9210 (vqdmladhq_s16): Likewise.
9211 (vmlsdavaxq_s16): Likewise.
9212 (vmlsdavaq_s16): Likewise.
9213 (vmlasq_n_s16): Likewise.
9214 (vmlaq_n_s16): Likewise.
9215 (vmladavaxq_s16): Likewise.
9216 (vmladavaq_s16): Likewise.
9217 (vsriq_n_s16): Likewise.
9218 (vsliq_n_s16): Likewise.
9219 (vpselq_u32): Likewise.
9220 (vpselq_s32): Likewise.
9221 (vrev64q_m_u32): Likewise.
9222 (vqrdmlashq_n_u32): Likewise.
9223 (vqrdmlahq_n_u32): Likewise.
9224 (vqdmlahq_n_u32): Likewise.
9225 (vmvnq_m_u32): Likewise.
9226 (vmlasq_n_u32): Likewise.
9227 (vmlaq_n_u32): Likewise.
9228 (vmladavq_p_u32): Likewise.
9229 (vmladavaq_u32): Likewise.
9230 (vminvq_p_u32): Likewise.
9231 (vmaxvq_p_u32): Likewise.
9232 (vdupq_m_n_u32): Likewise.
9233 (vcmpneq_m_u32): Likewise.
9234 (vcmpneq_m_n_u32): Likewise.
9235 (vcmphiq_m_u32): Likewise.
9236 (vcmphiq_m_n_u32): Likewise.
9237 (vcmpeqq_m_u32): Likewise.
9238 (vcmpeqq_m_n_u32): Likewise.
9239 (vcmpcsq_m_u32): Likewise.
9240 (vcmpcsq_m_n_u32): Likewise.
9241 (vclzq_m_u32): Likewise.
9242 (vaddvaq_p_u32): Likewise.
9243 (vsriq_n_u32): Likewise.
9244 (vsliq_n_u32): Likewise.
9245 (vshlq_m_r_u32): Likewise.
9246 (vrshlq_m_n_u32): Likewise.
9247 (vqshlq_m_r_u32): Likewise.
9248 (vqrshlq_m_n_u32): Likewise.
9249 (vminavq_p_s32): Likewise.
9250 (vminaq_m_s32): Likewise.
9251 (vmaxavq_p_s32): Likewise.
9252 (vmaxaq_m_s32): Likewise.
9253 (vcmpneq_m_s32): Likewise.
9254 (vcmpneq_m_n_s32): Likewise.
9255 (vcmpltq_m_s32): Likewise.
9256 (vcmpltq_m_n_s32): Likewise.
9257 (vcmpleq_m_s32): Likewise.
9258 (vcmpleq_m_n_s32): Likewise.
9259 (vcmpgtq_m_s32): Likewise.
9260 (vcmpgtq_m_n_s32): Likewise.
9261 (vcmpgeq_m_s32): Likewise.
9262 (vcmpgeq_m_n_s32): Likewise.
9263 (vcmpeqq_m_s32): Likewise.
9264 (vcmpeqq_m_n_s32): Likewise.
9265 (vshlq_m_r_s32): Likewise.
9266 (vrshlq_m_n_s32): Likewise.
9267 (vrev64q_m_s32): Likewise.
9268 (vqshlq_m_r_s32): Likewise.
9269 (vqrshlq_m_n_s32): Likewise.
9270 (vqnegq_m_s32): Likewise.
9271 (vqabsq_m_s32): Likewise.
9272 (vnegq_m_s32): Likewise.
9273 (vmvnq_m_s32): Likewise.
9274 (vmlsdavxq_p_s32): Likewise.
9275 (vmlsdavq_p_s32): Likewise.
9276 (vmladavxq_p_s32): Likewise.
9277 (vmladavq_p_s32): Likewise.
9278 (vminvq_p_s32): Likewise.
9279 (vmaxvq_p_s32): Likewise.
9280 (vdupq_m_n_s32): Likewise.
9281 (vclzq_m_s32): Likewise.
9282 (vclsq_m_s32): Likewise.
9283 (vaddvaq_p_s32): Likewise.
9284 (vabsq_m_s32): Likewise.
9285 (vqrdmlsdhxq_s32): Likewise.
9286 (vqrdmlsdhq_s32): Likewise.
9287 (vqrdmlashq_n_s32): Likewise.
9288 (vqrdmlahq_n_s32): Likewise.
9289 (vqrdmladhxq_s32): Likewise.
9290 (vqrdmladhq_s32): Likewise.
9291 (vqdmlsdhxq_s32): Likewise.
9292 (vqdmlsdhq_s32): Likewise.
9293 (vqdmlahq_n_s32): Likewise.
9294 (vqdmladhxq_s32): Likewise.
9295 (vqdmladhq_s32): Likewise.
9296 (vmlsdavaxq_s32): Likewise.
9297 (vmlsdavaq_s32): Likewise.
9298 (vmlasq_n_s32): Likewise.
9299 (vmlaq_n_s32): Likewise.
9300 (vmladavaxq_s32): Likewise.
9301 (vmladavaq_s32): Likewise.
9302 (vsriq_n_s32): Likewise.
9303 (vsliq_n_s32): Likewise.
9304 (vpselq_u64): Likewise.
9305 (vpselq_s64): Likewise.
9306 (__arm_vpselq_u8): Define intrinsic.
9307 (__arm_vpselq_s8): Likewise.
9308 (__arm_vrev64q_m_u8): Likewise.
9309 (__arm_vqrdmlashq_n_u8): Likewise.
9310 (__arm_vqrdmlahq_n_u8): Likewise.
9311 (__arm_vqdmlahq_n_u8): Likewise.
9312 (__arm_vmvnq_m_u8): Likewise.
9313 (__arm_vmlasq_n_u8): Likewise.
9314 (__arm_vmlaq_n_u8): Likewise.
9315 (__arm_vmladavq_p_u8): Likewise.
9316 (__arm_vmladavaq_u8): Likewise.
9317 (__arm_vminvq_p_u8): Likewise.
9318 (__arm_vmaxvq_p_u8): Likewise.
9319 (__arm_vdupq_m_n_u8): Likewise.
9320 (__arm_vcmpneq_m_u8): Likewise.
9321 (__arm_vcmpneq_m_n_u8): Likewise.
9322 (__arm_vcmphiq_m_u8): Likewise.
9323 (__arm_vcmphiq_m_n_u8): Likewise.
9324 (__arm_vcmpeqq_m_u8): Likewise.
9325 (__arm_vcmpeqq_m_n_u8): Likewise.
9326 (__arm_vcmpcsq_m_u8): Likewise.
9327 (__arm_vcmpcsq_m_n_u8): Likewise.
9328 (__arm_vclzq_m_u8): Likewise.
9329 (__arm_vaddvaq_p_u8): Likewise.
9330 (__arm_vsriq_n_u8): Likewise.
9331 (__arm_vsliq_n_u8): Likewise.
9332 (__arm_vshlq_m_r_u8): Likewise.
9333 (__arm_vrshlq_m_n_u8): Likewise.
9334 (__arm_vqshlq_m_r_u8): Likewise.
9335 (__arm_vqrshlq_m_n_u8): Likewise.
9336 (__arm_vminavq_p_s8): Likewise.
9337 (__arm_vminaq_m_s8): Likewise.
9338 (__arm_vmaxavq_p_s8): Likewise.
9339 (__arm_vmaxaq_m_s8): Likewise.
9340 (__arm_vcmpneq_m_s8): Likewise.
9341 (__arm_vcmpneq_m_n_s8): Likewise.
9342 (__arm_vcmpltq_m_s8): Likewise.
9343 (__arm_vcmpltq_m_n_s8): Likewise.
9344 (__arm_vcmpleq_m_s8): Likewise.
9345 (__arm_vcmpleq_m_n_s8): Likewise.
9346 (__arm_vcmpgtq_m_s8): Likewise.
9347 (__arm_vcmpgtq_m_n_s8): Likewise.
9348 (__arm_vcmpgeq_m_s8): Likewise.
9349 (__arm_vcmpgeq_m_n_s8): Likewise.
9350 (__arm_vcmpeqq_m_s8): Likewise.
9351 (__arm_vcmpeqq_m_n_s8): Likewise.
9352 (__arm_vshlq_m_r_s8): Likewise.
9353 (__arm_vrshlq_m_n_s8): Likewise.
9354 (__arm_vrev64q_m_s8): Likewise.
9355 (__arm_vqshlq_m_r_s8): Likewise.
9356 (__arm_vqrshlq_m_n_s8): Likewise.
9357 (__arm_vqnegq_m_s8): Likewise.
9358 (__arm_vqabsq_m_s8): Likewise.
9359 (__arm_vnegq_m_s8): Likewise.
9360 (__arm_vmvnq_m_s8): Likewise.
9361 (__arm_vmlsdavxq_p_s8): Likewise.
9362 (__arm_vmlsdavq_p_s8): Likewise.
9363 (__arm_vmladavxq_p_s8): Likewise.
9364 (__arm_vmladavq_p_s8): Likewise.
9365 (__arm_vminvq_p_s8): Likewise.
9366 (__arm_vmaxvq_p_s8): Likewise.
9367 (__arm_vdupq_m_n_s8): Likewise.
9368 (__arm_vclzq_m_s8): Likewise.
9369 (__arm_vclsq_m_s8): Likewise.
9370 (__arm_vaddvaq_p_s8): Likewise.
9371 (__arm_vabsq_m_s8): Likewise.
9372 (__arm_vqrdmlsdhxq_s8): Likewise.
9373 (__arm_vqrdmlsdhq_s8): Likewise.
9374 (__arm_vqrdmlashq_n_s8): Likewise.
9375 (__arm_vqrdmlahq_n_s8): Likewise.
9376 (__arm_vqrdmladhxq_s8): Likewise.
9377 (__arm_vqrdmladhq_s8): Likewise.
9378 (__arm_vqdmlsdhxq_s8): Likewise.
9379 (__arm_vqdmlsdhq_s8): Likewise.
9380 (__arm_vqdmlahq_n_s8): Likewise.
9381 (__arm_vqdmladhxq_s8): Likewise.
9382 (__arm_vqdmladhq_s8): Likewise.
9383 (__arm_vmlsdavaxq_s8): Likewise.
9384 (__arm_vmlsdavaq_s8): Likewise.
9385 (__arm_vmlasq_n_s8): Likewise.
9386 (__arm_vmlaq_n_s8): Likewise.
9387 (__arm_vmladavaxq_s8): Likewise.
9388 (__arm_vmladavaq_s8): Likewise.
9389 (__arm_vsriq_n_s8): Likewise.
9390 (__arm_vsliq_n_s8): Likewise.
9391 (__arm_vpselq_u16): Likewise.
9392 (__arm_vpselq_s16): Likewise.
9393 (__arm_vrev64q_m_u16): Likewise.
9394 (__arm_vqrdmlashq_n_u16): Likewise.
9395 (__arm_vqrdmlahq_n_u16): Likewise.
9396 (__arm_vqdmlahq_n_u16): Likewise.
9397 (__arm_vmvnq_m_u16): Likewise.
9398 (__arm_vmlasq_n_u16): Likewise.
9399 (__arm_vmlaq_n_u16): Likewise.
9400 (__arm_vmladavq_p_u16): Likewise.
9401 (__arm_vmladavaq_u16): Likewise.
9402 (__arm_vminvq_p_u16): Likewise.
9403 (__arm_vmaxvq_p_u16): Likewise.
9404 (__arm_vdupq_m_n_u16): Likewise.
9405 (__arm_vcmpneq_m_u16): Likewise.
9406 (__arm_vcmpneq_m_n_u16): Likewise.
9407 (__arm_vcmphiq_m_u16): Likewise.
9408 (__arm_vcmphiq_m_n_u16): Likewise.
9409 (__arm_vcmpeqq_m_u16): Likewise.
9410 (__arm_vcmpeqq_m_n_u16): Likewise.
9411 (__arm_vcmpcsq_m_u16): Likewise.
9412 (__arm_vcmpcsq_m_n_u16): Likewise.
9413 (__arm_vclzq_m_u16): Likewise.
9414 (__arm_vaddvaq_p_u16): Likewise.
9415 (__arm_vsriq_n_u16): Likewise.
9416 (__arm_vsliq_n_u16): Likewise.
9417 (__arm_vshlq_m_r_u16): Likewise.
9418 (__arm_vrshlq_m_n_u16): Likewise.
9419 (__arm_vqshlq_m_r_u16): Likewise.
9420 (__arm_vqrshlq_m_n_u16): Likewise.
9421 (__arm_vminavq_p_s16): Likewise.
9422 (__arm_vminaq_m_s16): Likewise.
9423 (__arm_vmaxavq_p_s16): Likewise.
9424 (__arm_vmaxaq_m_s16): Likewise.
9425 (__arm_vcmpneq_m_s16): Likewise.
9426 (__arm_vcmpneq_m_n_s16): Likewise.
9427 (__arm_vcmpltq_m_s16): Likewise.
9428 (__arm_vcmpltq_m_n_s16): Likewise.
9429 (__arm_vcmpleq_m_s16): Likewise.
9430 (__arm_vcmpleq_m_n_s16): Likewise.
9431 (__arm_vcmpgtq_m_s16): Likewise.
9432 (__arm_vcmpgtq_m_n_s16): Likewise.
9433 (__arm_vcmpgeq_m_s16): Likewise.
9434 (__arm_vcmpgeq_m_n_s16): Likewise.
9435 (__arm_vcmpeqq_m_s16): Likewise.
9436 (__arm_vcmpeqq_m_n_s16): Likewise.
9437 (__arm_vshlq_m_r_s16): Likewise.
9438 (__arm_vrshlq_m_n_s16): Likewise.
9439 (__arm_vrev64q_m_s16): Likewise.
9440 (__arm_vqshlq_m_r_s16): Likewise.
9441 (__arm_vqrshlq_m_n_s16): Likewise.
9442 (__arm_vqnegq_m_s16): Likewise.
9443 (__arm_vqabsq_m_s16): Likewise.
9444 (__arm_vnegq_m_s16): Likewise.
9445 (__arm_vmvnq_m_s16): Likewise.
9446 (__arm_vmlsdavxq_p_s16): Likewise.
9447 (__arm_vmlsdavq_p_s16): Likewise.
9448 (__arm_vmladavxq_p_s16): Likewise.
9449 (__arm_vmladavq_p_s16): Likewise.
9450 (__arm_vminvq_p_s16): Likewise.
9451 (__arm_vmaxvq_p_s16): Likewise.
9452 (__arm_vdupq_m_n_s16): Likewise.
9453 (__arm_vclzq_m_s16): Likewise.
9454 (__arm_vclsq_m_s16): Likewise.
9455 (__arm_vaddvaq_p_s16): Likewise.
9456 (__arm_vabsq_m_s16): Likewise.
9457 (__arm_vqrdmlsdhxq_s16): Likewise.
9458 (__arm_vqrdmlsdhq_s16): Likewise.
9459 (__arm_vqrdmlashq_n_s16): Likewise.
9460 (__arm_vqrdmlahq_n_s16): Likewise.
9461 (__arm_vqrdmladhxq_s16): Likewise.
9462 (__arm_vqrdmladhq_s16): Likewise.
9463 (__arm_vqdmlsdhxq_s16): Likewise.
9464 (__arm_vqdmlsdhq_s16): Likewise.
9465 (__arm_vqdmlahq_n_s16): Likewise.
9466 (__arm_vqdmladhxq_s16): Likewise.
9467 (__arm_vqdmladhq_s16): Likewise.
9468 (__arm_vmlsdavaxq_s16): Likewise.
9469 (__arm_vmlsdavaq_s16): Likewise.
9470 (__arm_vmlasq_n_s16): Likewise.
9471 (__arm_vmlaq_n_s16): Likewise.
9472 (__arm_vmladavaxq_s16): Likewise.
9473 (__arm_vmladavaq_s16): Likewise.
9474 (__arm_vsriq_n_s16): Likewise.
9475 (__arm_vsliq_n_s16): Likewise.
9476 (__arm_vpselq_u32): Likewise.
9477 (__arm_vpselq_s32): Likewise.
9478 (__arm_vrev64q_m_u32): Likewise.
9479 (__arm_vqrdmlashq_n_u32): Likewise.
9480 (__arm_vqrdmlahq_n_u32): Likewise.
9481 (__arm_vqdmlahq_n_u32): Likewise.
9482 (__arm_vmvnq_m_u32): Likewise.
9483 (__arm_vmlasq_n_u32): Likewise.
9484 (__arm_vmlaq_n_u32): Likewise.
9485 (__arm_vmladavq_p_u32): Likewise.
9486 (__arm_vmladavaq_u32): Likewise.
9487 (__arm_vminvq_p_u32): Likewise.
9488 (__arm_vmaxvq_p_u32): Likewise.
9489 (__arm_vdupq_m_n_u32): Likewise.
9490 (__arm_vcmpneq_m_u32): Likewise.
9491 (__arm_vcmpneq_m_n_u32): Likewise.
9492 (__arm_vcmphiq_m_u32): Likewise.
9493 (__arm_vcmphiq_m_n_u32): Likewise.
9494 (__arm_vcmpeqq_m_u32): Likewise.
9495 (__arm_vcmpeqq_m_n_u32): Likewise.
9496 (__arm_vcmpcsq_m_u32): Likewise.
9497 (__arm_vcmpcsq_m_n_u32): Likewise.
9498 (__arm_vclzq_m_u32): Likewise.
9499 (__arm_vaddvaq_p_u32): Likewise.
9500 (__arm_vsriq_n_u32): Likewise.
9501 (__arm_vsliq_n_u32): Likewise.
9502 (__arm_vshlq_m_r_u32): Likewise.
9503 (__arm_vrshlq_m_n_u32): Likewise.
9504 (__arm_vqshlq_m_r_u32): Likewise.
9505 (__arm_vqrshlq_m_n_u32): Likewise.
9506 (__arm_vminavq_p_s32): Likewise.
9507 (__arm_vminaq_m_s32): Likewise.
9508 (__arm_vmaxavq_p_s32): Likewise.
9509 (__arm_vmaxaq_m_s32): Likewise.
9510 (__arm_vcmpneq_m_s32): Likewise.
9511 (__arm_vcmpneq_m_n_s32): Likewise.
9512 (__arm_vcmpltq_m_s32): Likewise.
9513 (__arm_vcmpltq_m_n_s32): Likewise.
9514 (__arm_vcmpleq_m_s32): Likewise.
9515 (__arm_vcmpleq_m_n_s32): Likewise.
9516 (__arm_vcmpgtq_m_s32): Likewise.
9517 (__arm_vcmpgtq_m_n_s32): Likewise.
9518 (__arm_vcmpgeq_m_s32): Likewise.
9519 (__arm_vcmpgeq_m_n_s32): Likewise.
9520 (__arm_vcmpeqq_m_s32): Likewise.
9521 (__arm_vcmpeqq_m_n_s32): Likewise.
9522 (__arm_vshlq_m_r_s32): Likewise.
9523 (__arm_vrshlq_m_n_s32): Likewise.
9524 (__arm_vrev64q_m_s32): Likewise.
9525 (__arm_vqshlq_m_r_s32): Likewise.
9526 (__arm_vqrshlq_m_n_s32): Likewise.
9527 (__arm_vqnegq_m_s32): Likewise.
9528 (__arm_vqabsq_m_s32): Likewise.
9529 (__arm_vnegq_m_s32): Likewise.
9530 (__arm_vmvnq_m_s32): Likewise.
9531 (__arm_vmlsdavxq_p_s32): Likewise.
9532 (__arm_vmlsdavq_p_s32): Likewise.
9533 (__arm_vmladavxq_p_s32): Likewise.
9534 (__arm_vmladavq_p_s32): Likewise.
9535 (__arm_vminvq_p_s32): Likewise.
9536 (__arm_vmaxvq_p_s32): Likewise.
9537 (__arm_vdupq_m_n_s32): Likewise.
9538 (__arm_vclzq_m_s32): Likewise.
9539 (__arm_vclsq_m_s32): Likewise.
9540 (__arm_vaddvaq_p_s32): Likewise.
9541 (__arm_vabsq_m_s32): Likewise.
9542 (__arm_vqrdmlsdhxq_s32): Likewise.
9543 (__arm_vqrdmlsdhq_s32): Likewise.
9544 (__arm_vqrdmlashq_n_s32): Likewise.
9545 (__arm_vqrdmlahq_n_s32): Likewise.
9546 (__arm_vqrdmladhxq_s32): Likewise.
9547 (__arm_vqrdmladhq_s32): Likewise.
9548 (__arm_vqdmlsdhxq_s32): Likewise.
9549 (__arm_vqdmlsdhq_s32): Likewise.
9550 (__arm_vqdmlahq_n_s32): Likewise.
9551 (__arm_vqdmladhxq_s32): Likewise.
9552 (__arm_vqdmladhq_s32): Likewise.
9553 (__arm_vmlsdavaxq_s32): Likewise.
9554 (__arm_vmlsdavaq_s32): Likewise.
9555 (__arm_vmlasq_n_s32): Likewise.
9556 (__arm_vmlaq_n_s32): Likewise.
9557 (__arm_vmladavaxq_s32): Likewise.
9558 (__arm_vmladavaq_s32): Likewise.
9559 (__arm_vsriq_n_s32): Likewise.
9560 (__arm_vsliq_n_s32): Likewise.
9561 (__arm_vpselq_u64): Likewise.
9562 (__arm_vpselq_s64): Likewise.
9563 (vcmpneq_m_n): Define polymorphic variant.
9564 (vcmpneq_m): Likewise.
9565 (vqrdmlsdhq): Likewise.
9566 (vqrdmlsdhxq): Likewise.
9567 (vqrshlq_m_n): Likewise.
9568 (vqshlq_m_r): Likewise.
9569 (vrev64q_m): Likewise.
9570 (vrshlq_m_n): Likewise.
9571 (vshlq_m_r): Likewise.
9572 (vsliq_n): Likewise.
9573 (vsriq_n): Likewise.
9574 (vqrdmlashq_n): Likewise.
9575 (vqrdmlahq): Likewise.
9576 (vqrdmladhxq): Likewise.
9577 (vqrdmladhq): Likewise.
9578 (vqnegq_m): Likewise.
9579 (vqdmlsdhxq): Likewise.
9580 (vabsq_m): Likewise.
9581 (vclsq_m): Likewise.
9582 (vclzq_m): Likewise.
9583 (vcmpgeq_m): Likewise.
9584 (vcmpgeq_m_n): Likewise.
9585 (vdupq_m_n): Likewise.
9586 (vmaxaq_m): Likewise.
9587 (vmlaq_n): Likewise.
9588 (vmlasq_n): Likewise.
9589 (vmvnq_m): Likewise.
9590 (vnegq_m): Likewise.
9592 (vqdmlahq_n): Likewise.
9593 (vqrdmlahq_n): Likewise.
9594 (vqdmlsdhq): Likewise.
9595 (vqdmladhq): Likewise.
9596 (vqabsq_m): Likewise.
9597 (vminaq_m): Likewise.
9598 (vrmlaldavhaq): Likewise.
9599 (vmlsdavxq_p): Likewise.
9600 (vmlsdavq_p): Likewise.
9601 (vmlsdavaxq): Likewise.
9602 (vmlsdavaq): Likewise.
9603 (vaddvaq_p): Likewise.
9604 (vcmpcsq_m_n): Likewise.
9605 (vcmpcsq_m): Likewise.
9606 (vcmpeqq_m_n): Likewise.
9607 (vcmpeqq_m): Likewise.
9608 (vmladavxq_p): Likewise.
9609 (vmladavq_p): Likewise.
9610 (vmladavaxq): Likewise.
9611 (vmladavaq): Likewise.
9612 (vminvq_p): Likewise.
9613 (vminavq_p): Likewise.
9614 (vmaxvq_p): Likewise.
9615 (vmaxavq_p): Likewise.
9616 (vcmpltq_m_n): Likewise.
9617 (vcmpltq_m): Likewise.
9618 (vcmpleq_m): Likewise.
9619 (vcmpleq_m_n): Likewise.
9620 (vcmphiq_m_n): Likewise.
9621 (vcmphiq_m): Likewise.
9622 (vcmpgtq_m_n): Likewise.
9623 (vcmpgtq_m): Likewise.
9624 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
9626 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
9627 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
9628 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
9629 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
9630 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
9631 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
9632 * config/arm/constraints.md (Rc): Define constraint to check constant is
9633 in the range of 0 to 15.
9634 (Re): Define constraint to check constant is in the range of 0 to 31.
9635 * config/arm/mve.md (VADDVAQ_P): Define iterator.
9636 (VCLZQ_M): Likewise.
9637 (VCMPEQQ_M_N): Likewise.
9638 (VCMPEQQ_M): Likewise.
9639 (VCMPNEQ_M_N): Likewise.
9640 (VCMPNEQ_M): Likewise.
9641 (VDUPQ_M_N): Likewise.
9642 (VMAXVQ_P): Likewise.
9643 (VMINVQ_P): Likewise.
9644 (VMLADAVAQ): Likewise.
9645 (VMLADAVQ_P): Likewise.
9646 (VMLAQ_N): Likewise.
9647 (VMLASQ_N): Likewise.
9648 (VMVNQ_M): Likewise.
9650 (VQDMLAHQ_N): Likewise.
9651 (VQRDMLAHQ_N): Likewise.
9652 (VQRDMLASHQ_N): Likewise.
9653 (VQRSHLQ_M_N): Likewise.
9654 (VQSHLQ_M_R): Likewise.
9655 (VREV64Q_M): Likewise.
9656 (VRSHLQ_M_N): Likewise.
9657 (VSHLQ_M_R): Likewise.
9658 (VSLIQ_N): Likewise.
9659 (VSRIQ_N): Likewise.
9660 (mve_vabsq_m_s<mode>): Define RTL pattern.
9661 (mve_vaddvaq_p_<supf><mode>): Likewise.
9662 (mve_vclsq_m_s<mode>): Likewise.
9663 (mve_vclzq_m_<supf><mode>): Likewise.
9664 (mve_vcmpcsq_m_n_u<mode>): Likewise.
9665 (mve_vcmpcsq_m_u<mode>): Likewise.
9666 (mve_vcmpeqq_m_n_<supf><mode>): Likewise.
9667 (mve_vcmpeqq_m_<supf><mode>): Likewise.
9668 (mve_vcmpgeq_m_n_s<mode>): Likewise.
9669 (mve_vcmpgeq_m_s<mode>): Likewise.
9670 (mve_vcmpgtq_m_n_s<mode>): Likewise.
9671 (mve_vcmpgtq_m_s<mode>): Likewise.
9672 (mve_vcmphiq_m_n_u<mode>): Likewise.
9673 (mve_vcmphiq_m_u<mode>): Likewise.
9674 (mve_vcmpleq_m_n_s<mode>): Likewise.
9675 (mve_vcmpleq_m_s<mode>): Likewise.
9676 (mve_vcmpltq_m_n_s<mode>): Likewise.
9677 (mve_vcmpltq_m_s<mode>): Likewise.
9678 (mve_vcmpneq_m_n_<supf><mode>): Likewise.
9679 (mve_vcmpneq_m_<supf><mode>): Likewise.
9680 (mve_vdupq_m_n_<supf><mode>): Likewise.
9681 (mve_vmaxaq_m_s<mode>): Likewise.
9682 (mve_vmaxavq_p_s<mode>): Likewise.
9683 (mve_vmaxvq_p_<supf><mode>): Likewise.
9684 (mve_vminaq_m_s<mode>): Likewise.
9685 (mve_vminavq_p_s<mode>): Likewise.
9686 (mve_vminvq_p_<supf><mode>): Likewise.
9687 (mve_vmladavaq_<supf><mode>): Likewise.
9688 (mve_vmladavq_p_<supf><mode>): Likewise.
9689 (mve_vmladavxq_p_s<mode>): Likewise.
9690 (mve_vmlaq_n_<supf><mode>): Likewise.
9691 (mve_vmlasq_n_<supf><mode>): Likewise.
9692 (mve_vmlsdavq_p_s<mode>): Likewise.
9693 (mve_vmlsdavxq_p_s<mode>): Likewise.
9694 (mve_vmvnq_m_<supf><mode>): Likewise.
9695 (mve_vnegq_m_s<mode>): Likewise.
9696 (mve_vpselq_<supf><mode>): Likewise.
9697 (mve_vqabsq_m_s<mode>): Likewise.
9698 (mve_vqdmlahq_n_<supf><mode>): Likewise.
9699 (mve_vqnegq_m_s<mode>): Likewise.
9700 (mve_vqrdmladhq_s<mode>): Likewise.
9701 (mve_vqrdmladhxq_s<mode>): Likewise.
9702 (mve_vqrdmlahq_n_<supf><mode>): Likewise.
9703 (mve_vqrdmlashq_n_<supf><mode>): Likewise.
9704 (mve_vqrdmlsdhq_s<mode>): Likewise.
9705 (mve_vqrdmlsdhxq_s<mode>): Likewise.
9706 (mve_vqrshlq_m_n_<supf><mode>): Likewise.
9707 (mve_vqshlq_m_r_<supf><mode>): Likewise.
9708 (mve_vrev64q_m_<supf><mode>): Likewise.
9709 (mve_vrshlq_m_n_<supf><mode>): Likewise.
9710 (mve_vshlq_m_r_<supf><mode>): Likewise.
9711 (mve_vsliq_n_<supf><mode>): Likewise.
9712 (mve_vsriq_n_<supf><mode>): Likewise.
9713 (mve_vqdmlsdhxq_s<mode>): Likewise.
9714 (mve_vqdmlsdhq_s<mode>): Likewise.
9715 (mve_vqdmladhxq_s<mode>): Likewise.
9716 (mve_vqdmladhq_s<mode>): Likewise.
9717 (mve_vmlsdavaxq_s<mode>): Likewise.
9718 (mve_vmlsdavaq_s<mode>): Likewise.
9719 (mve_vmladavaxq_s<mode>): Likewise.
9720 * config/arm/predicates.md (mve_imm_15):Define predicate to check the
9721 matching constraint Rc.
9722 (mve_imm_31): Define predicate to check the matching constraint Re.
9724 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
9726 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
9727 (vec_cmp<mode>di_dup): Likewise.
9728 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
9730 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
9732 * config/gcn/gcn-valu.md (COND_MODE): Delete.
9733 (COND_INT_MODE): Delete.
9734 (cond_op): Add "mult".
9735 (cond_<expander><mode>): Use VEC_ALLREG_MODE.
9736 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
9738 2020-03-18 Richard Biener <rguenther@suse.de>
9741 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using
9742 partial int modes or not mode-precision integer types for
9745 2020-03-18 Jakub Jelinek <jakub@redhat.com>
9747 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
9749 * config/arc/arc.c (frame_stack_add): Likewise.
9750 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
9752 * ipa-predicate.c (predicate::remap_after_inlining): Likewise.
9753 * tree-ssa-strlen.h (handle_printf_call): Likewise.
9754 * tree-ssa-strlen.c (is_strlen_related_p): Likewise.
9755 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
9757 2020-03-18 Duan bo <duanbo3@huawei.com>
9760 * config/aarch64/aarch64.md (ldr_got_tiny): Delete.
9761 (@ldr_got_tiny_<mode>): New pattern.
9762 (ldr_got_tiny_sidi): Likewise.
9763 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
9764 them to handle SYMBOL_TINY_GOT for ILP32.
9766 2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
9768 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
9769 call-preserved for SVE PCS functions.
9770 (aarch64_layout_frame): Cope with up to 12 predicate save slots.
9771 Optimize the case in which there are no following vector save slots.
9773 2020-03-18 Richard Biener <rguenther@suse.de>
9776 * fold-const.c (build_fold_addr_expr): Convert address to
9778 * asan.c (maybe_create_ssa_name): Strip useless type conversions.
9779 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
9780 to build the ADDR_EXPR which we don't really want to simplify.
9781 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
9782 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
9783 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
9784 (simplify_builtin_call): Strip useless type conversions.
9785 * tree-ssa-strlen.c (new_strinfo): Likewise.
9787 2020-03-17 Alexey Neyman <stilor@att.net>
9790 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
9791 the debug level is terse and the declaration is public. Do not
9793 (dwarf2out_decl): Same.
9794 (add_type_attribute): Return immediately if debug level is
9797 2020-03-17 Richard Sandiford <richard.sandiford@arm.com>
9799 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.
9801 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9802 Mihail Ionescu <mihail.ionescu@arm.com>
9803 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9805 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
9806 Define qualifier for ternary operands.
9807 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9808 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9809 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9810 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9811 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
9812 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
9813 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9814 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
9815 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9816 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
9817 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9818 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9819 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
9820 * config/arm/arm_mve.h (vabavq_s8): Define macro.
9821 (vabavq_s16): Likewise.
9822 (vabavq_s32): Likewise.
9823 (vbicq_m_n_s16): Likewise.
9824 (vbicq_m_n_s32): Likewise.
9825 (vbicq_m_n_u16): Likewise.
9826 (vbicq_m_n_u32): Likewise.
9827 (vcmpeqq_m_f16): Likewise.
9828 (vcmpeqq_m_f32): Likewise.
9829 (vcvtaq_m_s16_f16): Likewise.
9830 (vcvtaq_m_u16_f16): Likewise.
9831 (vcvtaq_m_s32_f32): Likewise.
9832 (vcvtaq_m_u32_f32): Likewise.
9833 (vcvtq_m_f16_s16): Likewise.
9834 (vcvtq_m_f16_u16): Likewise.
9835 (vcvtq_m_f32_s32): Likewise.
9836 (vcvtq_m_f32_u32): Likewise.
9837 (vqrshrnbq_n_s16): Likewise.
9838 (vqrshrnbq_n_u16): Likewise.
9839 (vqrshrnbq_n_s32): Likewise.
9840 (vqrshrnbq_n_u32): Likewise.
9841 (vqrshrunbq_n_s16): Likewise.
9842 (vqrshrunbq_n_s32): Likewise.
9843 (vrmlaldavhaq_s32): Likewise.
9844 (vrmlaldavhaq_u32): Likewise.
9845 (vshlcq_s8): Likewise.
9846 (vshlcq_u8): Likewise.
9847 (vshlcq_s16): Likewise.
9848 (vshlcq_u16): Likewise.
9849 (vshlcq_s32): Likewise.
9850 (vshlcq_u32): Likewise.
9851 (vabavq_u8): Likewise.
9852 (vabavq_u16): Likewise.
9853 (vabavq_u32): Likewise.
9854 (__arm_vabavq_s8): Define intrinsic.
9855 (__arm_vabavq_s16): Likewise.
9856 (__arm_vabavq_s32): Likewise.
9857 (__arm_vabavq_u8): Likewise.
9858 (__arm_vabavq_u16): Likewise.
9859 (__arm_vabavq_u32): Likewise.
9860 (__arm_vbicq_m_n_s16): Likewise.
9861 (__arm_vbicq_m_n_s32): Likewise.
9862 (__arm_vbicq_m_n_u16): Likewise.
9863 (__arm_vbicq_m_n_u32): Likewise.
9864 (__arm_vqrshrnbq_n_s16): Likewise.
9865 (__arm_vqrshrnbq_n_u16): Likewise.
9866 (__arm_vqrshrnbq_n_s32): Likewise.
9867 (__arm_vqrshrnbq_n_u32): Likewise.
9868 (__arm_vqrshrunbq_n_s16): Likewise.
9869 (__arm_vqrshrunbq_n_s32): Likewise.
9870 (__arm_vrmlaldavhaq_s32): Likewise.
9871 (__arm_vrmlaldavhaq_u32): Likewise.
9872 (__arm_vshlcq_s8): Likewise.
9873 (__arm_vshlcq_u8): Likewise.
9874 (__arm_vshlcq_s16): Likewise.
9875 (__arm_vshlcq_u16): Likewise.
9876 (__arm_vshlcq_s32): Likewise.
9877 (__arm_vshlcq_u32): Likewise.
9878 (__arm_vcmpeqq_m_f16): Likewise.
9879 (__arm_vcmpeqq_m_f32): Likewise.
9880 (__arm_vcvtaq_m_s16_f16): Likewise.
9881 (__arm_vcvtaq_m_u16_f16): Likewise.
9882 (__arm_vcvtaq_m_s32_f32): Likewise.
9883 (__arm_vcvtaq_m_u32_f32): Likewise.
9884 (__arm_vcvtq_m_f16_s16): Likewise.
9885 (__arm_vcvtq_m_f16_u16): Likewise.
9886 (__arm_vcvtq_m_f32_s32): Likewise.
9887 (__arm_vcvtq_m_f32_u32): Likewise.
9888 (vcvtaq_m): Define polymorphic variant.
9889 (vcvtq_m): Likewise.
9892 (vbicq_m_n): Likewise.
9893 (vqrshrnbq_n): Likewise.
9894 (vqrshrunbq_n): Likewise.
9895 * config/arm/arm_mve_builtins.def
9896 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
9897 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
9898 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9899 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
9900 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
9901 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
9902 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
9903 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9904 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
9905 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
9906 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
9907 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
9908 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
9909 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
9910 * config/arm/mve.md (VBICQ_M_N): Define iterator.
9911 (VCVTAQ_M): Likewise.
9912 (VCVTQ_M_TO_F): Likewise.
9913 (VQRSHRNBQ_N): Likewise.
9916 (VRMLALDAVHAQ): Likewise.
9917 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
9918 (mve_vcmpeqq_m_f<mode>): Likewise.
9919 (mve_vcvtaq_m_<supf><mode>): Likewise.
9920 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
9921 (mve_vqrshrnbq_n_<supf><mode>): Likewise.
9922 (mve_vqrshrunbq_n_s<mode>): Likewise.
9923 (mve_vrmlaldavhaq_<supf>v4si): Likewise.
9924 (mve_vabavq_<supf><mode>): Likewise.
9925 (mve_vshlcq_<supf><mode>): Likewise.
9926 (mve_vshlcq_<supf><mode>): Likewise.
9927 (mve_vshlcq_vec_<supf><mode>): Define RTL expand.
9928 (mve_vshlcq_carry_<supf><mode>): Likewise.
9930 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
9931 Mihail Ionescu <mihail.ionescu@arm.com>
9932 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9934 * config/arm/arm_mve.h (vqmovntq_u16): Define macro.
9935 (vqmovnbq_u16): Likewise.
9936 (vmulltq_poly_p8): Likewise.
9937 (vmullbq_poly_p8): Likewise.
9938 (vmovntq_u16): Likewise.
9939 (vmovnbq_u16): Likewise.
9940 (vmlaldavxq_u16): Likewise.
9941 (vmlaldavq_u16): Likewise.
9942 (vqmovuntq_s16): Likewise.
9943 (vqmovunbq_s16): Likewise.
9944 (vshlltq_n_u8): Likewise.
9945 (vshllbq_n_u8): Likewise.
9946 (vorrq_n_u16): Likewise.
9947 (vbicq_n_u16): Likewise.
9948 (vcmpneq_n_f16): Likewise.
9949 (vcmpneq_f16): Likewise.
9950 (vcmpltq_n_f16): Likewise.
9951 (vcmpltq_f16): Likewise.
9952 (vcmpleq_n_f16): Likewise.
9953 (vcmpleq_f16): Likewise.
9954 (vcmpgtq_n_f16): Likewise.
9955 (vcmpgtq_f16): Likewise.
9956 (vcmpgeq_n_f16): Likewise.
9957 (vcmpgeq_f16): Likewise.
9958 (vcmpeqq_n_f16): Likewise.
9959 (vcmpeqq_f16): Likewise.
9960 (vsubq_f16): Likewise.
9961 (vqmovntq_s16): Likewise.
9962 (vqmovnbq_s16): Likewise.
9963 (vqdmulltq_s16): Likewise.
9964 (vqdmulltq_n_s16): Likewise.
9965 (vqdmullbq_s16): Likewise.
9966 (vqdmullbq_n_s16): Likewise.
9967 (vorrq_f16): Likewise.
9968 (vornq_f16): Likewise.
9969 (vmulq_n_f16): Likewise.
9970 (vmulq_f16): Likewise.
9971 (vmovntq_s16): Likewise.
9972 (vmovnbq_s16): Likewise.
9973 (vmlsldavxq_s16): Likewise.
9974 (vmlsldavq_s16): Likewise.
9975 (vmlaldavxq_s16): Likewise.
9976 (vmlaldavq_s16): Likewise.
9977 (vminnmvq_f16): Likewise.
9978 (vminnmq_f16): Likewise.
9979 (vminnmavq_f16): Likewise.
9980 (vminnmaq_f16): Likewise.
9981 (vmaxnmvq_f16): Likewise.
9982 (vmaxnmq_f16): Likewise.
9983 (vmaxnmavq_f16): Likewise.
9984 (vmaxnmaq_f16): Likewise.
9985 (veorq_f16): Likewise.
9986 (vcmulq_rot90_f16): Likewise.
9987 (vcmulq_rot270_f16): Likewise.
9988 (vcmulq_rot180_f16): Likewise.
9989 (vcmulq_f16): Likewise.
9990 (vcaddq_rot90_f16): Likewise.
9991 (vcaddq_rot270_f16): Likewise.
9992 (vbicq_f16): Likewise.
9993 (vandq_f16): Likewise.
9994 (vaddq_n_f16): Likewise.
9995 (vabdq_f16): Likewise.
9996 (vshlltq_n_s8): Likewise.
9997 (vshllbq_n_s8): Likewise.
9998 (vorrq_n_s16): Likewise.
9999 (vbicq_n_s16): Likewise.
10000 (vqmovntq_u32): Likewise.
10001 (vqmovnbq_u32): Likewise.
10002 (vmulltq_poly_p16): Likewise.
10003 (vmullbq_poly_p16): Likewise.
10004 (vmovntq_u32): Likewise.
10005 (vmovnbq_u32): Likewise.
10006 (vmlaldavxq_u32): Likewise.
10007 (vmlaldavq_u32): Likewise.
10008 (vqmovuntq_s32): Likewise.
10009 (vqmovunbq_s32): Likewise.
10010 (vshlltq_n_u16): Likewise.
10011 (vshllbq_n_u16): Likewise.
10012 (vorrq_n_u32): Likewise.
10013 (vbicq_n_u32): Likewise.
10014 (vcmpneq_n_f32): Likewise.
10015 (vcmpneq_f32): Likewise.
10016 (vcmpltq_n_f32): Likewise.
10017 (vcmpltq_f32): Likewise.
10018 (vcmpleq_n_f32): Likewise.
10019 (vcmpleq_f32): Likewise.
10020 (vcmpgtq_n_f32): Likewise.
10021 (vcmpgtq_f32): Likewise.
10022 (vcmpgeq_n_f32): Likewise.
10023 (vcmpgeq_f32): Likewise.
10024 (vcmpeqq_n_f32): Likewise.
10025 (vcmpeqq_f32): Likewise.
10026 (vsubq_f32): Likewise.
10027 (vqmovntq_s32): Likewise.
10028 (vqmovnbq_s32): Likewise.
10029 (vqdmulltq_s32): Likewise.
10030 (vqdmulltq_n_s32): Likewise.
10031 (vqdmullbq_s32): Likewise.
10032 (vqdmullbq_n_s32): Likewise.
10033 (vorrq_f32): Likewise.
10034 (vornq_f32): Likewise.
10035 (vmulq_n_f32): Likewise.
10036 (vmulq_f32): Likewise.
10037 (vmovntq_s32): Likewise.
10038 (vmovnbq_s32): Likewise.
10039 (vmlsldavxq_s32): Likewise.
10040 (vmlsldavq_s32): Likewise.
10041 (vmlaldavxq_s32): Likewise.
10042 (vmlaldavq_s32): Likewise.
10043 (vminnmvq_f32): Likewise.
10044 (vminnmq_f32): Likewise.
10045 (vminnmavq_f32): Likewise.
10046 (vminnmaq_f32): Likewise.
10047 (vmaxnmvq_f32): Likewise.
10048 (vmaxnmq_f32): Likewise.
10049 (vmaxnmavq_f32): Likewise.
10050 (vmaxnmaq_f32): Likewise.
10051 (veorq_f32): Likewise.
10052 (vcmulq_rot90_f32): Likewise.
10053 (vcmulq_rot270_f32): Likewise.
10054 (vcmulq_rot180_f32): Likewise.
10055 (vcmulq_f32): Likewise.
10056 (vcaddq_rot90_f32): Likewise.
10057 (vcaddq_rot270_f32): Likewise.
10058 (vbicq_f32): Likewise.
10059 (vandq_f32): Likewise.
10060 (vaddq_n_f32): Likewise.
10061 (vabdq_f32): Likewise.
10062 (vshlltq_n_s16): Likewise.
10063 (vshllbq_n_s16): Likewise.
10064 (vorrq_n_s32): Likewise.
10065 (vbicq_n_s32): Likewise.
10066 (vrmlaldavhq_u32): Likewise.
10067 (vctp8q_m): Likewise.
10068 (vctp64q_m): Likewise.
10069 (vctp32q_m): Likewise.
10070 (vctp16q_m): Likewise.
10071 (vaddlvaq_u32): Likewise.
10072 (vrmlsldavhxq_s32): Likewise.
10073 (vrmlsldavhq_s32): Likewise.
10074 (vrmlaldavhxq_s32): Likewise.
10075 (vrmlaldavhq_s32): Likewise.
10076 (vcvttq_f16_f32): Likewise.
10077 (vcvtbq_f16_f32): Likewise.
10078 (vaddlvaq_s32): Likewise.
10079 (__arm_vqmovntq_u16): Define intrinsic.
10080 (__arm_vqmovnbq_u16): Likewise.
10081 (__arm_vmulltq_poly_p8): Likewise.
10082 (__arm_vmullbq_poly_p8): Likewise.
10083 (__arm_vmovntq_u16): Likewise.
10084 (__arm_vmovnbq_u16): Likewise.
10085 (__arm_vmlaldavxq_u16): Likewise.
10086 (__arm_vmlaldavq_u16): Likewise.
10087 (__arm_vqmovuntq_s16): Likewise.
10088 (__arm_vqmovunbq_s16): Likewise.
10089 (__arm_vshlltq_n_u8): Likewise.
10090 (__arm_vshllbq_n_u8): Likewise.
10091 (__arm_vorrq_n_u16): Likewise.
10092 (__arm_vbicq_n_u16): Likewise.
10093 (__arm_vcmpneq_n_f16): Likewise.
10094 (__arm_vcmpneq_f16): Likewise.
10095 (__arm_vcmpltq_n_f16): Likewise.
10096 (__arm_vcmpltq_f16): Likewise.
10097 (__arm_vcmpleq_n_f16): Likewise.
10098 (__arm_vcmpleq_f16): Likewise.
10099 (__arm_vcmpgtq_n_f16): Likewise.
10100 (__arm_vcmpgtq_f16): Likewise.
10101 (__arm_vcmpgeq_n_f16): Likewise.
10102 (__arm_vcmpgeq_f16): Likewise.
10103 (__arm_vcmpeqq_n_f16): Likewise.
10104 (__arm_vcmpeqq_f16): Likewise.
10105 (__arm_vsubq_f16): Likewise.
10106 (__arm_vqmovntq_s16): Likewise.
10107 (__arm_vqmovnbq_s16): Likewise.
10108 (__arm_vqdmulltq_s16): Likewise.
10109 (__arm_vqdmulltq_n_s16): Likewise.
10110 (__arm_vqdmullbq_s16): Likewise.
10111 (__arm_vqdmullbq_n_s16): Likewise.
10112 (__arm_vorrq_f16): Likewise.
10113 (__arm_vornq_f16): Likewise.
10114 (__arm_vmulq_n_f16): Likewise.
10115 (__arm_vmulq_f16): Likewise.
10116 (__arm_vmovntq_s16): Likewise.
10117 (__arm_vmovnbq_s16): Likewise.
10118 (__arm_vmlsldavxq_s16): Likewise.
10119 (__arm_vmlsldavq_s16): Likewise.
10120 (__arm_vmlaldavxq_s16): Likewise.
10121 (__arm_vmlaldavq_s16): Likewise.
10122 (__arm_vminnmvq_f16): Likewise.
10123 (__arm_vminnmq_f16): Likewise.
10124 (__arm_vminnmavq_f16): Likewise.
10125 (__arm_vminnmaq_f16): Likewise.
10126 (__arm_vmaxnmvq_f16): Likewise.
10127 (__arm_vmaxnmq_f16): Likewise.
10128 (__arm_vmaxnmavq_f16): Likewise.
10129 (__arm_vmaxnmaq_f16): Likewise.
10130 (__arm_veorq_f16): Likewise.
10131 (__arm_vcmulq_rot90_f16): Likewise.
10132 (__arm_vcmulq_rot270_f16): Likewise.
10133 (__arm_vcmulq_rot180_f16): Likewise.
10134 (__arm_vcmulq_f16): Likewise.
10135 (__arm_vcaddq_rot90_f16): Likewise.
10136 (__arm_vcaddq_rot270_f16): Likewise.
10137 (__arm_vbicq_f16): Likewise.
10138 (__arm_vandq_f16): Likewise.
10139 (__arm_vaddq_n_f16): Likewise.
10140 (__arm_vabdq_f16): Likewise.
10141 (__arm_vshlltq_n_s8): Likewise.
10142 (__arm_vshllbq_n_s8): Likewise.
10143 (__arm_vorrq_n_s16): Likewise.
10144 (__arm_vbicq_n_s16): Likewise.
10145 (__arm_vqmovntq_u32): Likewise.
10146 (__arm_vqmovnbq_u32): Likewise.
10147 (__arm_vmulltq_poly_p16): Likewise.
10148 (__arm_vmullbq_poly_p16): Likewise.
10149 (__arm_vmovntq_u32): Likewise.
10150 (__arm_vmovnbq_u32): Likewise.
10151 (__arm_vmlaldavxq_u32): Likewise.
10152 (__arm_vmlaldavq_u32): Likewise.
10153 (__arm_vqmovuntq_s32): Likewise.
10154 (__arm_vqmovunbq_s32): Likewise.
10155 (__arm_vshlltq_n_u16): Likewise.
10156 (__arm_vshllbq_n_u16): Likewise.
10157 (__arm_vorrq_n_u32): Likewise.
10158 (__arm_vbicq_n_u32): Likewise.
10159 (__arm_vcmpneq_n_f32): Likewise.
10160 (__arm_vcmpneq_f32): Likewise.
10161 (__arm_vcmpltq_n_f32): Likewise.
10162 (__arm_vcmpltq_f32): Likewise.
10163 (__arm_vcmpleq_n_f32): Likewise.
10164 (__arm_vcmpleq_f32): Likewise.
10165 (__arm_vcmpgtq_n_f32): Likewise.
10166 (__arm_vcmpgtq_f32): Likewise.
10167 (__arm_vcmpgeq_n_f32): Likewise.
10168 (__arm_vcmpgeq_f32): Likewise.
10169 (__arm_vcmpeqq_n_f32): Likewise.
10170 (__arm_vcmpeqq_f32): Likewise.
10171 (__arm_vsubq_f32): Likewise.
10172 (__arm_vqmovntq_s32): Likewise.
10173 (__arm_vqmovnbq_s32): Likewise.
10174 (__arm_vqdmulltq_s32): Likewise.
10175 (__arm_vqdmulltq_n_s32): Likewise.
10176 (__arm_vqdmullbq_s32): Likewise.
10177 (__arm_vqdmullbq_n_s32): Likewise.
10178 (__arm_vorrq_f32): Likewise.
10179 (__arm_vornq_f32): Likewise.
10180 (__arm_vmulq_n_f32): Likewise.
10181 (__arm_vmulq_f32): Likewise.
10182 (__arm_vmovntq_s32): Likewise.
10183 (__arm_vmovnbq_s32): Likewise.
10184 (__arm_vmlsldavxq_s32): Likewise.
10185 (__arm_vmlsldavq_s32): Likewise.
10186 (__arm_vmlaldavxq_s32): Likewise.
10187 (__arm_vmlaldavq_s32): Likewise.
10188 (__arm_vminnmvq_f32): Likewise.
10189 (__arm_vminnmq_f32): Likewise.
10190 (__arm_vminnmavq_f32): Likewise.
10191 (__arm_vminnmaq_f32): Likewise.
10192 (__arm_vmaxnmvq_f32): Likewise.
10193 (__arm_vmaxnmq_f32): Likewise.
10194 (__arm_vmaxnmavq_f32): Likewise.
10195 (__arm_vmaxnmaq_f32): Likewise.
10196 (__arm_veorq_f32): Likewise.
10197 (__arm_vcmulq_rot90_f32): Likewise.
10198 (__arm_vcmulq_rot270_f32): Likewise.
10199 (__arm_vcmulq_rot180_f32): Likewise.
10200 (__arm_vcmulq_f32): Likewise.
10201 (__arm_vcaddq_rot90_f32): Likewise.
10202 (__arm_vcaddq_rot270_f32): Likewise.
10203 (__arm_vbicq_f32): Likewise.
10204 (__arm_vandq_f32): Likewise.
10205 (__arm_vaddq_n_f32): Likewise.
10206 (__arm_vabdq_f32): Likewise.
10207 (__arm_vshlltq_n_s16): Likewise.
10208 (__arm_vshllbq_n_s16): Likewise.
10209 (__arm_vorrq_n_s32): Likewise.
10210 (__arm_vbicq_n_s32): Likewise.
10211 (__arm_vrmlaldavhq_u32): Likewise.
10212 (__arm_vctp8q_m): Likewise.
10213 (__arm_vctp64q_m): Likewise.
10214 (__arm_vctp32q_m): Likewise.
10215 (__arm_vctp16q_m): Likewise.
10216 (__arm_vaddlvaq_u32): Likewise.
10217 (__arm_vrmlsldavhxq_s32): Likewise.
10218 (__arm_vrmlsldavhq_s32): Likewise.
10219 (__arm_vrmlaldavhxq_s32): Likewise.
10220 (__arm_vrmlaldavhq_s32): Likewise.
10221 (__arm_vcvttq_f16_f32): Likewise.
10222 (__arm_vcvtbq_f16_f32): Likewise.
10223 (__arm_vaddlvaq_s32): Likewise.
10224 (vst4q): Define polymorphic variant.
10225 (vrndxq): Likewise.
10227 (vrndpq): Likewise.
10228 (vrndnq): Likewise.
10229 (vrndmq): Likewise.
10230 (vrndaq): Likewise.
10231 (vrev64q): Likewise.
10233 (vdupq_n): Likewise.
10235 (vrev32q): Likewise.
10236 (vcvtbq_f32): Likewise.
10237 (vcvttq_f32): Likewise.
10239 (vsubq_n): Likewise.
10240 (vbrsrq_n): Likewise.
10241 (vcvtq_n): Likewise.
10245 (vaddq_n): Likewise.
10249 (vmulq_n): Likewise.
10251 (vcaddq_rot270): Likewise.
10252 (vcmpeqq_n): Likewise.
10253 (vcmpeqq): Likewise.
10254 (vcaddq_rot90): Likewise.
10255 (vcmpgeq_n): Likewise.
10256 (vcmpgeq): Likewise.
10257 (vcmpgtq_n): Likewise.
10258 (vcmpgtq): Likewise.
10259 (vcmpgtq): Likewise.
10260 (vcmpleq_n): Likewise.
10261 (vcmpleq_n): Likewise.
10262 (vcmpleq): Likewise.
10263 (vcmpleq): Likewise.
10264 (vcmpltq_n): Likewise.
10265 (vcmpltq_n): Likewise.
10266 (vcmpltq): Likewise.
10267 (vcmpltq): Likewise.
10268 (vcmpneq_n): Likewise.
10269 (vcmpneq_n): Likewise.
10270 (vcmpneq): Likewise.
10271 (vcmpneq): Likewise.
10272 (vcmulq): Likewise.
10273 (vcmulq): Likewise.
10274 (vcmulq_rot180): Likewise.
10275 (vcmulq_rot180): Likewise.
10276 (vcmulq_rot270): Likewise.
10277 (vcmulq_rot270): Likewise.
10278 (vcmulq_rot90): Likewise.
10279 (vcmulq_rot90): Likewise.
10282 (vmaxnmaq): Likewise.
10283 (vmaxnmaq): Likewise.
10284 (vmaxnmavq): Likewise.
10285 (vmaxnmavq): Likewise.
10286 (vmaxnmq): Likewise.
10287 (vmaxnmq): Likewise.
10288 (vmaxnmvq): Likewise.
10289 (vmaxnmvq): Likewise.
10290 (vminnmaq): Likewise.
10291 (vminnmaq): Likewise.
10292 (vminnmavq): Likewise.
10293 (vminnmavq): Likewise.
10294 (vminnmq): Likewise.
10295 (vminnmq): Likewise.
10296 (vminnmvq): Likewise.
10297 (vminnmvq): Likewise.
10298 (vbicq_n): Likewise.
10299 (vqmovntq): Likewise.
10300 (vqmovntq): Likewise.
10301 (vqmovnbq): Likewise.
10302 (vqmovnbq): Likewise.
10303 (vmulltq_poly): Likewise.
10304 (vmulltq_poly): Likewise.
10305 (vmullbq_poly): Likewise.
10306 (vmullbq_poly): Likewise.
10307 (vmovntq): Likewise.
10308 (vmovntq): Likewise.
10309 (vmovnbq): Likewise.
10310 (vmovnbq): Likewise.
10311 (vmlaldavxq): Likewise.
10312 (vmlaldavxq): Likewise.
10313 (vqmovuntq): Likewise.
10314 (vqmovuntq): Likewise.
10315 (vshlltq_n): Likewise.
10316 (vshlltq_n): Likewise.
10317 (vshllbq_n): Likewise.
10318 (vshllbq_n): Likewise.
10319 (vorrq_n): Likewise.
10320 (vorrq_n): Likewise.
10321 (vmlaldavq): Likewise.
10322 (vmlaldavq): Likewise.
10323 (vqmovunbq): Likewise.
10324 (vqmovunbq): Likewise.
10325 (vqdmulltq_n): Likewise.
10326 (vqdmulltq_n): Likewise.
10327 (vqdmulltq): Likewise.
10328 (vqdmulltq): Likewise.
10329 (vqdmullbq_n): Likewise.
10330 (vqdmullbq_n): Likewise.
10331 (vqdmullbq): Likewise.
10332 (vqdmullbq): Likewise.
10333 (vaddlvaq): Likewise.
10334 (vaddlvaq): Likewise.
10335 (vrmlaldavhq): Likewise.
10336 (vrmlaldavhq): Likewise.
10337 (vrmlaldavhxq): Likewise.
10338 (vrmlaldavhxq): Likewise.
10339 (vrmlsldavhq): Likewise.
10340 (vrmlsldavhq): Likewise.
10341 (vrmlsldavhxq): Likewise.
10342 (vrmlsldavhxq): Likewise.
10343 (vmlsldavxq): Likewise.
10344 (vmlsldavxq): Likewise.
10345 (vmlsldavq): Likewise.
10346 (vmlsldavq): Likewise.
10347 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
10348 (BINOP_NONE_NONE_NONE): Likewise.
10349 (BINOP_UNONE_NONE_NONE): Likewise.
10350 (BINOP_UNONE_UNONE_IMM): Likewise.
10351 (BINOP_UNONE_UNONE_NONE): Likewise.
10352 (BINOP_UNONE_UNONE_UNONE): Likewise.
10353 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
10354 (mve_vaddlvaq_<supf>v4si): Likewise.
10355 (mve_vaddq_n_f<mode>): Likewise.
10356 (mve_vandq_f<mode>): Likewise.
10357 (mve_vbicq_f<mode>): Likewise.
10358 (mve_vbicq_n_<supf><mode>): Likewise.
10359 (mve_vcaddq_rot270_f<mode>): Likewise.
10360 (mve_vcaddq_rot90_f<mode>): Likewise.
10361 (mve_vcmpeqq_f<mode>): Likewise.
10362 (mve_vcmpeqq_n_f<mode>): Likewise.
10363 (mve_vcmpgeq_f<mode>): Likewise.
10364 (mve_vcmpgeq_n_f<mode>): Likewise.
10365 (mve_vcmpgtq_f<mode>): Likewise.
10366 (mve_vcmpgtq_n_f<mode>): Likewise.
10367 (mve_vcmpleq_f<mode>): Likewise.
10368 (mve_vcmpleq_n_f<mode>): Likewise.
10369 (mve_vcmpltq_f<mode>): Likewise.
10370 (mve_vcmpltq_n_f<mode>): Likewise.
10371 (mve_vcmpneq_f<mode>): Likewise.
10372 (mve_vcmpneq_n_f<mode>): Likewise.
10373 (mve_vcmulq_f<mode>): Likewise.
10374 (mve_vcmulq_rot180_f<mode>): Likewise.
10375 (mve_vcmulq_rot270_f<mode>): Likewise.
10376 (mve_vcmulq_rot90_f<mode>): Likewise.
10377 (mve_vctp<mode1>q_mhi): Likewise.
10378 (mve_vcvtbq_f16_f32v8hf): Likewise.
10379 (mve_vcvttq_f16_f32v8hf): Likewise.
10380 (mve_veorq_f<mode>): Likewise.
10381 (mve_vmaxnmaq_f<mode>): Likewise.
10382 (mve_vmaxnmavq_f<mode>): Likewise.
10383 (mve_vmaxnmq_f<mode>): Likewise.
10384 (mve_vmaxnmvq_f<mode>): Likewise.
10385 (mve_vminnmaq_f<mode>): Likewise.
10386 (mve_vminnmavq_f<mode>): Likewise.
10387 (mve_vminnmq_f<mode>): Likewise.
10388 (mve_vminnmvq_f<mode>): Likewise.
10389 (mve_vmlaldavq_<supf><mode>): Likewise.
10390 (mve_vmlaldavxq_<supf><mode>): Likewise.
10391 (mve_vmlsldavq_s<mode>): Likewise.
10392 (mve_vmlsldavxq_s<mode>): Likewise.
10393 (mve_vmovnbq_<supf><mode>): Likewise.
10394 (mve_vmovntq_<supf><mode>): Likewise.
10395 (mve_vmulq_f<mode>): Likewise.
10396 (mve_vmulq_n_f<mode>): Likewise.
10397 (mve_vornq_f<mode>): Likewise.
10398 (mve_vorrq_f<mode>): Likewise.
10399 (mve_vorrq_n_<supf><mode>): Likewise.
10400 (mve_vqdmullbq_n_s<mode>): Likewise.
10401 (mve_vqdmullbq_s<mode>): Likewise.
10402 (mve_vqdmulltq_n_s<mode>): Likewise.
10403 (mve_vqdmulltq_s<mode>): Likewise.
10404 (mve_vqmovnbq_<supf><mode>): Likewise.
10405 (mve_vqmovntq_<supf><mode>): Likewise.
10406 (mve_vqmovunbq_s<mode>): Likewise.
10407 (mve_vqmovuntq_s<mode>): Likewise.
10408 (mve_vrmlaldavhxq_sv4si): Likewise.
10409 (mve_vrmlsldavhq_sv4si): Likewise.
10410 (mve_vrmlsldavhxq_sv4si): Likewise.
10411 (mve_vshllbq_n_<supf><mode>): Likewise.
10412 (mve_vshlltq_n_<supf><mode>): Likewise.
10413 (mve_vsubq_f<mode>): Likewise.
10414 (mve_vmulltq_poly_p<mode>): Likewise.
10415 (mve_vmullbq_poly_p<mode>): Likewise.
10416 (mve_vrmlaldavhq_<supf>v4si): Likewise.
10418 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10419 Mihail Ionescu <mihail.ionescu@arm.com>
10420 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10422 * config/arm/arm_mve.h (vsubq_u8): Define macro.
10423 (vsubq_n_u8): Likewise.
10424 (vrmulhq_u8): Likewise.
10425 (vrhaddq_u8): Likewise.
10426 (vqsubq_u8): Likewise.
10427 (vqsubq_n_u8): Likewise.
10428 (vqaddq_u8): Likewise.
10429 (vqaddq_n_u8): Likewise.
10430 (vorrq_u8): Likewise.
10431 (vornq_u8): Likewise.
10432 (vmulq_u8): Likewise.
10433 (vmulq_n_u8): Likewise.
10434 (vmulltq_int_u8): Likewise.
10435 (vmullbq_int_u8): Likewise.
10436 (vmulhq_u8): Likewise.
10437 (vmladavq_u8): Likewise.
10438 (vminvq_u8): Likewise.
10439 (vminq_u8): Likewise.
10440 (vmaxvq_u8): Likewise.
10441 (vmaxq_u8): Likewise.
10442 (vhsubq_u8): Likewise.
10443 (vhsubq_n_u8): Likewise.
10444 (vhaddq_u8): Likewise.
10445 (vhaddq_n_u8): Likewise.
10446 (veorq_u8): Likewise.
10447 (vcmpneq_n_u8): Likewise.
10448 (vcmphiq_u8): Likewise.
10449 (vcmphiq_n_u8): Likewise.
10450 (vcmpeqq_u8): Likewise.
10451 (vcmpeqq_n_u8): Likewise.
10452 (vcmpcsq_u8): Likewise.
10453 (vcmpcsq_n_u8): Likewise.
10454 (vcaddq_rot90_u8): Likewise.
10455 (vcaddq_rot270_u8): Likewise.
10456 (vbicq_u8): Likewise.
10457 (vandq_u8): Likewise.
10458 (vaddvq_p_u8): Likewise.
10459 (vaddvaq_u8): Likewise.
10460 (vaddq_n_u8): Likewise.
10461 (vabdq_u8): Likewise.
10462 (vshlq_r_u8): Likewise.
10463 (vrshlq_u8): Likewise.
10464 (vrshlq_n_u8): Likewise.
10465 (vqshlq_u8): Likewise.
10466 (vqshlq_r_u8): Likewise.
10467 (vqrshlq_u8): Likewise.
10468 (vqrshlq_n_u8): Likewise.
10469 (vminavq_s8): Likewise.
10470 (vminaq_s8): Likewise.
10471 (vmaxavq_s8): Likewise.
10472 (vmaxaq_s8): Likewise.
10473 (vbrsrq_n_u8): Likewise.
10474 (vshlq_n_u8): Likewise.
10475 (vrshrq_n_u8): Likewise.
10476 (vqshlq_n_u8): Likewise.
10477 (vcmpneq_n_s8): Likewise.
10478 (vcmpltq_s8): Likewise.
10479 (vcmpltq_n_s8): Likewise.
10480 (vcmpleq_s8): Likewise.
10481 (vcmpleq_n_s8): Likewise.
10482 (vcmpgtq_s8): Likewise.
10483 (vcmpgtq_n_s8): Likewise.
10484 (vcmpgeq_s8): Likewise.
10485 (vcmpgeq_n_s8): Likewise.
10486 (vcmpeqq_s8): Likewise.
10487 (vcmpeqq_n_s8): Likewise.
10488 (vqshluq_n_s8): Likewise.
10489 (vaddvq_p_s8): Likewise.
10490 (vsubq_s8): Likewise.
10491 (vsubq_n_s8): Likewise.
10492 (vshlq_r_s8): Likewise.
10493 (vrshlq_s8): Likewise.
10494 (vrshlq_n_s8): Likewise.
10495 (vrmulhq_s8): Likewise.
10496 (vrhaddq_s8): Likewise.
10497 (vqsubq_s8): Likewise.
10498 (vqsubq_n_s8): Likewise.
10499 (vqshlq_s8): Likewise.
10500 (vqshlq_r_s8): Likewise.
10501 (vqrshlq_s8): Likewise.
10502 (vqrshlq_n_s8): Likewise.
10503 (vqrdmulhq_s8): Likewise.
10504 (vqrdmulhq_n_s8): Likewise.
10505 (vqdmulhq_s8): Likewise.
10506 (vqdmulhq_n_s8): Likewise.
10507 (vqaddq_s8): Likewise.
10508 (vqaddq_n_s8): Likewise.
10509 (vorrq_s8): Likewise.
10510 (vornq_s8): Likewise.
10511 (vmulq_s8): Likewise.
10512 (vmulq_n_s8): Likewise.
10513 (vmulltq_int_s8): Likewise.
10514 (vmullbq_int_s8): Likewise.
10515 (vmulhq_s8): Likewise.
10516 (vmlsdavxq_s8): Likewise.
10517 (vmlsdavq_s8): Likewise.
10518 (vmladavxq_s8): Likewise.
10519 (vmladavq_s8): Likewise.
10520 (vminvq_s8): Likewise.
10521 (vminq_s8): Likewise.
10522 (vmaxvq_s8): Likewise.
10523 (vmaxq_s8): Likewise.
10524 (vhsubq_s8): Likewise.
10525 (vhsubq_n_s8): Likewise.
10526 (vhcaddq_rot90_s8): Likewise.
10527 (vhcaddq_rot270_s8): Likewise.
10528 (vhaddq_s8): Likewise.
10529 (vhaddq_n_s8): Likewise.
10530 (veorq_s8): Likewise.
10531 (vcaddq_rot90_s8): Likewise.
10532 (vcaddq_rot270_s8): Likewise.
10533 (vbrsrq_n_s8): Likewise.
10534 (vbicq_s8): Likewise.
10535 (vandq_s8): Likewise.
10536 (vaddvaq_s8): Likewise.
10537 (vaddq_n_s8): Likewise.
10538 (vabdq_s8): Likewise.
10539 (vshlq_n_s8): Likewise.
10540 (vrshrq_n_s8): Likewise.
10541 (vqshlq_n_s8): Likewise.
10542 (vsubq_u16): Likewise.
10543 (vsubq_n_u16): Likewise.
10544 (vrmulhq_u16): Likewise.
10545 (vrhaddq_u16): Likewise.
10546 (vqsubq_u16): Likewise.
10547 (vqsubq_n_u16): Likewise.
10548 (vqaddq_u16): Likewise.
10549 (vqaddq_n_u16): Likewise.
10550 (vorrq_u16): Likewise.
10551 (vornq_u16): Likewise.
10552 (vmulq_u16): Likewise.
10553 (vmulq_n_u16): Likewise.
10554 (vmulltq_int_u16): Likewise.
10555 (vmullbq_int_u16): Likewise.
10556 (vmulhq_u16): Likewise.
10557 (vmladavq_u16): Likewise.
10558 (vminvq_u16): Likewise.
10559 (vminq_u16): Likewise.
10560 (vmaxvq_u16): Likewise.
10561 (vmaxq_u16): Likewise.
10562 (vhsubq_u16): Likewise.
10563 (vhsubq_n_u16): Likewise.
10564 (vhaddq_u16): Likewise.
10565 (vhaddq_n_u16): Likewise.
10566 (veorq_u16): Likewise.
10567 (vcmpneq_n_u16): Likewise.
10568 (vcmphiq_u16): Likewise.
10569 (vcmphiq_n_u16): Likewise.
10570 (vcmpeqq_u16): Likewise.
10571 (vcmpeqq_n_u16): Likewise.
10572 (vcmpcsq_u16): Likewise.
10573 (vcmpcsq_n_u16): Likewise.
10574 (vcaddq_rot90_u16): Likewise.
10575 (vcaddq_rot270_u16): Likewise.
10576 (vbicq_u16): Likewise.
10577 (vandq_u16): Likewise.
10578 (vaddvq_p_u16): Likewise.
10579 (vaddvaq_u16): Likewise.
10580 (vaddq_n_u16): Likewise.
10581 (vabdq_u16): Likewise.
10582 (vshlq_r_u16): Likewise.
10583 (vrshlq_u16): Likewise.
10584 (vrshlq_n_u16): Likewise.
10585 (vqshlq_u16): Likewise.
10586 (vqshlq_r_u16): Likewise.
10587 (vqrshlq_u16): Likewise.
10588 (vqrshlq_n_u16): Likewise.
10589 (vminavq_s16): Likewise.
10590 (vminaq_s16): Likewise.
10591 (vmaxavq_s16): Likewise.
10592 (vmaxaq_s16): Likewise.
10593 (vbrsrq_n_u16): Likewise.
10594 (vshlq_n_u16): Likewise.
10595 (vrshrq_n_u16): Likewise.
10596 (vqshlq_n_u16): Likewise.
10597 (vcmpneq_n_s16): Likewise.
10598 (vcmpltq_s16): Likewise.
10599 (vcmpltq_n_s16): Likewise.
10600 (vcmpleq_s16): Likewise.
10601 (vcmpleq_n_s16): Likewise.
10602 (vcmpgtq_s16): Likewise.
10603 (vcmpgtq_n_s16): Likewise.
10604 (vcmpgeq_s16): Likewise.
10605 (vcmpgeq_n_s16): Likewise.
10606 (vcmpeqq_s16): Likewise.
10607 (vcmpeqq_n_s16): Likewise.
10608 (vqshluq_n_s16): Likewise.
10609 (vaddvq_p_s16): Likewise.
10610 (vsubq_s16): Likewise.
10611 (vsubq_n_s16): Likewise.
10612 (vshlq_r_s16): Likewise.
10613 (vrshlq_s16): Likewise.
10614 (vrshlq_n_s16): Likewise.
10615 (vrmulhq_s16): Likewise.
10616 (vrhaddq_s16): Likewise.
10617 (vqsubq_s16): Likewise.
10618 (vqsubq_n_s16): Likewise.
10619 (vqshlq_s16): Likewise.
10620 (vqshlq_r_s16): Likewise.
10621 (vqrshlq_s16): Likewise.
10622 (vqrshlq_n_s16): Likewise.
10623 (vqrdmulhq_s16): Likewise.
10624 (vqrdmulhq_n_s16): Likewise.
10625 (vqdmulhq_s16): Likewise.
10626 (vqdmulhq_n_s16): Likewise.
10627 (vqaddq_s16): Likewise.
10628 (vqaddq_n_s16): Likewise.
10629 (vorrq_s16): Likewise.
10630 (vornq_s16): Likewise.
10631 (vmulq_s16): Likewise.
10632 (vmulq_n_s16): Likewise.
10633 (vmulltq_int_s16): Likewise.
10634 (vmullbq_int_s16): Likewise.
10635 (vmulhq_s16): Likewise.
10636 (vmlsdavxq_s16): Likewise.
10637 (vmlsdavq_s16): Likewise.
10638 (vmladavxq_s16): Likewise.
10639 (vmladavq_s16): Likewise.
10640 (vminvq_s16): Likewise.
10641 (vminq_s16): Likewise.
10642 (vmaxvq_s16): Likewise.
10643 (vmaxq_s16): Likewise.
10644 (vhsubq_s16): Likewise.
10645 (vhsubq_n_s16): Likewise.
10646 (vhcaddq_rot90_s16): Likewise.
10647 (vhcaddq_rot270_s16): Likewise.
10648 (vhaddq_s16): Likewise.
10649 (vhaddq_n_s16): Likewise.
10650 (veorq_s16): Likewise.
10651 (vcaddq_rot90_s16): Likewise.
10652 (vcaddq_rot270_s16): Likewise.
10653 (vbrsrq_n_s16): Likewise.
10654 (vbicq_s16): Likewise.
10655 (vandq_s16): Likewise.
10656 (vaddvaq_s16): Likewise.
10657 (vaddq_n_s16): Likewise.
10658 (vabdq_s16): Likewise.
10659 (vshlq_n_s16): Likewise.
10660 (vrshrq_n_s16): Likewise.
10661 (vqshlq_n_s16): Likewise.
10662 (vsubq_u32): Likewise.
10663 (vsubq_n_u32): Likewise.
10664 (vrmulhq_u32): Likewise.
10665 (vrhaddq_u32): Likewise.
10666 (vqsubq_u32): Likewise.
10667 (vqsubq_n_u32): Likewise.
10668 (vqaddq_u32): Likewise.
10669 (vqaddq_n_u32): Likewise.
10670 (vorrq_u32): Likewise.
10671 (vornq_u32): Likewise.
10672 (vmulq_u32): Likewise.
10673 (vmulq_n_u32): Likewise.
10674 (vmulltq_int_u32): Likewise.
10675 (vmullbq_int_u32): Likewise.
10676 (vmulhq_u32): Likewise.
10677 (vmladavq_u32): Likewise.
10678 (vminvq_u32): Likewise.
10679 (vminq_u32): Likewise.
10680 (vmaxvq_u32): Likewise.
10681 (vmaxq_u32): Likewise.
10682 (vhsubq_u32): Likewise.
10683 (vhsubq_n_u32): Likewise.
10684 (vhaddq_u32): Likewise.
10685 (vhaddq_n_u32): Likewise.
10686 (veorq_u32): Likewise.
10687 (vcmpneq_n_u32): Likewise.
10688 (vcmphiq_u32): Likewise.
10689 (vcmphiq_n_u32): Likewise.
10690 (vcmpeqq_u32): Likewise.
10691 (vcmpeqq_n_u32): Likewise.
10692 (vcmpcsq_u32): Likewise.
10693 (vcmpcsq_n_u32): Likewise.
10694 (vcaddq_rot90_u32): Likewise.
10695 (vcaddq_rot270_u32): Likewise.
10696 (vbicq_u32): Likewise.
10697 (vandq_u32): Likewise.
10698 (vaddvq_p_u32): Likewise.
10699 (vaddvaq_u32): Likewise.
10700 (vaddq_n_u32): Likewise.
10701 (vabdq_u32): Likewise.
10702 (vshlq_r_u32): Likewise.
10703 (vrshlq_u32): Likewise.
10704 (vrshlq_n_u32): Likewise.
10705 (vqshlq_u32): Likewise.
10706 (vqshlq_r_u32): Likewise.
10707 (vqrshlq_u32): Likewise.
10708 (vqrshlq_n_u32): Likewise.
10709 (vminavq_s32): Likewise.
10710 (vminaq_s32): Likewise.
10711 (vmaxavq_s32): Likewise.
10712 (vmaxaq_s32): Likewise.
10713 (vbrsrq_n_u32): Likewise.
10714 (vshlq_n_u32): Likewise.
10715 (vrshrq_n_u32): Likewise.
10716 (vqshlq_n_u32): Likewise.
10717 (vcmpneq_n_s32): Likewise.
10718 (vcmpltq_s32): Likewise.
10719 (vcmpltq_n_s32): Likewise.
10720 (vcmpleq_s32): Likewise.
10721 (vcmpleq_n_s32): Likewise.
10722 (vcmpgtq_s32): Likewise.
10723 (vcmpgtq_n_s32): Likewise.
10724 (vcmpgeq_s32): Likewise.
10725 (vcmpgeq_n_s32): Likewise.
10726 (vcmpeqq_s32): Likewise.
10727 (vcmpeqq_n_s32): Likewise.
10728 (vqshluq_n_s32): Likewise.
10729 (vaddvq_p_s32): Likewise.
10730 (vsubq_s32): Likewise.
10731 (vsubq_n_s32): Likewise.
10732 (vshlq_r_s32): Likewise.
10733 (vrshlq_s32): Likewise.
10734 (vrshlq_n_s32): Likewise.
10735 (vrmulhq_s32): Likewise.
10736 (vrhaddq_s32): Likewise.
10737 (vqsubq_s32): Likewise.
10738 (vqsubq_n_s32): Likewise.
10739 (vqshlq_s32): Likewise.
10740 (vqshlq_r_s32): Likewise.
10741 (vqrshlq_s32): Likewise.
10742 (vqrshlq_n_s32): Likewise.
10743 (vqrdmulhq_s32): Likewise.
10744 (vqrdmulhq_n_s32): Likewise.
10745 (vqdmulhq_s32): Likewise.
10746 (vqdmulhq_n_s32): Likewise.
10747 (vqaddq_s32): Likewise.
10748 (vqaddq_n_s32): Likewise.
10749 (vorrq_s32): Likewise.
10750 (vornq_s32): Likewise.
10751 (vmulq_s32): Likewise.
10752 (vmulq_n_s32): Likewise.
10753 (vmulltq_int_s32): Likewise.
10754 (vmullbq_int_s32): Likewise.
10755 (vmulhq_s32): Likewise.
10756 (vmlsdavxq_s32): Likewise.
10757 (vmlsdavq_s32): Likewise.
10758 (vmladavxq_s32): Likewise.
10759 (vmladavq_s32): Likewise.
10760 (vminvq_s32): Likewise.
10761 (vminq_s32): Likewise.
10762 (vmaxvq_s32): Likewise.
10763 (vmaxq_s32): Likewise.
10764 (vhsubq_s32): Likewise.
10765 (vhsubq_n_s32): Likewise.
10766 (vhcaddq_rot90_s32): Likewise.
10767 (vhcaddq_rot270_s32): Likewise.
10768 (vhaddq_s32): Likewise.
10769 (vhaddq_n_s32): Likewise.
10770 (veorq_s32): Likewise.
10771 (vcaddq_rot90_s32): Likewise.
10772 (vcaddq_rot270_s32): Likewise.
10773 (vbrsrq_n_s32): Likewise.
10774 (vbicq_s32): Likewise.
10775 (vandq_s32): Likewise.
10776 (vaddvaq_s32): Likewise.
10777 (vaddq_n_s32): Likewise.
10778 (vabdq_s32): Likewise.
10779 (vshlq_n_s32): Likewise.
10780 (vrshrq_n_s32): Likewise.
10781 (vqshlq_n_s32): Likewise.
10782 (__arm_vsubq_u8): Define intrinsic.
10783 (__arm_vsubq_n_u8): Likewise.
10784 (__arm_vrmulhq_u8): Likewise.
10785 (__arm_vrhaddq_u8): Likewise.
10786 (__arm_vqsubq_u8): Likewise.
10787 (__arm_vqsubq_n_u8): Likewise.
10788 (__arm_vqaddq_u8): Likewise.
10789 (__arm_vqaddq_n_u8): Likewise.
10790 (__arm_vorrq_u8): Likewise.
10791 (__arm_vornq_u8): Likewise.
10792 (__arm_vmulq_u8): Likewise.
10793 (__arm_vmulq_n_u8): Likewise.
10794 (__arm_vmulltq_int_u8): Likewise.
10795 (__arm_vmullbq_int_u8): Likewise.
10796 (__arm_vmulhq_u8): Likewise.
10797 (__arm_vmladavq_u8): Likewise.
10798 (__arm_vminvq_u8): Likewise.
10799 (__arm_vminq_u8): Likewise.
10800 (__arm_vmaxvq_u8): Likewise.
10801 (__arm_vmaxq_u8): Likewise.
10802 (__arm_vhsubq_u8): Likewise.
10803 (__arm_vhsubq_n_u8): Likewise.
10804 (__arm_vhaddq_u8): Likewise.
10805 (__arm_vhaddq_n_u8): Likewise.
10806 (__arm_veorq_u8): Likewise.
10807 (__arm_vcmpneq_n_u8): Likewise.
10808 (__arm_vcmphiq_u8): Likewise.
10809 (__arm_vcmphiq_n_u8): Likewise.
10810 (__arm_vcmpeqq_u8): Likewise.
10811 (__arm_vcmpeqq_n_u8): Likewise.
10812 (__arm_vcmpcsq_u8): Likewise.
10813 (__arm_vcmpcsq_n_u8): Likewise.
10814 (__arm_vcaddq_rot90_u8): Likewise.
10815 (__arm_vcaddq_rot270_u8): Likewise.
10816 (__arm_vbicq_u8): Likewise.
10817 (__arm_vandq_u8): Likewise.
10818 (__arm_vaddvq_p_u8): Likewise.
10819 (__arm_vaddvaq_u8): Likewise.
10820 (__arm_vaddq_n_u8): Likewise.
10821 (__arm_vabdq_u8): Likewise.
10822 (__arm_vshlq_r_u8): Likewise.
10823 (__arm_vrshlq_u8): Likewise.
10824 (__arm_vrshlq_n_u8): Likewise.
10825 (__arm_vqshlq_u8): Likewise.
10826 (__arm_vqshlq_r_u8): Likewise.
10827 (__arm_vqrshlq_u8): Likewise.
10828 (__arm_vqrshlq_n_u8): Likewise.
10829 (__arm_vminavq_s8): Likewise.
10830 (__arm_vminaq_s8): Likewise.
10831 (__arm_vmaxavq_s8): Likewise.
10832 (__arm_vmaxaq_s8): Likewise.
10833 (__arm_vbrsrq_n_u8): Likewise.
10834 (__arm_vshlq_n_u8): Likewise.
10835 (__arm_vrshrq_n_u8): Likewise.
10836 (__arm_vqshlq_n_u8): Likewise.
10837 (__arm_vcmpneq_n_s8): Likewise.
10838 (__arm_vcmpltq_s8): Likewise.
10839 (__arm_vcmpltq_n_s8): Likewise.
10840 (__arm_vcmpleq_s8): Likewise.
10841 (__arm_vcmpleq_n_s8): Likewise.
10842 (__arm_vcmpgtq_s8): Likewise.
10843 (__arm_vcmpgtq_n_s8): Likewise.
10844 (__arm_vcmpgeq_s8): Likewise.
10845 (__arm_vcmpgeq_n_s8): Likewise.
10846 (__arm_vcmpeqq_s8): Likewise.
10847 (__arm_vcmpeqq_n_s8): Likewise.
10848 (__arm_vqshluq_n_s8): Likewise.
10849 (__arm_vaddvq_p_s8): Likewise.
10850 (__arm_vsubq_s8): Likewise.
10851 (__arm_vsubq_n_s8): Likewise.
10852 (__arm_vshlq_r_s8): Likewise.
10853 (__arm_vrshlq_s8): Likewise.
10854 (__arm_vrshlq_n_s8): Likewise.
10855 (__arm_vrmulhq_s8): Likewise.
10856 (__arm_vrhaddq_s8): Likewise.
10857 (__arm_vqsubq_s8): Likewise.
10858 (__arm_vqsubq_n_s8): Likewise.
10859 (__arm_vqshlq_s8): Likewise.
10860 (__arm_vqshlq_r_s8): Likewise.
10861 (__arm_vqrshlq_s8): Likewise.
10862 (__arm_vqrshlq_n_s8): Likewise.
10863 (__arm_vqrdmulhq_s8): Likewise.
10864 (__arm_vqrdmulhq_n_s8): Likewise.
10865 (__arm_vqdmulhq_s8): Likewise.
10866 (__arm_vqdmulhq_n_s8): Likewise.
10867 (__arm_vqaddq_s8): Likewise.
10868 (__arm_vqaddq_n_s8): Likewise.
10869 (__arm_vorrq_s8): Likewise.
10870 (__arm_vornq_s8): Likewise.
10871 (__arm_vmulq_s8): Likewise.
10872 (__arm_vmulq_n_s8): Likewise.
10873 (__arm_vmulltq_int_s8): Likewise.
10874 (__arm_vmullbq_int_s8): Likewise.
10875 (__arm_vmulhq_s8): Likewise.
10876 (__arm_vmlsdavxq_s8): Likewise.
10877 (__arm_vmlsdavq_s8): Likewise.
10878 (__arm_vmladavxq_s8): Likewise.
10879 (__arm_vmladavq_s8): Likewise.
10880 (__arm_vminvq_s8): Likewise.
10881 (__arm_vminq_s8): Likewise.
10882 (__arm_vmaxvq_s8): Likewise.
10883 (__arm_vmaxq_s8): Likewise.
10884 (__arm_vhsubq_s8): Likewise.
10885 (__arm_vhsubq_n_s8): Likewise.
10886 (__arm_vhcaddq_rot90_s8): Likewise.
10887 (__arm_vhcaddq_rot270_s8): Likewise.
10888 (__arm_vhaddq_s8): Likewise.
10889 (__arm_vhaddq_n_s8): Likewise.
10890 (__arm_veorq_s8): Likewise.
10891 (__arm_vcaddq_rot90_s8): Likewise.
10892 (__arm_vcaddq_rot270_s8): Likewise.
10893 (__arm_vbrsrq_n_s8): Likewise.
10894 (__arm_vbicq_s8): Likewise.
10895 (__arm_vandq_s8): Likewise.
10896 (__arm_vaddvaq_s8): Likewise.
10897 (__arm_vaddq_n_s8): Likewise.
10898 (__arm_vabdq_s8): Likewise.
10899 (__arm_vshlq_n_s8): Likewise.
10900 (__arm_vrshrq_n_s8): Likewise.
10901 (__arm_vqshlq_n_s8): Likewise.
10902 (__arm_vsubq_u16): Likewise.
10903 (__arm_vsubq_n_u16): Likewise.
10904 (__arm_vrmulhq_u16): Likewise.
10905 (__arm_vrhaddq_u16): Likewise.
10906 (__arm_vqsubq_u16): Likewise.
10907 (__arm_vqsubq_n_u16): Likewise.
10908 (__arm_vqaddq_u16): Likewise.
10909 (__arm_vqaddq_n_u16): Likewise.
10910 (__arm_vorrq_u16): Likewise.
10911 (__arm_vornq_u16): Likewise.
10912 (__arm_vmulq_u16): Likewise.
10913 (__arm_vmulq_n_u16): Likewise.
10914 (__arm_vmulltq_int_u16): Likewise.
10915 (__arm_vmullbq_int_u16): Likewise.
10916 (__arm_vmulhq_u16): Likewise.
10917 (__arm_vmladavq_u16): Likewise.
10918 (__arm_vminvq_u16): Likewise.
10919 (__arm_vminq_u16): Likewise.
10920 (__arm_vmaxvq_u16): Likewise.
10921 (__arm_vmaxq_u16): Likewise.
10922 (__arm_vhsubq_u16): Likewise.
10923 (__arm_vhsubq_n_u16): Likewise.
10924 (__arm_vhaddq_u16): Likewise.
10925 (__arm_vhaddq_n_u16): Likewise.
10926 (__arm_veorq_u16): Likewise.
10927 (__arm_vcmpneq_n_u16): Likewise.
10928 (__arm_vcmphiq_u16): Likewise.
10929 (__arm_vcmphiq_n_u16): Likewise.
10930 (__arm_vcmpeqq_u16): Likewise.
10931 (__arm_vcmpeqq_n_u16): Likewise.
10932 (__arm_vcmpcsq_u16): Likewise.
10933 (__arm_vcmpcsq_n_u16): Likewise.
10934 (__arm_vcaddq_rot90_u16): Likewise.
10935 (__arm_vcaddq_rot270_u16): Likewise.
10936 (__arm_vbicq_u16): Likewise.
10937 (__arm_vandq_u16): Likewise.
10938 (__arm_vaddvq_p_u16): Likewise.
10939 (__arm_vaddvaq_u16): Likewise.
10940 (__arm_vaddq_n_u16): Likewise.
10941 (__arm_vabdq_u16): Likewise.
10942 (__arm_vshlq_r_u16): Likewise.
10943 (__arm_vrshlq_u16): Likewise.
10944 (__arm_vrshlq_n_u16): Likewise.
10945 (__arm_vqshlq_u16): Likewise.
10946 (__arm_vqshlq_r_u16): Likewise.
10947 (__arm_vqrshlq_u16): Likewise.
10948 (__arm_vqrshlq_n_u16): Likewise.
10949 (__arm_vminavq_s16): Likewise.
10950 (__arm_vminaq_s16): Likewise.
10951 (__arm_vmaxavq_s16): Likewise.
10952 (__arm_vmaxaq_s16): Likewise.
10953 (__arm_vbrsrq_n_u16): Likewise.
10954 (__arm_vshlq_n_u16): Likewise.
10955 (__arm_vrshrq_n_u16): Likewise.
10956 (__arm_vqshlq_n_u16): Likewise.
10957 (__arm_vcmpneq_n_s16): Likewise.
10958 (__arm_vcmpltq_s16): Likewise.
10959 (__arm_vcmpltq_n_s16): Likewise.
10960 (__arm_vcmpleq_s16): Likewise.
10961 (__arm_vcmpleq_n_s16): Likewise.
10962 (__arm_vcmpgtq_s16): Likewise.
10963 (__arm_vcmpgtq_n_s16): Likewise.
10964 (__arm_vcmpgeq_s16): Likewise.
10965 (__arm_vcmpgeq_n_s16): Likewise.
10966 (__arm_vcmpeqq_s16): Likewise.
10967 (__arm_vcmpeqq_n_s16): Likewise.
10968 (__arm_vqshluq_n_s16): Likewise.
10969 (__arm_vaddvq_p_s16): Likewise.
10970 (__arm_vsubq_s16): Likewise.
10971 (__arm_vsubq_n_s16): Likewise.
10972 (__arm_vshlq_r_s16): Likewise.
10973 (__arm_vrshlq_s16): Likewise.
10974 (__arm_vrshlq_n_s16): Likewise.
10975 (__arm_vrmulhq_s16): Likewise.
10976 (__arm_vrhaddq_s16): Likewise.
10977 (__arm_vqsubq_s16): Likewise.
10978 (__arm_vqsubq_n_s16): Likewise.
10979 (__arm_vqshlq_s16): Likewise.
10980 (__arm_vqshlq_r_s16): Likewise.
10981 (__arm_vqrshlq_s16): Likewise.
10982 (__arm_vqrshlq_n_s16): Likewise.
10983 (__arm_vqrdmulhq_s16): Likewise.
10984 (__arm_vqrdmulhq_n_s16): Likewise.
10985 (__arm_vqdmulhq_s16): Likewise.
10986 (__arm_vqdmulhq_n_s16): Likewise.
10987 (__arm_vqaddq_s16): Likewise.
10988 (__arm_vqaddq_n_s16): Likewise.
10989 (__arm_vorrq_s16): Likewise.
10990 (__arm_vornq_s16): Likewise.
10991 (__arm_vmulq_s16): Likewise.
10992 (__arm_vmulq_n_s16): Likewise.
10993 (__arm_vmulltq_int_s16): Likewise.
10994 (__arm_vmullbq_int_s16): Likewise.
10995 (__arm_vmulhq_s16): Likewise.
10996 (__arm_vmlsdavxq_s16): Likewise.
10997 (__arm_vmlsdavq_s16): Likewise.
10998 (__arm_vmladavxq_s16): Likewise.
10999 (__arm_vmladavq_s16): Likewise.
11000 (__arm_vminvq_s16): Likewise.
11001 (__arm_vminq_s16): Likewise.
11002 (__arm_vmaxvq_s16): Likewise.
11003 (__arm_vmaxq_s16): Likewise.
11004 (__arm_vhsubq_s16): Likewise.
11005 (__arm_vhsubq_n_s16): Likewise.
11006 (__arm_vhcaddq_rot90_s16): Likewise.
11007 (__arm_vhcaddq_rot270_s16): Likewise.
11008 (__arm_vhaddq_s16): Likewise.
11009 (__arm_vhaddq_n_s16): Likewise.
11010 (__arm_veorq_s16): Likewise.
11011 (__arm_vcaddq_rot90_s16): Likewise.
11012 (__arm_vcaddq_rot270_s16): Likewise.
11013 (__arm_vbrsrq_n_s16): Likewise.
11014 (__arm_vbicq_s16): Likewise.
11015 (__arm_vandq_s16): Likewise.
11016 (__arm_vaddvaq_s16): Likewise.
11017 (__arm_vaddq_n_s16): Likewise.
11018 (__arm_vabdq_s16): Likewise.
11019 (__arm_vshlq_n_s16): Likewise.
11020 (__arm_vrshrq_n_s16): Likewise.
11021 (__arm_vqshlq_n_s16): Likewise.
11022 (__arm_vsubq_u32): Likewise.
11023 (__arm_vsubq_n_u32): Likewise.
11024 (__arm_vrmulhq_u32): Likewise.
11025 (__arm_vrhaddq_u32): Likewise.
11026 (__arm_vqsubq_u32): Likewise.
11027 (__arm_vqsubq_n_u32): Likewise.
11028 (__arm_vqaddq_u32): Likewise.
11029 (__arm_vqaddq_n_u32): Likewise.
11030 (__arm_vorrq_u32): Likewise.
11031 (__arm_vornq_u32): Likewise.
11032 (__arm_vmulq_u32): Likewise.
11033 (__arm_vmulq_n_u32): Likewise.
11034 (__arm_vmulltq_int_u32): Likewise.
11035 (__arm_vmullbq_int_u32): Likewise.
11036 (__arm_vmulhq_u32): Likewise.
11037 (__arm_vmladavq_u32): Likewise.
11038 (__arm_vminvq_u32): Likewise.
11039 (__arm_vminq_u32): Likewise.
11040 (__arm_vmaxvq_u32): Likewise.
11041 (__arm_vmaxq_u32): Likewise.
11042 (__arm_vhsubq_u32): Likewise.
11043 (__arm_vhsubq_n_u32): Likewise.
11044 (__arm_vhaddq_u32): Likewise.
11045 (__arm_vhaddq_n_u32): Likewise.
11046 (__arm_veorq_u32): Likewise.
11047 (__arm_vcmpneq_n_u32): Likewise.
11048 (__arm_vcmphiq_u32): Likewise.
11049 (__arm_vcmphiq_n_u32): Likewise.
11050 (__arm_vcmpeqq_u32): Likewise.
11051 (__arm_vcmpeqq_n_u32): Likewise.
11052 (__arm_vcmpcsq_u32): Likewise.
11053 (__arm_vcmpcsq_n_u32): Likewise.
11054 (__arm_vcaddq_rot90_u32): Likewise.
11055 (__arm_vcaddq_rot270_u32): Likewise.
11056 (__arm_vbicq_u32): Likewise.
11057 (__arm_vandq_u32): Likewise.
11058 (__arm_vaddvq_p_u32): Likewise.
11059 (__arm_vaddvaq_u32): Likewise.
11060 (__arm_vaddq_n_u32): Likewise.
11061 (__arm_vabdq_u32): Likewise.
11062 (__arm_vshlq_r_u32): Likewise.
11063 (__arm_vrshlq_u32): Likewise.
11064 (__arm_vrshlq_n_u32): Likewise.
11065 (__arm_vqshlq_u32): Likewise.
11066 (__arm_vqshlq_r_u32): Likewise.
11067 (__arm_vqrshlq_u32): Likewise.
11068 (__arm_vqrshlq_n_u32): Likewise.
11069 (__arm_vminavq_s32): Likewise.
11070 (__arm_vminaq_s32): Likewise.
11071 (__arm_vmaxavq_s32): Likewise.
11072 (__arm_vmaxaq_s32): Likewise.
11073 (__arm_vbrsrq_n_u32): Likewise.
11074 (__arm_vshlq_n_u32): Likewise.
11075 (__arm_vrshrq_n_u32): Likewise.
11076 (__arm_vqshlq_n_u32): Likewise.
11077 (__arm_vcmpneq_n_s32): Likewise.
11078 (__arm_vcmpltq_s32): Likewise.
11079 (__arm_vcmpltq_n_s32): Likewise.
11080 (__arm_vcmpleq_s32): Likewise.
11081 (__arm_vcmpleq_n_s32): Likewise.
11082 (__arm_vcmpgtq_s32): Likewise.
11083 (__arm_vcmpgtq_n_s32): Likewise.
11084 (__arm_vcmpgeq_s32): Likewise.
11085 (__arm_vcmpgeq_n_s32): Likewise.
11086 (__arm_vcmpeqq_s32): Likewise.
11087 (__arm_vcmpeqq_n_s32): Likewise.
11088 (__arm_vqshluq_n_s32): Likewise.
11089 (__arm_vaddvq_p_s32): Likewise.
11090 (__arm_vsubq_s32): Likewise.
11091 (__arm_vsubq_n_s32): Likewise.
11092 (__arm_vshlq_r_s32): Likewise.
11093 (__arm_vrshlq_s32): Likewise.
11094 (__arm_vrshlq_n_s32): Likewise.
11095 (__arm_vrmulhq_s32): Likewise.
11096 (__arm_vrhaddq_s32): Likewise.
11097 (__arm_vqsubq_s32): Likewise.
11098 (__arm_vqsubq_n_s32): Likewise.
11099 (__arm_vqshlq_s32): Likewise.
11100 (__arm_vqshlq_r_s32): Likewise.
11101 (__arm_vqrshlq_s32): Likewise.
11102 (__arm_vqrshlq_n_s32): Likewise.
11103 (__arm_vqrdmulhq_s32): Likewise.
11104 (__arm_vqrdmulhq_n_s32): Likewise.
11105 (__arm_vqdmulhq_s32): Likewise.
11106 (__arm_vqdmulhq_n_s32): Likewise.
11107 (__arm_vqaddq_s32): Likewise.
11108 (__arm_vqaddq_n_s32): Likewise.
11109 (__arm_vorrq_s32): Likewise.
11110 (__arm_vornq_s32): Likewise.
11111 (__arm_vmulq_s32): Likewise.
11112 (__arm_vmulq_n_s32): Likewise.
11113 (__arm_vmulltq_int_s32): Likewise.
11114 (__arm_vmullbq_int_s32): Likewise.
11115 (__arm_vmulhq_s32): Likewise.
11116 (__arm_vmlsdavxq_s32): Likewise.
11117 (__arm_vmlsdavq_s32): Likewise.
11118 (__arm_vmladavxq_s32): Likewise.
11119 (__arm_vmladavq_s32): Likewise.
11120 (__arm_vminvq_s32): Likewise.
11121 (__arm_vminq_s32): Likewise.
11122 (__arm_vmaxvq_s32): Likewise.
11123 (__arm_vmaxq_s32): Likewise.
11124 (__arm_vhsubq_s32): Likewise.
11125 (__arm_vhsubq_n_s32): Likewise.
11126 (__arm_vhcaddq_rot90_s32): Likewise.
11127 (__arm_vhcaddq_rot270_s32): Likewise.
11128 (__arm_vhaddq_s32): Likewise.
11129 (__arm_vhaddq_n_s32): Likewise.
11130 (__arm_veorq_s32): Likewise.
11131 (__arm_vcaddq_rot90_s32): Likewise.
11132 (__arm_vcaddq_rot270_s32): Likewise.
11133 (__arm_vbrsrq_n_s32): Likewise.
11134 (__arm_vbicq_s32): Likewise.
11135 (__arm_vandq_s32): Likewise.
11136 (__arm_vaddvaq_s32): Likewise.
11137 (__arm_vaddq_n_s32): Likewise.
11138 (__arm_vabdq_s32): Likewise.
11139 (__arm_vshlq_n_s32): Likewise.
11140 (__arm_vrshrq_n_s32): Likewise.
11141 (__arm_vqshlq_n_s32): Likewise.
11142 (vsubq): Define polymorphic variant.
11143 (vsubq_n): Likewise.
11144 (vshlq_r): Likewise.
11145 (vrshlq_n): Likewise.
11146 (vrshlq): Likewise.
11147 (vrmulhq): Likewise.
11148 (vrhaddq): Likewise.
11149 (vqsubq_n): Likewise.
11150 (vqsubq): Likewise.
11151 (vqshlq): Likewise.
11152 (vqshlq_r): Likewise.
11153 (vqshluq): Likewise.
11154 (vrshrq_n): Likewise.
11155 (vshlq_n): Likewise.
11156 (vqshluq_n): Likewise.
11157 (vqshlq_n): Likewise.
11158 (vqrshlq_n): Likewise.
11159 (vqrshlq): Likewise.
11160 (vqrdmulhq_n): Likewise.
11161 (vqrdmulhq): Likewise.
11162 (vqdmulhq_n): Likewise.
11163 (vqdmulhq): Likewise.
11164 (vqaddq_n): Likewise.
11165 (vqaddq): Likewise.
11166 (vorrq_n): Likewise.
11169 (vmulq_n): Likewise.
11171 (vmulltq_int): Likewise.
11172 (vmullbq_int): Likewise.
11173 (vmulhq): Likewise.
11175 (vminaq): Likewise.
11177 (vmaxaq): Likewise.
11178 (vhsubq_n): Likewise.
11179 (vhsubq): Likewise.
11180 (vhcaddq_rot90): Likewise.
11181 (vhcaddq_rot270): Likewise.
11182 (vhaddq_n): Likewise.
11183 (vhaddq): Likewise.
11185 (vcaddq_rot90): Likewise.
11186 (vcaddq_rot270): Likewise.
11187 (vbrsrq_n): Likewise.
11188 (vbicq_n): Likewise.
11191 (vaddq_n): Likewise.
11194 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
11195 (BINOP_NONE_NONE_NONE): Likewise.
11196 (BINOP_NONE_NONE_UNONE): Likewise.
11197 (BINOP_UNONE_NONE_IMM): Likewise.
11198 (BINOP_UNONE_NONE_NONE): Likewise.
11199 (BINOP_UNONE_UNONE_IMM): Likewise.
11200 (BINOP_UNONE_UNONE_NONE): Likewise.
11201 (BINOP_UNONE_UNONE_UNONE): Likewise.
11202 * config/arm/constraints.md (Ra): Define constraint to check constant is
11203 in the range of 0 to 7.
11204 (Rg): Define constriant to check the constant is one among 1, 2, 4
11206 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
11207 (mve_vaddq_n_<supf>): Likewise.
11208 (mve_vaddvaq_<supf>): Likewise.
11209 (mve_vaddvq_p_<supf>): Likewise.
11210 (mve_vandq_<supf>): Likewise.
11211 (mve_vbicq_<supf>): Likewise.
11212 (mve_vbrsrq_n_<supf>): Likewise.
11213 (mve_vcaddq_rot270_<supf>): Likewise.
11214 (mve_vcaddq_rot90_<supf>): Likewise.
11215 (mve_vcmpcsq_n_u): Likewise.
11216 (mve_vcmpcsq_u): Likewise.
11217 (mve_vcmpeqq_n_<supf>): Likewise.
11218 (mve_vcmpeqq_<supf>): Likewise.
11219 (mve_vcmpgeq_n_s): Likewise.
11220 (mve_vcmpgeq_s): Likewise.
11221 (mve_vcmpgtq_n_s): Likewise.
11222 (mve_vcmpgtq_s): Likewise.
11223 (mve_vcmphiq_n_u): Likewise.
11224 (mve_vcmphiq_u): Likewise.
11225 (mve_vcmpleq_n_s): Likewise.
11226 (mve_vcmpleq_s): Likewise.
11227 (mve_vcmpltq_n_s): Likewise.
11228 (mve_vcmpltq_s): Likewise.
11229 (mve_vcmpneq_n_<supf>): Likewise.
11230 (mve_vddupq_n_u): Likewise.
11231 (mve_veorq_<supf>): Likewise.
11232 (mve_vhaddq_n_<supf>): Likewise.
11233 (mve_vhaddq_<supf>): Likewise.
11234 (mve_vhcaddq_rot270_s): Likewise.
11235 (mve_vhcaddq_rot90_s): Likewise.
11236 (mve_vhsubq_n_<supf>): Likewise.
11237 (mve_vhsubq_<supf>): Likewise.
11238 (mve_vidupq_n_u): Likewise.
11239 (mve_vmaxaq_s): Likewise.
11240 (mve_vmaxavq_s): Likewise.
11241 (mve_vmaxq_<supf>): Likewise.
11242 (mve_vmaxvq_<supf>): Likewise.
11243 (mve_vminaq_s): Likewise.
11244 (mve_vminavq_s): Likewise.
11245 (mve_vminq_<supf>): Likewise.
11246 (mve_vminvq_<supf>): Likewise.
11247 (mve_vmladavq_<supf>): Likewise.
11248 (mve_vmladavxq_s): Likewise.
11249 (mve_vmlsdavq_s): Likewise.
11250 (mve_vmlsdavxq_s): Likewise.
11251 (mve_vmulhq_<supf>): Likewise.
11252 (mve_vmullbq_int_<supf>): Likewise.
11253 (mve_vmulltq_int_<supf>): Likewise.
11254 (mve_vmulq_n_<supf>): Likewise.
11255 (mve_vmulq_<supf>): Likewise.
11256 (mve_vornq_<supf>): Likewise.
11257 (mve_vorrq_<supf>): Likewise.
11258 (mve_vqaddq_n_<supf>): Likewise.
11259 (mve_vqaddq_<supf>): Likewise.
11260 (mve_vqdmulhq_n_s): Likewise.
11261 (mve_vqdmulhq_s): Likewise.
11262 (mve_vqrdmulhq_n_s): Likewise.
11263 (mve_vqrdmulhq_s): Likewise.
11264 (mve_vqrshlq_n_<supf>): Likewise.
11265 (mve_vqrshlq_<supf>): Likewise.
11266 (mve_vqshlq_n_<supf>): Likewise.
11267 (mve_vqshlq_r_<supf>): Likewise.
11268 (mve_vqshlq_<supf>): Likewise.
11269 (mve_vqshluq_n_s): Likewise.
11270 (mve_vqsubq_n_<supf>): Likewise.
11271 (mve_vqsubq_<supf>): Likewise.
11272 (mve_vrhaddq_<supf>): Likewise.
11273 (mve_vrmulhq_<supf>): Likewise.
11274 (mve_vrshlq_n_<supf>): Likewise.
11275 (mve_vrshlq_<supf>): Likewise.
11276 (mve_vrshrq_n_<supf>): Likewise.
11277 (mve_vshlq_n_<supf>): Likewise.
11278 (mve_vshlq_r_<supf>): Likewise.
11279 (mve_vsubq_n_<supf>): Likewise.
11280 (mve_vsubq_<supf>): Likewise.
11281 * config/arm/predicates.md (mve_imm_7): Define predicate to check
11282 the matching constraint Ra.
11283 (mve_imm_selective_upto_8): Define predicate to check the matching
11286 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11287 Mihail Ionescu <mihail.ionescu@arm.com>
11288 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11290 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
11291 qualifier for binary operands.
11292 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11293 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11294 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
11295 (vaddlvq_p_u32): Likewise.
11296 (vcmpneq_s8): Likewise.
11297 (vcmpneq_s16): Likewise.
11298 (vcmpneq_s32): Likewise.
11299 (vcmpneq_u8): Likewise.
11300 (vcmpneq_u16): Likewise.
11301 (vcmpneq_u32): Likewise.
11302 (vshlq_s8): Likewise.
11303 (vshlq_s16): Likewise.
11304 (vshlq_s32): Likewise.
11305 (vshlq_u8): Likewise.
11306 (vshlq_u16): Likewise.
11307 (vshlq_u32): Likewise.
11308 (__arm_vaddlvq_p_s32): Define intrinsic.
11309 (__arm_vaddlvq_p_u32): Likewise.
11310 (__arm_vcmpneq_s8): Likewise.
11311 (__arm_vcmpneq_s16): Likewise.
11312 (__arm_vcmpneq_s32): Likewise.
11313 (__arm_vcmpneq_u8): Likewise.
11314 (__arm_vcmpneq_u16): Likewise.
11315 (__arm_vcmpneq_u32): Likewise.
11316 (__arm_vshlq_s8): Likewise.
11317 (__arm_vshlq_s16): Likewise.
11318 (__arm_vshlq_s32): Likewise.
11319 (__arm_vshlq_u8): Likewise.
11320 (__arm_vshlq_u16): Likewise.
11321 (__arm_vshlq_u32): Likewise.
11322 (vaddlvq_p): Define polymorphic variant.
11323 (vcmpneq): Likewise.
11325 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
11327 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11328 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11329 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
11330 (mve_vcmpneq_<supf><mode>): Likewise.
11331 (mve_vshlq_<supf><mode>): Likewise.
11333 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11334 Mihail Ionescu <mihail.ionescu@arm.com>
11335 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11337 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
11338 qualifier for binary operands.
11339 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11340 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11341 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
11342 (vcvtq_n_s32_f32): Likewise.
11343 (vcvtq_n_u16_f16): Likewise.
11344 (vcvtq_n_u32_f32): Likewise.
11345 (vcreateq_u8): Likewise.
11346 (vcreateq_u16): Likewise.
11347 (vcreateq_u32): Likewise.
11348 (vcreateq_u64): Likewise.
11349 (vcreateq_s8): Likewise.
11350 (vcreateq_s16): Likewise.
11351 (vcreateq_s32): Likewise.
11352 (vcreateq_s64): Likewise.
11353 (vshrq_n_s8): Likewise.
11354 (vshrq_n_s16): Likewise.
11355 (vshrq_n_s32): Likewise.
11356 (vshrq_n_u8): Likewise.
11357 (vshrq_n_u16): Likewise.
11358 (vshrq_n_u32): Likewise.
11359 (__arm_vcreateq_u8): Define intrinsic.
11360 (__arm_vcreateq_u16): Likewise.
11361 (__arm_vcreateq_u32): Likewise.
11362 (__arm_vcreateq_u64): Likewise.
11363 (__arm_vcreateq_s8): Likewise.
11364 (__arm_vcreateq_s16): Likewise.
11365 (__arm_vcreateq_s32): Likewise.
11366 (__arm_vcreateq_s64): Likewise.
11367 (__arm_vshrq_n_s8): Likewise.
11368 (__arm_vshrq_n_s16): Likewise.
11369 (__arm_vshrq_n_s32): Likewise.
11370 (__arm_vshrq_n_u8): Likewise.
11371 (__arm_vshrq_n_u16): Likewise.
11372 (__arm_vshrq_n_u32): Likewise.
11373 (__arm_vcvtq_n_s16_f16): Likewise.
11374 (__arm_vcvtq_n_s32_f32): Likewise.
11375 (__arm_vcvtq_n_u16_f16): Likewise.
11376 (__arm_vcvtq_n_u32_f32): Likewise.
11377 (vshrq_n): Define polymorphic variant.
11378 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
11380 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11381 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11382 * config/arm/constraints.md (Rb): Define constraint to check constant is
11383 in the range of 1 to 8.
11384 (Rf): Define constraint to check constant is in the range of 1 to 32.
11385 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
11386 (mve_vshrq_n_<supf><mode>): Likewise.
11387 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
11388 * config/arm/predicates.md (mve_imm_8): Define predicate to check
11389 the matching constraint Rb.
11390 (mve_imm_32): Define predicate to check the matching constraint Rf.
11392 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11393 Mihail Ionescu <mihail.ionescu@arm.com>
11394 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11396 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
11397 qualifier for binary operands.
11398 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11399 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11400 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11401 * config/arm/arm_mve.h (vsubq_n_f16): Define macro.
11402 (vsubq_n_f32): Likewise.
11403 (vbrsrq_n_f16): Likewise.
11404 (vbrsrq_n_f32): Likewise.
11405 (vcvtq_n_f16_s16): Likewise.
11406 (vcvtq_n_f32_s32): Likewise.
11407 (vcvtq_n_f16_u16): Likewise.
11408 (vcvtq_n_f32_u32): Likewise.
11409 (vcreateq_f16): Likewise.
11410 (vcreateq_f32): Likewise.
11411 (__arm_vsubq_n_f16): Define intrinsic.
11412 (__arm_vsubq_n_f32): Likewise.
11413 (__arm_vbrsrq_n_f16): Likewise.
11414 (__arm_vbrsrq_n_f32): Likewise.
11415 (__arm_vcvtq_n_f16_s16): Likewise.
11416 (__arm_vcvtq_n_f32_s32): Likewise.
11417 (__arm_vcvtq_n_f16_u16): Likewise.
11418 (__arm_vcvtq_n_f32_u32): Likewise.
11419 (__arm_vcreateq_f16): Likewise.
11420 (__arm_vcreateq_f32): Likewise.
11421 (vsubq): Define polymorphic variant.
11422 (vbrsrq): Likewise.
11423 (vcvtq_n): Likewise.
11424 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
11426 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11427 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11428 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11429 * config/arm/constraints.md (Rd): Define constraint to check constant is
11430 in the range of 1 to 16.
11431 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
11432 mve_vbrsrq_n_f<mode>: Likewise.
11433 mve_vcvtq_n_to_f_<supf><mode>: Likewise.
11434 mve_vcreateq_f<mode>: Likewise.
11435 * config/arm/predicates.md (mve_imm_16): Define predicate to check
11436 the matching constraint Rd.
11438 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11439 Mihail Ionescu <mihail.ionescu@arm.com>
11440 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11442 * config/arm/arm-builtins.c (hi_UP): Define mode.
11443 * config/arm/arm.h (IS_VPR_REGNUM): Move.
11444 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
11445 (APSRQ_REGNUM): Modify.
11446 (APSRGE_REGNUM): Modify.
11447 * config/arm/arm_mve.h (vctp16q): Define macro.
11448 (vctp32q): Likewise.
11449 (vctp64q): Likewise.
11450 (vctp8q): Likewise.
11452 (__arm_vctp16q): Define intrinsic.
11453 (__arm_vctp32q): Likewise.
11454 (__arm_vctp64q): Likewise.
11455 (__arm_vctp8q): Likewise.
11456 (__arm_vpnot): Likewise.
11457 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
11459 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
11460 (mve_vpnothi): Likewise.
11462 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11463 Mihail Ionescu <mihail.ionescu@arm.com>
11464 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11466 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
11467 * config/arm/arm_mve.h (vdupq_n_s8): Define macro.
11468 (vdupq_n_s16): Likewise.
11469 (vdupq_n_s32): Likewise.
11470 (vabsq_s8): Likewise.
11471 (vabsq_s16): Likewise.
11472 (vabsq_s32): Likewise.
11473 (vclsq_s8): Likewise.
11474 (vclsq_s16): Likewise.
11475 (vclsq_s32): Likewise.
11476 (vclzq_s8): Likewise.
11477 (vclzq_s16): Likewise.
11478 (vclzq_s32): Likewise.
11479 (vnegq_s8): Likewise.
11480 (vnegq_s16): Likewise.
11481 (vnegq_s32): Likewise.
11482 (vaddlvq_s32): Likewise.
11483 (vaddvq_s8): Likewise.
11484 (vaddvq_s16): Likewise.
11485 (vaddvq_s32): Likewise.
11486 (vmovlbq_s8): Likewise.
11487 (vmovlbq_s16): Likewise.
11488 (vmovltq_s8): Likewise.
11489 (vmovltq_s16): Likewise.
11490 (vmvnq_s8): Likewise.
11491 (vmvnq_s16): Likewise.
11492 (vmvnq_s32): Likewise.
11493 (vrev16q_s8): Likewise.
11494 (vrev32q_s8): Likewise.
11495 (vrev32q_s16): Likewise.
11496 (vqabsq_s8): Likewise.
11497 (vqabsq_s16): Likewise.
11498 (vqabsq_s32): Likewise.
11499 (vqnegq_s8): Likewise.
11500 (vqnegq_s16): Likewise.
11501 (vqnegq_s32): Likewise.
11502 (vcvtaq_s16_f16): Likewise.
11503 (vcvtaq_s32_f32): Likewise.
11504 (vcvtnq_s16_f16): Likewise.
11505 (vcvtnq_s32_f32): Likewise.
11506 (vcvtpq_s16_f16): Likewise.
11507 (vcvtpq_s32_f32): Likewise.
11508 (vcvtmq_s16_f16): Likewise.
11509 (vcvtmq_s32_f32): Likewise.
11510 (vmvnq_u8): Likewise.
11511 (vmvnq_u16): Likewise.
11512 (vmvnq_u32): Likewise.
11513 (vdupq_n_u8): Likewise.
11514 (vdupq_n_u16): Likewise.
11515 (vdupq_n_u32): Likewise.
11516 (vclzq_u8): Likewise.
11517 (vclzq_u16): Likewise.
11518 (vclzq_u32): Likewise.
11519 (vaddvq_u8): Likewise.
11520 (vaddvq_u16): Likewise.
11521 (vaddvq_u32): Likewise.
11522 (vrev32q_u8): Likewise.
11523 (vrev32q_u16): Likewise.
11524 (vmovltq_u8): Likewise.
11525 (vmovltq_u16): Likewise.
11526 (vmovlbq_u8): Likewise.
11527 (vmovlbq_u16): Likewise.
11528 (vrev16q_u8): Likewise.
11529 (vaddlvq_u32): Likewise.
11530 (vcvtpq_u16_f16): Likewise.
11531 (vcvtpq_u32_f32): Likewise.
11532 (vcvtnq_u16_f16): Likewise.
11533 (vcvtmq_u16_f16): Likewise.
11534 (vcvtmq_u32_f32): Likewise.
11535 (vcvtaq_u16_f16): Likewise.
11536 (vcvtaq_u32_f32): Likewise.
11537 (__arm_vdupq_n_s8): Define intrinsic.
11538 (__arm_vdupq_n_s16): Likewise.
11539 (__arm_vdupq_n_s32): Likewise.
11540 (__arm_vabsq_s8): Likewise.
11541 (__arm_vabsq_s16): Likewise.
11542 (__arm_vabsq_s32): Likewise.
11543 (__arm_vclsq_s8): Likewise.
11544 (__arm_vclsq_s16): Likewise.
11545 (__arm_vclsq_s32): Likewise.
11546 (__arm_vclzq_s8): Likewise.
11547 (__arm_vclzq_s16): Likewise.
11548 (__arm_vclzq_s32): Likewise.
11549 (__arm_vnegq_s8): Likewise.
11550 (__arm_vnegq_s16): Likewise.
11551 (__arm_vnegq_s32): Likewise.
11552 (__arm_vaddlvq_s32): Likewise.
11553 (__arm_vaddvq_s8): Likewise.
11554 (__arm_vaddvq_s16): Likewise.
11555 (__arm_vaddvq_s32): Likewise.
11556 (__arm_vmovlbq_s8): Likewise.
11557 (__arm_vmovlbq_s16): Likewise.
11558 (__arm_vmovltq_s8): Likewise.
11559 (__arm_vmovltq_s16): Likewise.
11560 (__arm_vmvnq_s8): Likewise.
11561 (__arm_vmvnq_s16): Likewise.
11562 (__arm_vmvnq_s32): Likewise.
11563 (__arm_vrev16q_s8): Likewise.
11564 (__arm_vrev32q_s8): Likewise.
11565 (__arm_vrev32q_s16): Likewise.
11566 (__arm_vqabsq_s8): Likewise.
11567 (__arm_vqabsq_s16): Likewise.
11568 (__arm_vqabsq_s32): Likewise.
11569 (__arm_vqnegq_s8): Likewise.
11570 (__arm_vqnegq_s16): Likewise.
11571 (__arm_vqnegq_s32): Likewise.
11572 (__arm_vmvnq_u8): Likewise.
11573 (__arm_vmvnq_u16): Likewise.
11574 (__arm_vmvnq_u32): Likewise.
11575 (__arm_vdupq_n_u8): Likewise.
11576 (__arm_vdupq_n_u16): Likewise.
11577 (__arm_vdupq_n_u32): Likewise.
11578 (__arm_vclzq_u8): Likewise.
11579 (__arm_vclzq_u16): Likewise.
11580 (__arm_vclzq_u32): Likewise.
11581 (__arm_vaddvq_u8): Likewise.
11582 (__arm_vaddvq_u16): Likewise.
11583 (__arm_vaddvq_u32): Likewise.
11584 (__arm_vrev32q_u8): Likewise.
11585 (__arm_vrev32q_u16): Likewise.
11586 (__arm_vmovltq_u8): Likewise.
11587 (__arm_vmovltq_u16): Likewise.
11588 (__arm_vmovlbq_u8): Likewise.
11589 (__arm_vmovlbq_u16): Likewise.
11590 (__arm_vrev16q_u8): Likewise.
11591 (__arm_vaddlvq_u32): Likewise.
11592 (__arm_vcvtpq_u16_f16): Likewise.
11593 (__arm_vcvtpq_u32_f32): Likewise.
11594 (__arm_vcvtnq_u16_f16): Likewise.
11595 (__arm_vcvtmq_u16_f16): Likewise.
11596 (__arm_vcvtmq_u32_f32): Likewise.
11597 (__arm_vcvtaq_u16_f16): Likewise.
11598 (__arm_vcvtaq_u32_f32): Likewise.
11599 (__arm_vcvtaq_s16_f16): Likewise.
11600 (__arm_vcvtaq_s32_f32): Likewise.
11601 (__arm_vcvtnq_s16_f16): Likewise.
11602 (__arm_vcvtnq_s32_f32): Likewise.
11603 (__arm_vcvtpq_s16_f16): Likewise.
11604 (__arm_vcvtpq_s32_f32): Likewise.
11605 (__arm_vcvtmq_s16_f16): Likewise.
11606 (__arm_vcvtmq_s32_f32): Likewise.
11607 (vdupq_n): Define polymorphic variant.
11612 (vaddlvq): Likewise.
11613 (vaddvq): Likewise.
11614 (vmovlbq): Likewise.
11615 (vmovltq): Likewise.
11617 (vrev16q): Likewise.
11618 (vrev32q): Likewise.
11619 (vqabsq): Likewise.
11620 (vqnegq): Likewise.
11621 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11622 (UNOP_SNONE_NONE): Likewise.
11623 (UNOP_UNONE_UNONE): Likewise.
11624 (UNOP_UNONE_NONE): Likewise.
11625 * config/arm/constraints.md (e): Define new constriant to allow only
11627 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
11628 (mve_vnegq_s<mode>): Likewise.
11629 (mve_vmvnq_<supf><mode>): Likewise.
11630 (mve_vdupq_n_<supf><mode>): Likewise.
11631 (mve_vclzq_<supf><mode>): Likewise.
11632 (mve_vclsq_s<mode>): Likewise.
11633 (mve_vaddvq_<supf><mode>): Likewise.
11634 (mve_vabsq_s<mode>): Likewise.
11635 (mve_vrev32q_<supf><mode>): Likewise.
11636 (mve_vmovltq_<supf><mode>): Likewise.
11637 (mve_vmovlbq_<supf><mode>): Likewise.
11638 (mve_vcvtpq_<supf><mode>): Likewise.
11639 (mve_vcvtnq_<supf><mode>): Likewise.
11640 (mve_vcvtmq_<supf><mode>): Likewise.
11641 (mve_vcvtaq_<supf><mode>): Likewise.
11642 (mve_vrev16q_<supf>v16qi): Likewise.
11643 (mve_vaddlvq_<supf>v4si): Likewise.
11645 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11647 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in
11649 * tree-sra.c (create_access_replacement): Fix up duplicated word issue
11651 * read-rtl-function.c (find_param_by_name,
11652 function_reader::parse_enum_value, function_reader::get_insn_by_uid):
11654 * spellcheck.c (get_edit_distance_cutoff): Likewise.
11655 * tree-data-ref.c (create_ifn_alias_checks): Likewise.
11656 * tree.def (SWITCH_EXPR): Likewise.
11657 * selftest.c (assert_str_contains): Likewise.
11658 * ipa-param-manipulation.h (class ipa_param_body_adjustments):
11660 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
11661 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
11662 * langhooks.h (struct lang_hooks_for_decls): Likewise.
11663 * ipa-prop.h (struct ipa_param_descriptor): Likewise.
11664 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
11666 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
11667 * tree-ssa-reassoc.c (reassociate_bb): Likewise.
11668 * tree.c (component_ref_size): Likewise.
11669 * hsa-common.c (hsa_init_compilation_unit_data): Likewise.
11670 * gimple-ssa-sprintf.c (get_string_length, format_string,
11671 format_directive): Likewise.
11672 * omp-grid.c (grid_process_kernel_body_copy): Likewise.
11673 * input.c (string_concat_db::get_string_concatenation,
11674 test_lexer_string_locations_ucn4): Likewise.
11675 * cfgexpand.c (pass_expand::execute): Likewise.
11676 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
11677 maybe_diag_overlap): Likewise.
11678 * rtl.c (RTX_CODE_HWINT_P_1): Likewise.
11679 * shrink-wrap.c (spread_components): Likewise.
11680 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
11682 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
11684 * dwarf2out.c (dwarf2out_early_finish): Likewise.
11685 * gimple-ssa-store-merging.c: Likewise.
11686 * ira-costs.c (record_operand_costs): Likewise.
11687 * tree-vect-loop.c (vectorizable_reduction): Likewise.
11688 * target.def (dispatch): Likewise.
11689 (validate_dims, gen_ccmp_first): Fix up duplicated word issue
11690 in documentation text.
11691 * doc/tm.texi: Regenerated.
11692 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
11693 duplicated word issue in a comment.
11694 * config/i386/i386.c (ix86_test_loading_unspec): Likewise.
11695 * config/i386/i386-features.c (remove_partial_avx_dependency):
11697 * config/msp430/msp430.c (msp430_select_section): Likewise.
11698 * config/gcn/gcn-run.c (load_image): Likewise.
11699 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
11700 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
11701 * config/aarch64/falkor-tag-collision-avoidance.c
11702 (single_dest_per_chain): Likewise.
11703 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
11704 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
11705 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
11706 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
11708 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
11709 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
11710 * config/rs6000/rs6000-logue.c
11711 (rs6000_emit_probe_stack_range_stack_clash): Likewise.
11712 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
11713 Fix various other issues in the comment.
11715 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
11717 * config/arm/t-rmprofile: create new multilib for
11718 armv8.1-m.main+mve hard float and reuse v8-m.main ones for
11721 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11723 PR tree-optimization/94015
11724 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
11725 function where EXP is address of the bytes being stored rather than
11726 the bytes themselves into count_nonzero_bytes_addr. Punt on zero
11727 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
11728 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before
11729 calling native_encode_expr if host or target doesn't have 8-bit
11730 chars. Formatting fixes.
11731 (count_nonzero_bytes_addr): New function.
11733 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11734 Mihail Ionescu <mihail.ionescu@arm.com>
11735 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11737 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
11738 (UNOP_SNONE_NONE_QUALIFIERS): Likewise.
11739 (UNOP_SNONE_IMM_QUALIFIERS): Likewise.
11740 (UNOP_UNONE_NONE_QUALIFIERS): Likewise.
11741 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
11742 (UNOP_UNONE_IMM_QUALIFIERS): Likewise.
11743 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
11744 (vmvnq_n_s32): Likewise.
11745 (vrev64q_s8): Likewise.
11746 (vrev64q_s16): Likewise.
11747 (vrev64q_s32): Likewise.
11748 (vcvtq_s16_f16): Likewise.
11749 (vcvtq_s32_f32): Likewise.
11750 (vrev64q_u8): Likewise.
11751 (vrev64q_u16): Likewise.
11752 (vrev64q_u32): Likewise.
11753 (vmvnq_n_u16): Likewise.
11754 (vmvnq_n_u32): Likewise.
11755 (vcvtq_u16_f16): Likewise.
11756 (vcvtq_u32_f32): Likewise.
11757 (__arm_vmvnq_n_s16): Define intrinsic.
11758 (__arm_vmvnq_n_s32): Likewise.
11759 (__arm_vrev64q_s8): Likewise.
11760 (__arm_vrev64q_s16): Likewise.
11761 (__arm_vrev64q_s32): Likewise.
11762 (__arm_vrev64q_u8): Likewise.
11763 (__arm_vrev64q_u16): Likewise.
11764 (__arm_vrev64q_u32): Likewise.
11765 (__arm_vmvnq_n_u16): Likewise.
11766 (__arm_vmvnq_n_u32): Likewise.
11767 (__arm_vcvtq_s16_f16): Likewise.
11768 (__arm_vcvtq_s32_f32): Likewise.
11769 (__arm_vcvtq_u16_f16): Likewise.
11770 (__arm_vcvtq_u32_f32): Likewise.
11771 (vrev64q): Define polymorphic variant.
11772 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11773 (UNOP_SNONE_NONE): Likewise.
11774 (UNOP_SNONE_IMM): Likewise.
11775 (UNOP_UNONE_UNONE): Likewise.
11776 (UNOP_UNONE_NONE): Likewise.
11777 (UNOP_UNONE_IMM): Likewise.
11778 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
11779 (mve_vcvtq_from_f_<supf><mode>): Likewise.
11780 (mve_vmvnq_n_<supf><mode>): Likewise.
11782 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11783 Mihail Ionescu <mihail.ionescu@arm.com>
11784 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11786 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
11787 (UNOP_NONE_SNONE_QUALIFIERS): Likewise.
11788 (UNOP_NONE_UNONE_QUALIFIERS): Likewise.
11789 * config/arm/arm_mve.h (vrndxq_f16): Define macro.
11790 (vrndxq_f32): Likewise.
11791 (vrndq_f16) Likewise.
11792 (vrndq_f32): Likewise.
11793 (vrndpq_f16): Likewise.
11794 (vrndpq_f32): Likewise.
11795 (vrndnq_f16): Likewise.
11796 (vrndnq_f32): Likewise.
11797 (vrndmq_f16): Likewise.
11798 (vrndmq_f32): Likewise.
11799 (vrndaq_f16): Likewise.
11800 (vrndaq_f32): Likewise.
11801 (vrev64q_f16): Likewise.
11802 (vrev64q_f32): Likewise.
11803 (vnegq_f16): Likewise.
11804 (vnegq_f32): Likewise.
11805 (vdupq_n_f16): Likewise.
11806 (vdupq_n_f32): Likewise.
11807 (vabsq_f16): Likewise.
11808 (vabsq_f32): Likewise.
11809 (vrev32q_f16): Likewise.
11810 (vcvttq_f32_f16): Likewise.
11811 (vcvtbq_f32_f16): Likewise.
11812 (vcvtq_f16_s16): Likewise.
11813 (vcvtq_f32_s32): Likewise.
11814 (vcvtq_f16_u16): Likewise.
11815 (vcvtq_f32_u32): Likewise.
11816 (__arm_vrndxq_f16): Define intrinsic.
11817 (__arm_vrndxq_f32): Likewise.
11818 (__arm_vrndq_f16): Likewise.
11819 (__arm_vrndq_f32): Likewise.
11820 (__arm_vrndpq_f16): Likewise.
11821 (__arm_vrndpq_f32): Likewise.
11822 (__arm_vrndnq_f16): Likewise.
11823 (__arm_vrndnq_f32): Likewise.
11824 (__arm_vrndmq_f16): Likewise.
11825 (__arm_vrndmq_f32): Likewise.
11826 (__arm_vrndaq_f16): Likewise.
11827 (__arm_vrndaq_f32): Likewise.
11828 (__arm_vrev64q_f16): Likewise.
11829 (__arm_vrev64q_f32): Likewise.
11830 (__arm_vnegq_f16): Likewise.
11831 (__arm_vnegq_f32): Likewise.
11832 (__arm_vdupq_n_f16): Likewise.
11833 (__arm_vdupq_n_f32): Likewise.
11834 (__arm_vabsq_f16): Likewise.
11835 (__arm_vabsq_f32): Likewise.
11836 (__arm_vrev32q_f16): Likewise.
11837 (__arm_vcvttq_f32_f16): Likewise.
11838 (__arm_vcvtbq_f32_f16): Likewise.
11839 (__arm_vcvtq_f16_s16): Likewise.
11840 (__arm_vcvtq_f32_s32): Likewise.
11841 (__arm_vcvtq_f16_u16): Likewise.
11842 (__arm_vcvtq_f32_u32): Likewise.
11843 (vrndxq): Define polymorphic variants.
11845 (vrndpq): Likewise.
11846 (vrndnq): Likewise.
11847 (vrndmq): Likewise.
11848 (vrndaq): Likewise.
11849 (vrev64q): Likewise.
11852 (vrev32q): Likewise.
11853 (vcvtbq_f32): Likewise.
11854 (vcvttq_f32): Likewise.
11856 * config/arm/arm_mve_builtins.def (VAR2): Define.
11858 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
11859 (mve_vrndq_f<mode>): Likewise.
11860 (mve_vrndpq_f<mode>): Likewise.
11861 (mve_vrndnq_f<mode>): Likewise.
11862 (mve_vrndmq_f<mode>): Likewise.
11863 (mve_vrndaq_f<mode>): Likewise.
11864 (mve_vrev64q_f<mode>): Likewise.
11865 (mve_vnegq_f<mode>): Likewise.
11866 (mve_vdupq_n_f<mode>): Likewise.
11867 (mve_vabsq_f<mode>): Likewise.
11868 (mve_vrev32q_fv8hf): Likewise.
11869 (mve_vcvttq_f32_f16v4sf): Likewise.
11870 (mve_vcvtbq_f32_f16v4sf): Likewise.
11871 (mve_vcvtq_to_f_<supf><mode>): Likewise.
11873 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11874 Mihail Ionescu <mihail.ionescu@arm.com>
11875 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11877 * config/arm/arm-builtins.c (CF): Define mve_builtin_data.
11879 (ARM_BUILTIN_MVE_PATTERN_START): Define.
11880 (arm_init_mve_builtins): Define function.
11881 (arm_init_builtins): Add TARGET_HAVE_MVE check.
11882 (arm_expand_builtin_1): Check the range of fcode.
11883 (arm_expand_mve_builtin): Define function to expand MVE builtins.
11884 (arm_expand_builtin): Check the range of fcode.
11885 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
11887 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
11888 (vst4q_s8): Define macro.
11889 (vst4q_s16): Likewise.
11890 (vst4q_s32): Likewise.
11891 (vst4q_u8): Likewise.
11892 (vst4q_u16): Likewise.
11893 (vst4q_u32): Likewise.
11894 (vst4q_f16): Likewise.
11895 (vst4q_f32): Likewise.
11896 (__arm_vst4q_s8): Define inline builtin.
11897 (__arm_vst4q_s16): Likewise.
11898 (__arm_vst4q_s32): Likewise.
11899 (__arm_vst4q_u8): Likewise.
11900 (__arm_vst4q_u16): Likewise.
11901 (__arm_vst4q_u32): Likewise.
11902 (__arm_vst4q_f16): Likewise.
11903 (__arm_vst4q_f32): Likewise.
11904 (__ARM_mve_typeid): Define macro with MVE types.
11905 (__ARM_mve_coerce): Define macro with _Generic feature.
11906 (vst4q): Define polymorphic variant for different vst4q builtins.
11907 * config/arm/arm_mve_builtins.def: New file.
11908 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
11910 * config/arm/mve.md (MVE_VLD_ST): Define iterator.
11911 (unspec): Define unspec.
11912 (mve_vst4q<mode>): Define RTL pattern.
11913 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
11915 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
11917 (define_split): Allow OI mode split for MVE after reload.
11918 (define_split): Allow XI mode split for MVE after reload.
11919 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
11920 (arm-builtins.o): Likewise.
11922 2020-03-17 Christophe Lyon <christophe.lyon@linaro.org>
11924 * c-typeck.c (process_init_element): Handle constructor_type with
11925 type size represented by POLY_INT_CST.
11927 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11929 PR tree-optimization/94187
11930 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if
11931 nchars - offset < nbytes.
11933 PR middle-end/94189
11934 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
11935 emit a warning if it was enabled and don't depend on TREE_NO_WARNING
11936 for code-generation.
11938 2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
11941 * lra-spills.c (remove_pseudos): Do not reuse insn alternative
11942 after changing memory subreg.
11944 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11945 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11947 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
11948 emulator calls for dobule precision arithmetic operations for MVE.
11950 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
11951 Mihail Ionescu <mihail.ionescu@arm.com>
11952 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11954 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
11955 feature bit is on and -mfpu=auto is passed as compiler option, do not
11956 generate error on not finding any matching fpu. Because in this case
11957 fpu is not required.
11958 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
11959 enabled for MVE and also for all VFP extensions.
11960 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
11962 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
11963 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
11964 along with feature bits mve_float.
11965 (mve): Modify add options in armv8.1-m.main arch for MVE.
11966 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with
11968 * config/arm/arm.c (use_return_insn): Replace the
11969 check with TARGET_VFP_BASE.
11970 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
11972 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
11973 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
11975 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
11976 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
11978 (arm_compute_frame_layout): Likewise.
11979 (arm_save_coproc_regs): Likewise.
11980 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
11982 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
11983 with equivalent macro TARGET_VFP_BASE.
11984 (arm_expand_epilogue_apcs_frame): Likewise.
11985 (arm_expand_epilogue): Likewise.
11986 (arm_conditional_register_usage): Likewise.
11987 (arm_declare_function_name): Add check to skip printing .fpu directive
11988 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
11990 * config/arm/arm.h (TARGET_VFP_BASE): Define.
11991 * config/arm/arm.md (arch): Add "mve" to arch.
11992 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
11993 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
11994 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
11995 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR
11997 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
11998 to not allow for MVE.
11999 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
12001 (VUNSPEC_GET_FPSCR): Define.
12002 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
12003 instructions which move to general-purpose Register from Floating-point
12004 Special register and vice-versa.
12005 (thumb2_movhi_fp16): Likewise.
12006 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
12007 with MCR and MRC instructions which set and get Floating-point Status
12008 and Control Register (FPSCR).
12009 (movdi_vfp): Modify pattern to enable Single-precision scalar float move
12011 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
12012 float move patterns in MVE.
12013 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
12014 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
12015 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
12016 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
12017 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
12018 TARGET_VFP_BASE check.
12019 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
12020 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
12022 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
12023 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
12027 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12028 Mihail Ionescu <mihail.ionescu@arm.com>
12029 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12031 * config.gcc (arm_mve.h): Include mve intrinsics header file.
12032 * config/arm/aout.h (p0): Add new register name for MVE predicated
12034 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
12035 common to Neon and MVE.
12036 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
12037 (arm_init_simd_builtin_types): Disable poly types for MVE.
12038 (arm_init_neon_builtins): Move a check to arm_init_builtins function.
12039 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
12040 ARM_BUILTIN_NEON_LANE_CHECK.
12041 (mve_dereference_pointer): Add function.
12042 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
12044 (arm_expand_neon_builtin): Moved to arm_expand_builtin function.
12045 (arm_expand_builtin): Moved from arm_expand_neon_builtin function.
12046 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
12047 with floating point enabled.
12048 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
12049 simd_immediate_valid_for_move.
12050 (simd_immediate_valid_for_move): Renamed from
12051 neon_immediate_valid_for_move function.
12052 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
12053 error if vfpv2 feature bit is disabled and mve feature bit is also
12054 disabled for HARD_FLOAT_ABI.
12055 (use_return_insn): Check to not push VFP regs for MVE.
12056 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
12058 (aapcs_vfp_allocate_return_reg): Likewise.
12059 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
12060 address operand for MVE.
12061 (arm_rtx_costs_internal): MVE check to determine cost of rtx.
12062 (neon_valid_immediate): Rename to simd_valid_immediate.
12063 (simd_valid_immediate): Rename from neon_valid_immediate.
12064 (simd_valid_immediate): MVE check on size of vector is 128 bits.
12065 (neon_immediate_valid_for_move): Rename to
12066 simd_immediate_valid_for_move.
12067 (simd_immediate_valid_for_move): Rename from
12068 neon_immediate_valid_for_move.
12069 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
12071 (neon_make_constant): Modify call to neon_valid_immediate function.
12072 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
12074 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
12075 (arm_compute_frame_layout): Calculate space for saved VFP registers for
12077 (arm_save_coproc_regs): Save coproc registers for MVE.
12078 (arm_print_operand): Add case 'E' to print memory operands for MVE.
12079 (arm_print_operand_address): Check to print register number for MVE.
12080 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
12081 (arm_modes_tieable_p): Check to allow structure mode for MVE.
12082 (arm_regno_class): Add VPR_REGNUM check.
12083 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
12085 (arm_expand_epilogue): MVE check for enabling pop instructions in
12087 (arm_print_asm_arch_directives): Modify function to disable print of
12088 .arch_extension "mve" and "fp" for cases where MVE is enabled with
12090 (arm_vector_mode_supported_p): Check for modes available in MVE interger
12091 and MVE floating point.
12092 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
12094 (arm_conditional_register_usage): Enable usage of conditional regsiter
12096 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
12097 (arm_declare_function_name): Modify function to disable print of
12098 .arch_extension "mve" and "fp" for cases where MVE is enabled with
12100 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
12101 when target general registers are required.
12102 (TARGET_HAVE_MVE_FLOAT): Likewise.
12103 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
12105 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
12106 which indicate this is not available for across function calls.
12107 (FIRST_PSEUDO_REGISTER): Modify.
12108 (VALID_MVE_MODE): Define valid MVE mode.
12109 (VALID_MVE_SI_MODE): Define valid MVE SI mode.
12110 (VALID_MVE_SF_MODE): Define valid MVE SF mode.
12111 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
12112 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
12114 (IS_VPR_REGNUM): Macro to check for VPR_REG register.
12115 (REG_ALLOC_ORDER): Add VPR_REGNUM entry.
12116 (enum reg_class): Add VPR_REG entry.
12117 (REG_CLASS_NAMES): Add VPR_REG entry.
12118 * config/arm/arm.md (VPR_REGNUM): Define.
12119 (conds): Check is_mve_type attrbiute to differentiate "conditional" and
12120 "unconditional" instructions.
12121 (arm_movsf_soft_insn): Modify RTL to not allow for MVE.
12122 (movdf_soft_insn): Modify RTL to not allow for MVE.
12123 (vfp_pop_multiple_with_writeback): Enable for MVE.
12124 (include "mve.md"): Include mve.md file.
12125 * config/arm/arm_mve.h: Add MVE intrinsics head file.
12126 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
12127 for vector predicated operands.
12128 * config/arm/iterators.md (VNIM1): Define.
12129 (VNINOTM1): Define.
12130 (VHFBF_split): Define
12131 * config/arm/mve.md: New file.
12132 (mve_mov<mode>): Define RTL for move, store and load in MVE.
12133 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
12135 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with
12136 simd_immediate_valid_for_move.
12137 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
12138 is common to MVE and NEON to vec-common.md file.
12139 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
12140 * config/arm/predicates.md (vpr_register_operand): Define.
12141 * config/arm/t-arm: Add mve.md file.
12142 * config/arm/types.md (mve_move): Add MVE instructions mve_move to
12144 (mve_store): Add MVE instructions mve_store to attribute "type".
12145 (mve_load): Add MVE instructions mve_load to attribute "type".
12146 (is_mve_type): Define attribute.
12147 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
12148 standard move patterns in MVE along with NEON and IWMMXT with mode
12150 (mov<mode>): Modify RTL expand to support standard move patterns in NEON
12151 and IWMMXT with mode iterator V8HF.
12152 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in
12154 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
12155 simd_immediate_valid_for_move.
12158 2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
12161 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
12162 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
12164 * config/i386/predicates.md (ext_sse_reg_operand): Removed.
12166 2020-03-16 Jakub Jelinek <jakub@redhat.com>
12169 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
12172 PR tree-optimization/94166
12173 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
12174 as secondary comparison key.
12176 2020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com>
12178 PR tree-optimization/94125
12179 * tree-loop-distribution.c
12180 (loop_distribution::break_alias_scc_partitions): Update post order
12181 number for merged scc.
12183 2020-03-15 H.J. Lu <hongjiu.lu@intel.com>
12186 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
12188 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
12189 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
12190 and ext_sse_reg_operand check.
12192 2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
12194 * common.opt: Avoid redundancy in the help text.
12195 * config/arc/arc.opt: Likewise.
12196 * config/cr16/cr16.opt: Likewise.
12198 2020-03-14 Jakub Jelinek <jakub@redhat.com>
12200 PR middle-end/93566
12201 * tree-nested.c (convert_nonlocal_omp_clauses,
12202 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
12203 with C/C++ array sections.
12205 2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
12208 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
12209 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
12212 2020-03-14 Jakub Jelinek <jakub@redhat.com>
12214 * gimple-fold.c (gimple_fold_builtin_strncpy): Change
12215 "a an" to "an" in a comment.
12216 * hsa-common.h (is_a_helper): Likewise.
12217 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
12218 * config/arc/arc.c (arc600_corereg_hazard): Likewise.
12219 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
12221 2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
12224 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a
12225 64-bit value by 64 bits (UB).
12227 2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
12229 PR rtl-optimization/92303
12230 * lra-spills.c (remove_pseudos): Try to simplify memory subreg.
12232 2020-03-13 Segher Boessenkool <segher@kernel.crashing.org>
12234 PR rtl-optimization/94148
12235 PR rtl-optimization/94042
12236 * df-core.c (BB_LAST_CHANGE_AGE): Delete.
12237 (df_worklist_propagate_forward): New parameter last_change_age, use
12238 that instead of bb->aux.
12239 (df_worklist_propagate_backward): Ditto.
12240 (df_worklist_dataflow_doublequeue): Use a local array last_change_age.
12242 2020-03-13 Richard Biener <rguenther@suse.de>
12244 PR tree-optimization/94163
12245 * tree-ssa-pre.c (create_expression_by_pieces): Check
12246 whether alignment would be zero.
12248 2020-03-13 Martin Liska <mliska@suse.cz>
12251 * lto-wrapper.c (run_gcc): Use concat for appending
12252 to collect_gcc_options.
12254 2020-03-13 Jakub Jelinek <jakub@redhat.com>
12257 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
12258 instead of GEN_INT.
12260 2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
12263 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
12264 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
12265 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
12266 TARGET_AVX512VL and ext_sse_reg_operand check.
12268 2020-03-13 Bu Le <bule1@huawei.com>
12271 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
12272 (-param=aarch64-double-recp-precision=): New options.
12273 * doc/invoke.texi: Document them.
12274 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
12275 instead of hard-coding the choice of 1 for float and 2 for double.
12277 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12279 PR rtl-optimization/94119
12280 * resource.h (clear_hashed_info_until_next_barrier): Declare.
12281 * resource.c (clear_hashed_info_until_next_barrier): New function.
12282 * reorg.c (add_to_delay_list): Fix formatting.
12283 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
12284 the next instruction after removing a BARRIER.
12286 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12288 PR middle-end/92071
12289 * expmed.c (store_integral_bit_field): For fields larger than a word,
12290 call extract_bit_field on the value if the mode is BLKmode. Remove
12291 specific path for big-endian targets and tidy things up a little bit.
12293 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
12295 PR rtl-optimization/90275
12296 * cse.c (cse_insn): Delete no-op register moves too.
12298 2020-03-12 Darius Galis <darius.galis@cyberthorstudios.com>
12300 * config/rx/rx.md (CTRLREG_CPEN): Remove.
12301 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
12303 2020-03-12 Richard Biener <rguenther@suse.de>
12305 PR tree-optimization/94103
12306 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
12307 punning when the mode precision is not sufficient.
12309 2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
12312 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
12313 MODE_V1DF and MODE_V2SF.
12314 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
12315 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
12318 2020-03-12 Jakub Jelinek <jakub@redhat.com>
12320 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
12321 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
12322 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
12323 * doc/tm.texi: Regenerated.
12325 PR tree-optimization/94130
12326 * tree-ssa-dse.c: Include gimplify.h.
12327 (increment_start_addr): If stmt has lhs, drop the lhs from call and
12328 set it after the call to the original value of the first argument.
12330 (decrement_count): Formatting fix.
12332 2020-03-11 Delia Burduv <delia.burduv@arm.com>
12334 * config/arm/arm-builtins.c
12335 (arm_init_simd_builtin_scalar_types): New.
12336 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
12337 (vld2q_bf16): Used new builtin type.
12338 (vld3_bf16): Used new builtin type.
12339 (vld3q_bf16): Used new builtin type.
12340 (vld4_bf16): Used new builtin type.
12341 (vld4q_bf16): Used new builtin type.
12342 (vld2_dup_bf16): Used new builtin type.
12343 (vld2q_dup_bf16): Used new builtin type.
12344 (vld3_dup_bf16): Used new builtin type.
12345 (vld3q_dup_bf16): Used new builtin type.
12346 (vld4_dup_bf16): Used new builtin type.
12347 (vld4q_dup_bf16): Used new builtin type.
12349 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12352 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
12353 at the start to switch to data section. Don't print extra newline if
12354 .globl directive has not been emitted.
12356 2020-03-11 Richard Biener <rguenther@suse.de>
12358 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
12361 2020-03-11 Eric Botcazou <ebotcazou@adacore.com>
12363 PR middle-end/93961
12364 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields
12365 whose type is a qualified union.
12367 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12370 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
12371 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
12374 * value-prof.c (dump_histogram_value): Use abs_hwi instead of
12376 (get_nth_most_common_value): Use abs_hwi instead of abs.
12378 PR middle-end/94111
12379 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
12380 is rvc_normal, otherwise use real_to_decimal to print the number to
12383 PR tree-optimization/94114
12384 * tree-loop-distribution.c (generate_memset_builtin): Call
12385 rewrite_to_non_trapping_overflow even on mem.
12386 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
12389 2020-03-10 Jeff Law <law@redhat.com>
12391 * config/bfin/bfin.md (movsi_insv): Add length attribute.
12393 2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
12396 * config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
12397 NAN and SIGNED_ZEROR for smax/smin.
12399 2020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
12402 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
12403 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
12405 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12407 * loop-iv.c (find_simple_exit): Make it static.
12408 * cfgloop.h: Remove the corresponding prototype.
12410 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12412 * ddg.c (create_ddg): Fix intendation.
12413 (set_recurrence_length): Likewise.
12414 (create_ddg_all_sccs): Likewise.
12416 2020-03-10 Jakub Jelinek <jakub@redhat.com>
12419 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with
12420 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len
12423 2020-03-09 Jason Merrill <jason@redhat.com>
12425 * gdbinit.in (pgs): Fix typo in documentation.
12427 2020-03-09 Vladimir Makarov <vmakarov@redhat.com>
12431 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
12433 PR rtl-optimization/93564
12434 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
12435 do not honor reg alloc order.
12437 2020-03-09 Andrew Pinski <apinski@marvell.com>
12439 PR inline-asm/94095
12440 * doc/extend.texi (x86 Operand Modifiers): Fix column
12443 2020-03-09 Martin Liska <mliska@suse.cz>
12446 * config/rs6000/rs6000.c (rs6000_option_override_internal):
12447 Remove set of str_align_loops and str_align_jumps as these
12448 should be set in previous 2 conditions in the function.
12450 2020-03-09 Jakub Jelinek <jakub@redhat.com>
12452 PR rtl-optimization/94045
12453 * params.opt (-param=max-find-base-term-values=): New option.
12454 * alias.c (find_base_term): Add cut-off for number of visited VALUEs
12455 in a single toplevel find_base_term call.
12457 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12460 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define.
12461 * config/aarch64/aarch64-simd.md
12462 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul.
12463 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
12464 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
12465 * config/aarch64/arm_neon.h:
12466 (vmlal_lane_s16): Expand using intrinsics rather than inline asm.
12467 (vmlal_lane_u16): Likewise.
12468 (vmlal_lane_s32): Likewise.
12469 (vmlal_lane_u32): Likewise.
12470 (vmlal_laneq_s16): Likewise.
12471 (vmlal_laneq_u16): Likewise.
12472 (vmlal_laneq_s32): Likewise.
12473 (vmlal_laneq_u32): Likewise.
12474 (vmull_lane_s16): Likewise.
12475 (vmull_lane_u16): Likewise.
12476 (vmull_lane_s32): Likewise.
12477 (vmull_lane_u32): Likewise.
12478 (vmull_laneq_s16): Likewise.
12479 (vmull_laneq_u16): Likewise.
12480 (vmull_laneq_s32): Likewise.
12481 (vmull_laneq_u32): Likewise.
12482 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul.
12485 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12487 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
12488 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
12489 (aarch64_mls_elt<mode>): Likewise.
12490 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
12491 (aarch64_fma4_elt<mode>): Likewise.
12492 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
12493 (aarch64_fma4_elt_to_64v2df): Likewise.
12494 (aarch64_fnma4_elt<mode>): Likewise.
12495 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
12496 (aarch64_fnma4_elt_to_64v2df): Likewise.
12498 2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
12500 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
12501 Specify movprfx attribute.
12502 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
12504 2020-03-06 David Edelsohn <dje.gcc@gmail.com>
12507 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for
12509 (TARGET_NO_FP_IN_TOC): Same.
12510 * config/rs6000/aix71.h: Same.
12511 * config/rs6000/aix72.h: Same.
12513 2020-03-06 Andrew Pinski <apinski@marvell.com>
12514 Jeff Law <law@redhat.com>
12516 PR rtl-optimization/93996
12517 * haifa-sched.c (remove_notes): Be more careful when adding
12520 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12522 * config/arm/arm_neon.h (vld2_bf16): New.
12528 (vld2_dup_bf16): New.
12529 (vld2q_dup_bf16): New.
12530 (vld3_dup_bf16): New.
12531 (vld3q_dup_bf16): New.
12532 (vld4_dup_bf16): New.
12533 (vld4q_dup_bf16): New.
12534 * config/arm/arm_neon_builtins.def
12535 (vld2): Changed to VAR13 and added v4bf, v8bf
12536 (vld2_dup): Changed to VAR8 and added v4bf, v8bf
12537 (vld3): Changed to VAR13 and added v4bf, v8bf
12538 (vld3_dup): Changed to VAR8 and added v4bf, v8bf
12539 (vld4): Changed to VAR13 and added v4bf, v8bf
12540 (vld4_dup): Changed to VAR8 and added v4bf, v8bf
12541 * config/arm/iterators.md (VDXBF2): New iterator.
12542 *config/arm/neon.md (neon_vld2): Use new iterators.
12543 (neon_vld2_dup<mode): Use new iterators.
12544 (neon_vld3<mode>): Likewise.
12545 (neon_vld3qa<mode>): Likewise.
12546 (neon_vld3qb<mode>): Likewise.
12547 (neon_vld3_dup<mode>): Likewise.
12548 (neon_vld4<mode>): Likewise.
12549 (neon_vld4qa<mode>): Likewise.
12550 (neon_vld4qb<mode>): Likewise.
12551 (neon_vld4_dup<mode>): Likewise.
12552 (neon_vld2_dupv8bf): New.
12553 (neon_vld3_dupv8bf): Likewise.
12554 (neon_vld4_dupv8bf): Likewise.
12556 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12558 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
12559 (bfloat16x8x2_t): New typedef.
12560 (bfloat16x4x3_t): New typedef.
12561 (bfloat16x8x3_t): New typedef.
12562 (bfloat16x4x4_t): New typedef.
12563 (bfloat16x8x4_t): New typedef.
12570 * config/arm/arm-builtins.c (v2bf_UP): Define.
12572 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype.
12573 * config/arm/arm-modes.def (V2BF): New mode.
12574 * config/arm/arm-simd-builtin-types.def
12575 (Bfloat16x2_t): New entry.
12576 * config/arm/arm_neon_builtins.def
12577 (vst2): Changed to VAR13 and added v4bf, v8bf
12578 (vst3): Changed to VAR13 and added v4bf, v8bf
12579 (vst4): Changed to VAR13 and added v4bf, v8bf
12580 * config/arm/iterators.md (VDXBF): New iterator.
12581 (VQ2BF): New iterator.
12582 *config/arm/neon.md (neon_vst2<mode>): Used new iterators.
12583 (neon_vst2<mode>): Used new iterators.
12584 (neon_vst3<mode>): Used new iterators.
12585 (neon_vst3<mode>): Used new iterators.
12586 (neon_vst3qa<mode>): Used new iterators.
12587 (neon_vst3qb<mode>): Used new iterators.
12588 (neon_vst4<mode>): Used new iterators.
12589 (neon_vst4<mode>): Used new iterators.
12590 (neon_vst4qa<mode>): Used new iterators.
12591 (neon_vst4qb<mode>): Used new iterators.
12593 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12595 * config/aarch64/aarch64-simd-builtins.def
12596 (bfcvtn): New built-in function.
12597 (bfcvtn_q): New built-in function.
12598 (bfcvtn2): New built-in function.
12599 (bfcvt): New built-in function.
12600 * config/aarch64/aarch64-simd.md
12601 (aarch64_bfcvtn<q><mode>): New pattern.
12602 (aarch64_bfcvtn2v8bf): New pattern.
12603 (aarch64_bfcvtbf): New pattern.
12604 * config/aarch64/arm_bf16.h (float32_t): New typedef.
12605 (vcvth_bf16_f32): New intrinsic.
12606 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic.
12607 (vcvtq_low_bf16_f32): New intrinsic.
12608 (vcvtq_high_bf16_f32): New intrinsic.
12609 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator.
12610 (UNSPEC_BFCVTN): New UNSPEC.
12611 (UNSPEC_BFCVTN2): New UNSPEC.
12612 (UNSPEC_BFCVT): New UNSPEC.
12613 * config/arm/types.md (bf_cvt): New type.
12615 2020-03-06 Andreas Krebbel <krebbel@linux.ibm.com>
12617 * config/s390/s390.md ("tabort"): Get rid of two consecutive
12618 blanks in format string.
12620 2020-03-05 H.J. Lu <hongjiu.lu@intel.com>
12624 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype.
12625 * config/i386/i386.c (ix86_get_ssemov): New function.
12626 (ix86_output_ssemov): Likewise.
12627 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call
12628 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL
12630 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV.
12631 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV.
12632 Remove ext_sse_reg_operand and TARGET_AVX512VL check.
12633 (*movti_internal): Likewise.
12634 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV.
12636 2020-03-05 Jeff Law <law@redhat.com>
12638 PR tree-optimization/91890
12639 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument.
12640 Use gimple_or_expr_nonartificial_location.
12641 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds.
12642 Use gimple_or_expr_nonartificial_location.
12643 * gimple.c (gimple_or_expr_nonartificial_location): New function.
12644 * gimple.h (gimple_or_expr_nonartificial_location): Declare it.
12645 * tree-ssa-strlen.c (maybe_warn_overflow): Use
12646 gimple_or_expr_nonartificial_location.
12647 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise.
12648 (maybe_warn_pointless_strcmp): Likewise.
12650 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12653 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
12654 SRC and MASK arguments to __m128 from __m128d.
12655 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
12657 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
12659 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
12660 argument to __m128i from __m128d.
12661 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
12663 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
12664 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
12667 2020-03-05 Delia Burduv <delia.burduv@arm.com>
12669 * config/arm/arm_neon.h (vbfmmlaq_f32): New.
12670 (vbfmlalbq_f32): New.
12671 (vbfmlaltq_f32): New.
12672 (vbfmlalbq_lane_f32): New.
12673 (vbfmlaltq_lane_f32): New.
12674 (vbfmlalbq_laneq_f32): New.
12675 (vbfmlaltq_laneq_f32): New.
12676 * config/arm/arm_neon_builtins.def (vmmla): New.
12681 (vfmab_laneq): New.
12682 (vfmat_laneq): New.
12683 * config/arm/iterators.md (BF_MA): New int iterator.
12684 (bt): New int attribute.
12685 (VQXBF): Copy of VQX with V8BF.
12686 * config/arm/neon.md (neon_vmmlav8bf): New insn.
12687 (neon_vfma<bt>v8bf): New insn.
12688 (neon_vfma<bt>_lanev8bf): New insn.
12689 (neon_vfma<bt>_laneqv8bf): New expand.
12690 (neon_vget_high<mode>): Changed iterator to VQXBF.
12691 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
12692 (UNSPEC_BFMAB): New UNSPEC.
12693 (UNSPEC_BFMAT): New UNSPEC.
12695 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12697 PR middle-end/93399
12698 * tree-pretty-print.h (pretty_print_string): Declare.
12699 * tree-pretty-print.c (pretty_print_string): Remove forward
12700 declaration, no longer static. Change nbytes parameter type
12701 from unsigned to size_t.
12702 * print-rtl.c (print_value) <case CONST_STRING>: Use
12703 pretty_print_string and for shrink way too long strings.
12705 2020-03-05 Richard Biener <rguenther@suse.de>
12706 Jakub Jelinek <jakub@redhat.com>
12708 PR tree-optimization/93582
12709 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR
12710 last operand as signed when looking for memset offset. Formatting
12713 2020-03-04 Andrew Pinski <apinski@marvell.com>
12716 * value-prof.c (dump_histogram_value): Use std::abs.
12718 2020-03-04 Martin Sebor <msebor@redhat.com>
12720 PR tree-optimization/93986
12721 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int
12722 operands to the same precision widest_int to avoid ICEs.
12724 2020-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
12727 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define.
12728 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry
12729 for OPTION_MASK_ALTIVEC.
12731 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12733 * config.gcc: Include the glibc-stdint.h header for zTPF.
12735 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12737 * config/s390/s390.c (s390_secondary_memory_needed): Disallow
12738 direct FPR-GPR copies.
12739 (s390_register_info_gprtofpr): Disallow GPR content to be saved in
12742 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
12744 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new
12745 operands to the prologue_tpf expander.
12746 (s390_emit_epilogue): Likewise.
12747 (s390_option_override_internal): Do error checking and setup for
12749 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK)
12750 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET)
12751 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET)
12752 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions.
12753 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new
12754 operands for the check flag and the branch target.
12755 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check")
12756 ("mtpf-trace-hook-prologue-target")
12757 ("mtpf-trace-hook-epilogue-check")
12758 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New
12760 * doc/invoke.texi: Document -mtpf-trace-skip option. The other
12761 options are for debugging purposes and will not be documented
12764 2020-03-04 Jakub Jelinek <jakub@redhat.com>
12767 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
12769 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti
12770 argument. Change pd argument so that it can be modified. Turn
12771 constant non-CONSTRUCTOR store into non-constant if it is too large.
12772 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid
12774 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust
12777 2020-02-04 Richard Biener <rguenther@suse.de>
12779 PR tree-optimization/93964
12780 * graphite-isl-ast-to-gimple.c
12781 (gcc_expression_from_isl_ast_expr_id): Add intermediate
12782 conversion for pointer to integer converts.
12783 * graphite-scop-detection.c (assign_parameter_index_in_region):
12786 2020-03-04 Martin Liska <mliska@suse.cz>
12790 * doc/invoke.texi: Clarify --help=language and --help=common
12793 2020-03-04 Jakub Jelinek <jakub@redhat.com>
12795 PR tree-optimization/94001
12796 * tree-tailcall.c (process_assignment): Before comparing op1 to
12797 *ass_var, verify *ass_var is non-NULL.
12799 2020-03-04 Kito Cheng <kito.cheng@sifive.com>
12802 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
12805 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
12807 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
12808 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
12809 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
12810 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
12811 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
12812 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
12813 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
12814 (V_bf_low, V_bf_cvt_m): New mode attributes.
12815 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
12816 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
12817 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
12818 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
12819 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
12821 2020-03-03 Jakub Jelinek <jakub@redhat.com>
12823 PR tree-optimization/93582
12824 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
12825 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
12826 members, initialize them in the constructor and if mask is non-NULL,
12827 artificially push_partial_def {} for the portions of the mask that
12829 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
12830 val and return (void *)-1. Formatting fix.
12831 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
12833 (vn_reference_lookup): Add mask argument. If non-NULL, don't call
12834 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
12836 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
12838 (visit_stmt): Formatting fix.
12840 2020-03-03 Richard Biener <rguenther@suse.de>
12842 PR tree-optimization/93946
12843 * alias.h (refs_same_for_tbaa_p): Declare.
12844 * alias.c (refs_same_for_tbaa_p): New function.
12845 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
12847 * tree-ssa-scopedtables.h
12848 (avail_exprs_stack::lookup_avail_expr): Add output argument
12849 giving access to the hashtable entry.
12850 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
12852 * tree-ssa-dom.c: Include alias.h.
12853 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
12854 removing redundant store.
12855 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
12856 (ao_ref_init_from_vn_reference): Adjust prototype.
12857 (vn_reference_lookup_pieces): Likewise.
12858 (vn_reference_insert_pieces): Likewise.
12859 * tree-ssa-sccvn.c: Track base alias set in addition to alias
12861 (eliminate_dom_walker::eliminate_stmt): Also check base alias
12862 set when removing redundant stores.
12863 (visit_reference_op_store): Likewise.
12864 * dse.c (record_store): Adjust valdity check for redundant
12867 2020-03-03 Jakub Jelinek <jakub@redhat.com>
12870 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
12872 PR rtl-optimization/94002
12873 * explow.c (plus_constant): Punt if cst has VOIDmode and
12874 get_pool_mode is different from mode.
12876 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12878 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
12879 address has an offset which fits the scalling constraint for a
12880 load/store operation.
12881 (legitimate_scaled_address_p): Update use
12882 leigitimate_small_data_address_p.
12883 (arc_print_operand): Likewise.
12884 (arc_legitimate_address_p): Likewise.
12885 (legitimate_small_data_address_p): Likewise.
12887 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12889 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
12890 (fnmasf4_fpu): Likewise.
12892 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12894 * config/arc/arc.md (adddi3): Early expand the 64bit operation into
12896 (subdi3): Likewise.
12897 (adddi3_i): Remove pattern.
12898 (subdi3_i): Likewise.
12900 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
12902 * config/arc/arc.md (eh_return): Add length info.
12904 2020-03-02 David Malcolm <dmalcolm@redhat.com>
12906 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
12908 2020-03-02 David Malcolm <dmalcolm@redhat.com>
12910 * doc/invoke.texi (Static Analyzer Options): Add
12911 -Wanalyzer-stale-setjmp-buffer to the list of options enabled
12914 2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
12917 * config/i386/i386.md (movstrict<mode>): Allow only
12918 registers with VALID_INT_MODE_P modes.
12920 2020-03-02 Andrew Stubbs <ams@codesourcery.com>
12922 * config/gcn/gcn-valu.md (dpp_move<mode>): New.
12923 (reduc_insn): Use 'U' and 'B' operand codes.
12924 (reduc_<reduc_op>_scal_<mode>): Allow all types.
12925 (reduc_<reduc_op>_scal_v64di): Delete.
12926 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
12927 (*plus_carry_dpp_shr_v64si): Change to ...
12928 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
12929 (mov_from_lane63_v64di): Change to ...
12930 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
12931 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
12932 Support UNSPEC_MOV_DPP_SHR output formats.
12933 (gcn_expand_reduc_scalar): Add "use_moves" reductions.
12934 Add "use_extends" reductions.
12935 (print_operand_address): Add 'I' and 'U' codes.
12936 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
12938 2020-03-02 Martin Liska <mliska@suse.cz>
12940 * lto-wrapper.c: Fix typo in comment about
12941 C++ standard version.
12943 2020-03-01 Martin Sebor <msebor@redhat.com>
12946 * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
12948 2020-03-01 Martin Sebor <msebor@redhat.com>
12950 PR middle-end/93829
12951 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
12952 of a pointer in the outermost ADDR_EXPRs.
12954 2020-02-28 Jeff Law <law@redhat.com>
12956 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
12957 * config/v850/v850.c (v850_asm_trampoline_template): Update
12960 2020-02-28 Michael Meissner <meissner@linux.ibm.com>
12963 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
12966 2020-02-28 Martin Liska <mliska@suse.cz>
12969 * configure.ac: Improve detection of ld_date by requiring
12970 either two dashes or none.
12971 * configure: Regenerate.
12973 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
12975 PR rtl-optimization/93564
12976 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
12977 do not honor reg alloc order.
12979 2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
12982 * config/aarch64/aarch64.c (aarch64_override_options): Fix
12983 misleading warning string.
12985 2020-02-27 Martin Sebor <msebor@redhat.com>
12987 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
12989 2020-02-27 Michael Meissner <meissner@linux.ibm.com>
12992 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
12993 Split the insn into two parts. This insn only does variable
12994 extract from a register.
12995 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
12996 variable extract from memory.
12997 (vsx_extract_v4sf_var): Split the insn into two parts. This insn
12998 only does variable extract from a register.
12999 (vsx_extract_v4sf_var_load): New insn, do variable extract from
13001 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
13002 into two parts. This insn only does variable extract from a
13004 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
13005 do variable extract from memory.
13007 2020-02-27 Martin Jambor <mjambor@suse.cz>
13008 Feng Xue <fxue@os.amperecomputing.com>
13011 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
13012 new function calls_same_node_or_its_all_contexts_clone_p.
13013 (cgraph_edge_brings_value_p): Use it.
13014 (cgraph_edge_brings_value_p): Likewise.
13015 (self_recursive_pass_through_p): Return false if caller is a clone.
13016 (self_recursive_agg_pass_through_p): Likewise.
13018 2020-02-27 Jan Hubicka <hubicka@ucw.cz>
13020 PR middle-end/92152
13021 * alias.c (ends_tbaa_access_path_p): Break out from ...
13022 (component_uses_parent_alias_set_from): ... here.
13023 * alias.h (ends_tbaa_access_path_p): Declare.
13024 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
13025 handle trailing arrays past end of tbaa access path.
13026 (aliasing_component_refs_p): ... here; likewise.
13027 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
13028 path; disambiguate also past end of it.
13029 (nonoverlapping_component_refs_p): Use only TBAA segment of the access
13032 2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
13034 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
13035 beginning of the file.
13036 (vcreate_bf16, vcombine_bf16): New.
13037 (vdup_n_bf16, vdupq_n_bf16): New.
13038 (vdup_lane_bf16, vdup_laneq_bf16): New.
13039 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
13040 (vduph_lane_bf16, vduph_laneq_bf16): New.
13041 (vset_lane_bf16, vsetq_lane_bf16): New.
13042 (vget_lane_bf16, vgetq_lane_bf16): New.
13043 (vget_high_bf16, vget_low_bf16): New.
13044 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
13045 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
13046 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
13047 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
13048 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
13049 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
13050 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
13051 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
13052 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
13053 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
13054 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
13055 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
13056 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
13057 (vreinterpretq_bf16_p128): New.
13058 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
13059 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
13060 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
13061 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
13062 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
13063 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
13064 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
13065 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
13066 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
13067 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
13068 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
13069 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
13070 (vreinterpretq_p128_bf16): New.
13071 * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
13072 (V_elem): Likewise.
13073 (V_elem_l): Likewise.
13074 (VD_LANE): Likewise.
13076 (V_DOUBLE): Likewise.
13077 (VDQX): Add V4BF and V8BF.
13078 (V_two_elem, V_three_elem, V_four_elem): Likewise.
13080 (V_HALF): Likewise.
13081 (V_double_vector_mode): Likewise.
13082 (V_cmp_result): Likewise.
13083 (V_uf_sclr): Likewise.
13084 (V_sz_elem): Likewise.
13085 (Is_d_reg): Likewise.
13086 (V_mode_nunits): Likewise.
13087 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
13089 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
13091 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
13092 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
13093 (<expander><mode>3<exec>): Likewise.
13094 (<expander><mode>3): New.
13095 (v<expander><mode>3): New.
13096 (<expander><mode>3): New.
13097 (<expander><mode>3<exec>): Rename to ...
13098 (<expander>v64si3<exec>): ... this, and change modes to V64SI.
13099 * config/gcn/gcn.md (mnemonic): Use '%B' for not.
13101 2020-02-27 Alexandre Oliva <oliva@adacore.com>
13103 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
13106 2020-02-27 Richard Biener <rguenther@suse.de>
13108 PR tree-optimization/93508
13109 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
13110 non-_CHK variants. Valueize their length arguments.
13112 2020-02-27 Richard Biener <rguenther@suse.de>
13114 PR tree-optimization/93953
13115 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
13116 to the hash-map entry.
13118 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
13120 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
13122 2020-02-27 Mark Williams <mwilliams@fb.com>
13124 * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
13125 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
13126 -ffile-prefix-map and -fmacro-prefix-map.
13127 * lto-streamer-out.c: Include file-prefix-map.h.
13128 (lto_output_location): Remap the file part of locations.
13130 2020-02-27 Jakub Jelinek <jakub@redhat.com>
13133 * gimplify.c (gimplify_init_constructor): Don't promote readonly
13134 DECL_REGISTER variables to TREE_STATIC.
13136 PR tree-optimization/93582
13137 PR tree-optimization/93945
13138 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
13139 non-zero INTEGER_CST second argument and ref->offset or ref->size
13140 not a multiple of BITS_PER_UNIT.
13142 2020-02-27 Jonathan Wakely <jwakely@redhat.com>
13144 * doc/install.texi (Binaries): Update description of BullFreeware.
13146 2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
13150 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
13151 C++ Language Options, Warning Options, and Static Analyzer
13152 Options lists. Document negative form of options enabled by
13153 default. Move some things around to more accurately sort
13154 warnings by category.
13155 (C++ Dialect Options, Warning Options, Static Analyzer
13156 Options): Document negative form of options when enabled by
13157 default. Move some things around to more accurately sort
13158 warnings by category. Add some missing index entries.
13159 Light copy-editing.
13161 2020-02-26 Carl Love <cel@us.ibm.com>
13164 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
13165 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
13166 for the vector unsigned short arguments. It is also listed as the
13167 name of the built-in for arguments vector unsigned short,
13168 vector unsigned int and vector unsigned long long built-ins. The
13169 name of the builtins for these arguments should be:
13170 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
13171 __builtin_crypto_vpmsumd respectively.
13173 2020-02-26 Richard Biener <rguenther@suse.de>
13175 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
13176 and load permutation.
13178 2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
13180 PR middle-end/93843
13181 * optabs-tree.c (supportable_convert_operation): Reject types with
13184 2020-02-26 David Malcolm <dmalcolm@redhat.com>
13186 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
13188 2020-02-26 Jakub Jelinek <jakub@redhat.com>
13190 PR tree-optimization/93820
13191 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
13192 argument to ALL_INTEGER_CST_P boolean.
13193 (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
13194 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
13195 adjacent INTEGER_CST store into merged_store->only_constants like
13198 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13201 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
13203 * cfghooks.c (verify_flow_info): Likewise.
13204 * predict.c (combine_predictions_for_bb): Likewise.
13205 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
13206 sucessor -> successor.
13207 (find_traces_1_round): Fix comment typo, destinarion -> destination.
13208 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
13210 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
13211 message typo, sucessors -> successors.
13213 2020-02-25 Martin Sebor <msebor@redhat.com>
13215 * doc/extend.texi (attribute access): Correct an example.
13217 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
13219 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
13221 (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
13222 (VAR15, VAR16): New.
13223 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
13224 (VD): Enable for V4BF.
13226 (VQ): Enable for V8BF.
13228 (VQ_NO2E): Likewise.
13229 (VDBL, Vdbl): Add V4BF.
13230 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
13231 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
13232 (bfloat16x8x2_t): Likewise.
13233 (bfloat16x4x3_t): Likewise.
13234 (bfloat16x8x3_t): Likewise.
13235 (bfloat16x4x4_t): Likewise.
13236 (bfloat16x8x4_t): Likewise.
13237 (vcombine_bf16): New.
13238 (vld1_bf16, vld1_bf16_x2): New.
13239 (vld1_bf16_x3, vld1_bf16_x4): New.
13240 (vld1q_bf16, vld1q_bf16_x2): New.
13241 (vld1q_bf16_x3, vld1q_bf16_x4): New.
13242 (vld1_lane_bf16): New.
13243 (vld1q_lane_bf16): New.
13244 (vld1_dup_bf16): New.
13245 (vld1q_dup_bf16): New.
13248 (vld2_dup_bf16): New.
13249 (vld2q_dup_bf16): New.
13252 (vld3_dup_bf16): New.
13253 (vld3q_dup_bf16): New.
13256 (vld4_dup_bf16): New.
13257 (vld4q_dup_bf16): New.
13258 (vst1_bf16, vst1_bf16_x2): New.
13259 (vst1_bf16_x3, vst1_bf16_x4): New.
13260 (vst1q_bf16, vst1q_bf16_x2): New.
13261 (vst1q_bf16_x3, vst1q_bf16_x4): New.
13262 (vst1_lane_bf16): New.
13263 (vst1q_lane_bf16): New.
13271 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
13273 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
13274 (VALL_F16): Likewise.
13275 (VALLDI_F16): Likewise.
13277 (Vetype): Likewise.
13278 (vswap_width_name): Likewise.
13279 (VSWAP_WIDTH): Likewise.
13283 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
13284 (vget_lane_bf16, vgetq_lane_bf16): New.
13285 (vcreate_bf16): New.
13286 (vdup_n_bf16, vdupq_n_bf16): New.
13287 (vdup_lane_bf16, vdup_laneq_bf16): New.
13288 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
13289 (vduph_lane_bf16, vduph_laneq_bf16): New.
13290 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
13291 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
13292 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
13293 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
13294 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
13295 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
13296 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
13297 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
13298 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
13299 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
13300 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
13301 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
13302 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
13303 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
13304 (vreinterpretq_bf16_p128): New.
13305 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
13306 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
13307 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
13308 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
13309 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
13310 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
13311 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
13312 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
13313 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
13314 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
13315 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
13316 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
13317 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
13318 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
13319 (vreinterpretq_p128_bf16): New.
13321 2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
13323 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
13324 (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
13325 (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
13326 * config/arm/arm_neon_builtins.def (vbfdot): New entry.
13327 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
13328 * config/arm/iterators.md (VSF2BF): New attribute.
13329 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
13330 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
13331 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
13333 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
13335 * config/arm/arm.md (required_for_purecode): New attribute.
13336 (enabled): Handle required_for_purecode.
13337 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
13338 work with -mpure-code.
13340 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13342 PR rtl-optimization/93908
13343 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
13346 2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
13348 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
13350 2020-02-25 Roman Zhuykov <zhroma@ispras.ru>
13352 * doc/install.texi (--enable-checking): Adjust wording.
13354 2020-02-25 Richard Biener <rguenther@suse.de>
13356 PR tree-optimization/93868
13357 * tree-vect-slp.c (slp_copy_subtree): New function.
13358 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before
13359 re-arranging stmts in it.
13361 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13363 PR middle-end/93874
13364 * passes.c (pass_manager::dump_passes): Create a cgraph node for the
13365 dummy function and remove it at the end.
13367 PR translation/93864
13368 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo
13369 paramter -> parameter.
13370 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise.
13371 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise.
13373 2020-02-24 Roman Zhuykov <zhroma@ispras.ru>
13375 * doc/install.texi (--enable-checking): Properly document current
13377 (--enable-stage1-checking): Minor clarification about bootstrap.
13379 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13382 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that
13383 -fanalyzer-checker=taint is also required.
13384 (-fanalyzer-checker=): Note that providing this option enables the
13385 given checker, and doing so may be required for checkers that are
13386 disabled by default.
13388 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13390 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows
13391 significant control flow events; add a "3" which shows all
13392 control flow events; the old "3" becomes "4".
13394 2020-02-24 Jakub Jelinek <jakub@redhat.com>
13396 PR tree-optimization/93582
13397 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider
13398 pd.offset and pd.size to be counted in bits rather than bytes, add
13399 support for maxsizei that is not a multiple of BITS_PER_UNIT and
13400 handle bitfield stores and loads.
13401 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with
13402 uncomparable quantities - bytes vs. bits. Allow push_partial_def
13403 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust
13404 pd.offset/pd.size to be counted in bits rather than bytes.
13405 Formatting fix. Rename shadowed len variable to buflen.
13407 2020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
13408 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org>
13411 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function.
13412 (driver::main): Call putenv_COLLECT_AS_OPTIONS.
13413 * opts-common.c (parse_options_from_collect_gcc_options): New function.
13414 (prepend_xassembler_to_collect_as_options): Likewise.
13415 * opts.h (parse_options_from_collect_gcc_options): Declare prototype.
13416 (prepend_xassembler_to_collect_as_options): Likewise.
13417 * lto-opts.c (lto_write_options): Stream assembler options
13418 in COLLECT_AS_OPTIONS.
13419 * lto-wrapper.c (xassembler_options_error): New static variable.
13420 (get_options_from_collect_gcc_options): Move parsing options code to
13421 parse_options_from_collect_gcc_options and call it.
13422 (merge_and_complain): Validate -Xassembler options.
13423 (append_compiler_options): Handle OPT_Xassembler.
13424 (run_gcc): Append command line -Xassembler options to
13425 collect_gcc_options.
13426 * doc/invoke.texi: Add documentation about using Xassembler
13429 2020-02-24 Kito Cheng <kito.cheng@sifive.com>
13431 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen
13433 (riscv_rtx_costs): Update cost model for LTGT.
13435 2020-02-23 Vladimir Makarov <vmakarov@redhat.com>
13437 PR rtl-optimization/93564
13438 * ira-color.c (struct update_cost_queue_elem): New member start.
13439 (queue_update_cost, get_next_update_cost): Add new arg start.
13440 (allocnos_conflict_p): New function.
13441 (update_costs_from_allocno): Add new arg conflict_cost_update_p.
13442 Add checking conflicts with allocnos_conflict_p.
13443 (update_costs_from_prefs, restore_costs_from_copies): Adjust
13444 update_costs_from_allocno calls.
13445 (update_conflict_hard_regno_costs): Add checking conflicts with
13446 allocnos_conflict_p. Adjust calls of queue_update_cost and
13447 get_next_update_cost.
13448 (assign_hard_reg): Adjust calls of queue_update_cost. Add
13450 (bucket_allocno_compare_func): Restore previous version.
13452 2020-02-21 John David Anglin <danglin@gcc.gnu.org>
13454 * config/pa/pa.c (pa_function_value): Fix check for word and
13455 double-word size when handling aggregate return values.
13456 * config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate
13457 that homogeneous SFmode and DFmode aggregates are passed and returned
13458 in general registers.
13460 2020-02-21 Jakub Jelinek <jakub@redhat.com>
13462 PR translation/93759
13463 * opts.c (print_filtered_help): Translate help before appending
13464 messages to it rather than after that.
13466 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13468 PR rtl-optimization/PR92989
13469 * lra-lives.c (process_bb_lives): Restore the original order
13470 of the bb liveness update. Call make_hard_regno_dead for each
13471 register clobbered at the start of an EH receiver.
13473 2020-02-18 Feng Xue <fxue@os.amperecomputing.com>
13476 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as
13477 self-recursively generated.
13479 2020-02-21 Iain Sandoe <iain@sandoe.co.uk>
13482 * config/darwin-c.c (pop_field_alignment): Adjust quoting of
13485 2020-02-21 Mihail Ionescu <mihail.ionescu@arm.com>
13487 * doc/sourcebuild.texi (arm_v8_1m_mve_ok):
13488 Document new target supports option.
13490 2020-02-21 Dennis Zhang <dennis.zhang@arm.com>
13492 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New.
13493 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New.
13494 * config/arm/iterators.md (MATMUL): New iterator.
13495 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US.
13496 (mmla_sfx): New attribute.
13497 * config/arm/neon.md (neon_<sup>mmlav16qi): New.
13498 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New.
13499 (UNSPEC_MATMUL_US): New.
13501 2020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13503 * config/arm/arm.md: Prevent scalar shifts from being used when big
13506 2020-02-21 Jan Hubicka <hubicka@ucw.cz>
13507 Richard Biener <rguenther@suse.de>
13509 PR tree-optimization/93586
13510 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk
13511 after mismatched array refs; do not sure type size information to
13512 recover from unmatched referneces with !flag_strict_aliasing_p.
13514 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13516 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
13517 (gather_load<mode>v64si): ... this and set operand 2 to V64SI.
13518 (scatter_store<mode>): Rename to ...
13519 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
13520 (scatter<mode>_exec): Delete. Move contents ...
13521 (mask_scatter_store<mode>): ... here, and rename that to ...
13522 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
13523 Remove mode conversion.
13524 (mask_gather_load<mode>): Rename to ...
13525 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
13526 Remove mode conversion.
13527 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
13529 2020-02-21 Martin Jambor <mjambor@suse.cz>
13531 PR tree-optimization/93845
13532 * tree-sra.c (verify_sra_access_forest): Only test access size of
13535 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13537 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
13538 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
13539 (addv64di3_exec): Likewise.
13540 (subv64di3): Likewise.
13541 (subv64di3_exec): Likewise.
13542 (addv64di3_zext): Likewise.
13543 (addv64di3_zext_exec): Likewise.
13544 (addv64di3_zext_dup): Likewise.
13545 (addv64di3_zext_dup_exec): Likewise.
13546 (addv64di3_zext_dup2): Likewise.
13547 (addv64di3_zext_dup2_exec): Likewise.
13548 (addv64di3_sext_dup2): Likewise.
13549 (addv64di3_sext_dup2_exec): Likewise.
13550 (<expander>v64di3): Likewise.
13551 (<expander>v64di3_exec): Likewise.
13552 (*<reduc_op>_dpp_shr_v64di): Likewise.
13553 (*plus_carry_dpp_shr_v64di): Likewise.
13554 * config/gcn/gcn.md (adddi3): Likewise.
13555 (addptrdi3): Likewise.
13556 (<expander>di3): Likewise.
13558 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13560 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
13562 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13564 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
13565 support. Use aarch64_emit_mult instead of emitting multiplication
13566 instructions directly.
13567 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2)
13568 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders.
13570 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13572 * config/aarch64/aarch64.c (aarch64_emit_mult): New function.
13573 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult
13574 instead of emitting multiplication instructions directly.
13575 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator.
13576 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>)
13577 (@aarch64_frecps<mode>): New expanders.
13579 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13581 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate
13582 on and produce uint64_ts rather than ints.
13583 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts.
13584 (cpu_approx_modes): Change the fields from unsigned int to uint64_t.
13586 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13588 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create
13589 an unused xmsk register when handling approximate rsqrt.
13591 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13593 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted
13594 flag_finite_math_only condition.
13596 2020-02-20 Uroš Bizjak <ubizjak@gmail.com>
13599 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand
13600 to destination operand for shufps alternative.
13601 (*vec_extractv2si_1): Ditto.
13603 2020-02-20 Peter Bergner <bergner@linux.ibm.com>
13606 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
13609 2020-02-20 Martin Liska <mliska@suse.cz>
13611 PR translation/93831
13612 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode.
13614 2020-02-20 Martin Liska <mliska@suse.cz>
13616 PR translation/93830
13617 * common/config/avr/avr-common.c: Remote trailing "|".
13619 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13621 * collect2.c (maybe_run_lto_and_relink): Fix typo in
13624 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13626 PR tree-optimization/93767
13627 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the
13628 access-size bias from the offset calculations for negative strides.
13630 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13632 * collect2.c (c_file, o_file): Make const again.
13633 (ldout,lderrout, dump_ld_file): Remove.
13634 (tool_cleanup): Avoid calling not signal-safe functions.
13635 (maybe_run_lto_and_relink): Avoid possible signal handler
13636 access to unintialzed memory (lto_o_files).
13637 (main): Avoid leaking temp files in $TMPDIR.
13638 Initialize c_file/o_file with concat, which avoids exposing
13639 uninitialized memory to signal handler, which calls unlink(!).
13640 Avoid calling maybe_unlink when the main function returns,
13641 since the atexit handler is already doing this.
13642 * collect2.h (dump_ld_file, ldout, lderrout): Remove.
13644 2020-02-19 Martin Jambor <mjambor@suse.cz>
13646 PR tree-optimization/93776
13647 * tree-sra.c (create_access): Do not create zero size accesses.
13648 (get_access_for_expr): Do not search for zero sized accesses.
13650 2020-02-19 Martin Jambor <mjambor@suse.cz>
13652 PR tree-optimization/93667
13653 * tree-sra.c (scalarizable_type_p): Return false if record fields
13654 do not follow wach other.
13656 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
13658 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
13659 rather than fmv.x.s/fmv.s.x.
13661 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
13663 * config/aarch64/aarch64-simd-builtins.def
13664 (intrinsic_vec_smult_lo_): New.
13665 (intrinsic_vec_umult_lo_): Likewise.
13666 (vec_widen_smult_hi_): Likewise.
13667 (vec_widen_umult_hi_): Likewise.
13668 * config/aarch64/aarch64-simd.md
13669 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New.
13670 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics.
13671 (vmull_high_s16): Likewise.
13672 (vmull_high_s32): Likewise.
13673 (vmull_high_u8): Likewise.
13674 (vmull_high_u16): Likewise.
13675 (vmull_high_u32): Likewise.
13676 (vmull_s8): Likewise.
13677 (vmull_s16): Likewise.
13678 (vmull_s32): Likewise.
13679 (vmull_u8): Likewise.
13680 (vmull_u16): Likewise.
13681 (vmull_u32): Likewise.
13683 2020-02-18 Martin Liska <mliska@suse.cz>
13685 * value-prof.c (stream_out_histogram_value): Restore LTO PGO
13686 bootstrap by missing removal of invalid sanity check.
13688 2020-02-18 Martin Liska <mliska@suse.cz>
13691 * ipa-icf-gimple.c (func_checker::compare_gimple_assign):
13692 Always compare LHS of gimple_assign.
13694 2020-02-18 Martin Liska <mliska@suse.cz>
13697 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute
13698 and return type of functions.
13699 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl):
13700 Drop MALLOC attribute for void functions.
13701 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop
13702 malloc_state for a new VOID clone.
13704 2020-02-18 Martin Liska <mliska@suse.cz>
13707 * common.opt: Add -fprofile-reproducibility.
13708 * doc/invoke.texi: Document it.
13709 * value-prof.c (dump_histogram_value):
13710 Document and support behavior for counters[0]
13711 being a negative value.
13712 (get_nth_most_common_value): Handle negative
13713 counters[0] in respect to flag_profile_reproducible.
13715 2020-02-18 Jakub Jelinek <jakub@redhat.com>
13718 * cgraph.c (verify_speculative_call): Use speculative_id instead of
13719 speculative_uid in messages. Remove trailing whitespace from error
13720 message. Use num_speculative_call_targets instead of
13721 num_speculative_targets in a message.
13722 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in
13723 edge messages and stmt instead of cal_stmt in reference message.
13725 PR tree-optimization/93780
13726 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p
13727 before calling build_vector_type.
13728 (execute_update_addresses_taken): Likewise.
13731 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help
13732 typo, functoin -> function.
13733 * tree.c (free_lang_data_in_decl): Fix comment typo,
13734 functoin -> function.
13735 * ipa-visibility.c (cgraph_externally_visible_p): Likewise.
13737 2020-02-17 David Malcolm <dmalcolm@redhat.com>
13739 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs
13741 (print_option_information): Don't call get_option_url if URLs
13744 2020-02-17 Alexandre Oliva <oliva@adacore.com>
13746 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete
13747 handling of register_common-less targets.
13749 2020-02-17 Martin Liska <mliska@suse.cz>
13752 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar.
13754 2020-02-17 Martin Liska <mliska@suse.cz>
13756 PR translation/93755
13757 * config/rs6000/rs6000.c (rs6000_option_override_internal):
13760 2020-02-17 Martin Liska <mliska@suse.cz>
13763 * config/rx/elf.opt: Fix typo.
13765 2020-02-17 Richard Biener <rguenther@suse.de>
13768 * opts-global.c (print_ignored_options): Use inform and
13771 2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
13774 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
13776 2020-02-16 Uroš Bizjak <ubizjak@gmail.com>
13779 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2.
13780 (atan2<mode>3): Update operand order in the call to gen_atan2xf3.
13782 2020-02-15 Jason Merrill <jason@redhat.com>
13784 * doc/invoke.texi (C Dialect Options): Add -std=c++20.
13786 2020-02-15 Jakub Jelinek <jakub@redhat.com>
13788 PR tree-optimization/93744
13789 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0,
13790 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A,
13791 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make
13792 sure @2 in the first and @1 in the other patterns has no side-effects.
13794 2020-02-15 David Malcolm <dmalcolm@redhat.com>
13795 Bernd Edlinger <bernd.edlinger@hotmail.de>
13799 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
13800 * configure.ac (--with-diagnostics-urls): New configuration
13801 option, based on --with-diagnostics-color.
13802 (DIAGNOSTICS_URLS_DEFAULT): New define.
13803 * config.h: Regenerate.
13804 * configure: Regenerate.
13805 * diagnostic.c (diagnostic_urls_init): Handle -1 for
13806 DIAGNOSTICS_URLS_DEFAULT from configure-time
13807 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
13808 and TERM_URLS environment variable.
13809 * diagnostic-url.h (diagnostic_url_format): New enum type.
13810 (diagnostic_urls_enabled_p): rename to...
13811 (determine_url_format): ... this, and change return type.
13812 * diagnostic-color.c (parse_env_vars_for_urls): New helper function.
13813 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
13814 the linux console, and mingw.
13815 (diagnostic_urls_enabled_p): rename to...
13816 (determine_url_format): ... this, and adjust.
13817 * pretty-print.h (pretty_printer::show_urls): rename to...
13818 (pretty_printer::url_format): ... this, and change to enum.
13819 * pretty-print.c (pretty_printer::pretty_printer,
13820 pp_begin_url, pp_end_url, test_urls): Adjust.
13821 * doc/install.texi (--with-diagnostics-urls): Document the new
13822 configuration option.
13823 (--with-diagnostics-color): Document the existing interaction
13824 with GCC_COLORS better.
13825 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
13826 vindex reference. Update description of defaults based on the above.
13827 (-fdiagnostics-color): Update description of how -fdiagnostics-color
13828 interacts with GCC_COLORS.
13830 2020-02-14 Eric Botcazou <ebotcazou@adacore.com>
13833 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in
13834 conjunction with TARGET_GNU_TLS in early return.
13836 2020-02-14 Alexander Monakov <amonakov@ispras.ru>
13838 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if
13839 the mode is not wider than UNITS_PER_WORD.
13841 2020-02-14 Martin Jambor <mjambor@suse.cz>
13843 PR tree-optimization/93516
13844 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create
13845 access of the same type as the parent.
13846 (propagate_subaccesses_from_lhs): Likewise.
13848 2020-02-14 Hongtao Liu <hongtao.liu@intel.com>
13851 * config/i386/avx512vbmi2intrin.h
13852 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16,
13853 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32,
13854 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
13855 _m512_shrdi_epi64, _m512_mask_shrdi_epi64,
13856 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16,
13857 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16,
13858 _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
13859 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
13860 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo
13861 of lacking a closing parenthesis.
13862 * config/i386/avx512vbmi2vlintrin.h
13863 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16,
13864 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32,
13865 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32,
13866 _m256_shrdi_epi64, _m256_mask_shrdi_epi64,
13867 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16,
13868 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
13869 _mm256_shldi_epi32, _mm256_mask_shldi_epi32,
13870 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64,
13871 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64,
13872 _mm_shrdi_epi16, _mm_mask_shrdi_epi16,
13873 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32,
13874 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32,
13875 _mm_shrdi_epi64, _mm_mask_shrdi_epi64,
13876 _m_maskz_shrdi_epi64, _mm_shldi_epi16,
13877 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16,
13878 _mm_shldi_epi32, _mm_mask_shldi_epi32,
13879 _mm_maskz_shldi_epi32, _mm_shldi_epi64,
13880 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto.
13882 2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
13885 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
13886 the target function entry.
13888 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13890 * common/config/arc/arc-common.c (arc_option_optimization_table):
13891 Disable if-conversion step when optimized for size.
13893 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13895 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
13896 R12-R15 are always in ARCOMPACT16_REGS register class.
13897 * config/arc/arc.opt (mq-class): Deprecate.
13898 * config/arc/constraint.md ("q"): Remove dependency on mq-class
13900 * doc/invoke.texi (mq-class): Update text.
13901 * common/config/arc/arc-common.c (arc_option_optimization_table):
13904 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13906 * config/arc/arc.c (arc_insn_cost): New function.
13907 (TARGET_INSN_COST): Define.
13908 * config/arc/arc.md (cost): New attribute.
13909 (add_n): Use arc_nonmemory_operand.
13910 (ashlsi3_insn): Likewise, also update constraints.
13911 (ashrsi3_insn): Likewise.
13912 (rotrsi3): Likewise.
13913 (add_shift): Likewise.
13914 * config/arc/predicates.md (arc_nonmemory_operand): New predicate.
13916 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
13918 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
13920 (umulsidi_600): Likewise.
13922 2020-02-13 Jakub Jelinek <jakub@redhat.com>
13925 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8,
13926 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8,
13927 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8,
13928 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W,
13929 pass __A to the builtin followed by __W instead of __A followed by
13931 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32,
13932 _mm512_mask_popcnt_epi64): Likewise.
13933 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32,
13934 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64,
13935 _mm256_mask_popcnt_epi64): Likewise.
13937 PR tree-optimization/93582
13938 * fold-const.h (shift_bytes_in_array_left,
13939 shift_bytes_in_array_right): Declare.
13940 * fold-const.c (shift_bytes_in_array_left,
13941 shift_bytes_in_array_right): New function, moved from
13942 gimple-ssa-store-merging.c, no longer static.
13943 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move
13944 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left.
13945 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c.
13946 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of
13947 shift_bytes_in_array.
13948 (verify_shift_bytes_in_array): Rename to ...
13949 (verify_shift_bytes_in_array_left): ... this. Use
13950 shift_bytes_in_array_left instead of shift_bytes_in_array.
13951 (store_merging_c_tests): Call verify_shift_bytes_in_array_left
13952 instead of verify_shift_bytes_in_array.
13953 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr
13954 / native_interpret_expr where the store covers all needed bits,
13955 punt on PDP-endian, otherwise allow all involved offsets and sizes
13956 not to be byte-aligned.
13959 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and
13960 use const_0_to_255_operand predicate instead of immediate_operand.
13961 (avx512dq_fpclass<mode><mask_scalar_merge_name>,
13962 avx512dq_vmfpclass<mode><mask_scalar_merge_name>,
13963 vgf2p8affineinvqb_<mode><mask_name>,
13964 vgf2p8affineqb_<mode><mask_name>): Drop mode from
13965 const_0_to_255_operand predicated operands.
13967 2020-02-12 Jeff Law <law@redhat.com>
13969 * config/h8300/h8300.md (comparison shortening peepholes): Use
13970 a mode iterator to merge the HImode and SImode peepholes.
13972 2020-02-12 Jakub Jelinek <jakub@redhat.com>
13974 PR middle-end/93663
13975 * real.c (is_even): Make static. Function comment fix.
13976 (is_halfway_below): Make static, don't assert R is not inf/nan,
13977 instead return false for those. Small formatting fixes.
13979 2020-02-12 Martin Sebor <msebor@redhat.com>
13981 PR middle-end/93646
13982 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename...
13983 (handle_builtin_stxncpy_strncat): ...to this. Change first argument.
13984 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation.
13985 (strlen_check_and_optimize_call): Adjust callee name.
13987 2020-02-12 Jeff Law <law@redhat.com>
13989 * config/h8300/h8300.md (comparison shortening peepholes): Drop
13990 (and (xor)) variant. Combine other two into single peephole.
13992 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
13994 PR rtl-optimization/93565
13995 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs.
13997 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
13999 * config/aarch64/aarch64-simd.md
14000 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
14001 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
14002 generating separate ADDV and zero_extend patterns.
14003 * config/aarch64/iterators.md (VDQV_E): New iterator.
14005 2020-02-12 Jeff Law <law@redhat.com>
14007 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,
14008 expanders, splits, etc.
14009 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise.
14010 (stpcpy_internal_<mode>, stpcpy splitter): Likewise.
14011 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise.
14012 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function.
14013 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise
14014 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused
14015 function prototype.
14016 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
14018 2020-02-12 Jakub Jelinek <jakub@redhat.com>
14021 * config/i386/sse.md (VI48F_256_DQ): New mode iterator.
14022 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove
14023 TARGET_AVX512DQ from condition.
14024 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition>
14025 instead of <mask_mode512bit_condition> in condition. If
14026 TARGET_AVX512DQ is false, emit vextract*64x4 instead of
14028 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition>
14031 2020-02-12 Kewen Lin <linkw@gcc.gnu.org>
14034 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
14036 2020-02-12 Segher Boessenkool <segher@kernel.crashing.org>
14038 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof
14039 where strlen is more legible.
14040 (rs6000_builtin_vectorized_libmass): Ditto.
14041 (rs6000_print_options_internal): Ditto.
14043 2020-02-11 Martin Sebor <msebor@redhat.com>
14045 PR tree-optimization/93683
14046 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
14048 2020-02-11 Michael Meissner <meissner@linux.ibm.com>
14050 * config/rs6000/predicates.md (cint34_operand): Rename the
14051 -mprefixed-addr option to be -mprefixed.
14052 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
14053 the -mprefixed-addr option to be -mprefixed.
14054 (OTHER_FUTURE_MASKS): Likewise.
14055 (POWERPC_MASKS): Likewise.
14056 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
14057 the -mprefixed-addr option to be -mprefixed. Change error
14058 messages to refer to -mprefixed.
14059 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be
14061 (rs6000_legitimate_offset_address_p): Likewise.
14062 (rs6000_mode_dependent_address): Likewise.
14063 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
14064 "-mprefixed" for target attributes and pragmas.
14065 (address_to_insn_form): Rename the -mprefixed-addr option to be
14067 (rs6000_adjust_insn_length): Likewise.
14068 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
14069 -mprefixed-addr option to be -mprefixed.
14070 (ASM_OUTPUT_OPCODE): Likewise.
14071 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the
14072 -mprefixed-addr option to be -mprefixed.
14073 * config/rs6000/rs6000.opt (-mprefixed): Rename the
14074 -mprefixed-addr option to be prefixed. Change the option from
14075 being undocumented to being documented.
14076 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the
14077 -mprefixed option. Update the -mpcrel documentation to mention
14080 2020-02-11 Hans-Peter Nilsson <hp@axis.com>
14082 * ira-conflicts.c (print_hard_reg_set): Correct output for sets
14083 including FIRST_PSEUDO_REGISTER - 1.
14084 * ira-color.c (print_hard_reg_set): Ditto.
14086 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14088 * config/arm/arm-builtins.c (enum arm_type_qualifiers):
14089 (USTERNOP_QUALIFIERS): New define.
14090 (USMAC_LANE_QUADTUP_QUALIFIERS): New define.
14091 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
14092 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
14093 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
14094 * config/arm/arm_neon.h (vusdot_s32): New.
14095 (vusdot_lane_s32): New.
14096 (vusdotq_lane_s32): New.
14097 (vsudot_lane_s32): New.
14098 (vsudotq_lane_s32): New.
14099 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
14100 * config/arm/iterators.md (DOTPROD_I8MM): New.
14101 (sup, opsuffix): Add <us/su>.
14102 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
14103 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
14105 2020-02-11 Richard Biener <rguenther@suse.de>
14107 PR tree-optimization/93661
14108 PR tree-optimization/93662
14109 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard
14110 tree_to_poly_int64.
14111 * tree-sra.c (get_access_for_expr): Likewise.
14113 2020-02-10 Jakub Jelinek <jakub@redhat.com>
14116 * config/i386/sse.md (VI_256_AVX2): New mode iterator.
14117 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256.
14118 Change condition from TARGET_AVX2 to TARGET_AVX.
14120 2020-02-10 Iain Sandoe <iain@sandoe.co.uk>
14123 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last
14124 argument of strncmp.
14126 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
14128 Try to generate zero-based comparisons.
14129 * config/cris/cris.c (cris_reduce_compare): New function.
14130 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype.
14131 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4")
14132 (cstore<mode>4"): Apply cris_reduce_compare in expanders.
14134 2020-02-10 Richard Earnshaw <rearnsha@arm.com>
14137 * config/arm/arm.md (movsi_compare0): Allow SP as a source register
14138 in Thumb state and also as a destination in Arm state. Add T16
14141 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
14143 * md.texi (Define Subst): Match closing paren in example.
14145 2020-02-10 Jakub Jelinek <jakub@redhat.com>
14149 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last
14150 arguments of strncmp.
14152 2020-02-10 Feng Xue <fxue@os.amperecomputing.com>
14155 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge
14156 but different source value.
14157 (adjust_callers_for_value_intersection): New function.
14158 (gather_edges_for_value): Adjust order of callers to let a
14159 non-self-recursive caller be the first element.
14160 (self_recursive_pass_through_p): Add a new parameter "simple", and
14161 check generalized self-recursive pass-through jump function.
14162 (self_recursive_agg_pass_through_p): Likewise.
14163 (find_more_scalar_values_for_callers_subset): Compute value from
14164 pass-through jump function for self-recursive.
14165 (intersect_with_plats): Cleanup previous implementation code for value
14166 itersection with self-recursive call edge.
14167 (intersect_with_agg_replacements): Likewise.
14168 (intersect_aggregates_with_edge): Deduce value from pass-through jump
14169 function for self-recursive call edge. Cleanup previous implementation
14170 code for value intersection with self-recursive call edge.
14171 (decide_whether_version_node): Remove dead callers and adjust order
14172 to let a non-self-recursive caller be the first element.
14174 2020-02-09 Uroš Bizjak <ubizjak@gmail.com>
14176 * recog.c: Move pass_split_before_sched2 code in front of
14177 pass_split_before_regstack.
14178 (pass_data_split_before_sched2): Rename pass to split3 from split4.
14179 (pass_data_split_before_regstack): Rename pass to split4 from split3.
14180 (rest_of_handle_split_before_sched2): Remove.
14181 (pass_split_before_sched2::execute): Unconditionally call
14183 (enable_split_before_sched2): New function.
14184 (pass_split_before_sched2::gate): Use enable_split_before_sched2.
14185 (pass_split_before_regstack::gate): Ditto.
14186 * config/nds32/nds32.c (nds32_split_double_word_load_store_p):
14187 Update name check for renamed split4 pass.
14188 * config/sh/sh.c (register_sh_passes): Update pass insertion
14189 point for renamed split4 pass.
14191 2020-02-09 Jakub Jelinek <jakub@redhat.com>
14193 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote
14194 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid
14195 copying them around between host and target.
14197 2020-02-08 Andrew Pinski <apinski@marvell.com>
14200 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
14201 STRICT_ALIGNMENT also.
14203 2020-02-08 Jim Wilson <jimw@sifive.com>
14206 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
14208 2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
14209 Jakub Jelinek <jakub@redhat.com>
14212 * config/i386/i386.h (CALL_USED_REGISTERS): Make
14213 xmm16-xmm31 call-used even in 64-bit ms-abi.
14215 2020-02-07 Dennis Zhang <dennis.zhang@arm.com>
14217 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry.
14218 (simd_ummla, simd_usmmla): Likewise.
14219 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New.
14220 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New.
14221 (vusmmlaq_s32): New.
14223 2020-02-07 Richard Biener <rguenther@suse.de>
14225 PR middle-end/93519
14226 * tree-inline.c (fold_marked_statements): Do a PRE walk,
14227 skipping unreachable regions.
14228 (optimize_inline_calls): Skip folding stmts when we didn't
14231 2020-02-07 H.J. Lu <hongjiu.lu@intel.com>
14234 * config/i386/i386.c (function_arg_ms_64): Add a type argument.
14235 Don't return aggregates with only SFmode and DFmode in SSE
14237 (ix86_function_arg): Pass arg.type to function_arg_ms_64.
14239 2020-02-07 Jakub Jelinek <jakub@redhat.com>
14242 * config/rs6000/rs6000-logue.c
14243 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn,
14244 if it fails, move rs into end_addr and retry. Add
14245 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or
14246 the insn pattern doesn't describe well what exactly happens to
14250 * config/i386/predicates.md (avx_identity_operand): Remove.
14251 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove.
14252 (avx_<castmode><avxsizesuffix>_<castmode>,
14253 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to
14254 a VEC_CONCAT of the operand and UNSPEC_CAST.
14255 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to
14256 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with
14260 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear
14261 recog_data.insn if distance_non_agu_define changed it.
14263 2020-02-06 Michael Meissner <meissner@linux.ibm.com>
14266 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
14267 we only had X-FORM (reg+reg) addressing for vectors. Also before
14268 ISA 3.0, we only had X-FORM addressing for scalars in the
14269 traditional Altivec registers.
14271 2020-02-06 <zhongyunde@huawei.com>
14272 Vladimir Makarov <vmakarov@redhat.com>
14274 PR rtl-optimization/93561
14275 * lra-assigns.c (spill_for): Check that tested hard regno is not out of
14276 hard register range.
14278 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14280 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type
14283 2020-02-06 Segher Boessenkool <segher@kernel.crashing.org>
14285 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case
14286 where the low and the high 32 bits are equal to each other specially,
14287 with an rldimi instruction.
14289 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14291 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main.
14293 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14295 * config/arm/arm-tables.opt: Regenerate.
14297 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14300 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
14301 * config/aarch64/aarch64.c (aarch64_movk_shift): New function.
14302 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
14304 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14306 PR rtl-optimization/87763
14307 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
14309 2020-02-06 Delia Burduv <delia.burduv@arm.com>
14311 * config/aarch64/aarch64-simd-builtins.def
14312 (bfmlaq): New built-in function.
14313 (bfmlalb): New built-in function.
14314 (bfmlalt): New built-in function.
14315 (bfmlalb_lane): New built-in function.
14316 (bfmlalt_lane): New built-in function.
14317 * config/aarch64/aarch64-simd.md
14318 (aarch64_bfmmlaqv4sf): New pattern.
14319 (aarch64_bfmlal<bt>v4sf): New pattern.
14320 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern.
14321 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic.
14322 (vbfmlalbq_f32): New intrinsic.
14323 (vbfmlaltq_f32): New intrinsic.
14324 (vbfmlalbq_lane_f32): New intrinsic.
14325 (vbfmlaltq_lane_f32): New intrinsic.
14326 (vbfmlalbq_laneq_f32): New intrinsic.
14327 (vbfmlaltq_laneq_f32): New intrinsic.
14328 * config/aarch64/iterators.md (BF_MLA): New int iterator.
14329 (bt): New int attribute.
14331 2020-02-06 Uroš Bizjak <ubizjak@gmail.com>
14333 * config/i386/i386.md (*pushtf): Emit "#" instead of
14334 calling gcc_unreachable in insn output.
14337 (*pushsf_rex64): Ditto for alternatives other than 1.
14338 (*pushsf): Ditto for alternatives other than 1.
14340 2020-02-06 Martin Liska <mliska@suse.cz>
14342 PR gcov-profile/91971
14343 PR gcov-profile/93466
14344 * coverage.c (coverage_init): Revert mangling of
14345 path into filename. It can lead to huge filename length.
14346 Creation of subfolders seem more natural.
14348 2020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14351 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New.
14352 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs.
14353 Use arm_block_arith_comp_libfuncs_for_mode for HFmode.
14355 2020-02-06 Jakub Jelinek <jakub@redhat.com>
14358 * config/i386/predicates.md (avx_identity_operand): New predicate.
14359 * config/i386/sse.md (*avx_vec_concat<mode>_1): New
14360 define_insn_and_split.
14363 * omp-low.c (use_pointer_for_field): For nested constructs, also
14364 look for map clauses on target construct.
14365 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily
14366 taskreg_nesting_level.
14369 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding
14370 shared clause, call omp_notice_variable on outer context if any.
14372 2020-02-05 Jason Merrill <jason@redhat.com>
14375 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has
14376 non-zero address even if weak and not yet defined.
14378 2020-02-05 Martin Sebor <msebor@redhat.com>
14380 PR tree-optimization/92765
14381 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL.
14382 * tree-ssa-strlen.c (compute_string_length): Remove.
14383 (determine_min_objsize): Remove.
14384 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic.
14385 Avoid using type size as the upper bound on string length.
14386 (handle_builtin_string_cmp): Add an argument. Adjust.
14387 (strlen_check_and_optimize_call): Pass additional argument to
14388 handle_builtin_string_cmp.
14390 2020-02-05 Uroš Bizjak <ubizjak@gmail.com>
14392 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove.
14393 (*pushdi2_rex64 peephole2): Unconditionally split after
14394 epilogue_completed.
14395 (*ashl<mode>3_doubleword): Ditto.
14396 (*<shift_insn><mode>3_doubleword): Ditto.
14398 2020-02-05 Michael Meissner <meissner@linux.ibm.com>
14401 * config/rs6000/rs6000.c (get_vector_offset): Fix
14403 2020-02-05 Andrew Stubbs <ams@codesourcery.com>
14405 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
14407 2020-02-05 David Malcolm <dmalcolm@redhat.com>
14409 * doc/analyzer.texi
14410 (Special Functions for Debugging the Analyzer): Update description
14411 of __analyzer_dump_exploded_nodes.
14413 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14416 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
14417 include sets and not clobbers in the vzeroupper pattern.
14418 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
14419 the parallel has 17 (64-bit) or 9 (32-bit) elts.
14420 (*avx_vzeroupper_1): New define_insn_and_split.
14423 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets,
14424 don't run when !optimize.
14425 (pass_split_before_regstack::gate): For STACK_REGS targets, run even
14428 2020-02-05 Richard Biener <rguenther@suse.de>
14430 PR middle-end/90648
14431 * genmatch.c (dt_node::gen_kids_1): Emit number of argument
14432 checks before matching calls.
14434 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14436 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up
14437 function comment typo.
14439 PR middle-end/93555
14440 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or
14441 simd_clone_create failed when i == 0, adjust clone->nargs by
14444 2020-02-05 Martin Liska <mliska@suse.cz>
14447 * doc/invoke.texi: Document that one should
14448 not combine ASLR and -fpch.
14450 2020-02-04 Richard Biener <rguenther@suse.de>
14452 PR tree-optimization/93538
14453 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr.
14455 2020-02-04 Richard Biener <rguenther@suse.de>
14457 PR tree-optimization/91123
14458 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
14459 (vn_walk_cb_data::last_vuse): New member.
14460 (vn_walk_cb_data::saved_operands): Likewsie.
14461 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
14462 (vn_walk_cb_data::push_partial_def): Use finish.
14463 (vn_reference_lookup_2): Update last_vuse and use finish if
14464 we've saved operands.
14465 (vn_reference_lookup_3): Use finish and update calls to
14466 push_partial_defs everywhere. When translating through
14467 memcpy or aggregate copies save off operands and alias-set.
14468 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
14469 operation for redundant store removal.
14471 2020-02-04 Richard Biener <rguenther@suse.de>
14473 PR tree-optimization/92819
14474 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
14475 generating more stmts than before.
14477 2020-02-04 Martin Liska <mliska@suse.cz>
14479 * config/arm/arm.c (arm_gen_far_branch): Move the function
14480 outside of selftests.
14482 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14484 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
14485 function to adjust PC-relative vector addresses.
14486 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
14487 handle vectors with PC-relative addresses.
14489 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14491 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
14493 (hard_reg_and_mode_to_addr_mask): Delete.
14494 (rs6000_adjust_vec_address): If the original vector address
14495 was REG+REG or REG+OFFSET and the element is not zero, do the add
14496 of the elements in the original address before adding the offset
14497 for the vector element. Use address_to_insn_form to validate the
14498 address using the register being loaded, rather than guessing
14499 whether the address is a DS-FORM or DQ-FORM address.
14501 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14503 * config/rs6000/rs6000.c (get_vector_offset): New helper function
14504 to calculate the offset in memory from the start of a vector of a
14505 particular element. Add code to keep the element number in
14506 bounds if the element number is variable.
14507 (rs6000_adjust_vec_address): Move calculation of offset of the
14508 vector element to get_vector_offset.
14509 (rs6000_split_vec_extract_var): Do not do the initial AND of
14510 element here, move the code to get_vector_offset.
14512 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14514 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
14517 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
14519 * config/rs6000/constraints.md: Improve documentation.
14521 2020-02-03 Richard Earnshaw <rearnsha@arm.com>
14524 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md)
14525 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
14527 2020-02-03 Andrew Stubbs <ams@codesourcery.com>
14529 * config.gcc: Remove "carrizo" support.
14530 * config/gcn/gcn-opts.h (processor_type): Likewise.
14531 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
14532 * config/gcn/gcn.opt (gpu_type): Likewise.
14533 * config/gcn/t-omp-device: Likewise.
14535 2020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14538 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
14539 * config/arm/arm.c (arm_gen_far_branch): New function
14540 arm_gen_far_branch.
14541 * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
14543 2020-02-03 Julian Brown <julian@codesourcery.com>
14544 Tobias Burnus <tobias@codesourcery.com>
14546 * doc/invoke.texi: Update mention of OpenACC version to 2.6.
14548 2020-02-03 Jakub Jelinek <jakub@redhat.com>
14551 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
14552 valid RTL to sum up the lowest and second lowest bytes of the popcnt
14555 2020-02-02 Vladimir Makarov <vmakarov@redhat.com>
14557 PR rtl-optimization/91333
14558 * ira-color.c (struct allocno_color_data): Add member
14560 (init_allocno_threads): Set the member up.
14561 (bucket_allocno_compare_func): Add compare hard reg
14564 2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
14566 nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
14568 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14569 * config.in: Regenerated.
14570 * configure: Regenerated.
14571 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
14572 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14573 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.
14575 2020-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
14577 * configure: Regenerate.
14579 2020-01-31 Vladimir Makarov <vmakarov@redhat.com>
14581 PR rtl-optimization/91333
14582 * ira-color.c (bucket_allocno_compare_func): Move conflict hard
14583 reg preferences comparison up.
14585 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14587 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
14588 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
14589 aarch64-sve-builtins-base.h.
14590 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
14591 aarch64-sve-builtins-base.cc.
14592 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
14593 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14594 (svcvtnt): Declare.
14595 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
14596 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14597 (svcvtnt): New functions.
14598 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
14599 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14600 (svcvtnt): New functions.
14601 (svcvt): Add a form that converts f32 to bf16.
14602 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
14603 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
14605 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
14606 Treat B as bfloat16_t.
14607 (ternary_bfloat_lane_base): New class.
14608 (ternary_bfloat_def): Likewise.
14609 (ternary_bfloat): New shape.
14610 (ternary_bfloat_lane_def): New class.
14611 (ternary_bfloat_lane): New shape.
14612 (ternary_bfloat_lanex2_def): New class.
14613 (ternary_bfloat_lanex2): New shape.
14614 (ternary_bfloat_opt_n_def): New class.
14615 (ternary_bfloat_opt_n): New shape.
14616 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
14617 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
14618 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
14619 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
14620 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14621 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14622 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
14623 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
14624 the pattern off the narrow mode instead of the wider one.
14625 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
14626 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
14627 (sve_fp_op): Handle them.
14628 (SVE_BFLOAT_TERNARY_LONG): New int itertor.
14629 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
14631 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14633 * config/aarch64/arm_sve.h: Include arm_bf16.h.
14634 * config/aarch64/aarch64-modes.def (BF): Move definition before
14635 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF.
14636 (SVE_MODES): Handle BF modes.
14637 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
14639 (aarch64_full_sve_mode): Likewise.
14640 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
14642 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
14643 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
14644 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
14645 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
14647 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
14649 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
14650 (TYPES_all_data): Add bf16.
14651 (TYPES_reinterpret1, TYPES_reinterpret): Likewise.
14652 (register_tuple_type): Increase buffer size.
14653 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
14654 (bf16): New type suffix.
14655 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
14656 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
14657 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
14658 Change type from all_data to all_arith.
14659 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
14660 (svminp): Likewise.
14662 2020-01-31 Dennis Zhang <dennis.zhang@arm.com>
14663 Matthew Malcomson <matthew.malcomson@arm.com>
14664 Richard Sandiford <richard.sandiford@arm.com>
14666 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
14667 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
14668 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
14669 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define
14670 __ARM_FEATURE_MATMUL_FP64.
14671 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
14672 (sve): Add AARCH64_FL_F32MM to the list of extensions that should
14673 be disabled at the same time.
14674 (f32mm): New extension.
14675 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
14676 (AARCH64_FL_F64MM): Bump to the next bit up.
14677 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
14678 (TARGET_SVE_F64MM): New macros.
14679 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
14680 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
14681 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
14682 (UNSPEC_ZIP2Q): New unspeccs.
14683 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
14684 (optab, sur, perm_insn): Handle the new unspecs.
14685 (sve_fp_op): Handle UNSPEC_FMMLA. Resort.
14686 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
14687 TARGET_SVE_F64MM instead of separate tests.
14688 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
14689 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
14690 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
14691 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
14692 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
14693 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
14694 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
14695 (TYPES_s_signed): New macro.
14696 (TYPES_s_integer): Use it.
14697 (TYPES_d_float): New macro.
14698 (TYPES_d_data): Use it.
14699 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
14700 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
14701 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
14702 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
14703 (svmmla): New shape.
14704 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
14705 template parameters.
14706 (ternary_resize2_lane_base): Likewise.
14707 (ternary_resize2_base): New class.
14708 (ternary_qq_lane_base): Likewise.
14709 (ternary_intq_uintq_lane_def): Likewise.
14710 (ternary_intq_uintq_lane): New shape.
14711 (ternary_intq_uintq_opt_n_def): New class
14712 (ternary_intq_uintq_opt_n): New shape.
14713 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
14714 (ternary_uintq_intq_def): New class.
14715 (ternary_uintq_intq): New shape.
14716 (ternary_uintq_intq_lane_def): New class.
14717 (ternary_uintq_intq_lane): New shape.
14718 (ternary_uintq_intq_opt_n_def): New class.
14719 (ternary_uintq_intq_opt_n): New shape.
14720 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
14721 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
14722 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
14723 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
14725 (svdotprod_lane_impl): ...this new class.
14726 (svmmla_impl, svusdot_impl): New classes.
14727 (svdot_lane): Update to use svdotprod_lane_impl.
14728 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
14729 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
14731 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
14732 function, with no types defined.
14733 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
14734 AARCH64_FL_I8MM functions.
14735 (svmmla): New AARCH64_FL_F32MM function.
14736 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
14737 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
14738 AARCH64_FL_F64MM function.
14739 (REQUIRED_EXTENSIONS):
14741 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
14743 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
14746 2020-01-31 Uroš Bizjak <ubizjak@gmail.com>
14748 * config/i386/i386.md (*movoi_internal_avx): Do not check for
14749 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling.
14750 (*movti_internal): Do not check for
14751 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
14752 (*movtf_internal): Move check for TARGET_SSE2 and size optimization
14753 just after check for TARGET_AVX.
14754 (*movdf_internal): Ditto.
14755 * config/i386/mmx.md (*mov<mode>_internal): Do not check for
14756 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
14757 * config/i386/sse.md (mov<mode>_internal): Only check
14758 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check
14759 for TARGET_SSE2 and size optimization just after check for TARGET_AVX.
14760 (<sse>_andnot<mode>3<mask_name>): Move check for
14761 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX.
14762 (<code><mode>3<mask_name>): Ditto.
14763 (*andnot<mode>3): Ditto.
14764 (*andnottf3): Ditto.
14765 (*<code><mode>3): Ditto.
14766 (*<code>tf3): Ditto.
14767 (*andnot<VI:mode>3): Remove
14768 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling.
14769 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto.
14770 (*<code><VI12_AVX_AVX512F:mode>3): Ditto.
14771 (sse4_1_blendv<ssemodesuffix>): Ditto.
14772 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL):
14773 Explain that tune applies to 128bit instructions only.
14775 2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com>
14777 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count
14778 to definition of hsa_kernel_description. Parse assembly to find SGPR
14779 and VGPR count of kernel and store in hsa_kernel_description.
14781 2020-01-31 Tamar Christina <tamar.christina@arm.com>
14783 PR rtl-optimization/91838
14784 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case
14785 to truncate if allowed or reject combination.
14787 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
14789 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step.
14790 (find_inv_vars_cb): Likewise.
14792 2020-01-31 David Malcolm <dmalcolm@redhat.com>
14794 * calls.c (special_function_p): Split out the check for DECL_NAME
14795 being non-NULL and fndecl being extern at file scope into a
14796 new maybe_special_function_p and call it. Drop check for fndecl
14797 being non-NULL that was after a usage of DECL_NAME (fndecl).
14798 * tree.h (maybe_special_function_p): New inline function.
14800 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
14802 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ...
14803 (mask_gather_load<mode>): ... here, and zero-initialize the
14805 (maskload<mode>di): Zero-initialize the destination.
14806 * config/gcn/gcn.c:
14808 2020-01-30 David Malcolm <dmalcolm@redhat.com>
14811 * doc/analyzer.texi (Limitations): Note that constraints on
14812 floating-point values are currently ignored.
14814 2020-01-30 Jakub Jelinek <jakub@redhat.com>
14817 * symtab.c (symtab_node::noninterposable_alias): If localalias
14818 already exists, but is not usable, append numbers after it until
14819 a unique name is found. Formatting fix.
14821 PR middle-end/93505
14822 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range
14825 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
14827 * config/gcn/gcn.c (print_operand): Handle LTGT.
14828 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
14830 2020-01-30 Richard Biener <rguenther@suse.de>
14832 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST
14833 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE.
14835 2020-01-30 John David Anglin <danglin@gcc.gnu.org>
14837 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers
14838 without a DECL in .data.rel.ro.local.
14840 2020-01-30 Jakub Jelinek <jakub@redhat.com>
14843 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4
14847 * config/i386/sse.md
14848 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
14849 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
14850 any_extend code iterator instead of always zero_extend.
14851 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
14852 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
14853 Use any_extend code iterator instead of always zero_extend.
14854 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
14855 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
14856 Use any_extend code iterator instead of always zero_extend.
14857 (*sse2_pmovmskb_ext): New define_insn.
14858 (*sse2_pmovmskb_ext_lt): New define_insn_and_split.
14861 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
14862 (*popcountsi2_zext_falsedep): New define_insn.
14864 2020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
14866 * config.in: Regenerated.
14867 * configure: Regenerated.
14869 2020-01-29 Tobias Burnus <tobias@codesourcery.com>
14872 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as
14873 LLVM's assembler changed the default in version 9.
14875 2020-01-24 Jeff Law <law@redhat.com>
14877 PR tree-optimization/89689
14878 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure.
14880 2020-01-29 Richard Sandiford <richard.sandiford@arm.com>
14884 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
14886 PR rtl-optimization/87763
14887 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
14888 simplification to handle subregs as well as bare regs.
14889 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
14891 2020-01-29 Joel Hutton <Joel.Hutton@arm.com>
14894 * ira.c (ira): Revert use of simplified LRA algorithm.
14896 2020-01-29 Martin Jambor <mjambor@suse.cz>
14898 PR tree-optimization/92706
14899 * tree-sra.c (struct access): Fields first_link, last_link,
14900 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link,
14901 next_rhs_queued and grp_rhs_queued respectively, new fields
14902 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued.
14903 (struct assign_link): Field next renamed to next_rhs, new field
14904 next_lhs. Updated comment.
14905 (work_queue_head): Renamed to rhs_work_queue_head.
14906 (lhs_work_queue_head): New variable.
14907 (add_link_to_lhs): New function.
14908 (relink_to_new_repr): Also relink LHS lists.
14909 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue.
14910 (add_access_to_lhs_work_queue): New function.
14911 (pop_access_from_work_queue): Renamed to
14912 pop_access_from_rhs_work_queue.
14913 (pop_access_from_lhs_work_queue): New function.
14914 (build_accesses_from_assign): Also add links to LHS lists and to LHS
14916 (child_would_conflict_in_lacc): Renamed to
14917 child_would_conflict_in_acc. Adjusted parameter names.
14918 (create_artificial_child_access): New parameter set_grp_read, use it.
14919 (subtree_mark_written_and_enqueue): Renamed to
14920 subtree_mark_written_and_rhs_enqueue.
14921 (propagate_subaccesses_across_link): Renamed to
14922 propagate_subaccesses_from_rhs.
14923 (propagate_subaccesses_from_lhs): New function.
14924 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to
14927 2020-01-29 Martin Jambor <mjambor@suse.cz>
14929 PR tree-optimization/92706
14930 * tree-sra.c (struct access): Adjust comment of
14931 grp_total_scalarization.
14932 (find_access_in_subtree): Look for single children spanning an entire
14934 (scalarizable_type_p): Allow register accesses, adjust callers.
14935 (completely_scalarize): Remove function.
14936 (scalarize_elem): Likewise.
14937 (create_total_scalarization_access): Likewise.
14938 (sort_and_splice_var_accesses): Do not track total scalarization
14940 (analyze_access_subtree): New parameter totally, adjust to new meaning
14941 of grp_total_scalarization.
14942 (analyze_access_trees): Pass new parameter to analyze_access_subtree.
14943 (can_totally_scalarize_forest_p): New function.
14944 (create_total_scalarization_access): Likewise.
14945 (create_total_access_and_reshape): Likewise.
14946 (total_should_skip_creating_access): Likewise.
14947 (totally_scalarize_subtree): Likewise.
14948 (analyze_all_variable_accesses): Perform total scalarization after
14949 subaccess propagation using the new functions above.
14950 (initialize_constant_pool_replacements): Output initializers by
14951 traversing the access tree.
14953 2020-01-29 Martin Jambor <mjambor@suse.cz>
14955 * tree-sra.c (verify_sra_access_forest): New function.
14956 (verify_all_sra_access_forests): Likewise.
14957 (create_artificial_child_access): Set parent.
14958 (analyze_all_variable_accesses): Call the verifier.
14960 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14962 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge
14963 if called on indirect edge.
14964 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of
14965 speculative call if needed.
14967 2020-01-29 Richard Biener <rguenther@suse.de>
14969 PR tree-optimization/93428
14970 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load
14971 permutation when the load node is created.
14972 (vect_analyze_slp_instance): Re-use it here.
14974 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14976 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning.
14978 2020-01-28 Vladimir Makarov <vmakarov@redhat.com>
14980 PR rtl-optimization/93272
14981 * ira-lives.c (process_out_of_region_eh_regs): New function.
14982 (process_bb_node_lives): Call it.
14984 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14986 * coverage.c (read_counts_file): Make error message lowercase.
14988 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14990 * profile-count.c (profile_quality_display_names): Fix ordering.
14992 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
14995 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site
14996 hash only when edge is first within the sequence.
14997 (cgraph_edge::set_call_stmt): Update handling of speculative calls.
14998 (symbol_table::create_edge): Do not set target_prob.
14999 (cgraph_edge::remove_caller): Watch for speculative calls when updating
15000 the call site hash.
15001 (cgraph_edge::make_speculative): Drop target_prob parameter.
15002 (cgraph_edge::speculative_call_info): Remove.
15003 (cgraph_edge::first_speculative_call_target): New member function.
15004 (update_call_stmt_hash_for_removing_direct_edge): New function.
15005 (cgraph_edge::resolve_speculation): Rewrite to new API.
15006 (cgraph_edge::speculative_call_for_target): New member function.
15007 (cgraph_edge::make_direct): Rewrite to new API; fix handling of
15008 multiple speculation targets.
15009 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating
15011 (verify_speculative_call): Verify that targets form an interval.
15012 * cgraph.h (cgraph_edge::speculative_call_info): Remove.
15013 (cgraph_edge::first_speculative_call_target): New member function.
15014 (cgraph_edge::next_speculative_call_target): New member function.
15015 (cgraph_edge::speculative_call_target_ref): New member function.
15016 (cgraph_edge;:speculative_call_indirect_edge): New member funtion.
15017 (cgraph_edge): Remove target_prob.
15018 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
15019 Fix handling of speculative calls.
15020 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals.
15021 * ipa-fnsummary.c (analyze_function_body): Likewise.
15022 * ipa-inline.c (speculation_useful_p): Use new speculative call API.
15023 * ipa-profile.c (dump_histogram): Fix formating.
15024 (ipa_profile_generate_summary): Watch for overflows.
15025 (ipa_profile): Do not require probablity to be 1/2; update to new API.
15026 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API.
15027 (update_indirect_edges_after_inlining): Update to new API.
15028 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call
15030 * profile-count.h: (profile_probability::adjusted): New.
15031 * tree-inline.c (copy_bb): Update to new speculative call API; fix
15032 updating of profile.
15033 * value-prof.c (gimple_ic_transform): Rename to ...
15034 (dump_ic_profile): ... this one; update dumping.
15035 (stream_in_histogram_value): Fix formating.
15036 (gimple_value_profile_transformations): Update.
15038 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
15041 * config/i386/i386.md (*movoi_internal_avx): Remove
15042 TARGET_SSE_TYPELESS_STORES check.
15043 (*movti_internal): Prefer TARGET_AVX over
15044 TARGET_SSE_TYPELESS_STORES.
15045 (*movtf_internal): Likewise.
15046 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over
15047 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check
15048 from TARGET_SSE_TYPELESS_STORES.
15050 2020-01-28 David Malcolm <dmalcolm@redhat.com>
15052 * diagnostic-core.h (warning_at): Rename overload to...
15053 (warning_meta): ...this.
15054 (emit_diagnostic_valist): Delete decl of overload taking
15055 diagnostic_metadata.
15056 * diagnostic.c (emit_diagnostic_valist): Likewise for defn.
15057 (warning_at): Rename overload taking diagnostic_metadata to...
15058 (warning_meta): ...this.
15060 2020-01-28 Richard Biener <rguenther@suse.de>
15062 PR tree-optimization/93439
15063 * tree-parloops.c (create_loop_fn): Move clique bookkeeping...
15064 * tree-cfg.c (move_sese_region_to_fn): ... here.
15065 (verify_types_in_gimple_reference): Verify used cliques are
15068 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
15071 * config/i386/i386-options.c (set_ix86_tune_features): Add an
15072 argument of a pointer to struct gcc_options and pass it to
15073 parse_mtune_ctrl_str.
15074 (ix86_function_specific_restore): Pass opts to
15075 set_ix86_tune_features.
15076 (ix86_option_override_internal): Likewise.
15077 (parse_mtune_ctrl_str): Add an argument of a pointer to struct
15078 gcc_options and use it for x_ix86_tune_ctrl_string.
15080 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15082 PR rtl-optimization/87763
15083 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
15084 simplification to handle subregs as well as bare regs.
15085 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
15087 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15089 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully
15090 for reduction chains that (now) include a call.
15092 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15094 PR tree-optimization/92822
15095 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling
15096 out the don't-care elements of a vector whose significant elements
15097 are duplicates, make the don't-care elements duplicates too.
15099 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15101 PR tree-optimization/93434
15102 * tree-predcom.c (split_data_refs_to_components): Record which
15103 components have had aliasing loads removed. Prevent store-store
15104 commoning for all such components.
15106 2020-01-28 Jakub Jelinek <jakub@redhat.com>
15109 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not
15110 -1 or is_vshift is true, use new_vector with number of elts npatterns
15111 rather than new_unary_operation.
15113 PR tree-optimization/93454
15114 * gimple-fold.c (fold_array_ctor_reference): Perform
15115 elt_size.to_uhwi () just once, instead of calling it in every
15116 iteration. Punt if that value is above size of the temporary
15117 buffer. Decrease third native_encode_expr argument when
15118 bufoff + elt_sz is above size of buf.
15120 2020-01-27 Joseph Myers <joseph@codesourcery.com>
15122 * config/mips/mips.c (mips_declare_object_name)
15123 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object.
15125 2020-01-27 Martin Liska <mliska@suse.cz>
15127 PR gcov-profile/93403
15128 * tree-profile.c (gimple_init_gcov_profiler): Generate
15129 both __gcov_indirect_call_profiler_v4 and
15130 __gcov_indirect_call_profiler_v4_atomic.
15132 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15135 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
15137 (@aarch64_split_simd_mov<mode>): Use it.
15138 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
15139 Leave the vec_extract patterns to handle 2-element vectors.
15140 (aarch64_simd_mov_from_<mode>high): Likewise.
15141 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
15142 (vec_extractv2dfv1df): Likewise.
15144 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15146 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
15147 jump conditions for *compare_condjump<GPI:mode>.
15149 2020-01-27 David Malcolm <dmalcolm@redhat.com>
15152 * digraph.cc (test_edge::test_edge): Specify template for base
15155 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15157 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
15159 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15161 * config/arc/arc-protos.h (gen_mlo): Remove.
15162 (gen_mhi): Likewise.
15163 * config/arc/arc.c (AUX_MULHI): Define.
15164 (arc_must_save_reister): Special handling for r58/59.
15165 (arc_compute_frame_size): Consider mlo/mhi registers.
15166 (arc_save_callee_saves): Emit fp/sp move only when emit_move
15168 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
15169 mlo/mhi name selection.
15170 (arc_restore_callee_saves): Don't early restore blink when ISR.
15171 (arc_expand_prologue): Add mlo/mhi saving.
15172 (arc_expand_epilogue): Add mlo/mhi restoring.
15175 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
15176 numbering when MUL64 option is used.
15177 (DWARF2_FRAME_REG_OUT): Define.
15178 * config/arc/arc.md (arc600_stall): New pattern.
15179 (VUNSPEC_ARC_ARC600_STALL): Define.
15180 (mulsi64): Use correct mlo/mhi registers.
15181 (mulsi_600): Clean it up.
15182 * config/arc/predicates.md (mlo_operand): Remove any dependency on
15184 (mhi_operand): Likewise.
15186 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15187 Petro Karashchenko <petro.karashchenko@ring.com>
15189 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct
15190 attributes if needed.
15191 (prepare_move_operands): Generate special unspec instruction for
15193 (arc_isuncached_mem_p): Propagate uncached attribute to each
15195 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
15196 (VUNSPEC_ARC_STDI): Likewise.
15197 (ALLI): New mode iterator.
15198 (mALLI): New mode attribute.
15199 (lddi): New instruction pattern.
15201 (stdidi_split): Split instruction for architectures which are not
15202 supporting ll64 option.
15203 (lddidi_split): Likewise.
15205 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15207 PR rtl-optimization/92989
15208 * lra-lives.c (process_bb_lives): Update the live-in set before
15209 processing additional clobbers.
15211 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15213 PR rtl-optimization/93170
15214 * cselib.c (cselib_invalidate_regno_val): New function, split out
15216 (cselib_invalidate_regno): ...here.
15217 (cselib_invalidated_by_call_p): New function.
15218 (cselib_process_insn): Iterate over all the hard-register entries in
15219 REG_VALUES and invalidate any that cross call-clobbered registers.
15221 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15223 * dojump.c (split_comparison): Use HONOR_NANS rather than
15224 HONOR_SNANS when splitting LTGT.
15226 2020-01-27 Martin Liska <mliska@suse.cz>
15229 * opts.c (print_filtered_help): Exclude language-specific
15230 options from --help=common unless enabled in all FEs.
15232 2020-01-27 Martin Liska <mliska@suse.cz>
15234 * opts.c (print_help): Exclude params from
15235 all except --help=param.
15237 2020-01-27 Martin Liska <mliska@suse.cz>
15240 * config/i386/i386-features.c (make_resolver_func):
15241 Align the code with ppc64 target implementation.
15242 Do not generate a unique name for resolver function.
15244 2020-01-27 Richard Biener <rguenther@suse.de>
15246 PR tree-optimization/93397
15247 * tree-vect-slp.c (vect_analyze_slp_instance): Delay
15248 converted reduction chain SLP graph adjustment.
15250 2020-01-26 Marek Polacek <polacek@redhat.com>
15253 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
15256 2020-01-26 Jason Merrill <jason@redhat.com>
15259 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
15262 2020-01-26 Darius Galis <darius.galis@cyberthorstudios.com>
15264 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
15265 (rx_setmem): Likewise.
15267 2020-01-26 Jakub Jelinek <jakub@redhat.com>
15270 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
15271 Use nonimmediate_operand instead of x86_64_hilo_general_operand and
15272 drop <di> from constraint of last operand.
15275 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
15276 TARGET_AVX2 and V4DFmode not in the split condition, but in the
15277 pattern condition, though allow { 0, 0, 0, 0 } broadcast always.
15279 2020-01-25 Feng Xue <fxue@os.amperecomputing.com>
15282 * ipa-cp.c (get_info_about_necessary_edges): Remove value
15285 2020-01-24 Jeff Law <law@redhat.com>
15287 PR tree-optimization/92788
15288 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX
15291 2020-01-24 Jakub Jelinek <jakub@redhat.com>
15294 * config/i386/sse.md (*avx_vperm_broadcast_v4sf,
15295 *avx_vperm_broadcast_<mode>,
15296 <sse2_avx_avx512f>_vpermil<mode><mask_name>,
15297 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>):
15298 Move before avx2_perm<mode>/avx512f_perm<mode>.
15301 * simplify-rtx.c (simplify_const_unary_operation,
15302 simplify_const_binary_operation): Punt for mode precision above
15303 MAX_BITSIZE_MODE_ANY_INT.
15305 2020-01-24 Andrew Pinski <apinski@marvell.com>
15307 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change
15308 alu.shift_reg to 0.
15310 2020-01-24 Jeff Law <law@redhat.com>
15313 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg
15314 for REGs. Call output_operand_lossage to get more reasonable
15317 2020-01-24 Andrew Stubbs <ams@codesourcery.com>
15319 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use
15320 gcn_fp_compare_operator.
15321 (vec_cmpu<mode>di): Use gcn_compare_operator.
15322 (vec_cmp<u>v64qidi): Use gcn_compare_operator.
15323 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator.
15324 (vec_cmpu<mode>di_exec): Use gcn_compare_operator.
15325 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator.
15326 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator.
15327 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator.
15328 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use
15329 gcn_fp_compare_operator.
15330 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use
15331 gcn_fp_compare_operator.
15332 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use
15333 gcn_fp_compare_operator.
15334 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use
15335 gcn_fp_compare_operator.
15337 2020-01-24 Maciej W. Rozycki <macro@wdc.com>
15339 * doc/install.texi (Cross-Compiler-Specific Options): Document
15340 `--with-toolexeclibdir' option.
15342 2020-01-24 Hans-Peter Nilsson <hp@axis.com>
15344 * target.def (flags_regnum): Also mention effect on delay slot filling.
15345 * doc/tm.texi: Regenerate.
15347 2020-01-23 Jeff Law <law@redhat.com>
15349 PR translation/90162
15350 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text.
15352 2020-01-23 Mikael Tillenius <mti-1@tillenius.com>
15355 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of
15358 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15360 PR rtl-optimization/93402
15361 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust
15364 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15366 * config.in: Regenerated.
15367 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
15368 for TARGET_LIBC_GNUSTACK.
15369 * configure: Regenerated.
15370 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
15371 found to be 2.31 or greater.
15373 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15375 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
15377 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
15378 (mips_asm_file_end): New function. Delegate to
15379 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
15380 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
15382 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15385 * config/i386/i386-modes.def (POImode): New mode.
15386 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160.
15387 * config/i386/i386.md (DPWI): New mode attribute.
15388 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>.
15389 (QWI): Rename to...
15390 (QPWI): ... this. Use POI instead of OI for TImode.
15391 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1,
15392 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI>
15395 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15398 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New
15400 (speculation_tracker_rev): New pattern.
15401 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation):
15402 Use speculation_tracker_rev to track the inverse condition.
15404 2020-01-23 Richard Biener <rguenther@suse.de>
15406 PR tree-optimization/93381
15407 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take
15408 alias-set of the def as argument and record the first one.
15409 (vn_walk_cb_data::first_set): New member.
15410 (vn_reference_lookup_3): Pass the alias-set of the current def
15411 to push_partial_def. Fix alias-set used in the aggregate copy
15413 (vn_reference_lookup): Consistently set *last_vuse_ptr.
15414 * real.c (clear_significand_below): Fix out-of-bound access.
15416 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15419 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3):
15420 New define_insn patterns.
15422 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15424 * doc/sourcebuild.texi (check-function-bodies): Add an
15425 optional target/xfail selector.
15427 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15429 PR rtl-optimization/93124
15430 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to
15431 bare USE and CLOBBER insns.
15433 2020-01-22 Andrew Pinski <apinski@marvell.com>
15435 * config/arc/arc.c (output_short_suffix): Check insn for nullness.
15437 2020-01-22 David Malcolm <dmalcolm@redhat.com>
15440 * gdbinit.in (break-on-saved-diagnostic): Update for move of
15441 diagnostic_manager into "ana" namespace.
15442 * selftest-run-tests.c (selftest::run_tests): Update for move of
15443 selftest::run_analyzer_selftests to
15444 ana::selftest::run_analyzer_selftests.
15446 2020-01-22 Richard Sandiford <richard.sandiford@arm.com>
15448 * cfgexpand.c (union_stack_vars): Update the size.
15450 2020-01-22 Richard Biener <rguenther@suse.de>
15452 PR tree-optimization/93381
15453 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting
15454 throughout, handle all conversions the same.
15456 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15459 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use
15460 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate
15461 predicate, not whenever it is CONST_INT. Otherwise, force_reg it.
15462 Call force_reg on high_in2 unconditionally.
15464 2020-01-22 Martin Liska <mliska@suse.cz>
15466 PR tree-optimization/92924
15467 * profile.c (compute_value_histograms): Divide
15468 all counter values.
15470 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15473 * output.h (assemble_name_resolve): Declare.
15474 * varasm.c (assemble_name_resolve): New function.
15475 (assemble_name): Use it.
15476 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define.
15478 2020-01-22 Joseph Myers <joseph@codesourcery.com>
15480 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to
15481 update_web_docs_git instead of update_web_docs_svn.
15483 2020-01-21 Andrew Pinski <apinski@marvell.com>
15486 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
15487 as PTR mode. Have operand 1 as being modeless, it can be P mode.
15488 (*tlsgd_small_<mode>): Likewise.
15489 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
15490 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
15491 register. Convert that register back to dest using convert_mode.
15493 2020-01-21 Jim Wilson <jimw@sifive.com>
15495 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
15498 2020-01-21 H.J. Lu <hongjiu.lu@intel.com>
15499 Uros Bizjak <ubizjak@gmail.com>
15502 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode
15504 (legitimize_tls_address): Do GNU2 TLS address computation in
15505 ptr_mode and zero-extend result to Pmode.
15506 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
15507 :P with :PTR and Pmode with ptr_mode.
15508 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
15509 (*tls_dynamic_gnu2_call_64_<mode>): Likewise.
15510 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise.
15512 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15515 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
15516 the last two operands are CONST_INT_P before using them as such.
15518 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15520 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
15521 to get the integer element types.
15523 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15525 * config/aarch64/aarch64-sve-builtins.h
15526 (function_expander::convert_to_pmode): Declare.
15527 * config/aarch64/aarch64-sve-builtins.cc
15528 (function_expander::convert_to_pmode): New function.
15529 (function_expander::get_contiguous_base): Use it.
15530 (function_expander::prepare_gather_address_operands): Likewise.
15531 * config/aarch64/aarch64-sve-builtins-sve2.cc
15532 (svwhilerw_svwhilewr_impl::expand): Likewise.
15534 2020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com>
15537 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set
15538 cfun->machine->label_is_assembled.
15539 (aarch64_print_patchable_function_entry): New.
15540 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
15541 * config/aarch64/aarch64.h (struct machine_function): New field,
15542 label_is_assembled.
15544 2020-01-21 David Malcolm <dmalcolm@redhat.com>
15547 * ipa-profile.c (ipa_profile): Delete call_sums and set it to
15550 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15553 * cgraph.c (cgraph_edge::resolve_speculation,
15554 cgraph_edge::redirect_call_stmt_to_callee): Fix update of
15555 call_stmt_site_hash.
15557 2020-01-21 Martin Liska <mliska@suse.cz>
15559 * config/rs6000/rs6000.c (common_mode_defined): Remove
15562 2020-01-21 Richard Biener <rguenther@suse.de>
15564 PR tree-optimization/92328
15565 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
15566 type when value-numbering same-sized store by inserting a
15568 (eliminate_dom_walker::eliminate_stmt): When eliminating
15569 a redundant store handle bit-reinterpretation of the same value.
15571 2020-01-21 Andrew Pinski <apinski@marvel.com>
15574 * tree-into-ssa.c (prepare_block_for_update_1): Split out
15576 (prepare_block_for_update): This. Use a worklist instead of
15579 2020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15581 * config/arm/arm.c (clear_operation_p):
15582 Initialise last_regno, skip first iteration
15583 based on the first_set value and use ints instead
15584 of the unnecessary HOST_WIDE_INTs.
15586 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15589 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
15590 compare_mode other than SFmode or DFmode.
15592 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
15595 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
15596 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
15597 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
15599 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15601 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
15603 2020-01-20 Andrew Pinski <apinski@marvell.com>
15605 PR middle-end/93242
15606 * targhooks.c (default_print_patchable_function_entry): Use
15607 output_asm_insn to emit the nop instruction.
15609 2020-01-20 Fangrui Song <maskray@google.com>
15611 PR middle-end/93194
15612 * targhooks.c (default_print_patchable_function_entry): Align to
15615 2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
15618 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to
15619 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode.
15620 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ...
15621 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P.
15622 (*tls_dynamic_gnu2_lea_64): Renamed to ...
15623 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P.
15624 Remove the {q} suffix from lea.
15625 (*tls_dynamic_gnu2_call_64): Renamed to ...
15626 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P.
15627 (*tls_dynamic_gnu2_combine_64): Renamed to ...
15628 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P.
15629 Pass Pmode to gen_tls_dynamic_gnu2_64.
15631 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15633 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
15635 2020-01-20 Richard Sandiford <richard.sandiford@arm.com>
15637 * config/aarch64/aarch64-sve-builtins-base.cc
15638 (svld1ro_impl::memory_vector_mode): Remove parameter name.
15640 2020-01-20 Richard Biener <rguenther@suse.de>
15643 * dwarf2out.c (prune_unused_types): Unconditionally mark
15644 called function DIEs.
15646 2020-01-20 Martin Liska <mliska@suse.cz>
15648 PR tree-optimization/93199
15649 * tree-eh.c (struct leh_state): Add
15650 new field outer_non_cleanup.
15651 (cleanup_is_dead_in): Pass leh_state instead
15652 of eh_region. Add a checking that state->outer_non_cleanup
15653 points to outer non-clean up region.
15654 (lower_try_finally): Record outer_non_cleanup
15656 (lower_catch): Likewise.
15657 (lower_eh_filter): Likewise.
15658 (lower_eh_must_not_throw): Likewise.
15659 (lower_cleanup): Likewise.
15661 2020-01-20 Richard Biener <rguenther@suse.de>
15663 PR tree-optimization/93094
15664 * tree-vectorizer.h (vect_loop_versioning): Adjust.
15665 (vect_transform_loop): Likewise.
15666 * tree-vectorizer.c (try_vectorize_loop_1): Pass down
15667 loop_vectorized_call to vect_transform_loop.
15668 * tree-vect-loop.c (vect_transform_loop): Pass down
15669 loop_vectorized_call to vect_loop_versioning.
15670 * tree-vect-loop-manip.c (vect_loop_versioning): Use
15671 the earlier discovered loop_vectorized_call.
15673 2020-01-19 Eric S. Raymond <esr@thyrsus.com>
15675 * doc/contribute.texi: Update for SVN -> Git transition.
15676 * doc/install.texi: Likewise.
15678 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15681 * cgraph.c (cgraph_edge::make_speculative): Increase number of
15682 speculative targets.
15683 (verify_speculative_call): New function
15684 (cgraph_node::verify_node): Use it.
15685 * ipa-profile.c (ipa_profile): Fix formating; do not set number of
15688 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15691 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting.
15692 (cgraph_edge::make_direct): Remove all indirect targets.
15693 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct..
15694 (cgraph_node::verify_node): Verify that only one call_stmt or
15695 lto_stmt_uid is set.
15696 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or
15698 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt.
15699 (lto_output_ref): Simplify streaming of stmt.
15700 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid.
15702 2020-01-18 Tamar Christina <tamar.christina@arm.com>
15704 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode):
15705 Mark parameter unused.
15707 2020-01-18 Hans-Peter Nilsson <hp@axis.com>
15709 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux*
15711 2019-01-18 Gerald Pfeifer <gerald@pfeifer.com>
15713 * varpool.c (ctor_useable_for_folding_p): Fix grammar.
15715 2020-01-18 Iain Sandoe <iain@sandoe.co.uk>
15717 * Makefile.in: Add coroutine-passes.o.
15718 * builtin-types.def (BT_CONST_SIZE): New.
15719 (BT_FN_BOOL_PTR): New.
15720 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New.
15721 * builtins.def (DEF_COROUTINE_BUILTIN): New.
15722 * coroutine-builtins.def: New file.
15723 * coroutine-passes.cc: New file.
15724 * function.h (struct GTY function): Add a bit to indicate that the
15725 function is a coroutine component.
15726 * internal-fn.c (expand_CO_FRAME): New.
15727 (expand_CO_YIELD): New.
15728 (expand_CO_SUSPN): New.
15729 (expand_CO_ACTOR): New.
15730 * internal-fn.def (CO_ACTOR): New.
15734 * passes.def: Add pass_coroutine_lower_builtins,
15735 pass_coroutine_early_expand_ifns.
15736 * tree-pass.h (make_pass_coroutine_lower_builtins): New.
15737 (make_pass_coroutine_early_expand_ifns): New.
15738 * doc/invoke.texi: Document the fcoroutines command line
15741 2020-01-18 Jakub Jelinek <jakub@redhat.com>
15743 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable.
15746 * config/arm/arm.c (clear_operation_p): Don't use REGNO until
15747 after checking the argument is a REG. Don't use REGNO (reg)
15748 again to set last_regno, reuse regno variable instead.
15750 2020-01-17 David Malcolm <dmalcolm@redhat.com>
15752 * doc/analyzer.texi (Limitations): Add note about NaN.
15754 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15755 Sudakshina Das <sudi.das@arm.com>
15757 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
15758 and valid immediate.
15759 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
15760 (lshrdi3): Generate thumb2_lsrl for valid immediates.
15761 * config/arm/constraints.md (Pg): New.
15762 * config/arm/predicates.md (long_shift_imm): New.
15763 (arm_reg_or_long_shift_imm): Likewise.
15764 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
15765 (thumb2_lsll): Likewise.
15766 (thumb2_lsrl): New.
15768 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15769 Sudakshina Das <sudi.das@arm.com>
15771 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
15772 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
15773 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
15774 register pairs for doubleword quantities for ARMv8.1M-Mainline.
15775 * config/arm/thumb2.md (thumb2_asrl): New.
15776 (thumb2_lsll): Likewise.
15778 2020-01-17 Jakub Jelinek <jakub@redhat.com>
15780 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
15783 2020-01-17 Alexander Monakov <amonakov@ispras.ru>
15785 * gdbinit.in (help-gcc-hooks): New command.
15786 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
15787 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
15790 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15792 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
15793 correct target macro.
15795 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15797 * config/aarch64/aarch64-protos.h
15798 (aarch64_sve_ld1ro_operand_p): New.
15799 * config/aarch64/aarch64-sve-builtins-base.cc
15800 (class load_replicate): New.
15801 (class svld1ro_impl): New.
15802 (class svld1rq_impl): Change to inherit from load_replicate.
15803 (svld1ro): New sve intrinsic function base.
15804 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
15805 New DEF_SVE_FUNCTION.
15806 * config/aarch64/aarch64-sve-builtins-base.h
15807 (svld1ro): New decl.
15808 * config/aarch64/aarch64-sve-builtins.cc
15809 (function_expander::add_mem_operand): Modify assert to allow
15811 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
15813 * config/aarch64/aarch64.c
15814 (aarch64_sve_ld1rq_operand_p): Implement in terms of ...
15815 (aarch64_sve_ld1rq_ld1ro_operand_p): This.
15816 (aarch64_sve_ld1ro_operand_p): New.
15817 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
15818 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
15819 * config/aarch64/predicates.md
15820 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New.
15822 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
15824 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
15825 Introduce this ACLE specified predefined macro.
15826 * config/aarch64/aarch64-option-extensions.def (f64mm): New.
15827 (fp): Disabling this disables f64mm.
15828 (simd): Disabling this disables f64mm.
15829 (fp16): Disabling this disables f64mm.
15830 (sve): Disabling this disables f64mm.
15831 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
15832 (AARCH64_ISA_F64MM): New.
15833 (TARGET_F64MM): New.
15834 * doc/invoke.texi (f64mm): Document new option.
15836 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
15838 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
15839 (neoversen1_tunings): Likewise.
15841 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
15844 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
15845 Add assert to ensure prolog has been emitted.
15846 (aarch64_split_atomic_op): Likewise.
15847 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
15848 Use epilogue_completed rather than reload_completed.
15849 (aarch64_atomic_exchange<mode>): Likewise.
15850 (aarch64_atomic_<atomic_optab><mode>): Likewise.
15851 (atomic_nand<mode>): Likewise.
15852 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
15853 (atomic_fetch_nand<mode>): Likewise.
15854 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
15855 (atomic_nand_fetch<mode>): Likewise.
15857 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
15860 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
15862 (REVERSE_CONDITION): Delete.
15863 * config/aarch64/iterators.md (CC_ONLY): New mode iterator.
15864 (CCFP_CCFPE): Likewise.
15865 (e): New mode attribute.
15866 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
15867 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
15868 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
15869 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
15870 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
15871 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
15872 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
15873 name of generator from gen_ccmpdi to gen_ccmpccdi.
15874 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse
15875 the previous comparison but aren't able to, use the new ccmp_rev
15878 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
15880 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
15881 than testing directly for INTEGER_CST.
15882 (gimplify_target_expr, gimplify_omp_depend): Likewise.
15884 2020-01-17 Jakub Jelinek <jakub@redhat.com>
15886 PR tree-optimization/93292
15887 * tree-vect-stmts.c (vectorizable_comparison): Punt also if
15888 get_vectype_for_scalar_type returns NULL.
15890 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
15892 * params.opt (-param=max-predicted-iterations): Increase range from 0.
15893 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.
15895 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
15897 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
15899 * params.opt: (max-predicted-iterations): Set bounds.
15900 * predict.c (real_almost_one, real_br_prob_base,
15901 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
15902 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic
15903 probabilities; do not truncate to reg_br_prob_bases.
15904 (estimate_loops_at_level): Pass max_cyclic_prob.
15905 (estimate_loops): Compute max_cyclic_prob.
15906 (estimate_bb_frequencies): Do not initialize real_*; update calculation
15908 * profile-count.c (profile_probability::to_sreal): New.
15909 * profile-count.h (class sreal): Move up in file.
15910 (profile_probability::to_sreal): Declare.
15912 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15915 (arm_invalid_conversion): New function for target hook.
15916 (arm_invalid_unary_op): New function for target hook.
15917 (arm_invalid_binary_op): New function for target hook.
15919 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
15921 * config.gcc: Add arm_bf16.h.
15922 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
15923 (arm_simd_builtin_std_type): Add BFmode.
15924 (arm_init_simd_builtin_types): Define element types for vector types.
15925 (arm_init_bf16_types): New function.
15926 (arm_init_builtins): Add arm_init_bf16_types function call.
15927 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
15928 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
15929 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
15930 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
15931 (arm_vector_mode_supported_p): Add V4BF, V8BF.
15932 (arm_mangle_type): Add __bf16.
15933 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
15934 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
15935 arm_bf16_ptr_type_node.
15936 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
15937 define_split between ARM registers.
15938 * config/arm/arm_bf16.h: New file.
15939 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
15940 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
15941 (VQXMOV): Add V8BF.
15942 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
15943 * config/arm/vfp.md: Add BFmode to movhf patterns.
15945 2020-01-16 Mihail Ionescu <mihail.ionescu@arm.com>
15946 Andre Vieira <andre.simoesdiasvieira@arm.com>
15948 * config/arm/arm-cpus.in (mve, mve_float): New features.
15949 (dsp, mve, mve.fp): New options.
15950 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
15951 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
15952 * doc/invoke.texi: Document the armv8.1-m mve and dps options.
15954 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15955 Thomas Preud'homme <thomas.preudhomme@arm.com>
15957 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
15959 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
15960 error for using -mcmse when targeting Armv8.1-M Mainline.
15962 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15963 Thomas Preud'homme <thomas.preudhomme@arm.com>
15965 * config/arm/arm.md (nonsecure_call_internal): Do not force memory
15966 address in r4 when targeting Armv8.1-M Mainline.
15967 (nonsecure_call_value_internal): Likewise.
15968 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
15969 a register match_operand again. Emit BLXNS when targeting
15970 Armv8.1-M Mainline.
15971 (nonsecure_call_value_reg_thumb2): Likewise.
15973 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15974 Thomas Preud'homme <thomas.preudhomme@arm.com>
15976 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
15977 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
15978 variable as true when floating-point ABI is not hard. Replace
15979 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
15980 Generate VLSTM and VLLDM instruction respectively before and
15981 after a function call to cmse_nonsecure_call function.
15982 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
15983 (VUNSPEC_VLLDM): Likewise.
15984 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
15985 (lazy_load_multiple_insn): Likewise.
15987 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15988 Thomas Preud'homme <thomas.preudhomme@arm.com>
15990 * config/arm/arm.c (vfp_emit_fstmd): Declare early.
15991 (arm_emit_vfp_multi_reg_pop): Likewise.
15992 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
15993 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and
15994 restore callee-saved VFP registers.
15996 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15997 Thomas Preud'homme <thomas.preudhomme@arm.com>
15999 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
16000 (cmse_nonsecure_call_clear_caller_saved): Rename into ...
16001 (cmse_nonsecure_call_inline_register_clear): This. Save and clear
16002 callee-saved GPRs as well as clear ip register before doing a nonsecure
16003 call then restore callee-saved GPRs after it when targeting
16004 Armv8.1-M Mainline.
16005 (arm_reorg): Adapt to function rename.
16007 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16008 Thomas Preud'homme <thomas.preudhomme@arm.com>
16010 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
16011 * config/arm/arm.c (clear_operation_p): Extend to be able to check a
16012 clear_vfp_multiple pattern based on a new vfp parameter.
16013 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
16014 targeting Armv8.1-M Mainline.
16015 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers
16016 unconditionally when targeting Armv8.1-M Mainline architecture. Check
16017 whether VFP registers are available before looking call_used_regs for a
16019 * config/arm/predicates.md (clear_multiple_operation): Adapt to change
16020 of prototype of clear_operation_p.
16021 (clear_vfp_multiple_operation): New predicate.
16022 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
16023 * config/arm/vfp.md (clear_vfp_multiple): New define_insn.
16025 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16026 Thomas Preud'homme <thomas.preudhomme@arm.com>
16028 * config/arm/arm-protos.h (clear_operation_p): Declare.
16029 * config/arm/arm.c (clear_operation_p): New function.
16030 (cmse_clear_registers): Generate clear_multiple instruction pattern if
16031 targeting Armv8.1-M Mainline or successor.
16032 (output_return_instruction): Only output APSR register clearing if
16033 Armv8.1-M Mainline instructions not available.
16034 (thumb_exit): Likewise.
16035 * config/arm/predicates.md (clear_multiple_operation): New predicate.
16036 * config/arm/thumb2.md (clear_apsr): New define_insn.
16037 (clear_multiple): Likewise.
16038 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.
16040 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16041 Thomas Preud'homme <thomas.preudhomme@arm.com>
16043 * config/arm/arm.c (fp_sysreg_names): Declare and define.
16044 (use_return_insn): Also return false for Armv8.1-M Mainline.
16045 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M
16046 Mainline instructions are available.
16047 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS
16048 when targeting Armv8.1-M Mainline Security Extensions.
16049 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
16050 Mainline entry function.
16051 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
16052 targeting Armv8.1-M Mainline or successor.
16053 (arm_expand_epilogue): Fix indentation of caller-saved register
16054 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline
16056 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
16057 (FP_SYSREGS): Likewise.
16058 (enum vfp_sysregs_encoding): Define enum.
16059 (fp_sysreg_names): Declare.
16060 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
16061 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
16062 (pop_fpsysreg_insn): Likewise.
16064 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16065 Thomas Preud'homme <thomas.preudhomme@arm.com>
16067 * config/arm/arm-cpus.in (armv8_1m_main): New feature.
16068 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
16069 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
16070 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
16071 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
16072 (ARMv8_1m_main): New feature group.
16073 (armv8.1-m.main): New architecture.
16074 * config/arm/arm-tables.opt: Regenerate.
16075 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
16076 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
16077 (arm_options_perform_arch_sanity_checks): Error out when targeting
16078 Armv8.1-M Mainline Security Extensions.
16079 * config/arm/arm.h (arm_arch8_1m_main): Declare.
16081 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16083 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
16084 aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
16085 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
16086 aarch64_bfdot_laneq): New.
16087 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
16088 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
16089 vbfdotq_laneq_f32): New.
16090 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
16091 VBFMLA_W, VBF): New.
16092 (isquadop): Add V4BF, V8BF.
16094 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16096 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
16097 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
16098 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
16099 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
16100 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
16101 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
16102 usdot_laneq, sudot_lane,sudot_laneq): New.
16103 * config/aarch64/aarch64-simd.md (aarch64_usdot): New.
16104 (aarch64_<sur>dot_lane): New.
16105 * config/aarch64/arm_neon.h (vusdot_s32): New.
16106 (vusdotq_s32): New.
16107 (vusdot_lane_s32): New.
16108 (vsudot_lane_s32): New.
16109 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
16110 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
16112 2020-01-16 Martin Liska <mliska@suse.cz>
16114 * value-prof.c (dump_histogram_value): Fix
16115 obvious spacing issue.
16117 2020-01-16 Andrew Pinski <apinski@marvell.com>
16119 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
16120 !storage_order_barrier_p.
16122 2020-01-16 Andrew Pinski <apinski@marvell.com>
16124 * sched-int.h (_dep): Add unused bit-field field for the padding.
16125 * sched-deps.c (init_dep_1): Init unused field.
16127 2020-01-16 Andrew Pinski <apinski@marvell.com>
16129 * optabs.h (create_expand_operand): Initialize target field also.
16131 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
16133 PR tree-optimization/92429
16134 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
16135 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
16137 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
16140 2020-01-16 Richard Sandiford <richard.sandiford@arm.com>
16142 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
16143 aarch64_sve_int_mode to each mode.
16145 2020-01-15 David Malcolm <dmalcolm@redhat.com>
16147 * doc/analyzer.texi (Overview): Add note about
16148 -fdump-ipa-analyzer.
16150 2020-01-15 Wilco Dijkstra <wdijkstr@arm.com>
16152 PR tree-optimization/93231
16153 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
16154 input_type is unsigned. Use tree_to_shwi for shift constant.
16155 Check CST_STRING element size is CHAR_TYPE_SIZE bits.
16156 (simplify_count_trailing_zeroes): Add test to handle known non-zero
16157 inputs more efficiently.
16159 2020-01-15 Uroš Bizjak <ubizjak@gmail.com>
16161 * config/i386/i386.md (*movsf_internal): Do not require
16162 SSE2 ISA for alternatives 14 and 15.
16164 2020-01-15 Richard Biener <rguenther@suse.de>
16166 PR middle-end/93273
16167 * tree-eh.c (sink_clobbers): If we already visited the destination
16168 block do not defer insertion.
16169 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
16170 the purpose of defered insertion.
16172 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16174 * BASE-VER: Bump to 10.0.1.
16176 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
16178 PR tree-optimization/93247
16179 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
16180 type of the stmt that we're going to vectorize.
16182 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
16184 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
16185 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
16188 2020-01-15 Martin Liska <mliska@suse.cz>
16190 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
16191 2 calls of streamer_read_hwi in a function call.
16193 2020-01-15 Richard Biener <rguenther@suse.de>
16195 * alias.c (record_alias_subset): Avoid redundant work when
16196 subset is already recorded.
16198 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16200 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
16201 the analyzer options provide CWE identifiers.
16203 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16205 * tree-diagnostic-path.cc (path_summary::event_range::print):
16206 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
16207 using get_pure_location.
16209 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16211 PR tree-optimization/93262
16212 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
16213 perform head trimming only if the last argument is constant,
16214 either all ones, or larger or equal to head trim, in the latter
16215 case decrease the last argument by head_trim.
16217 PR tree-optimization/93249
16218 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
16219 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to
16220 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
16221 perform head trim unless we can prove there are no '\0' chars
16222 from the source among the first head_trim chars.
16224 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16226 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.
16228 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16231 * config/i386/sse.md
16232 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1,
16233 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1,
16234 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1,
16235 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use
16236 just a single alternative instead of two, make operands 1 and 2
16239 2020-01-14 Jan Hubicka <hubicka@ucw.cz>
16242 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
16245 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16247 * Makefile.in (lang_opt_files): Add analyzer.opt.
16248 (ANALYZER_OBJS): New.
16249 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o,
16250 tristate.o and ANALYZER_OBJS.
16251 (TEXI_GCCINT_FILES): Add analyzer.texi.
16252 * common.opt (-fanalyzer): New driver option.
16253 * config.in: Regenerate.
16254 * configure: Regenerate.
16255 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option.
16256 (gccdepdir): Also create depdir for "analyzer" subdir.
16257 * digraph.cc: New file.
16258 * digraph.h: New file.
16259 * doc/analyzer.texi: New file.
16260 * doc/gccint.texi ("Static Analyzer") New menu item.
16261 (analyzer.texi): Include it.
16262 * doc/invoke.texi ("Static Analyzer Options"): New list and new section.
16263 ("Warning Options"): Add static analysis warnings to the list.
16264 (-Wno-analyzer-double-fclose): New option.
16265 (-Wno-analyzer-double-free): New option.
16266 (-Wno-analyzer-exposure-through-output-file): New option.
16267 (-Wno-analyzer-file-leak): New option.
16268 (-Wno-analyzer-free-of-non-heap): New option.
16269 (-Wno-analyzer-malloc-leak): New option.
16270 (-Wno-analyzer-possible-null-argument): New option.
16271 (-Wno-analyzer-possible-null-dereference): New option.
16272 (-Wno-analyzer-null-argument): New option.
16273 (-Wno-analyzer-null-dereference): New option.
16274 (-Wno-analyzer-stale-setjmp-buffer): New option.
16275 (-Wno-analyzer-tainted-array-index): New option.
16276 (-Wno-analyzer-use-after-free): New option.
16277 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option.
16278 (-Wno-analyzer-use-of-uninitialized-value): New option.
16279 (-Wanalyzer-too-complex): New option.
16280 (-fanalyzer-call-summaries): New warning.
16281 (-fanalyzer-checker=): New warning.
16282 (-fanalyzer-fine-grained): New warning.
16283 (-fno-analyzer-state-merge): New warning.
16284 (-fno-analyzer-state-purge): New warning.
16285 (-fanalyzer-transitivity): New warning.
16286 (-fanalyzer-verbose-edges): New warning.
16287 (-fanalyzer-verbose-state-changes): New warning.
16288 (-fanalyzer-verbosity=): New warning.
16289 (-fdump-analyzer): New warning.
16290 (-fdump-analyzer-callgraph): New warning.
16291 (-fdump-analyzer-exploded-graph): New warning.
16292 (-fdump-analyzer-exploded-nodes): New warning.
16293 (-fdump-analyzer-exploded-nodes-2): New warning.
16294 (-fdump-analyzer-exploded-nodes-3): New warning.
16295 (-fdump-analyzer-supergraph): New warning.
16296 * doc/sourcebuild.texi (dg-require-dot): New.
16297 (dg-check-dot): New.
16298 * gdbinit.in (break-on-saved-diagnostic): New command.
16299 * graphviz.cc: New file.
16300 * graphviz.h: New file.
16301 * ordered-hash-map-tests.cc: New file.
16302 * ordered-hash-map.h: New file.
16303 * passes.def (pass_analyzer): Add before
16304 pass_ipa_whole_program_visibility.
16305 * selftest-run-tests.c (selftest::run_tests): Call
16306 selftest::ordered_hash_map_tests_cc_tests.
16307 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New
16309 * shortest-paths.h: New file.
16310 * timevar.def (TV_ANALYZER): New timevar.
16311 (TV_ANALYZER_SUPERGRAPH): Likewise.
16312 (TV_ANALYZER_STATE_PURGE): Likewise.
16313 (TV_ANALYZER_PLAN): Likewise.
16314 (TV_ANALYZER_SCC): Likewise.
16315 (TV_ANALYZER_WORKLIST): Likewise.
16316 (TV_ANALYZER_DUMP): Likewise.
16317 (TV_ANALYZER_DIAGNOSTICS): Likewise.
16318 (TV_ANALYZER_SHORTEST_PATHS): Likewise.
16319 * tree-pass.h (make_pass_analyzer): New decl.
16320 * tristate.cc: New file.
16321 * tristate.h: New file.
16323 2020-01-14 Uroš Bizjak <ubizjak@gmail.com>
16326 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for
16327 alternatives 9 and 10.
16329 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16331 * attribs.c (excl_hash_traits::empty_zero_p): New static constant.
16332 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise.
16333 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise.
16334 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
16335 (selftest::hash_map_tests_c_tests): Call it.
16336 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p):
16337 New static constant, using the value of = H::empty_zero_p.
16338 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value
16339 from default_hash_traits <Value>.
16340 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value
16342 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise.
16343 * hash-table.h (hash_table::alloc_entries): Guard the loop of
16344 calls to mark_empty with !Descriptor::empty_zero_p.
16345 (hash_table::empty_slow): Conditionalize the memset call with a
16346 check that Descriptor::empty_zero_p; otherwise, loop through the
16347 entries calling mark_empty on them.
16348 * hash-traits.h (int_hash::empty_zero_p): New static constant.
16349 (pointer_hash::empty_zero_p): Likewise.
16350 (pair_hash::empty_zero_p): Likewise.
16351 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p):
16353 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise.
16354 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise.
16355 * profile.c (location_triplet_hash::empty_zero_p): Likewise.
16356 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise.
16357 (sanopt_tree_couple_hash::empty_zero_p): Likewise.
16358 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise.
16359 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise.
16360 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise.
16361 * tree-vectorizer.h
16362 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p):
16365 2020-01-14 Kewen Lin <linkw@gcc.gnu.org>
16367 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return,
16368 fix typo on return value.
16370 2020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
16373 * cgraph.c (symbol_table::create_edge): Init speculative_id and
16375 (cgraph_edge::make_speculative): Add param for setting speculative_id
16377 (cgraph_edge::speculative_call_info): Update comments and find reference
16378 by speculative_id for multiple indirect targets.
16379 (cgraph_edge::resolve_speculation): Decrease the speculations
16380 for indirect edge, drop it's speculative if not direct target
16381 left. Update comments.
16382 (cgraph_edge::redirect_call_stmt_to_callee): Likewise.
16383 (cgraph_node::dump): Print num_speculative_call_targets.
16384 (cgraph_node::verify_node): Don't report error if speculative
16385 edge not include statement.
16386 (cgraph_edge::num_speculative_call_targets_p): New function.
16387 * cgraph.h (int common_target_id): Remove.
16388 (int common_target_probability): Remove.
16389 (num_speculative_call_targets): New variable.
16390 (make_speculative): Add param for setting speculative_id.
16391 (cgraph_edge::num_speculative_call_targets_p): New declare.
16392 (target_prob): New variable.
16393 (speculative_id): New variable.
16394 * ipa-fnsummary.c (analyze_function_body): Create and duplicate
16395 call summaries for multiple speculative call targets.
16396 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id.
16397 * ipa-profile.c (struct speculative_call_target): New struct.
16398 (class speculative_call_summary): New class.
16399 (class speculative_call_summaries): New class.
16400 (call_sums): New variable.
16401 (ipa_profile_generate_summary): Generate indirect multiple targets summaries.
16402 (ipa_profile_write_edge_summary): New function.
16403 (ipa_profile_write_summary): Stream out indirect multiple targets summaries.
16404 (ipa_profile_dump_all_summaries): New function.
16405 (ipa_profile_read_edge_summary): New function.
16406 (ipa_profile_read_summary_section): New function.
16407 (ipa_profile_read_summary): Stream in indirect multiple targets summaries.
16408 (ipa_profile): Generate num_speculative_call_targets from
16410 * ipa-ref.h (speculative_id): New variable.
16411 * ipa-utils.c (ipa_merge_profiles): Update with target_prob.
16412 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and
16413 common_target_probability. Stream out speculative_id and
16414 num_speculative_call_targets.
16415 (input_edge): Likewise.
16416 * predict.c (dump_prediction): Remove edges count assert to be
16418 * symtab.c (symtab_node::create_reference): Init speculative_id.
16419 (symtab_node::clone_references): Clone speculative_id.
16420 (symtab_node::clone_referring): Clone speculative_id.
16421 (symtab_node::clone_reference): Clone speculative_id.
16422 (symtab_node::clear_stmts_in_references): Clear speculative_id.
16423 * tree-inline.c (copy_bb): Duplicate all the speculative edges
16424 if indirect call contains multiple speculative targets.
16425 * value-prof.h (check_ic_target): Remove.
16426 * value-prof.c (gimple_value_profile_transformations):
16427 Use void function gimple_ic_transform.
16428 * value-prof.c (gimple_ic_transform): Handle topn case.
16429 Fix comment typos. Change it to a void function.
16431 2020-01-13 Andrew Pinski <apinski@marvell.com>
16433 * config/aarch64/aarch64-cores.def (octeontx2): New define.
16434 (octeontx2t98): New define.
16435 (octeontx2t96): New define.
16436 (octeontx2t93): New define.
16437 (octeontx2f95): New define.
16438 (octeontx2f95n): New define.
16439 (octeontx2f95mm): New define.
16440 * config/aarch64/aarch64-tune.md: Regenerate.
16441 * doc/invoke.texi (-mcpu=): Document the new cpu types.
16443 2020-01-13 Jason Merrill <jason@redhat.com>
16445 PR c++/33799 - destroy return value if local cleanup throws.
16446 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR.
16448 2020-01-13 Martin Liska <mliska@suse.cz>
16450 * ipa-cp.c (get_max_overall_size): Use newly
16451 renamed param param_ipa_cp_unit_growth.
16452 * params.opt: Remove legacy param name.
16454 2020-01-13 Martin Sebor <msebor@redhat.com>
16456 PR tree-optimization/93213
16457 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul
16458 stores to be eliminated.
16460 2020-01-13 Martin Liska <mliska@suse.cz>
16462 * opts.c (print_help): Do not print CL_PARAM
16463 and CL_WARNING for CL_OPTIMIZATION.
16465 2020-01-13 Jonathan Wakely <jwakely@redhat.com>
16468 * doc/invoke.texi (Warning Options): Add caveat about some warnings
16469 depending on optimization settings.
16471 2020-01-13 Jakub Jelinek <jakub@redhat.com>
16473 PR tree-optimization/90838
16474 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16475 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro
16476 argument rather than to initialize temporary for targets that
16477 don't use the mode argument at all. Initialize ctzval to avoid
16480 2020-01-10 Thomas Schwinge <thomas@codesourcery.com>
16482 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition.
16483 * tree-core.h: Document it.
16484 * gimplify.c (gimplify_omp_workshare): Set it.
16485 * omp-low.c (lower_omp_target): Use it.
16486 * tree-pretty-print.c (dump_omp_clause): Print it.
16488 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>:
16489 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'.
16491 2020-01-10 David Malcolm <dmalcolm@redhat.com>
16493 * Makefile.in (OBJS): Add tree-diagnostic-path.o.
16494 * common.opt (fdiagnostics-path-format=): New option.
16495 (diagnostic_path_format): New enum.
16496 (fdiagnostics-show-path-depths): New option.
16497 * coretypes.h (diagnostic_event_id_t): New forward decl.
16498 * diagnostic-color.c (color_dict): Add "path".
16499 * diagnostic-event-id.h: New file.
16500 * diagnostic-format-json.cc (json_from_expanded_location): Make
16502 (json_end_diagnostic): Call context->make_json_for_path if it
16503 exists and the diagnostic has a path.
16504 (diagnostic_output_format_init): Clear context->print_path.
16505 * diagnostic-path.h: New file.
16506 * diagnostic-show-locus.c (colorizer::set_range): Special-case
16507 when printing a run of events in a diagnostic_path so that they
16508 all get the same color.
16509 (layout::m_diagnostic_path_p): New field.
16510 (layout::layout): Initialize it.
16511 (layout::print_any_labels): Don't colorize the label text for an
16512 event in a diagnostic_path.
16513 (gcc_rich_location::add_location_if_nearby): Add
16514 "restrict_to_current_line_spans" and "label" params. Pass the
16515 former to layout.maybe_add_location_range; pass the latter
16516 when calling add_range.
16517 * diagnostic.c: Include "diagnostic-path.h".
16518 (diagnostic_initialize): Initialize context->path_format and
16519 context->show_path_depths.
16520 (diagnostic_show_any_path): New function.
16521 (diagnostic_path::interprocedural_p): New function.
16522 (diagnostic_report_diagnostic): Call diagnostic_show_any_path.
16523 (simple_diagnostic_path::num_events): New function.
16524 (simple_diagnostic_path::get_event): New function.
16525 (simple_diagnostic_path::add_event): New function.
16526 (simple_diagnostic_event::simple_diagnostic_event): New ctor.
16527 (simple_diagnostic_event::~simple_diagnostic_event): New dtor.
16528 (debug): New overload taking a diagnostic_path *.
16529 * diagnostic.def (DK_DIAGNOSTIC_PATH): New.
16530 * diagnostic.h (enum diagnostic_path_format): New enum.
16531 (json::value): New forward decl.
16532 (diagnostic_context::path_format): New field.
16533 (diagnostic_context::show_path_depths): New field.
16534 (diagnostic_context::print_path): New callback field.
16535 (diagnostic_context::make_json_for_path): New callback field.
16536 (diagnostic_show_any_path): New decl.
16537 (json_from_expanded_location): New decl.
16538 * doc/invoke.texi (-fdiagnostics-path-format=): New option.
16539 (-fdiagnostics-show-path-depths): New option.
16540 (-fdiagnostics-color): Add "path" to description of default
16541 GCC_COLORS; describe it.
16542 (-fdiagnostics-format=json): Document how diagnostic paths are
16543 represented in the JSON output format.
16544 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
16545 Add optional params "restrict_to_current_line_spans" and "label".
16546 * opts.c (common_handle_option): Handle
16547 OPT_fdiagnostics_path_format_ and
16548 OPT_fdiagnostics_show_path_depths.
16549 * pretty-print.c: Include "diagnostic-event-id.h".
16550 (pp_format): Implement "%@" format code for printing
16551 diagnostic_event_id_t *.
16552 (selftest::test_pp_format): Add tests for "%@".
16553 * selftest-run-tests.c (selftest::run_tests): Call
16554 selftest::tree_diagnostic_path_cc_tests.
16555 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl.
16556 * toplev.c (general_init): Initialize global_dc->path_format and
16557 global_dc->show_path_depths.
16558 * tree-diagnostic-path.cc: New file.
16559 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make
16560 non-static. Drop "diagnostic" param in favor of storing the
16561 original value of "where" and re-using it.
16562 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of
16563 maybe_unwind_expanded_macro_loc.
16564 (tree_diagnostics_defaults): Initialize context->print_path and
16565 context->make_json_for_path.
16566 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New
16568 (default_tree_make_json_for_path): New decl.
16569 (maybe_unwind_expanded_macro_loc): New decl.
16571 2020-01-10 Jakub Jelinek <jakub@redhat.com>
16573 PR tree-optimization/93210
16574 * fold-const.h (native_encode_initializer,
16575 can_native_interpret_type_p): Declare.
16576 * fold-const.c (native_encode_string): Fix up handling with off != -1,
16578 (native_encode_initializer): New function, moved from dwarf2out.c.
16579 Adjust to native_encode_expr compatible arguments, including dry-run
16580 and partial extraction modes. Don't handle STRING_CST.
16581 (can_native_interpret_type_p): No longer static.
16582 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
16583 offset / BITS_PER_UNIT fits into int and don't call it if
16584 can_native_interpret_type_p fails. If suboff is NULL and for
16585 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
16586 native_encode_initializer.
16587 (fold_const_aggregate_ref_1): Formatting fix.
16588 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
16589 (tree_add_const_value_attribute): Adjust caller.
16591 PR tree-optimization/90838
16592 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16593 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
16594 CTZ_DEFINED_VALUE_AT_ZERO.
16596 2020-01-10 Vladimir Makarov <vmakarov@redhat.com>
16598 PR inline-asm/93027
16599 * lra-constraints.c (match_reload): Permit input operands have the
16600 same mode as output while other input operands have a different
16603 2020-01-10 Wilco Dijkstra <wdijkstr@arm.com>
16605 PR tree-optimization/90838
16606 * tree-ssa-forwprop.c (check_ctz_array): Add new function.
16607 (check_ctz_string): Likewise.
16608 (optimize_count_trailing_zeroes): Likewise.
16609 (simplify_count_trailing_zeroes): Likewise.
16610 (pass_forwprop::execute): Try ctz simplification.
16611 * match.pd: Add matching for ctz idioms.
16613 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16615 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
16617 (aarch64_invalid_unary_op): New function for target hook.
16618 (aarch64_invalid_binary_op): New function for target hook.
16620 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16622 * config.gcc: Add arm_bf16.h.
16623 * config/aarch64/aarch64-builtins.c
16624 (aarch64_simd_builtin_std_type): Add BFmode.
16625 (aarch64_init_simd_builtin_types): Define element types for vector
16627 (aarch64_init_bf16_types): New function.
16628 (aarch64_general_init_builtins): Add arm_init_bf16_types function call.
16629 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
16631 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
16632 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
16634 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
16635 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
16636 * config/aarch64/aarch64.c
16637 (aarch64_classify_vector_mode): Add support for BF types.
16638 (aarch64_gimplify_va_arg_expr): Add support for BF types.
16639 (aarch64_vq_mode): Add support for BF types.
16640 (aarch64_simd_container_mode): Add support for BF types.
16641 (aarch64_mangle_type): Add support for BF scalar type.
16642 * config/aarch64/aarch64.md: Add BFmode to movhf pattern.
16643 * config/aarch64/arm_bf16.h: New file.
16644 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
16645 * config/aarch64/iterators.md: Add BF types to mode attributes.
16646 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
16648 2020-01-10 Jason Merrill <jason@redhat.com>
16650 PR c++/93173 - incorrect tree sharing.
16651 * gimplify.c (copy_if_shared): No longer static.
16652 * gimplify.h: Declare it.
16654 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16656 * doc/invoke.texi (-msve-vector-bits=): Document that
16657 -msve-vector-bits=128 now generates VL-specific code for
16658 little-endian targets.
16659 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
16660 build_vector_type_for_mode to construct the data vector types.
16661 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
16662 VL-specific code for -msve-vector-bits=128 on little-endian targets.
16663 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes
16664 for 128-bit vectors.
16666 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16668 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
16671 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16673 * config/aarch64/aarch64-builtins.c
16674 (aarch64_builtin_vectorized_function): Check for specific vector modes,
16675 rather than checking the number of elements and the element mode.
16677 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16679 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use
16680 get_related_vectype_for_scalar_type rather than build_vector_type
16681 to create the index type for a conditional reduction.
16683 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16685 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
16686 for any type of gather or scatter, including strided accesses.
16688 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16690 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
16693 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16695 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
16696 get_dr_vinfo_offset
16697 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init
16698 parameter and its use to reset DR_OFFSET's.
16699 (vect_transform_loop): Remove orig_drs_init argument.
16700 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
16701 member of dr_vec_info rather than the offset of the associated
16702 data_reference's innermost_loop_behavior.
16703 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
16704 (vect_do_peeling): Remove orig_drs_init parameter and its construction.
16705 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
16706 get_dr_vinfo_offset.
16707 (vectorizable_store): Likewise.
16708 (vectorizable_load): Likewise.
16710 2020-01-10 Richard Biener <rguenther@suse.de>
16712 * gimple-ssa-store-merging
16713 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info.
16715 2020-01-10 Martin Liska <mliska@suse.cz>
16718 * ipa-inline-analysis.c (offline_size): Make proper parenthesis
16719 encapsulation that was there before r280040.
16721 2020-01-10 Richard Biener <rguenther@suse.de>
16723 PR middle-end/93199
16724 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
16725 sequences to avoid walking them again for secondary opportunities.
16726 (pass_lower_eh_dispatch::execute): Instead actually insert
16729 2020-01-10 Richard Biener <rguenther@suse.de>
16731 PR middle-end/93199
16732 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
16733 (cleanup_all_empty_eh): Walk landing pads in reverse order to
16734 avoid quadraticness.
16736 2020-01-10 Martin Jambor <mjambor@suse.cz>
16738 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
16739 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
16740 to get param_ipa_sra_max_replacements.
16741 (param_splitting_across_edge): Pass the caller to
16742 pull_accesses_from_callee.
16744 2020-01-10 Martin Jambor <mjambor@suse.cz>
16746 * params.opt (param_ipcp_unit_growth): Mark as Optimization.
16747 * ipa-cp.c (max_new_size): Removed.
16748 (orig_overall_size): New variable.
16749 (get_max_overall_size): New function.
16750 (estimate_local_effects): Use it. Adjust dump.
16751 (decide_about_value): Likewise.
16752 (ipcp_propagate_stage): Do not calculate max_new_size, just store
16753 orig_overall_size. Adjust dump.
16754 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.
16756 2020-01-10 Martin Jambor <mjambor@suse.cz>
16758 * params.opt (param_ipa_max_agg_items): Mark as Optimization
16759 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
16760 instead of param_ipa_max_agg_items.
16761 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from
16762 optimization info for the callee.
16764 2020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com>
16766 * lto-streamer-in.c (input_function): Remove streamed-in inline debug
16767 markers if debug_inline_points is false.
16769 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
16771 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
16773 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
16774 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
16775 aarch64-sve-builtins-sve2.h.
16776 (aarch64-sve-builtins-sve2.o): New rule.
16777 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
16778 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
16779 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
16780 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
16781 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
16782 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
16784 * config/aarch64/aarch64-sve.md: Update comments with SVE2
16785 instructions that are handled here.
16786 (@cond_asrd<mode>): Generalize to...
16787 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
16788 (*cond_asrd<mode>_2): Generalize to...
16789 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
16790 (*cond_asrd<mode>_z): Generalize to...
16791 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
16792 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
16793 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
16794 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
16795 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
16797 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
16798 (@aarch64_scatter_stnt<mode>): Likewise.
16799 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
16800 (@aarch64_mul_lane_<mode>): Likewise.
16801 (@aarch64_sve_suqadd<mode>_const): Likewise.
16802 (*<sur>h<addsub><mode>): Generalize to...
16803 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
16805 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
16806 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
16807 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
16808 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
16809 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
16810 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
16811 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
16812 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
16813 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
16814 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
16815 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
16816 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
16817 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
16818 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
16819 (@aarch64_sve_add_mul_lane_<mode>): Likewise.
16820 (@aarch64_sve_sub_mul_lane_<mode>): Likewise.
16821 (@aarch64_sve2_xar<mode>): Likewise.
16822 (@aarch64_sve2_bcax<mode>): Likewise.
16823 (*aarch64_sve2_eor3<mode>): Rename to...
16824 (@aarch64_sve2_eor3<mode>): ...this.
16825 (@aarch64_sve2_bsl<mode>): New expander.
16826 (@aarch64_sve2_nbsl<mode>): Likewise.
16827 (@aarch64_sve2_bsl1n<mode>): Likewise.
16828 (@aarch64_sve2_bsl2n<mode>): Likewise.
16829 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
16830 (*aarch64_sve2_sra<mode>): Add MOVPRFX support.
16831 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
16832 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
16833 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
16834 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
16835 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
16836 (<su>mull<bt><Vwide>): Generalize to...
16837 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
16839 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
16840 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
16841 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
16842 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16843 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
16844 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16845 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
16846 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16847 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
16848 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
16849 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
16850 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
16851 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
16852 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
16853 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
16854 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
16855 (<SHRNB:r>shrnb<mode>): Generalize to...
16856 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
16858 (<SHRNT:r>shrnt<mode>): Generalize to...
16859 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
16861 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
16862 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
16863 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
16864 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
16865 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
16866 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
16867 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
16868 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
16869 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
16870 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
16871 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
16872 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
16873 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
16874 (@aarch64_sve2_cvtnt<mode>): Likewise.
16875 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
16876 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
16877 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
16878 (@aarch64_sve2_cvtxnt<mode>): Likewise.
16879 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
16880 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
16881 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
16882 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
16883 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
16884 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
16885 (@aarch64_sve2_pmul<mode>): Likewise.
16886 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
16887 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
16888 (@aarch64_sve2_tbl2<mode>): Likewise.
16889 (@aarch64_sve2_tbx<mode>): Likewise.
16890 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
16891 (@aarch64_sve2_histcnt<mode>): Likewise.
16892 (@aarch64_sve2_histseg<mode>): Likewise.
16893 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
16894 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
16895 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
16896 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
16897 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
16898 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
16899 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
16900 (<su>mulh<r>s<mode>3): Update after above pattern name changes.
16901 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
16902 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
16903 (SVE2_PMULL_PAIR_I): New mode iterators.
16904 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
16905 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
16906 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
16907 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
16908 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
16909 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
16910 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
16911 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
16912 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
16913 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
16914 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
16915 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
16916 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
16917 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
16918 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
16919 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
16920 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
16921 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
16922 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
16923 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
16924 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
16925 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
16926 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
16927 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
16928 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
16929 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
16930 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
16931 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
16932 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
16933 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
16934 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
16936 (VNARROW, Ventype): New mode attributes.
16937 (Vewtype): Handle VNx2DI. Fix typo in comment.
16938 (VDOUBLE): New mode attribute.
16939 (sve_lane_con): Handle VNx8HI.
16940 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
16941 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
16942 (sve_int_op, sve_int_op_rev): Handle the above codes.
16943 (sve_pred_int_rhs2_operand): Likewise.
16944 (MULLBT, SHRNB, SHRNT): Delete.
16945 (SVE_INT_SHIFT_IMM): New int iterator.
16946 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
16947 and UNSPEC_WHILEHS for TARGET_SVE2.
16948 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
16949 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
16950 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
16951 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
16952 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
16953 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
16954 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
16955 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
16956 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
16957 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
16958 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
16959 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
16960 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
16961 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
16962 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
16963 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
16964 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
16965 (optab): Handle the new unspecs.
16966 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
16968 (lr): Handle the new unspecs.
16970 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
16971 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
16972 (sve_int_qsub_op): New int attributes.
16973 (sve_fp_op, rot): Handle the new unspecs.
16974 * config/aarch64/aarch64-sve-builtins.h
16975 (function_resolver::require_matching_pointer_type): Declare.
16976 (function_resolver::resolve_unary): Add an optional boolean argument.
16977 (function_resolver::finish_opt_n_resolution): Add an optional
16978 type_suffix_index argument.
16979 (gimple_folder::redirect_call): Declare.
16980 (gimple_expander::prepare_gather_address_operands): Add an optional
16982 * config/aarch64/aarch64-sve-builtins.cc: Include
16983 aarch64-sve-builtins-sve2.h.
16984 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
16985 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
16986 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
16987 (TYPES_hsd_integer): Use TYPES_hsd_signed.
16988 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
16989 (TYPES_s_unsigned): Likewise.
16990 (TYPES_s_integer): Use TYPES_s_unsigned.
16991 (TYPES_sd_signed, TYPES_sd_unsigned): New macros.
16992 (TYPES_sd_integer): Use them.
16993 (TYPES_d_unsigned): New macro.
16994 (TYPES_d_integer): Use it.
16995 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
16996 (TYPES_cvt_narrow): Likewise.
16997 (DEF_SVE_TYPES_ARRAY): Include the new types macros above.
16998 (preds_mx): New variable.
16999 (function_builder::add_overloaded_function): Allow the new feature
17000 set to be more restrictive than the original one.
17001 (function_resolver::infer_pointer_type): Remove qualifiers from
17002 the pointer type before printing it.
17003 (function_resolver::require_matching_pointer_type): New function.
17004 (function_resolver::resolve_sv_displacement): Handle functions
17005 that don't support 32-bit vector indices or svint32_t vector offsets.
17006 (function_resolver::finish_opt_n_resolution): Take the inferred type
17007 as a separate argument.
17008 (function_resolver::resolve_unary): Optionally treat all forms in
17009 the same way as normal merging functions.
17010 (gimple_folder::redirect_call): New function.
17011 (function_expander::prepare_gather_address_operands): Add an argument
17012 that says whether scaled forms are available. If they aren't,
17013 handle scaling of vector indices and don't add the extension and
17015 (function_expander::map_to_unspecs): If aarch64_sve isn't available,
17016 fall back to using cond_* instead.
17017 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
17018 Split out the member variables into...
17019 (rtx_code_function_base): ...this new base class.
17020 (rtx_code_function_rotated): Inherit rtx_code_function_base.
17021 (unspec_based_function): Split out the member variables into...
17022 (unspec_based_function_base): ...this new base class.
17023 (unspec_based_function_rotated): Inherit unspec_based_function_base.
17024 (unspec_based_function_exact_insn): New class.
17025 (unspec_based_add_function, unspec_based_add_lane_function)
17026 (unspec_based_lane_function, unspec_based_pred_function)
17027 (unspec_based_qadd_function, unspec_based_qadd_lane_function)
17028 (unspec_based_qsub_function, unspec_based_qsub_lane_function)
17029 (unspec_based_sub_function, unspec_based_sub_lane_function): New
17031 (unspec_based_fused_function): New class.
17032 (unspec_based_mla_function, unspec_based_mls_function): New typedefs.
17033 (unspec_based_fused_lane_function): New class.
17034 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
17036 (CODE_FOR_MODE1): New macro.
17037 (fixed_insn_function): New class.
17038 (while_comparison): Likewise.
17039 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
17040 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
17041 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
17042 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
17043 (load_gather_sv_restricted, shift_left_imm_long): Declare.
17044 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
17045 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
17046 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
17047 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
17048 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
17049 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
17050 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
17051 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
17052 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
17053 Also add an initial argument for unary_convert_narrowt, regardless
17054 of the predication type.
17055 (build_32_64): Allow loads and stores to specify MODE_none.
17056 (build_sv_index64, build_sv_uint_offset): New functions.
17057 (long_type_suffix): New function.
17058 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
17059 (binary_imm_long_base, load_gather_sv_base): Likewise.
17060 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
17061 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
17062 (unary_narrowb_base, unary_narrowt_base): Likewise.
17063 (binary_long_lane_def, binary_long_lane): New shape.
17064 (binary_long_opt_n_def, binary_long_opt_n): Likewise.
17065 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
17066 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
17067 (binary_to_uint_def, binary_to_uint): Likewise.
17068 (binary_wide_def, binary_wide): Likewise.
17069 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
17070 (compare_def, compare): Likewise.
17071 (compare_ptr_def, compare_ptr): Likewise.
17072 (load_ext_gather_index_restricted_def,
17073 load_ext_gather_index_restricted): Likewise.
17074 (load_ext_gather_offset_restricted_def,
17075 load_ext_gather_offset_restricted): Likewise.
17076 (load_gather_sv_def): Inherit from load_gather_sv_base.
17077 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
17078 (shift_left_imm_def, shift_left_imm): Likewise.
17079 (shift_left_imm_long_def, shift_left_imm_long): Likewise.
17080 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
17081 (store_scatter_index_restricted_def,
17082 store_scatter_index_restricted): Likewise.
17083 (store_scatter_offset_restricted_def,
17084 store_scatter_offset_restricted): Likewise.
17085 (tbl_tuple_def, tbl_tuple): Likewise.
17086 (ternary_long_lane_def, ternary_long_lane): Likewise.
17087 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
17088 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
17089 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
17090 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
17091 (ternary_qq_rotate_def, ternary_qq_rotate): New shape.
17092 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
17093 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
17094 (ternary_uint_def, ternary_uint): Likewise.
17095 (unary_convert): Fix typo in comment.
17096 (unary_convert_narrowt_def, unary_convert_narrowt): New shape.
17097 (unary_long_def, unary_long): Likewise.
17098 (unary_narrowb_def, unary_narrowb): Likewise.
17099 (unary_narrowt_def, unary_narrowt): Likewise.
17100 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
17101 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
17102 (unary_to_int_def, unary_to_int): Likewise.
17103 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
17104 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
17105 (svasrd_impl): Delete.
17106 (svcadd_impl::expand): Handle integer operations too.
17107 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
17108 new functions to derive the unspec numbers.
17109 (svmla_svmls_lane_impl): Replace with...
17110 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
17111 integer operations too.
17112 (svwhile_impl): Rename to...
17113 (svwhilelx_impl): ...this and inherit from while_comparison.
17114 (svasrd): Use unspec_based_function.
17115 (svmla_lane): Use svmla_lane_impl.
17116 (svmls_lane): Use svmls_lane_impl.
17117 (svrecpe, svrsqrte): Handle unsigned integer operations too.
17118 (svwhilele, svwhilelt): Use svwhilelx_impl.
17119 * config/aarch64/aarch64-sve-builtins-sve2.h: New file.
17120 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
17121 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
17122 * config/aarch64/aarch64-sve-builtins.def: Include
17123 aarch64-sve-builtins-sve2.def.
17125 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17127 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
17128 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
17129 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
17130 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar
17131 immediates as well as vector ones.
17132 * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
17133 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
17134 (aarch64_sve_qsub_immediate): Update calls accordingly.
17136 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17138 * config/aarch64/aarch64-sve2.md: Add banner comments.
17139 (<su>mulh<r>s<mode>3): Move further up file.
17140 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
17141 (*aarch64_sve2_sra<mode>): Move further down file.
17142 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
17144 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17146 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
17147 and UNSPEC_WHILEWR.
17148 (while_optab_cmp): Handle them.
17149 * config/aarch64/aarch64-sve.md
17150 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public
17151 and add a "@" marker.
17152 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it
17153 instead of gen_aarch64_sve2_while_ptest.
17154 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete.
17156 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17158 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to...
17159 (UNSPEC_WHILELE): ...this.
17160 (UNSPEC_WHILE_LO): Rename to...
17161 (UNSPEC_WHILELO): ...this.
17162 (UNSPEC_WHILE_LS): Rename to...
17163 (UNSPEC_WHILELS): ...this.
17164 (UNSPEC_WHILE_LT): Rename to...
17165 (UNSPEC_WHILELT): ...this.
17166 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly.
17167 (cmp_op, while_optab_cmp): Likewise.
17168 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise.
17169 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise.
17170 (svwhilelt): Likewise.
17172 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17174 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete.
17175 (unary_to_uint): Define.
17176 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def)
17177 (unary_count): Rename to...
17178 (unary_to_uint_def, unary_to_uint): ...this.
17179 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly.
17181 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17183 * config/aarch64/aarch64-sve-builtins-functions.h
17184 (code_for_mode_function): New class.
17185 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros.
17186 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl)
17187 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete.
17188 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0.
17189 (svmul_lane, svtmad): Use CODE_FOR_MODE0.
17191 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17193 * config/aarch64/iterators.md (addsub): New code attribute.
17194 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
17196 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
17197 in the asm string and attributes. Fix indentation.
17198 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
17200 (@aarch64_sve_<optab><mode>): ...this.
17201 * config/aarch64/aarch64-sve-builtins.h
17202 (function_expander::expand_signed_unpred_op): Delete.
17203 * config/aarch64/aarch64-sve-builtins.cc
17204 (function_expander::expand_signed_unpred_op): Likewise.
17205 (function_expander::map_to_rtx_codes): If the optab isn't defined,
17206 try using code_for_aarch64_sve instead.
17207 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
17208 (svqsub_impl): Likewise.
17209 (svqadd, svqsub): Use rtx_code_function instead.
17211 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17213 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete.
17214 (HADDSUB, sur, addsub): Remove them.
17216 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17218 * tree-nrv.c (pass_return_slot::execute): Handle all internal
17219 functions the same way, rather than singling out those that
17220 aren't mapped directly to optabs.
17222 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17224 * target.def (compatible_vector_types_p): New target hook.
17225 * hooks.h (hook_bool_const_tree_const_tree_true): Declare.
17226 * hooks.c (hook_bool_const_tree_const_tree_true): New function.
17227 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook.
17228 * doc/tm.texi: Regenerate.
17229 * gimple-expr.c: Include target.h.
17230 (useless_type_conversion_p): Use targetm.compatible_vector_types_p.
17231 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New
17233 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define.
17234 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred):
17235 Use the original predicate if it already has a suitable type.
17237 2020-01-09 Martin Jambor <mjambor@suse.cz>
17239 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct,
17240 resolve_speculation and redirect_call_stmt_to_callee static. Change
17241 return type of set_call_stmt to cgraph_edge *.
17242 * auto-profile.c (afdo_indirect_call): Adjust call to
17243 redirect_call_stmt_to_callee.
17244 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *,
17245 make the this pointer explicit, adjust self-recursive calls and the
17246 call top make_direct. Return the resulting edge.
17247 (cgraph_edge::remove): Make this pointer explicit.
17248 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove.
17249 (cgraph_edge::make_direct): Likewise, adjust call to
17250 resolve_speculation.
17251 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust
17252 call to set_call_stmt.
17253 (cgraph_update_edges_for_call_stmt_node): Update call to
17254 set_call_stmt and remove.
17255 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
17256 Renamed edge to master_edge. Adjusted calls to set_call_stmt.
17257 (cgraph_node::create_edge_including_clones): Moved "first" definition
17258 of edge to the block where it was used. Adjusted calls to
17260 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to
17261 cgraph_edge::remove.
17262 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to
17263 make_direct and redirect_call_stmt_to_callee.
17264 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to
17265 resolve_speculation and make_direct.
17266 * ipa-inline-transform.c (inline_transform): Adjust call to
17267 redirect_call_stmt_to_callee.
17268 (check_speculations_1):: Adjust call to resolve_speculation.
17269 * ipa-inline.c (resolve_noninline_speculation): Adjust call to
17270 resolve-speculation.
17271 (inline_small_functions): Adjust call to resolve_speculation.
17272 (ipa_inline): Likewise.
17273 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to
17275 * ipa-visibility.c (function_and_variable_visibility): Make iteration
17276 safe with regards to edge removal, adjust calls to
17277 redirect_call_stmt_to_callee.
17278 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct
17279 and redirect_call_stmt_to_callee.
17280 * multiple_target.c (create_dispatcher_calls): Adjust call to
17281 redirect_call_stmt_to_callee
17282 (redirect_to_specific_clone): Likewise.
17283 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph):
17284 Adjust calls to cgraph_edge::remove.
17285 * tree-inline.c (copy_bb): Adjust call to set_call_stmt.
17286 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee.
17287 (expand_call_inline): Adjust call to cgraph_edge::remove.
17289 2020-01-09 Martin Liska <mliska@suse.cz>
17291 * params.opt: Set Optimization for
17292 param_max_speculative_devirt_maydefs.
17294 2020-01-09 Martin Sebor <msebor@redhat.com>
17296 PR middle-end/93200
17298 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type.
17300 2020-01-09 Martin Liska <mliska@suse.cz>
17302 * auto-profile.c (auto_profile): Use opt_for_fn
17304 * ipa-cp.c (ipcp_lattice::add_value): Likewise.
17305 (propagate_vals_across_arith_jfunc): Likewise.
17306 (hint_time_bonus): Likewise.
17307 (incorporate_penalties): Likewise.
17308 (good_cloning_opportunity_p): Likewise.
17309 (perform_estimation_of_a_value): Likewise.
17310 (estimate_local_effects): Likewise.
17311 (ipcp_propagate_stage): Likewise.
17312 * ipa-fnsummary.c (decompose_param_expr): Likewise.
17313 (set_switch_stmt_execution_predicate): Likewise.
17314 (analyze_function_body): Likewise.
17315 * ipa-inline-analysis.c (offline_size): Likewise.
17316 * ipa-inline.c (early_inliner): Likewise.
17317 * ipa-prop.c (ipa_analyze_node): Likewise.
17318 (ipcp_transform_function): Likewise.
17319 * ipa-sra.c (process_scan_results): Likewise.
17320 (ipa_sra_summarize_function): Likewise.
17321 * params.opt: Rename ipcp-unit-growth to
17322 ipa-cp-unit-growth. Add Optimization for various
17323 IPA-related parameters.
17325 2020-01-09 Richard Biener <rguenther@suse.de>
17327 PR middle-end/93054
17328 * gimplify.c (gimplify_expr): Deal with NOP definitions.
17330 2020-01-09 Richard Biener <rguenther@suse.de>
17332 PR tree-optimization/93040
17333 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit.
17335 2020-01-09 Georg-Johann Lay <avr@gjlay.de>
17337 * common/config/avr/avr-common.c (avr_option_optimization_table)
17338 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.
17340 2020-01-09 Martin Liska <mliska@suse.cz>
17342 * cgraphclones.c (symbol_table::materialize_all_clones):
17343 Use cgraph_node::dump_name.
17345 2020-01-09 Jakub Jelinek <jakub@redhat.com>
17347 PR inline-asm/93202
17348 * config/riscv/riscv.c (riscv_print_operand_reloc): Use
17349 output_operand_lossage instead of gcc_unreachable.
17350 * doc/md.texi (riscv f constraint): Fix typo.
17353 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
17354 SWI. Use <general_hilo_operand> instead of <general_operand>. Use
17355 CONST_SCALAR_INT_P instead of CONST_INT_P.
17356 (*subv<mode>4_1): Rename to ...
17357 (subv<mode>4_1): ... this.
17358 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
17359 define_insn_and_split patterns.
17360 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
17363 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17365 * vec.c (class selftest::count_dtor): New class.
17366 (selftest::test_auto_delete_vec): New test.
17367 (selftest::vec_c_tests): Call it.
17368 * vec.h (class auto_delete_vec): New class template.
17369 (auto_delete_vec<T>::~auto_delete_vec): New dtor.
17371 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17373 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap.
17375 2020-01-08 Jim Wilson <jimw@sifive.com>
17377 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out
17378 use of TLS_MODEL_LOCAL_EXEC when not pic.
17380 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17382 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix
17385 2020-01-08 Jakub Jelinek <jakub@redhat.com>
17388 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2,
17389 *stack_protect_set_3 peephole2): Also check that the second
17390 insns source is general_operand.
17393 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand
17394 predicate for output operand instead of register_operand.
17395 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with
17396 memory destination and non-memory operands[2].
17398 2020-01-08 Martin Liska <mliska@suse.cz>
17400 * cgraph.c (cgraph_node::dump): Use ::dump_name or
17401 ::dump_asm_name instead of (::name or ::asm_name).
17402 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise.
17403 * cgraphunit.c (walk_polymorphic_call_targets): Likewise.
17404 (analyze_functions): Likewise.
17405 (expand_all_functions): Likewise.
17406 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise.
17407 (propagate_bits_across_jump_function): Likewise.
17408 (dump_profile_updates): Likewise.
17409 (ipcp_store_bits_results): Likewise.
17410 (ipcp_store_vr_results): Likewise.
17411 * ipa-devirt.c (dump_targets): Likewise.
17412 * ipa-fnsummary.c (analyze_function_body): Likewise.
17413 * ipa-hsa.c (check_warn_node_versionable): Likewise.
17414 (process_hsa_functions): Likewise.
17415 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise.
17416 (set_alias_uids): Likewise.
17417 * ipa-inline-transform.c (save_inline_function_body): Likewise.
17418 * ipa-inline.c (recursive_inlining): Likewise.
17419 (inline_to_all_callers_1): Likewise.
17420 (ipa_inline): Likewise.
17421 * ipa-profile.c (ipa_propagate_frequency_1): Likewise.
17422 (ipa_propagate_frequency): Likewise.
17423 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
17424 (remove_described_reference): Likewise.
17425 * ipa-pure-const.c (worse_state): Likewise.
17426 (check_retval_uses): Likewise.
17427 (analyze_function): Likewise.
17428 (propagate_pure_const): Likewise.
17429 (propagate_nothrow): Likewise.
17430 (dump_malloc_lattice): Likewise.
17431 (propagate_malloc): Likewise.
17432 (pass_local_pure_const::execute): Likewise.
17433 * ipa-visibility.c (optimize_weakref): Likewise.
17434 (function_and_variable_visibility): Likewise.
17435 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise.
17436 (ipa_discover_variable_flags): Likewise.
17437 * lto-streamer-out.c (output_function): Likewise.
17438 (output_constructor): Likewise.
17439 * tree-inline.c (copy_bb): Likewise.
17440 * tree-ssa-structalias.c (ipa_pta_execute): Likewise.
17441 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise.
17443 2020-01-08 Richard Biener <rguenther@suse.de>
17445 PR middle-end/93199
17446 * tree-eh.c (sink_clobbers): Update virtual operands for
17447 the first and last stmt only. Add a dry-run capability.
17448 (pass_lower_eh_dispatch::execute): Perform clobber sinking
17449 after CFG manipulations and in RPO order to catch all
17450 secondary opportunities reliably.
17452 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17455 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17457 2019-01-08 Richard Biener <rguenther@suse.de>
17459 PR middle-end/93199
17460 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
17461 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
17462 virtual operand, also updating SSA use.
17463 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
17464 Update stmt after resetting virtual operand.
17465 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
17466 * gimple-iterator.c (gsi_remove): When not removing the stmt
17467 permanently do not delink immediate uses or mark the stmt modified.
17469 2020-01-08 Martin Liska <mliska@suse.cz>
17471 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
17472 (ipa_call_context::estimate_size_and_time): Likewise.
17473 (inline_analyze_function): Likewise.
17475 2020-01-08 Martin Liska <mliska@suse.cz>
17477 * cgraph.c (cgraph_node::dump): Use systematically
17480 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17482 Add -nodevicespecs option for avr.
17485 * config/avr/avr.opt (-nodevicespecs): New driver option.
17486 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
17487 "-specs=device-specs/..." if that option is not set.
17488 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17490 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17492 Implement 64-bit double functions for avr.
17495 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
17496 --with-double-comparison.
17497 * doc/install.texi: Document them.
17498 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
17499 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
17500 <WITH_DOUBLE_COMPARISON>: New built-in defines.
17501 * doc/invoke.texi (AVR Built-in Macros): Document them.
17502 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
17503 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
17504 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
17506 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
17509 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
17510 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
17511 when only building rm-profile multilibs.
17513 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
17516 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
17517 lattice for a value to check.
17518 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
17519 finite propagation in self-recursive scc.
17521 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
17523 * ipa-inline.c (caller_growth_limits): Restore the AND.
17525 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17527 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
17528 (VEC_ALLREG_ALT): New iterator.
17529 (VEC_ALLREG_INT_MODE): New iterator.
17530 (VCMP_MODE): New iterator.
17531 (VCMP_MODE_INT): New iterator.
17532 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
17533 (vec_cmp<u>v64qidi): New define_expand.
17534 (vec_cmp<mode>di_exec): Use VCMP_MODE.
17535 (vec_cmpu<mode>di_exec): New define_expand.
17536 (vec_cmp<u>v64qidi_exec): New define_expand.
17537 (vec_cmp<mode>di_dup): Use VCMP_MODE.
17538 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
17539 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
17540 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
17541 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
17542 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
17543 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
17544 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
17545 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
17546 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
17548 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
17549 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
17551 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17553 * config/gcn/constraints.md (DA): Update description and match.
17555 (Db): New constraint.
17556 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
17558 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
17559 Implement 'Db' mixed immediate type.
17560 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
17561 (addcv64si3_dup<exec_vcc>): Delete.
17562 (subcv64si3<exec_vcc>): Rework constraints.
17563 (addv64di3): Rework constraints.
17564 (addv64di3_exec): Rework constraints.
17565 (subv64di3): Rework constraints.
17566 (addv64di3_dup): Delete.
17567 (addv64di3_dup_exec): Delete.
17568 (addv64di3_zext): Rework constraints.
17569 (addv64di3_zext_exec): Rework constraints.
17570 (addv64di3_zext_dup): Rework constraints.
17571 (addv64di3_zext_dup_exec): Rework constraints.
17572 (addv64di3_zext_dup2): Rework constraints.
17573 (addv64di3_zext_dup2_exec): Rework constraints.
17574 (addv64di3_sext_dup2): Rework constraints.
17575 (addv64di3_sext_dup2_exec): Rework constraints.
17577 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
17579 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
17580 existing target checks.
17582 2020-01-07 Richard Biener <rguenther@suse.de>
17584 * doc/install.texi: Bump minimal supported MPC version.
17586 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17588 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
17589 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
17590 * langhooks.c: Include stor-layout.h.
17591 (lhd_simulate_enum_decl): New function.
17592 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
17593 handle_arm_sve_h for the LTO frontend.
17594 (register_vector_type): Cope with null returns from pushdecl.
17596 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17598 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
17599 (aarch64_sve::nvectors_if_data_type): Replace with...
17600 (aarch64_sve::builtin_type_p): ...this.
17601 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
17602 (find_vector_type): Delete.
17603 (add_sve_type_attribute): New function.
17604 (lookup_sve_type_attribute): Likewise.
17605 (register_builtin_types): Add an "SVE type" attribute to each type.
17606 (register_tuple_type): Likewise.
17607 (svbool_type_p, nvectors_if_data_type): Delete.
17608 (mangle_builtin_type): Use lookup_sve_type_attribute.
17609 (builtin_type_p): Likewise. Add an overload that returns the
17610 number of constituent vector and predicate registers.
17611 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
17612 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
17613 instead of aarch64_sve_argument_p.
17614 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
17615 (aarch64_pass_by_reference): Likewise.
17616 (aarch64_function_value_1): Likewise.
17617 (aarch64_return_in_memory): Likewise.
17618 (aarch64_layout_arg): Likewise.
17620 2020-01-07 Jakub Jelinek <jakub@redhat.com>
17622 PR tree-optimization/93156
17623 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
17624 least significant bit is always clear.
17626 PR tree-optimization/93118
17627 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
17628 simplifier with two intermediate conversions.
17630 2020-01-07 Martin Liska <mliska@suse.cz>
17632 * params.opt: Add Optimization for various parameters.
17634 2020-01-07 Martin Liska <mliska@suse.cz>
17637 * doc/extend.texi: Explain cloning for target_clone
17640 2020-01-07 Martin Liska <mliska@suse.cz>
17642 PR tree-optimization/92860
17643 * common.opt: Make in Optimization option
17644 as it is affected by -O0, which is an Optimization
17646 * tree-inline.c (tree_inlinable_function_p):
17647 Use opt_for_fn for warn_inline.
17648 (expand_call_inline): Likewise.
17650 2020-01-07 Martin Liska <mliska@suse.cz>
17652 PR tree-optimization/92860
17653 * common.opt: Make flag_ree as optimization
17656 2020-01-07 Martin Liska <mliska@suse.cz>
17658 PR optimization/92860
17659 * params.opt: Mark param_min_crossjump_insns with Optimization
17662 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
17664 * ipa-inline-analysis.c (estimate_growth): Fix typo.
17665 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
17667 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
17669 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
17670 helper function to return the valid addressing formats for a given
17671 hard register and mode.
17672 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
17674 * config/rs6000/constraints.md (Q constraint): Update
17676 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
17679 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
17680 Use 'Q' for doing vector extract from memory.
17681 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
17683 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
17684 doing vector extract from memory.
17685 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
17686 extract from memory.
17688 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
17689 for the offset being 34-bits when -mcpu=future is used.
17691 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
17693 * config/pa/pa.md: Revert change to use ordered_comparison_operator
17694 instead of cmpib_comparison_operator in cmpib patterns.
17695 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
17696 of cmpib_comparison_operator. Revise comment.
17698 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17700 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
17701 in an IFN_DIV_POW2 node to be equal.
17703 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17705 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
17706 (vect_check_scalar_mask): ...this.
17707 (vectorizable_store, vectorizable_load): Update call accordingly.
17708 (vectorizable_call): Use vect_check_scalar_mask to check the mask
17709 argument in calls to conditional internal functions.
17711 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17713 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
17714 '0' matching inputs.
17715 (subv64di3_exec): Likewise.
17717 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
17719 * config/mips/mips.c (vr4130_align_insns): Fix typo.
17720 * doc/md.texi (movstr): Likewise.
17722 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17724 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
17727 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17729 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
17731 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
17732 to a temporary file and use move-if-change to update the real
17733 file where necessary.
17735 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17737 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
17738 rather than Upa for CPY /M.
17740 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
17742 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
17745 2020-01-06 Martin Liska <mliska@suse.cz>
17747 PR tree-optimization/92860
17748 * params.opt: Mark param_max_combine_insns with Optimization
17751 2020-01-05 Jakub Jelinek <jakub@redhat.com>
17754 * config/i386/i386.md (SWIDWI): New mode iterator.
17755 (DWI, dwi): Add TImode variants.
17756 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
17757 <general_hilo_operand> instead of <general_operand>. Use
17758 CONST_SCALAR_INT_P instead of CONST_INT_P.
17759 (*addv<mode>4_1): Rename to ...
17760 (addv<mode>4_1): ... this.
17761 (QWI): New mode attribute.
17762 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
17763 define_insn_and_split patterns.
17764 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
17766 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
17767 <general_hilo_operand> instead of <general_operand>.
17768 (*addcarry<mode>_1): New define_insn.
17769 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
17771 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
17773 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
17774 Use "call" instead of "set".
17776 2020-01-03 Martin Jambor <mjambor@suse.cz>
17779 * ipa-cp.c (print_all_lattices): Skip functions without info.
17781 2020-01-03 Jakub Jelinek <jakub@redhat.com>
17784 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
17785 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
17786 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
17787 for 'e' simd clones.
17790 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
17792 (mprefer-vector-width=): Add Save.
17793 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
17794 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
17795 (ix86_debug_options, ix86_function_specific_print): Adjust
17796 ix86_target_string callers.
17797 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
17798 (ix86_valid_target_attribute_tree): Likewise.
17799 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
17800 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
17801 ix86_target_string caller.
17804 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
17805 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
17806 instead of gen_int_shift_amount + convert_modes.
17808 PR rtl-optimization/93088
17809 * loop-iv.c (find_single_def_src): Punt after looking through
17810 128 reg copies for regs with single definitions. Move definitions
17813 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
17815 * config/arm/arm-c.c (arm_cpu_builtins): Define
17816 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
17817 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
17818 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
17819 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
17820 * config/arm/arm-tables.opt: Regenerated.
17821 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
17822 arm_arch_i8mm and arm_arch_bf16 when enabled.
17823 * config/arm/arm.h (TARGET_I8MM): New macro.
17824 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
17825 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
17826 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
17827 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
17828 (v8_6_a_simd_variants): New.
17829 (v8_*_a_simd_variants): Add i8mm and bf16.
17830 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
17832 2020-01-02 Jakub Jelinek <jakub@redhat.com>
17835 * predict.c (compute_function_frequency): Don't call
17836 warn_function_cold on functions that already have cold attribute.
17838 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
17841 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
17842 COMDAT group function labels in .data.rel.ro.local section.
17843 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
17846 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
17847 comparison_operator in B and S integer comparisons. Likewise, use
17848 ordered_comparison_operator instead of cmpib_comparison_operator in
17850 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
17852 2020-01-01 Jakub Jelinek <jakub@redhat.com>
17854 Update copyright years.
17856 * gcc.c (process_command): Update copyright notice dates.
17857 * gcov-dump.c (print_version): Ditto.
17858 * gcov.c (print_version): Ditto.
17859 * gcov-tool.c (print_version): Ditto.
17860 * gengtype.c (create_file): Ditto.
17861 * doc/cpp.texi: Bump @copying's copyright year.
17862 * doc/cppinternals.texi: Ditto.
17863 * doc/gcc.texi: Ditto.
17864 * doc/gccint.texi: Ditto.
17865 * doc/gcov.texi: Ditto.
17866 * doc/install.texi: Ditto.
17867 * doc/invoke.texi: Ditto.
17869 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
17871 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
17874 2020-01-01 Jakub Jelinek <jakub@redhat.com>
17876 PR tree-optimization/93098
17877 * match.pd (popcount): For shift amounts, use integer_onep
17878 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
17879 tests. Make sure that precision is power of two larger than or equal
17880 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
17881 instead of ULL suffixed constants. Formatting fixes.
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