1 2020-05-21 Uroš Bizjak <ubizjak@gmail.com>
5 * config/i386/mmx.md (*mmx_<code>v2sf): Do not mark
6 operands 1 and 2 commutative. Manually swap operands.
7 (*mmx_nabsv2sf2): Ditto.
10 2020-05-18 Uroš Bizjak <ubizjak@gmail.com>
12 * config/i386/i386.md (*<code>tf2_1):
13 Mark operands 1 and 2 commutative.
15 * config/i386/sse.md (*<code><mode>2): Mark operands 1 and 2
16 commutative. Do not swap operands.
17 (*nabs<mode>2): Ditto.
19 2020-05-20 Uroš Bizjak <ubizjak@gmail.com>
22 * config/i386/sse.md (<code>v8qiv8hi2): Use
23 simplify_gen_subreg instead of simplify_subreg.
24 (<code>v8qiv8si2): Ditto.
25 (<code>v4qiv4si2): Ditto.
26 (<code>v4hiv4si2): Ditto.
27 (<code>v8qiv8di2): Ditto.
28 (<code>v4qiv4di2): Ditto.
29 (<code>v2qiv2di2): Ditto.
30 (<code>v4hiv4di2): Ditto.
31 (<code>v2hiv2di2): Ditto.
32 (<code>v2siv2di2): Ditto.
34 2020-05-20 Uroš Bizjak <ubizjak@gmail.com>
37 * config/i386/i386.md (*pushsi2_rex64):
38 Use "e" constraint instead of "i".
40 2020-05-20 Jan Hubicka <hubicka@ucw.cz>
42 * lto-streamer-in.c (lto_input_scc): Add SHARED_SCC parameter.
43 (lto_input_tree_1): Strenghten sanity check.
44 (lto_input_tree): Update call of lto_input_scc.
45 * lto-streamer-out.c: Include ipa-utils.h
46 (create_output_block): Initialize local_trees if merigng is going
48 (destroy_output_block): Destroy local_trees.
49 (DFS): Add max_local_entry.
50 (local_tree_p): New function.
51 (DFS::DFS): Initialize and maintain it.
52 (DFS::DFS_write_tree): Decide on streaming format.
53 (lto_output_tree): Stream inline singleton SCCs
54 * lto-streamer.h (enum LTO_tags): Add LTO_trees.
55 (struct output_block): Add local_trees.
56 (lto_input_scc): Update prototype.
58 2020-05-20 Patrick Palka <ppalka@redhat.com>
61 * hash-table.h (hash_table::find_with_hash): Move up the call to
64 2020-05-20 Martin Liska <mliska@suse.cz>
66 * lto-compress.c (lto_compression_zstd): Fill up
67 num_compressed_il_bytes.
68 (lto_uncompression_zstd): Likewise for num_uncompressed_il_bytes here.
70 2020-05-20 Richard Biener <rguenther@suse.de>
72 PR tree-optimization/95219
73 * tree-vect-loop.c (vectorizable_induction): Reduce
74 group_size before computing the number of required IVs.
76 2020-05-20 Richard Biener <rguenther@suse.de>
79 * tree-inline.c (remap_gimple_stmt): Revert adjusting
80 COND_EXPR and VEC_COND_EXPR for a -fnon-call-exception boundary.
82 2020-05-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
83 Andre Vieira <andre.simoesdiasvieira@arm.com>
86 * config/arm/arm-protos.h (arm_mode_base_reg_class): Function
88 (mve_vector_mem_operand): Likewise.
89 * config/arm/arm.c (thumb2_legitimate_address_p): For MVE target check
90 the load from memory to a core register is legitimate for give mode.
91 (mve_vector_mem_operand): Define function.
92 (arm_print_operand): Modify comment.
93 (arm_mode_base_reg_class): Define.
94 * config/arm/arm.h (MODE_BASE_REG_CLASS): Modify to add check for
95 TARGET_HAVE_MVE and expand to arm_mode_base_reg_class on TRUE.
96 * config/arm/constraints.md (Ux): Likewise.
98 * config/arm/mve.md (mve_mov): Replace constraint Us with Ux and also
99 add support for missing Vector Store Register and Vector Load Register.
100 Add a new alternative to support load from memory to PC (or label) in
102 (mve_vstrbq_<supf><mode>): Modify constraint Us to Ux.
103 (mve_vldrbq_<supf><mode>): Modify constriant Us to Ux, predicate to
104 mve_memory_operand and also modify the MVE instructions to emit.
105 (mve_vldrbq_z_<supf><mode>): Modify constraint Us to Ux.
106 (mve_vldrhq_fv8hf): Modify constriant Us to Ux, predicate to
107 mve_memory_operand and also modify the MVE instructions to emit.
108 (mve_vldrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
109 mve_memory_operand and also modify the MVE instructions to emit.
110 (mve_vldrhq_z_fv8hf): Likewise.
111 (mve_vldrhq_z_<supf><mode>): Likewise.
112 (mve_vldrwq_fv4sf): Likewise.
113 (mve_vldrwq_<supf>v4si): Likewise.
114 (mve_vldrwq_z_fv4sf): Likewise.
115 (mve_vldrwq_z_<supf>v4si): Likewise.
116 (mve_vld1q_f<mode>): Modify constriant Us to Ux.
117 (mve_vld1q_<supf><mode>): Likewise.
118 (mve_vstrhq_fv8hf): Modify constriant Us to Ux, predicate to
120 (mve_vstrhq_p_fv8hf): Modify constriant Us to Ux, predicate to
121 mve_memory_operand and also modify the MVE instructions to emit.
122 (mve_vstrhq_p_<supf><mode>): Likewise.
123 (mve_vstrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
125 (mve_vstrwq_fv4sf): Modify constriant Us to Ux.
126 (mve_vstrwq_p_fv4sf): Modify constriant Us to Ux and also modify the MVE
127 instructions to emit.
128 (mve_vstrwq_p_<supf>v4si): Likewise.
129 (mve_vstrwq_<supf>v4si): Likewise.Modify constriant Us to Ux.
130 * config/arm/predicates.md (mve_memory_operand): Define.
132 2020-05-30 Richard Biener <rguenther@suse.de>
135 * c-fold.c (c_fully_fold_internal): Enhance guard on
138 2020-05-20 Kito Cheng <kito.cheng@sifive.com>
141 * Makefile.in (OBJS): Add adjust-alignment.o.
142 * adjust-alignment.c (pass_data_adjust_alignment): New.
143 (pass_adjust_alignment): New.
144 (pass_adjust_alignment::execute): New.
145 (make_pass_adjust_alignment): New.
146 * tree-pass.h (make_pass_adjust_alignment): New.
147 * passes.def: Add pass_adjust_alignment.
149 2020-05-19 Alex Coplan <alex.coplan@arm.com>
152 * config/aarch64/aarch64.c (aarch64_evpc_rev_local): Don't match
153 identity permutation.
155 2020-05-19 Jozef Lawrynowicz <jozef.l@mittosystems.com>
157 * doc/sourcebuild.texi: Document new short_eq_int, ptr_eq_short,
158 msp430_small, msp430_large and size24plus DejaGNU effective
160 Improve grammar in descriptions for size20plus and size32plus effective
163 2020-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
165 * config/bpf/bpf.c (bpf_compute_frame_layout): Include space for
166 callee saved registers only in xBPF.
167 (bpf_expand_prologue): Save callee saved registers only in xBPF.
168 (bpf_expand_epilogue): Likewise for restoring.
169 * doc/invoke.texi (eBPF Options): Document this is activated by
172 2020-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
174 * config/bpf/bpf.opt (mxbpf): New option.
175 * doc/invoke.texi (Option Summary): Add -mxbpf.
176 (eBPF Options): Document -mxbbpf.
178 2020-05-19 Uroš Bizjak <ubizjak@gmail.com>
181 * config/i386/sse.md (<code>v16qiv16hi2): New expander.
182 (<code>v32qiv32hi2): Ditto.
183 (<code>v8qiv8hi2): Ditto.
184 (<code>v16qiv16si2): Ditto.
185 (<code>v8qiv8si2): Ditto.
186 (<code>v4qiv4si2): Ditto.
187 (<code>v16hiv16si2): Ditto.
188 (<code>v8hiv8si2): Ditto.
189 (<code>v4hiv4si2): Ditto.
190 (<code>v8qiv8di2): Ditto.
191 (<code>v4qiv4di2): Ditto.
192 (<code>v2qiv2di2): Ditto.
193 (<code>v8hiv8di2): Ditto.
194 (<code>v4hiv4di2): Ditto.
195 (<code>v2hiv2di2): Ditto.
196 (<code>v8siv8di2): Ditto.
197 (<code>v4siv4di2): Ditto.
198 (<code>v2siv2di2): Ditto.
200 2020-05-19 Kito Cheng <kito.cheng@sifive.com>
202 * common/config/riscv/riscv-common.c (riscv_implied_info_t): New.
203 (riscv_implied_info): New.
204 (riscv_subset_list): Add handle_implied_ext.
205 (riscv_subset_list::to_string): New parameter version_p to
206 control output format.
207 (riscv_subset_list::handle_implied_ext): New.
208 (riscv_subset_list::parse_std_ext): Call handle_implied_ext.
209 (riscv_arch_str): New parameter version_p to control output format.
210 (riscv_expand_arch): New.
211 * config/riscv/riscv-protos.h (riscv_arch_str): New parameter,
213 * config/riscv/riscv.h (riscv_expand_arch): New,
214 (EXTRA_SPEC_FUNCTIONS): Define.
215 (ASM_SPEC): Transform -march= via riscv_expand_arch.
217 2020-05-19 Kito Cheng <kito.cheng@sifive.com>
219 * riscv-common.c (parse_sv_or_non_std_ext): Rename to
220 parse_multiletter_ext.
221 (parse_multiletter_ext): Add parsing `h` and `z`, drop `sx`,
222 adjust parsing order for 's' and 'x'.
224 2020-05-19 Richard Biener <rguenther@suse.de>
226 * tree-vectorizer.h (_slp_tree::vectype): Add field.
227 (SLP_TREE_VECTYPE): New.
228 * tree-vect-slp.c (vect_create_new_slp_node): Initialize
230 (vect_create_new_slp_node): Likewise.
231 (vect_prologue_cost_for_slp): Move here from tree-vect-stmts.c
233 (vect_slp_analyze_node_operations): Walk nodes children for
235 (vect_get_constant_vectors): Use local scope op variable.
236 * tree-vect-stmts.c (vect_prologue_cost_for_slp_op): Remove here.
237 (vect_model_simple_cost): Adjust.
238 (vect_model_store_cost): Likewise.
239 (vectorizable_store): Likewise.
241 2020-05-18 Martin Sebor <msebor@redhat.com>
244 * tree-object-size.c (decl_init_size): New function.
245 (addr_object_size): Call it.
246 * tree.h (last_field): Declare.
247 (first_field): Add attribute nonnull.
249 2020-05-18 Martin Sebor <msebor@redhat.com>
252 * tree-vrp.c (vrp_prop::check_mem_ref): Remove unreachable code.
253 * tree.c (component_ref_size): Correct the handling or array members
255 Drop a pointless test.
256 Rename a local variable.
258 2020-05-18 Jason Merrill <jason@redhat.com>
260 * aclocal.m4: Add ax_cxx_compile_stdcxx.m4.
261 * configure.ac: Use AX_CXX_COMPILE_STDCXX(11).
263 2020-05-14 Jason Merrill <jason@redhat.com>
265 * doc/install.texi (Prerequisites): Update boostrap compiler
266 requirement to C++11/GCC 4.8.
268 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
270 PR tree-optimization/94952
271 * gimple-ssa-store-merging.c (pass_store_merging::process_store):
272 Initialize variables bitpos, bitregion_start, and bitregion_end in
273 order to silence warnings about use of uninitialized variables.
275 2020-05-18 Carl Love <cel@us.ibm.com>
278 * config/rs6000/vsx.md (define_expand): Fix instruction generation for
279 first_match_index_<mode>.
280 * testsuite/gcc.target/powerpc/builtins-8-p9-runnable.c (main): Add
281 additional test cases with zero vector elements.
283 2020-05-18 Uroš Bizjak <ubizjak@gmail.com>
286 * config/i386/i386-expand.c (ix86_expand_int_movcc):
287 Avoid reversing a non-trapping comparison to a trapping one.
289 2020-05-18 Alex Coplan <alex.coplan@arm.com>
291 * config/arm/arm.c (output_move_double): Fix codegen when loading into
292 a register pair with an odd base register.
294 2020-05-18 Uroš Bizjak <ubizjak@gmail.com>
296 * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator):
297 Do not emit FLAGS_REG clobber for TFmode.
298 * config/i386/i386.md (*<code>tf2_1): Rewrite as
299 define_insn_and_split. Mark operands 1 and 2 commutative.
301 (absneg SSE splitter): Use MODEF mode iterator instead of SSEMODEF.
302 Do not swap memory operands. Simplify RTX generation.
303 (neg abs SSE splitter): Ditto.
304 * config/i386/sse.md (*<code><mode>2): Mark operands 1 and 2
305 commutative. Do not swap operands. Simplify RTX generation.
306 (*nabs<mode>2): Ditto.
308 2020-05-18 Richard Biener <rguenther@suse.de>
310 * tree-vect-slp.c (vect_slp_bb): Start after labels.
311 (vect_get_constant_vectors): Really place init stmt after scalar defs.
312 * tree-vect-stmts.c (vect_init_vector_1): Insert before
315 2020-05-18 H.J. Lu <hongjiu.lu@intel.com>
317 * config/i386/driver-i386.c (host_detect_local_cpu): Support
318 Intel Airmont, Tremont, Comet Lake, Ice Lake and Tiger Lake
321 2020-05-18 Richard Biener <rguenther@suse.de>
324 * tree-inline.c (remap_gimple_stmt): Split out trapping compares
325 when inlining into a non-call EH function.
327 2020-05-18 Richard Biener <rguenther@suse.de>
329 PR tree-optimization/95172
330 * tree-ssa-loop-im.c (execute_sm): Get flag whether we
331 eventually need the conditional processing.
332 (execute_sm_exit): When processing an orderd sequence
333 avoid doing any conditional processing.
334 (hoist_memory_references): Pass down whether all edges
335 have ordered processing for a ref to execute_sm.
337 2020-05-17 Jeff Law <law@redhat.com>
339 * config/h8300/predicates.md (pc_or_label_operand): New predicate.
340 * config/h8300/jumpcall.md (branch_true, branch_false): Consolidate
341 into a single pattern using pc_or_label_operand.
342 * config/h8300/combiner.md (bit branch patterns): Likewise.
343 * config/h8300/peepholes.md (HImode and SImode branches): Likewise.
345 2020-05-17 H.J. Lu <hongjiu.lu@intel.com>
348 * config/i386/i386-features.c (has_non_address_hard_reg):
350 (pseudo_reg_set): This. Return the SET expression. Ignore
351 pseudo register push.
352 (general_scalar_to_vector_candidate_p): Combine single_set and
353 has_non_address_hard_reg calls to pseudo_reg_set.
354 (timode_scalar_to_vector_candidate_p): Likewise.
355 * config/i386/i386.md (*pushv1ti2): New pattern.
357 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
360 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
362 * tree-vrp.c (operand_less_p): Move to...
363 * vr-values.c (operand_less_p): ...here.
364 * tree-vrp.h (operand_less_p): Remove.
366 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
368 * tree-vrp.c (operand_less_p): Move to...
369 * vr-values.c (operand_less_p): ...here.
370 * tree-vrp.h (operand_less_p): Remove.
372 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
374 * tree-vrp.c (class vrp_insert): Remove prototype for
377 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
379 * tree-vrp.c (class live_names): New.
380 (live_on_edge): Move into live_names.
381 (build_assert_expr_for): Move into vrp_insert.
382 (find_assert_locations_in_bb): Rename from
383 find_assert_locations_1.
384 (process_assert_insertions_for): Move into vrp_insert.
385 (compare_assert_loc): Same.
386 (remove_range_assertions): Same.
387 (dump_asserts_for): Rename to vrp_insert::dump.
388 (debug_asserts_for): Rename to vrp_insert::debug.
389 (dump_all_asserts): Rename to vrp_insert::dump.
390 (debug_all_asserts): Rename to vrp_insert::debug.
392 2020-05-17 Aldy Hernandez <aldyh@redhat.com>
394 * tree-vrp.c (class vrp_prop): Move check_all_array_refs,
395 check_array_ref, check_mem_ref, and search_for_addr_array
397 (class array_bounds_checker): ...here.
398 (class check_array_bounds_dom_walker): Adjust to use
399 array_bounds_checker.
400 (check_all_array_refs): Move into array_bounds_checker and rename
402 (class vrp_folder): Make fold_predicate_in private.
404 2020-05-15 Jeff Law <law@redhat.com>
406 * config/h8300/h8300.md (SFI iterator): New iterator for
408 * config/h8300/peepholes.md (memory comparison): Use mode
409 iterator to consolidate 3 patterns into one.
410 (stack allocation and stack store): Handle SFmode. Handle
413 2020-05-15 Segher Boessenkool <segher@kernel.crashing.org>
415 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_2): Also require
416 RS6000_BTM_POWERPC64.
418 2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
420 * config/i386/i386.md (SWI48DWI): New mode iterator.
421 (*push<mode>2): Allow XMM registers.
422 (*pushdi2_rex64): Ditto.
423 (*pushsi2_rex64): Ditto.
425 (push XMM reg splitter): New splitter
427 (*pushdf) Change "x" operand constraint to "v".
428 (*pushsf_rex64): Ditto.
431 2020-05-15 Richard Biener <rguenther@suse.de>
433 PR tree-optimization/92260
434 * tree-vect-slp.c (vect_get_constant_vectors): Compute
435 the number of vector stmts in a canonical way.
437 2020-05-15 Martin Liska <mliska@suse.cz>
439 * hsa-gen.c (get_symbol_for_decl): Fix misleading indentation
442 2020-05-15 Andrew Stubbs <ams@codesourcery.com>
444 * config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.
446 2020-05-15 Richard Biener <rguenther@suse.de>
448 PR tree-optimization/95133
449 * gimple-ssa-split-paths.c
450 (find_block_to_duplicate_for_splitting_paths): Check for
453 2020-05-15 Christophe Lyon <christophe.lyon@linaro.org>
455 * config/arm/arm.c (reg_needs_saving_p): Add support for interrupt
457 (arm_compute_save_reg0_reg12_mask): Use reg_needs_saving_p.
459 2020-05-15 Tobias Burnus <tobias@codesourcery.com>
462 * gimplify.c (gimplify_scan_omp_clauses): For MAP_TO_PSET with
463 OMP_TARGET_EXIT_DATA, use 'release:' unless the associated
466 2020-05-15 Uroš Bizjak <ubizjak@gmail.com>
469 * config/i386/i386.md (isa): Add sse3_noavx.
470 (enabled): Handle sse3_noavx.
472 * config/i386/mmx.md (mmx_haddv2sf3): New expander.
473 (*mmx_haddv2sf3): Rename from mmx_haddv2sf3. Add SSE/AVX
474 alternatives. Match commutative vec_select selector operands.
475 (*mmx_haddv2sf3_low): New insn pattern.
477 (*mmx_hsubv2sf3): Add SSE/AVX alternatives.
478 (*mmx_hsubv2sf3_low): New insn pattern.
480 2020-05-15 Richard Biener <rguenther@suse.de>
482 PR tree-optimization/33315
483 * tree-ssa-sink.c: Include tree-eh.h.
484 (sink_stats): Add commoned member.
485 (sink_common_stores_to_bb): New function implementing store
486 commoning by sinking to the successor.
487 (sink_code_in_bb): Call it, pass down TODO_cleanup_cfg returned.
488 (pass_sink_code::execute): Likewise. Record commoned stores
491 2020-05-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
493 PR rtl-optimization/37451, part of PR target/61837
494 * loop-doloop.c (doloop_simplify_count): New function. Simplify
495 (add -1; zero_ext; add +1) to zero_ext when not wrapping.
496 (doloop_modify): Call doloop_simplify_count.
498 2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
501 * doc/sourcebuild.texi: Document effective target lgccjit.
503 2020-05-14 Andrew Stubbs <ams@codesourcery.com>
505 * config/gcn/gcn-valu.md (add<mode>3_zext_dup): Change to a
506 define_expand, and rename the original to ...
507 (add<mode>3_vcc_zext_dup): ... this, and add a custom VCC operand.
508 (add<mode>3_zext_dup_exec): Likewise, with ...
509 (add<mode>3_vcc_zext_dup_exec): ... this.
510 (add<mode>3_zext_dup2): Likewise, with ...
511 (add<mode>3_zext_dup_exec): ... this.
512 (add<mode>3_zext_dup2_exec): Likewise, with ...
513 (add<mode>3_zext_dup2): ... this.
514 * config/gcn/gcn.c (gcn_expand_scalar_to_vector_address): Switch
515 addv64di3_zext* calls to use addv64di3_vcc_zext*.
517 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
520 * config/i386/sse.md (truncv2dfv2df2): New insn pattern.
521 (extendv2sfv2df2): Ditto.
523 2020-05-14 H.J. Lu <hongjiu.lu@intel.com>
525 * configure: Regenerated.
527 2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
529 * config/arm/arm.c (reg_needs_saving_p): New function.
530 (use_return_insn): Use reg_needs_saving_p.
531 (arm_get_vfp_saved_size): Likewise.
532 (arm_compute_frame_layout): Likewise.
533 (arm_save_coproc_regs): Likewise.
534 (thumb1_expand_epilogue): Likewise.
535 (arm_expand_epilogue_apcs_frame): Likewise.
536 (arm_expand_epilogue): Likewise.
538 2020-05-14 Christophe Lyon <christophe.lyon@linaro.org>
540 * config/arm/arm.c (thumb1_expand_prologue): Update error message.
542 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
545 * config/i386/sse.md (sse2_cvtpi2pd): Add memory to alternative 1.
547 (floatv2siv2df2): New expander.
548 (floatunsv2siv2df2): New insn pattern.
550 (fix_truncv2dfv2si2): New expander.
551 (fixuns_truncv2dfv2si2): New insn pattern.
553 2020-05-14 Richard Sandiford <richard.sandiford@arm.com>
556 * config/aarch64/aarch64-sve-builtins.cc
557 (handle_arm_sve_vector_bits_attribute): Create a copy of the
558 original type's TYPE_MAIN_VARIANT, then reapply all the differences
559 between the original type and its main variant.
561 2020-05-14 Richard Biener <rguenther@suse.de>
564 * real.c (real_to_decimal_for_mode): Make sure we handle
565 a zero with nonzero exponent.
567 2020-05-14 Jakub Jelinek <jakub@redhat.com>
569 * Makefile.in (GTFILES): Add omp-general.c.
570 * cgraph.h (struct cgraph_node): Add declare_variant_alt and
571 calls_declare_variant_alt members and initialize them in the
573 * ipa.c (symbol_table::remove_unreachable_nodes): Handle direct
574 calls to declare_variant_alt nodes.
575 * lto-cgraph.c (lto_output_node): Write declare_variant_alt
576 and calls_declare_variant_alt.
577 (input_overwrite_node): Read them back.
578 * omp-simd-clone.c (simd_clone_create): Copy calls_declare_variant_alt
580 * tree-inline.c (expand_call_inline): Or in calls_declare_variant_alt
582 (tree_function_versioning): Copy calls_declare_variant_alt bit.
583 * omp-offload.c (execute_omp_device_lower): Call
584 omp_resolve_declare_variant on direct function calls.
585 (pass_omp_device_lower::gate): Also enable for
586 calls_declare_variant_alt functions.
587 * omp-general.c (omp_maybe_offloaded): Return false after inlining.
588 (omp_context_selector_matches): Handle the case when
589 cfun->curr_properties has PROP_gimple_any bit set.
590 (struct omp_declare_variant_entry): New type.
591 (struct omp_declare_variant_base_entry): New type.
592 (struct omp_declare_variant_hasher): New type.
593 (omp_declare_variant_hasher::hash, omp_declare_variant_hasher::equal):
595 (omp_declare_variants): New variable.
596 (struct omp_declare_variant_alt_hasher): New type.
597 (omp_declare_variant_alt_hasher::hash,
598 omp_declare_variant_alt_hasher::equal): New methods.
599 (omp_declare_variant_alt): New variables.
600 (omp_resolve_late_declare_variant): New function.
601 (omp_resolve_declare_variant): Call omp_resolve_late_declare_variant
602 when called late. Create a magic declare_variant_alt fndecl and
603 cgraph node and return that if decision needs to be deferred until
604 after gimplification.
605 * cgraph.c (symbol_table::create_edge): Or in calls_declare_variant_alt
609 * omp-simd-clone.c (struct modify_stmt_info): Add after_stmt member.
610 (ipa_simd_modify_stmt_ops): For PHIs, only add before first stmt in
611 entry block if info->after_stmt is NULL, otherwise add after that stmt
612 and update it after adding each stmt.
613 (ipa_simd_modify_function_body): Initialize info.after_stmt.
615 * function.h (struct function): Add has_omp_target bit.
616 * omp-offload.c (omp_discover_declare_target_fn_r): New function,
618 (omp_discover_declare_target_tgt_fn_r): ... this.
619 (omp_discover_declare_target_var_r): Call
620 omp_discover_declare_target_tgt_fn_r instead of
621 omp_discover_declare_target_fn_r.
622 (omp_discover_implicit_declare_target): Also queue functions with
623 has_omp_target bit set, for those walk with
624 omp_discover_declare_target_fn_r, for declare target to functions
625 walk with omp_discover_declare_target_tgt_fn_r.
627 2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
630 * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): Rename from mmx_pf2id.
631 Add SSE/AVX alternative. Change operand predicates from
632 nonimmediate_operand to register_mmxmem_operand.
633 Enable instruction pattern for TARGET_MMX_WITH_SSE.
634 (fix_truncv2sfv2si2): New expander.
635 (fixuns_truncv2sfv2si2): New insn pattern.
637 (mmx_floatv2siv2sf2): rename from mmx_floatv2si2.
638 Add SSE/AVX alternative. Change operand predicates from
639 nonimmediate_operand to register_mmxmem_operand.
640 Enable instruction pattern for TARGET_MMX_WITH_SSE.
641 (floatv2siv2sf2): New expander.
642 (floatunsv2siv2sf2): New insn pattern.
644 * config/i386/i386-builtin.def (IX86_BUILTIN_PF2ID):
646 (IX86_BUILTIN_PI2FD): Ditto.
648 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
650 * config/s390/s390.c (s390_emit_stack_probe): Call the probe_stack
652 * config/s390/s390.md ("@probe_stack2<mode>", "probe_stack"): New
655 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
657 * config/s390/s390.c (allocate_stack_space): Add missing updates
658 of last_probe_offset.
660 2020-05-14 Andreas Krebbel <krebbel@linux.ibm.com>
662 * config/s390/s390.md ("allocate_stack"): Call
663 anti_adjust_stack_and_probe_stack_clash when stack clash
664 protection is enabled.
665 * explow.c (anti_adjust_stack_and_probe_stack_clash): Remove
666 prototype. Remove static.
667 * explow.h (anti_adjust_stack_and_probe_stack_clash): Add
670 2020-05-13 Kelvin Nilsen <kelvin@gcc.gnu.org>
672 * config/rs6000/altivec.h (vec_extractl): New #define.
673 (vec_extracth): Likewise.
674 * config/rs6000/altivec.md (UNSPEC_EXTRACTL): New constant.
675 (UNSPEC_EXTRACTR): Likewise.
676 (vextractl<mode>): New expansion.
677 (vextractl<mode>_internal): New insn.
678 (vextractr<mode>): New expansion.
679 (vextractr<mode>_internal): New insn.
680 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vextdubvlx):
681 New built-in function.
682 (__builtin_altivec_vextduhvlx): Likewise.
683 (__builtin_altivec_vextduwvlx): Likewise.
684 (__builtin_altivec_vextddvlx): Likewise.
685 (__builtin_altivec_vextdubvhx): Likewise.
686 (__builtin_altivec_vextduhvhx): Likewise.
687 (__builtin_altivec_vextduwvhx): Likewise.
688 (__builtin_altivec_vextddvhx): Likewise.
689 (__builtin_vec_extractl): New overloaded built-in function.
690 (__builtin_vec_extracth): Likewise.
691 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
692 Define overloaded forms of __builtin_vec_extractl and
693 __builtin_vec_extracth.
694 (builtin_function_type): Add cases to mark arguments of new
695 built-in functions as unsigned.
696 (rs6000_common_init_builtins): Add
697 opaque_ftype_opaque_opaque_opaque_opaque.
698 * config/rs6000/rs6000.md (du_or_d): New mode attribute.
699 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
700 for a Future Architecture): Add description of vec_extractl and
701 vec_extractr built-in functions.
703 2020-05-13 Richard Biener <rguenther@suse.de>
705 * target.def (add_stmt_cost): Add new vectype parameter.
706 * targhooks.c (default_add_stmt_cost): Adjust.
707 * targhooks.h (default_add_stmt_cost): Likewise.
708 * config/aarch64/aarch64.c (aarch64_add_stmt_cost): Take new
710 * config/arm/arm.c (arm_add_stmt_cost): Likewise.
711 * config/i386/i386.c (ix86_add_stmt_cost): Likewise.
712 * config/rs6000/rs6000.c (rs6000_add_stmt_cost): Likewise.
714 * tree-vectorizer.h (stmt_info_for_cost::vectype): Add.
715 (dump_stmt_cost): Add new vectype parameter.
716 (add_stmt_cost): Likewise.
717 (record_stmt_cost): Likewise.
718 (record_stmt_cost): Add overload with old signature.
719 * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost):
721 (vect_get_known_peeling_cost): Likewise.
722 (vect_estimate_min_profitable_iters): Likewise.
723 * tree-vectorizer.c (dump_stmt_cost): Add new vectype parameter.
724 * tree-vect-stmts.c (record_stmt_cost): Likewise.
725 (vect_prologue_cost_for_slp_op): Remove stmt_vec_info parameter
726 and pass down correct vectype and NULL stmt_info.
727 (vect_model_simple_cost): Adjust.
728 (vect_model_store_cost): Likewise.
730 2020-05-13 Richard Biener <rguenther@suse.de>
732 * tree-vectorizer.h (SLP_INSTANCE_GROUP_SIZE): Remove.
733 (_slp_instance::group_size): Likewise.
734 * tree-vect-loop.c (vectorizable_reduction): The group size
735 is the number of lanes in the node.
736 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Likewise.
737 (vect_analyze_slp_instance): Do not set SLP_INSTANCE_GROUP_SIZE,
738 verify it matches the instance trees number of lanes.
739 (vect_slp_analyze_node_operations_1): Use the numer of lanes
740 in the node as group size.
741 (vect_bb_vectorization_profitable_p): Use the instance root
742 number of lanes for the size of life.
743 (vect_schedule_slp_instance): Use the number of lanes as
745 * tree-vect-stmts.c (vectorizable_load): Remove SLP instance
746 parameter. Use the number of lanes of the load for the group
747 size in the gap adjustment code.
748 (vect_analyze_stmt): Adjust.
749 (vect_transform_stmt): Likewise.
751 2020-05-13 Jakub Jelinek <jakub@redhat.com>
754 * cfgrtl.c (purge_dead_edges): Skip over debug and note insns even
755 if the last insn is a note.
757 PR tree-optimization/95060
758 * tree-ssa-math-opts.c (convert_mult_to_fma_1): Fold a NEGATE_EXPR
759 if it is the single use of the FMA internal builtin.
761 2020-05-13 Bin Cheng <bin.cheng@linux.alibaba.com>
763 PR tree-optimization/94969
764 * tree-data-dependence.c (constant_access_functions): Rename to...
765 (invariant_access_functions): ...this. Add parameter. Check for
766 invariant access function, rather than constant.
767 (build_classic_dist_vector): Call above function.
768 * tree-loop-distribution.c (pg_add_dependence_edges): Add comment.
770 2020-05-13 Hongtao Liu <hongtao.liu@intel.com>
773 * doc/extend.texi (x86Operandmodifiers): Document more x86
775 * gcc/config/i386/i386.c: Add comment for operand modifier N and I.
777 2020-05-12 Giuliano Belinassi <giuliano.belinassi@usp.br>
779 * tree-vrp.c (class vrp_insert): New.
780 (insert_range_assertions): Move to class vrp_insert.
781 (dump_all_asserts): Same as above.
782 (dump_asserts_for): Same as above.
783 (live): Same as above.
784 (need_assert_for): Same as above.
785 (live_on_edge): Same as above.
786 (finish_register_edge_assert_for): Same as above.
787 (find_switch_asserts): Same as above.
788 (find_assert_locations): Same as above.
789 (find_assert_locations_1): Same as above.
790 (find_conditional_asserts): Same as above.
791 (process_assert_insertions): Same as above.
792 (register_new_assert_for): Same as above.
793 (vrp_prop): New variable fun.
794 (vrp_initialize): New parameter.
795 (identify_jump_threads): Same as above.
796 (execute_vrp): Same as above.
799 2020-05-12 Keith Packard <keith.packard@sifive.com>
801 * config/riscv/riscv.c (riscv_unique_section): New.
802 (TARGET_ASM_UNIQUE_SECTION): New.
804 2020-05-12 Craig Blackmore <craig.blackmore@embecosm.com>
806 * config.gcc: Add riscv-shorten-memrefs.o to extra_objs for riscv.
807 * config/riscv/riscv-passes.def: New file.
808 * config/riscv/riscv-protos.h (make_pass_shorten_memrefs): Declare.
809 * config/riscv/riscv-shorten-memrefs.c: New file.
810 * config/riscv/riscv.c (tree-pass.h): New include.
811 (riscv_compressed_reg_p): New Function
812 (riscv_compressed_lw_offset_p): Likewise.
813 (riscv_compressed_lw_address_p): Likewise.
814 (riscv_shorten_lw_offset): Likewise.
815 (riscv_legitimize_address): Attempt to convert base + large_offset
816 to compressible new_base + small_offset.
817 (riscv_address_cost): Make anticipated compressed load/stores
818 cheaper for code size than uncompressed load/stores.
819 (riscv_register_priority): Move compressed register check to
820 riscv_compressed_reg_p.
821 * config/riscv/riscv.h (C_S_BITS): Define.
822 (CSW_MAX_OFFSET): Define.
823 * config/riscv/riscv.opt (mshorten-memefs): New option.
824 * config/riscv/t-riscv (riscv-shorten-memrefs.o): New rule.
825 (PASSES_EXTRA): Add riscv-passes.def.
826 * doc/invoke.texi: Document -mshorten-memrefs.
828 * config/riscv/riscv.c (riscv_new_address_profitable_p): New function.
829 (TARGET_NEW_ADDRESS_PROFITABLE_P): Define.
830 * doc/tm.texi: Regenerate.
831 * doc/tm.texi.in (TARGET_NEW_ADDRESS_PROFITABLE_P): New hook.
832 * sched-deps.c (attempt_change): Use old address if it is cheaper than
834 * target.def (new_address_profitable_p): New hook.
835 * targhooks.c (default_new_address_profitable_p): New function.
836 * targhooks.h (default_new_address_profitable_p): Declare.
838 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
841 * config/i386/mmx.md (copysignv2sf3): New expander.
842 (xorsignv2sf3): Ditto.
843 (signbitv2sf3): Ditto.
845 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
848 * config/i386/mmx.md (fmav2sf4): New insn pattern.
853 2020-05-12 H.J. Lu <hongjiu.lu@intel.com>
855 * Makefile.in (CET_HOST_FLAGS): New.
856 (COMPILER): Add $(CET_HOST_FLAGS).
857 * configure.ac: Add GCC_CET_HOST_FLAGS(CET_HOST_FLAGS) and
858 AC_SUBST(CET_HOST_FLAGS). Clear CET_HOST_FLAGS if jit isn't
860 * aclocal.m4: Regenerated.
861 * configure: Likewise.
863 2020-05-12 Uroš Bizjak <ubizjak@gmail.com>
866 * config/i386/mmx.md (<code>v2sf2): New insn pattern.
867 (*mmx_<code>v2sf2): New insn_and_split pattern.
868 (*mmx_nabsv2sf2): Ditto.
869 (*mmx_andnotv2sf3): New insn pattern.
870 (*mmx_<code>v2sf3): Ditto.
871 * config/i386/i386.md (absneg_op): New code attribute.
872 * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
873 (ix86_build_signbit_mask): Ditto.
875 2020-05-12 Richard Biener <rguenther@suse.de>
877 * tree-ssa-live.c (remove_unused_locals): Remove dead debug
880 2020-05-12 Jozef Lawrynowicz <jozef.l@mittosystems.com>
882 * config/msp430/msp430-protos.h (msp430_output_aligned_decl_common):
883 Update prototype to include "local" argument.
884 * config/msp430/msp430.c (msp430_output_aligned_decl_common): Add
885 "local" argument. Handle local common decls.
886 * config/msp430/msp430.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Adjust
887 msp430_output_aligned_decl_common call with 0 for "local" argument.
888 (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Define.
890 2020-05-12 Richard Biener <rguenther@suse.de>
892 * cfghooks.c (split_edge): Preserve EDGE_DFS_BACK if set.
894 2020-05-12 Martin Liska <mliska@suse.cz>
898 * sanopt.c (sanitize_rewrite_addressable_params):
899 Clear DECL_NOT_GIMPLE_REG_P for argument.
901 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
903 PR tree-optimization/94980
904 * tree-vect-generic.c (expand_vector_comparison): Use
905 vector_element_bits_tree to get the element size in bits,
906 rather than using TYPE_SIZE.
907 (expand_vector_condition, vector_element): Likewise.
909 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
911 PR tree-optimization/94980
912 * tree-vect-generic.c (build_replicated_const): Take the number
913 of bits as a parameter, instead of the type of the elements.
914 (do_plus_minus): Update accordingly, using vector_element_bits
915 to calculate the correct number of bits.
916 (do_negate): Likewise.
918 2020-05-12 Richard Sandiford <richard.sandiford@arm.com>
920 PR tree-optimization/94980
921 * tree.h (vector_element_bits, vector_element_bits_tree): Declare.
922 * tree.c (vector_element_bits, vector_element_bits_tree): New.
923 * match.pd: Use the new functions instead of determining the
924 vector element size directly from TYPE_SIZE(_UNIT).
925 * tree-vect-data-refs.c (vect_gather_scatter_fn_p): Likewise.
926 * tree-vect-patterns.c (vect_recog_mask_conversion_pattern): Likewise.
927 * tree-vect-stmts.c (vect_is_simple_cond): Likewise.
928 * tree-vect-generic.c (expand_vector_piecewise): Likewise.
929 (expand_vector_conversion): Likewise.
930 (expand_vector_addition): Likewise for a TYPE_SIZE_UNIT used as
931 a divisor. Convert the dividend to bits to compensate.
932 * tree-vect-loop.c (vectorizable_live_operation): Call
933 vector_element_bits instead of open-coding it.
935 2020-05-12 Jakub Jelinek <jakub@redhat.com>
937 * omp-offload.h (omp_discover_implicit_declare_target): Declare.
938 * omp-offload.c: Include context.h.
939 (omp_declare_target_fn_p, omp_declare_target_var_p,
940 omp_discover_declare_target_fn_r, omp_discover_declare_target_var_r,
941 omp_discover_implicit_declare_target): New functions.
942 * cgraphunit.c (analyze_functions): Call
943 omp_discover_implicit_declare_target.
945 2020-05-12 Richard Biener <rguenther@suse.de>
947 * gimple-fold.c (maybe_canonicalize_mem_ref_addr): Canonicalize
948 literal constant &MEM[..] to a constant literal.
950 2020-05-12 Richard Biener <rguenther@suse.de>
952 PR tree-optimization/95045
953 * dbgcnt.def (lim): Add debug-counter.
954 * tree-ssa-loop-im.c: Include dbgcnt.h.
955 (find_refs_for_sm): Use lim debug counter for store motion
957 (do_store_motion): Rename form store_motion. Commit edge
959 (store_motion_loop): ... here.
960 (tree_ssa_lim): Adjust.
962 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
964 * config/rs6000/altivec.h (vec_clzm): Rename to vec_cntlzm.
965 (vec_ctzm): Rename to vec_cnttzm.
966 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
967 Change fourth operand for vec_ternarylogic to require
968 compatibility with unsigned SImode rather than unsigned QImode.
969 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
970 Remove overloaded forms of vec_gnb that are no longer needed.
971 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
972 for a Future Architecture): Replace vec_clzm with vec_cntlzm;
973 replace vec_ctzm with vec_cntlzm; remove four unwanted forms of
974 vec_gnb; move vec_ternarylogic documentation into this section
975 and replace const unsigned char with const unsigned int as its
978 2020-05-11 Carl Love <cel@us.ibm.com>
980 * config/rs6000/altivec.h (vec_genpcvm): New #define.
981 * config/rs6000/rs6000-builtin.def (XXGENPCVM_V16QI): New built-in
983 (XXGENPCVM_V8HI): Likewise.
984 (XXGENPCVM_V4SI): Likewise.
985 (XXGENPCVM_V2DI): Likewise.
986 (XXGENPCVM): New overloaded built-in instantiation.
987 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Add
988 entries for FUTURE_BUILTIN_VEC_XXGENPCVM.
989 (altivec_expand_builtin): Add special handling for
990 FUTURE_BUILTIN_VEC_XXGENPCVM.
991 (builtin_function_type): Add handling for
992 FUTURE_BUILTIN_XXGENPCVM_{V16QI,V8HI,V4SI,V2DI}.
993 * config/rs6000/vsx.md (VSX_EXTRACT_I4): New mode iterator.
994 (UNSPEC_XXGENPCV): New constant.
995 (xxgenpcvm_<mode>_internal): New insn.
996 (xxgenpcvm_<mode>): New expansion.
997 * doc/extend.texi: Add documentation for vec_genpcvm built-ins.
999 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1001 * config/rs6000/altivec.h (vec_strir): New #define.
1002 (vec_stril): Likewise.
1003 (vec_strir_p): Likewise.
1004 (vec_stril_p): Likewise.
1005 * config/rs6000/altivec.md (UNSPEC_VSTRIR): New constant.
1006 (UNSPEC_VSTRIL): Likewise.
1007 (vstrir_<mode>): New expansion.
1008 (vstrir_code_<mode>): New insn.
1009 (vstrir_p_<mode>): New expansion.
1010 (vstrir_p_code_<mode>): New insn.
1011 (vstril_<mode>): New expansion.
1012 (vstril_code_<mode>): New insn.
1013 (vstril_p_<mode>): New expansion.
1014 (vstril_p_code_<mode>): New insn.
1015 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vstribr):
1016 New built-in function.
1017 (__builtin_altivec_vstrihr): Likewise.
1018 (__builtin_altivec_vstribl): Likewise.
1019 (__builtin_altivec_vstrihl): Likewise.
1020 (__builtin_altivec_vstribr_p): Likewise.
1021 (__builtin_altivec_vstrihr_p): Likewise.
1022 (__builtin_altivec_vstribl_p): Likewise.
1023 (__builtin_altivec_vstrihl_p): Likewise.
1024 (__builtin_vec_strir): New overloaded built-in function.
1025 (__builtin_vec_stril): Likewise.
1026 (__builtin_vec_strir_p): Likewise.
1027 (__builtin_vec_stril_p): Likewise.
1028 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
1029 Define overloaded forms of __builtin_vec_strir,
1030 __builtin_vec_stril, __builtin_vec_strir_p, and
1031 __builtin_vec_stril_p.
1032 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
1033 for a Future Architecture): Add description of vec_stril,
1034 vec_stril_p, vec_strir, and vec_strir_p built-in functions.
1036 2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>
1038 * config/rs6000/altivec.h (vec_ternarylogic): New #define.
1039 * config/rs6000/altivec.md (UNSPEC_XXEVAL): New constant.
1041 * config/rs6000/predicates.md (u8bit_cint_operand): New predicate.
1042 * config/rs6000/rs6000-builtin.def: Add handling of new macro
1044 (BU_FUTURE_V_4): New macro. Use it.
1045 (BU_FUTURE_OVERLOAD_4): Likewise.
1046 * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Add
1047 handling for quaternary built-in functions.
1048 (altivec_resolve_overloaded_builtin): Add special-case handling
1049 for __builtin_vec_xxeval.
1050 * config/rs6000/rs6000-call.c: Add handling of new macro
1051 RS6000_BUILTIN_4 in initialization of rs6000_builtin_info,
1052 bdesc0_arg, bdesc1_arg, bdesc2_arg, bdesc_3arg,
1053 bdesc_altivec_preds, bdesc_abs, and bdesc_htm arrays.
1054 (altivec_overloaded_builtins): Add definitions for
1055 FUTURE_BUILTIN_VEC_XXEVAL.
1056 (bdesc_4arg): New array.
1057 (htm_expand_builtin): Add handling for quaternary built-in
1059 (rs6000_expand_quaternop_builtin): New function.
1060 (rs6000_expand_builtin): Add handling for quaternary built-in
1062 (rs6000_init_builtins): Initialize builtin_mode_to_type entries
1063 for unsigned QImode and unsigned HImode.
1064 (builtin_quaternary_function_type): New function.
1065 (rs6000_common_init_builtins): Add handling of quaternary
1067 * config/rs6000/rs6000.h (RS6000_BTC_QUATERNARY): New defined
1069 (RS6000_BTC_PREDICATE): Change value of constant.
1070 (RS6000_BTC_ABS): Likewise.
1071 (rs6000_builtins): Add support for new macro RS6000_BUILTIN_4.
1072 * doc/extend.texi (PowerPC AltiVec Built-In Functions Available
1073 for a Future Architecture): Add description of vec_ternarylogic
1076 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1078 * config/rs6000/rs6000-builtin.def (__builtin_pdepd): New built-in
1080 (__builtin_pextd): Likewise.
1081 * config/rs6000/rs6000.md (UNSPEC_PDEPD): New constant.
1082 (UNSPEC_PEXTD): Likewise.
1085 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
1086 a Future Architecture): Add descriptions of __builtin_pdepd and
1087 __builtin_pextd functions.
1089 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1091 * config/rs6000/altivec.h (vec_clrl): New #define.
1092 (vec_clrr): Likewise.
1093 * config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant.
1094 (UNSPEC_VCLRRB): Likewise.
1097 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New
1099 (__builtin_altivec_vclrrb): Likewise.
1100 (__builtin_vec_clrl): New overloaded built-in function.
1101 (__builtin_vec_clrr): Likewise.
1102 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
1103 Define overloaded forms of __builtin_vec_clrl and
1105 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
1106 for a Future Architecture): Add descriptions of vec_clrl and
1109 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1111 * config/rs6000/rs6000-builtin.def (__builtin_cntlzdm): New
1112 built-in function definition.
1113 (__builtin_cnttzdm): Likewise.
1114 * config/rs6000/rs6000.md (UNSPEC_CNTLZDM): New constant.
1115 (UNSPEC_CNTTZDM): Likewise.
1116 (cntlzdm): New insn.
1117 (cnttzdm): Likewise.
1118 * doc/extend.texi (Basic PowerPC Built-in Functions available for
1119 a Future Architecture): Add descriptions of __builtin_cntlzdm and
1120 __builtin_cnttzdm functions.
1122 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
1125 * config/i386/mmx.md (sqrtv2sf2): New insn pattern.
1127 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1129 * config/rs6000/altivec.h (vec_cfuge): New #define.
1130 * config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant.
1131 (vcfuged): New insn.
1132 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged):
1133 New built-in function.
1134 * config/rs6000/rs6000-call.c (builtin_function_type): Add
1135 handling for FUTURE_BUILTIN_VCFUGED case.
1136 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
1137 for a Future Architecture): Add description of vec_cfuge built-in
1140 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1142 * config/rs6000/rs6000-builtin.def (BU_FUTURE_MISC_0): New
1144 (BU_FUTURE_MISC_1): Likewise.
1145 (BU_FUTURE_MISC_2): Likewise.
1146 (BU_FUTURE_MISC_3): Likewise.
1147 (__builtin_cfuged): New built-in function definition.
1148 * config/rs6000/rs6000.md (UNSPEC_CFUGED): New constant.
1150 * doc/extend.texi (Basic PowerPC Built-in Functions Available for
1151 a Future Architecture): New subsubsection.
1153 2020-05-11 Richard Biener <rguenther@suse.de>
1155 PR tree-optimization/95049
1156 * tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition
1157 between different constants.
1159 2020-05-11 Richard Sandiford <richard.sandiford@arm.com>
1161 * tree-pretty-print.c (dump_generic_node): Handle BOOLEAN_TYPEs.
1163 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1164 Bill Schmidt <wschmidt@linux.ibm.com>
1166 * config/rs6000/altivec.h (vec_gnb): New #define.
1167 * config/rs6000/altivec.md (UNSPEC_VGNB): New constant.
1169 * config/rs6000/rs6000-builtin.def (BU_FUTURE_OVERLOAD_1): New
1171 (BU_FUTURE_OVERLOAD_2): Likewise.
1172 (BU_FUTURE_OVERLOAD_3): Likewise.
1173 (__builtin_altivec_gnb): New built-in function.
1174 (__buiiltin_vec_gnb): New overloaded built-in function.
1175 * config/rs6000/rs6000-call.c (altivec_overloaded_builtins):
1176 Define overloaded forms of __builtin_vec_gnb.
1177 (rs6000_expand_binop_builtin): Add error checking for 2nd argument
1178 of __builtin_vec_gnb.
1179 (builtin_function_type): Mark return value and arguments unsigned
1180 for FUTURE_BUILTIN_VGNB.
1181 * doc/extend.texi (PowerPC AltiVec Built-in Functions Available
1182 for a Future Architecture): Add description of vec_gnb built-in
1185 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1186 Bill Schmidt <wschmidt@linux.ibm.com>
1188 * config/rs6000/altivec.h (vec_pdep): New macro implementing new
1190 (vec_pext): Likewise.
1191 * config/rs6000/altivec.md (UNSPEC_VPDEPD): New constant.
1192 (UNSPEC_VPEXTD): Likewise.
1195 * config/rs6000/rs6000-builtin.def (__builtin_altivec_vpdepd): New
1197 (__builtin_altivec_vpextd): Likewise.
1198 * config/rs6000/rs6000-call.c (builtin_function_type): Add
1199 handling for FUTURE_BUILTIN_VPDEPD and FUTURE_BUILTIN_VPEXTD
1201 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
1202 for a Future Architecture): Add description of vec_pdep and
1203 vec_pext built-in functions.
1205 2020-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
1206 Bill Schmidt <wschmidt@linux.ibm.com>
1208 * config/rs6000/altivec.h (vec_clzm): New macro.
1209 (vec_ctzm): Likewise.
1210 * config/rs6000/altivec.md (UNSPEC_VCLZDM): New constant.
1211 (UNSPEC_VCTZDM): Likewise.
1214 * config/rs6000/rs6000-builtin.def (BU_FUTURE_V_0): New macro.
1215 (BU_FUTURE_V_1): Likewise.
1216 (BU_FUTURE_V_2): Likewise.
1217 (BU_FUTURE_V_3): Likewise.
1218 (__builtin_altivec_vclzdm): New builtin definition.
1219 (__builtin_altivec_vctzdm): Likewise.
1220 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Cause
1221 _ARCH_PWR_FUTURE macro to be defined if OPTION_MASK_FUTURE flag is
1223 * config/rs6000/rs6000-call.c (builtin_function_type): Set return
1224 value and parameter types to be unsigned for VCLZDM and VCTZDM.
1225 * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
1226 support for TARGET_FUTURE flag.
1227 * config/rs6000/rs6000.h (RS6000_BTM_FUTURE): New macro constant.
1228 * doc/extend.texi (PowerPC Altivec Built-in Functions Available
1229 for a Future Architecture): New subsubsection.
1231 2020-05-11 Richard Biener <rguenther@suse.de>
1233 PR tree-optimization/94988
1234 PR tree-optimization/95025
1235 * tree-ssa-loop-im.c (seq_entry): Make a struct, add from.
1236 (sm_seq_push_down): Take extra parameter denoting where we
1238 (execute_sm_exit): Re-issue sm_other stores in the correct
1240 (sm_seq_valid_bb): When always executed, allow sm_other to
1241 prevail inbetween sm_ord and record their stored value.
1242 (hoist_memory_references): Adjust refs_not_supported propagation
1243 and prune sm_other from the end of the ordered sequences.
1245 2020-05-11 Felix Yang <felix.yang@huawei.com>
1248 * config/aarch64/aarch64.md (mov<mode>):
1249 Bitcasts to the equivalent integer mode using gen_lowpart
1250 instead of doing FAIL for scalar floating point move.
1252 2020-05-11 Alex Coplan <alex.coplan@arm.com>
1254 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Add case
1255 to correctly calculate cost for new pattern (*csinv3_uxtw_insn3).
1256 * config/aarch64/aarch64.md (*csinv3_utxw_insn1): New.
1257 (*csinv3_uxtw_insn2): New.
1258 (*csinv3_uxtw_insn3): New.
1259 * config/aarch64/iterators.md (neg_not_cs): New.
1261 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
1264 * config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint
1265 instead of "Yv" for AVX alternatives. Add "prefix" attribute.
1266 (*mmx_addv2sf3): Ditto.
1267 (*mmx_subv2sf3): Ditto.
1268 (*mmx_mulv2sf3): Ditto.
1269 (*mmx_<code>v2sf3): Ditto.
1270 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
1272 2020-05-11 Uroš Bizjak <ubizjak@gmail.com>
1275 * config/i386/i386.c (ix86_vector_mode_supported_p):
1276 Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
1277 * config/i386/mmx.md (*mov<mode>_internal): Do not set
1278 mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.
1280 (mmx_addv2sf3): Change operand predicates from
1281 nonimmediate_operand to register_mmxmem_operand.
1282 (addv2sf3): New expander.
1283 (*mmx_addv2sf3): Add SSE/AVX alternatives. Change operand
1284 predicates from nonimmediate_operand to register_mmxmem_operand.
1285 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1287 (mmx_subv2sf3): Change operand predicate from
1288 nonimmediate_operand to register_mmxmem_operand.
1289 (mmx_subrv2sf3): Ditto.
1290 (subv2sf3): New expander.
1291 (*mmx_subv2sf3): Add SSE/AVX alternatives. Change operand
1292 predicates from nonimmediate_operand to register_mmxmem_operand.
1293 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1295 (mmx_mulv2sf3): Change operand predicates from
1296 nonimmediate_operand to register_mmxmem_operand.
1297 (mulv2sf3): New expander.
1298 (*mmx_mulv2sf3): Add SSE/AVX alternatives. Change operand
1299 predicates from nonimmediate_operand to register_mmxmem_operand.
1300 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1302 (mmx_<code>v2sf3): Change operand predicates from
1303 nonimmediate_operand to register_mmxmem_operand.
1304 (<code>v2sf3): New expander.
1305 (*mmx_<code>v2sf3): Add SSE/AVX alternatives. Change operand
1306 predicates from nonimmediate_operand to register_mmxmem_operand.
1307 Enable instruction pattern for TARGET_MMX_WITH_SSE.
1308 (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.
1310 2020-05-11 Martin Liska <mliska@suse.cz>
1313 * common.opt: Fix typo in option description.
1315 2020-05-11 Martin Liska <mliska@suse.cz>
1317 PR gcov-profile/94928
1318 * gcov-io.h: Add caveat about coverage format parsing and
1319 possible outdated documentation.
1321 2020-05-11 Xiong Hu Luo <luoxhu@linux.ibm.com>
1323 PR tree-optimization/83403
1324 * tree-affine.c (expr_to_aff_combination): Replace SSA_NAME with
1325 determine_value_range, Add fold conversion of MULT_EXPR, fix the
1328 2020-05-10 Gerald Pfeifer <gerald@pfeifer.com>
1330 * config/i386/i386-c.c (ix86_target_macros): Define _ILP32 and
1331 __ILP32__ for 32-bit targets.
1333 2020-05-09 Eric Botcazou <ebotcazou@adacore.com>
1335 * tree.h (expr_align): Delete.
1336 * tree.c (expr_align): Likewise.
1338 2020-05-09 Hans-Peter Nilsson <hp@axis.com>
1340 * resource.c (init_resource_info): Filter-out TARGET_FLAGS_REGNUM
1341 from end_of_function_needs.
1343 * config.gcc: Remove support for crisv32-*-* and cris-*-linux*.
1344 * config/cris/t-linux, config/cris/linux.h, config/cris/linux.opt:
1346 * config/cris/t-elfmulti: Remove crisv32 multilib.
1347 * config/cris: Remove shared-library and CRIS v32 support.
1349 Move trivially from cc0 to reg:CC model, removing most optimizations.
1350 * config/cris/cris.md: Remove all side-effect patterns and their
1351 splitters. Remove most peepholes. Add clobbers of CRIS_CC0_REGNUM
1352 to all but post-reload control-flow and movem insns. Remove
1353 constraints on all modified expanders. Remove obsoleted cc0-related
1355 (attr "cc"): Remove alternative "rev".
1356 (mode_iterator BWDD, DI_, SI_): New.
1357 (mode_attr sCC_destc, cmp_op1c, cmp_op2c): New.
1358 ("tst<mode>"): Remove; fold as "M" alternative into compare insn.
1359 ("mstep_shift", "mstep_mul"): Remove patterns.
1360 ("s<rcond>", "s<ocond>", "s<ncond>"): Anonymize.
1361 * config/cris/cris.c: Change all non-condition-code,
1362 non-control-flow emitted insns to add a parallel with clobber of
1363 CRIS_CC0_REGNUM, mostly by changing from gen_rtx_SET with
1364 emit_insn to use of emit_move_insn, gen_add2_insn or
1365 cris_emit_insn, as convenient.
1366 (cris_reg_overlap_mentioned_p)
1367 (cris_normal_notice_update_cc, cris_notice_update_cc): Remove.
1368 (cris_movem_load_rest_p): Don't assume all elements in a
1370 (cris_store_multiple_op_p): Ditto.
1371 (cris_emit_insn): New function.
1372 * cris/cris-protos.h (cris_emit_insn): Declare.
1375 * config/cris/cris.md (zcond): New code_iterator.
1376 ("*cbranch<mode>4_btstq<CC>"): New insn_and_split.
1378 * config/cris/cris.c (TARGET_FLAGS_REGNUM): Define.
1380 * config/cris/cris.h (REVERSIBLE_CC_MODE): Define to true.
1382 * config/cris/cris.md ("movsi"): For memory destination
1383 post-reload, generate clobberless variant. Similarly for a
1384 zero-source post-reload.
1385 ("*mov_tomem<mode>_split"): New split.
1386 ("*mov_tomem<mode>"): New insn.
1387 ("enabled", mov_tomem_enabled): Define and use to exclude "x" ->
1388 "Q>m" for less-than-SImode.
1389 ("*mov_fromzero<mode>_split"): New split.
1390 ("*mov_fromzero<mode>"): New insn.
1392 Prepare for cmpelim pass to eliminate redundant compare insns.
1393 * config/cris/cris-modes.def: New file.
1394 * config/cris/cris-protos.h (cris_select_cc_mode): Declare.
1395 (cris_notice_update_cc): Remove left-over declaration.
1396 * config/cris/cris.c (TARGET_CC_MODES_COMPATIBLE): Define.
1397 (cris_select_cc_mode, cris_cc_modes_compatible): New functions.
1398 * config/cris/cris.h (SELECT_CC_MODE): Define.
1399 * config/cris/cris.md (NZSET, NZUSE, NZVCSET, NZVCUSE): New
1401 (cond): New code_iterator.
1402 (nzcond): Replacement for incorrect ncond. All callers changed.
1403 (nzvccond): Replacement for ocond. All callers changed.
1404 (rnzcond): Replacement for rcond. All callers changed.
1405 (xCC): New code_attr.
1406 (cmp_op1c, cmp_op0c): Renumber from cmp_op1c and cmp_op2c. All
1408 ("*cmpdi<NZVCSET:mode>"): Rename from "*cmpdi". Replace
1409 CCmode with iteration over NZVCSET.
1410 ("*cmp_ext<BW:mode><NZVCSET:mode>"): Similarly; rename from
1412 ("*cmpsi<NZVCSET:mode>"): Similarly, from "*cmpsi".
1413 ("*cmp<BW:mode><NZVCSET:mode>"): Similarly from "*cmp<mode>".
1414 ("*btst<mode>"): Similarly, from "*btst".
1415 ("*cbranch<mode><code>4"): Rename from "*cbranch<mode>4",
1416 iterating over cond instead of matching the comparison with
1417 ordered_comparison_operator.
1418 ("*cbranch<mode>4_btstq<CC>"): Correct label operand number.
1419 ("b<zcond:code><mode>"): Rename from "b<ncond:code>", iterating
1421 ("b<nzvccond:code><mode>"): Similarly from "b<ocond:code>", over
1422 NZVCUSE. Remove FIXME.
1423 ("*b<nzcond:code>_reversed<mode>"): Similarly from
1424 "*b<ncond:code>_reversed", over NZUSE.
1425 ("*b<nzvccond:code>_reversed<mode>"): Similarly from
1426 "*b<ocond:code>_reversed", over NZVCUSE. Remove FIXME.
1427 ("b<rnzcond:code><mode>"): Similarly from "b<rcond:code>",
1428 over NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
1429 depending on CC_NZmode vs. CCmode. Remove FIXME.
1430 ("*b<rnzcond:code>_reversed<mode>"): Similarly from
1431 "*b<rcond:code>_reversed", over NZUSE.
1432 ("*cstore<mode><code>4"): Rename from "*cstore<mode>4",
1433 iterating over cond instead of matching the comparison with
1434 ordered_comparison_operator.
1435 ("*s<nzcond:code><mode>"): Rename from "*s<ncond:code>",
1436 iterating over NZUSE.
1437 ("*s<rnzcond:code><mode>"): Similar from "*s<rcond:code>", over
1438 NZUSE. Reinstate "b<oCC>" vs. "b<CC>" mnemonic choice,
1439 depending on CC_NZmode vs. CCmode.
1440 ("*s<nzvccond:code><mode>"): Simlar from "*s<ocond:code>", over
1441 NZVCUSE. Remove FIXME.
1442 ("cc"): Comment on new use.
1443 ("cc_enabled"): New attribute.
1444 ("enabled"): Make default fall back to cc_enabled.
1445 ("setnz", "ccnz", "setnzvc", "ccnzvc", "setcc", "cccc"): New
1446 default_subst_attrs.
1447 ("setnz_subst", "setnzvc_subst", "setcc_subst"): New default_subst.
1448 ("*movsi_internal<setcc><setnz><setnzvc>"): Rename from
1449 "*movsi_internal". Correct contents of, and rename attribute
1450 "cc" to "cc<cccc><ccnz><ccnzvc>".
1451 ("anz", "anzvc", "acc"): New define_subst_attrs.
1452 ("<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>"): Rename from
1453 "movhi". Rename "cc" attribute to "cc<cccc><ccnz><ccnzvc>".
1454 ("<acc><anz><anzvc>movqi<setcc><setnz><setnzvc>"): Similar from
1455 "movqi". Correct contents of, and rename "cc" attribute to
1456 "cc<cccc><ccnz><ccnzvc>".
1457 ("*b<zcond:code><mode>"): Rename from "b<zcond:code><mode>".
1458 ("*b<nzvccond:code><mode>"): Rename from "b<nzvccond:code><mode>".
1459 ("*b<rnzcond:code><mode>"): Rename from "*b<rnzcond:code><mode>".
1460 ("<acc><anz><anzvc>extend<mode>si2<setcc><setnz><setnzvc>"):
1461 Rename from "extend<mode>si2".
1462 ("<acc><anz><anzvc>zero_extend<mode>si2<setcc><setnz><setnzvc>"):
1463 Similar, from "zero_extend<mode>si2".
1464 ("*adddi3<setnz>"): Rename from "*adddi3".
1465 ("*subdi3<setnz>"): Similarly from "*subdi3".
1466 ("*addsi3<setnz>"): Similarly from "*addsi3".
1467 ("*subsi3<setnz>"): Similarly from "*subsi3".
1468 ("*addhi3<setnz>"): Similarly from "*addhi3" and decorate the
1469 "cc" attribute to "cc<ccnz>".
1470 ("*addqi3<setnz>"): Similarly from "*addqi3".
1471 ("*sub<mode>3<setnz>"): Similarly from "*sub<mode>3".
1472 ("*expanded_andsi<setcc><setnz><setnzvc>"): Rename from
1474 ("*iorsi3<setcc><setnz><setnzvc>"): Similar from "*iorsi3".
1475 Decorate "cc" attribute to make "cc<cccc><ccnz><ccnzvc>".
1476 ("*iorhi3<setcc><setnz><setnzvc>"): Similar from "*iorhi3".
1477 ("*iorqi3<setcc><setnz><setnzvc>"): Similar from "*iorqi3".
1478 ("*expanded_andhi<setcc><setnz><setnzvc>"): Similar from
1479 "*expanded_andhi". Add quick cc-setting alternative for 0..31.
1480 ("*andqi3<setcc><setnz><setnzvc>"): Similar from "*andqi3".
1481 ("<acc><anz><anzvc>xorsi3<setcc><setnz><setnzvc>"): Rename
1483 ("<acc><anz><anzvc>one_cmplsi2<setcc><setnz><setnzvc>"): Rename
1485 ("<acc><anz><anzvc><shlr>si3<setcc><setnz><setnzvc>"): Rename
1487 ("<acc><anz><anzvc>clzsi2<setcc><setnz><setnzvc>"): Rename
1489 ("<acc><anz><anzvc>bswapsi2<setcc><setnz><setnzvc>"): Rename
1491 ("*uminsi3<setcc><setnz><setnzvc>"): Rename from "*uminsi3".
1493 * config/cris/cris-modes.def (CC_ZnN): New CC_MODE.
1494 * config/cris/cris.c (cris_rtx_costs): Handle pre-split bit-test
1495 * config/cris/cris.md (ZnNNZSET, ZnNNZUSE): New mode_iterators.
1496 (znnCC, rznnCC): New code_attrs.
1497 ("*btst<mode>"): Iterator over ZnNNZSET instead of NZVCSET. Remove
1498 obseolete comment. Add belt-and-suspenders mode-test to condition.
1499 Add fixme regarding remaining matched-but-not-generated case.
1500 ("*cbranch<mode>4_btstrq1_<CC>"): New insn_and_split.
1501 ("*cbranch<mode>4_btstqb0_<CC>"): Rename from
1502 "*cbranch<mode>4_btstq<CC>". Split to CC_NZ instead of CC.
1503 ("*b<zcond:code><mode>"): Iterate over ZnNNZUSE instead of NZUSE.
1504 Handle output of CC_ZnNmode.
1505 ("*b<nzcond:code>_reversed<mode>"): Ditto.
1507 * config/cris/cris.c (cris_select_cc_mode): Return CC_NZmode for
1508 NEG too. Correct comment.
1509 * config/cris/cris.md ("<anz>neg<mode>2<setnz>"): Rename from
1512 2020-05-08 Vladimir Makarov <vmakarov@redhat.com>
1514 * ira-color.c (update_costs_from_allocno): Remove
1515 conflict_cost_update_p argument. Propagate costs only along
1516 threads. Always do conflict cost update. Add printing debugging
1518 (update_costs_from_copies): Add printing debugging info.
1519 (restore_costs_from_copies): Ditto.
1520 (assign_hard_reg): Improve debug info.
1521 (push_only_colorable): Ditto. Call update_costs_from_prefs.
1522 (color_allocnos): Remove update_costs_from_prefs.
1524 2020-05-08 Richard Biener <rguenther@suse.de>
1526 * tree-vectorizer.h (vec_info::slp_loads): New.
1527 (vect_optimize_slp): Declare.
1528 * tree-vect-slp.c (vect_attempt_slp_rearrange_stmts): Do
1529 nothing when there are no loads.
1530 (vect_gather_slp_loads): Gather loads into a vector.
1531 (vect_supported_load_permutation_p): Remove.
1532 (vect_analyze_slp_instance): Do not verify permutation
1534 (vect_analyze_slp): Optimize permutations of reductions
1535 after all SLP instances have been gathered and gather
1537 (vect_optimize_slp): New function split out from
1538 vect_supported_load_permutation_p. Elide some permutations.
1539 (vect_slp_analyze_bb_1): Call vect_optimize_slp.
1540 * tree-vect-loop.c (vect_analyze_loop_2): Likewise.
1541 * tree-vect-stmts.c (vectorizable_load): Check whether
1542 the load can be permuted. When generating code assert we can.
1544 2020-05-08 Richard Biener <rguenther@suse.de>
1546 * tree-ssa-sccvn.c (rpo_avail): Change type to
1547 eliminate_dom_walker *.
1548 (eliminate_with_rpo_vn): Adjust rpo_avail to make vn_valueize
1549 use the DOM walker availability.
1550 (vn_reference_fold_indirect): Use get_addr_base_and_unit_offset_1
1551 with vn_valueize as valueization callback.
1552 (vn_reference_maybe_forwprop_address): Likewise.
1553 * tree-dfa.c (get_addr_base_and_unit_offset_1): Also valueize
1554 array_ref_low_bound.
1556 2020-05-08 Jakub Jelinek <jakub@redhat.com>
1558 PR tree-optimization/94786
1559 * match.pd (A ^ ((A ^ B) & -(C cmp D)) -> (C cmp D) ? B : A): New
1563 * config/i386/i386.md (peephole2 after *add<mode>3_cc_overflow_1): New
1567 * tree.c (get_narrower): Reuse the op temporary instead of
1570 PR tree-optimization/94783
1571 * match.pd ((X + (X >> (prec - 1))) ^ (X >> (prec - 1)) to abs (X)):
1574 PR tree-optimization/94956
1575 * match.pd (FFS): Optimize __builtin_ffs* of non-zero argument into
1576 __builtin_ctz* + 1 if direct IFN_CTZ is supported.
1578 PR tree-optimization/94913
1579 * match.pd (A - B + -1 >= A to B >= A): New simplification.
1580 (A - B > A to A < B): Don't test TYPE_OVERFLOW_WRAPS which is always
1581 true for TYPE_UNSIGNED integral types.
1584 PR rtl-optimization/94516
1585 * rtl.h (remove_reg_equal_equiv_notes): Add a bool argument defaulted
1587 * rtlanal.c (remove_reg_equal_equiv_notes): Add no_rescan argument.
1588 Call df_notes_rescan if that argument is not true and returning true.
1589 * combine.c (adjust_for_new_dest): Pass true as second argument to
1590 remove_reg_equal_equiv_notes.
1591 * postreload.c (reload_combine_recognize_pattern): Don't call
1594 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1596 * config/rs6000/rs6000.md (*setnbc_<un>signed_<GPR:mode>): New
1598 (*setnbcr_<un>signed_<GPR:mode>): New define_insn.
1599 (*neg_eq_<mode>): Avoid for TARGET_FUTURE; add missing && 1.
1600 (*neg_ne_<mode>): Likewise.
1602 2020-05-07 Segher Boessenkool <segher@kernel.crashing.org>
1604 * config/rs6000/rs6000.md (setbc_<un>signed_<GPR:mode>): New
1606 (*setbcr_<un>signed_<GPR:mode>): Likewise.
1607 (cstore<mode>4): Use setbc[r] if available.
1608 (<code><GPR:mode><GPR2:mode>2_isel): Avoid for TARGET_FUTURE.
1609 (eq<mode>3): Use setbc for TARGET_FUTURE.
1610 (*eq<mode>3): Avoid for TARGET_FUTURE.
1611 (ne<mode>3): Replace :P with :GPR; use setbc for TARGET_FUTURE;
1612 else for non-Pmode, use gen_eq and gen_xor.
1613 (*ne<mode>3): Avoid for TARGET_FUTURE.
1614 (*eqsi3_ext<mode>): Avoid for TARGET_FUTURE; fix missing && 1.
1616 2020-05-07 Jeff Law <law@redhat.com>
1618 * config/h8300/h8300.md: Move expanders and patterns into
1619 files based on functionality.
1620 * config/h8300/addsub.md: New file.
1621 * config/h8300/bitfield.md: New file
1622 * config/h8300/combiner.md: New file
1623 * config/h8300/divmod.md: New file
1624 * config/h8300/extensions.md: New file
1625 * config/h8300/jumpcall.md: New file
1626 * config/h8300/logical.md: New file
1627 * config/h8300/movepush.md: New file
1628 * config/h8300/multiply.md: New file
1629 * config/h8300/other.md: New file
1630 * config/h8300/proepi.md: New file
1631 * config/h8300/shiftrotate.md: New file
1632 * config/h8300/testcompare.md: New file
1634 * config/h8300/h8300.md (adds/subs splitters): Merge into single
1636 (negation expanders and patterns): Simplify and combine using
1638 (one_cmpl expanders and patterns): Likewise.
1639 (tablejump, indirect_jump patterns ): Likewise.
1640 (shift and rotate expanders and patterns): Likewise.
1641 (absolute value expander and pattern): Drop expander, rename pattern
1643 (peephole2 patterns): Move into...
1644 * config/h8300/peepholes.md: New file.
1646 * config/h8300/constraints.md (L and N): Simplify now that we're not
1647 longer supporting the original H8/300 chip.
1648 * config/h8300/elf.h (LINK_SPEC): Likewise. Default to H8/300H.
1649 * config/h8300/h8300.c (shift_alg_qi): Drop H8/300 support.
1650 (shift_alg_hi, shift_alg_si): Similarly.
1651 (h8300_option_overrides): Similarly. Default to H8/300H. If
1652 compiling for H8/S, then turn off H8/300H. Do not update the
1653 shift_alg tables for H8/300 port.
1654 (h8300_emit_stack_adjustment): Remove support for H8/300. Simplify
1656 (push, split_adds_subs, h8300_rtx_costs): Likewise.
1657 (h8300_print_operand, compute_mov_length): Likewise.
1658 (output_plussi, compute_plussi_length): Likewise.
1659 (compute_plussi_cc, output_logical_op): Likewise.
1660 (compute_logical_op_length, compute_logical_op_cc): Likewise.
1661 (get_shift_alg, h8300_shift_needs_scratch): Likewise.
1662 (output_a_shift, compute_a_shift_length): Likewise.
1663 (output_a_rotate, compute_a_rotate_length): Likewise.
1664 (output_simode_bld, h8300_hard_regno_mode_ok): Likewise.
1665 (h8300_modes_tieable_p, h8300_return_in_memory): Likewise.
1666 * config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Likewise.
1667 (attr_cpu, TARGET_H8300): Remove.
1668 (TARGET_DEFAULT): Update.
1669 (UNITS_PER_WORD, PARM_BOUNDARY): Simplify where possible.
1670 (BIGGEST_ALIGNMENT, STACK_BOUNDARY): Likewise.
1671 (CONSTANT_ADDRESS_P, MOVE_MAX, Pmode): Likewise.
1672 (SIZE_TYPE, POINTER_SIZE, ASM_WORD_OP): Likewise.
1673 * config/h8300/h8300.md: Simplify patterns throughout.
1674 * config/h8300/t-h8300: Update multilib configuration.
1676 * config/h8300/h8300.h (LINK_SPEC): Remove.
1677 (USER_LABEL_PREFIX): Likewise.
1679 * config/h8300/h8300.c (h8300_asm_named_section): Remove.
1680 (h8300_option_override): Remove remnants of COFF support.
1682 2020-05-07 Alan Modra <amodra@gmail.com>
1684 * tree-ssa-reassoc.c (optimize_range_tests_to_bit_test): Replace
1685 set_rtx_cost with set_src_cost.
1686 * tree-switch-conversion.c (bit_test_cluster::emit): Likewise.
1688 2020-05-07 Kewen Lin <linkw@gcc.gnu.org>
1690 * tree-vect-stmts.c (vectorizable_load): Check alignment to avoid
1691 redundant half vector handlings for no peeling gaps.
1693 2020-05-07 Giuliano Belinassi <giuliano.belinassi@usp.br>
1695 * tree-ssa-operands.c (operands_scanner): New class.
1696 (operands_bitmap_obstack): Remove.
1697 (n_initialized): Remove.
1698 (build_uses): Move to operands_scanner class.
1699 (build_vuse): Same as above.
1700 (build_vdef): Same as above.
1701 (verify_ssa_operands): Same as above.
1702 (finalize_ssa_uses): Same as above.
1703 (cleanup_build_arrays): Same as above.
1704 (finalize_ssa_stmt_operands): Same as above.
1705 (start_ssa_stmt_operands): Same as above.
1706 (append_use): Same as above.
1707 (append_vdef): Same as above.
1708 (add_virtual_operand): Same as above.
1709 (add_stmt_operand): Same as above.
1710 (get_mem_ref_operands): Same as above.
1711 (get_tmr_operands): Same as above.
1712 (maybe_add_call_vops): Same as above.
1713 (get_asm_stmt_operands): Same as above.
1714 (get_expr_operands): Same as above.
1715 (parse_ssa_operands): Same as above.
1716 (finalize_ssa_defs): Same as above.
1717 (build_ssa_operands): Same as above, plus create a C-like wrapper.
1718 (update_stmt_operands): Create an instance of operands_scanner.
1720 2020-05-07 Richard Biener <rguenther@suse.de>
1723 * tree-ssa-structalias.c (refered_from_nonlocal_fn): Use
1724 DECL_EXTERNAL || TREE_PUBLIC instead of externally_visible.
1725 (refered_from_nonlocal_var): Likewise.
1726 (ipa_pta_execute): Likewise.
1728 2020-05-07 Erick Ochoa <erick.ochoa@theobroma-systems.com>
1730 * gcc/tree-ssa-struct-alias.c: Fix comments
1732 2020-05-07 Martin Liska <mliska@suse.cz>
1734 * doc/invoke.texi: Fix 2 optindex entries.
1736 2020-05-07 Richard Biener <rguenther@suse.de>
1739 * tree-core.h (tree_decl_common::gimple_reg_flag): Rename ...
1740 (tree_decl_common::not_gimple_reg_flag): ... to this.
1741 * tree.h (DECL_GIMPLE_REG_P): Rename ...
1742 (DECL_NOT_GIMPLE_REG_P): ... to this.
1743 * gimple-expr.c (copy_var_decl): Copy DECL_NOT_GIMPLE_REG_P.
1744 (create_tmp_reg): Simplify.
1745 (create_tmp_reg_fn): Likewise.
1746 (is_gimple_reg): Check DECL_NOT_GIMPLE_REG_P for all regs.
1747 * gimplify.c (create_tmp_from_val): Simplify.
1748 (gimplify_bind_expr): Likewise.
1749 (gimplify_compound_literal_expr): Likewise.
1750 (gimplify_function_tree): Likewise.
1751 (prepare_gimple_addressable): Set DECL_NOT_GIMPLE_REG_P.
1752 * asan.c (create_odr_indicator): Do not clear DECL_GIMPLE_REG_P.
1753 (asan_add_global): Copy it.
1754 * cgraphunit.c (cgraph_node::expand_thunk): Force args
1756 * function.c (gimplify_parameters): Copy
1757 DECL_NOT_GIMPLE_REG_P.
1758 * ipa-param-manipulation.c
1759 (ipa_param_body_adjustments::common_initialization): Simplify.
1760 (ipa_param_body_adjustments::reset_debug_stmts): Copy
1761 DECL_NOT_GIMPLE_REG_P.
1762 * omp-low.c (lower_omp_for_scan): Do not set DECL_GIMPLE_REG_P.
1763 * sanopt.c (sanitize_rewrite_addressable_params): Likewise.
1764 * tree-cfg.c (make_blocks_1): Simplify.
1765 (verify_address): Do not verify DECL_GIMPLE_REG_P setting.
1766 * tree-eh.c (lower_eh_constructs_2): Simplify.
1767 * tree-inline.c (declare_return_variable): Adjust and
1769 (copy_decl_to_var): Copy DECL_NOT_GIMPLE_REG_P.
1770 (copy_result_decl_to_var): Likewise.
1771 * tree-into-ssa.c (pass_build_ssa::execute): Adjust comment.
1772 * tree-nested.c (create_tmp_var_for): Simplify.
1773 * tree-parloops.c (separate_decls_in_region_name): Copy
1774 DECL_NOT_GIMPLE_REG_P.
1775 * tree-sra.c (create_access_replacement): Adjust and
1776 generalize partial def support.
1777 * tree-ssa-forwprop.c (pass_forwprop::execute): Set
1778 DECL_NOT_GIMPLE_REG_P on decls we introduce partial defs on.
1779 * tree-ssa.c (maybe_optimize_var): Handle clearing of
1780 TREE_ADDRESSABLE and setting/clearing DECL_NOT_GIMPLE_REG_P
1782 * lto-streamer-out.c (hash_tree): Hash DECL_NOT_GIMPLE_REG_P.
1783 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Stream
1784 DECL_NOT_GIMPLE_REG_P.
1785 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
1786 * cfgexpand.c (avoid_type_punning_on_regs): New.
1787 (discover_nonconstant_array_refs): Call
1788 avoid_type_punning_on_regs to avoid unsupported mode punning.
1790 2020-05-07 Alex Coplan <alex.coplan@arm.com>
1792 * config/arm/arm.c (arm_add_stmt_cost): Fix declaration, remove class
1795 2020-05-07 Richard Biener <rguenther@suse.de>
1797 PR tree-optimization/57359
1798 * tree-ssa-loop-im.c (im_mem_ref::indep_loop): Remove.
1799 (in_mem_ref::dep_loop): Repurpose.
1800 (LOOP_DEP_BIT): Remove.
1801 (enum dep_kind): New.
1802 (enum dep_state): Likewise.
1803 (record_loop_dependence): New function to populate the
1805 (query_loop_dependence): New function to query the dependence
1807 (memory_accesses::refs_in_loop): Rename to ...
1808 (memory_accesses::refs_loaded_in_loop): ... this and change to
1810 (outermost_indep_loop): Adjust.
1811 (mem_ref_alloc): Likewise.
1812 (gather_mem_refs_stmt): Likewise.
1813 (mem_refs_may_alias_p): Add tbaa_p parameter and pass it down.
1814 (struct sm_aux): New.
1815 (execute_sm): Split code generation on exits, record state
1817 (enum sm_kind): New.
1818 (execute_sm_exit): Exit code generation part.
1819 (sm_seq_push_down): Helper for sm_seq_valid_bb performing
1820 dependence checking on stores reached from exits.
1821 (sm_seq_valid_bb): New function gathering SM stores on exits.
1822 (hoist_memory_references): Re-implement.
1823 (refs_independent_p): Add tbaa_p parameter and pass it down.
1824 (record_dep_loop): Remove.
1825 (ref_indep_loop_p_1): Fold into ...
1826 (ref_indep_loop_p): ... this and generalize for three kinds
1827 of dependence queries.
1828 (can_sm_ref_p): Adjust according to hoist_memory_references
1830 (store_motion_loop): Don't do anything if the set of SM
1831 candidates is empty.
1832 (tree_ssa_lim_initialize): Adjust.
1833 (tree_ssa_lim_finalize): Likewise.
1835 2020-05-07 Eric Botcazou <ebotcazou@adacore.com>
1836 Pierre-Marie de Rodat <derodat@adacore.com>
1838 * dwarf2out.c (add_data_member_location_attribute): Take into account
1839 the variant part offset in the computation of the data bit offset.
1840 (add_bit_offset_attribute): Remove CTX parameter. Pass a new context
1841 in the call to field_byte_offset.
1842 (gen_field_die): Adjust call to add_bit_offset_attribute and remove
1843 confusing assertion.
1844 (analyze_variant_discr): Deal with boolean subtypes.
1846 2020-05-07 Martin Liska <mliska@suse.cz>
1848 * lto-wrapper.c: Split arguments of MAKE environment
1851 2020-05-07 Uroš Bizjak <ubizjak@gmail.com>
1853 * config/alpha/alpha.c (alpha_atomic_assign_expand_fenv): Use
1854 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
1855 fenv_var and new_fenv_var.
1857 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1860 * config/i386/subst.md (store_mask_constraint, store_mask_predicate):
1862 (avx512dq_vextract<shuffletype>64x2_1_maskm,
1863 avx512f_vextract<shuffletype>32x4_1_maskm,
1864 vec_extract_lo_<mode>_maskm, vec_extract_hi_<mode>_maskm): Remove.
1865 (<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>): Split
1867 (*avx512dq_vextract<shuffletype>64x2_1,
1868 avx512dq_vextract<shuffletype>64x2_1_mask): ... these new
1869 define_insns. Even in the masked variant allow memory output but in
1870 that case use 0 rather than 0C constraint on the source of masked-out
1872 (<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>): Split
1874 (*avx512f_vextract<shuffletype>32x4_1,
1875 avx512f_vextract<shuffletype>32x4_1_mask): ... these new define_insns.
1876 Even in the masked variant allow memory output but in that case use
1877 0 rather than 0C constraint on the source of masked-out elts.
1878 (vec_extract_lo_<mode><mask_name>): Split into ...
1879 (vec_extract_lo_<mode>, vec_extract_lo_<mode>_mask): ... these new
1880 define_insns. Even in the masked variant allow memory output but in
1881 that case use 0 rather than 0C constraint on the source of masked-out
1883 (vec_extract_hi_<mode><mask_name>): Split into ...
1884 (vec_extract_hi_<mode>, vec_extract_hi_<mode>_mask): ... these new
1885 define_insns. Even in the masked variant allow memory output but in
1886 that case use 0 rather than 0C constraint on the source of masked-out
1889 2020-05-06 qing zhao <qing.zhao@oracle.com>
1892 * common.opt: Add -flarge-source-files.
1893 * doc/invoke.texi: Document it.
1894 * toplev.c (process_options): set line_table->default_range_bits
1895 to 0 when flag_large_source_files is true.
1897 2020-05-06 Uroš Bizjak <ubizjak@gmail.com>
1900 * config/i386/predicates.md (add_comparison_operator): New predicate.
1901 * config/i386/i386.md (compare->add splitter): New splitters.
1903 2020-05-06 Richard Biener <rguenther@suse.de>
1905 * tree-vectorizer.h (vect_transform_slp_perm_load): Adjust.
1906 * tree-vect-data-refs.c (vect_slp_analyze_node_dependences):
1907 Remove slp_instance parameter, just iterate over all scalar stmts.
1908 (vect_slp_analyze_instance_dependence): Adjust and likewise.
1909 * tree-vect-slp.c (vect_bb_slp_scalar_cost): Remove unused BB
1911 (vect_schedule_slp): Just iterate over all scalar stmts.
1912 (vect_supported_load_permutation_p): Adjust.
1913 (vect_transform_slp_perm_load): Remove slp_instance parameter,
1914 instead use the number of lanes in the node as group size.
1915 * tree-vect-stmts.c (vect_model_load_cost): Get vectorization
1916 factor instead of slp_instance as parameter.
1917 (vectorizable_load): Adjust.
1919 2020-05-06 Andreas Schwab <schwab@suse.de>
1921 * config/aarch64/driver-aarch64.c: Include "aarch64-protos.h".
1922 (aarch64_get_extension_string_for_isa_flags): Don't declare.
1924 2020-05-06 Richard Biener <rguenther@suse.de>
1927 * cfgloopmanip.c (create_preheader): Require non-complex
1928 preheader edge for CP_SIMPLE_PREHEADERS.
1930 2020-05-06 Richard Biener <rguenther@suse.de>
1932 PR tree-optimization/94963
1933 * tree-ssa-loop-im.c (execute_sm_if_changed): Remove
1934 no-warning marking of the conditional store.
1935 (execute_sm): Instead mark the uninitialized state
1936 on loop entry to be not warned about.
1938 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
1940 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_TSXLDTRK_SET,
1941 OPTION_MASK_ISA2_TSXLDTRK_UNSET): New macros.
1942 * config.gcc: Add tsxldtrkintrin.h to extra_headers.
1943 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
1945 * config/i386/i386-builtin.def: Add new builtins.
1946 * config/i386/i386-c.c (ix86_target_macros_internal): Define
1948 * config/i386/i386-options.c (ix86_target_string): Add
1950 (ix86_valid_target_attribute_inner_p): Add attribute tsxldtrk.
1951 * config/i386/i386.h (TARGET_TSXLDTRK, TARGET_TSXLDTRK_P):
1953 * config/i386/i386.md (define_c_enum "unspec"): Add
1954 UNSPECV_SUSLDTRK, UNSPECV_RESLDTRK.
1955 (TSXLDTRK): New define_int_iterator.
1956 ("<tsxldtrk>"): New define_insn.
1957 * config/i386/i386.opt: Add -mtsxldtrk.
1958 * config/i386/immintrin.h: Include tsxldtrkintrin.h.
1959 * config/i386/tsxldtrkintrin.h: New.
1960 * doc/invoke.texi: Document -mtsxldtrk.
1962 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1964 PR tree-optimization/94921
1965 * match.pd (~(~X - Y) -> X + Y, ~(~X + Y) -> X - Y): New
1968 2020-05-06 Richard Biener <rguenther@suse.de>
1970 PR tree-optimization/94965
1971 * tree-vect-stmts.c (vectorizable_load): Fix typo.
1973 2020-05-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1975 * doc/install.texi: Replace Sun with Solaris as appropriate.
1976 (Tools/packages necessary for building GCC, Perl version between
1977 5.6.1 and 5.6.24): Remove Solaris 8 reference.
1978 (Installing GCC: Binaries, Solaris 2 (SPARC, Intel)): Remove
1980 (Specific, i?86-*-solaris2*): Update version references for
1981 Solaris 11.3 and later. Remove gas 2.26 caveat.
1982 (Specific, *-*-solaris2*): Update version references for
1983 Solaris 11.3 and later. Remove boehm-gc reference.
1984 Document GMP, MPFR caveats on Solaris 11.3.
1985 (Specific, sparc-sun-solaris2*): Update Solaris 9 references.
1986 (Specific, sparc64-*-solaris2*): Likewise.
1987 Document --build requirement.
1989 2020-05-06 Jakub Jelinek <jakub@redhat.com>
1992 * config/riscv/riscv-builtins.c (riscv_atomic_assign_expand_fenv): Use
1993 TARGET_EXPR instead of MODIFY_EXPR for first assignment to old_flags.
1995 PR rtl-optimization/94873
1996 * combine.c (combine_instructions): Don't optimize using REG_EQUAL
1997 note if SET_SRC (set) has side-effects.
1999 2020-05-06 Hongtao Liu <hongtao.liu@intel.com>
2000 Wei Xiao <wei3.xiao@intel.com>
2002 * common/config/i386/i386-common.c (OPTION_MASK_ISA2_SERIALIZE_SET,
2003 OPTION_MASK_ISA2_SERIALIZE_UNSET): New macros.
2004 (ix86_handle_option): Handle -mserialize.
2005 * config.gcc (serializeintrin.h): New header file.
2006 * config/i386/cpuid.h (bit_SERIALIZE): New bit.
2007 * config/i386/driver-i386.c (host_detect_local_cpu): Detect
2009 * config/i386/i386-builtin.def: Add new builtin.
2010 * config/i386/i386-c.c (__SERIALIZE__): New macro.
2011 * config/i386/i386-options.c (ix86_target_opts_isa2_opts):
2013 * (ix86_valid_target_attribute_inner_p): Add target attribute
2015 * config/i386/i386.h (TARGET_SERIALIZE, TARGET_SERIALIZE_P):
2017 * config/i386/i386.md (UNSPECV_SERIALIZE): New unspec.
2018 (serialize): New define_insn.
2019 * config/i386/i386.opt (mserialize): New option
2020 * config/i386/immintrin.h: Include serailizeintrin.h.
2021 * config/i386/serializeintrin.h: New header file.
2022 * doc/invoke.texi: Add documents for -mserialize.
2024 2020-05-06 Richard Biener <rguenther@suse.de>
2026 * tree-cfg.c (verify_gimple_assign_unary): Adjust integer
2027 to/from pointer conversion checking.
2029 2020-05-05 Michael Meissner <meissner@linux.ibm.com>
2031 * config/rs6000/rs6000-builtin.def: Delete changes meant for a
2033 * config/rs6000/rs6000-c.c: Likewise.
2034 * config/rs6000/rs6000-call.c: Likewise.
2035 * config/rs6000/rs6000.c: Likewise.
2037 2020-05-05 Sebastian Huber <sebastian.huber@embedded-brains.de>
2039 * config/rtems.h (RTEMS_STARTFILE_SPEC): Define if undefined.
2040 (RTEMS_ENDFILE_SPEC): Likewise.
2041 (STARTFILE_SPEC): Update comment. Add RTEMS_STARTFILE_SPEC.
2042 (ENDFILE_SPEC): Add RTEMS_ENDFILE_SPEC.
2043 (LIB_SPECS): Support -nodefaultlibs option.
2044 * config/or1k/rtems.h (RTEMS_STARTFILE_SPEC): Define.
2045 (RTEMS_ENDFILE_SPEC): Likewise.
2046 * config/rs6000/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
2047 (RTEMS_ENDFILE_SPEC): Likewise.
2048 * config/v850/rtems.h (RTEMS_STARTFILE_SPEC): Likewise.
2049 (RTEMS_ENDFILE_SPEC): Likewise.
2051 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
2053 * config/pru/pru.c (pru_hard_regno_call_part_clobbered): Remove.
2054 (TARGET_HARD_REGNO_CALL_PART_CLOBBERED): Remove.
2056 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
2058 * config/pru/pru.h: Mark R3.w0 as caller saved.
2060 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
2062 * config/pru/pru.c (pru_emit_doloop): Use new gen_doloop_end_internal
2063 and gen_doloop_begin_internal.
2064 (pru_reorg_loop): Use gen_pruloop with mode.
2065 * config/pru/pru.md: Use new @insn syntax.
2067 2020-05-05 Dimitar Dimitrov <dimitar@dinux.eu>
2069 * config/pru/pru.c (pru_print_operand): Fix fall through comment.
2071 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
2073 * config/i386/i386.md (fixuns_trunc<mode>si2): Use
2074 "clobber (scratch:M)" instad of "clobber (match_scratch:M N)".
2075 (addqi3_cconly_overflow): Ditto.
2076 (umulv<mode>4): Ditto.
2077 (<s>mul<mode>3_highpart): Ditto.
2078 (tls_global_dynamic_32): Ditto.
2079 (tls_local_dynamic_base_32): Ditto.
2086 (*adddi_4): Remove "m" constraint from scratch operand.
2087 (*add<mode>_4): Ditto.
2089 2020-05-05 Jakub Jelinek <jakub@redhat.com>
2091 PR rtl-optimization/94516
2092 * postreload.c (reload_cse_simplify): When replacing sp = sp + const
2093 with sp = reg, add REG_EQUAL note with sp + const.
2094 * combine-stack-adj.c (try_apply_stack_adjustment): Change return
2095 type from int to bool. Add LIVE and OTHER_INSN arguments. Undo
2096 postreload sp = sp + const to sp = reg optimization if needed and
2098 (combine_stack_adjustments_for_block): Add LIVE argument. Handle
2099 reg = sp insn with sp + const REG_EQUAL note. Adjust
2100 try_apply_stack_adjustment caller, call
2101 df_simulate_initialize_forwards and df_simulate_one_insn_forwards.
2102 (combine_stack_adjustments): Allocate and free LIVE bitmap,
2103 adjust combine_stack_adjustments_for_block caller.
2105 2020-05-05 Martin Liska <mliska@suse.cz>
2107 PR gcov-profile/93623
2108 * tree-cfg.c (stmt_can_terminate_bb_p): Update comment to reflect
2111 2020-05-05 Martin Liska <mliska@suse.cz>
2113 * opt-functions.awk (opt_args_non_empty): New function.
2114 * opt-read.awk: Use the function for various option arguments.
2116 2020-05-05 Martin Liska <mliska@suse.cz>
2119 * lto-wrapper.c (run_gcc): When using -flto=jobserver,
2120 report warning when the jobserver is not detected.
2122 2020-05-05 Martin Liska <mliska@suse.cz>
2124 PR gcov-profile/94636
2125 * gcov.c (main): Print total lines summary at the end.
2126 (generate_results): Expect file_name always being non-null.
2127 Print newline after intermediate file is printed in order to align with
2128 what we do for normal files.
2130 2020-05-05 Martin Liska <mliska@suse.cz>
2132 * dumpfile.c (dump_switch_p): Change return type
2133 and print option suggestion.
2134 * dumpfile.h: Change return type.
2135 * opts-global.c (handle_common_deferred_options):
2136 Move error into dump_switch_p function.
2138 2020-05-05 Martin Liska <mliska@suse.cz>
2141 * alloc-pool.h: Use const for some arguments.
2142 * bitmap.h: Likewise.
2143 * mem-stats.h: Likewise.
2144 * sese.h (get_entry_bb): Likewise.
2145 (get_exit_bb): Likewise.
2147 2020-05-05 Richard Biener <rguenther@suse.de>
2149 * tree-vect-slp.c (struct vdhs_data): New.
2150 (vect_detect_hybrid_slp): New walker.
2151 (vect_detect_hybrid_slp): Rewrite.
2153 2020-05-05 Richard Biener <rguenther@suse.de>
2156 * tree-ssa-structalias.c (ipa_pta_execute): Use
2157 varpool_node::externally_visible_p ().
2158 (refered_from_nonlocal_var): Likewise.
2160 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
2162 * gcc.c (LTO_PLUGIN_SPEC): Define if not already.
2163 (LINK_PLUGIN_SPEC): Execute LTO_PLUGIN_SPEC.
2164 * config/vxworks.h (LTO_PLUGIN_SPEC): Define.
2166 2020-05-05 Eric Botcazou <ebotcazou@adacore.com>
2168 * gimplify.c (gimplify_init_constructor): Do not put the constructor
2169 into static memory if it is not complete.
2171 2020-05-05 Richard Biener <rguenther@suse.de>
2173 PR tree-optimization/94949
2174 * tree-ssa-loop-im.c (execute_sm): Check whether we use
2175 the multithreaded model or always compute the stored value
2176 before eliding a load.
2178 2020-05-05 Alex Coplan <alex.coplan@arm.com>
2180 * config/aarch64/aarch64.md (*one_cmpl_zero_extend): New.
2182 2020-05-05 Jakub Jelinek <jakub@redhat.com>
2184 PR tree-optimization/94800
2185 * match.pd (X + (X << C) to X * (1 + (1 << C)),
2186 (X << C1) + (X << C2) to X * ((1 << C1) + (1 << C2))): New
2190 * config/i386/mmx.md (*vec_dupv4hi): Use xYw constraints instead of Yv.
2192 PR tree-optimization/94914
2193 * match.pd ((((type)A * B) >> prec) != 0 to .MUL_OVERFLOW(A, B) != 0):
2196 2020-05-05 Uroš Bizjak <ubizjak@gmail.com>
2198 * config/i386/i386.md (*testqi_ext_3): Use
2199 int_nonimmediate_operand instead of manual mode checks.
2200 (*x86_mov<SWI48:mode>cc_0_m1_neg_leu<SWI:mode>):
2201 Use int_nonimmediate_operand predicate. Rewrite
2202 define_insn_and_split pattern to a combine pass splitter.
2204 2020-05-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2206 * configure.ac <i[34567]86-*-*>: Add --32 to tls_as_opt on Solaris.
2207 * configure: Regenerate.
2209 2020-05-05 Jakub Jelinek <jakub@redhat.com>
2212 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
2213 ssse3_ph<plusminus_mnemonic>wv8hi3, ssse3_ph<plusminus_mnemonic>wv4hi3,
2214 avx2_ph<plusminus_mnemonic>dv8si3, ssse3_ph<plusminus_mnemonic>dv4si3,
2215 ssse3_ph<plusminus_mnemonic>dv2si3): Simplify RTL patterns.
2217 2020-05-04 Clement Chigot <clement.chigot@atos.net>
2218 David Edelsohn <dje.gcc@gmail.com>
2220 * config/rs6000/rs6000-call.c (rs6000_init_builtins): Override explicit
2221 for fmodl, frexpl, ldexpl and modfl builtins.
2223 2020-05-04 Richard Sandiford <richard.sandiford@arm.com>
2226 * internal-fn.c (expand_load_lanes_optab_fn): Emit a move if the
2227 chosen lhs is different from the gcall lhs.
2228 (expand_mask_load_optab_fn): Likewise.
2229 (expand_gather_load_optab_fn): Likewise.
2231 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
2234 * config/i386/i386.md (*neg<mode>_ccc): New insn pattern.
2235 (EQ compare->LTU compare splitter): New splitter.
2236 (NE compare->NEG splitter): Ditto.
2238 2020-05-04 Marek Polacek <polacek@redhat.com>
2241 2020-04-30 Marek Polacek <polacek@redhat.com>
2244 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
2245 (check_aligned_type): Check if TYPE_USER_ALIGN match.
2247 2020-05-04 Richard Biener <rguenther@suse.de>
2249 PR tree-optimization/93891
2250 * tree-ssa-sccvn.c (vn_reference_lookup_3): Fall back to
2251 the original reference tree for assessing access alignment.
2253 2020-05-04 Richard Biener <rguenther@suse.de>
2255 PR tree-optimization/39612
2256 * tree-ssa-loop-im.c (im_mem_ref::loaded): New member.
2257 (set_ref_loaded_in_loop): New.
2258 (mark_ref_loaded): Likewise.
2259 (gather_mem_refs_stmt): Call mark_ref_loaded for loads.
2260 (execute_sm): Avoid issueing a load when it was not there.
2261 (execute_sm_if_changed): Avoid issueing warnings for the
2264 2020-05-04 Martin Jambor <mjambor@suse.cz>
2267 * tree-inline.c (tree_function_versioning): Leave any type conversion
2268 of replacements to setup_one_parameter and its friend
2269 force_value_to_type.
2271 2020-05-04 Uroš Bizjak <ubizjak@gmail.com>
2274 * config/i386/predicates.md (shr_comparison_operator): New predicate.
2275 * config/i386/i386.md (compare->shr splitter): New splitters.
2277 2020-05-04 Jakub Jelinek <jakub@redhat.com>
2279 PR tree-optimization/94718
2280 * match.pd ((X < 0) != (Y < 0) into (X ^ Y) < 0): New simplification.
2282 PR tree-optimization/94718
2283 * match.pd (bitop (convert @0) (convert? @1)): For GIMPLE, if we can,
2284 replace two nop conversions on bit_{and,ior,xor} argument
2285 and result with just one conversion on the result or another argument.
2287 PR tree-optimization/94718
2288 * fold-const.c (fold_binary_loc): Move (X & C) eqne (Y & C)
2289 -> (X ^ Y) & C eqne 0 optimization to ...
2290 * match.pd ((X & C) op (Y & C) into (X ^ Y) & C op 0): ... here.
2292 * opts.c (get_option_html_page): Instead of hardcoding a list of
2293 options common between C/C++ and Fortran only use gfortran/
2294 documentation for warnings that have CL_Fortran set but not
2297 2020-05-03 Uroš Bizjak <ubizjak@gmail.com>
2299 * config/i386/i386-expand.c (ix86_expand_int_movcc):
2300 Use plus_constant instead of gen_rtx_PLUS with GEN_INT.
2301 (emit_memmov): Ditto.
2302 (emit_memset): Ditto.
2303 (ix86_expand_strlensi_unroll_1): Ditto.
2304 (release_scratch_register_on_entry): Ditto.
2305 (gen_frame_set): Ditto.
2306 (ix86_emit_restore_reg_using_pop): Ditto.
2307 (ix86_emit_outlined_ms2sysv_restore): Ditto.
2308 (ix86_expand_epilogue): Ditto.
2309 (ix86_expand_split_stack_prologue): Ditto.
2310 * config/i386/i386.md (push immediate splitter): Ditto.
2314 2020-05-02 Iain Sandoe <iain@sandoe.co.uk>
2316 PR translation/93861
2317 * config/darwin-driver.c (darwin_driver_init): Adjust spelling in
2320 2020-05-02 Jakub Jelinek <jakub@redhat.com>
2322 * config/tilegx/tilegx.md
2323 (insn_stnt<I124MODE:n>_add<I48MODE:bitsuffix>): Use <I124MODE:n>
2324 rather than just <n>.
2326 2020-05-01 H.J. Lu <hongjiu.lu@intel.com>
2329 * cfgexpand.c (pass_expand::execute): Set crtl->patch_area_size
2330 and crtl->patch_area_entry.
2331 * emit-rtl.h (rtl_data): Add patch_area_size and patch_area_entry.
2332 * opts.c (common_handle_option): Limit
2333 function_entry_patch_area_size and function_entry_patch_area_start
2334 to USHRT_MAX. Fix a typo in error message.
2335 * varasm.c (assemble_start_function): Use crtl->patch_area_size
2336 and crtl->patch_area_entry.
2337 * doc/invoke.texi: Document the maximum value for
2338 -fpatchable-function-entry.
2340 2020-05-01 Iain Sandoe <iain@sandoe.co.uk>
2342 * config/i386/darwin.h: Repair SUBTARGET_INIT_BUILTINS.
2343 Override SUBTARGET_SHADOW_OFFSET macro.
2345 2020-05-01 Andreas Tobler <andreast@gcc.gnu.org>
2347 * config/i386/i386.h: Define a new macro: SUBTARGET_SHADOW_OFFSET.
2348 * config/i386/i386.c (ix86_asan_shadow_offset): Use this macro.
2349 * config/i386/darwin.h: Override the SUBTARGET_SHADOW_OFFSET macro.
2350 * config/i386/freebsd.h: Likewise.
2351 * config/freebsd.h (LIBASAN_EARLY_SPEC): Define.
2352 LIBTSAN_EARLY_SPEC): Likewise. (LIBLSAN_EARLY_SPEC): Likewise.
2354 2020-04-30 Alexandre Oliva <oliva@adacore.com>
2356 * doc/sourcebuild.texi (Effective-Target Keywords): Document
2357 the newly-introduced fileio effective target.
2359 2020-04-30 Richard Sandiford <richard.sandiford@arm.com>
2361 PR rtl-optimization/94740
2362 * cse.c (cse_process_notes_1): Replace with...
2363 (cse_process_note_1): ...this new function, acting as a
2364 simplify_replace_fn_rtx callback to process_note. Handle only
2365 REGs and MEMs directly. Validate the MEM if cse_process_note
2366 changes its address.
2367 (cse_process_notes): Replace with...
2368 (cse_process_note): ...this new function.
2369 (cse_extended_basic_block): Update accordingly, iterating over
2370 the register notes and passing individual notes to cse_process_note.
2372 2020-04-30 Carl Love <cel@us.ibm.com>
2374 * config/rs6000/emmintrin.h (_mm_movemask_epi8): Fix comment.
2376 2020-04-30 Martin Jambor <mjambor@suse.cz>
2379 * cgraph.c (clone_of_p): Also consider thunks whih had their bodies
2380 saved by the inliner and thunks which had their call inlined.
2381 * ipa-inline-transform.c (save_inline_function_body): Fill in
2382 former_clone_of of new body holders.
2384 2020-04-30 Jakub Jelinek <jakub@redhat.com>
2386 * BASE-VER: Set to 11.0.0.
2388 2020-04-30 Jonathan Wakely <jwakely@redhat.com>
2390 * pretty-print.c (pp_take_prefix): Fix spelling in comment.
2392 2020-04-30 Marek Polacek <polacek@redhat.com>
2395 * tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
2396 (check_aligned_type): Check if TYPE_USER_ALIGN match.
2398 2020-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2400 * config/aarch64/aarch64.h (TARGET_OUTLINE_ATOMICS): Define.
2401 * config/aarch64/aarch64.opt (moutline-atomics): Change to Int variable.
2402 * doc/invoke.texi (moutline-atomics): Document as on by default.
2404 2020-04-30 Szabolcs Nagy <szabolcs.nagy@arm.com>
2407 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Remove
2408 the check for NOTE_INSN_DELETED_LABEL.
2410 2020-04-30 Jakub Jelinek <jakub@redhat.com>
2412 * configure.ac (--with-documentation-root-url,
2413 --with-changes-root-url): Diagnose URL not ending with /,
2414 use AC_DEFINE_UNQUOTED instead of AC_SUBST.
2415 * opts.h (get_changes_url): Remove.
2416 * opts.c (get_changes_url): Remove.
2417 * Makefile.in (CFLAGS-opts.o): Don't add -DDOCUMENTATION_ROOT_URL
2418 or -DCHANGES_ROOT_URL.
2419 * doc/install.texi (--with-documentation-root-url,
2420 --with-changes-root-url): Document.
2421 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Don't call
2422 get_changes_url and free, change url variable type to const char * and
2423 set it to CHANGES_ROOT_URL "gcc-10/changes.html#empty_base".
2424 * config/s390/s390.c (s390_function_arg_vector,
2425 s390_function_arg_float): Likewise.
2426 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
2428 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
2430 * config.in: Regenerate.
2431 * configure: Regenerate.
2433 2020-04-30 Christophe Lyon <christophe.lyon@linaro.org>
2436 * config/arm/arm.c (isr_attribute_args): Remove duplicate entries.
2438 2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
2440 * config/s390/constraints.md ("j>f", "jb4"): New constraints.
2441 * config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix
2443 * config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a
2445 ("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst.
2446 Change constraint for vlrl/vstrl to jb4.
2448 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2450 * var-tracking.c (vt_initialize): Move variables pre and post
2451 into inner block and initialize both in order to fix warning
2452 about uninitialized use. Remove unnecessary checks for
2453 frame_pointer_needed.
2455 2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2457 * toplev.c (output_stack_usage_1): Ensure that first
2458 argument to fprintf is not null.
2460 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2462 * configure.ac (-with-changes-root-url): New configure option,
2463 defaulting to https://gcc.gnu.org/.
2464 * Makefile.in (CFLAGS-opts.o): Define CHANGES_ROOT_URL for
2466 * pretty-print.c (get_end_url_string): New function.
2467 (pp_format): Handle %{ and %} for URLs.
2468 (pp_begin_url): Use pp_string instead of pp_printf.
2469 (pp_end_url): Use get_end_url_string.
2470 * opts.h (get_changes_url): Declare.
2471 * opts.c (get_changes_url): New function.
2472 * config/rs6000/rs6000-call.c: Include opts.h.
2473 (rs6000_discover_homogeneous_aggregate): Use %{in GCC 10.1%} instead
2474 of just in GCC 10.1 in diagnostics and add URL.
2475 * config/arm/arm.c (aapcs_vfp_is_call_or_return_candidate): Likewise.
2476 * config/aarch64/aarch64.c (aarch64_vfp_is_call_or_return_candidate):
2478 * config/s390/s390.c (s390_function_arg_vector,
2479 s390_function_arg_float): Likewise.
2480 * configure: Regenerated.
2483 * config/s390/s390.c (s390_function_arg_vector,
2484 s390_function_arg_float): Use DECL_FIELD_ABI_IGNORED instead of
2485 cxx17_empty_base_field_p. In -Wpsabi diagnostics use the type
2486 passed to the function rather than the type of the single element.
2487 Rename cxx17_empty_base_seen variable to empty_base_seen, change
2488 type to int, and adjust diagnostics depending on if the field
2489 has [[no_unique_attribute]] or not.
2492 * config/i386/avx512bwintrin.h (_mm512_alignr_epi8,
2493 _mm512_mask_alignr_epi8, _mm512_maskz_alignr_epi8): Wrap macro operands
2494 used in casts into parens.
2495 * config/i386/avx512fintrin.h (_mm512_cvt_roundps_ph, _mm512_cvtps_ph,
2496 _mm512_mask_cvt_roundps_ph, _mm512_mask_cvtps_ph,
2497 _mm512_maskz_cvt_roundps_ph, _mm512_maskz_cvtps_ph,
2498 _mm512_mask_cmp_epi64_mask, _mm512_mask_cmp_epi32_mask,
2499 _mm512_mask_cmp_epu64_mask, _mm512_mask_cmp_epu32_mask,
2500 _mm512_mask_cmp_round_pd_mask, _mm512_mask_cmp_round_ps_mask,
2501 _mm512_mask_cmp_pd_mask, _mm512_mask_cmp_ps_mask): Likewise.
2502 * config/i386/avx512vlbwintrin.h (_mm256_mask_alignr_epi8,
2503 _mm256_maskz_alignr_epi8, _mm_mask_alignr_epi8, _mm_maskz_alignr_epi8,
2504 _mm256_mask_cmp_epu8_mask): Likewise.
2505 * config/i386/avx512vlintrin.h (_mm_mask_cvtps_ph, _mm_maskz_cvtps_ph,
2506 _mm256_mask_cvtps_ph, _mm256_maskz_cvtps_ph): Likewise.
2507 * config/i386/f16cintrin.h (_mm_cvtps_ph, _mm256_cvtps_ph): Likewise.
2508 * config/i386/shaintrin.h (_mm_sha1rnds4_epu32): Likewise.
2511 * config/i386/avx2intrin.h (_mm_mask_i32gather_pd,
2512 _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd,
2513 _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps,
2514 _mm256_mask_i32gather_ps, _mm_mask_i64gather_ps,
2515 _mm256_mask_i64gather_ps, _mm_i32gather_epi64,
2516 _mm_mask_i32gather_epi64, _mm256_i32gather_epi64,
2517 _mm256_mask_i32gather_epi64, _mm_i64gather_epi64,
2518 _mm_mask_i64gather_epi64, _mm256_i64gather_epi64,
2519 _mm256_mask_i64gather_epi64, _mm_i32gather_epi32,
2520 _mm_mask_i32gather_epi32, _mm256_i32gather_epi32,
2521 _mm256_mask_i32gather_epi32, _mm_i64gather_epi32,
2522 _mm_mask_i64gather_epi32, _mm256_i64gather_epi32,
2523 _mm256_mask_i64gather_epi32): Surround macro parameter uses with
2525 (_mm_i32gather_pd, _mm256_i32gather_pd, _mm_i64gather_pd,
2526 _mm256_i64gather_pd, _mm_i32gather_ps, _mm256_i32gather_ps,
2527 _mm_i64gather_ps, _mm256_i64gather_ps): Likewise. Don't use
2528 as mask vector containing -1.0 or -1.0f elts, but instead vector
2529 with all bits set using _mm*_cmpeq_p? with zero operands.
2530 * config/i386/avx512fintrin.h (_mm512_i32gather_ps,
2531 _mm512_mask_i32gather_ps, _mm512_i32gather_pd,
2532 _mm512_mask_i32gather_pd, _mm512_i64gather_ps,
2533 _mm512_mask_i64gather_ps, _mm512_i64gather_pd,
2534 _mm512_mask_i64gather_pd, _mm512_i32gather_epi32,
2535 _mm512_mask_i32gather_epi32, _mm512_i32gather_epi64,
2536 _mm512_mask_i32gather_epi64, _mm512_i64gather_epi32,
2537 _mm512_mask_i64gather_epi32, _mm512_i64gather_epi64,
2538 _mm512_mask_i64gather_epi64, _mm512_i32scatter_ps,
2539 _mm512_mask_i32scatter_ps, _mm512_i32scatter_pd,
2540 _mm512_mask_i32scatter_pd, _mm512_i64scatter_ps,
2541 _mm512_mask_i64scatter_ps, _mm512_i64scatter_pd,
2542 _mm512_mask_i64scatter_pd, _mm512_i32scatter_epi32,
2543 _mm512_mask_i32scatter_epi32, _mm512_i32scatter_epi64,
2544 _mm512_mask_i32scatter_epi64, _mm512_i64scatter_epi32,
2545 _mm512_mask_i64scatter_epi32, _mm512_i64scatter_epi64,
2546 _mm512_mask_i64scatter_epi64): Surround macro parameter uses with
2548 * config/i386/avx512pfintrin.h (_mm512_prefetch_i32gather_pd,
2549 _mm512_prefetch_i32gather_ps, _mm512_mask_prefetch_i32gather_pd,
2550 _mm512_mask_prefetch_i32gather_ps, _mm512_prefetch_i64gather_pd,
2551 _mm512_prefetch_i64gather_ps, _mm512_mask_prefetch_i64gather_pd,
2552 _mm512_mask_prefetch_i64gather_ps, _mm512_prefetch_i32scatter_pd,
2553 _mm512_prefetch_i32scatter_ps, _mm512_mask_prefetch_i32scatter_pd,
2554 _mm512_mask_prefetch_i32scatter_ps, _mm512_prefetch_i64scatter_pd,
2555 _mm512_prefetch_i64scatter_ps, _mm512_mask_prefetch_i64scatter_pd,
2556 _mm512_mask_prefetch_i64scatter_ps): Likewise.
2557 * config/i386/avx512vlintrin.h (_mm256_mmask_i32gather_ps,
2558 _mm_mmask_i32gather_ps, _mm256_mmask_i32gather_pd,
2559 _mm_mmask_i32gather_pd, _mm256_mmask_i64gather_ps,
2560 _mm_mmask_i64gather_ps, _mm256_mmask_i64gather_pd,
2561 _mm_mmask_i64gather_pd, _mm256_mmask_i32gather_epi32,
2562 _mm_mmask_i32gather_epi32, _mm256_mmask_i32gather_epi64,
2563 _mm_mmask_i32gather_epi64, _mm256_mmask_i64gather_epi32,
2564 _mm_mmask_i64gather_epi32, _mm256_mmask_i64gather_epi64,
2565 _mm_mmask_i64gather_epi64, _mm256_i32scatter_ps,
2566 _mm256_mask_i32scatter_ps, _mm_i32scatter_ps, _mm_mask_i32scatter_ps,
2567 _mm256_i32scatter_pd, _mm256_mask_i32scatter_pd, _mm_i32scatter_pd,
2568 _mm_mask_i32scatter_pd, _mm256_i64scatter_ps,
2569 _mm256_mask_i64scatter_ps, _mm_i64scatter_ps, _mm_mask_i64scatter_ps,
2570 _mm256_i64scatter_pd, _mm256_mask_i64scatter_pd, _mm_i64scatter_pd,
2571 _mm_mask_i64scatter_pd, _mm256_i32scatter_epi32,
2572 _mm256_mask_i32scatter_epi32, _mm_i32scatter_epi32,
2573 _mm_mask_i32scatter_epi32, _mm256_i32scatter_epi64,
2574 _mm256_mask_i32scatter_epi64, _mm_i32scatter_epi64,
2575 _mm_mask_i32scatter_epi64, _mm256_i64scatter_epi32,
2576 _mm256_mask_i64scatter_epi32, _mm_i64scatter_epi32,
2577 _mm_mask_i64scatter_epi32, _mm256_i64scatter_epi64,
2578 _mm256_mask_i64scatter_epi64, _mm_i64scatter_epi64,
2579 _mm_mask_i64scatter_epi64): Likewise.
2581 2020-04-29 Jeff Law <law@redhat.com>
2583 * config/h8300/h8300.md (H8/SX div patterns): All H8/SX specific
2584 division instructions are 4 bytes long.
2586 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2589 * config/rs6000/rs6000.c (rs6000_atomic_assign_expand_fenv): Use
2590 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2591 fenv_var, fenv_clear and old_fenv variables. For fenv_addr
2592 take address of TARGET_EXPR of fenv_var with void_node initializer.
2595 2020-04-29 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2597 PR tree-optimization/94774
2598 * gimple-ssa-sprintf.c (try_substitute_return_value): Initialize
2601 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2603 * calls.h (cxx17_empty_base_field_p): Turn into a function declaration.
2604 * calls.c (cxx17_empty_base_field_p): New function. Check
2605 DECL_ARTIFICIAL and RECORD_OR_UNION_TYPE_P in addition to the
2608 2020-04-29 H.J. Lu <hongjiu.lu@intel.com>
2611 * config/i386/i386-options.c (ix86_set_indirect_branch_type):
2612 Allow -fcf-protection with -mindirect-branch=thunk-extern and
2613 -mfunction-return=thunk-extern.
2614 * doc/invoke.texi: Update notes for -fcf-protection=branch with
2615 -mindirect-branch=thunk-extern and -mindirect-return=thunk-extern.
2617 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2619 * doc/sourcebuild.texi: Add missing arm_arch_v8a_hard_ok anchor.
2621 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2623 * config/arm/arm-builtins.c (arm_atomic_assign_expand_fenv): Use
2624 TARGET_EXPR instead of MODIFY_EXPR for the first assignments to
2625 fenv_var and new_fenv_var.
2627 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2629 * doc/sourcebuild.texi (arm_arch_v8a_hard_ok): Document new
2630 effective-target keyword.
2631 (arm_arch_v8a_hard_multilib): Likewise.
2632 (arm_arch_v8a_hard): Document new dg-add-options keyword.
2633 * config/arm/arm.c (arm_return_in_memory): Note that the APCS
2634 code is deprecated and has not been updated to handle
2635 DECL_FIELD_ABI_IGNORED.
2636 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2637 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2638 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2639 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2640 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2641 something actually is a HFA or HVA. Record whether we see a
2642 [[no_unique_address]] field that previous GCCs would not have
2643 ignored in this way.
2644 (aapcs_vfp_is_call_or_return_candidate): Update the calls to
2645 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2646 [[no_unique_address]] case. Use TYPE_MAIN_VARIANT in the
2647 diagnostic messages.
2648 (arm_needs_doubleword_align): Add a comment explaining why we
2649 consider even zero-sized fields.
2651 2020-04-29 Richard Biener <rguenther@suse.de>
2652 Li Zekun <lizekun1@huawei.com>
2655 * tree.c (component_ref_size): Guard against error_mark_node
2656 DECL_INITIAL as it happens with LTO.
2658 2020-04-29 Richard Sandiford <richard.sandiford@arm.com>
2660 * config/aarch64/aarch64.c (aarch64_function_arg_alignment): Add a
2661 comment explaining why we consider even zero-sized fields.
2662 (WARN_PSABI_EMPTY_CXX17_BASE): New constant.
2663 (WARN_PSABI_NO_UNIQUE_ADDRESS): Likewise.
2664 (aapcs_vfp_sub_candidate): Replace the boolean pointer parameter
2665 avoid_cxx17_empty_base with a pointer to a bitmask. Ignore fields
2666 whose DECL_FIELD_ABI_IGNORED bit is set when determining whether
2667 something actually is a HFA or HVA. Record whether we see a
2668 [[no_unique_address]] field that previous GCCs would not have
2669 ignored in this way.
2670 (aarch64_vfp_is_call_or_return_candidate): Add a parameter to say
2671 whether diagnostics should be suppressed. Update the calls to
2672 aapcs_vfp_sub_candidate and report a -Wpsabi warning for the
2673 [[no_unique_address]] case.
2674 (aarch64_return_in_msb): Update call accordingly, never silencing
2676 (aarch64_function_value): Likewise.
2677 (aarch64_return_in_memory_1): Likewise.
2678 (aarch64_init_cumulative_args): Likewise.
2679 (aarch64_gimplify_va_arg_expr): Likewise.
2680 (aarch64_pass_by_reference_1): Take a CUMULATIVE_ARGS pointer and
2681 use it to decide whether arch64_vfp_is_call_or_return_candidate
2683 (aarch64_pass_by_reference): Update calls accordingly.
2684 (aarch64_vfp_is_call_candidate): Use the CUMULATIVE_ARGS argument
2685 to decide whether arch64_vfp_is_call_or_return_candidate should be
2688 2020-04-29 Haijian Zhang <z.zhanghaijian@huawei.com>
2691 * config/aarch64/aarch64-builtins.c
2692 (aarch64_atomic_assign_expand_fenv): Use TARGET_EXPR instead of
2693 MODIFY_EXPR for first assignment to fenv_cr, fenv_sr and
2696 2020-04-29 Thomas Schwinge <thomas@codesourcery.com>
2698 * configure.ac <$enable_offload_targets>: Do parsing as done
2700 * configure: Regenerate.
2702 * configure.ac <$enable_offload_targets>: 'amdgcn' is 'gcn'.
2703 * configure: Regenerate.
2706 * rtlanal.c (set_noop_p): Handle non-constant selectors.
2709 * common/config/gcn/gcn-common.c (gcn_except_unwind_info): New
2711 (TARGET_EXCEPT_UNWIND_INFO): Define.
2713 2020-04-29 Jakub Jelinek <jakub@redhat.com>
2716 * config/gcn/gcn.md (*mov<mode>_insn): Use
2717 'reg_overlap_mentioned_p' to check for overlap.
2720 * config/ia64/ia64.c (hfa_element_mode): Use DECL_FIELD_ABI_IGNORED
2721 instead of cxx17_empty_base_field_p.
2724 * tree-core.h (tree_decl_common): Note decl_flag_0 used for
2725 DECL_FIELD_ABI_IGNORED.
2726 * tree.h (DECL_FIELD_ABI_IGNORED): Define.
2727 * calls.h (cxx17_empty_base_field_p): Change into a temporary
2728 macro, check DECL_FIELD_ABI_IGNORED flag with no "no_unique_address"
2730 * calls.c (cxx17_empty_base_field_p): Remove.
2731 * tree-streamer-out.c (pack_ts_decl_common_value_fields): Handle
2732 DECL_FIELD_ABI_IGNORED.
2733 * tree-streamer-in.c (unpack_ts_decl_common_value_fields): Likewise.
2734 * lto-streamer-out.c (hash_tree): Likewise.
2735 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Rename
2736 cxx17_empty_base_seen to empty_base_seen, change type to int *,
2737 adjust recursive calls, use DECL_FIELD_ABI_IGNORED instead of
2738 cxx17_empty_base_field_p, if "no_unique_address" attribute is
2739 present, propagate that to the caller too.
2740 (rs6000_discover_homogeneous_aggregate): Adjust
2741 rs6000_aggregate_candidate caller, emit different diagnostics
2742 when c++17 empty base fields are present and when empty
2743 [[no_unique_address]] fields are present.
2744 * config/rs6000/rs6000.c (rs6000_special_round_type_align,
2745 darwin_rs6000_special_round_type_align): Skip DECL_FIELD_ABI_IGNORED
2748 2020-04-29 Richard Biener <rguenther@suse.de>
2750 * tree-ssa-loop-im.c (ref_always_accessed::operator ()):
2751 Just check whether the stmt stores.
2753 2020-04-28 Alexandre Oliva <oliva@adacore.com>
2756 * config/rs6000/rs6000.md (rs6000_mffsl): Copy result to
2757 output operand in emulation. Don't overwrite pseudos.
2759 2020-04-28 Jeff Law <law@redhat.com>
2761 * config/h8300/h8300.md (H8/SX mult patterns): All H8/SX specific
2762 multiply patterns are 4 bytes long.
2764 2020-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2766 * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option.
2767 * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option.
2769 2020-04-28 Matthew Malcomson <matthew.malcomson@arm.com>
2770 Jakub Jelinek <jakub@redhat.com>
2773 * config/arm/arm.c (aapcs_vfp_sub_candidate): Account for C++17 empty
2774 base class artificial fields.
2775 (aapcs_vfp_is_call_or_return_candidate): Warn when PCS ABI
2776 decision is different after this fix.
2778 2020-04-28 David Malcolm <dmalcolm@redhat.com>
2784 * doc/invoke.texi (Static Analyzer Options): Remove
2785 -Wanalyzer-use-of-uninitialized-value.
2786 (-Wno-analyzer-use-of-uninitialized-value): Remove item.
2788 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2790 PR tree-optimization/94809
2791 * tree.c (build_call_expr_internal_loc_array): Call
2792 process_call_operands.
2794 2020-04-27 Anton Youdkevitch <anton.youdkevitch@bell-sw.com>
2796 * config/aarch64/aarch64-cores.def (thunderx3t110): Add the chip name.
2797 * config/aarch64/aarch64-tune.md: Regenerate.
2798 * config/aarch64/aarch64.c (thunderx3t110_addrcost_table): Define.
2799 (thunderx3t110_regmove_cost): Likewise.
2800 (thunderx3t110_vector_cost): Likewise.
2801 (thunderx3t110_prefetch_tune): Likewise.
2802 (thunderx3t110_tunings): Likewise.
2803 * config/aarch64/aarch64-cost-tables.h (thunderx3t110_extra_costs):
2805 * config/aarch64/thunderx3t110.md: New file.
2806 * config/aarch64/aarch64.md: Include thunderx3t110.md.
2807 * doc/invoke.texi (AArch64 options): Add thunderx3t110.
2809 2020-04-28 Jakub Jelinek <jakub@redhat.com>
2812 * config/s390/s390.c (s390_function_arg_vector,
2813 s390_function_arg_float): Emit -Wpsabi diagnostics if the ABI changed.
2815 2020-04-28 Richard Sandiford <richard.sandiford@arm.com>
2817 PR tree-optimization/94727
2818 * tree-vect-stmts.c (vect_is_simple_cond): If both comparison
2819 operands are invariant booleans, use the mask type associated with the
2820 STMT_VINFO_VECTYPE. Use !slp_node instead of !vectype to exclude SLP.
2821 (vectorizable_condition): Pass vectype unconditionally to
2822 vect_is_simple_cond.
2824 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2827 * config/i386/i386.c (ix86_atomic_assign_expand_fenv): Use
2828 TARGET_EXPR instead of MODIFY_EXPR for first assignment to
2829 sw_var, exceptions_var, mxcsr_orig_var and mxcsr_mod_var.
2831 2020-04-27 David Malcolm <dmalcolm@redhat.com>
2834 * configure.ac (DOCUMENTATION_ROOT_URL): Drop trailing "gcc/" from
2835 default value, so that it can by supplied by get_option_html_page.
2836 * configure: Regenerate.
2837 * opts.c: Include "selftest.h".
2838 (get_option_html_page): New function.
2839 (get_option_url): Use it. Reformat to place comments next to the
2840 expressions they refer to.
2841 (selftest::test_get_option_html_page): New.
2842 (selftest::opts_c_tests): New.
2843 * selftest-run-tests.c (selftest::run_tests): Call
2844 selftest::opts_c_tests.
2845 * selftest.h (selftest::opts_c_tests): New decl.
2847 2020-04-27 Richard Sandiford <richard.sandiford@arm.com>
2849 * config/arm/arm-builtins.c (arm_expand_builtin_args): Only apply
2850 UINTVAL to CONST_INTs.
2852 2020-04-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2854 * config/arm/constraints.md (e): Remove constraint.
2855 (Te): Define constraint.
2856 * config/arm/mve.md (vaddvq_<supf><mode>): Modify constraint in
2857 operand 0 from "e" to "Te".
2858 (vaddvaq_<supf><mode>): Likewise.
2859 (vaddvq_p_<supf><mode>): Likewise.
2860 (vmladavq_<supf><mode>): Likewise.
2861 (vmladavxq_s<mode>): Likewise.
2862 (vmlsdavq_s<mode>): Likewise.
2863 (vmlsdavxq_s<mode>): Likewise.
2864 (vaddvaq_p_<supf><mode>): Likewise.
2865 (vmladavaq_<supf><mode>): Likewise.
2866 (vmladavq_p_<supf><mode>): Likewise.
2867 (vmladavxq_p_s<mode>): Likewise.
2868 (vmlsdavq_p_s<mode>): Likewise.
2869 (vmlsdavxq_p_s<mode>): Likewise.
2870 (vmlsdavaxq_s<mode>): Likewise.
2871 (vmlsdavaq_s<mode>): Likewise.
2872 (vmladavaxq_s<mode>): Likewise.
2873 (vmladavaq_p_<supf><mode>): Likewise.
2874 (vmladavaxq_p_s<mode>): Likewise.
2875 (vmlsdavaq_p_s<mode>): Likewise.
2876 (vmlsdavaxq_p_s<mode>): Likewise.
2878 2020-04-27 Andre Vieira <andre.simoesdiasvieira@arm.com>
2880 * config/arm/arm.c (output_move_neon): Only get the first operand if
2883 2020-04-27 Felix Yang <felix.yang@huawei.com>
2885 PR tree-optimization/94784
2886 * tree-ssa-forwprop.c (simplify_vector_constructor): Flip the
2887 assert around so that it checks that the two vectors have equal
2888 TYPE_VECTOR_SUBPARTS and that converting the corresponding element
2889 types is a useless_type_conversion_p.
2891 2020-04-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
2894 * dwarf2cfi.c (struct GTY): Add ra_mangled.
2895 (cfi_row_equal_p): Check ra_mangled.
2896 (dwarf2out_frame_debug_cfa_window_save): Remove the argument,
2897 this only handles the sparc logic now.
2898 (dwarf2out_frame_debug_cfa_toggle_ra_mangle): New function for
2899 the aarch64 specific logic.
2900 (dwarf2out_frame_debug): Update to use the new subroutines.
2901 (change_cfi_row): Check ra_mangled.
2903 2020-04-27 Jakub Jelinek <jakub@redhat.com>
2906 * config/s390/s390.c (s390_function_arg_vector,
2907 s390_function_arg_float): Ignore cxx17_empty_base_field_p fields.
2909 2020-04-27 Jiufu Guo <guojiufu@cn.ibm.com>
2911 * common/config/rs6000/rs6000-common.c
2912 (rs6000_option_optimization_table) [OPT_LEVELS_ALL]: Remove turn off
2914 * config/rs6000/rs6000.c (rs6000_option_override_internal): Avoid to
2917 2020-04-27 Martin Liska <mliska@suse.cz>
2920 * cgraph.h (cgraph_node::can_remove_if_no_direct_calls_and_refs_p):
2921 Do not remove ifunc_resolvers in remove unreachable nodes in LTO.
2923 2020-04-27 Xiong Hu Luo <luoxhu@linux.ibm.com>
2926 * config/rs6000/rs6000-logue.c (frame_pointer_needed_indeed):
2928 (rs6000_emit_prologue_components):
2929 Check with frame_pointer_needed_indeed.
2930 (rs6000_emit_epilogue_components): Likewise.
2931 (rs6000_emit_prologue): Likewise.
2932 (rs6000_emit_epilogue): Set frame_pointer_needed_indeed.
2934 2020-04-25 David Edelsohn <dje.gcc@gmail.com>
2936 * config/rs6000/rs6000-logue.c (rs6000_stack_info): Don't push a
2937 stack frame when debugging and flag_compare_debug is enabled.
2939 2020-04-25 Michael Meissner <meissner@linux.ibm.com>
2941 * config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Define to
2942 enable PC-relative addressing for -mcpu=future.
2943 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Move
2944 after OTHER_FUTURE_MASKS. Use OTHER_FUTURE_MASKS.
2945 * config/rs6000/rs6000.c (PCREL_SUPPORTED_BY_OS): If not defined,
2946 suppress PC-relative addressing.
2947 (rs6000_option_override_internal): Split up error messages
2948 checking for -mprefixed and -mpcrel. Enable -mpcrel if the target
2951 2020-04-25 Jakub Jelinek <jakub@redhat.com>
2952 Richard Biener <rguenther@suse.de>
2954 PR tree-optimization/94734
2955 PR tree-optimization/89430
2956 * tree-ssa-phiopt.c: Include tree-eh.h.
2957 (cond_store_replacement): Return false if an automatic variable
2958 access could trap. If -fstore-data-races, don't return false
2959 just because an automatic variable is addressable.
2961 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2963 * config/gcn/gcn-valu.md (add<mode>_zext_dup2_exec): Fix merge
2965 (add<mode>_sext_dup2_exec): Likewise.
2967 2020-04-24 Segher Boessenkool <segher@kernel.crashing.org>
2970 * config/rs6000/vector.md (vec_shr_<mode> for VEC_L): Correct little
2971 endian byteshift_val calculation.
2973 2020-04-24 Andrew Stubbs <ams@codesourcery.com>
2975 * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
2977 2020-04-24 Richard Sandiford <richard.sandiford@arm.com>
2979 * config/aarch64/arm_sve.h: Add a comment.
2981 2020-04-24 Haijian Zhang <z.zhanghaijian@huawei.com>
2983 PR rtl-optimization/94708
2984 * combine.c (simplify_if_then_else): Add check for
2985 !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode).
2987 2020-04-23 Martin Sebor <msebor@redhat.com>
2990 * common.opt (-Wno-frame-larger-than): New option.
2991 (-Wno-larger-than, -Wno-stack-usage): Same.
2993 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
2995 * config/gcn/gcn-valu.md (mov<mode>_exec): Swap the numbers on operands
2997 (mov<mode>_exec): Likewise.
2998 (trunc<vndi><mode>2_exec): Swap parameters to gen_mov<mode>_exec.
2999 (<convop><mode><vndi>2_exec): Likewise.
3001 2019-04-23 Eric Botcazou <ebotcazou@adacore.com>
3003 PR tree-optimization/94717
3004 * gimple-ssa-store-merging.c (try_coalesce_bswap): Return false if one
3005 of the stores doesn't have the same landing pad number as the first.
3006 (coalesce_immediate_stores): Do not try to coalesce the store using
3007 bswap if it doesn't have the same landing pad number as the first.
3009 2020-04-23 Bill Schmidt <wschmidt@linux.ibm.com>
3011 * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
3012 Replace outdated link to ELFv2 ABI.
3014 2020-04-23 Jakub Jelinek <jakub@redhat.com>
3017 * optabs.c (expand_vec_perm_const): For shift_amt const0_rtx
3021 * tree.c (get_narrower): Instead of creating COMPOUND_EXPRs
3022 temporarily with non-final second operand and updating it later,
3023 push COMPOUND_EXPRs into a vector and process it in reverse,
3024 creating COMPOUND_EXPRs with the final operands.
3026 2020-04-23 Szabolcs Nagy <szabolcs.nagy@arm.com>
3029 * config/aarch64/aarch64-bti-insert.c (rest_of_insert_bti): Swap
3030 bti c and bti j handling.
3032 2020-04-23 Andrew Stubbs <ams@codesourcery.com>
3033 Thomas Schwinge <thomas@codesourcery.com>
3037 * omp-expand.c (expand_omp_target): Use force_gimple_operand_gsi on
3038 t_async and the wait arguments.
3040 2020-04-23 Richard Sandiford <richard.sandiford@arm.com>
3042 PR tree-optimization/94727
3043 * tree-vect-stmts.c (vectorizable_comparison): Use mask_type when
3044 comparing invariant scalar booleans.
3046 2020-04-23 Matthew Malcomson <matthew.malcomson@arm.com>
3047 Jakub Jelinek <jakub@redhat.com>
3050 * config/aarch64/aarch64.c (aapcs_vfp_sub_candidate): Account for C++17
3051 empty base class artificial fields.
3052 (aarch64_vfp_is_call_or_return_candidate): Warn when ABI PCS decision is
3053 different after this fix.
3055 2020-04-23 Jakub Jelinek <jakub@redhat.com>
3058 * config/rs6000/rs6000-call.c (rs6000_discover_homogeneous_aggregate):
3059 Use TYPE_UID (TYPE_MAIN_VARIANT (type)) instead of type to check
3060 if the same type has been diagnosed most recently already.
3062 2020-04-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3064 * config/arm/arm_mve.h (__arm_vbicq_n_u16): Modify function parameter's
3066 (__arm_vbicq_n_s16): Likewise.
3067 (__arm_vbicq_n_u32): Likewise.
3068 (__arm_vbicq_n_s32): Likewise.
3069 (__arm_vbicq): Likewise.
3070 (__arm_vbicq_n_s16): Modify MVE polymorphic variant argument's datatype.
3071 (__arm_vbicq_n_s32): Likewise.
3072 (__arm_vbicq_n_u16): Likewise.
3073 (__arm_vbicq_n_u32): Likewise.
3074 (__arm_vdupq_m_n_s8): Likewise.
3075 (__arm_vdupq_m_n_s16): Likewise.
3076 (__arm_vdupq_m_n_s32): Likewise.
3077 (__arm_vdupq_m_n_u8): Likewise.
3078 (__arm_vdupq_m_n_u16): Likewise.
3079 (__arm_vdupq_m_n_u32): Likewise.
3080 (__arm_vdupq_m_n_f16): Likewise.
3081 (__arm_vdupq_m_n_f32): Likewise.
3082 (__arm_vldrhq_gather_offset_s16): Likewise.
3083 (__arm_vldrhq_gather_offset_s32): Likewise.
3084 (__arm_vldrhq_gather_offset_u16): Likewise.
3085 (__arm_vldrhq_gather_offset_u32): Likewise.
3086 (__arm_vldrhq_gather_offset_f16): Likewise.
3087 (__arm_vldrhq_gather_offset_z_s16): Likewise.
3088 (__arm_vldrhq_gather_offset_z_s32): Likewise.
3089 (__arm_vldrhq_gather_offset_z_u16): Likewise.
3090 (__arm_vldrhq_gather_offset_z_u32): Likewise.
3091 (__arm_vldrhq_gather_offset_z_f16): Likewise.
3092 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
3093 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
3094 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
3095 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
3096 (__arm_vldrhq_gather_shifted_offset_f16): Likewise.
3097 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
3098 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
3099 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
3100 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
3101 (__arm_vldrhq_gather_shifted_offset_z_f16): Likewise.
3102 (__arm_vldrwq_gather_offset_s32): Likewise.
3103 (__arm_vldrwq_gather_offset_u32): Likewise.
3104 (__arm_vldrwq_gather_offset_f32): Likewise.
3105 (__arm_vldrwq_gather_offset_z_s32): Likewise.
3106 (__arm_vldrwq_gather_offset_z_u32): Likewise.
3107 (__arm_vldrwq_gather_offset_z_f32): Likewise.
3108 (__arm_vldrwq_gather_shifted_offset_s32): Likewise.
3109 (__arm_vldrwq_gather_shifted_offset_u32): Likewise.
3110 (__arm_vldrwq_gather_shifted_offset_f32): Likewise.
3111 (__arm_vldrwq_gather_shifted_offset_z_s32): Likewise.
3112 (__arm_vldrwq_gather_shifted_offset_z_u32): Likewise.
3113 (__arm_vldrwq_gather_shifted_offset_z_f32): Likewise.
3114 (__arm_vdwdupq_x_n_u8): Likewise.
3115 (__arm_vdwdupq_x_n_u16): Likewise.
3116 (__arm_vdwdupq_x_n_u32): Likewise.
3117 (__arm_viwdupq_x_n_u8): Likewise.
3118 (__arm_viwdupq_x_n_u16): Likewise.
3119 (__arm_viwdupq_x_n_u32): Likewise.
3120 (__arm_vidupq_x_n_u8): Likewise.
3121 (__arm_vddupq_x_n_u8): Likewise.
3122 (__arm_vidupq_x_n_u16): Likewise.
3123 (__arm_vddupq_x_n_u16): Likewise.
3124 (__arm_vidupq_x_n_u32): Likewise.
3125 (__arm_vddupq_x_n_u32): Likewise.
3126 (__arm_vldrdq_gather_offset_s64): Likewise.
3127 (__arm_vldrdq_gather_offset_u64): Likewise.
3128 (__arm_vldrdq_gather_offset_z_s64): Likewise.
3129 (__arm_vldrdq_gather_offset_z_u64): Likewise.
3130 (__arm_vldrdq_gather_shifted_offset_s64): Likewise.
3131 (__arm_vldrdq_gather_shifted_offset_u64): Likewise.
3132 (__arm_vldrdq_gather_shifted_offset_z_s64): Likewise.
3133 (__arm_vldrdq_gather_shifted_offset_z_u64): Likewise.
3134 (__arm_vidupq_m_n_u8): Likewise.
3135 (__arm_vidupq_m_n_u16): Likewise.
3136 (__arm_vidupq_m_n_u32): Likewise.
3137 (__arm_vddupq_m_n_u8): Likewise.
3138 (__arm_vddupq_m_n_u16): Likewise.
3139 (__arm_vddupq_m_n_u32): Likewise.
3140 (__arm_vidupq_n_u16): Likewise.
3141 (__arm_vidupq_n_u32): Likewise.
3142 (__arm_vidupq_n_u8): Likewise.
3143 (__arm_vddupq_n_u16): Likewise.
3144 (__arm_vddupq_n_u32): Likewise.
3145 (__arm_vddupq_n_u8): Likewise.
3147 2020-04-23 Iain Buclaw <ibuclaw@gdcproject.org>
3149 * doc/install.texi (D-Specific Options): Document
3150 --enable-libphobos-checking and --with-libphobos-druntime-only.
3152 2020-04-23 Jakub Jelinek <jakub@redhat.com>
3155 * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Add
3156 cxx17_empty_base_seen argument. Pass it to recursive calls.
3157 Ignore cxx17_empty_base_field_p fields after setting
3158 *cxx17_empty_base_seen to true.
3159 (rs6000_discover_homogeneous_aggregate): Adjust
3160 rs6000_aggregate_candidate caller. With -Wpsabi, diagnose homogeneous
3161 aggregates with C++17 empty base fields.
3164 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
3165 if last_decl is error_mark_node or has such a TREE_TYPE.
3168 * attribs.c (decl_attribute): Don't diagnose attribute exclusions
3169 if last_decl is error_mark_node or has such a TREE_TYPE.
3171 2020-04-22 Felix Yang <felix.yang@huawei.com>
3174 * config/aarch64/aarch64.h (TARGET_SVE):
3175 Add && !TARGET_GENERAL_REGS_ONLY.
3176 (TARGET_SVE2): Add && TARGET_SVE.
3177 (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3,
3178 TARGET_SVE2_SM4): Add && TARGET_SVE2.
3179 * config/aarch64/aarch64-sve-builtins.h
3180 (sve_switcher::m_old_general_regs_only): New member.
3181 * config/aarch64/aarch64-sve-builtins.cc (check_required_registers):
3183 (reported_missing_registers_p): New variable.
3184 (check_required_extensions): Call check_required_registers before
3185 return if all required extenstions are present.
3186 (sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in
3187 m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in
3188 global_options.x_target_flags.
3189 (sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in
3190 global_options.x_target_flags if m_old_general_regs_only is true.
3192 2020-04-22 Zackery Spytz <zspytz@gmail.com>
3194 * doc/extend.exi: Add "free" to list of other builtin functions
3197 2020-04-20 Aaron Sawdey <acsawdey@linux.ibm.com>
3200 * config/rs6000/sync.md (load_quadpti): Add attr "prefixed"
3202 (store_quadpti): Ditto.
3203 (atomic_load<mode>): Do not swap doublewords if TARGET_PREFIXED as
3204 plq will be used and doesn't need it.
3205 (atomic_store<mode>): Ditto, for pstq.
3207 2020-04-22 Erick Ochoa <erick.ochoa@theobroma-systems.com>
3209 * doc/invoke.texi: Update flags turned on by -O3.
3211 2020-04-22 Jakub Jelinek <jakub@redhat.com>
3214 * config/ia64/ia64.c (hfa_element_mode): Ignore
3215 cxx17_empty_base_field_p fields.
3218 * calls.h (cxx17_empty_base_field_p): Declare.
3219 * calls.c (cxx17_empty_base_field_p): Define.
3221 2020-04-22 Christophe Lyon <christophe.lyon@linaro.org>
3223 * doc/sourcebuild.texi (arm_softfp_ok, arm_hard_ok): Document.
3225 2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
3226 Andre Vieira <andre.simoesdiasvieira@arm.com>
3227 Mihail Ionescu <mihail.ionescu@arm.com>
3229 * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
3230 * config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
3231 (ALL_QUIRKS): Add quirk_no_asmcpu.
3232 (cortex-m55): Define new cpu.
3233 * config/arm/arm-tables.opt: Regenerate.
3234 * config/arm/arm-tune.md: Likewise.
3235 * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
3237 2020-04-22 Richard Sandiford <richard.sandiford@arm.com>
3239 PR tree-optimization/94700
3240 * tree-ssa-forwprop.c (simplify_vector_constructor): When processing
3241 an identity constructor, use a VIEW_CONVERT_EXPR to handle mixtures
3242 of similarly-structured but distinct vector types.
3244 2020-04-21 Martin Sebor <msebor@redhat.com>
3247 * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Correct
3248 the computation of the lower bound of the source access size.
3249 (builtin_access::generic_overlap): Remove a hack for setting ranges
3252 2020-04-21 John David Anglin <danglin@gcc.gnu.org>
3254 * config/pa/som.h (ASM_WEAKEN_LABEL): Delete.
3255 (ASM_WEAKEN_DECL): New define.
3256 (HAVE_GAS_WEAKREF): Undefine.
3258 2020-04-21 Richard Sandiford <richard.sandiford@arm.com>
3260 PR tree-optimization/94683
3261 * tree-ssa-forwprop.c (simplify_vector_constructor): Use a
3262 VIEW_CONVERT_EXPR to handle mixtures of similarly-structured
3263 but distinct vector types.
3265 2020-04-21 Jakub Jelinek <jakub@redhat.com>
3268 * stor-layout.c (place_field, finalize_record_size): Don't emit
3269 -Wpadded warning on TYPE_ARTIFICIAL rli->t.
3270 * ubsan.c (ubsan_get_type_descriptor_type,
3271 ubsan_get_source_location_type, ubsan_create_data): Set
3273 * asan.c (asan_global_struct): Likewise.
3275 2020-04-21 Duan bo <duanbo3@huawei.com>
3278 * config/aarch64/aarch64.c: Add an error message for option conflict.
3279 * doc/invoke.texi (-mcmodel=large): Mention that -mcmodel=large is
3280 incompatible with -fpic, -fPIC and -mabi=ilp32.
3282 2020-04-21 Frederik Harwath <frederik@codesourcery.com>
3285 * omp-low.c (new_omp_context): Remove assignments to
3286 ctx->outer_reduction_clauses and ctx->local_reduction_clauses.
3288 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
3290 * config/s390/vector.md ("popcountv8hi2_vx", "popcountv4si2_vx")
3291 ("popcountv2di2_vx"): Use simplify_gen_subreg.
3293 2020-04-20 Andreas Krebbel <krebbel@linux.ibm.com>
3296 * config/s390/s390-builtin-types.def: Add 3 new function modes.
3297 * config/s390/s390-builtins.def: Add mode dependent low-level
3298 builtin and map the overloaded builtins to these.
3299 * config/s390/vx-builtins.md ("vec_selV_HW"): Rename to ...
3300 ("vsel<V_HW"): ... this and rewrite the pattern with bitops.
3302 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
3304 * tree-vect-loop.c (vect_better_loop_vinfo_p): If old_loop_vinfo
3305 has a variable VF, prefer new_loop_vinfo if it is cheaper for the
3306 estimated VF and is no worse at double the estimated VF.
3308 2020-04-20 Richard Sandiford <richard.sandiford@arm.com>
3311 * config/aarch64/aarch64.c (aarch64_sve_expand_vector_init): Fix
3312 order of arguments to rtx_vector_builder.
3313 (aarch64_sve_expand_vector_init_handle_trailing_constants): Likewise.
3314 When extending the trailing constants to a full vector, replace any
3315 variables with zeros.
3317 2020-04-20 Jan Hubicka <hubicka@ucw.cz>
3320 * tree-inline.c (optimize_inline_calls): Recompute calls_comdat_local
3323 2020-04-20 Martin Liska <mliska@suse.cz>
3325 * symtab.c (symtab_node::dump_references): Add space after
3327 (symtab_node::dump_referring): Likewise.
3329 2020-04-18 Jeff Law <law@redhat.com>
3332 * regrename.c (check_new_reg_p): Ignore DEBUG_INSNs when walking
3335 2020-04-18 Iain Buclaw <ibuclaw@gdcproject.org>
3337 * doc/sourcebuild.texi (Effective-Target Keywords, Environment
3338 attributes): Document d_runtime_has_std_library.
3340 2020-04-17 Jeff Law <law@redhat.com>
3342 PR rtl-optimization/90275
3343 * cse.c (cse_insn): Avoid recording nop sets in multi-set parallels
3344 when the destination has a REG_UNUSED note.
3346 2020-04-17 Tobias Burnus <tobias@codesourcery.com>
3349 * gimplify.c (gimplify_scan_omp_clauses): Turn MAP_TO_PSET to
3352 2020-04-17 Richard Sandiford <richard.sandiford@arm.com>
3354 * config/aarch64/aarch64.c (aarch64_advsimd_ldp_stp_p): New function.
3355 (aarch64_sve_adjust_stmt_cost): Add a vectype parameter. Double the
3356 cost of load and store insns if one loop iteration has enough scalar
3357 elements to use an Advanced SIMD LDP or STP.
3358 (aarch64_add_stmt_cost): Update call accordingly.
3360 2020-04-17 Jakub Jelinek <jakub@redhat.com>
3361 Jeff Law <law@redhat.com>
3364 * config/i386/i386.md (*testqi_ext_3): Use CCZmode rather than
3365 CCNOmode in ix86_match_ccmode if len is equal to <MODE>mode precision,
3366 or pos + len >= 32, or pos + len is equal to operands[2] precision
3367 and operands[2] is not a register operand. During splitting perform
3368 SImode AND if operands[0] doesn't have CCZmode and pos + len is
3369 equal to mode precision.
3371 2020-04-17 Richard Biener <rguenther@suse.de>
3374 * cgraphclones.c (cgraph_node::create_clone): Remove duplicate
3376 * dwarf2out.c (dw_val_equal_p): Fix pasto in
3377 dw_val_class_vms_delta comparison.
3378 * optabs.c (expand_binop_directly): Fix pasto in commutation
3380 * tree-ssa-sccvn.c (vn_reference_lookup_pieces): Fix pasto in
3383 2020-04-17 Jakub Jelinek <jakub@redhat.com>
3385 PR rtl-optimization/94618
3386 * cfgrtl.c (delete_insn_and_edges): Set purge not just when
3387 insn is the BB_END of its block, but also when it is only followed
3388 by DEBUG_INSNs in its block.
3390 PR tree-optimization/94621
3391 * tree-inline.c (remap_type_1): Don't dereference NULL TYPE_DOMAIN.
3392 Move id->adjust_array_error_bounds check first in the condition.
3394 2020-04-17 Martin Liska <mliska@suse.cz>
3395 Jonathan Yong <10walls@gmail.com>
3397 PR gcov-profile/94570
3398 * coverage.c (coverage_init): Use separator properly.
3400 2020-04-16 Peter Bergner <bergner@linux.ibm.com>
3402 PR rtl-optimization/93974
3403 * config/rs6000/rs6000.c (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
3404 (rs6000_cannot_substitute_mem_equiv_p): New function.
3406 2020-04-16 Martin Jambor <mjambor@suse.cz>
3409 * ipa-inline.h (ipa_saved_clone_sources): Declare.
3410 * ipa-inline-transform.c (ipa_saved_clone_sources): New variable.
3411 (save_inline_function_body): Link the new body holder with the
3413 * cgraph.c: Include ipa-inline.h.
3414 (cgraph_edge::redirect_call_stmt_to_callee): Try to find the decl from
3415 the statement in ipa_saved_clone_sources.
3416 * cgraphunit.c: Include ipa-inline.h.
3417 (expand_all_functions): Free ipa_saved_clone_sources.
3419 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
3422 * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
3423 the VNx16BI lowpart of the recursively-generated constant.
3425 2020-04-16 Martin Liska <mliska@suse.cz>
3426 Jakub Jelinek <jakub@redhat.com>
3429 * cgraphclones.c (set_new_clone_decl_and_node_flags): Drop
3430 DECL_IS_REPLACEABLE_OPERATOR during cloning.
3431 * tree-ssa-dce.c (valid_new_delete_pair_p): New function.
3432 (propagate_necessity): Check operator names.
3434 2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
3436 PR rtl-optimization/94605
3437 * early-remat.c (early_remat::process_block): Handle insns that
3438 set multiple candidate registers.
3439 2020-04-16 Jan Hubicka <hubicka@ucw.cz>
3441 PR gcov-profile/93401
3442 * common.opt (profile-prefix-path): New option.
3443 * coverae.c: Include diagnostics.h.
3444 (coverage_init): Strip profile prefix path.
3445 * doc/invoke.texi (-fprofile-prefix-path): Document.
3447 2020-04-16 Richard Biener <rguenther@suse.de>
3450 * expr.c (emit_move_multi_word): Do not generate code when
3451 the destination part is undefined_operand_subword_p.
3452 * lower-subreg.c (resolve_clobber): Look through a paradoxica
3455 2020-04-16 Martin Jambor <mjambor@suse.cz>
3457 PR tree-optimization/94598
3458 * tree-sra.c (verify_sra_access_forest): Fix verification of total
3459 scalarization accesses under access to one-element arrays.
3461 2020-04-16 Jakub Jelinek <jakub@redhat.com>
3464 * function.c (assign_parm_find_data_types): Add workaround for
3465 BROKEN_VALUE_INITIALIZATION compilers.
3467 2020-04-16 Richard Biener <rguenther@suse.de>
3469 * gdbhooks.py (TreePrinter): Print SSA_NAME_VERSION of SSA_NAME
3472 2020-04-15 Uroš Bizjak <ubizjak@gmail.com>
3475 * config/i386/i386-builtin.def (__builtin_ia32_movq128):
3476 Require OPTION_MASK_ISA_SSE2.
3478 2020-04-15 Gustavo Romero <gromero@linux.ibm.com>
3481 * dumpfile.c (selftest::temp_dump_context::temp_dump_context):
3482 Don't construct a dump_context temporary to call static method.
3484 2020-04-15 Andrea Corallo <andrea.corallo@arm.com>
3486 * config/aarch64/falkor-tag-collision-avoidance.c
3487 (valid_src_p): Check for aarch64_address_info type before
3488 accessing base field.
3490 2020-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
3492 * config/arm/mve.md (mve_vec_duplicate<mode>): New pattern.
3493 (V_sz_elem2): Remove unused mode attribute.
3495 2020-04-15 Matthew Malcomson <matthew.malcomson@arm.com>
3497 * config/arm/arm.md (arm_movdi): Disallow for MVE.
3499 2020-04-15 Richard Biener <rguenther@suse.de>
3502 * tree-ssa-alias.c (same_type_for_tbaa): Defer to
3503 alias_sets_conflict_p for pointers.
3505 2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
3508 * config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
3509 (extendhisi2_internal): Add %v1 before the load instructions.
3511 2020-04-14 Aaron Sawdey <acsawdey@linux.ibm.com>
3514 * config/rs6000/rs6000.c (address_to_insn_form): Do not attempt to
3515 use PC-relative addressing for TLS references.
3517 2020-04-14 Martin Jambor <mjambor@suse.cz>
3520 * ipa-sra.c: Include internal-fn.h.
3521 (enum isra_scan_context): Update comment.
3522 (scan_function): Treat calls to internal_functions like loads or stores.
3524 2020-04-14 Yang Yang <yangyang305@huawei.com>
3526 PR tree-optimization/94574
3527 * tree-ssa.c (non_rewritable_lvalue_p): Add size check when analyzing
3528 whether a vector-insert is rewritable using a BIT_INSERT_EXPR.
3530 2020-04-14 H.J. Lu <hongjiu.lu@intel.com>
3533 * config/i386/i386.c (ix86_get_ssemov): Remove mode size check.
3535 2020-04-13 Martin Sebor <msebor@redhat.com>
3537 * doc/extend.texi (-Wall): Mention -Wformat-overflow and
3538 -Wformat-truncation. Move -Wzero-length-bounds last.
3539 (-Wrestrict): Document positive form of option enabled by -Wall.
3541 2020-04-13 Zachary Spytz <zspytz@gmail.com>
3543 * doc/extend.texi: Add realloc to list of built-in functions
3544 are recognized by the compiler.
3546 2020-04-13 H.J. Lu <hongjiu.lu@intel.com>
3549 * config/i386/i386.c (ix86_expand_epilogue): Restore the frame
3550 pointer in word_mode for eh_return epilogues.
3552 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3554 * config/msp430/msp430.c (msp430_print_operand): Don't add offsets to
3555 memory references in %B, %C and %D operand selectors when the inner
3556 operand is a post increment address.
3558 2020-04-13 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3560 * config/msp430/msp430.c (msp430_print_operand): Offset a %C memory
3561 reference by 4 bytes, and %D memory reference by 6 bytes.
3563 2020-04-11 Uroš Bizjak <ubizjak@gmail.com>
3566 * config/i386/sse.md (REDUC_SSE_SMINMAX_MODE): Use TARGET_SSE2
3567 condition for V4SI, V8HI and V16QI modes.
3569 2020-04-11 Jakub Jelinek <jakub@redhat.com>
3573 * cselib.c (cselib_record_sp_cfa_base_equiv): Set PRESERVED_VALUE_P on
3576 2020-04-10 Thomas Schwinge <thomas@codesourcery.com>
3580 * omp-general.c (oacc_verify_routine_clauses): Diagnose if
3581 "#pragma omp declare target" has also been applied.
3583 2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
3585 * config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
3586 when to emit the epilogue_helper insn.
3587 * config/msp430/msp430.md (epilogue_helper): Add a return insn to the
3590 2020-04-09 Jakub Jelinek <jakub@redhat.com>
3593 * cselib.h (cselib_record_sp_cfa_base_equiv,
3594 cselib_sp_derived_value_p): Declare.
3595 * cselib.c (cselib_record_sp_cfa_base_equiv,
3596 cselib_sp_derived_value_p): New functions.
3597 * var-tracking.c (add_stores): Don't record MO_VAL_SET for
3598 cselib_sp_derived_value_p values.
3599 (vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
3600 start of extended basic blocks other than the first one
3601 for !frame_pointer_needed functions.
3603 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3605 * doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
3606 (aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
3607 (aarch64_sve2048_hw): Document.
3608 * config/aarch64/aarch64-protos.h
3609 (aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
3610 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
3611 __ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
3612 * config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
3614 (find_type_suffix_for_scalar_type): Use it instead of comparing
3616 (function_resolver::infer_vector_or_tuple_type): Likewise.
3617 (function_resolver::require_vector_type): Likewise.
3618 (handle_arm_sve_vector_bits_attribute): New function.
3619 * config/aarch64/aarch64.c (pure_scalable_type_info): New class.
3620 (aarch64_attribute_table): Add arm_sve_vector_bits.
3621 (aarch64_return_in_memory_1):
3622 (pure_scalable_type_info::piece::get_rtx): New function.
3623 (pure_scalable_type_info::num_zr): Likewise.
3624 (pure_scalable_type_info::num_pr): Likewise.
3625 (pure_scalable_type_info::get_rtx): Likewise.
3626 (pure_scalable_type_info::analyze): Likewise.
3627 (pure_scalable_type_info::analyze_registers): Likewise.
3628 (pure_scalable_type_info::analyze_array): Likewise.
3629 (pure_scalable_type_info::analyze_record): Likewise.
3630 (pure_scalable_type_info::add_piece): Likewise.
3631 (aarch64_some_values_include_pst_objects_p): Likewise.
3632 (aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
3633 to analyze whether the type is returned in SVE registers.
3634 (aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
3635 is passed in SVE registers.
3636 (aarch64_pass_by_reference_1): New function, extracted from...
3637 (aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
3638 to analyze whether the type is a pure scalable type and, if so,
3639 whether it should be passed by reference.
3640 (aarch64_return_in_msb): Return false for pure scalable types.
3641 (aarch64_function_value_1): Fold back into...
3642 (aarch64_function_value): ...this function. Use
3643 pure_scalable_type_info to analyze whether the type is a pure
3644 scalable type and, if so, which registers it should use. Handle
3645 types that include pure scalable types but are not themselves
3646 pure scalable types.
3647 (aarch64_return_in_memory_1): New function, split out from...
3648 (aarch64_return_in_memory): ...here. Use pure_scalable_type_info
3649 to analyze whether the type is a pure scalable type and, if so,
3650 whether it should be returned by reference.
3651 (aarch64_layout_arg): Remove orig_mode argument. Use
3652 pure_scalable_type_info to analyze whether the type is a pure
3653 scalable type and, if so, which registers it should use. Handle
3654 types that include pure scalable types but are not themselves
3655 pure scalable types.
3656 (aarch64_function_arg): Update call accordingly.
3657 (aarch64_function_arg_advance): Likewise.
3658 (aarch64_pad_reg_upward): On big-endian targets, return false for
3659 pure scalable types that are smaller than 16 bytes.
3660 (aarch64_member_type_forces_blk): New function.
3661 (aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
3662 (aarch64_short_vector_p): Return false for VECTOR_TYPEs that
3663 correspond to built-in SVE types. Do not rely on a vector mode
3664 if the type includes an pure scalable type. When returning true,
3665 assert that the mode is not an SVE mode.
3666 (aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
3667 built-in types here. When returning true, assert that the type
3668 does not have an SVE mode.
3669 (aarch64_can_change_mode_class): Don't allow anything to change
3670 between a predicate mode and a non-predicate mode. Also don't
3671 allow changes between SVE vector modes and other modes that
3672 might be bigger than 128 bits.
3673 (aarch64_invalid_binary_op): Reject binary operations that mix
3674 SVE and GNU vector types.
3675 (TARGET_MEMBER_TYPE_FORCES_BLK): Define.
3677 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3679 * config/aarch64/aarch64.c (aarch64_attribute_table): Add
3680 "SVE sizeless type".
3681 * config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
3682 (sizeless_type_p): New functions.
3683 (register_builtin_types): Apply make_type_sizeless to the type.
3684 (register_tuple_type): Likewise.
3685 (verify_type_context): Use sizeless_type_p instead of builin_type_p.
3687 2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
3689 * config/arm/arm_cde.h: Remove `extern "C"` when compiling for
3692 2020-04-09 Martin Jambor <mjambor@suse.cz>
3693 Richard Biener <rguenther@suse.de>
3695 PR tree-optimization/94482
3696 * tree-sra.c (create_access_replacement): Dump new replacement with
3698 (sra_modify_expr): Fix handling of cases when the original EXPR writes
3699 to only part of the replacement.
3700 * tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
3701 the first operand of combinations into REAL/IMAGPART_EXPR and
3704 2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
3706 * doc/sourcebuild.texi (check-function-bodies): Treat the third
3707 parameter as a list of option regexps and require each regexp
3710 2020-04-09 Andrea Corallo <andrea.corallo@arm.com>
3713 * config/aarch64/falkor-tag-collision-avoidance.c
3714 (valid_src_p): Fix missing rtx type check.
3716 2020-04-09 Bin Cheng <bin.cheng@linux.alibaba.com>
3717 Richard Biener <rguenther@suse.de>
3719 PR tree-optimization/93674
3720 * tree-ssa-loop-ivopts.c (langhooks.h): New include.
3721 (add_iv_candidate_for_use): For iv_use of non integer or pointer type,
3722 or non-mode precision type, add candidate in unsigned type with the
3725 2020-04-08 Clement Chigot <clement.chigot@atos.net>
3727 * config/rs6000/aix61.h (LIB_SPEC): Add -lc128 with -mlong-double-128.
3728 * config/rs6000/aix71.h (LIB_SPEC): Likewise.
3729 * config/rs6000/aix72.h (LIB_SPEC): Likewise.
3731 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3734 * cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
3736 * reload1.c (eliminate_regs_1): Avoid creating
3737 (plus (reg) (const_int 0)) in DEBUG_INSNs.
3739 PR tree-optimization/94524
3740 * tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
3741 negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
3742 op1 rather than op1 itself at the end. Punt for signed modulo by
3743 most negative constant.
3744 * tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
3745 modulo by most negative constant.
3747 2020-04-08 Richard Biener <rguenther@suse.de>
3749 PR rtl-optimization/93946
3750 * cse.c (cse_insn): Record the tabled expression in
3751 src_related. Verify a redundant store removal is valid.
3753 2020-04-08 H.J. Lu <hongjiu.lu@intel.com>
3756 * config/i386/i386-features.c (rest_of_insert_endbranch): Insert
3757 ENDBR at function entry if function will be called indirectly.
3759 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3762 * config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
3765 2020-04-08 Martin Liska <mliska@suse.cz>
3768 * gimple.c (gimple_call_operator_delete_p): Rename to...
3769 (gimple_call_replaceable_operator_delete_p): ... this.
3770 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3771 * gimple.h (gimple_call_operator_delete_p): Rename to ...
3772 (gimple_call_replaceable_operator_delete_p): ... this.
3773 * tree-core.h (tree_function_decl): Add replaceable_operator
3775 * tree-ssa-dce.c (mark_all_reaching_defs_necessary_1):
3776 Use DECL_IS_REPLACEABLE_OPERATOR_DELETE_P.
3777 (propagate_necessity): Use gimple_call_replaceable_operator_delete_p.
3778 (eliminate_unnecessary_stmts): Likewise.
3779 * tree-streamer-in.c (unpack_ts_function_decl_value_fields):
3780 Pack DECL_IS_REPLACEABLE_OPERATOR.
3781 * tree-streamer-out.c (pack_ts_function_decl_value_fields):
3782 Unpack the field here.
3783 * tree.h (DECL_IS_REPLACEABLE_OPERATOR): New.
3784 (DECL_IS_REPLACEABLE_OPERATOR_NEW_P): New.
3785 (DECL_IS_REPLACEABLE_OPERATOR_DELETE_P): New.
3786 * cgraph.c (cgraph_node::dump): Dump if an operator is replaceable.
3787 * ipa-icf.c (sem_item::compare_referenced_symbol_properties): Compare
3788 replaceable operator flags.
3790 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3791 Matthew Malcomson <matthew.malcomson@arm.com>
3793 * config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
3794 (CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
3795 (CX_TERNARY_QUALIFIERS): Likewise.
3796 (ARM_BUILTIN_CDE_PATTERN_START): Likewise.
3797 (ARM_BUILTIN_CDE_PATTERN_END): Likewise.
3798 (arm_init_acle_builtins): Initialize CDE builtins.
3799 (arm_expand_acle_builtin): Check CDE constant operands.
3800 * config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
3801 of CDE constant operand.
3802 * config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
3804 (ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
3805 * config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
3806 (__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
3807 (__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
3808 (__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
3809 (__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
3810 * config/arm/arm_cde_builtins.def: New file.
3811 * config/arm/iterators.md (V_reg): New attribute of SI.
3812 * config/arm/predicates.md (const_int_coproc_operand): New.
3813 (const_int_vcde1_operand, const_int_vcde2_operand): New.
3814 (const_int_vcde3_operand): New.
3815 * config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
3816 * config/arm/vfp.md (arm_vcx1<mode>): New entry.
3817 (arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
3818 (arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
3820 2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
3822 * config.gcc: Add arm_cde.h.
3823 * config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
3824 __ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
3825 * config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
3826 * config/arm/arm.c (arm_option_reconfigure_globals): Configure
3827 arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
3828 * config/arm/arm.h (TARGET_CDE): New macro.
3829 * config/arm/arm_cde.h: New file.
3830 * doc/invoke.texi: Document CDE options +cdecp[0-7].
3831 * doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
3833 (arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
3835 2020-04-08 Jakub Jelinek <jakub@redhat.com>
3837 PR rtl-optimization/94516
3838 * postreload.c: Include rtl-iter.h.
3839 (reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
3840 looking for all MEMs with RTX_AUTOINC operand.
3841 (move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
3843 2020-04-08 Tobias Burnus <tobias@codesourcery.com>
3845 * omp-grid.c (grid_eliminate_combined_simd_part): Use
3846 OMP_CLAUSE_CODE to access the omp clause code.
3848 2020-04-07 Jeff Law <law@redhat.com>
3850 PR rtl-optimization/92264
3851 * config/h8300/h8300.md (mov;add peephole2): Avoid applying when
3852 the destination is the stack pointer.
3854 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3856 PR rtl-optimization/94291
3857 PR rtl-optimization/84169
3858 * combine.c (try_combine): For split_i2i3, don't assume SET_DEST
3859 must be a REG or SUBREG of REG; if it is not one of these, don't
3862 2020-04-07 Richard Biener <rguenther@suse.de>
3865 * gimplify.c (gimplify_addr_expr): Also consider generated
3868 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3870 * config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
3872 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3874 * config/arm/arm_mve.h: Cast some pointers to expected types.
3876 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3878 * config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
3879 same with '__arm_' prefix.
3881 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3883 * config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
3885 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3887 * config/arm/arm.c (arm_mve_immediate_check): Removed.
3888 * config/arm/mve.md (MVE_pred2, MVE_constraint2): Added FP types.
3889 (mve_vcvtq_n_to_f_*, mve_vcvtq_n_from_f_*, mve_vqshrnbq_n_*,
3890 mve_vqshrntq_n_*, mve_vqshrunbq_n_s*, mve_vqshruntq_n_s*,
3891 mve_vcvtq_m_n_from_f_*, mve_vcvtq_m_n_to_f_*, mve_vqshrnbq_m_n_*,
3892 mve_vqrshruntq_m_n_s*, mve_vqshrunbq_m_n_s*,
3893 mve_vqshruntq_m_n_s*): Fixed immediate constraints.
3895 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3897 * config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
3899 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3901 * config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
3902 * config/arm/mve/md: Fix v[id]wdup patterns.
3904 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3906 * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
3907 * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
3909 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3911 * config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
3912 and remove const_ptr enums.
3914 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
3916 * config/arm/arm_mve.h (vsubq_n): Merge with...
3918 (vmulq_n): Merge with...
3920 (__ARM_mve_typeid): Simplify scalar and constant detection.
3922 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3925 * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
3926 for inter-lane permutation for 64-byte modes.
3929 * config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
3930 ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
3931 Assume it is a REG after that instead of testing it and doing FAIL
3932 otherwise. Formatting fix.
3934 2020-04-07 Sebastian Huber <sebastian.huber@embedded-brains.de>
3936 * config/rs6000/t-rtems: Delete mcpu=8540 multilib.
3938 2020-04-07 Jakub Jelinek <jakub@redhat.com>
3941 * config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
3942 handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
3944 2020-04-06 Jakub Jelinek <jakub@redhat.com>
3946 * cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
3947 + const0_rtx return the SP_DERIVED_VALUE_P.
3949 2020-04-06 Richard Sandiford <richard.sandiford@arm.com>
3951 PR rtl-optimization/92989
3952 * lra-lives.c (process_bb_lives): Do not treat eh_return data
3953 registers as being live at the beginning of the EH receiver.
3955 2020-04-05 Zachary Spytz <zspytz@gmail.com>
3957 * extend.texi: Add free to list of ISO C90 functions that
3958 are recognized by the compiler.
3960 2020-04-05 Nagaraju Mekala <nmekala@xilix.com>
3962 * config/microblaze/microblaze.c (microblaze_must_save_register): Check
3965 * config/microblaze/microblaze.md (trap): Update output pattern.
3967 2020-04-04 Hannes Domani <ssbssa@yahoo.de>
3968 Jakub Jelinek <jakub@redhat.com>
3971 * dwarf2out.c (gen_subprogram_die): Look through references, pointers,
3972 arrays, pointer-to-members, function types and qualifiers when
3973 checking if in-class DIE had an 'auto' or 'decltype(auto)' return type
3974 to emit type again on definition.
3976 2020-04-04 Jan Hubicka <hubicka@ucw.cz>
3979 * ipa-fnsummary.c (vrp_will_run_p): New function.
3980 (fre_will_run_p): New function.
3981 (evaluate_properties_for_edge): Use it.
3982 * ipa-inline.c (can_inline_edge_by_limits_p): Do not inline
3983 !optimize_debug to optimize_debug.
3985 2020-04-04 Jakub Jelinek <jakub@redhat.com>
3987 PR rtl-optimization/94468
3988 * cselib.c (references_value_p): Formatting fix.
3989 (cselib_useless_value_p): New function.
3990 (discard_useless_locs, discard_useless_values,
3991 cselib_invalidate_regno_val, cselib_invalidate_mem,
3992 cselib_record_set): Use it instead of
3993 v->locs == 0 && !PRESERVED_VALUE_P (v->val_rtx).
3996 * tree-iterator.h (expr_single): Declare.
3997 * tree-iterator.c (expr_single): New function.
3998 * tree.h (protected_set_expr_location_if_unset): Declare.
3999 * tree.c (protected_set_expr_location): Use expr_single.
4000 (protected_set_expr_location_if_unset): New function.
4002 2020-04-03 Jeff Law <law@redhat.com>
4004 PR rtl-optimization/92264
4005 * config/stormy16/stormy16.c (xstormy16_preferred_reload_class): Handle
4006 reloading of auto-increment addressing modes.
4008 2020-04-03 H.J. Lu <hongjiu.lu@intel.com>
4011 * config/i386/sse.md (ssse3_pshufbv8qi3): Mark scratch operand
4014 2020-04-03 Jeff Law <law@redhat.com>
4016 PR rtl-optimization/92264
4017 * config/m32r/m32r.c (m32r_output_block_move): Properly account for
4018 post-increment addressing of source operands as well as residuals
4019 when computing any adjustments to the input pointer.
4021 2020-04-03 Jakub Jelinek <jakub@redhat.com>
4024 * config/i386/sse.md (avx2_ph<plusminus_mnemonic>wv16hi3,
4025 avx2_ph<plusminus_mnemonic>dv8si3): Fix up RTL pattern to do
4026 second half of first lane from first lane of second operand and
4027 first half of second lane from second lane of first operand.
4029 2020-04-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
4031 * config/arm/arm_mve.h: Condition the header file on __ARM_FEATURE_MVE.
4033 2020-04-03 Tamar Christina <tamar.christina@arm.com>
4036 * common/config/aarch64/aarch64-common.c
4037 (aarch64_get_extension_string_for_isa_flags): Handle default flags.
4039 2020-04-03 Richard Biener <rguenther@suse.de>
4042 * tree.c (array_ref_low_bound): Deal with released SSA names
4045 2020-04-03 Kwok Cheung Yeung <kcy@codesourcery.com>
4047 * config/gcn/gcn.c (print_operand): Handle unordered comparison
4049 * config/gcn/predicates.md (gcn_fp_compare_operator): Add unordered
4050 comparison operators.
4052 2020-04-03 Kewen Lin <linkw@gcc.gnu.org>
4054 PR tree-optimization/94443
4055 * tree-vect-loop.c (vectorizable_live_operation): Use
4056 gsi_insert_seq_before to replace gsi_insert_before.
4058 2020-04-03 Martin Liska <mliska@suse.cz>
4061 * ipa-icf-gimple.c (func_checker::compare_gimple_call):
4062 Compare type attributes for gimple_call_fntypes.
4064 2020-04-02 Sandra Loosemore <sandra@codesourcery.com>
4066 * alias.c (get_alias_set): Fix comment typos.
4068 2020-04-02 Fritz Reese <foreese@gcc.gnu.org>
4071 * fortran/decl.c (match_attr_spec): Lump COMP_STRUCTURE/COMP_MAP into
4072 attribute checking used by TYPE.
4074 2020-04-02 Martin Jambor <mjambor@suse.cz>
4077 * ipa-sra.c (struct caller_issues): New fields candidate and
4078 call_from_outside_comdat.
4079 (check_for_caller_issues): Check for calls from outsied of
4080 candidate's same_comdat_group.
4081 (check_all_callers_for_issues): Set up issues.candidate, check result
4083 (mark_callers_calls_comdat_local): New function.
4084 (process_isra_node_results): Set calls_comdat_local of callers if
4087 2020-04-02 Richard Biener <rguenther@suse.de>
4090 * common.opt (ffinite-loops): Initialize to zero.
4091 * opts.c (default_options_table): Remove OPT_ffinite_loops
4093 * cfgloop.h (loop::finite_p): New member.
4094 * cfgloopmanip.c (copy_loop_info): Copy finite_p.
4095 * ipa-icf-gimple.c (func_checker::compare_loops): Compare
4097 * lto-streamer-in.c (input_cfg): Stream finite_p.
4098 * lto-streamer-out.c (output_cfg): Likewise.
4099 * tree-cfg.c (replace_loop_annotate): Initialize finite_p
4100 from flag_finite_loops at CFG build time.
4101 * tree-ssa-loop-niter.c (finite_loop_p): Check the loops
4102 finite_p flag instead of flag_finite_loops.
4103 * doc/invoke.texi (ffinite-loops): Adjust documentation of
4106 2020-04-02 Richard Biener <rguenther@suse.de>
4109 * dwarf2out.c (dwarf2out_early_finish): Remove code emitting
4110 DW_TAG_imported_unit.
4112 2020-04-02 Maciej W. Rozycki <macro@wdc.com>
4114 * doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
4115 <riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
4118 2020-04-02 Kewen Lin <linkw@gcc.gnu.org>
4120 PR tree-optimization/94401
4121 * tree-vect-loop.c (vectorizable_load): Handle VMAT_CONTIGUOUS_REVERSE
4122 access type when loading halves of vector to avoid peeling for gaps.
4124 2020-04-02 Jakub Jelinek <jakub@redhat.com>
4126 * config/mips/mti-linux.h (SYSROOT_SUFFIX_SPEC): Add a space in
4127 between a string literal and MIPS_SYSVERSION_SPEC macro.
4129 2020-04-02 Martin Jambor <mjambor@suse.cz>
4131 * doc/invoke.texi (Optimize Options): Document sra-max-propagations.
4133 2020-04-02 Jakub Jelinek <jakub@redhat.com>
4135 PR rtl-optimization/92264
4136 * params.opt (-param=max-find-base-term-values=): Decrease default
4139 PR rtl-optimization/92264
4140 * rtl.h (struct rtx_def): Mention that call bit is used as
4141 SP_DERIVED_VALUE_P in cselib.c.
4142 * cselib.c (SP_DERIVED_VALUE_P): Define.
4143 (PRESERVED_VALUE_P, SP_BASED_VALUE_P): Move definitions earlier.
4144 (cselib_hasher::equal): Handle equality between SP_DERIVED_VALUE_P
4145 val_rtx and sp based expression where offsets cancel each other.
4146 (preserve_constants_and_equivs): Formatting fix.
4147 (cselib_reset_table): Add reverse op loc to SP_DERIVED_VALUE_P
4148 locs list for cfa_base_preserved_val if needed. Formatting fix.
4149 (autoinc_split): If the to be returned value is a REG, MEM or
4150 VALUE which has SP_DERIVED_VALUE_P + CONST_INT as one of its
4151 locs, return the SP_DERIVED_VALUE_P VALUE and adjust *off.
4152 (rtx_equal_for_cselib_1): Call autoinc_split even if both
4153 expressions are PLUS in Pmode with CONST_INT second operands.
4154 Handle SP_DERIVED_VALUE_P cases.
4155 (cselib_hash_plus_const_int): New function.
4156 (cselib_hash_rtx): Use it for PLUS in Pmode with CONST_INT
4157 second operand, as well as for PRE_DEC etc. that ought to be
4158 hashed the same way.
4159 (cselib_subst_to_values): Substitute PLUS with Pmode and
4160 CONST_INT operand if the first operand is a VALUE which has
4161 SP_DERIVED_VALUE_P + CONST_INT as one of its locs for the
4162 SP_DERIVED_VALUE_P + adjusted offset.
4163 (cselib_lookup_1): When creating a new VALUE for stack_pointer_rtx,
4164 set SP_DERIVED_VALUE_P on it. Set PRESERVED_VALUE_P when adding
4165 SP_DERIVED_VALUE_P PRESERVED_VALUE_P subseted VALUE location.
4166 * var-tracking.c (vt_initialize): Call cselib_add_permanent_equiv
4167 on the sp value before calling cselib_add_permanent_equiv on the
4169 * dse.c (check_for_inc_dec_1, check_for_inc_dec): Punt on RTX_AUTOINC
4170 in the insn without REG_INC note.
4171 (replace_read): Punt on RTX_AUTOINC in the *loc being replaced.
4172 Punt on invalid insns added by copy_to_mode_reg. Formatting fixes.
4175 * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
4176 y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.
4178 2020-04-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4181 * config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
4182 (LDRGBWBXU_Z_QUALIFIERS): Likewise.
4183 * config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
4184 intrinsic defintion by adding a new builtin call to writeback into base
4186 (__arm_vldrdq_gather_base_wb_u64): Likewise.
4187 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
4188 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
4189 (__arm_vldrwq_gather_base_wb_s32): Likewise.
4190 (__arm_vldrwq_gather_base_wb_u32): Likewise.
4191 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
4192 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
4193 (__arm_vldrwq_gather_base_wb_f32): Likewise.
4194 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
4195 * config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
4196 builtin's qualifier.
4197 (vldrdq_gather_base_wb_z_u): Likewise.
4198 (vldrwq_gather_base_wb_u): Likewise.
4199 (vldrdq_gather_base_wb_u): Likewise.
4200 (vldrwq_gather_base_wb_z_s): Likewise.
4201 (vldrwq_gather_base_wb_z_f): Likewise.
4202 (vldrdq_gather_base_wb_z_s): Likewise.
4203 (vldrwq_gather_base_wb_s): Likewise.
4204 (vldrwq_gather_base_wb_f): Likewise.
4205 (vldrdq_gather_base_wb_s): Likewise.
4206 (vldrwq_gather_base_nowb_z_u): Define builtin.
4207 (vldrdq_gather_base_nowb_z_u): Likewise.
4208 (vldrwq_gather_base_nowb_u): Likewise.
4209 (vldrdq_gather_base_nowb_u): Likewise.
4210 (vldrwq_gather_base_nowb_z_s): Likewise.
4211 (vldrwq_gather_base_nowb_z_f): Likewise.
4212 (vldrdq_gather_base_nowb_z_s): Likewise.
4213 (vldrwq_gather_base_nowb_s): Likewise.
4214 (vldrwq_gather_base_nowb_f): Likewise.
4215 (vldrdq_gather_base_nowb_s): Likewise.
4216 * config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
4218 (mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
4219 (mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
4220 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
4221 (mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
4222 (mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
4223 (mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
4224 (mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
4225 (mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
4226 (mve_vldrdq_gather_base_wb_<supf>v4di): Modify RTL pattern.
4227 (mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
4228 (mve_vldrdq_gather_base_wb_z_<supf>v4di): Modify RTL pattern.
4230 2020-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
4232 * config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
4233 ("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
4234 ("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
4235 ("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
4236 ("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
4237 ("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
4238 ("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
4239 ("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
4240 ("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
4242 ("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
4243 ("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
4244 Remove constraints from expander.
4245 * config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
4246 ("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
4247 ("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
4248 ("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
4249 ("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
4250 ("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.
4252 2020-04-01 Peter Bergner <bergner@linux.ibm.com>
4254 PR rtl-optimization/94123
4255 * lower-subreg.c (pass_lower_subreg3::gate): Remove test for
4256 flag_split_wide_types_early.
4258 2020-04-01 Joerg Sonnenberger <joerg@bec.de>
4260 * doc/extend.texi (Common Function Attributes): Fix typo.
4262 2020-04-01 Segher Boessenkool <segher@kernel.crashing.org>
4265 * config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
4268 2020-04-01 Zackery Spytz <zspytz@gmail.com>
4270 * doc/extend.texi: Fix a typo in the documentation of the
4271 copy function attribute.
4273 2020-04-01 Jakub Jelinek <jakub@redhat.com>
4276 * tree-object-size.c (pass_object_sizes::execute): Don't call
4277 replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
4278 call replace_call_with_value.
4280 2020-04-01 Kewen Lin <linkw@gcc.gnu.org>
4282 PR tree-optimization/94043
4283 * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
4284 phi for vec_lhs and use it for lane extraction.
4286 2020-03-31 Felix Yang <felix.yang@huawei.com>
4288 PR tree-optimization/94398
4289 * tree-vect-stmts.c (vectorizable_store): Instead of calling
4290 vect_supportable_dr_alignment, set alignment_support_scheme to
4291 dr_unaligned_supported for gather-scatter accesses.
4292 (vectorizable_load): Likewise.
4294 2020-03-31 Andrew Stubbs <ams@codesourcery.com>
4296 * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
4298 (vnsi, VnSI, vndi, VnDI): New mode attributes.
4299 (mov<mode>): Use <VnDI> in place of V64DI.
4300 (mov<mode>_exec): Likewise.
4301 (mov<mode>_sgprbase): Likewise.
4302 (reload_out<mode>): Likewise.
4303 (*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
4304 (gather_load<mode>v64si): Rename to ...
4305 (gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
4306 and <VnDI> in place of V64DI.
4307 (gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
4308 (gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
4309 (gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
4310 (scatter_store<mode>v64si): Rename to ...
4311 (scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4312 (scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
4313 (scatter<mode>_insn_1offset<exec_scatter>): Likewise.
4314 (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
4315 (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
4316 (ds_bpermute<mode>): Use <VnSI>.
4317 (addv64si3_vcc<exec_vcc>): Rename to ...
4318 (add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
4319 (addv64si3_vcc_dup<exec_vcc>): Rename to ...
4320 (add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
4321 (addcv64si3<exec_vcc>): Rename to ...
4322 (addc<mode>3<exec_vcc>): ... this, and use V_SI.
4323 (subv64si3_vcc<exec_vcc>): Rename to ...
4324 (sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
4325 (subcv64si3<exec_vcc>): Rename to ...
4326 (subc<mode>3<exec_vcc>): ... this, and use V_SI.
4327 (addv64di3): Rename to ...
4328 (add<mode>3): ... this, and use V_DI.
4329 (addv64di3_exec): Rename to ...
4330 (add<mode>3_exec): ... this, and use V_DI.
4331 (subv64di3): Rename to ...
4332 (sub<mode>3): ... this, and use V_DI.
4333 (subv64di3_exec): Rename to ...
4334 (sub<mode>3_exec): ... this, and use V_DI.
4335 (addv64di3_zext): Rename to ...
4336 (add<mode>3_zext): ... this, and use V_DI and <VnSI>.
4337 (addv64di3_zext_exec): Rename to ...
4338 (add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
4339 (addv64di3_zext_dup): Rename to ...
4340 (add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
4341 (addv64di3_zext_dup_exec): Rename to ...
4342 (add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
4343 (addv64di3_zext_dup2): Rename to ...
4344 (add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
4345 (addv64di3_zext_dup2_exec): Rename to ...
4346 (add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
4347 (addv64di3_sext_dup2): Rename to ...
4348 (add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
4349 (addv64di3_sext_dup2_exec): Rename to ...
4350 (add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
4351 (<su>mulv64si3_highpart<exec>): Rename to ...
4352 (<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
4353 (mulv64di3): Rename to ...
4354 (mul<mode>3): ... this, and use V_DI and <VnSI>.
4355 (mulv64di3_exec): Rename to ...
4356 (mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
4357 (mulv64di3_zext): Rename to ...
4358 (mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
4359 (mulv64di3_zext_exec): Rename to ...
4360 (mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
4361 (mulv64di3_zext_dup2): Rename to ...
4362 (mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
4363 (mulv64di3_zext_dup2_exec): Rename to ...
4364 (mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
4365 (<expander>v64di3): Rename to ...
4366 (<expander><mode>3): ... this, and use V_DI and <VnSI>.
4367 (<expander>v64di3_exec): Rename to ...
4368 (<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
4369 (<expander>v64si3<exec>): Rename to ...
4370 (<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
4371 (v<expander>v64si3<exec>): Rename to ...
4372 (v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
4373 (<expander>v64si3<exec>): Rename to ...
4374 (<expander><vnsi>3<exec>): ... this, and use V_SI.
4375 (subv64df3<exec>): Rename to ...
4376 (sub<mode>3<exec>): ... this, and use V_DF.
4377 (truncv64di<mode>2): Rename to ...
4378 (trunc<vndi><mode>2): ... this, and use <VnDI>.
4379 (truncv64di<mode>2_exec): Rename to ...
4380 (trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
4381 (<convop><mode>v64di2): Rename to ...
4382 (<convop><mode><vndi>2): ... this, and use <VnDI>.
4383 (<convop><mode>v64di2_exec): Rename to ...
4384 (<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
4385 (vec_cmp<u>v64qidi): Rename to ...
4386 (vec_cmp<u><mode>di): ... this, and use <VnSI>.
4387 (vec_cmp<u>v64qidi_exec): Rename to ...
4388 (vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
4389 (vcond_mask_<mode>di): Use <VnDI>.
4390 (maskload<mode>di): Likewise.
4391 (maskstore<mode>di): Likewise.
4392 (mask_gather_load<mode>v64si): Rename to ...
4393 (mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4394 (mask_scatter_store<mode>v64si): Rename to ...
4395 (mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
4396 (*<reduc_op>_dpp_shr_v64di): Rename to ...
4397 (*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
4398 (*plus_carry_in_dpp_shr_v64si): Rename to ...
4399 (*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
4400 (*plus_carry_dpp_shr_v64di): Rename to ...
4401 (*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
4402 (vec_seriesv64si): Rename to ...
4403 (vec_series<mode>): ... this, and use V_SI.
4404 (vec_seriesv64di): Rename to ...
4405 (vec_series<mode>): ... this, and use V_DI.
4407 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
4409 * config/arc/arc.c (arc_print_operand): Use
4410 HOST_WIDE_INT_PRINT_DEC macro.
4412 2020-03-31 Claudiu Zissulescu <claziss@synopsys.com>
4414 * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
4416 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4418 * config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
4420 (__arm_vbicq): Likewise.
4422 2020-03-31 Vineet Gupta <vgupta@synopsys.com>
4424 * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
4426 2020-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4428 * config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
4429 common section of both MVE Integer and MVE Floating Point.
4431 (vaddlvq_p): Likewise.
4432 (vaddvaq): Likewise.
4433 (vaddvq_p): Likewise.
4434 (vcmpcsq): Likewise.
4435 (vmlsdavxq): Likewise.
4436 (vmlsdavq): Likewise.
4437 (vmladavxq): Likewise.
4438 (vmladavq): Likewise.
4440 (vminavq): Likewise.
4442 (vmaxavq): Likewise.
4443 (vmlaldavq): Likewise.
4444 (vcmphiq): Likewise.
4445 (vaddlvaq): Likewise.
4446 (vrmlaldavhq): Likewise.
4447 (vrmlaldavhxq): Likewise.
4448 (vrmlsldavhq): Likewise.
4449 (vrmlsldavhxq): Likewise.
4450 (vmlsldavxq): Likewise.
4451 (vmlsldavq): Likewise.
4453 (vrmlaldavhaq): Likewise.
4454 (vcmpgeq_m_n): Likewise.
4455 (vmlsdavxq_p): Likewise.
4456 (vmlsdavq_p): Likewise.
4457 (vmlsdavaxq): Likewise.
4458 (vmlsdavaq): Likewise.
4459 (vaddvaq_p): Likewise.
4460 (vcmpcsq_m_n): Likewise.
4461 (vcmpcsq_m): Likewise.
4462 (vmladavxq_p): Likewise.
4463 (vmladavq_p): Likewise.
4464 (vmladavaxq): Likewise.
4465 (vmladavaq): Likewise.
4466 (vminvq_p): Likewise.
4467 (vminavq_p): Likewise.
4468 (vmaxvq_p): Likewise.
4469 (vmaxavq_p): Likewise.
4470 (vcmphiq_m): Likewise.
4471 (vaddlvaq_p): Likewise.
4472 (vmlaldavaq): Likewise.
4473 (vmlaldavaxq): Likewise.
4474 (vmlaldavq_p): Likewise.
4475 (vmlaldavxq_p): Likewise.
4476 (vmlsldavaq): Likewise.
4477 (vmlsldavaxq): Likewise.
4478 (vmlsldavq_p): Likewise.
4479 (vmlsldavxq_p): Likewise.
4480 (vrmlaldavhaxq): Likewise.
4481 (vrmlaldavhq_p): Likewise.
4482 (vrmlaldavhxq_p): Likewise.
4483 (vrmlsldavhaq): Likewise.
4484 (vrmlsldavhaxq): Likewise.
4485 (vrmlsldavhq_p): Likewise.
4486 (vrmlsldavhxq_p): Likewise.
4487 (vabavq_p): Likewise.
4488 (vmladavaq_p): Likewise.
4489 (vstrbq_scatter_offset): Likewise.
4490 (vstrbq_p): Likewise.
4491 (vstrbq_scatter_offset_p): Likewise.
4492 (vstrdq_scatter_base_p): Likewise.
4493 (vstrdq_scatter_base): Likewise.
4494 (vstrdq_scatter_offset_p): Likewise.
4495 (vstrdq_scatter_offset): Likewise.
4496 (vstrdq_scatter_shifted_offset_p): Likewise.
4497 (vstrdq_scatter_shifted_offset): Likewise.
4498 (vmaxq_x): Likewise.
4499 (vminq_x): Likewise.
4500 (vmovlbq_x): Likewise.
4501 (vmovltq_x): Likewise.
4502 (vmulhq_x): Likewise.
4503 (vmullbq_int_x): Likewise.
4504 (vmullbq_poly_x): Likewise.
4505 (vmulltq_int_x): Likewise.
4506 (vmulltq_poly_x): Likewise.
4509 2020-03-31 Jakub Jelinek <jakub@redhat.com>
4512 * config/aarch64/constraints.md (Uph): New constraint.
4513 * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
4514 (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
4517 2020-03-31 Marc Glisse <marc.glisse@inria.fr>
4518 Jakub Jelinek <jakub@redhat.com>
4521 * fold-const.c (fold_binary_loc) <case TRUNC_DIV_EXPR>: Use
4522 ANY_INTEGRAL_TYPE_P instead of INTEGRAL_TYPE_P.
4524 2020-03-31 Jakub Jelinek <jakub@redhat.com>
4526 PR tree-optimization/94403
4527 * gimple-ssa-store-merging.c (verify_symbolic_number_p): Allow also
4528 ENUMERAL_TYPE lhs_type.
4530 PR rtl-optimization/94344
4531 * tree-ssa-forwprop.c (simplify_rotate): Handle also same precision
4532 conversions, either on both operands of |^+ or just one. Handle
4533 also extra same precision conversion on RSHIFT_EXPR first operand
4534 provided RSHIFT_EXPR is performed in unsigned type.
4536 2020-03-30 David Malcolm <dmalcolm@redhat.com>
4538 * lra.c (finish_insn_code_data_once): Set the array elements
4539 to NULL after freeing them.
4541 2020-03-30 Andreas Schwab <schwab@suse.de>
4543 * config/host-linux.c (TRY_EMPTY_VM_SPACE) [__riscv && __LP64__]:
4546 2020-03-30 Will Schmidt <will_schmidt@vnet.ibm.com>
4548 * config/rs6000/rs6000-call.c altivec_init_builtins(): Remove code
4549 to skip defining builtins based on builtin_mask.
4551 2020-03-30 Jakub Jelinek <jakub@redhat.com>
4554 * config/i386/sse.md (<mask_codefor>one_cmpl<mode>2<mask_name>): If
4555 !TARGET_AVX512VL, use 512-bit vpternlog and make sure the input
4556 operand is a register. Don't enable masked variants for V*[QH]Imode.
4559 * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
4560 <store_mask_constraint> instead of m in output operand constraint.
4561 (vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
4564 2020-03-30 Alan Modra <amodra@gmail.com>
4566 * config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.
4567 (rs6000_indirect_call_template_1): Adjust to suit.
4568 * config/rs6000/rs6000.md (call_local): Merge call_local32,
4569 call_local64, and call_local_aix.
4570 (call_value_local): Simlarly.
4571 (call_nonlocal_aix, call_value_nonlocal_aix): Adjust rtl to suit,
4572 and disable pattern when CALL_LONG.
4573 (call_indirect_aix, call_value_indirect_aix): Adjust rtl.
4574 (call_indirect_elfv2, call_indirect_pcrel): Likewise.
4575 (call_value_indirect_elfv2, call_value_indirect_pcrel): Likewise.
4577 2020-03-29 H.J. Lu <hongjiu.lu@intel.com>
4580 * doc/invoke.texi: Update -falign-functions, -falign-loops and
4581 -falign-jumps documentation.
4583 2020-03-29 Martin Liska <mliska@suse.cz>
4586 * cgraphunit.c (process_function_and_variable_attributes): Remove
4587 double 'attribute' words.
4589 2020-03-29 John David Anglin <dave.anglin@bell.net>
4591 * config/pa/pa.c (pa_asm_output_aligned_bss): Delete duplicate
4594 2020-03-28 Jakub Jelinek <jakub@redhat.com>
4597 * c-decl.c (grokdeclarator): After issuing errors, set size_int_const
4598 to true after setting size to integer_one_node.
4600 PR tree-optimization/94329
4601 * tree-ssa-reassoc.c (reassociate_bb): When calling reassoc_remove_stmt
4602 on the last stmt in a bb, make sure gsi_prev isn't done immediately
4605 2020-03-27 Alan Modra <amodra@gmail.com>
4608 * config/rs6000/rs6000.c (rs6000_longcall_ref): Use unspec_volatile
4609 for PLT16_LO and PLT_PCREL.
4610 * config/rs6000/rs6000.md (UNSPEC_PLT16_LO, UNSPEC_PLT_PCREL): Remove.
4611 (UNSPECV_PLT16_LO, UNSPECV_PLT_PCREL): Define.
4612 (pltseq_plt16_lo_, pltseq_plt_pcrel): Use unspec_volatile.
4614 2020-03-27 Martin Sebor <msebor@redhat.com>
4617 * calls.c (init_attr_rdwr_indices): Iterate over all access attributes.
4619 2020-03-27 Andrew Stubbs <ams@codesourcery.com>
4621 * config/gcn/gcn-valu.md:
4622 (VEC_SUBDWORD_MODE): Rename to V_QIHI throughout.
4623 (VEC_1REG_MODE): Delete.
4624 (VEC_1REG_ALT): Delete.
4625 (VEC_ALL1REG_MODE): Rename to V_1REG throughout.
4626 (VEC_1REG_INT_MODE): Delete.
4627 (VEC_ALL1REG_INT_MODE): Rename to V_INT_1REG throughout.
4628 (VEC_ALL1REG_INT_ALT): Rename to V_INT_1REG_ALT throughout.
4629 (VEC_2REG_MODE): Rename to V_2REG throughout.
4630 (VEC_REG_MODE): Rename to V_noHI throughout.
4631 (VEC_ALLREG_MODE): Rename to V_ALL throughout.
4632 (VEC_ALLREG_ALT): Rename to V_ALL_ALT throughout.
4633 (VEC_ALLREG_INT_MODE): Rename to V_INT throughout.
4634 (VEC_INT_MODE): Delete.
4635 (VEC_FP_MODE): Rename to V_FP throughout and move to top.
4636 (VEC_FP_1REG_MODE): Rename to V_FP_1REG throughout and move to top.
4637 (FP_MODE): Delete and replace with FP throughout.
4638 (FP_1REG_MODE): Delete and replace with FP_1REG throughout.
4639 (VCMP_MODE): Rename to V_noQI throughout and move to top.
4640 (VCMP_MODE_INT): Rename to V_INT_noQI throughout and move to top.
4641 * config/gcn/gcn.md (FP): New mode iterator.
4642 (FP_1REG): New mode iterator.
4644 2020-03-27 David Malcolm <dmalcolm@redhat.com>
4646 * doc/invoke.texi (-fdump-analyzer-supergraph): Document that this
4647 now emits two .dot files.
4648 * graphviz.cc (graphviz_out::begin_tr): Only emit a TR, not a TD.
4649 (graphviz_out::end_tr): Only close a TR, not a TD.
4650 (graphviz_out::begin_td): New.
4651 (graphviz_out::end_td): New.
4652 (graphviz_out::begin_trtd): New, replacing the old implementation
4653 of graphviz_out::begin_tr.
4654 (graphviz_out::end_tdtr): New, replacing the old implementation
4655 of graphviz_out::end_tr.
4656 * graphviz.h (graphviz_out::begin_td): New decl.
4657 (graphviz_out::end_td): New decl.
4658 (graphviz_out::begin_trtd): New decl.
4659 (graphviz_out::end_tdtr): New decl.
4661 2020-03-27 Richard Biener <rguenther@suse.de>
4664 * dwarf2out.c (should_emit_struct_debug): Return false for
4667 2020-03-27 Richard Biener <rguenther@suse.de>
4669 PR tree-optimization/94352
4670 * tree-ssa-propagate.c (ssa_prop_init): Move seeding of the
4672 (ssa_propagation_engine::ssa_propagate): ... here after
4673 initializing curr_order.
4675 2020-03-27 Kewen Lin <linkw@gcc.gnu.org>
4677 PR tree-optimization/90332
4678 * tree-vect-stmts.c (vector_vector_composition_type): New function.
4679 (get_group_load_store_type): Adjust to call
4680 vector_vector_composition_type, extend it to construct with scalar
4682 (vectorizable_load): Likewise.
4684 2020-03-27 Roman Zhuykov <zhroma@ispras.ru>
4686 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove assertions.
4687 (create_ddg_dep_no_link): Likewise.
4688 (add_cross_iteration_register_deps): Move debug instruction check.
4689 Other minor refactoring.
4690 (add_intra_loop_mem_dep): Do not check for debug instructions.
4691 (add_inter_loop_mem_dep): Likewise.
4692 (build_intra_loop_deps): Likewise.
4693 (create_ddg): Do not include debug insns into the graph.
4694 * ddg.h (struct ddg): Remove num_debug field.
4695 * modulo-sched.c (doloop_register_get): Adjust condition.
4696 (res_MII): Remove DDG num_debug field usage.
4697 (sms_schedule_by_order): Use assertion against debug insns.
4698 (ps_has_conflicts): Drop debug insn check.
4700 2020-03-26 Jakub Jelinek <jakub@redhat.com>
4703 * tree.c (protected_set_expr_location): Recurse on STATEMENT_LIST
4704 that contains exactly one non-DEBUG_BEGIN_STMT statement.
4707 * gimple.h (gimple_seq_first_nondebug_stmt): New function.
4708 (gimple_seq_last_nondebug_stmt): Don't return NULL if seq contains
4709 a single non-debug stmt followed by one or more debug stmts.
4710 * gimplify.c (gimplify_body): Use gimple_seq_first_nondebug_stmt
4711 instead of gimple_seq_first_stmt, use gimple_seq_first_nondebug_stmt
4712 and gimple_seq_last_nondebug_stmt instead of gimple_seq_first and
4713 gimple_seq_last to check if outer_stmt gbind could be reused and
4714 if yes and it is surrounded by any debug stmts, move them into the
4717 PR rtl-optimization/92264
4718 * var-tracking.c (add_stores): Call cselib_set_value_sp_based even
4719 for sp based values in !frame_pointer_needed
4720 && !ACCUMULATE_OUTGOING_ARGS functions.
4722 2020-03-26 Felix Yang <felix.yang@huawei.com>
4724 PR tree-optimization/94269
4725 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Restrict
4727 operation to single basic block.
4729 2020-03-25 Jeff Law <law@redhat.com>
4731 PR rtl-optimization/90275
4732 * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
4735 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4738 * config/arm/arm.c (arm_gen_dicompare_reg): Set mode of COMPARE to
4739 mode rather than VOIDmode.
4741 2020-03-25 Martin Sebor <msebor@redhat.com>
4744 * gimple-ssa-warn-alloca.c (pass_walloca::execute): Issue warnings
4745 even for alloca calls resulting from system macro expansion.
4746 Include inlining context in all warnings.
4748 2020-03-25 Richard Sandiford <richard.sandiford@arm.com>
4751 * config/rs6000/rs6000.c (rs6000_can_change_mode_class): Allow
4752 FPRs to change between SDmode and DDmode.
4754 2020-03-25 Martin Sebor <msebor@redhat.com>
4756 PR tree-optimization/94131
4757 * gimple-fold.c (get_range_strlen_tree): Fail for variable-length
4759 * tree-ssa-strlen.c (get_range_strlen_dynamic): Avoid assuming
4760 types have constant sizes.
4762 2020-03-25 Martin Liska <mliska@suse.cz>
4765 * configure.ac: Report error only when --with-zstd
4767 * configure: Regenerate.
4769 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4772 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
4773 INSN_CODE (insn) to -1 when changing the pattern.
4775 2020-03-25 Martin Liska <mliska@suse.cz>
4779 * config/i386/i386-features.c (make_resolver_func): Drop
4780 public flag for resolver.
4781 * config/rs6000/rs6000.c (make_resolver_func): Add comdat
4782 group for resolver and drop public flag if possible.
4783 * multiple_target.c (create_dispatcher_calls): Drop unique_name
4784 and resolution as we want to enable LTO privatization of the default
4787 2020-03-25 Martin Liska <mliska@suse.cz>
4790 * configure.ac: Respect --without-zstd and report
4791 error when we can't find header file with --with-zstd.
4792 * configure: Regenerate.
4794 2020-03-25 Jakub Jelinek <jakub@redhat.com>
4797 * varasm.c (output_constructor_array_range): If local->index
4798 RANGE_EXPR doesn't start at the current location in the constructor,
4799 skip needed number of bytes using assemble_zeros or assert we don't
4803 * langhooks.c (lhd_set_decl_assembler_name): Use a static ulong
4804 counter instead of DECL_UID.
4806 PR tree-optimization/94300
4807 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): If pd.offset
4808 is positive, make sure that off + size isn't larger than needed_len.
4810 2020-03-25 Richard Biener <rguenther@suse.de>
4811 Jakub Jelinek <jakub@redhat.com>
4814 * tree-if-conv.c (ifcvt_local_dce): Delete dead statements backwards.
4816 2020-03-24 Christophe Lyon <christophe.lyon@linaro.org>
4818 * doc/sourcebuild.texi (ARM-specific attributes): Add
4820 (Features for dg-add-options): Add arm_fp_dp.
4822 2020-03-24 John David Anglin <danglin@gcc.gnu.org>
4825 * config/pa/pa.h (TARGET_CPU_CPP_BUILTINS): Define __BIG_ENDIAN__.
4827 2020-03-24 Tobias Burnus <tobias@codesourcery.com>
4830 * omp-offload.c (omp_finish_file): Fix target-link handling if
4831 targetm_common.have_named_sections is false.
4833 2020-03-24 Jakub Jelinek <jakub@redhat.com>
4836 * config/arm/arm.md (subvdi4, usubvsi4, usubvdi4): Use gen_int_mode
4840 * tree-ssa-loop-manip.c (create_iv): If after, set stmt location to
4841 e->goto_locus even if gsi_bb (*incr_pos) contains only debug stmts.
4842 If not after and at *incr_pos is a debug stmt, set stmt location to
4843 location of next non-debug stmt after it if any.
4846 * tree-if-conv.c (ifcvt_local_dce): For gimple debug stmts, just set
4847 GF_PLF_2, but don't add them to worklist. Don't add an assigment to
4848 worklist or set GF_PLF_2 just because it is used in a debug stmt in
4849 another bb. Formatting improvements.
4852 * cgraphunit.c (check_global_declaration): For DECL_EXTERNAL and
4853 non-TREE_PUBLIC non-DECL_ARTIFICIAL FUNCTION_DECLs, set TREE_PUBLIC
4854 regardless of whether TREE_NO_WARNING is set on it or whether
4855 warn_unused_function is true or not.
4857 2020-03-23 Jeff Law <law@redhat.com>
4859 PR rtl-optimization/90275
4862 * simplify-rtx.c (comparison_code_valid_for_mode): New function.
4863 (simplify_logical_relational_operation): Use it.
4865 2020-03-23 Jakub Jelinek <jakub@redhat.com>
4868 * tree.c (get_narrower): Handle COMPOUND_EXPR by recursing on
4869 ultimate rhs and if returned something different, reconstructing
4872 2020-03-23 Lewis Hyatt <lhyatt@gmail.com>
4874 * opts.c (print_filtered_help): Improve the help text for alias options.
4876 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4877 Andre Vieira <andre.simoesdiasvieira@arm.com>
4878 Mihail Ionescu <mihail.ionescu@arm.com>
4880 * config/arm/arm_mve.h (vshlcq_m_s8): Define macro.
4881 (vshlcq_m_u8): Likewise.
4882 (vshlcq_m_s16): Likewise.
4883 (vshlcq_m_u16): Likewise.
4884 (vshlcq_m_s32): Likewise.
4885 (vshlcq_m_u32): Likewise.
4886 (__arm_vshlcq_m_s8): Define intrinsic.
4887 (__arm_vshlcq_m_u8): Likewise.
4888 (__arm_vshlcq_m_s16): Likewise.
4889 (__arm_vshlcq_m_u16): Likewise.
4890 (__arm_vshlcq_m_s32): Likewise.
4891 (__arm_vshlcq_m_u32): Likewise.
4892 (vshlcq_m): Define polymorphic variant.
4893 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_UNONE_IMM_UNONE):
4894 Use builtin qualifier.
4895 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
4896 * config/arm/mve.md (mve_vshlcq_m_vec_<supf><mode>): Define RTL pattern.
4897 (mve_vshlcq_m_carry_<supf><mode>): Likewise.
4898 (mve_vshlcq_m_<supf><mode>): Likewise.
4900 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4902 * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier.
4903 (UQSHL_QUALIFIERS): Likewise.
4904 (ASRL_QUALIFIERS): Likewise.
4905 (SQSHL_QUALIFIERS): Likewise.
4906 * config/arm/arm_mve.h (__ARM_BIG_ENDIAN): Check to not support MVE in
4908 (sqrshr): Define macro.
4909 (sqrshrl): Likewise.
4910 (sqrshrl_sat48): Likewise.
4916 (uqrshll): Likewise.
4917 (uqrshll_sat48): Likewise.
4924 (__arm_lsll): Define intrinsic.
4925 (__arm_asrl): Likewise.
4926 (__arm_uqrshll): Likewise.
4927 (__arm_uqrshll_sat48): Likewise.
4928 (__arm_sqrshrl): Likewise.
4929 (__arm_sqrshrl_sat48): Likewise.
4930 (__arm_uqshll): Likewise.
4931 (__arm_urshrl): Likewise.
4932 (__arm_srshrl): Likewise.
4933 (__arm_sqshll): Likewise.
4934 (__arm_uqrshl): Likewise.
4935 (__arm_sqrshr): Likewise.
4936 (__arm_uqshl): Likewise.
4937 (__arm_urshr): Likewise.
4938 (__arm_sqshl): Likewise.
4939 (__arm_srshr): Likewise.
4940 * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin
4942 (UQSHL_QUALIFIERS): Likewise.
4943 (ASRL_QUALIFIERS): Likewise.
4944 (SQSHL_QUALIFIERS): Likewise.
4945 * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern.
4946 (mve_sqrshrl_sat<supf>_di): Likewise.
4947 (mve_uqrshl_si): Likewise.
4948 (mve_sqrshr_si): Likewise.
4949 (mve_uqshll_di): Likewise.
4950 (mve_urshrl_di): Likewise.
4951 (mve_uqshl_si): Likewise.
4952 (mve_urshr_si): Likewise.
4953 (mve_sqshl_si): Likewise.
4954 (mve_srshr_si): Likewise.
4955 (mve_srshrl_di): Likewise.
4956 (mve_sqshll_di): Likewise.
4958 2020-03-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
4959 Andre Vieira <andre.simoesdiasvieira@arm.com>
4960 Mihail Ionescu <mihail.ionescu@arm.com>
4962 * config/arm/arm_mve.h (vsetq_lane_f16): Define macro.
4963 (vsetq_lane_f32): Likewise.
4964 (vsetq_lane_s16): Likewise.
4965 (vsetq_lane_s32): Likewise.
4966 (vsetq_lane_s8): Likewise.
4967 (vsetq_lane_s64): Likewise.
4968 (vsetq_lane_u8): Likewise.
4969 (vsetq_lane_u16): Likewise.
4970 (vsetq_lane_u32): Likewise.
4971 (vsetq_lane_u64): Likewise.
4972 (vgetq_lane_f16): Likewise.
4973 (vgetq_lane_f32): Likewise.
4974 (vgetq_lane_s16): Likewise.
4975 (vgetq_lane_s32): Likewise.
4976 (vgetq_lane_s8): Likewise.
4977 (vgetq_lane_s64): Likewise.
4978 (vgetq_lane_u8): Likewise.
4979 (vgetq_lane_u16): Likewise.
4980 (vgetq_lane_u32): Likewise.
4981 (vgetq_lane_u64): Likewise.
4982 (__ARM_NUM_LANES): Likewise.
4983 (__ARM_LANEQ): Likewise.
4984 (__ARM_CHECK_LANEQ): Likewise.
4985 (__arm_vsetq_lane_s16): Define intrinsic.
4986 (__arm_vsetq_lane_s32): Likewise.
4987 (__arm_vsetq_lane_s8): Likewise.
4988 (__arm_vsetq_lane_s64): Likewise.
4989 (__arm_vsetq_lane_u8): Likewise.
4990 (__arm_vsetq_lane_u16): Likewise.
4991 (__arm_vsetq_lane_u32): Likewise.
4992 (__arm_vsetq_lane_u64): Likewise.
4993 (__arm_vgetq_lane_s16): Likewise.
4994 (__arm_vgetq_lane_s32): Likewise.
4995 (__arm_vgetq_lane_s8): Likewise.
4996 (__arm_vgetq_lane_s64): Likewise.
4997 (__arm_vgetq_lane_u8): Likewise.
4998 (__arm_vgetq_lane_u16): Likewise.
4999 (__arm_vgetq_lane_u32): Likewise.
5000 (__arm_vgetq_lane_u64): Likewise.
5001 (__arm_vsetq_lane_f16): Likewise.
5002 (__arm_vsetq_lane_f32): Likewise.
5003 (__arm_vgetq_lane_f16): Likewise.
5004 (__arm_vgetq_lane_f32): Likewise.
5005 (vgetq_lane): Define polymorphic variant.
5006 (vsetq_lane): Likewise.
5007 * config/arm/mve.md (mve_vec_extract<mode><V_elem_l>): Define RTL
5009 (mve_vec_extractv2didi): Likewise.
5010 (mve_vec_extract_sext_internal<mode>): Likewise.
5011 (mve_vec_extract_zext_internal<mode>): Likewise.
5012 (mve_vec_set<mode>_internal): Likewise.
5013 (mve_vec_setv2di_internal): Likewise.
5014 * config/arm/neon.md (vec_set<mode>): Move RTL pattern to vec-common.md
5016 (vec_extract<mode><V_elem_l>): Rename to
5017 "neon_vec_extract<mode><V_elem_l>".
5018 (vec_extractv2didi): Rename to "neon_vec_extractv2didi".
5019 * config/arm/vec-common.md (vec_extract<mode><V_elem_l>): Define RTL
5020 pattern common for MVE and NEON.
5021 (vec_set<mode>): Move RTL pattern from neon.md and modify to accept both
5024 2020-03-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
5026 * config/arm/mve.md (earlyclobber_32): New mode attribute.
5027 (mve_vrev64q_*, mve_vcaddq*, mve_vhcaddq_*, mve_vcmulq_*,
5028 mve_vmull[bt]q_*, mve_vqdmull[bt]q_*): Add appropriate early clobbers.
5030 2020-03-23 Richard Biener <rguenther@suse.de>
5032 PR tree-optimization/94261
5033 * tree-vect-slp.c (vect_get_and_check_slp_defs): Remove
5034 IL operand swapping code.
5035 (vect_slp_rearrange_stmts): Do not arrange isomorphic
5036 nodes that would need operation code adjustments.
5038 2020-03-23 Tobias Burnus <tobias@codesourcery.com>
5040 * doc/install.texi (amdgcn-*-amdhsa): Renamed
5041 from amdgcn-unknown-amdhsa; change
5042 amdgcn-unknown-amdhsa to amdgcn-amdhsa.
5044 2020-03-23 Richard Biener <rguenther@suse.de>
5047 * ipa-prop.c (ipa_read_jump_function): Build the ADDR_EXRP
5048 directly rather than also folding it via build_fold_addr_expr.
5050 2020-03-23 Richard Biener <rguenther@suse.de>
5052 PR tree-optimization/94266
5053 * tree-ssa-forwprop.c (pass_forwprop::execute): Do not propagate
5054 addresses of TARGET_MEM_REFs.
5056 2020-03-23 Martin Liska <mliska@suse.cz>
5059 * symtab.c (symtab_node::clone_references): Save speculative_id
5060 as ref may be overwritten by create_reference.
5061 (symtab_node::clone_referring): Likewise.
5062 (symtab_node::clone_reference): Likewise.
5064 2020-03-22 Iain Sandoe <iain@sandoe.co.uk>
5066 * config/i386/darwin.h (JUMP_TABLES_IN_TEXT_SECTION): Remove
5067 references to Darwin.
5068 * config/i386/i386.h (JUMP_TABLES_IN_TEXT_SECTION): Define this
5069 unconditionally and comment on why.
5071 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
5073 * config/darwin.c (darwin_mergeable_constant_section): Collect
5074 section anchor checks into the caller.
5075 (machopic_select_section): Collect section anchor checks into
5076 the determination of 'effective zero-size' objects. When the
5077 size is unknown, assume it is non-zero, and thus return the
5078 'generic' section for the DECL.
5080 2020-03-21 Iain Sandoe <iain@sandoe.co.uk>
5083 * config/darwin.opt: Amend options descriptions.
5085 2020-03-21 Richard Sandiford <richard.sandiford@arm.com>
5087 PR rtl-optimization/94052
5088 * lra-constraints.c (simplify_operand_subreg): Reload the inner
5089 register of a paradoxical subreg if simplify_subreg_regno fails
5090 to give a valid hard register for the outer mode.
5092 2020-03-20 Martin Jambor <mjambor@suse.cz>
5094 PR tree-optimization/93435
5095 * params.opt (sra-max-propagations): New parameter.
5096 * tree-sra.c (propagation_budget): New variable.
5097 (budget_for_propagation_access): New function.
5098 (propagate_subaccesses_from_rhs): Use it.
5099 (propagate_subaccesses_from_lhs): Likewise.
5100 (propagate_all_subaccesses): Set up and destroy propagation_budget.
5102 2020-03-20 Carl Love <cel@us.ibm.com>
5105 * config/rs6000/rs6000.c (rs6000_option_override_internal):
5106 Add check for TARGET_FPRND for Power 7 or newer.
5108 2020-03-20 Jan Hubicka <hubicka@ucw.cz>
5111 * cgraph.c (symbol_table::create_edge): Update calls_comdat_local flag.
5112 (cgraph_edge::redirect_callee): Move here; likewise.
5113 (cgraph_node::remove_callees): Update calls_comdat_local flag.
5114 (cgraph_node::verify_node): Verify that calls_comdat_local flag match
5116 (cgraph_node::check_calls_comdat_local_p): New member function.
5117 * cgraph.h (cgraph_node::check_calls_comdat_local_p): Declare.
5118 (cgraph_edge::redirect_callee): Move offline.
5119 * ipa-fnsummary.c (compute_fn_summary): Do not compute
5120 calls_comdat_local flag here.
5121 * ipa-inline-transform.c (inline_call): Fix updating of
5122 calls_comdat_local flag.
5123 * ipa-split.c (split_function): Use true instead of 1 to set the flag.
5124 * symtab.c (symtab_node::add_to_same_comdat_group): Update
5125 calls_comdat_local flag.
5127 2020-03-20 Richard Biener <rguenther@suse.de>
5129 * tree-vect-slp.c (vect_analyze_slp_instance): Dump SLP tree
5130 from the possibly modified root.
5132 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5133 Andre Vieira <andre.simoesdiasvieira@arm.com>
5134 Mihail Ionescu <mihail.ionescu@arm.com>
5136 * config/arm/arm_mve.h (vst1q_p_u8): Define macro.
5137 (vst1q_p_s8): Likewise.
5138 (vst2q_s8): Likewise.
5139 (vst2q_u8): Likewise.
5140 (vld1q_z_u8): Likewise.
5141 (vld1q_z_s8): Likewise.
5142 (vld2q_s8): Likewise.
5143 (vld2q_u8): Likewise.
5144 (vld4q_s8): Likewise.
5145 (vld4q_u8): Likewise.
5146 (vst1q_p_u16): Likewise.
5147 (vst1q_p_s16): Likewise.
5148 (vst2q_s16): Likewise.
5149 (vst2q_u16): Likewise.
5150 (vld1q_z_u16): Likewise.
5151 (vld1q_z_s16): Likewise.
5152 (vld2q_s16): Likewise.
5153 (vld2q_u16): Likewise.
5154 (vld4q_s16): Likewise.
5155 (vld4q_u16): Likewise.
5156 (vst1q_p_u32): Likewise.
5157 (vst1q_p_s32): Likewise.
5158 (vst2q_s32): Likewise.
5159 (vst2q_u32): Likewise.
5160 (vld1q_z_u32): Likewise.
5161 (vld1q_z_s32): Likewise.
5162 (vld2q_s32): Likewise.
5163 (vld2q_u32): Likewise.
5164 (vld4q_s32): Likewise.
5165 (vld4q_u32): Likewise.
5166 (vld4q_f16): Likewise.
5167 (vld2q_f16): Likewise.
5168 (vld1q_z_f16): Likewise.
5169 (vst2q_f16): Likewise.
5170 (vst1q_p_f16): Likewise.
5171 (vld4q_f32): Likewise.
5172 (vld2q_f32): Likewise.
5173 (vld1q_z_f32): Likewise.
5174 (vst2q_f32): Likewise.
5175 (vst1q_p_f32): Likewise.
5176 (__arm_vst1q_p_u8): Define intrinsic.
5177 (__arm_vst1q_p_s8): Likewise.
5178 (__arm_vst2q_s8): Likewise.
5179 (__arm_vst2q_u8): Likewise.
5180 (__arm_vld1q_z_u8): Likewise.
5181 (__arm_vld1q_z_s8): Likewise.
5182 (__arm_vld2q_s8): Likewise.
5183 (__arm_vld2q_u8): Likewise.
5184 (__arm_vld4q_s8): Likewise.
5185 (__arm_vld4q_u8): Likewise.
5186 (__arm_vst1q_p_u16): Likewise.
5187 (__arm_vst1q_p_s16): Likewise.
5188 (__arm_vst2q_s16): Likewise.
5189 (__arm_vst2q_u16): Likewise.
5190 (__arm_vld1q_z_u16): Likewise.
5191 (__arm_vld1q_z_s16): Likewise.
5192 (__arm_vld2q_s16): Likewise.
5193 (__arm_vld2q_u16): Likewise.
5194 (__arm_vld4q_s16): Likewise.
5195 (__arm_vld4q_u16): Likewise.
5196 (__arm_vst1q_p_u32): Likewise.
5197 (__arm_vst1q_p_s32): Likewise.
5198 (__arm_vst2q_s32): Likewise.
5199 (__arm_vst2q_u32): Likewise.
5200 (__arm_vld1q_z_u32): Likewise.
5201 (__arm_vld1q_z_s32): Likewise.
5202 (__arm_vld2q_s32): Likewise.
5203 (__arm_vld2q_u32): Likewise.
5204 (__arm_vld4q_s32): Likewise.
5205 (__arm_vld4q_u32): Likewise.
5206 (__arm_vld4q_f16): Likewise.
5207 (__arm_vld2q_f16): Likewise.
5208 (__arm_vld1q_z_f16): Likewise.
5209 (__arm_vst2q_f16): Likewise.
5210 (__arm_vst1q_p_f16): Likewise.
5211 (__arm_vld4q_f32): Likewise.
5212 (__arm_vld2q_f32): Likewise.
5213 (__arm_vld1q_z_f32): Likewise.
5214 (__arm_vst2q_f32): Likewise.
5215 (__arm_vst1q_p_f32): Likewise.
5216 (vld1q_z): Define polymorphic variant.
5219 (vst1q_p): Likewise.
5221 * config/arm/arm_mve_builtins.def (STORE1): Use builtin qualifier.
5223 * config/arm/mve.md (mve_vst2q<mode>): Define RTL pattern.
5224 (mve_vld2q<mode>): Likewise.
5225 (mve_vld4q<mode>): Likewise.
5227 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5228 Andre Vieira <andre.simoesdiasvieira@arm.com>
5229 Mihail Ionescu <mihail.ionescu@arm.com>
5231 * config/arm/arm-builtins.c (ARM_BUILTIN_GET_FPSCR_NZCVQC): Define.
5232 (ARM_BUILTIN_SET_FPSCR_NZCVQC): Likewise.
5233 (arm_init_mve_builtins): Add "__builtin_arm_get_fpscr_nzcvqc" and
5234 "__builtin_arm_set_fpscr_nzcvqc" to arm_builtin_decls array.
5235 (arm_expand_builtin): Define case ARM_BUILTIN_GET_FPSCR_NZCVQC
5236 and ARM_BUILTIN_SET_FPSCR_NZCVQC.
5237 * config/arm/arm_mve.h (vadciq_s32): Define macro.
5238 (vadciq_u32): Likewise.
5239 (vadciq_m_s32): Likewise.
5240 (vadciq_m_u32): Likewise.
5241 (vadcq_s32): Likewise.
5242 (vadcq_u32): Likewise.
5243 (vadcq_m_s32): Likewise.
5244 (vadcq_m_u32): Likewise.
5245 (vsbciq_s32): Likewise.
5246 (vsbciq_u32): Likewise.
5247 (vsbciq_m_s32): Likewise.
5248 (vsbciq_m_u32): Likewise.
5249 (vsbcq_s32): Likewise.
5250 (vsbcq_u32): Likewise.
5251 (vsbcq_m_s32): Likewise.
5252 (vsbcq_m_u32): Likewise.
5253 (__arm_vadciq_s32): Define intrinsic.
5254 (__arm_vadciq_u32): Likewise.
5255 (__arm_vadciq_m_s32): Likewise.
5256 (__arm_vadciq_m_u32): Likewise.
5257 (__arm_vadcq_s32): Likewise.
5258 (__arm_vadcq_u32): Likewise.
5259 (__arm_vadcq_m_s32): Likewise.
5260 (__arm_vadcq_m_u32): Likewise.
5261 (__arm_vsbciq_s32): Likewise.
5262 (__arm_vsbciq_u32): Likewise.
5263 (__arm_vsbciq_m_s32): Likewise.
5264 (__arm_vsbciq_m_u32): Likewise.
5265 (__arm_vsbcq_s32): Likewise.
5266 (__arm_vsbcq_u32): Likewise.
5267 (__arm_vsbcq_m_s32): Likewise.
5268 (__arm_vsbcq_m_u32): Likewise.
5269 (vadciq_m): Define polymorphic variant.
5271 (vadcq_m): Likewise.
5273 (vsbciq_m): Likewise.
5275 (vsbcq_m): Likewise.
5277 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE): Use builtin
5279 (BINOP_UNONE_UNONE_UNONE): Likewise.
5280 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
5281 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
5282 * config/arm/mve.md (VADCIQ): Define iterator.
5283 (VADCIQ_M): Likewise.
5285 (VSBCQ_M): Likewise.
5287 (VSBCIQ_M): Likewise.
5289 (VADCQ_M): Likewise.
5290 (mve_vadciq_m_<supf>v4si): Define RTL pattern.
5291 (mve_vadciq_<supf>v4si): Likewise.
5292 (mve_vadcq_m_<supf>v4si): Likewise.
5293 (mve_vadcq_<supf>v4si): Likewise.
5294 (mve_vsbciq_m_<supf>v4si): Likewise.
5295 (mve_vsbciq_<supf>v4si): Likewise.
5296 (mve_vsbcq_m_<supf>v4si): Likewise.
5297 (mve_vsbcq_<supf>v4si): Likewise.
5298 (get_fpscr_nzcvqc): Define isns.
5299 (set_fpscr_nzcvqc): Define isns.
5300 * config/arm/unspecs.md (UNSPEC_GET_FPSCR_NZCVQC): Define.
5301 (UNSPEC_SET_FPSCR_NZCVQC): Define.
5303 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
5305 * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
5306 (vddupq_x_n_u16): Likewise.
5307 (vddupq_x_n_u32): Likewise.
5308 (vddupq_x_wb_u8): Likewise.
5309 (vddupq_x_wb_u16): Likewise.
5310 (vddupq_x_wb_u32): Likewise.
5311 (vdwdupq_x_n_u8): Likewise.
5312 (vdwdupq_x_n_u16): Likewise.
5313 (vdwdupq_x_n_u32): Likewise.
5314 (vdwdupq_x_wb_u8): Likewise.
5315 (vdwdupq_x_wb_u16): Likewise.
5316 (vdwdupq_x_wb_u32): Likewise.
5317 (vidupq_x_n_u8): Likewise.
5318 (vidupq_x_n_u16): Likewise.
5319 (vidupq_x_n_u32): Likewise.
5320 (vidupq_x_wb_u8): Likewise.
5321 (vidupq_x_wb_u16): Likewise.
5322 (vidupq_x_wb_u32): Likewise.
5323 (viwdupq_x_n_u8): Likewise.
5324 (viwdupq_x_n_u16): Likewise.
5325 (viwdupq_x_n_u32): Likewise.
5326 (viwdupq_x_wb_u8): Likewise.
5327 (viwdupq_x_wb_u16): Likewise.
5328 (viwdupq_x_wb_u32): Likewise.
5329 (vdupq_x_n_s8): Likewise.
5330 (vdupq_x_n_s16): Likewise.
5331 (vdupq_x_n_s32): Likewise.
5332 (vdupq_x_n_u8): Likewise.
5333 (vdupq_x_n_u16): Likewise.
5334 (vdupq_x_n_u32): Likewise.
5335 (vminq_x_s8): Likewise.
5336 (vminq_x_s16): Likewise.
5337 (vminq_x_s32): Likewise.
5338 (vminq_x_u8): Likewise.
5339 (vminq_x_u16): Likewise.
5340 (vminq_x_u32): Likewise.
5341 (vmaxq_x_s8): Likewise.
5342 (vmaxq_x_s16): Likewise.
5343 (vmaxq_x_s32): Likewise.
5344 (vmaxq_x_u8): Likewise.
5345 (vmaxq_x_u16): Likewise.
5346 (vmaxq_x_u32): Likewise.
5347 (vabdq_x_s8): Likewise.
5348 (vabdq_x_s16): Likewise.
5349 (vabdq_x_s32): Likewise.
5350 (vabdq_x_u8): Likewise.
5351 (vabdq_x_u16): Likewise.
5352 (vabdq_x_u32): Likewise.
5353 (vabsq_x_s8): Likewise.
5354 (vabsq_x_s16): Likewise.
5355 (vabsq_x_s32): Likewise.
5356 (vaddq_x_s8): Likewise.
5357 (vaddq_x_s16): Likewise.
5358 (vaddq_x_s32): Likewise.
5359 (vaddq_x_n_s8): Likewise.
5360 (vaddq_x_n_s16): Likewise.
5361 (vaddq_x_n_s32): Likewise.
5362 (vaddq_x_u8): Likewise.
5363 (vaddq_x_u16): Likewise.
5364 (vaddq_x_u32): Likewise.
5365 (vaddq_x_n_u8): Likewise.
5366 (vaddq_x_n_u16): Likewise.
5367 (vaddq_x_n_u32): Likewise.
5368 (vclsq_x_s8): Likewise.
5369 (vclsq_x_s16): Likewise.
5370 (vclsq_x_s32): Likewise.
5371 (vclzq_x_s8): Likewise.
5372 (vclzq_x_s16): Likewise.
5373 (vclzq_x_s32): Likewise.
5374 (vclzq_x_u8): Likewise.
5375 (vclzq_x_u16): Likewise.
5376 (vclzq_x_u32): Likewise.
5377 (vnegq_x_s8): Likewise.
5378 (vnegq_x_s16): Likewise.
5379 (vnegq_x_s32): Likewise.
5380 (vmulhq_x_s8): Likewise.
5381 (vmulhq_x_s16): Likewise.
5382 (vmulhq_x_s32): Likewise.
5383 (vmulhq_x_u8): Likewise.
5384 (vmulhq_x_u16): Likewise.
5385 (vmulhq_x_u32): Likewise.
5386 (vmullbq_poly_x_p8): Likewise.
5387 (vmullbq_poly_x_p16): Likewise.
5388 (vmullbq_int_x_s8): Likewise.
5389 (vmullbq_int_x_s16): Likewise.
5390 (vmullbq_int_x_s32): Likewise.
5391 (vmullbq_int_x_u8): Likewise.
5392 (vmullbq_int_x_u16): Likewise.
5393 (vmullbq_int_x_u32): Likewise.
5394 (vmulltq_poly_x_p8): Likewise.
5395 (vmulltq_poly_x_p16): Likewise.
5396 (vmulltq_int_x_s8): Likewise.
5397 (vmulltq_int_x_s16): Likewise.
5398 (vmulltq_int_x_s32): Likewise.
5399 (vmulltq_int_x_u8): Likewise.
5400 (vmulltq_int_x_u16): Likewise.
5401 (vmulltq_int_x_u32): Likewise.
5402 (vmulq_x_s8): Likewise.
5403 (vmulq_x_s16): Likewise.
5404 (vmulq_x_s32): Likewise.
5405 (vmulq_x_n_s8): Likewise.
5406 (vmulq_x_n_s16): Likewise.
5407 (vmulq_x_n_s32): Likewise.
5408 (vmulq_x_u8): Likewise.
5409 (vmulq_x_u16): Likewise.
5410 (vmulq_x_u32): Likewise.
5411 (vmulq_x_n_u8): Likewise.
5412 (vmulq_x_n_u16): Likewise.
5413 (vmulq_x_n_u32): Likewise.
5414 (vsubq_x_s8): Likewise.
5415 (vsubq_x_s16): Likewise.
5416 (vsubq_x_s32): Likewise.
5417 (vsubq_x_n_s8): Likewise.
5418 (vsubq_x_n_s16): Likewise.
5419 (vsubq_x_n_s32): Likewise.
5420 (vsubq_x_u8): Likewise.
5421 (vsubq_x_u16): Likewise.
5422 (vsubq_x_u32): Likewise.
5423 (vsubq_x_n_u8): Likewise.
5424 (vsubq_x_n_u16): Likewise.
5425 (vsubq_x_n_u32): Likewise.
5426 (vcaddq_rot90_x_s8): Likewise.
5427 (vcaddq_rot90_x_s16): Likewise.
5428 (vcaddq_rot90_x_s32): Likewise.
5429 (vcaddq_rot90_x_u8): Likewise.
5430 (vcaddq_rot90_x_u16): Likewise.
5431 (vcaddq_rot90_x_u32): Likewise.
5432 (vcaddq_rot270_x_s8): Likewise.
5433 (vcaddq_rot270_x_s16): Likewise.
5434 (vcaddq_rot270_x_s32): Likewise.
5435 (vcaddq_rot270_x_u8): Likewise.
5436 (vcaddq_rot270_x_u16): Likewise.
5437 (vcaddq_rot270_x_u32): Likewise.
5438 (vhaddq_x_n_s8): Likewise.
5439 (vhaddq_x_n_s16): Likewise.
5440 (vhaddq_x_n_s32): Likewise.
5441 (vhaddq_x_n_u8): Likewise.
5442 (vhaddq_x_n_u16): Likewise.
5443 (vhaddq_x_n_u32): Likewise.
5444 (vhaddq_x_s8): Likewise.
5445 (vhaddq_x_s16): Likewise.
5446 (vhaddq_x_s32): Likewise.
5447 (vhaddq_x_u8): Likewise.
5448 (vhaddq_x_u16): Likewise.
5449 (vhaddq_x_u32): Likewise.
5450 (vhcaddq_rot90_x_s8): Likewise.
5451 (vhcaddq_rot90_x_s16): Likewise.
5452 (vhcaddq_rot90_x_s32): Likewise.
5453 (vhcaddq_rot270_x_s8): Likewise.
5454 (vhcaddq_rot270_x_s16): Likewise.
5455 (vhcaddq_rot270_x_s32): Likewise.
5456 (vhsubq_x_n_s8): Likewise.
5457 (vhsubq_x_n_s16): Likewise.
5458 (vhsubq_x_n_s32): Likewise.
5459 (vhsubq_x_n_u8): Likewise.
5460 (vhsubq_x_n_u16): Likewise.
5461 (vhsubq_x_n_u32): Likewise.
5462 (vhsubq_x_s8): Likewise.
5463 (vhsubq_x_s16): Likewise.
5464 (vhsubq_x_s32): Likewise.
5465 (vhsubq_x_u8): Likewise.
5466 (vhsubq_x_u16): Likewise.
5467 (vhsubq_x_u32): Likewise.
5468 (vrhaddq_x_s8): Likewise.
5469 (vrhaddq_x_s16): Likewise.
5470 (vrhaddq_x_s32): Likewise.
5471 (vrhaddq_x_u8): Likewise.
5472 (vrhaddq_x_u16): Likewise.
5473 (vrhaddq_x_u32): Likewise.
5474 (vrmulhq_x_s8): Likewise.
5475 (vrmulhq_x_s16): Likewise.
5476 (vrmulhq_x_s32): Likewise.
5477 (vrmulhq_x_u8): Likewise.
5478 (vrmulhq_x_u16): Likewise.
5479 (vrmulhq_x_u32): Likewise.
5480 (vandq_x_s8): Likewise.
5481 (vandq_x_s16): Likewise.
5482 (vandq_x_s32): Likewise.
5483 (vandq_x_u8): Likewise.
5484 (vandq_x_u16): Likewise.
5485 (vandq_x_u32): Likewise.
5486 (vbicq_x_s8): Likewise.
5487 (vbicq_x_s16): Likewise.
5488 (vbicq_x_s32): Likewise.
5489 (vbicq_x_u8): Likewise.
5490 (vbicq_x_u16): Likewise.
5491 (vbicq_x_u32): Likewise.
5492 (vbrsrq_x_n_s8): Likewise.
5493 (vbrsrq_x_n_s16): Likewise.
5494 (vbrsrq_x_n_s32): Likewise.
5495 (vbrsrq_x_n_u8): Likewise.
5496 (vbrsrq_x_n_u16): Likewise.
5497 (vbrsrq_x_n_u32): Likewise.
5498 (veorq_x_s8): Likewise.
5499 (veorq_x_s16): Likewise.
5500 (veorq_x_s32): Likewise.
5501 (veorq_x_u8): Likewise.
5502 (veorq_x_u16): Likewise.
5503 (veorq_x_u32): Likewise.
5504 (vmovlbq_x_s8): Likewise.
5505 (vmovlbq_x_s16): Likewise.
5506 (vmovlbq_x_u8): Likewise.
5507 (vmovlbq_x_u16): Likewise.
5508 (vmovltq_x_s8): Likewise.
5509 (vmovltq_x_s16): Likewise.
5510 (vmovltq_x_u8): Likewise.
5511 (vmovltq_x_u16): Likewise.
5512 (vmvnq_x_s8): Likewise.
5513 (vmvnq_x_s16): Likewise.
5514 (vmvnq_x_s32): Likewise.
5515 (vmvnq_x_u8): Likewise.
5516 (vmvnq_x_u16): Likewise.
5517 (vmvnq_x_u32): Likewise.
5518 (vmvnq_x_n_s16): Likewise.
5519 (vmvnq_x_n_s32): Likewise.
5520 (vmvnq_x_n_u16): Likewise.
5521 (vmvnq_x_n_u32): Likewise.
5522 (vornq_x_s8): Likewise.
5523 (vornq_x_s16): Likewise.
5524 (vornq_x_s32): Likewise.
5525 (vornq_x_u8): Likewise.
5526 (vornq_x_u16): Likewise.
5527 (vornq_x_u32): Likewise.
5528 (vorrq_x_s8): Likewise.
5529 (vorrq_x_s16): Likewise.
5530 (vorrq_x_s32): Likewise.
5531 (vorrq_x_u8): Likewise.
5532 (vorrq_x_u16): Likewise.
5533 (vorrq_x_u32): Likewise.
5534 (vrev16q_x_s8): Likewise.
5535 (vrev16q_x_u8): Likewise.
5536 (vrev32q_x_s8): Likewise.
5537 (vrev32q_x_s16): Likewise.
5538 (vrev32q_x_u8): Likewise.
5539 (vrev32q_x_u16): Likewise.
5540 (vrev64q_x_s8): Likewise.
5541 (vrev64q_x_s16): Likewise.
5542 (vrev64q_x_s32): Likewise.
5543 (vrev64q_x_u8): Likewise.
5544 (vrev64q_x_u16): Likewise.
5545 (vrev64q_x_u32): Likewise.
5546 (vrshlq_x_s8): Likewise.
5547 (vrshlq_x_s16): Likewise.
5548 (vrshlq_x_s32): Likewise.
5549 (vrshlq_x_u8): Likewise.
5550 (vrshlq_x_u16): Likewise.
5551 (vrshlq_x_u32): Likewise.
5552 (vshllbq_x_n_s8): Likewise.
5553 (vshllbq_x_n_s16): Likewise.
5554 (vshllbq_x_n_u8): Likewise.
5555 (vshllbq_x_n_u16): Likewise.
5556 (vshlltq_x_n_s8): Likewise.
5557 (vshlltq_x_n_s16): Likewise.
5558 (vshlltq_x_n_u8): Likewise.
5559 (vshlltq_x_n_u16): Likewise.
5560 (vshlq_x_s8): Likewise.
5561 (vshlq_x_s16): Likewise.
5562 (vshlq_x_s32): Likewise.
5563 (vshlq_x_u8): Likewise.
5564 (vshlq_x_u16): Likewise.
5565 (vshlq_x_u32): Likewise.
5566 (vshlq_x_n_s8): Likewise.
5567 (vshlq_x_n_s16): Likewise.
5568 (vshlq_x_n_s32): Likewise.
5569 (vshlq_x_n_u8): Likewise.
5570 (vshlq_x_n_u16): Likewise.
5571 (vshlq_x_n_u32): Likewise.
5572 (vrshrq_x_n_s8): Likewise.
5573 (vrshrq_x_n_s16): Likewise.
5574 (vrshrq_x_n_s32): Likewise.
5575 (vrshrq_x_n_u8): Likewise.
5576 (vrshrq_x_n_u16): Likewise.
5577 (vrshrq_x_n_u32): Likewise.
5578 (vshrq_x_n_s8): Likewise.
5579 (vshrq_x_n_s16): Likewise.
5580 (vshrq_x_n_s32): Likewise.
5581 (vshrq_x_n_u8): Likewise.
5582 (vshrq_x_n_u16): Likewise.
5583 (vshrq_x_n_u32): Likewise.
5584 (vdupq_x_n_f16): Likewise.
5585 (vdupq_x_n_f32): Likewise.
5586 (vminnmq_x_f16): Likewise.
5587 (vminnmq_x_f32): Likewise.
5588 (vmaxnmq_x_f16): Likewise.
5589 (vmaxnmq_x_f32): Likewise.
5590 (vabdq_x_f16): Likewise.
5591 (vabdq_x_f32): Likewise.
5592 (vabsq_x_f16): Likewise.
5593 (vabsq_x_f32): Likewise.
5594 (vaddq_x_f16): Likewise.
5595 (vaddq_x_f32): Likewise.
5596 (vaddq_x_n_f16): Likewise.
5597 (vaddq_x_n_f32): Likewise.
5598 (vnegq_x_f16): Likewise.
5599 (vnegq_x_f32): Likewise.
5600 (vmulq_x_f16): Likewise.
5601 (vmulq_x_f32): Likewise.
5602 (vmulq_x_n_f16): Likewise.
5603 (vmulq_x_n_f32): Likewise.
5604 (vsubq_x_f16): Likewise.
5605 (vsubq_x_f32): Likewise.
5606 (vsubq_x_n_f16): Likewise.
5607 (vsubq_x_n_f32): Likewise.
5608 (vcaddq_rot90_x_f16): Likewise.
5609 (vcaddq_rot90_x_f32): Likewise.
5610 (vcaddq_rot270_x_f16): Likewise.
5611 (vcaddq_rot270_x_f32): Likewise.
5612 (vcmulq_x_f16): Likewise.
5613 (vcmulq_x_f32): Likewise.
5614 (vcmulq_rot90_x_f16): Likewise.
5615 (vcmulq_rot90_x_f32): Likewise.
5616 (vcmulq_rot180_x_f16): Likewise.
5617 (vcmulq_rot180_x_f32): Likewise.
5618 (vcmulq_rot270_x_f16): Likewise.
5619 (vcmulq_rot270_x_f32): Likewise.
5620 (vcvtaq_x_s16_f16): Likewise.
5621 (vcvtaq_x_s32_f32): Likewise.
5622 (vcvtaq_x_u16_f16): Likewise.
5623 (vcvtaq_x_u32_f32): Likewise.
5624 (vcvtnq_x_s16_f16): Likewise.
5625 (vcvtnq_x_s32_f32): Likewise.
5626 (vcvtnq_x_u16_f16): Likewise.
5627 (vcvtnq_x_u32_f32): Likewise.
5628 (vcvtpq_x_s16_f16): Likewise.
5629 (vcvtpq_x_s32_f32): Likewise.
5630 (vcvtpq_x_u16_f16): Likewise.
5631 (vcvtpq_x_u32_f32): Likewise.
5632 (vcvtmq_x_s16_f16): Likewise.
5633 (vcvtmq_x_s32_f32): Likewise.
5634 (vcvtmq_x_u16_f16): Likewise.
5635 (vcvtmq_x_u32_f32): Likewise.
5636 (vcvtbq_x_f32_f16): Likewise.
5637 (vcvttq_x_f32_f16): Likewise.
5638 (vcvtq_x_f16_u16): Likewise.
5639 (vcvtq_x_f16_s16): Likewise.
5640 (vcvtq_x_f32_s32): Likewise.
5641 (vcvtq_x_f32_u32): Likewise.
5642 (vcvtq_x_n_f16_s16): Likewise.
5643 (vcvtq_x_n_f16_u16): Likewise.
5644 (vcvtq_x_n_f32_s32): Likewise.
5645 (vcvtq_x_n_f32_u32): Likewise.
5646 (vcvtq_x_s16_f16): Likewise.
5647 (vcvtq_x_s32_f32): Likewise.
5648 (vcvtq_x_u16_f16): Likewise.
5649 (vcvtq_x_u32_f32): Likewise.
5650 (vcvtq_x_n_s16_f16): Likewise.
5651 (vcvtq_x_n_s32_f32): Likewise.
5652 (vcvtq_x_n_u16_f16): Likewise.
5653 (vcvtq_x_n_u32_f32): Likewise.
5654 (vrndq_x_f16): Likewise.
5655 (vrndq_x_f32): Likewise.
5656 (vrndnq_x_f16): Likewise.
5657 (vrndnq_x_f32): Likewise.
5658 (vrndmq_x_f16): Likewise.
5659 (vrndmq_x_f32): Likewise.
5660 (vrndpq_x_f16): Likewise.
5661 (vrndpq_x_f32): Likewise.
5662 (vrndaq_x_f16): Likewise.
5663 (vrndaq_x_f32): Likewise.
5664 (vrndxq_x_f16): Likewise.
5665 (vrndxq_x_f32): Likewise.
5666 (vandq_x_f16): Likewise.
5667 (vandq_x_f32): Likewise.
5668 (vbicq_x_f16): Likewise.
5669 (vbicq_x_f32): Likewise.
5670 (vbrsrq_x_n_f16): Likewise.
5671 (vbrsrq_x_n_f32): Likewise.
5672 (veorq_x_f16): Likewise.
5673 (veorq_x_f32): Likewise.
5674 (vornq_x_f16): Likewise.
5675 (vornq_x_f32): Likewise.
5676 (vorrq_x_f16): Likewise.
5677 (vorrq_x_f32): Likewise.
5678 (vrev32q_x_f16): Likewise.
5679 (vrev64q_x_f16): Likewise.
5680 (vrev64q_x_f32): Likewise.
5681 (__arm_vddupq_x_n_u8): Define intrinsic.
5682 (__arm_vddupq_x_n_u16): Likewise.
5683 (__arm_vddupq_x_n_u32): Likewise.
5684 (__arm_vddupq_x_wb_u8): Likewise.
5685 (__arm_vddupq_x_wb_u16): Likewise.
5686 (__arm_vddupq_x_wb_u32): Likewise.
5687 (__arm_vdwdupq_x_n_u8): Likewise.
5688 (__arm_vdwdupq_x_n_u16): Likewise.
5689 (__arm_vdwdupq_x_n_u32): Likewise.
5690 (__arm_vdwdupq_x_wb_u8): Likewise.
5691 (__arm_vdwdupq_x_wb_u16): Likewise.
5692 (__arm_vdwdupq_x_wb_u32): Likewise.
5693 (__arm_vidupq_x_n_u8): Likewise.
5694 (__arm_vidupq_x_n_u16): Likewise.
5695 (__arm_vidupq_x_n_u32): Likewise.
5696 (__arm_vidupq_x_wb_u8): Likewise.
5697 (__arm_vidupq_x_wb_u16): Likewise.
5698 (__arm_vidupq_x_wb_u32): Likewise.
5699 (__arm_viwdupq_x_n_u8): Likewise.
5700 (__arm_viwdupq_x_n_u16): Likewise.
5701 (__arm_viwdupq_x_n_u32): Likewise.
5702 (__arm_viwdupq_x_wb_u8): Likewise.
5703 (__arm_viwdupq_x_wb_u16): Likewise.
5704 (__arm_viwdupq_x_wb_u32): Likewise.
5705 (__arm_vdupq_x_n_s8): Likewise.
5706 (__arm_vdupq_x_n_s16): Likewise.
5707 (__arm_vdupq_x_n_s32): Likewise.
5708 (__arm_vdupq_x_n_u8): Likewise.
5709 (__arm_vdupq_x_n_u16): Likewise.
5710 (__arm_vdupq_x_n_u32): Likewise.
5711 (__arm_vminq_x_s8): Likewise.
5712 (__arm_vminq_x_s16): Likewise.
5713 (__arm_vminq_x_s32): Likewise.
5714 (__arm_vminq_x_u8): Likewise.
5715 (__arm_vminq_x_u16): Likewise.
5716 (__arm_vminq_x_u32): Likewise.
5717 (__arm_vmaxq_x_s8): Likewise.
5718 (__arm_vmaxq_x_s16): Likewise.
5719 (__arm_vmaxq_x_s32): Likewise.
5720 (__arm_vmaxq_x_u8): Likewise.
5721 (__arm_vmaxq_x_u16): Likewise.
5722 (__arm_vmaxq_x_u32): Likewise.
5723 (__arm_vabdq_x_s8): Likewise.
5724 (__arm_vabdq_x_s16): Likewise.
5725 (__arm_vabdq_x_s32): Likewise.
5726 (__arm_vabdq_x_u8): Likewise.
5727 (__arm_vabdq_x_u16): Likewise.
5728 (__arm_vabdq_x_u32): Likewise.
5729 (__arm_vabsq_x_s8): Likewise.
5730 (__arm_vabsq_x_s16): Likewise.
5731 (__arm_vabsq_x_s32): Likewise.
5732 (__arm_vaddq_x_s8): Likewise.
5733 (__arm_vaddq_x_s16): Likewise.
5734 (__arm_vaddq_x_s32): Likewise.
5735 (__arm_vaddq_x_n_s8): Likewise.
5736 (__arm_vaddq_x_n_s16): Likewise.
5737 (__arm_vaddq_x_n_s32): Likewise.
5738 (__arm_vaddq_x_u8): Likewise.
5739 (__arm_vaddq_x_u16): Likewise.
5740 (__arm_vaddq_x_u32): Likewise.
5741 (__arm_vaddq_x_n_u8): Likewise.
5742 (__arm_vaddq_x_n_u16): Likewise.
5743 (__arm_vaddq_x_n_u32): Likewise.
5744 (__arm_vclsq_x_s8): Likewise.
5745 (__arm_vclsq_x_s16): Likewise.
5746 (__arm_vclsq_x_s32): Likewise.
5747 (__arm_vclzq_x_s8): Likewise.
5748 (__arm_vclzq_x_s16): Likewise.
5749 (__arm_vclzq_x_s32): Likewise.
5750 (__arm_vclzq_x_u8): Likewise.
5751 (__arm_vclzq_x_u16): Likewise.
5752 (__arm_vclzq_x_u32): Likewise.
5753 (__arm_vnegq_x_s8): Likewise.
5754 (__arm_vnegq_x_s16): Likewise.
5755 (__arm_vnegq_x_s32): Likewise.
5756 (__arm_vmulhq_x_s8): Likewise.
5757 (__arm_vmulhq_x_s16): Likewise.
5758 (__arm_vmulhq_x_s32): Likewise.
5759 (__arm_vmulhq_x_u8): Likewise.
5760 (__arm_vmulhq_x_u16): Likewise.
5761 (__arm_vmulhq_x_u32): Likewise.
5762 (__arm_vmullbq_poly_x_p8): Likewise.
5763 (__arm_vmullbq_poly_x_p16): Likewise.
5764 (__arm_vmullbq_int_x_s8): Likewise.
5765 (__arm_vmullbq_int_x_s16): Likewise.
5766 (__arm_vmullbq_int_x_s32): Likewise.
5767 (__arm_vmullbq_int_x_u8): Likewise.
5768 (__arm_vmullbq_int_x_u16): Likewise.
5769 (__arm_vmullbq_int_x_u32): Likewise.
5770 (__arm_vmulltq_poly_x_p8): Likewise.
5771 (__arm_vmulltq_poly_x_p16): Likewise.
5772 (__arm_vmulltq_int_x_s8): Likewise.
5773 (__arm_vmulltq_int_x_s16): Likewise.
5774 (__arm_vmulltq_int_x_s32): Likewise.
5775 (__arm_vmulltq_int_x_u8): Likewise.
5776 (__arm_vmulltq_int_x_u16): Likewise.
5777 (__arm_vmulltq_int_x_u32): Likewise.
5778 (__arm_vmulq_x_s8): Likewise.
5779 (__arm_vmulq_x_s16): Likewise.
5780 (__arm_vmulq_x_s32): Likewise.
5781 (__arm_vmulq_x_n_s8): Likewise.
5782 (__arm_vmulq_x_n_s16): Likewise.
5783 (__arm_vmulq_x_n_s32): Likewise.
5784 (__arm_vmulq_x_u8): Likewise.
5785 (__arm_vmulq_x_u16): Likewise.
5786 (__arm_vmulq_x_u32): Likewise.
5787 (__arm_vmulq_x_n_u8): Likewise.
5788 (__arm_vmulq_x_n_u16): Likewise.
5789 (__arm_vmulq_x_n_u32): Likewise.
5790 (__arm_vsubq_x_s8): Likewise.
5791 (__arm_vsubq_x_s16): Likewise.
5792 (__arm_vsubq_x_s32): Likewise.
5793 (__arm_vsubq_x_n_s8): Likewise.
5794 (__arm_vsubq_x_n_s16): Likewise.
5795 (__arm_vsubq_x_n_s32): Likewise.
5796 (__arm_vsubq_x_u8): Likewise.
5797 (__arm_vsubq_x_u16): Likewise.
5798 (__arm_vsubq_x_u32): Likewise.
5799 (__arm_vsubq_x_n_u8): Likewise.
5800 (__arm_vsubq_x_n_u16): Likewise.
5801 (__arm_vsubq_x_n_u32): Likewise.
5802 (__arm_vcaddq_rot90_x_s8): Likewise.
5803 (__arm_vcaddq_rot90_x_s16): Likewise.
5804 (__arm_vcaddq_rot90_x_s32): Likewise.
5805 (__arm_vcaddq_rot90_x_u8): Likewise.
5806 (__arm_vcaddq_rot90_x_u16): Likewise.
5807 (__arm_vcaddq_rot90_x_u32): Likewise.
5808 (__arm_vcaddq_rot270_x_s8): Likewise.
5809 (__arm_vcaddq_rot270_x_s16): Likewise.
5810 (__arm_vcaddq_rot270_x_s32): Likewise.
5811 (__arm_vcaddq_rot270_x_u8): Likewise.
5812 (__arm_vcaddq_rot270_x_u16): Likewise.
5813 (__arm_vcaddq_rot270_x_u32): Likewise.
5814 (__arm_vhaddq_x_n_s8): Likewise.
5815 (__arm_vhaddq_x_n_s16): Likewise.
5816 (__arm_vhaddq_x_n_s32): Likewise.
5817 (__arm_vhaddq_x_n_u8): Likewise.
5818 (__arm_vhaddq_x_n_u16): Likewise.
5819 (__arm_vhaddq_x_n_u32): Likewise.
5820 (__arm_vhaddq_x_s8): Likewise.
5821 (__arm_vhaddq_x_s16): Likewise.
5822 (__arm_vhaddq_x_s32): Likewise.
5823 (__arm_vhaddq_x_u8): Likewise.
5824 (__arm_vhaddq_x_u16): Likewise.
5825 (__arm_vhaddq_x_u32): Likewise.
5826 (__arm_vhcaddq_rot90_x_s8): Likewise.
5827 (__arm_vhcaddq_rot90_x_s16): Likewise.
5828 (__arm_vhcaddq_rot90_x_s32): Likewise.
5829 (__arm_vhcaddq_rot270_x_s8): Likewise.
5830 (__arm_vhcaddq_rot270_x_s16): Likewise.
5831 (__arm_vhcaddq_rot270_x_s32): Likewise.
5832 (__arm_vhsubq_x_n_s8): Likewise.
5833 (__arm_vhsubq_x_n_s16): Likewise.
5834 (__arm_vhsubq_x_n_s32): Likewise.
5835 (__arm_vhsubq_x_n_u8): Likewise.
5836 (__arm_vhsubq_x_n_u16): Likewise.
5837 (__arm_vhsubq_x_n_u32): Likewise.
5838 (__arm_vhsubq_x_s8): Likewise.
5839 (__arm_vhsubq_x_s16): Likewise.
5840 (__arm_vhsubq_x_s32): Likewise.
5841 (__arm_vhsubq_x_u8): Likewise.
5842 (__arm_vhsubq_x_u16): Likewise.
5843 (__arm_vhsubq_x_u32): Likewise.
5844 (__arm_vrhaddq_x_s8): Likewise.
5845 (__arm_vrhaddq_x_s16): Likewise.
5846 (__arm_vrhaddq_x_s32): Likewise.
5847 (__arm_vrhaddq_x_u8): Likewise.
5848 (__arm_vrhaddq_x_u16): Likewise.
5849 (__arm_vrhaddq_x_u32): Likewise.
5850 (__arm_vrmulhq_x_s8): Likewise.
5851 (__arm_vrmulhq_x_s16): Likewise.
5852 (__arm_vrmulhq_x_s32): Likewise.
5853 (__arm_vrmulhq_x_u8): Likewise.
5854 (__arm_vrmulhq_x_u16): Likewise.
5855 (__arm_vrmulhq_x_u32): Likewise.
5856 (__arm_vandq_x_s8): Likewise.
5857 (__arm_vandq_x_s16): Likewise.
5858 (__arm_vandq_x_s32): Likewise.
5859 (__arm_vandq_x_u8): Likewise.
5860 (__arm_vandq_x_u16): Likewise.
5861 (__arm_vandq_x_u32): Likewise.
5862 (__arm_vbicq_x_s8): Likewise.
5863 (__arm_vbicq_x_s16): Likewise.
5864 (__arm_vbicq_x_s32): Likewise.
5865 (__arm_vbicq_x_u8): Likewise.
5866 (__arm_vbicq_x_u16): Likewise.
5867 (__arm_vbicq_x_u32): Likewise.
5868 (__arm_vbrsrq_x_n_s8): Likewise.
5869 (__arm_vbrsrq_x_n_s16): Likewise.
5870 (__arm_vbrsrq_x_n_s32): Likewise.
5871 (__arm_vbrsrq_x_n_u8): Likewise.
5872 (__arm_vbrsrq_x_n_u16): Likewise.
5873 (__arm_vbrsrq_x_n_u32): Likewise.
5874 (__arm_veorq_x_s8): Likewise.
5875 (__arm_veorq_x_s16): Likewise.
5876 (__arm_veorq_x_s32): Likewise.
5877 (__arm_veorq_x_u8): Likewise.
5878 (__arm_veorq_x_u16): Likewise.
5879 (__arm_veorq_x_u32): Likewise.
5880 (__arm_vmovlbq_x_s8): Likewise.
5881 (__arm_vmovlbq_x_s16): Likewise.
5882 (__arm_vmovlbq_x_u8): Likewise.
5883 (__arm_vmovlbq_x_u16): Likewise.
5884 (__arm_vmovltq_x_s8): Likewise.
5885 (__arm_vmovltq_x_s16): Likewise.
5886 (__arm_vmovltq_x_u8): Likewise.
5887 (__arm_vmovltq_x_u16): Likewise.
5888 (__arm_vmvnq_x_s8): Likewise.
5889 (__arm_vmvnq_x_s16): Likewise.
5890 (__arm_vmvnq_x_s32): Likewise.
5891 (__arm_vmvnq_x_u8): Likewise.
5892 (__arm_vmvnq_x_u16): Likewise.
5893 (__arm_vmvnq_x_u32): Likewise.
5894 (__arm_vmvnq_x_n_s16): Likewise.
5895 (__arm_vmvnq_x_n_s32): Likewise.
5896 (__arm_vmvnq_x_n_u16): Likewise.
5897 (__arm_vmvnq_x_n_u32): Likewise.
5898 (__arm_vornq_x_s8): Likewise.
5899 (__arm_vornq_x_s16): Likewise.
5900 (__arm_vornq_x_s32): Likewise.
5901 (__arm_vornq_x_u8): Likewise.
5902 (__arm_vornq_x_u16): Likewise.
5903 (__arm_vornq_x_u32): Likewise.
5904 (__arm_vorrq_x_s8): Likewise.
5905 (__arm_vorrq_x_s16): Likewise.
5906 (__arm_vorrq_x_s32): Likewise.
5907 (__arm_vorrq_x_u8): Likewise.
5908 (__arm_vorrq_x_u16): Likewise.
5909 (__arm_vorrq_x_u32): Likewise.
5910 (__arm_vrev16q_x_s8): Likewise.
5911 (__arm_vrev16q_x_u8): Likewise.
5912 (__arm_vrev32q_x_s8): Likewise.
5913 (__arm_vrev32q_x_s16): Likewise.
5914 (__arm_vrev32q_x_u8): Likewise.
5915 (__arm_vrev32q_x_u16): Likewise.
5916 (__arm_vrev64q_x_s8): Likewise.
5917 (__arm_vrev64q_x_s16): Likewise.
5918 (__arm_vrev64q_x_s32): Likewise.
5919 (__arm_vrev64q_x_u8): Likewise.
5920 (__arm_vrev64q_x_u16): Likewise.
5921 (__arm_vrev64q_x_u32): Likewise.
5922 (__arm_vrshlq_x_s8): Likewise.
5923 (__arm_vrshlq_x_s16): Likewise.
5924 (__arm_vrshlq_x_s32): Likewise.
5925 (__arm_vrshlq_x_u8): Likewise.
5926 (__arm_vrshlq_x_u16): Likewise.
5927 (__arm_vrshlq_x_u32): Likewise.
5928 (__arm_vshllbq_x_n_s8): Likewise.
5929 (__arm_vshllbq_x_n_s16): Likewise.
5930 (__arm_vshllbq_x_n_u8): Likewise.
5931 (__arm_vshllbq_x_n_u16): Likewise.
5932 (__arm_vshlltq_x_n_s8): Likewise.
5933 (__arm_vshlltq_x_n_s16): Likewise.
5934 (__arm_vshlltq_x_n_u8): Likewise.
5935 (__arm_vshlltq_x_n_u16): Likewise.
5936 (__arm_vshlq_x_s8): Likewise.
5937 (__arm_vshlq_x_s16): Likewise.
5938 (__arm_vshlq_x_s32): Likewise.
5939 (__arm_vshlq_x_u8): Likewise.
5940 (__arm_vshlq_x_u16): Likewise.
5941 (__arm_vshlq_x_u32): Likewise.
5942 (__arm_vshlq_x_n_s8): Likewise.
5943 (__arm_vshlq_x_n_s16): Likewise.
5944 (__arm_vshlq_x_n_s32): Likewise.
5945 (__arm_vshlq_x_n_u8): Likewise.
5946 (__arm_vshlq_x_n_u16): Likewise.
5947 (__arm_vshlq_x_n_u32): Likewise.
5948 (__arm_vrshrq_x_n_s8): Likewise.
5949 (__arm_vrshrq_x_n_s16): Likewise.
5950 (__arm_vrshrq_x_n_s32): Likewise.
5951 (__arm_vrshrq_x_n_u8): Likewise.
5952 (__arm_vrshrq_x_n_u16): Likewise.
5953 (__arm_vrshrq_x_n_u32): Likewise.
5954 (__arm_vshrq_x_n_s8): Likewise.
5955 (__arm_vshrq_x_n_s16): Likewise.
5956 (__arm_vshrq_x_n_s32): Likewise.
5957 (__arm_vshrq_x_n_u8): Likewise.
5958 (__arm_vshrq_x_n_u16): Likewise.
5959 (__arm_vshrq_x_n_u32): Likewise.
5960 (__arm_vdupq_x_n_f16): Likewise.
5961 (__arm_vdupq_x_n_f32): Likewise.
5962 (__arm_vminnmq_x_f16): Likewise.
5963 (__arm_vminnmq_x_f32): Likewise.
5964 (__arm_vmaxnmq_x_f16): Likewise.
5965 (__arm_vmaxnmq_x_f32): Likewise.
5966 (__arm_vabdq_x_f16): Likewise.
5967 (__arm_vabdq_x_f32): Likewise.
5968 (__arm_vabsq_x_f16): Likewise.
5969 (__arm_vabsq_x_f32): Likewise.
5970 (__arm_vaddq_x_f16): Likewise.
5971 (__arm_vaddq_x_f32): Likewise.
5972 (__arm_vaddq_x_n_f16): Likewise.
5973 (__arm_vaddq_x_n_f32): Likewise.
5974 (__arm_vnegq_x_f16): Likewise.
5975 (__arm_vnegq_x_f32): Likewise.
5976 (__arm_vmulq_x_f16): Likewise.
5977 (__arm_vmulq_x_f32): Likewise.
5978 (__arm_vmulq_x_n_f16): Likewise.
5979 (__arm_vmulq_x_n_f32): Likewise.
5980 (__arm_vsubq_x_f16): Likewise.
5981 (__arm_vsubq_x_f32): Likewise.
5982 (__arm_vsubq_x_n_f16): Likewise.
5983 (__arm_vsubq_x_n_f32): Likewise.
5984 (__arm_vcaddq_rot90_x_f16): Likewise.
5985 (__arm_vcaddq_rot90_x_f32): Likewise.
5986 (__arm_vcaddq_rot270_x_f16): Likewise.
5987 (__arm_vcaddq_rot270_x_f32): Likewise.
5988 (__arm_vcmulq_x_f16): Likewise.
5989 (__arm_vcmulq_x_f32): Likewise.
5990 (__arm_vcmulq_rot90_x_f16): Likewise.
5991 (__arm_vcmulq_rot90_x_f32): Likewise.
5992 (__arm_vcmulq_rot180_x_f16): Likewise.
5993 (__arm_vcmulq_rot180_x_f32): Likewise.
5994 (__arm_vcmulq_rot270_x_f16): Likewise.
5995 (__arm_vcmulq_rot270_x_f32): Likewise.
5996 (__arm_vcvtaq_x_s16_f16): Likewise.
5997 (__arm_vcvtaq_x_s32_f32): Likewise.
5998 (__arm_vcvtaq_x_u16_f16): Likewise.
5999 (__arm_vcvtaq_x_u32_f32): Likewise.
6000 (__arm_vcvtnq_x_s16_f16): Likewise.
6001 (__arm_vcvtnq_x_s32_f32): Likewise.
6002 (__arm_vcvtnq_x_u16_f16): Likewise.
6003 (__arm_vcvtnq_x_u32_f32): Likewise.
6004 (__arm_vcvtpq_x_s16_f16): Likewise.
6005 (__arm_vcvtpq_x_s32_f32): Likewise.
6006 (__arm_vcvtpq_x_u16_f16): Likewise.
6007 (__arm_vcvtpq_x_u32_f32): Likewise.
6008 (__arm_vcvtmq_x_s16_f16): Likewise.
6009 (__arm_vcvtmq_x_s32_f32): Likewise.
6010 (__arm_vcvtmq_x_u16_f16): Likewise.
6011 (__arm_vcvtmq_x_u32_f32): Likewise.
6012 (__arm_vcvtbq_x_f32_f16): Likewise.
6013 (__arm_vcvttq_x_f32_f16): Likewise.
6014 (__arm_vcvtq_x_f16_u16): Likewise.
6015 (__arm_vcvtq_x_f16_s16): Likewise.
6016 (__arm_vcvtq_x_f32_s32): Likewise.
6017 (__arm_vcvtq_x_f32_u32): Likewise.
6018 (__arm_vcvtq_x_n_f16_s16): Likewise.
6019 (__arm_vcvtq_x_n_f16_u16): Likewise.
6020 (__arm_vcvtq_x_n_f32_s32): Likewise.
6021 (__arm_vcvtq_x_n_f32_u32): Likewise.
6022 (__arm_vcvtq_x_s16_f16): Likewise.
6023 (__arm_vcvtq_x_s32_f32): Likewise.
6024 (__arm_vcvtq_x_u16_f16): Likewise.
6025 (__arm_vcvtq_x_u32_f32): Likewise.
6026 (__arm_vcvtq_x_n_s16_f16): Likewise.
6027 (__arm_vcvtq_x_n_s32_f32): Likewise.
6028 (__arm_vcvtq_x_n_u16_f16): Likewise.
6029 (__arm_vcvtq_x_n_u32_f32): Likewise.
6030 (__arm_vrndq_x_f16): Likewise.
6031 (__arm_vrndq_x_f32): Likewise.
6032 (__arm_vrndnq_x_f16): Likewise.
6033 (__arm_vrndnq_x_f32): Likewise.
6034 (__arm_vrndmq_x_f16): Likewise.
6035 (__arm_vrndmq_x_f32): Likewise.
6036 (__arm_vrndpq_x_f16): Likewise.
6037 (__arm_vrndpq_x_f32): Likewise.
6038 (__arm_vrndaq_x_f16): Likewise.
6039 (__arm_vrndaq_x_f32): Likewise.
6040 (__arm_vrndxq_x_f16): Likewise.
6041 (__arm_vrndxq_x_f32): Likewise.
6042 (__arm_vandq_x_f16): Likewise.
6043 (__arm_vandq_x_f32): Likewise.
6044 (__arm_vbicq_x_f16): Likewise.
6045 (__arm_vbicq_x_f32): Likewise.
6046 (__arm_vbrsrq_x_n_f16): Likewise.
6047 (__arm_vbrsrq_x_n_f32): Likewise.
6048 (__arm_veorq_x_f16): Likewise.
6049 (__arm_veorq_x_f32): Likewise.
6050 (__arm_vornq_x_f16): Likewise.
6051 (__arm_vornq_x_f32): Likewise.
6052 (__arm_vorrq_x_f16): Likewise.
6053 (__arm_vorrq_x_f32): Likewise.
6054 (__arm_vrev32q_x_f16): Likewise.
6055 (__arm_vrev64q_x_f16): Likewise.
6056 (__arm_vrev64q_x_f32): Likewise.
6057 (vabdq_x): Define polymorphic variant.
6058 (vabsq_x): Likewise.
6059 (vaddq_x): Likewise.
6060 (vandq_x): Likewise.
6061 (vbicq_x): Likewise.
6062 (vbrsrq_x): Likewise.
6063 (vcaddq_rot270_x): Likewise.
6064 (vcaddq_rot90_x): Likewise.
6065 (vcmulq_rot180_x): Likewise.
6066 (vcmulq_rot270_x): Likewise.
6067 (vcmulq_x): Likewise.
6068 (vcvtq_x): Likewise.
6069 (vcvtq_x_n): Likewise.
6070 (vcvtnq_m): Likewise.
6071 (veorq_x): Likewise.
6072 (vmaxnmq_x): Likewise.
6073 (vminnmq_x): Likewise.
6074 (vmulq_x): Likewise.
6075 (vnegq_x): Likewise.
6076 (vornq_x): Likewise.
6077 (vorrq_x): Likewise.
6078 (vrev32q_x): Likewise.
6079 (vrev64q_x): Likewise.
6080 (vrndaq_x): Likewise.
6081 (vrndmq_x): Likewise.
6082 (vrndnq_x): Likewise.
6083 (vrndpq_x): Likewise.
6084 (vrndq_x): Likewise.
6085 (vrndxq_x): Likewise.
6086 (vsubq_x): Likewise.
6087 (vcmulq_rot90_x): Likewise.
6089 (vclsq_x): Likewise.
6090 (vclzq_x): Likewise.
6091 (vhaddq_x): Likewise.
6092 (vhcaddq_rot270_x): Likewise.
6093 (vhcaddq_rot90_x): Likewise.
6094 (vhsubq_x): Likewise.
6095 (vmaxq_x): Likewise.
6096 (vminq_x): Likewise.
6097 (vmovlbq_x): Likewise.
6098 (vmovltq_x): Likewise.
6099 (vmulhq_x): Likewise.
6100 (vmullbq_int_x): Likewise.
6101 (vmullbq_poly_x): Likewise.
6102 (vmulltq_int_x): Likewise.
6103 (vmulltq_poly_x): Likewise.
6104 (vmvnq_x): Likewise.
6105 (vrev16q_x): Likewise.
6106 (vrhaddq_x): Likewise.
6107 (vrmulhq_x): Likewise.
6108 (vrshlq_x): Likewise.
6109 (vrshrq_x): Likewise.
6110 (vshllbq_x): Likewise.
6111 (vshlltq_x): Likewise.
6112 (vshlq_x_n): Likewise.
6113 (vshlq_x): Likewise.
6114 (vdwdupq_x_u8): Likewise.
6115 (vdwdupq_x_u16): Likewise.
6116 (vdwdupq_x_u32): Likewise.
6117 (viwdupq_x_u8): Likewise.
6118 (viwdupq_x_u16): Likewise.
6119 (viwdupq_x_u32): Likewise.
6120 (vidupq_x_u8): Likewise.
6121 (vddupq_x_u8): Likewise.
6122 (vidupq_x_u16): Likewise.
6123 (vddupq_x_u16): Likewise.
6124 (vidupq_x_u32): Likewise.
6125 (vddupq_x_u32): Likewise.
6126 (vshrq_x): Likewise.
6128 2020-03-20 Richard Biener <rguenther@suse.de>
6130 * tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
6131 to vectorize for CTOR defs.
6133 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6134 Andre Vieira <andre.simoesdiasvieira@arm.com>
6135 Mihail Ionescu <mihail.ionescu@arm.com>
6137 * config/arm/arm-builtins.c (LDRGBWBS_QUALIFIERS): Define builtin
6139 (LDRGBWBU_QUALIFIERS): Likewise.
6140 (LDRGBWBS_Z_QUALIFIERS): Likewise.
6141 (LDRGBWBU_Z_QUALIFIERS): Likewise.
6142 (STRSBWBS_QUALIFIERS): Likewise.
6143 (STRSBWBU_QUALIFIERS): Likewise.
6144 (STRSBWBS_P_QUALIFIERS): Likewise.
6145 (STRSBWBU_P_QUALIFIERS): Likewise.
6146 * config/arm/arm_mve.h (vldrdq_gather_base_wb_s64): Define macro.
6147 (vldrdq_gather_base_wb_u64): Likewise.
6148 (vldrdq_gather_base_wb_z_s64): Likewise.
6149 (vldrdq_gather_base_wb_z_u64): Likewise.
6150 (vldrwq_gather_base_wb_f32): Likewise.
6151 (vldrwq_gather_base_wb_s32): Likewise.
6152 (vldrwq_gather_base_wb_u32): Likewise.
6153 (vldrwq_gather_base_wb_z_f32): Likewise.
6154 (vldrwq_gather_base_wb_z_s32): Likewise.
6155 (vldrwq_gather_base_wb_z_u32): Likewise.
6156 (vstrdq_scatter_base_wb_p_s64): Likewise.
6157 (vstrdq_scatter_base_wb_p_u64): Likewise.
6158 (vstrdq_scatter_base_wb_s64): Likewise.
6159 (vstrdq_scatter_base_wb_u64): Likewise.
6160 (vstrwq_scatter_base_wb_p_s32): Likewise.
6161 (vstrwq_scatter_base_wb_p_f32): Likewise.
6162 (vstrwq_scatter_base_wb_p_u32): Likewise.
6163 (vstrwq_scatter_base_wb_s32): Likewise.
6164 (vstrwq_scatter_base_wb_u32): Likewise.
6165 (vstrwq_scatter_base_wb_f32): Likewise.
6166 (__arm_vldrdq_gather_base_wb_s64): Define intrinsic.
6167 (__arm_vldrdq_gather_base_wb_u64): Likewise.
6168 (__arm_vldrdq_gather_base_wb_z_s64): Likewise.
6169 (__arm_vldrdq_gather_base_wb_z_u64): Likewise.
6170 (__arm_vldrwq_gather_base_wb_s32): Likewise.
6171 (__arm_vldrwq_gather_base_wb_u32): Likewise.
6172 (__arm_vldrwq_gather_base_wb_z_s32): Likewise.
6173 (__arm_vldrwq_gather_base_wb_z_u32): Likewise.
6174 (__arm_vstrdq_scatter_base_wb_s64): Likewise.
6175 (__arm_vstrdq_scatter_base_wb_u64): Likewise.
6176 (__arm_vstrdq_scatter_base_wb_p_s64): Likewise.
6177 (__arm_vstrdq_scatter_base_wb_p_u64): Likewise.
6178 (__arm_vstrwq_scatter_base_wb_p_s32): Likewise.
6179 (__arm_vstrwq_scatter_base_wb_p_u32): Likewise.
6180 (__arm_vstrwq_scatter_base_wb_s32): Likewise.
6181 (__arm_vstrwq_scatter_base_wb_u32): Likewise.
6182 (__arm_vldrwq_gather_base_wb_f32): Likewise.
6183 (__arm_vldrwq_gather_base_wb_z_f32): Likewise.
6184 (__arm_vstrwq_scatter_base_wb_f32): Likewise.
6185 (__arm_vstrwq_scatter_base_wb_p_f32): Likewise.
6186 (vstrwq_scatter_base_wb): Define polymorphic variant.
6187 (vstrwq_scatter_base_wb_p): Likewise.
6188 (vstrdq_scatter_base_wb_p): Likewise.
6189 (vstrdq_scatter_base_wb): Likewise.
6190 * config/arm/arm_mve_builtins.def (LDRGBWBS_QUALIFIERS): Use builtin
6192 * config/arm/mve.md (mve_vstrwq_scatter_base_wb_<supf>v4si): Define RTL
6194 (mve_vstrwq_scatter_base_wb_add_<supf>v4si): Likewise.
6195 (mve_vstrwq_scatter_base_wb_<supf>v4si_insn): Likewise.
6196 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
6197 (mve_vstrwq_scatter_base_wb_p_add_<supf>v4si): Likewise.
6198 (mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn): Likewise.
6199 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
6200 (mve_vstrwq_scatter_base_wb_add_fv4sf): Likewise.
6201 (mve_vstrwq_scatter_base_wb_fv4sf_insn): Likewise.
6202 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
6203 (mve_vstrwq_scatter_base_wb_p_add_fv4sf): Likewise.
6204 (mve_vstrwq_scatter_base_wb_p_fv4sf_insn): Likewise.
6205 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
6206 (mve_vstrdq_scatter_base_wb_add_<supf>v2di): Likewise.
6207 (mve_vstrdq_scatter_base_wb_<supf>v2di_insn): Likewise.
6208 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
6209 (mve_vstrdq_scatter_base_wb_p_add_<supf>v2di): Likewise.
6210 (mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn): Likewise.
6211 (mve_vldrwq_gather_base_wb_<supf>v4si): Likewise.
6212 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
6213 (mve_vldrwq_gather_base_wb_z_<supf>v4si): Likewise.
6214 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
6215 (mve_vldrwq_gather_base_wb_fv4sf): Likewise.
6216 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
6217 (mve_vldrwq_gather_base_wb_z_fv4sf): Likewise.
6218 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
6219 (mve_vldrdq_gather_base_wb_<supf>v2di): Likewise.
6220 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
6221 (mve_vldrdq_gather_base_wb_z_<supf>v2di): Likewise.
6222 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
6224 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6225 Andre Vieira <andre.simoesdiasvieira@arm.com>
6226 Mihail Ionescu <mihail.ionescu@arm.com>
6228 * config/arm/arm-builtins.c
6229 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Define quinary
6231 * config/arm/arm_mve.h (vddupq_m_n_u8): Define macro.
6232 (vddupq_m_n_u32): Likewise.
6233 (vddupq_m_n_u16): Likewise.
6234 (vddupq_m_wb_u8): Likewise.
6235 (vddupq_m_wb_u16): Likewise.
6236 (vddupq_m_wb_u32): Likewise.
6237 (vddupq_n_u8): Likewise.
6238 (vddupq_n_u32): Likewise.
6239 (vddupq_n_u16): Likewise.
6240 (vddupq_wb_u8): Likewise.
6241 (vddupq_wb_u16): Likewise.
6242 (vddupq_wb_u32): Likewise.
6243 (vdwdupq_m_n_u8): Likewise.
6244 (vdwdupq_m_n_u32): Likewise.
6245 (vdwdupq_m_n_u16): Likewise.
6246 (vdwdupq_m_wb_u8): Likewise.
6247 (vdwdupq_m_wb_u32): Likewise.
6248 (vdwdupq_m_wb_u16): Likewise.
6249 (vdwdupq_n_u8): Likewise.
6250 (vdwdupq_n_u32): Likewise.
6251 (vdwdupq_n_u16): Likewise.
6252 (vdwdupq_wb_u8): Likewise.
6253 (vdwdupq_wb_u32): Likewise.
6254 (vdwdupq_wb_u16): Likewise.
6255 (vidupq_m_n_u8): Likewise.
6256 (vidupq_m_n_u32): Likewise.
6257 (vidupq_m_n_u16): Likewise.
6258 (vidupq_m_wb_u8): Likewise.
6259 (vidupq_m_wb_u16): Likewise.
6260 (vidupq_m_wb_u32): Likewise.
6261 (vidupq_n_u8): Likewise.
6262 (vidupq_n_u32): Likewise.
6263 (vidupq_n_u16): Likewise.
6264 (vidupq_wb_u8): Likewise.
6265 (vidupq_wb_u16): Likewise.
6266 (vidupq_wb_u32): Likewise.
6267 (viwdupq_m_n_u8): Likewise.
6268 (viwdupq_m_n_u32): Likewise.
6269 (viwdupq_m_n_u16): Likewise.
6270 (viwdupq_m_wb_u8): Likewise.
6271 (viwdupq_m_wb_u32): Likewise.
6272 (viwdupq_m_wb_u16): Likewise.
6273 (viwdupq_n_u8): Likewise.
6274 (viwdupq_n_u32): Likewise.
6275 (viwdupq_n_u16): Likewise.
6276 (viwdupq_wb_u8): Likewise.
6277 (viwdupq_wb_u32): Likewise.
6278 (viwdupq_wb_u16): Likewise.
6279 (__arm_vddupq_m_n_u8): Define intrinsic.
6280 (__arm_vddupq_m_n_u32): Likewise.
6281 (__arm_vddupq_m_n_u16): Likewise.
6282 (__arm_vddupq_m_wb_u8): Likewise.
6283 (__arm_vddupq_m_wb_u16): Likewise.
6284 (__arm_vddupq_m_wb_u32): Likewise.
6285 (__arm_vddupq_n_u8): Likewise.
6286 (__arm_vddupq_n_u32): Likewise.
6287 (__arm_vddupq_n_u16): Likewise.
6288 (__arm_vdwdupq_m_n_u8): Likewise.
6289 (__arm_vdwdupq_m_n_u32): Likewise.
6290 (__arm_vdwdupq_m_n_u16): Likewise.
6291 (__arm_vdwdupq_m_wb_u8): Likewise.
6292 (__arm_vdwdupq_m_wb_u32): Likewise.
6293 (__arm_vdwdupq_m_wb_u16): Likewise.
6294 (__arm_vdwdupq_n_u8): Likewise.
6295 (__arm_vdwdupq_n_u32): Likewise.
6296 (__arm_vdwdupq_n_u16): Likewise.
6297 (__arm_vdwdupq_wb_u8): Likewise.
6298 (__arm_vdwdupq_wb_u32): Likewise.
6299 (__arm_vdwdupq_wb_u16): Likewise.
6300 (__arm_vidupq_m_n_u8): Likewise.
6301 (__arm_vidupq_m_n_u32): Likewise.
6302 (__arm_vidupq_m_n_u16): Likewise.
6303 (__arm_vidupq_n_u8): Likewise.
6304 (__arm_vidupq_m_wb_u8): Likewise.
6305 (__arm_vidupq_m_wb_u16): Likewise.
6306 (__arm_vidupq_m_wb_u32): Likewise.
6307 (__arm_vidupq_n_u32): Likewise.
6308 (__arm_vidupq_n_u16): Likewise.
6309 (__arm_vidupq_wb_u8): Likewise.
6310 (__arm_vidupq_wb_u16): Likewise.
6311 (__arm_vidupq_wb_u32): Likewise.
6312 (__arm_vddupq_wb_u8): Likewise.
6313 (__arm_vddupq_wb_u16): Likewise.
6314 (__arm_vddupq_wb_u32): Likewise.
6315 (__arm_viwdupq_m_n_u8): Likewise.
6316 (__arm_viwdupq_m_n_u32): Likewise.
6317 (__arm_viwdupq_m_n_u16): Likewise.
6318 (__arm_viwdupq_m_wb_u8): Likewise.
6319 (__arm_viwdupq_m_wb_u32): Likewise.
6320 (__arm_viwdupq_m_wb_u16): Likewise.
6321 (__arm_viwdupq_n_u8): Likewise.
6322 (__arm_viwdupq_n_u32): Likewise.
6323 (__arm_viwdupq_n_u16): Likewise.
6324 (__arm_viwdupq_wb_u8): Likewise.
6325 (__arm_viwdupq_wb_u32): Likewise.
6326 (__arm_viwdupq_wb_u16): Likewise.
6327 (vidupq_m): Define polymorphic variant.
6328 (vddupq_m): Likewise.
6329 (vidupq_u16): Likewise.
6330 (vidupq_u32): Likewise.
6331 (vidupq_u8): Likewise.
6332 (vddupq_u16): Likewise.
6333 (vddupq_u32): Likewise.
6334 (vddupq_u8): Likewise.
6335 (viwdupq_m): Likewise.
6336 (viwdupq_u16): Likewise.
6337 (viwdupq_u32): Likewise.
6338 (viwdupq_u8): Likewise.
6339 (vdwdupq_m): Likewise.
6340 (vdwdupq_u16): Likewise.
6341 (vdwdupq_u32): Likewise.
6342 (vdwdupq_u8): Likewise.
6343 * config/arm/arm_mve_builtins.def
6344 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Use builtin
6346 * config/arm/mve.md (mve_vidupq_n_u<mode>): Define RTL pattern.
6347 (mve_vidupq_u<mode>_insn): Likewise.
6348 (mve_vidupq_m_n_u<mode>): Likewise.
6349 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
6350 (mve_vddupq_n_u<mode>): Likewise.
6351 (mve_vddupq_u<mode>_insn): Likewise.
6352 (mve_vddupq_m_n_u<mode>): Likewise.
6353 (mve_vddupq_m_wb_u<mode>_insn): Likewise.
6354 (mve_vdwdupq_n_u<mode>): Likewise.
6355 (mve_vdwdupq_wb_u<mode>): Likewise.
6356 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
6357 (mve_vdwdupq_m_n_u<mode>): Likewise.
6358 (mve_vdwdupq_m_wb_u<mode>): Likewise.
6359 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
6360 (mve_viwdupq_n_u<mode>): Likewise.
6361 (mve_viwdupq_wb_u<mode>): Likewise.
6362 (mve_viwdupq_wb_u<mode>_insn): Likewise.
6363 (mve_viwdupq_m_n_u<mode>): Likewise.
6364 (mve_viwdupq_m_wb_u<mode>): Likewise.
6365 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
6367 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6369 * config/arm/arm_mve.h (vreinterpretq_s16_s32): Define macro.
6370 (vreinterpretq_s16_s64): Likewise.
6371 (vreinterpretq_s16_s8): Likewise.
6372 (vreinterpretq_s16_u16): Likewise.
6373 (vreinterpretq_s16_u32): Likewise.
6374 (vreinterpretq_s16_u64): Likewise.
6375 (vreinterpretq_s16_u8): Likewise.
6376 (vreinterpretq_s32_s16): Likewise.
6377 (vreinterpretq_s32_s64): Likewise.
6378 (vreinterpretq_s32_s8): Likewise.
6379 (vreinterpretq_s32_u16): Likewise.
6380 (vreinterpretq_s32_u32): Likewise.
6381 (vreinterpretq_s32_u64): Likewise.
6382 (vreinterpretq_s32_u8): Likewise.
6383 (vreinterpretq_s64_s16): Likewise.
6384 (vreinterpretq_s64_s32): Likewise.
6385 (vreinterpretq_s64_s8): Likewise.
6386 (vreinterpretq_s64_u16): Likewise.
6387 (vreinterpretq_s64_u32): Likewise.
6388 (vreinterpretq_s64_u64): Likewise.
6389 (vreinterpretq_s64_u8): Likewise.
6390 (vreinterpretq_s8_s16): Likewise.
6391 (vreinterpretq_s8_s32): Likewise.
6392 (vreinterpretq_s8_s64): Likewise.
6393 (vreinterpretq_s8_u16): Likewise.
6394 (vreinterpretq_s8_u32): Likewise.
6395 (vreinterpretq_s8_u64): Likewise.
6396 (vreinterpretq_s8_u8): Likewise.
6397 (vreinterpretq_u16_s16): Likewise.
6398 (vreinterpretq_u16_s32): Likewise.
6399 (vreinterpretq_u16_s64): Likewise.
6400 (vreinterpretq_u16_s8): Likewise.
6401 (vreinterpretq_u16_u32): Likewise.
6402 (vreinterpretq_u16_u64): Likewise.
6403 (vreinterpretq_u16_u8): Likewise.
6404 (vreinterpretq_u32_s16): Likewise.
6405 (vreinterpretq_u32_s32): Likewise.
6406 (vreinterpretq_u32_s64): Likewise.
6407 (vreinterpretq_u32_s8): Likewise.
6408 (vreinterpretq_u32_u16): Likewise.
6409 (vreinterpretq_u32_u64): Likewise.
6410 (vreinterpretq_u32_u8): Likewise.
6411 (vreinterpretq_u64_s16): Likewise.
6412 (vreinterpretq_u64_s32): Likewise.
6413 (vreinterpretq_u64_s64): Likewise.
6414 (vreinterpretq_u64_s8): Likewise.
6415 (vreinterpretq_u64_u16): Likewise.
6416 (vreinterpretq_u64_u32): Likewise.
6417 (vreinterpretq_u64_u8): Likewise.
6418 (vreinterpretq_u8_s16): Likewise.
6419 (vreinterpretq_u8_s32): Likewise.
6420 (vreinterpretq_u8_s64): Likewise.
6421 (vreinterpretq_u8_s8): Likewise.
6422 (vreinterpretq_u8_u16): Likewise.
6423 (vreinterpretq_u8_u32): Likewise.
6424 (vreinterpretq_u8_u64): Likewise.
6425 (vreinterpretq_s32_f16): Likewise.
6426 (vreinterpretq_s32_f32): Likewise.
6427 (vreinterpretq_u16_f16): Likewise.
6428 (vreinterpretq_u16_f32): Likewise.
6429 (vreinterpretq_u32_f16): Likewise.
6430 (vreinterpretq_u32_f32): Likewise.
6431 (vreinterpretq_u64_f16): Likewise.
6432 (vreinterpretq_u64_f32): Likewise.
6433 (vreinterpretq_u8_f16): Likewise.
6434 (vreinterpretq_u8_f32): Likewise.
6435 (vreinterpretq_f16_f32): Likewise.
6436 (vreinterpretq_f16_s16): Likewise.
6437 (vreinterpretq_f16_s32): Likewise.
6438 (vreinterpretq_f16_s64): Likewise.
6439 (vreinterpretq_f16_s8): Likewise.
6440 (vreinterpretq_f16_u16): Likewise.
6441 (vreinterpretq_f16_u32): Likewise.
6442 (vreinterpretq_f16_u64): Likewise.
6443 (vreinterpretq_f16_u8): Likewise.
6444 (vreinterpretq_f32_f16): Likewise.
6445 (vreinterpretq_f32_s16): Likewise.
6446 (vreinterpretq_f32_s32): Likewise.
6447 (vreinterpretq_f32_s64): Likewise.
6448 (vreinterpretq_f32_s8): Likewise.
6449 (vreinterpretq_f32_u16): Likewise.
6450 (vreinterpretq_f32_u32): Likewise.
6451 (vreinterpretq_f32_u64): Likewise.
6452 (vreinterpretq_f32_u8): Likewise.
6453 (vreinterpretq_s16_f16): Likewise.
6454 (vreinterpretq_s16_f32): Likewise.
6455 (vreinterpretq_s64_f16): Likewise.
6456 (vreinterpretq_s64_f32): Likewise.
6457 (vreinterpretq_s8_f16): Likewise.
6458 (vreinterpretq_s8_f32): Likewise.
6459 (vuninitializedq_u8): Likewise.
6460 (vuninitializedq_u16): Likewise.
6461 (vuninitializedq_u32): Likewise.
6462 (vuninitializedq_u64): Likewise.
6463 (vuninitializedq_s8): Likewise.
6464 (vuninitializedq_s16): Likewise.
6465 (vuninitializedq_s32): Likewise.
6466 (vuninitializedq_s64): Likewise.
6467 (vuninitializedq_f16): Likewise.
6468 (vuninitializedq_f32): Likewise.
6469 (__arm_vuninitializedq_u8): Define intrinsic.
6470 (__arm_vuninitializedq_u16): Likewise.
6471 (__arm_vuninitializedq_u32): Likewise.
6472 (__arm_vuninitializedq_u64): Likewise.
6473 (__arm_vuninitializedq_s8): Likewise.
6474 (__arm_vuninitializedq_s16): Likewise.
6475 (__arm_vuninitializedq_s32): Likewise.
6476 (__arm_vuninitializedq_s64): Likewise.
6477 (__arm_vreinterpretq_s16_s32): Likewise.
6478 (__arm_vreinterpretq_s16_s64): Likewise.
6479 (__arm_vreinterpretq_s16_s8): Likewise.
6480 (__arm_vreinterpretq_s16_u16): Likewise.
6481 (__arm_vreinterpretq_s16_u32): Likewise.
6482 (__arm_vreinterpretq_s16_u64): Likewise.
6483 (__arm_vreinterpretq_s16_u8): Likewise.
6484 (__arm_vreinterpretq_s32_s16): Likewise.
6485 (__arm_vreinterpretq_s32_s64): Likewise.
6486 (__arm_vreinterpretq_s32_s8): Likewise.
6487 (__arm_vreinterpretq_s32_u16): Likewise.
6488 (__arm_vreinterpretq_s32_u32): Likewise.
6489 (__arm_vreinterpretq_s32_u64): Likewise.
6490 (__arm_vreinterpretq_s32_u8): Likewise.
6491 (__arm_vreinterpretq_s64_s16): Likewise.
6492 (__arm_vreinterpretq_s64_s32): Likewise.
6493 (__arm_vreinterpretq_s64_s8): Likewise.
6494 (__arm_vreinterpretq_s64_u16): Likewise.
6495 (__arm_vreinterpretq_s64_u32): Likewise.
6496 (__arm_vreinterpretq_s64_u64): Likewise.
6497 (__arm_vreinterpretq_s64_u8): Likewise.
6498 (__arm_vreinterpretq_s8_s16): Likewise.
6499 (__arm_vreinterpretq_s8_s32): Likewise.
6500 (__arm_vreinterpretq_s8_s64): Likewise.
6501 (__arm_vreinterpretq_s8_u16): Likewise.
6502 (__arm_vreinterpretq_s8_u32): Likewise.
6503 (__arm_vreinterpretq_s8_u64): Likewise.
6504 (__arm_vreinterpretq_s8_u8): Likewise.
6505 (__arm_vreinterpretq_u16_s16): Likewise.
6506 (__arm_vreinterpretq_u16_s32): Likewise.
6507 (__arm_vreinterpretq_u16_s64): Likewise.
6508 (__arm_vreinterpretq_u16_s8): Likewise.
6509 (__arm_vreinterpretq_u16_u32): Likewise.
6510 (__arm_vreinterpretq_u16_u64): Likewise.
6511 (__arm_vreinterpretq_u16_u8): Likewise.
6512 (__arm_vreinterpretq_u32_s16): Likewise.
6513 (__arm_vreinterpretq_u32_s32): Likewise.
6514 (__arm_vreinterpretq_u32_s64): Likewise.
6515 (__arm_vreinterpretq_u32_s8): Likewise.
6516 (__arm_vreinterpretq_u32_u16): Likewise.
6517 (__arm_vreinterpretq_u32_u64): Likewise.
6518 (__arm_vreinterpretq_u32_u8): Likewise.
6519 (__arm_vreinterpretq_u64_s16): Likewise.
6520 (__arm_vreinterpretq_u64_s32): Likewise.
6521 (__arm_vreinterpretq_u64_s64): Likewise.
6522 (__arm_vreinterpretq_u64_s8): Likewise.
6523 (__arm_vreinterpretq_u64_u16): Likewise.
6524 (__arm_vreinterpretq_u64_u32): Likewise.
6525 (__arm_vreinterpretq_u64_u8): Likewise.
6526 (__arm_vreinterpretq_u8_s16): Likewise.
6527 (__arm_vreinterpretq_u8_s32): Likewise.
6528 (__arm_vreinterpretq_u8_s64): Likewise.
6529 (__arm_vreinterpretq_u8_s8): Likewise.
6530 (__arm_vreinterpretq_u8_u16): Likewise.
6531 (__arm_vreinterpretq_u8_u32): Likewise.
6532 (__arm_vreinterpretq_u8_u64): Likewise.
6533 (__arm_vuninitializedq_f16): Likewise.
6534 (__arm_vuninitializedq_f32): Likewise.
6535 (__arm_vreinterpretq_s32_f16): Likewise.
6536 (__arm_vreinterpretq_s32_f32): Likewise.
6537 (__arm_vreinterpretq_s16_f16): Likewise.
6538 (__arm_vreinterpretq_s16_f32): Likewise.
6539 (__arm_vreinterpretq_s64_f16): Likewise.
6540 (__arm_vreinterpretq_s64_f32): Likewise.
6541 (__arm_vreinterpretq_s8_f16): Likewise.
6542 (__arm_vreinterpretq_s8_f32): Likewise.
6543 (__arm_vreinterpretq_u16_f16): Likewise.
6544 (__arm_vreinterpretq_u16_f32): Likewise.
6545 (__arm_vreinterpretq_u32_f16): Likewise.
6546 (__arm_vreinterpretq_u32_f32): Likewise.
6547 (__arm_vreinterpretq_u64_f16): Likewise.
6548 (__arm_vreinterpretq_u64_f32): Likewise.
6549 (__arm_vreinterpretq_u8_f16): Likewise.
6550 (__arm_vreinterpretq_u8_f32): Likewise.
6551 (__arm_vreinterpretq_f16_f32): Likewise.
6552 (__arm_vreinterpretq_f16_s16): Likewise.
6553 (__arm_vreinterpretq_f16_s32): Likewise.
6554 (__arm_vreinterpretq_f16_s64): Likewise.
6555 (__arm_vreinterpretq_f16_s8): Likewise.
6556 (__arm_vreinterpretq_f16_u16): Likewise.
6557 (__arm_vreinterpretq_f16_u32): Likewise.
6558 (__arm_vreinterpretq_f16_u64): Likewise.
6559 (__arm_vreinterpretq_f16_u8): Likewise.
6560 (__arm_vreinterpretq_f32_f16): Likewise.
6561 (__arm_vreinterpretq_f32_s16): Likewise.
6562 (__arm_vreinterpretq_f32_s32): Likewise.
6563 (__arm_vreinterpretq_f32_s64): Likewise.
6564 (__arm_vreinterpretq_f32_s8): Likewise.
6565 (__arm_vreinterpretq_f32_u16): Likewise.
6566 (__arm_vreinterpretq_f32_u32): Likewise.
6567 (__arm_vreinterpretq_f32_u64): Likewise.
6568 (__arm_vreinterpretq_f32_u8): Likewise.
6569 (vuninitializedq): Define polymorphic variant.
6570 (vreinterpretq_f16): Likewise.
6571 (vreinterpretq_f32): Likewise.
6572 (vreinterpretq_s16): Likewise.
6573 (vreinterpretq_s32): Likewise.
6574 (vreinterpretq_s64): Likewise.
6575 (vreinterpretq_s8): Likewise.
6576 (vreinterpretq_u16): Likewise.
6577 (vreinterpretq_u32): Likewise.
6578 (vreinterpretq_u64): Likewise.
6579 (vreinterpretq_u8): Likewise.
6581 2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6582 Andre Vieira <andre.simoesdiasvieira@arm.com>
6583 Mihail Ionescu <mihail.ionescu@arm.com>
6585 * config/arm/arm_mve.h (vaddq_s8): Define macro.
6586 (vaddq_s16): Likewise.
6587 (vaddq_s32): Likewise.
6588 (vaddq_u8): Likewise.
6589 (vaddq_u16): Likewise.
6590 (vaddq_u32): Likewise.
6591 (vaddq_f16): Likewise.
6592 (vaddq_f32): Likewise.
6593 (__arm_vaddq_s8): Define intrinsic.
6594 (__arm_vaddq_s16): Likewise.
6595 (__arm_vaddq_s32): Likewise.
6596 (__arm_vaddq_u8): Likewise.
6597 (__arm_vaddq_u16): Likewise.
6598 (__arm_vaddq_u32): Likewise.
6599 (__arm_vaddq_f16): Likewise.
6600 (__arm_vaddq_f32): Likewise.
6601 (vaddq): Define polymorphic variant.
6602 * config/arm/iterators.md (VNIM): Define mode iterator for common types
6603 Neon, IWMMXT and MVE.
6604 (VNINOTM): Likewise.
6605 * config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
6606 (mve_vaddq_f<mode>): Define RTL pattern.
6607 * config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
6608 (addv8hf3_neon): Define RTL pattern.
6609 * config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
6611 (addv8hf3): Define standard RTL pattern for MVE and Neon.
6612 (add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.
6614 2020-03-20 Martin Liska <mliska@suse.cz>
6617 * ipa-cp.c (ipa_get_jf_ancestor_result): Use offset in bytes. Previously
6618 build_ref_for_offset function was used and it transforms off to bytes
6621 2020-03-20 Richard Biener <rguenther@suse.de>
6623 PR tree-optimization/94266
6624 * gimple-ssa-sprintf.c (get_origin_and_offset): Use the
6625 type of the underlying object to adjust for the containing
6628 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6630 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
6631 (VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
6632 * config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
6634 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6636 * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
6638 2020-03-20 Jakub Jelinek <jakub@redhat.com>
6640 PR tree-optimization/94224
6641 * gimple-ssa-store-merging.c
6642 (imm_store_chain_info::coalesce_immediate): Don't consider overlapping
6643 or adjacent INTEGER_CST rhs_code stores as mergeable if they have
6646 2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
6648 * config/arm/arm.md (define_attr "conds"): Fix logic for neon and mve.
6650 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6653 * cgraph.c (cgraph_node::function_symbol): Fix availability computation.
6654 (cgraph_node::function_or_virtual_thunk_symbol): Likewise.
6656 2020-03-19 Jan Hubicka <hubicka@ucw.cz>
6659 * cgraphunit.c (process_function_and_variable_attributes): warn
6660 for flatten attribute on alias.
6661 * ipa-inline.c (ipa_inline): Do not ICE on flatten attribute on alias.
6663 2020-03-19 Martin Liska <mliska@suse.cz>
6665 * lto-section-in.c: Add ext_symtab.
6666 * lto-streamer-out.c (write_symbol_extension_info): New.
6667 (produce_symtab_extension): New.
6668 (produce_asm_for_decls): Stream also produce_symtab_extension.
6669 * lto-streamer.h (enum lto_section_type): New section.
6671 2020-03-19 Jakub Jelinek <jakub@redhat.com>
6673 PR tree-optimization/94211
6674 * tree-ssa-phiopt.c (value_replacement): Use estimate_num_insns_seq
6675 instead of estimate_num_insns for bb_seq (middle_bb). Rename
6676 emtpy_or_with_defined_p variable to empty_or_with_defined_p, adjust
6679 2020-03-19 Richard Biener <rguenther@suse.de>
6682 * ipa-cp.c (ipa_get_jf_ancestor_result): Avoid build_fold_addr_expr
6683 and build_ref_for_offset.
6685 2020-03-19 Richard Biener <rguenther@suse.de>
6688 * fold-const.c (fold_binary_loc): Avoid using
6689 build_fold_addr_expr when we really want an ADDR_EXPR.
6691 2020-03-18 Segher Boessenkool <segher@kernel.crashing.org>
6693 * config/rs6000/constraints.md (wd, wf, wi, ws, ww): New undocumented
6696 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
6698 PR rtl-optimization/90275
6699 * cse.c (cse_insn): Delete no-op register moves too.
6701 2020-03-18 Martin Sebor <msebor@redhat.com>
6704 * cgraphunit.c (process_function_and_variable_attributes): Also
6705 complain about weakref function definitions and drop all effects
6708 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6709 Mihail Ionescu <mihail.ionescu@arm.com>
6710 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6712 * config/arm/arm_mve.h (vstrdq_scatter_base_p_s64): Define macro.
6713 (vstrdq_scatter_base_p_u64): Likewise.
6714 (vstrdq_scatter_base_s64): Likewise.
6715 (vstrdq_scatter_base_u64): Likewise.
6716 (vstrdq_scatter_offset_p_s64): Likewise.
6717 (vstrdq_scatter_offset_p_u64): Likewise.
6718 (vstrdq_scatter_offset_s64): Likewise.
6719 (vstrdq_scatter_offset_u64): Likewise.
6720 (vstrdq_scatter_shifted_offset_p_s64): Likewise.
6721 (vstrdq_scatter_shifted_offset_p_u64): Likewise.
6722 (vstrdq_scatter_shifted_offset_s64): Likewise.
6723 (vstrdq_scatter_shifted_offset_u64): Likewise.
6724 (vstrhq_scatter_offset_f16): Likewise.
6725 (vstrhq_scatter_offset_p_f16): Likewise.
6726 (vstrhq_scatter_shifted_offset_f16): Likewise.
6727 (vstrhq_scatter_shifted_offset_p_f16): Likewise.
6728 (vstrwq_scatter_base_f32): Likewise.
6729 (vstrwq_scatter_base_p_f32): Likewise.
6730 (vstrwq_scatter_offset_f32): Likewise.
6731 (vstrwq_scatter_offset_p_f32): Likewise.
6732 (vstrwq_scatter_offset_p_s32): Likewise.
6733 (vstrwq_scatter_offset_p_u32): Likewise.
6734 (vstrwq_scatter_offset_s32): Likewise.
6735 (vstrwq_scatter_offset_u32): Likewise.
6736 (vstrwq_scatter_shifted_offset_f32): Likewise.
6737 (vstrwq_scatter_shifted_offset_p_f32): Likewise.
6738 (vstrwq_scatter_shifted_offset_p_s32): Likewise.
6739 (vstrwq_scatter_shifted_offset_p_u32): Likewise.
6740 (vstrwq_scatter_shifted_offset_s32): Likewise.
6741 (vstrwq_scatter_shifted_offset_u32): Likewise.
6742 (__arm_vstrdq_scatter_base_p_s64): Define intrinsic.
6743 (__arm_vstrdq_scatter_base_p_u64): Likewise.
6744 (__arm_vstrdq_scatter_base_s64): Likewise.
6745 (__arm_vstrdq_scatter_base_u64): Likewise.
6746 (__arm_vstrdq_scatter_offset_p_s64): Likewise.
6747 (__arm_vstrdq_scatter_offset_p_u64): Likewise.
6748 (__arm_vstrdq_scatter_offset_s64): Likewise.
6749 (__arm_vstrdq_scatter_offset_u64): Likewise.
6750 (__arm_vstrdq_scatter_shifted_offset_p_s64): Likewise.
6751 (__arm_vstrdq_scatter_shifted_offset_p_u64): Likewise.
6752 (__arm_vstrdq_scatter_shifted_offset_s64): Likewise.
6753 (__arm_vstrdq_scatter_shifted_offset_u64): Likewise.
6754 (__arm_vstrwq_scatter_offset_p_s32): Likewise.
6755 (__arm_vstrwq_scatter_offset_p_u32): Likewise.
6756 (__arm_vstrwq_scatter_offset_s32): Likewise.
6757 (__arm_vstrwq_scatter_offset_u32): Likewise.
6758 (__arm_vstrwq_scatter_shifted_offset_p_s32): Likewise.
6759 (__arm_vstrwq_scatter_shifted_offset_p_u32): Likewise.
6760 (__arm_vstrwq_scatter_shifted_offset_s32): Likewise.
6761 (__arm_vstrwq_scatter_shifted_offset_u32): Likewise.
6762 (__arm_vstrhq_scatter_offset_f16): Likewise.
6763 (__arm_vstrhq_scatter_offset_p_f16): Likewise.
6764 (__arm_vstrhq_scatter_shifted_offset_f16): Likewise.
6765 (__arm_vstrhq_scatter_shifted_offset_p_f16): Likewise.
6766 (__arm_vstrwq_scatter_base_f32): Likewise.
6767 (__arm_vstrwq_scatter_base_p_f32): Likewise.
6768 (__arm_vstrwq_scatter_offset_f32): Likewise.
6769 (__arm_vstrwq_scatter_offset_p_f32): Likewise.
6770 (__arm_vstrwq_scatter_shifted_offset_f32): Likewise.
6771 (__arm_vstrwq_scatter_shifted_offset_p_f32): Likewise.
6772 (vstrhq_scatter_offset): Define polymorphic variant.
6773 (vstrhq_scatter_offset_p): Likewise.
6774 (vstrhq_scatter_shifted_offset): Likewise.
6775 (vstrhq_scatter_shifted_offset_p): Likewise.
6776 (vstrwq_scatter_base): Likewise.
6777 (vstrwq_scatter_base_p): Likewise.
6778 (vstrwq_scatter_offset): Likewise.
6779 (vstrwq_scatter_offset_p): Likewise.
6780 (vstrwq_scatter_shifted_offset): Likewise.
6781 (vstrwq_scatter_shifted_offset_p): Likewise.
6782 (vstrdq_scatter_base_p): Likewise.
6783 (vstrdq_scatter_base): Likewise.
6784 (vstrdq_scatter_offset_p): Likewise.
6785 (vstrdq_scatter_offset): Likewise.
6786 (vstrdq_scatter_shifted_offset_p): Likewise.
6787 (vstrdq_scatter_shifted_offset): Likewise.
6788 * config/arm/arm_mve_builtins.def (STRSBS): Use builtin qualifier.
6789 (STRSBS_P): Likewise.
6791 (STRSBU_P): Likewise.
6793 (STRSS_P): Likewise.
6795 (STRSU_P): Likewise.
6796 * config/arm/constraints.md (Ri): Define.
6797 * config/arm/mve.md (VSTRDSBQ): Define iterator.
6798 (VSTRDSOQ): Likewise.
6799 (VSTRDSSOQ): Likewise.
6800 (VSTRWSOQ): Likewise.
6801 (VSTRWSSOQ): Likewise.
6802 (mve_vstrdq_scatter_base_p_<supf>v2di): Define RTL pattern.
6803 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
6804 (mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
6805 (mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
6806 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
6807 (mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
6808 (mve_vstrhq_scatter_offset_fv8hf): Likewise.
6809 (mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
6810 (mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
6811 (mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
6812 (mve_vstrwq_scatter_base_fv4sf): Likewise.
6813 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
6814 (mve_vstrwq_scatter_offset_fv4sf): Likewise.
6815 (mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
6816 (mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
6817 (mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
6818 (mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
6819 (mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
6820 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
6821 (mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
6822 * config/arm/predicates.md (Ri): Define predicate to check immediate
6823 is the range +/-1016 and multiple of 8.
6825 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6826 Mihail Ionescu <mihail.ionescu@arm.com>
6827 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6829 * config/arm/arm_mve.h (vst1q_f32): Define macro.
6830 (vst1q_f16): Likewise.
6831 (vst1q_s8): Likewise.
6832 (vst1q_s32): Likewise.
6833 (vst1q_s16): Likewise.
6834 (vst1q_u8): Likewise.
6835 (vst1q_u32): Likewise.
6836 (vst1q_u16): Likewise.
6837 (vstrhq_f16): Likewise.
6838 (vstrhq_scatter_offset_s32): Likewise.
6839 (vstrhq_scatter_offset_s16): Likewise.
6840 (vstrhq_scatter_offset_u32): Likewise.
6841 (vstrhq_scatter_offset_u16): Likewise.
6842 (vstrhq_scatter_offset_p_s32): Likewise.
6843 (vstrhq_scatter_offset_p_s16): Likewise.
6844 (vstrhq_scatter_offset_p_u32): Likewise.
6845 (vstrhq_scatter_offset_p_u16): Likewise.
6846 (vstrhq_scatter_shifted_offset_s32): Likewise.
6847 (vstrhq_scatter_shifted_offset_s16): Likewise.
6848 (vstrhq_scatter_shifted_offset_u32): Likewise.
6849 (vstrhq_scatter_shifted_offset_u16): Likewise.
6850 (vstrhq_scatter_shifted_offset_p_s32): Likewise.
6851 (vstrhq_scatter_shifted_offset_p_s16): Likewise.
6852 (vstrhq_scatter_shifted_offset_p_u32): Likewise.
6853 (vstrhq_scatter_shifted_offset_p_u16): Likewise.
6854 (vstrhq_s32): Likewise.
6855 (vstrhq_s16): Likewise.
6856 (vstrhq_u32): Likewise.
6857 (vstrhq_u16): Likewise.
6858 (vstrhq_p_f16): Likewise.
6859 (vstrhq_p_s32): Likewise.
6860 (vstrhq_p_s16): Likewise.
6861 (vstrhq_p_u32): Likewise.
6862 (vstrhq_p_u16): Likewise.
6863 (vstrwq_f32): Likewise.
6864 (vstrwq_s32): Likewise.
6865 (vstrwq_u32): Likewise.
6866 (vstrwq_p_f32): Likewise.
6867 (vstrwq_p_s32): Likewise.
6868 (vstrwq_p_u32): Likewise.
6869 (__arm_vst1q_s8): Define intrinsic.
6870 (__arm_vst1q_s32): Likewise.
6871 (__arm_vst1q_s16): Likewise.
6872 (__arm_vst1q_u8): Likewise.
6873 (__arm_vst1q_u32): Likewise.
6874 (__arm_vst1q_u16): Likewise.
6875 (__arm_vstrhq_scatter_offset_s32): Likewise.
6876 (__arm_vstrhq_scatter_offset_s16): Likewise.
6877 (__arm_vstrhq_scatter_offset_u32): Likewise.
6878 (__arm_vstrhq_scatter_offset_u16): Likewise.
6879 (__arm_vstrhq_scatter_offset_p_s32): Likewise.
6880 (__arm_vstrhq_scatter_offset_p_s16): Likewise.
6881 (__arm_vstrhq_scatter_offset_p_u32): Likewise.
6882 (__arm_vstrhq_scatter_offset_p_u16): Likewise.
6883 (__arm_vstrhq_scatter_shifted_offset_s32): Likewise.
6884 (__arm_vstrhq_scatter_shifted_offset_s16): Likewise.
6885 (__arm_vstrhq_scatter_shifted_offset_u32): Likewise.
6886 (__arm_vstrhq_scatter_shifted_offset_u16): Likewise.
6887 (__arm_vstrhq_scatter_shifted_offset_p_s32): Likewise.
6888 (__arm_vstrhq_scatter_shifted_offset_p_s16): Likewise.
6889 (__arm_vstrhq_scatter_shifted_offset_p_u32): Likewise.
6890 (__arm_vstrhq_scatter_shifted_offset_p_u16): Likewise.
6891 (__arm_vstrhq_s32): Likewise.
6892 (__arm_vstrhq_s16): Likewise.
6893 (__arm_vstrhq_u32): Likewise.
6894 (__arm_vstrhq_u16): Likewise.
6895 (__arm_vstrhq_p_s32): Likewise.
6896 (__arm_vstrhq_p_s16): Likewise.
6897 (__arm_vstrhq_p_u32): Likewise.
6898 (__arm_vstrhq_p_u16): Likewise.
6899 (__arm_vstrwq_s32): Likewise.
6900 (__arm_vstrwq_u32): Likewise.
6901 (__arm_vstrwq_p_s32): Likewise.
6902 (__arm_vstrwq_p_u32): Likewise.
6903 (__arm_vstrwq_p_f32): Likewise.
6904 (__arm_vstrwq_f32): Likewise.
6905 (__arm_vst1q_f32): Likewise.
6906 (__arm_vst1q_f16): Likewise.
6907 (__arm_vstrhq_f16): Likewise.
6908 (__arm_vstrhq_p_f16): Likewise.
6909 (vst1q): Define polymorphic variant.
6911 (vstrhq_p): Likewise.
6912 (vstrhq_scatter_offset_p): Likewise.
6913 (vstrhq_scatter_offset): Likewise.
6914 (vstrhq_scatter_shifted_offset_p): Likewise.
6915 (vstrhq_scatter_shifted_offset): Likewise.
6916 (vstrwq_p): Likewise.
6918 * config/arm/arm_mve_builtins.def (STRS): Use builtin qualifier.
6921 (STRSS_P): Likewise.
6923 (STRSU_P): Likewise.
6926 * config/arm/mve.md (VST1Q): Define iterator.
6927 (VSTRHSOQ): Likewise.
6928 (VSTRHSSOQ): Likewise.
6931 (mve_vstrhq_fv8hf): Define RTL pattern.
6932 (mve_vstrhq_p_fv8hf): Likewise.
6933 (mve_vstrhq_p_<supf><mode>): Likewise.
6934 (mve_vstrhq_scatter_offset_p_<supf><mode>): Likewise.
6935 (mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
6936 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
6937 (mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
6938 (mve_vstrhq_<supf><mode>): Likewise.
6939 (mve_vstrwq_fv4sf): Likewise.
6940 (mve_vstrwq_p_fv4sf): Likewise.
6941 (mve_vstrwq_p_<supf>v4si): Likewise.
6942 (mve_vstrwq_<supf>v4si): Likewise.
6943 (mve_vst1q_f<mode>): Define expand.
6944 (mve_vst1q_<supf><mode>): Likewise.
6946 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
6947 Mihail Ionescu <mihail.ionescu@arm.com>
6948 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
6950 * config/arm/arm_mve.h (vld1q_s8): Define macro.
6951 (vld1q_s32): Likewise.
6952 (vld1q_s16): Likewise.
6953 (vld1q_u8): Likewise.
6954 (vld1q_u32): Likewise.
6955 (vld1q_u16): Likewise.
6956 (vldrhq_gather_offset_s32): Likewise.
6957 (vldrhq_gather_offset_s16): Likewise.
6958 (vldrhq_gather_offset_u32): Likewise.
6959 (vldrhq_gather_offset_u16): Likewise.
6960 (vldrhq_gather_offset_z_s32): Likewise.
6961 (vldrhq_gather_offset_z_s16): Likewise.
6962 (vldrhq_gather_offset_z_u32): Likewise.
6963 (vldrhq_gather_offset_z_u16): Likewise.
6964 (vldrhq_gather_shifted_offset_s32): Likewise.
6965 (vldrhq_gather_shifted_offset_s16): Likewise.
6966 (vldrhq_gather_shifted_offset_u32): Likewise.
6967 (vldrhq_gather_shifted_offset_u16): Likewise.
6968 (vldrhq_gather_shifted_offset_z_s32): Likewise.
6969 (vldrhq_gather_shifted_offset_z_s16): Likewise.
6970 (vldrhq_gather_shifted_offset_z_u32): Likewise.
6971 (vldrhq_gather_shifted_offset_z_u16): Likewise.
6972 (vldrhq_s32): Likewise.
6973 (vldrhq_s16): Likewise.
6974 (vldrhq_u32): Likewise.
6975 (vldrhq_u16): Likewise.
6976 (vldrhq_z_s32): Likewise.
6977 (vldrhq_z_s16): Likewise.
6978 (vldrhq_z_u32): Likewise.
6979 (vldrhq_z_u16): Likewise.
6980 (vldrwq_s32): Likewise.
6981 (vldrwq_u32): Likewise.
6982 (vldrwq_z_s32): Likewise.
6983 (vldrwq_z_u32): Likewise.
6984 (vld1q_f32): Likewise.
6985 (vld1q_f16): Likewise.
6986 (vldrhq_f16): Likewise.
6987 (vldrhq_z_f16): Likewise.
6988 (vldrwq_f32): Likewise.
6989 (vldrwq_z_f32): Likewise.
6990 (__arm_vld1q_s8): Define intrinsic.
6991 (__arm_vld1q_s32): Likewise.
6992 (__arm_vld1q_s16): Likewise.
6993 (__arm_vld1q_u8): Likewise.
6994 (__arm_vld1q_u32): Likewise.
6995 (__arm_vld1q_u16): Likewise.
6996 (__arm_vldrhq_gather_offset_s32): Likewise.
6997 (__arm_vldrhq_gather_offset_s16): Likewise.
6998 (__arm_vldrhq_gather_offset_u32): Likewise.
6999 (__arm_vldrhq_gather_offset_u16): Likewise.
7000 (__arm_vldrhq_gather_offset_z_s32): Likewise.
7001 (__arm_vldrhq_gather_offset_z_s16): Likewise.
7002 (__arm_vldrhq_gather_offset_z_u32): Likewise.
7003 (__arm_vldrhq_gather_offset_z_u16): Likewise.
7004 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
7005 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
7006 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
7007 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
7008 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
7009 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
7010 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
7011 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
7012 (__arm_vldrhq_s32): Likewise.
7013 (__arm_vldrhq_s16): Likewise.
7014 (__arm_vldrhq_u32): Likewise.
7015 (__arm_vldrhq_u16): Likewise.
7016 (__arm_vldrhq_z_s32): Likewise.
7017 (__arm_vldrhq_z_s16): Likewise.
7018 (__arm_vldrhq_z_u32): Likewise.
7019 (__arm_vldrhq_z_u16): Likewise.
7020 (__arm_vldrwq_s32): Likewise.
7021 (__arm_vldrwq_u32): Likewise.
7022 (__arm_vldrwq_z_s32): Likewise.
7023 (__arm_vldrwq_z_u32): Likewise.
7024 (__arm_vld1q_f32): Likewise.
7025 (__arm_vld1q_f16): Likewise.
7026 (__arm_vldrwq_f32): Likewise.
7027 (__arm_vldrwq_z_f32): Likewise.
7028 (__arm_vldrhq_z_f16): Likewise.
7029 (__arm_vldrhq_f16): Likewise.
7030 (vld1q): Define polymorphic variant.
7031 (vldrhq_gather_offset): Likewise.
7032 (vldrhq_gather_offset_z): Likewise.
7033 (vldrhq_gather_shifted_offset): Likewise.
7034 (vldrhq_gather_shifted_offset_z): Likewise.
7035 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
7039 (LDRGU_Z): Likewise.
7041 (LDRGS_Z): Likewise.
7043 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
7044 (V_sz_elem1): Likewise.
7045 (VLD1Q): Define iterator.
7046 (VLDRHGOQ): Likewise.
7047 (VLDRHGSOQ): Likewise.
7050 (mve_vldrhq_fv8hf): Define RTL pattern.
7051 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
7052 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
7053 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
7054 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
7055 (mve_vldrhq_<supf><mode>): Likewise.
7056 (mve_vldrhq_z_fv8hf): Likewise.
7057 (mve_vldrhq_z_<supf><mode>): Likewise.
7058 (mve_vldrwq_fv4sf): Likewise.
7059 (mve_vldrwq_<supf>v4si): Likewise.
7060 (mve_vldrwq_z_fv4sf): Likewise.
7061 (mve_vldrwq_z_<supf>v4si): Likewise.
7062 (mve_vld1q_f<mode>): Define RTL expand pattern.
7063 (mve_vld1q_<supf><mode>): Likewise.
7065 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7066 Mihail Ionescu <mihail.ionescu@arm.com>
7067 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7069 * config/arm/arm_mve.h (vld1q_s8): Define macro.
7070 (vld1q_s32): Likewise.
7071 (vld1q_s16): Likewise.
7072 (vld1q_u8): Likewise.
7073 (vld1q_u32): Likewise.
7074 (vld1q_u16): Likewise.
7075 (vldrhq_gather_offset_s32): Likewise.
7076 (vldrhq_gather_offset_s16): Likewise.
7077 (vldrhq_gather_offset_u32): Likewise.
7078 (vldrhq_gather_offset_u16): Likewise.
7079 (vldrhq_gather_offset_z_s32): Likewise.
7080 (vldrhq_gather_offset_z_s16): Likewise.
7081 (vldrhq_gather_offset_z_u32): Likewise.
7082 (vldrhq_gather_offset_z_u16): Likewise.
7083 (vldrhq_gather_shifted_offset_s32): Likewise.
7084 (vldrhq_gather_shifted_offset_s16): Likewise.
7085 (vldrhq_gather_shifted_offset_u32): Likewise.
7086 (vldrhq_gather_shifted_offset_u16): Likewise.
7087 (vldrhq_gather_shifted_offset_z_s32): Likewise.
7088 (vldrhq_gather_shifted_offset_z_s16): Likewise.
7089 (vldrhq_gather_shifted_offset_z_u32): Likewise.
7090 (vldrhq_gather_shifted_offset_z_u16): Likewise.
7091 (vldrhq_s32): Likewise.
7092 (vldrhq_s16): Likewise.
7093 (vldrhq_u32): Likewise.
7094 (vldrhq_u16): Likewise.
7095 (vldrhq_z_s32): Likewise.
7096 (vldrhq_z_s16): Likewise.
7097 (vldrhq_z_u32): Likewise.
7098 (vldrhq_z_u16): Likewise.
7099 (vldrwq_s32): Likewise.
7100 (vldrwq_u32): Likewise.
7101 (vldrwq_z_s32): Likewise.
7102 (vldrwq_z_u32): Likewise.
7103 (vld1q_f32): Likewise.
7104 (vld1q_f16): Likewise.
7105 (vldrhq_f16): Likewise.
7106 (vldrhq_z_f16): Likewise.
7107 (vldrwq_f32): Likewise.
7108 (vldrwq_z_f32): Likewise.
7109 (__arm_vld1q_s8): Define intrinsic.
7110 (__arm_vld1q_s32): Likewise.
7111 (__arm_vld1q_s16): Likewise.
7112 (__arm_vld1q_u8): Likewise.
7113 (__arm_vld1q_u32): Likewise.
7114 (__arm_vld1q_u16): Likewise.
7115 (__arm_vldrhq_gather_offset_s32): Likewise.
7116 (__arm_vldrhq_gather_offset_s16): Likewise.
7117 (__arm_vldrhq_gather_offset_u32): Likewise.
7118 (__arm_vldrhq_gather_offset_u16): Likewise.
7119 (__arm_vldrhq_gather_offset_z_s32): Likewise.
7120 (__arm_vldrhq_gather_offset_z_s16): Likewise.
7121 (__arm_vldrhq_gather_offset_z_u32): Likewise.
7122 (__arm_vldrhq_gather_offset_z_u16): Likewise.
7123 (__arm_vldrhq_gather_shifted_offset_s32): Likewise.
7124 (__arm_vldrhq_gather_shifted_offset_s16): Likewise.
7125 (__arm_vldrhq_gather_shifted_offset_u32): Likewise.
7126 (__arm_vldrhq_gather_shifted_offset_u16): Likewise.
7127 (__arm_vldrhq_gather_shifted_offset_z_s32): Likewise.
7128 (__arm_vldrhq_gather_shifted_offset_z_s16): Likewise.
7129 (__arm_vldrhq_gather_shifted_offset_z_u32): Likewise.
7130 (__arm_vldrhq_gather_shifted_offset_z_u16): Likewise.
7131 (__arm_vldrhq_s32): Likewise.
7132 (__arm_vldrhq_s16): Likewise.
7133 (__arm_vldrhq_u32): Likewise.
7134 (__arm_vldrhq_u16): Likewise.
7135 (__arm_vldrhq_z_s32): Likewise.
7136 (__arm_vldrhq_z_s16): Likewise.
7137 (__arm_vldrhq_z_u32): Likewise.
7138 (__arm_vldrhq_z_u16): Likewise.
7139 (__arm_vldrwq_s32): Likewise.
7140 (__arm_vldrwq_u32): Likewise.
7141 (__arm_vldrwq_z_s32): Likewise.
7142 (__arm_vldrwq_z_u32): Likewise.
7143 (__arm_vld1q_f32): Likewise.
7144 (__arm_vld1q_f16): Likewise.
7145 (__arm_vldrwq_f32): Likewise.
7146 (__arm_vldrwq_z_f32): Likewise.
7147 (__arm_vldrhq_z_f16): Likewise.
7148 (__arm_vldrhq_f16): Likewise.
7149 (vld1q): Define polymorphic variant.
7150 (vldrhq_gather_offset): Likewise.
7151 (vldrhq_gather_offset_z): Likewise.
7152 (vldrhq_gather_shifted_offset): Likewise.
7153 (vldrhq_gather_shifted_offset_z): Likewise.
7154 * config/arm/arm_mve_builtins.def (LDRU): Use builtin qualifier.
7158 (LDRGU_Z): Likewise.
7160 (LDRGS_Z): Likewise.
7162 * config/arm/mve.md (MVE_H_ELEM): Define mode iterator.
7163 (V_sz_elem1): Likewise.
7164 (VLD1Q): Define iterator.
7165 (VLDRHGOQ): Likewise.
7166 (VLDRHGSOQ): Likewise.
7169 (mve_vldrhq_fv8hf): Define RTL pattern.
7170 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
7171 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
7172 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
7173 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
7174 (mve_vldrhq_<supf><mode>): Likewise.
7175 (mve_vldrhq_z_fv8hf): Likewise.
7176 (mve_vldrhq_z_<supf><mode>): Likewise.
7177 (mve_vldrwq_fv4sf): Likewise.
7178 (mve_vldrwq_<supf>v4si): Likewise.
7179 (mve_vldrwq_z_fv4sf): Likewise.
7180 (mve_vldrwq_z_<supf>v4si): Likewise.
7181 (mve_vld1q_f<mode>): Define RTL expand pattern.
7182 (mve_vld1q_<supf><mode>): Likewise.
7184 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7185 Mihail Ionescu <mihail.ionescu@arm.com>
7186 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7188 * config/arm/arm-builtins.c (LDRGBS_Z_QUALIFIERS): Define builtin
7190 (LDRGBU_Z_QUALIFIERS): Likewise.
7191 (LDRGS_Z_QUALIFIERS): Likewise.
7192 (LDRGU_Z_QUALIFIERS): Likewise.
7193 (LDRS_Z_QUALIFIERS): Likewise.
7194 (LDRU_Z_QUALIFIERS): Likewise.
7195 * config/arm/arm_mve.h (vldrbq_gather_offset_z_s16): Define macro.
7196 (vldrbq_gather_offset_z_u8): Likewise.
7197 (vldrbq_gather_offset_z_s32): Likewise.
7198 (vldrbq_gather_offset_z_u16): Likewise.
7199 (vldrbq_gather_offset_z_u32): Likewise.
7200 (vldrbq_gather_offset_z_s8): Likewise.
7201 (vldrbq_z_s16): Likewise.
7202 (vldrbq_z_u8): Likewise.
7203 (vldrbq_z_s8): Likewise.
7204 (vldrbq_z_s32): Likewise.
7205 (vldrbq_z_u16): Likewise.
7206 (vldrbq_z_u32): Likewise.
7207 (vldrwq_gather_base_z_u32): Likewise.
7208 (vldrwq_gather_base_z_s32): Likewise.
7209 (__arm_vldrbq_gather_offset_z_s8): Define intrinsic.
7210 (__arm_vldrbq_gather_offset_z_s32): Likewise.
7211 (__arm_vldrbq_gather_offset_z_s16): Likewise.
7212 (__arm_vldrbq_gather_offset_z_u8): Likewise.
7213 (__arm_vldrbq_gather_offset_z_u32): Likewise.
7214 (__arm_vldrbq_gather_offset_z_u16): Likewise.
7215 (__arm_vldrbq_z_s8): Likewise.
7216 (__arm_vldrbq_z_s32): Likewise.
7217 (__arm_vldrbq_z_s16): Likewise.
7218 (__arm_vldrbq_z_u8): Likewise.
7219 (__arm_vldrbq_z_u32): Likewise.
7220 (__arm_vldrbq_z_u16): Likewise.
7221 (__arm_vldrwq_gather_base_z_s32): Likewise.
7222 (__arm_vldrwq_gather_base_z_u32): Likewise.
7223 (vldrbq_gather_offset_z): Define polymorphic variant.
7224 * config/arm/arm_mve_builtins.def (LDRGBS_Z_QUALIFIERS): Use builtin
7226 (LDRGBU_Z_QUALIFIERS): Likewise.
7227 (LDRGS_Z_QUALIFIERS): Likewise.
7228 (LDRGU_Z_QUALIFIERS): Likewise.
7229 (LDRS_Z_QUALIFIERS): Likewise.
7230 (LDRU_Z_QUALIFIERS): Likewise.
7231 * config/arm/mve.md (mve_vldrbq_gather_offset_z_<supf><mode>): Define
7233 (mve_vldrbq_z_<supf><mode>): Likewise.
7234 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
7236 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7237 Mihail Ionescu <mihail.ionescu@arm.com>
7238 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7240 * config/arm/arm-builtins.c (STRS_P_QUALIFIERS): Define builtin
7242 (STRU_P_QUALIFIERS): Likewise.
7243 (STRSU_P_QUALIFIERS): Likewise.
7244 (STRSS_P_QUALIFIERS): Likewise.
7245 (STRSBS_P_QUALIFIERS): Likewise.
7246 (STRSBU_P_QUALIFIERS): Likewise.
7247 * config/arm/arm_mve.h (vstrbq_p_s8): Define macro.
7248 (vstrbq_p_s32): Likewise.
7249 (vstrbq_p_s16): Likewise.
7250 (vstrbq_p_u8): Likewise.
7251 (vstrbq_p_u32): Likewise.
7252 (vstrbq_p_u16): Likewise.
7253 (vstrbq_scatter_offset_p_s8): Likewise.
7254 (vstrbq_scatter_offset_p_s32): Likewise.
7255 (vstrbq_scatter_offset_p_s16): Likewise.
7256 (vstrbq_scatter_offset_p_u8): Likewise.
7257 (vstrbq_scatter_offset_p_u32): Likewise.
7258 (vstrbq_scatter_offset_p_u16): Likewise.
7259 (vstrwq_scatter_base_p_s32): Likewise.
7260 (vstrwq_scatter_base_p_u32): Likewise.
7261 (__arm_vstrbq_p_s8): Define intrinsic.
7262 (__arm_vstrbq_p_s32): Likewise.
7263 (__arm_vstrbq_p_s16): Likewise.
7264 (__arm_vstrbq_p_u8): Likewise.
7265 (__arm_vstrbq_p_u32): Likewise.
7266 (__arm_vstrbq_p_u16): Likewise.
7267 (__arm_vstrbq_scatter_offset_p_s8): Likewise.
7268 (__arm_vstrbq_scatter_offset_p_s32): Likewise.
7269 (__arm_vstrbq_scatter_offset_p_s16): Likewise.
7270 (__arm_vstrbq_scatter_offset_p_u8): Likewise.
7271 (__arm_vstrbq_scatter_offset_p_u32): Likewise.
7272 (__arm_vstrbq_scatter_offset_p_u16): Likewise.
7273 (__arm_vstrwq_scatter_base_p_s32): Likewise.
7274 (__arm_vstrwq_scatter_base_p_u32): Likewise.
7275 (vstrbq_p): Define polymorphic variant.
7276 (vstrbq_scatter_offset_p): Likewise.
7277 (vstrwq_scatter_base_p): Likewise.
7278 * config/arm/arm_mve_builtins.def (STRS_P_QUALIFIERS): Use builtin
7280 (STRU_P_QUALIFIERS): Likewise.
7281 (STRSU_P_QUALIFIERS): Likewise.
7282 (STRSS_P_QUALIFIERS): Likewise.
7283 (STRSBS_P_QUALIFIERS): Likewise.
7284 (STRSBU_P_QUALIFIERS): Likewise.
7285 * config/arm/mve.md (mve_vstrbq_scatter_offset_p_<supf><mode>): Define
7287 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
7288 (mve_vstrbq_p_<supf><mode>): Likewise.
7290 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7291 Mihail Ionescu <mihail.ionescu@arm.com>
7292 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7294 * config/arm/arm-builtins.c (LDRGU_QUALIFIERS): Define builtin
7296 (LDRGS_QUALIFIERS): Likewise.
7297 (LDRS_QUALIFIERS): Likewise.
7298 (LDRU_QUALIFIERS): Likewise.
7299 (LDRGBS_QUALIFIERS): Likewise.
7300 (LDRGBU_QUALIFIERS): Likewise.
7301 * config/arm/arm_mve.h (vldrbq_gather_offset_u8): Define macro.
7302 (vldrbq_gather_offset_s8): Likewise.
7303 (vldrbq_s8): Likewise.
7304 (vldrbq_u8): Likewise.
7305 (vldrbq_gather_offset_u16): Likewise.
7306 (vldrbq_gather_offset_s16): Likewise.
7307 (vldrbq_s16): Likewise.
7308 (vldrbq_u16): Likewise.
7309 (vldrbq_gather_offset_u32): Likewise.
7310 (vldrbq_gather_offset_s32): Likewise.
7311 (vldrbq_s32): Likewise.
7312 (vldrbq_u32): Likewise.
7313 (vldrwq_gather_base_s32): Likewise.
7314 (vldrwq_gather_base_u32): Likewise.
7315 (__arm_vldrbq_gather_offset_u8): Define intrinsic.
7316 (__arm_vldrbq_gather_offset_s8): Likewise.
7317 (__arm_vldrbq_s8): Likewise.
7318 (__arm_vldrbq_u8): Likewise.
7319 (__arm_vldrbq_gather_offset_u16): Likewise.
7320 (__arm_vldrbq_gather_offset_s16): Likewise.
7321 (__arm_vldrbq_s16): Likewise.
7322 (__arm_vldrbq_u16): Likewise.
7323 (__arm_vldrbq_gather_offset_u32): Likewise.
7324 (__arm_vldrbq_gather_offset_s32): Likewise.
7325 (__arm_vldrbq_s32): Likewise.
7326 (__arm_vldrbq_u32): Likewise.
7327 (__arm_vldrwq_gather_base_s32): Likewise.
7328 (__arm_vldrwq_gather_base_u32): Likewise.
7329 (vldrbq_gather_offset): Define polymorphic variant.
7330 * config/arm/arm_mve_builtins.def (LDRGU_QUALIFIERS): Use builtin
7332 (LDRGS_QUALIFIERS): Likewise.
7333 (LDRS_QUALIFIERS): Likewise.
7334 (LDRU_QUALIFIERS): Likewise.
7335 (LDRGBS_QUALIFIERS): Likewise.
7336 (LDRGBU_QUALIFIERS): Likewise.
7337 * config/arm/mve.md (VLDRBGOQ): Define iterator.
7339 (VLDRWGBQ): Likewise.
7340 (mve_vldrbq_gather_offset_<supf><mode>): Define RTL pattern.
7341 (mve_vldrbq_<supf><mode>): Likewise.
7342 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
7344 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7345 Mihail Ionescu <mihail.ionescu@arm.com>
7346 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7348 * config/arm/arm-builtins.c (STRS_QUALIFIERS): Define builtin qualifier.
7349 (STRU_QUALIFIERS): Likewise.
7350 (STRSS_QUALIFIERS): Likewise.
7351 (STRSU_QUALIFIERS): Likewise.
7352 (STRSBS_QUALIFIERS): Likewise.
7353 (STRSBU_QUALIFIERS): Likewise.
7354 * config/arm/arm_mve.h (vstrbq_s8): Define macro.
7355 (vstrbq_u8): Likewise.
7356 (vstrbq_u16): Likewise.
7357 (vstrbq_scatter_offset_s8): Likewise.
7358 (vstrbq_scatter_offset_u8): Likewise.
7359 (vstrbq_scatter_offset_u16): Likewise.
7360 (vstrbq_s16): Likewise.
7361 (vstrbq_u32): Likewise.
7362 (vstrbq_scatter_offset_s16): Likewise.
7363 (vstrbq_scatter_offset_u32): Likewise.
7364 (vstrbq_s32): Likewise.
7365 (vstrbq_scatter_offset_s32): Likewise.
7366 (vstrwq_scatter_base_s32): Likewise.
7367 (vstrwq_scatter_base_u32): Likewise.
7368 (__arm_vstrbq_scatter_offset_s8): Define intrinsic.
7369 (__arm_vstrbq_scatter_offset_s32): Likewise.
7370 (__arm_vstrbq_scatter_offset_s16): Likewise.
7371 (__arm_vstrbq_scatter_offset_u8): Likewise.
7372 (__arm_vstrbq_scatter_offset_u32): Likewise.
7373 (__arm_vstrbq_scatter_offset_u16): Likewise.
7374 (__arm_vstrbq_s8): Likewise.
7375 (__arm_vstrbq_s32): Likewise.
7376 (__arm_vstrbq_s16): Likewise.
7377 (__arm_vstrbq_u8): Likewise.
7378 (__arm_vstrbq_u32): Likewise.
7379 (__arm_vstrbq_u16): Likewise.
7380 (__arm_vstrwq_scatter_base_s32): Likewise.
7381 (__arm_vstrwq_scatter_base_u32): Likewise.
7382 (vstrbq): Define polymorphic variant.
7383 (vstrbq_scatter_offset): Likewise.
7384 (vstrwq_scatter_base): Likewise.
7385 * config/arm/arm_mve_builtins.def (STRS_QUALIFIERS): Use builtin
7387 (STRU_QUALIFIERS): Likewise.
7388 (STRSS_QUALIFIERS): Likewise.
7389 (STRSU_QUALIFIERS): Likewise.
7390 (STRSBS_QUALIFIERS): Likewise.
7391 (STRSBU_QUALIFIERS): Likewise.
7392 * config/arm/mve.md (MVE_B_ELEM): Define mode attribute iterator.
7393 (VSTRWSBQ): Define iterators.
7394 (VSTRBSOQ): Likewise.
7396 (mve_vstrbq_<supf><mode>): Define RTL pattern.
7397 (mve_vstrbq_scatter_offset_<supf><mode>): Likewise.
7398 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
7400 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7401 Mihail Ionescu <mihail.ionescu@arm.com>
7402 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7404 * config/arm/arm_mve.h (vabdq_m_f32): Define macro.
7405 (vabdq_m_f16): Likewise.
7406 (vaddq_m_f32): Likewise.
7407 (vaddq_m_f16): Likewise.
7408 (vaddq_m_n_f32): Likewise.
7409 (vaddq_m_n_f16): Likewise.
7410 (vandq_m_f32): Likewise.
7411 (vandq_m_f16): Likewise.
7412 (vbicq_m_f32): Likewise.
7413 (vbicq_m_f16): Likewise.
7414 (vbrsrq_m_n_f32): Likewise.
7415 (vbrsrq_m_n_f16): Likewise.
7416 (vcaddq_rot270_m_f32): Likewise.
7417 (vcaddq_rot270_m_f16): Likewise.
7418 (vcaddq_rot90_m_f32): Likewise.
7419 (vcaddq_rot90_m_f16): Likewise.
7420 (vcmlaq_m_f32): Likewise.
7421 (vcmlaq_m_f16): Likewise.
7422 (vcmlaq_rot180_m_f32): Likewise.
7423 (vcmlaq_rot180_m_f16): Likewise.
7424 (vcmlaq_rot270_m_f32): Likewise.
7425 (vcmlaq_rot270_m_f16): Likewise.
7426 (vcmlaq_rot90_m_f32): Likewise.
7427 (vcmlaq_rot90_m_f16): Likewise.
7428 (vcmulq_m_f32): Likewise.
7429 (vcmulq_m_f16): Likewise.
7430 (vcmulq_rot180_m_f32): Likewise.
7431 (vcmulq_rot180_m_f16): Likewise.
7432 (vcmulq_rot270_m_f32): Likewise.
7433 (vcmulq_rot270_m_f16): Likewise.
7434 (vcmulq_rot90_m_f32): Likewise.
7435 (vcmulq_rot90_m_f16): Likewise.
7436 (vcvtq_m_n_s32_f32): Likewise.
7437 (vcvtq_m_n_s16_f16): Likewise.
7438 (vcvtq_m_n_u32_f32): Likewise.
7439 (vcvtq_m_n_u16_f16): Likewise.
7440 (veorq_m_f32): Likewise.
7441 (veorq_m_f16): Likewise.
7442 (vfmaq_m_f32): Likewise.
7443 (vfmaq_m_f16): Likewise.
7444 (vfmaq_m_n_f32): Likewise.
7445 (vfmaq_m_n_f16): Likewise.
7446 (vfmasq_m_n_f32): Likewise.
7447 (vfmasq_m_n_f16): Likewise.
7448 (vfmsq_m_f32): Likewise.
7449 (vfmsq_m_f16): Likewise.
7450 (vmaxnmq_m_f32): Likewise.
7451 (vmaxnmq_m_f16): Likewise.
7452 (vminnmq_m_f32): Likewise.
7453 (vminnmq_m_f16): Likewise.
7454 (vmulq_m_f32): Likewise.
7455 (vmulq_m_f16): Likewise.
7456 (vmulq_m_n_f32): Likewise.
7457 (vmulq_m_n_f16): Likewise.
7458 (vornq_m_f32): Likewise.
7459 (vornq_m_f16): Likewise.
7460 (vorrq_m_f32): Likewise.
7461 (vorrq_m_f16): Likewise.
7462 (vsubq_m_f32): Likewise.
7463 (vsubq_m_f16): Likewise.
7464 (vsubq_m_n_f32): Likewise.
7465 (vsubq_m_n_f16): Likewise.
7466 (__attribute__): Likewise.
7467 (__arm_vabdq_m_f32): Likewise.
7468 (__arm_vabdq_m_f16): Likewise.
7469 (__arm_vaddq_m_f32): Likewise.
7470 (__arm_vaddq_m_f16): Likewise.
7471 (__arm_vaddq_m_n_f32): Likewise.
7472 (__arm_vaddq_m_n_f16): Likewise.
7473 (__arm_vandq_m_f32): Likewise.
7474 (__arm_vandq_m_f16): Likewise.
7475 (__arm_vbicq_m_f32): Likewise.
7476 (__arm_vbicq_m_f16): Likewise.
7477 (__arm_vbrsrq_m_n_f32): Likewise.
7478 (__arm_vbrsrq_m_n_f16): Likewise.
7479 (__arm_vcaddq_rot270_m_f32): Likewise.
7480 (__arm_vcaddq_rot270_m_f16): Likewise.
7481 (__arm_vcaddq_rot90_m_f32): Likewise.
7482 (__arm_vcaddq_rot90_m_f16): Likewise.
7483 (__arm_vcmlaq_m_f32): Likewise.
7484 (__arm_vcmlaq_m_f16): Likewise.
7485 (__arm_vcmlaq_rot180_m_f32): Likewise.
7486 (__arm_vcmlaq_rot180_m_f16): Likewise.
7487 (__arm_vcmlaq_rot270_m_f32): Likewise.
7488 (__arm_vcmlaq_rot270_m_f16): Likewise.
7489 (__arm_vcmlaq_rot90_m_f32): Likewise.
7490 (__arm_vcmlaq_rot90_m_f16): Likewise.
7491 (__arm_vcmulq_m_f32): Likewise.
7492 (__arm_vcmulq_m_f16): Likewise.
7493 (__arm_vcmulq_rot180_m_f32): Define intrinsic.
7494 (__arm_vcmulq_rot180_m_f16): Likewise.
7495 (__arm_vcmulq_rot270_m_f32): Likewise.
7496 (__arm_vcmulq_rot270_m_f16): Likewise.
7497 (__arm_vcmulq_rot90_m_f32): Likewise.
7498 (__arm_vcmulq_rot90_m_f16): Likewise.
7499 (__arm_vcvtq_m_n_s32_f32): Likewise.
7500 (__arm_vcvtq_m_n_s16_f16): Likewise.
7501 (__arm_vcvtq_m_n_u32_f32): Likewise.
7502 (__arm_vcvtq_m_n_u16_f16): Likewise.
7503 (__arm_veorq_m_f32): Likewise.
7504 (__arm_veorq_m_f16): Likewise.
7505 (__arm_vfmaq_m_f32): Likewise.
7506 (__arm_vfmaq_m_f16): Likewise.
7507 (__arm_vfmaq_m_n_f32): Likewise.
7508 (__arm_vfmaq_m_n_f16): Likewise.
7509 (__arm_vfmasq_m_n_f32): Likewise.
7510 (__arm_vfmasq_m_n_f16): Likewise.
7511 (__arm_vfmsq_m_f32): Likewise.
7512 (__arm_vfmsq_m_f16): Likewise.
7513 (__arm_vmaxnmq_m_f32): Likewise.
7514 (__arm_vmaxnmq_m_f16): Likewise.
7515 (__arm_vminnmq_m_f32): Likewise.
7516 (__arm_vminnmq_m_f16): Likewise.
7517 (__arm_vmulq_m_f32): Likewise.
7518 (__arm_vmulq_m_f16): Likewise.
7519 (__arm_vmulq_m_n_f32): Likewise.
7520 (__arm_vmulq_m_n_f16): Likewise.
7521 (__arm_vornq_m_f32): Likewise.
7522 (__arm_vornq_m_f16): Likewise.
7523 (__arm_vorrq_m_f32): Likewise.
7524 (__arm_vorrq_m_f16): Likewise.
7525 (__arm_vsubq_m_f32): Likewise.
7526 (__arm_vsubq_m_f16): Likewise.
7527 (__arm_vsubq_m_n_f32): Likewise.
7528 (__arm_vsubq_m_n_f16): Likewise.
7529 (vabdq_m): Define polymorphic variant.
7530 (vaddq_m): Likewise.
7531 (vaddq_m_n): Likewise.
7532 (vandq_m): Likewise.
7533 (vbicq_m): Likewise.
7534 (vbrsrq_m_n): Likewise.
7535 (vcaddq_rot270_m): Likewise.
7536 (vcaddq_rot90_m): Likewise.
7537 (vcmlaq_m): Likewise.
7538 (vcmlaq_rot180_m): Likewise.
7539 (vcmlaq_rot270_m): Likewise.
7540 (vcmlaq_rot90_m): Likewise.
7541 (vcmulq_m): Likewise.
7542 (vcmulq_rot180_m): Likewise.
7543 (vcmulq_rot270_m): Likewise.
7544 (vcmulq_rot90_m): Likewise.
7545 (veorq_m): Likewise.
7546 (vfmaq_m): Likewise.
7547 (vfmaq_m_n): Likewise.
7548 (vfmasq_m_n): Likewise.
7549 (vfmsq_m): Likewise.
7550 (vmaxnmq_m): Likewise.
7551 (vminnmq_m): Likewise.
7552 (vmulq_m): Likewise.
7553 (vmulq_m_n): Likewise.
7554 (vornq_m): Likewise.
7555 (vsubq_m): Likewise.
7556 (vsubq_m_n): Likewise.
7557 (vorrq_m): Likewise.
7558 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7560 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7561 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7562 * config/arm/mve.md (mve_vabdq_m_f<mode>): Define RTL pattern.
7563 (mve_vaddq_m_f<mode>): Likewise.
7564 (mve_vaddq_m_n_f<mode>): Likewise.
7565 (mve_vandq_m_f<mode>): Likewise.
7566 (mve_vbicq_m_f<mode>): Likewise.
7567 (mve_vbrsrq_m_n_f<mode>): Likewise.
7568 (mve_vcaddq_rot270_m_f<mode>): Likewise.
7569 (mve_vcaddq_rot90_m_f<mode>): Likewise.
7570 (mve_vcmlaq_m_f<mode>): Likewise.
7571 (mve_vcmlaq_rot180_m_f<mode>): Likewise.
7572 (mve_vcmlaq_rot270_m_f<mode>): Likewise.
7573 (mve_vcmlaq_rot90_m_f<mode>): Likewise.
7574 (mve_vcmulq_m_f<mode>): Likewise.
7575 (mve_vcmulq_rot180_m_f<mode>): Likewise.
7576 (mve_vcmulq_rot270_m_f<mode>): Likewise.
7577 (mve_vcmulq_rot90_m_f<mode>): Likewise.
7578 (mve_veorq_m_f<mode>): Likewise.
7579 (mve_vfmaq_m_f<mode>): Likewise.
7580 (mve_vfmaq_m_n_f<mode>): Likewise.
7581 (mve_vfmasq_m_n_f<mode>): Likewise.
7582 (mve_vfmsq_m_f<mode>): Likewise.
7583 (mve_vmaxnmq_m_f<mode>): Likewise.
7584 (mve_vminnmq_m_f<mode>): Likewise.
7585 (mve_vmulq_m_f<mode>): Likewise.
7586 (mve_vmulq_m_n_f<mode>): Likewise.
7587 (mve_vornq_m_f<mode>): Likewise.
7588 (mve_vorrq_m_f<mode>): Likewise.
7589 (mve_vsubq_m_f<mode>): Likewise.
7590 (mve_vsubq_m_n_f<mode>): Likewise.
7592 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7593 Mihail Ionescu <mihail.ionescu@arm.com>
7594 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7596 * config/arm/arm-protos.h (arm_mve_immediate_check):
7597 * config/arm/arm.c (arm_mve_immediate_check): Define fuction to check
7598 mode and interger value.
7599 * config/arm/arm_mve.h (vmlaldavaq_p_s32): Define macro.
7600 (vmlaldavaq_p_s16): Likewise.
7601 (vmlaldavaq_p_u32): Likewise.
7602 (vmlaldavaq_p_u16): Likewise.
7603 (vmlaldavaxq_p_s32): Likewise.
7604 (vmlaldavaxq_p_s16): Likewise.
7605 (vmlaldavaxq_p_u32): Likewise.
7606 (vmlaldavaxq_p_u16): Likewise.
7607 (vmlsldavaq_p_s32): Likewise.
7608 (vmlsldavaq_p_s16): Likewise.
7609 (vmlsldavaxq_p_s32): Likewise.
7610 (vmlsldavaxq_p_s16): Likewise.
7611 (vmullbq_poly_m_p8): Likewise.
7612 (vmullbq_poly_m_p16): Likewise.
7613 (vmulltq_poly_m_p8): Likewise.
7614 (vmulltq_poly_m_p16): Likewise.
7615 (vqdmullbq_m_n_s32): Likewise.
7616 (vqdmullbq_m_n_s16): Likewise.
7617 (vqdmullbq_m_s32): Likewise.
7618 (vqdmullbq_m_s16): Likewise.
7619 (vqdmulltq_m_n_s32): Likewise.
7620 (vqdmulltq_m_n_s16): Likewise.
7621 (vqdmulltq_m_s32): Likewise.
7622 (vqdmulltq_m_s16): Likewise.
7623 (vqrshrnbq_m_n_s32): Likewise.
7624 (vqrshrnbq_m_n_s16): Likewise.
7625 (vqrshrnbq_m_n_u32): Likewise.
7626 (vqrshrnbq_m_n_u16): Likewise.
7627 (vqrshrntq_m_n_s32): Likewise.
7628 (vqrshrntq_m_n_s16): Likewise.
7629 (vqrshrntq_m_n_u32): Likewise.
7630 (vqrshrntq_m_n_u16): Likewise.
7631 (vqrshrunbq_m_n_s32): Likewise.
7632 (vqrshrunbq_m_n_s16): Likewise.
7633 (vqrshruntq_m_n_s32): Likewise.
7634 (vqrshruntq_m_n_s16): Likewise.
7635 (vqshrnbq_m_n_s32): Likewise.
7636 (vqshrnbq_m_n_s16): Likewise.
7637 (vqshrnbq_m_n_u32): Likewise.
7638 (vqshrnbq_m_n_u16): Likewise.
7639 (vqshrntq_m_n_s32): Likewise.
7640 (vqshrntq_m_n_s16): Likewise.
7641 (vqshrntq_m_n_u32): Likewise.
7642 (vqshrntq_m_n_u16): Likewise.
7643 (vqshrunbq_m_n_s32): Likewise.
7644 (vqshrunbq_m_n_s16): Likewise.
7645 (vqshruntq_m_n_s32): Likewise.
7646 (vqshruntq_m_n_s16): Likewise.
7647 (vrmlaldavhaq_p_s32): Likewise.
7648 (vrmlaldavhaq_p_u32): Likewise.
7649 (vrmlaldavhaxq_p_s32): Likewise.
7650 (vrmlsldavhaq_p_s32): Likewise.
7651 (vrmlsldavhaxq_p_s32): Likewise.
7652 (vrshrnbq_m_n_s32): Likewise.
7653 (vrshrnbq_m_n_s16): Likewise.
7654 (vrshrnbq_m_n_u32): Likewise.
7655 (vrshrnbq_m_n_u16): Likewise.
7656 (vrshrntq_m_n_s32): Likewise.
7657 (vrshrntq_m_n_s16): Likewise.
7658 (vrshrntq_m_n_u32): Likewise.
7659 (vrshrntq_m_n_u16): Likewise.
7660 (vshllbq_m_n_s8): Likewise.
7661 (vshllbq_m_n_s16): Likewise.
7662 (vshllbq_m_n_u8): Likewise.
7663 (vshllbq_m_n_u16): Likewise.
7664 (vshlltq_m_n_s8): Likewise.
7665 (vshlltq_m_n_s16): Likewise.
7666 (vshlltq_m_n_u8): Likewise.
7667 (vshlltq_m_n_u16): Likewise.
7668 (vshrnbq_m_n_s32): Likewise.
7669 (vshrnbq_m_n_s16): Likewise.
7670 (vshrnbq_m_n_u32): Likewise.
7671 (vshrnbq_m_n_u16): Likewise.
7672 (vshrntq_m_n_s32): Likewise.
7673 (vshrntq_m_n_s16): Likewise.
7674 (vshrntq_m_n_u32): Likewise.
7675 (vshrntq_m_n_u16): Likewise.
7676 (__arm_vmlaldavaq_p_s32): Define intrinsic.
7677 (__arm_vmlaldavaq_p_s16): Likewise.
7678 (__arm_vmlaldavaq_p_u32): Likewise.
7679 (__arm_vmlaldavaq_p_u16): Likewise.
7680 (__arm_vmlaldavaxq_p_s32): Likewise.
7681 (__arm_vmlaldavaxq_p_s16): Likewise.
7682 (__arm_vmlaldavaxq_p_u32): Likewise.
7683 (__arm_vmlaldavaxq_p_u16): Likewise.
7684 (__arm_vmlsldavaq_p_s32): Likewise.
7685 (__arm_vmlsldavaq_p_s16): Likewise.
7686 (__arm_vmlsldavaxq_p_s32): Likewise.
7687 (__arm_vmlsldavaxq_p_s16): Likewise.
7688 (__arm_vmullbq_poly_m_p8): Likewise.
7689 (__arm_vmullbq_poly_m_p16): Likewise.
7690 (__arm_vmulltq_poly_m_p8): Likewise.
7691 (__arm_vmulltq_poly_m_p16): Likewise.
7692 (__arm_vqdmullbq_m_n_s32): Likewise.
7693 (__arm_vqdmullbq_m_n_s16): Likewise.
7694 (__arm_vqdmullbq_m_s32): Likewise.
7695 (__arm_vqdmullbq_m_s16): Likewise.
7696 (__arm_vqdmulltq_m_n_s32): Likewise.
7697 (__arm_vqdmulltq_m_n_s16): Likewise.
7698 (__arm_vqdmulltq_m_s32): Likewise.
7699 (__arm_vqdmulltq_m_s16): Likewise.
7700 (__arm_vqrshrnbq_m_n_s32): Likewise.
7701 (__arm_vqrshrnbq_m_n_s16): Likewise.
7702 (__arm_vqrshrnbq_m_n_u32): Likewise.
7703 (__arm_vqrshrnbq_m_n_u16): Likewise.
7704 (__arm_vqrshrntq_m_n_s32): Likewise.
7705 (__arm_vqrshrntq_m_n_s16): Likewise.
7706 (__arm_vqrshrntq_m_n_u32): Likewise.
7707 (__arm_vqrshrntq_m_n_u16): Likewise.
7708 (__arm_vqrshrunbq_m_n_s32): Likewise.
7709 (__arm_vqrshrunbq_m_n_s16): Likewise.
7710 (__arm_vqrshruntq_m_n_s32): Likewise.
7711 (__arm_vqrshruntq_m_n_s16): Likewise.
7712 (__arm_vqshrnbq_m_n_s32): Likewise.
7713 (__arm_vqshrnbq_m_n_s16): Likewise.
7714 (__arm_vqshrnbq_m_n_u32): Likewise.
7715 (__arm_vqshrnbq_m_n_u16): Likewise.
7716 (__arm_vqshrntq_m_n_s32): Likewise.
7717 (__arm_vqshrntq_m_n_s16): Likewise.
7718 (__arm_vqshrntq_m_n_u32): Likewise.
7719 (__arm_vqshrntq_m_n_u16): Likewise.
7720 (__arm_vqshrunbq_m_n_s32): Likewise.
7721 (__arm_vqshrunbq_m_n_s16): Likewise.
7722 (__arm_vqshruntq_m_n_s32): Likewise.
7723 (__arm_vqshruntq_m_n_s16): Likewise.
7724 (__arm_vrmlaldavhaq_p_s32): Likewise.
7725 (__arm_vrmlaldavhaq_p_u32): Likewise.
7726 (__arm_vrmlaldavhaxq_p_s32): Likewise.
7727 (__arm_vrmlsldavhaq_p_s32): Likewise.
7728 (__arm_vrmlsldavhaxq_p_s32): Likewise.
7729 (__arm_vrshrnbq_m_n_s32): Likewise.
7730 (__arm_vrshrnbq_m_n_s16): Likewise.
7731 (__arm_vrshrnbq_m_n_u32): Likewise.
7732 (__arm_vrshrnbq_m_n_u16): Likewise.
7733 (__arm_vrshrntq_m_n_s32): Likewise.
7734 (__arm_vrshrntq_m_n_s16): Likewise.
7735 (__arm_vrshrntq_m_n_u32): Likewise.
7736 (__arm_vrshrntq_m_n_u16): Likewise.
7737 (__arm_vshllbq_m_n_s8): Likewise.
7738 (__arm_vshllbq_m_n_s16): Likewise.
7739 (__arm_vshllbq_m_n_u8): Likewise.
7740 (__arm_vshllbq_m_n_u16): Likewise.
7741 (__arm_vshlltq_m_n_s8): Likewise.
7742 (__arm_vshlltq_m_n_s16): Likewise.
7743 (__arm_vshlltq_m_n_u8): Likewise.
7744 (__arm_vshlltq_m_n_u16): Likewise.
7745 (__arm_vshrnbq_m_n_s32): Likewise.
7746 (__arm_vshrnbq_m_n_s16): Likewise.
7747 (__arm_vshrnbq_m_n_u32): Likewise.
7748 (__arm_vshrnbq_m_n_u16): Likewise.
7749 (__arm_vshrntq_m_n_s32): Likewise.
7750 (__arm_vshrntq_m_n_s16): Likewise.
7751 (__arm_vshrntq_m_n_u32): Likewise.
7752 (__arm_vshrntq_m_n_u16): Likewise.
7753 (vmullbq_poly_m): Define polymorphic variant.
7754 (vmulltq_poly_m): Likewise.
7755 (vshllbq_m): Likewise.
7756 (vshrntq_m_n): Likewise.
7757 (vshrnbq_m_n): Likewise.
7758 (vshlltq_m_n): Likewise.
7759 (vshllbq_m_n): Likewise.
7760 (vrshrntq_m_n): Likewise.
7761 (vrshrnbq_m_n): Likewise.
7762 (vqshruntq_m_n): Likewise.
7763 (vqshrunbq_m_n): Likewise.
7764 (vqdmullbq_m_n): Likewise.
7765 (vqdmullbq_m): Likewise.
7766 (vqdmulltq_m_n): Likewise.
7767 (vqdmulltq_m): Likewise.
7768 (vqrshrnbq_m_n): Likewise.
7769 (vqrshrntq_m_n): Likewise.
7770 (vqrshrunbq_m_n): Likewise.
7771 (vqrshruntq_m_n): Likewise.
7772 (vqshrnbq_m_n): Likewise.
7773 (vqshrntq_m_n): Likewise.
7774 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
7776 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
7777 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE): Likewise.
7778 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
7779 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
7780 * config/arm/mve.md (VMLALDAVAQ_P): Define iterator.
7781 (VMLALDAVAXQ_P): Likewise.
7782 (VQRSHRNBQ_M_N): Likewise.
7783 (VQRSHRNTQ_M_N): Likewise.
7784 (VQSHRNBQ_M_N): Likewise.
7785 (VQSHRNTQ_M_N): Likewise.
7786 (VRSHRNBQ_M_N): Likewise.
7787 (VRSHRNTQ_M_N): Likewise.
7788 (VSHLLBQ_M_N): Likewise.
7789 (VSHLLTQ_M_N): Likewise.
7790 (VSHRNBQ_M_N): Likewise.
7791 (VSHRNTQ_M_N): Likewise.
7792 (mve_vmlaldavaq_p_<supf><mode>): Define RTL pattern.
7793 (mve_vmlaldavaxq_p_<supf><mode>): Likewise.
7794 (mve_vqrshrnbq_m_n_<supf><mode>): Likewise.
7795 (mve_vqrshrntq_m_n_<supf><mode>): Likewise.
7796 (mve_vqshrnbq_m_n_<supf><mode>): Likewise.
7797 (mve_vqshrntq_m_n_<supf><mode>): Likewise.
7798 (mve_vrmlaldavhaq_p_sv4si): Likewise.
7799 (mve_vrshrnbq_m_n_<supf><mode>): Likewise.
7800 (mve_vrshrntq_m_n_<supf><mode>): Likewise.
7801 (mve_vshllbq_m_n_<supf><mode>): Likewise.
7802 (mve_vshlltq_m_n_<supf><mode>): Likewise.
7803 (mve_vshrnbq_m_n_<supf><mode>): Likewise.
7804 (mve_vshrntq_m_n_<supf><mode>): Likewise.
7805 (mve_vmlsldavaq_p_s<mode>): Likewise.
7806 (mve_vmlsldavaxq_p_s<mode>): Likewise.
7807 (mve_vmullbq_poly_m_p<mode>): Likewise.
7808 (mve_vmulltq_poly_m_p<mode>): Likewise.
7809 (mve_vqdmullbq_m_n_s<mode>): Likewise.
7810 (mve_vqdmullbq_m_s<mode>): Likewise.
7811 (mve_vqdmulltq_m_n_s<mode>): Likewise.
7812 (mve_vqdmulltq_m_s<mode>): Likewise.
7813 (mve_vqrshrunbq_m_n_s<mode>): Likewise.
7814 (mve_vqrshruntq_m_n_s<mode>): Likewise.
7815 (mve_vqshrunbq_m_n_s<mode>): Likewise.
7816 (mve_vqshruntq_m_n_s<mode>): Likewise.
7817 (mve_vrmlaldavhaq_p_uv4si): Likewise.
7818 (mve_vrmlaldavhaxq_p_sv4si): Likewise.
7819 (mve_vrmlsldavhaq_p_sv4si): Likewise.
7820 (mve_vrmlsldavhaxq_p_sv4si): Likewise.
7822 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
7823 Mihail Ionescu <mihail.ionescu@arm.com>
7824 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
7826 * config/arm/arm_mve.h (vabdq_m_s8): Define macro.
7827 (vabdq_m_s32): Likewise.
7828 (vabdq_m_s16): Likewise.
7829 (vabdq_m_u8): Likewise.
7830 (vabdq_m_u32): Likewise.
7831 (vabdq_m_u16): Likewise.
7832 (vaddq_m_n_s8): Likewise.
7833 (vaddq_m_n_s32): Likewise.
7834 (vaddq_m_n_s16): Likewise.
7835 (vaddq_m_n_u8): Likewise.
7836 (vaddq_m_n_u32): Likewise.
7837 (vaddq_m_n_u16): Likewise.
7838 (vaddq_m_s8): Likewise.
7839 (vaddq_m_s32): Likewise.
7840 (vaddq_m_s16): Likewise.
7841 (vaddq_m_u8): Likewise.
7842 (vaddq_m_u32): Likewise.
7843 (vaddq_m_u16): Likewise.
7844 (vandq_m_s8): Likewise.
7845 (vandq_m_s32): Likewise.
7846 (vandq_m_s16): Likewise.
7847 (vandq_m_u8): Likewise.
7848 (vandq_m_u32): Likewise.
7849 (vandq_m_u16): Likewise.
7850 (vbicq_m_s8): Likewise.
7851 (vbicq_m_s32): Likewise.
7852 (vbicq_m_s16): Likewise.
7853 (vbicq_m_u8): Likewise.
7854 (vbicq_m_u32): Likewise.
7855 (vbicq_m_u16): Likewise.
7856 (vbrsrq_m_n_s8): Likewise.
7857 (vbrsrq_m_n_s32): Likewise.
7858 (vbrsrq_m_n_s16): Likewise.
7859 (vbrsrq_m_n_u8): Likewise.
7860 (vbrsrq_m_n_u32): Likewise.
7861 (vbrsrq_m_n_u16): Likewise.
7862 (vcaddq_rot270_m_s8): Likewise.
7863 (vcaddq_rot270_m_s32): Likewise.
7864 (vcaddq_rot270_m_s16): Likewise.
7865 (vcaddq_rot270_m_u8): Likewise.
7866 (vcaddq_rot270_m_u32): Likewise.
7867 (vcaddq_rot270_m_u16): Likewise.
7868 (vcaddq_rot90_m_s8): Likewise.
7869 (vcaddq_rot90_m_s32): Likewise.
7870 (vcaddq_rot90_m_s16): Likewise.
7871 (vcaddq_rot90_m_u8): Likewise.
7872 (vcaddq_rot90_m_u32): Likewise.
7873 (vcaddq_rot90_m_u16): Likewise.
7874 (veorq_m_s8): Likewise.
7875 (veorq_m_s32): Likewise.
7876 (veorq_m_s16): Likewise.
7877 (veorq_m_u8): Likewise.
7878 (veorq_m_u32): Likewise.
7879 (veorq_m_u16): Likewise.
7880 (vhaddq_m_n_s8): Likewise.
7881 (vhaddq_m_n_s32): Likewise.
7882 (vhaddq_m_n_s16): Likewise.
7883 (vhaddq_m_n_u8): Likewise.
7884 (vhaddq_m_n_u32): Likewise.
7885 (vhaddq_m_n_u16): Likewise.
7886 (vhaddq_m_s8): Likewise.
7887 (vhaddq_m_s32): Likewise.
7888 (vhaddq_m_s16): Likewise.
7889 (vhaddq_m_u8): Likewise.
7890 (vhaddq_m_u32): Likewise.
7891 (vhaddq_m_u16): Likewise.
7892 (vhcaddq_rot270_m_s8): Likewise.
7893 (vhcaddq_rot270_m_s32): Likewise.
7894 (vhcaddq_rot270_m_s16): Likewise.
7895 (vhcaddq_rot90_m_s8): Likewise.
7896 (vhcaddq_rot90_m_s32): Likewise.
7897 (vhcaddq_rot90_m_s16): Likewise.
7898 (vhsubq_m_n_s8): Likewise.
7899 (vhsubq_m_n_s32): Likewise.
7900 (vhsubq_m_n_s16): Likewise.
7901 (vhsubq_m_n_u8): Likewise.
7902 (vhsubq_m_n_u32): Likewise.
7903 (vhsubq_m_n_u16): Likewise.
7904 (vhsubq_m_s8): Likewise.
7905 (vhsubq_m_s32): Likewise.
7906 (vhsubq_m_s16): Likewise.
7907 (vhsubq_m_u8): Likewise.
7908 (vhsubq_m_u32): Likewise.
7909 (vhsubq_m_u16): Likewise.
7910 (vmaxq_m_s8): Likewise.
7911 (vmaxq_m_s32): Likewise.
7912 (vmaxq_m_s16): Likewise.
7913 (vmaxq_m_u8): Likewise.
7914 (vmaxq_m_u32): Likewise.
7915 (vmaxq_m_u16): Likewise.
7916 (vminq_m_s8): Likewise.
7917 (vminq_m_s32): Likewise.
7918 (vminq_m_s16): Likewise.
7919 (vminq_m_u8): Likewise.
7920 (vminq_m_u32): Likewise.
7921 (vminq_m_u16): Likewise.
7922 (vmladavaq_p_s8): Likewise.
7923 (vmladavaq_p_s32): Likewise.
7924 (vmladavaq_p_s16): Likewise.
7925 (vmladavaq_p_u8): Likewise.
7926 (vmladavaq_p_u32): Likewise.
7927 (vmladavaq_p_u16): Likewise.
7928 (vmladavaxq_p_s8): Likewise.
7929 (vmladavaxq_p_s32): Likewise.
7930 (vmladavaxq_p_s16): Likewise.
7931 (vmlaq_m_n_s8): Likewise.
7932 (vmlaq_m_n_s32): Likewise.
7933 (vmlaq_m_n_s16): Likewise.
7934 (vmlaq_m_n_u8): Likewise.
7935 (vmlaq_m_n_u32): Likewise.
7936 (vmlaq_m_n_u16): Likewise.
7937 (vmlasq_m_n_s8): Likewise.
7938 (vmlasq_m_n_s32): Likewise.
7939 (vmlasq_m_n_s16): Likewise.
7940 (vmlasq_m_n_u8): Likewise.
7941 (vmlasq_m_n_u32): Likewise.
7942 (vmlasq_m_n_u16): Likewise.
7943 (vmlsdavaq_p_s8): Likewise.
7944 (vmlsdavaq_p_s32): Likewise.
7945 (vmlsdavaq_p_s16): Likewise.
7946 (vmlsdavaxq_p_s8): Likewise.
7947 (vmlsdavaxq_p_s32): Likewise.
7948 (vmlsdavaxq_p_s16): Likewise.
7949 (vmulhq_m_s8): Likewise.
7950 (vmulhq_m_s32): Likewise.
7951 (vmulhq_m_s16): Likewise.
7952 (vmulhq_m_u8): Likewise.
7953 (vmulhq_m_u32): Likewise.
7954 (vmulhq_m_u16): Likewise.
7955 (vmullbq_int_m_s8): Likewise.
7956 (vmullbq_int_m_s32): Likewise.
7957 (vmullbq_int_m_s16): Likewise.
7958 (vmullbq_int_m_u8): Likewise.
7959 (vmullbq_int_m_u32): Likewise.
7960 (vmullbq_int_m_u16): Likewise.
7961 (vmulltq_int_m_s8): Likewise.
7962 (vmulltq_int_m_s32): Likewise.
7963 (vmulltq_int_m_s16): Likewise.
7964 (vmulltq_int_m_u8): Likewise.
7965 (vmulltq_int_m_u32): Likewise.
7966 (vmulltq_int_m_u16): Likewise.
7967 (vmulq_m_n_s8): Likewise.
7968 (vmulq_m_n_s32): Likewise.
7969 (vmulq_m_n_s16): Likewise.
7970 (vmulq_m_n_u8): Likewise.
7971 (vmulq_m_n_u32): Likewise.
7972 (vmulq_m_n_u16): Likewise.
7973 (vmulq_m_s8): Likewise.
7974 (vmulq_m_s32): Likewise.
7975 (vmulq_m_s16): Likewise.
7976 (vmulq_m_u8): Likewise.
7977 (vmulq_m_u32): Likewise.
7978 (vmulq_m_u16): Likewise.
7979 (vornq_m_s8): Likewise.
7980 (vornq_m_s32): Likewise.
7981 (vornq_m_s16): Likewise.
7982 (vornq_m_u8): Likewise.
7983 (vornq_m_u32): Likewise.
7984 (vornq_m_u16): Likewise.
7985 (vorrq_m_s8): Likewise.
7986 (vorrq_m_s32): Likewise.
7987 (vorrq_m_s16): Likewise.
7988 (vorrq_m_u8): Likewise.
7989 (vorrq_m_u32): Likewise.
7990 (vorrq_m_u16): Likewise.
7991 (vqaddq_m_n_s8): Likewise.
7992 (vqaddq_m_n_s32): Likewise.
7993 (vqaddq_m_n_s16): Likewise.
7994 (vqaddq_m_n_u8): Likewise.
7995 (vqaddq_m_n_u32): Likewise.
7996 (vqaddq_m_n_u16): Likewise.
7997 (vqaddq_m_s8): Likewise.
7998 (vqaddq_m_s32): Likewise.
7999 (vqaddq_m_s16): Likewise.
8000 (vqaddq_m_u8): Likewise.
8001 (vqaddq_m_u32): Likewise.
8002 (vqaddq_m_u16): Likewise.
8003 (vqdmladhq_m_s8): Likewise.
8004 (vqdmladhq_m_s32): Likewise.
8005 (vqdmladhq_m_s16): Likewise.
8006 (vqdmladhxq_m_s8): Likewise.
8007 (vqdmladhxq_m_s32): Likewise.
8008 (vqdmladhxq_m_s16): Likewise.
8009 (vqdmlahq_m_n_s8): Likewise.
8010 (vqdmlahq_m_n_s32): Likewise.
8011 (vqdmlahq_m_n_s16): Likewise.
8012 (vqdmlahq_m_n_u8): Likewise.
8013 (vqdmlahq_m_n_u32): Likewise.
8014 (vqdmlahq_m_n_u16): Likewise.
8015 (vqdmlsdhq_m_s8): Likewise.
8016 (vqdmlsdhq_m_s32): Likewise.
8017 (vqdmlsdhq_m_s16): Likewise.
8018 (vqdmlsdhxq_m_s8): Likewise.
8019 (vqdmlsdhxq_m_s32): Likewise.
8020 (vqdmlsdhxq_m_s16): Likewise.
8021 (vqdmulhq_m_n_s8): Likewise.
8022 (vqdmulhq_m_n_s32): Likewise.
8023 (vqdmulhq_m_n_s16): Likewise.
8024 (vqdmulhq_m_s8): Likewise.
8025 (vqdmulhq_m_s32): Likewise.
8026 (vqdmulhq_m_s16): Likewise.
8027 (vqrdmladhq_m_s8): Likewise.
8028 (vqrdmladhq_m_s32): Likewise.
8029 (vqrdmladhq_m_s16): Likewise.
8030 (vqrdmladhxq_m_s8): Likewise.
8031 (vqrdmladhxq_m_s32): Likewise.
8032 (vqrdmladhxq_m_s16): Likewise.
8033 (vqrdmlahq_m_n_s8): Likewise.
8034 (vqrdmlahq_m_n_s32): Likewise.
8035 (vqrdmlahq_m_n_s16): Likewise.
8036 (vqrdmlahq_m_n_u8): Likewise.
8037 (vqrdmlahq_m_n_u32): Likewise.
8038 (vqrdmlahq_m_n_u16): Likewise.
8039 (vqrdmlashq_m_n_s8): Likewise.
8040 (vqrdmlashq_m_n_s32): Likewise.
8041 (vqrdmlashq_m_n_s16): Likewise.
8042 (vqrdmlashq_m_n_u8): Likewise.
8043 (vqrdmlashq_m_n_u32): Likewise.
8044 (vqrdmlashq_m_n_u16): Likewise.
8045 (vqrdmlsdhq_m_s8): Likewise.
8046 (vqrdmlsdhq_m_s32): Likewise.
8047 (vqrdmlsdhq_m_s16): Likewise.
8048 (vqrdmlsdhxq_m_s8): Likewise.
8049 (vqrdmlsdhxq_m_s32): Likewise.
8050 (vqrdmlsdhxq_m_s16): Likewise.
8051 (vqrdmulhq_m_n_s8): Likewise.
8052 (vqrdmulhq_m_n_s32): Likewise.
8053 (vqrdmulhq_m_n_s16): Likewise.
8054 (vqrdmulhq_m_s8): Likewise.
8055 (vqrdmulhq_m_s32): Likewise.
8056 (vqrdmulhq_m_s16): Likewise.
8057 (vqrshlq_m_s8): Likewise.
8058 (vqrshlq_m_s32): Likewise.
8059 (vqrshlq_m_s16): Likewise.
8060 (vqrshlq_m_u8): Likewise.
8061 (vqrshlq_m_u32): Likewise.
8062 (vqrshlq_m_u16): Likewise.
8063 (vqshlq_m_n_s8): Likewise.
8064 (vqshlq_m_n_s32): Likewise.
8065 (vqshlq_m_n_s16): Likewise.
8066 (vqshlq_m_n_u8): Likewise.
8067 (vqshlq_m_n_u32): Likewise.
8068 (vqshlq_m_n_u16): Likewise.
8069 (vqshlq_m_s8): Likewise.
8070 (vqshlq_m_s32): Likewise.
8071 (vqshlq_m_s16): Likewise.
8072 (vqshlq_m_u8): Likewise.
8073 (vqshlq_m_u32): Likewise.
8074 (vqshlq_m_u16): Likewise.
8075 (vqsubq_m_n_s8): Likewise.
8076 (vqsubq_m_n_s32): Likewise.
8077 (vqsubq_m_n_s16): Likewise.
8078 (vqsubq_m_n_u8): Likewise.
8079 (vqsubq_m_n_u32): Likewise.
8080 (vqsubq_m_n_u16): Likewise.
8081 (vqsubq_m_s8): Likewise.
8082 (vqsubq_m_s32): Likewise.
8083 (vqsubq_m_s16): Likewise.
8084 (vqsubq_m_u8): Likewise.
8085 (vqsubq_m_u32): Likewise.
8086 (vqsubq_m_u16): Likewise.
8087 (vrhaddq_m_s8): Likewise.
8088 (vrhaddq_m_s32): Likewise.
8089 (vrhaddq_m_s16): Likewise.
8090 (vrhaddq_m_u8): Likewise.
8091 (vrhaddq_m_u32): Likewise.
8092 (vrhaddq_m_u16): Likewise.
8093 (vrmulhq_m_s8): Likewise.
8094 (vrmulhq_m_s32): Likewise.
8095 (vrmulhq_m_s16): Likewise.
8096 (vrmulhq_m_u8): Likewise.
8097 (vrmulhq_m_u32): Likewise.
8098 (vrmulhq_m_u16): Likewise.
8099 (vrshlq_m_s8): Likewise.
8100 (vrshlq_m_s32): Likewise.
8101 (vrshlq_m_s16): Likewise.
8102 (vrshlq_m_u8): Likewise.
8103 (vrshlq_m_u32): Likewise.
8104 (vrshlq_m_u16): Likewise.
8105 (vrshrq_m_n_s8): Likewise.
8106 (vrshrq_m_n_s32): Likewise.
8107 (vrshrq_m_n_s16): Likewise.
8108 (vrshrq_m_n_u8): Likewise.
8109 (vrshrq_m_n_u32): Likewise.
8110 (vrshrq_m_n_u16): Likewise.
8111 (vshlq_m_n_s8): Likewise.
8112 (vshlq_m_n_s32): Likewise.
8113 (vshlq_m_n_s16): Likewise.
8114 (vshlq_m_n_u8): Likewise.
8115 (vshlq_m_n_u32): Likewise.
8116 (vshlq_m_n_u16): Likewise.
8117 (vshrq_m_n_s8): Likewise.
8118 (vshrq_m_n_s32): Likewise.
8119 (vshrq_m_n_s16): Likewise.
8120 (vshrq_m_n_u8): Likewise.
8121 (vshrq_m_n_u32): Likewise.
8122 (vshrq_m_n_u16): Likewise.
8123 (vsliq_m_n_s8): Likewise.
8124 (vsliq_m_n_s32): Likewise.
8125 (vsliq_m_n_s16): Likewise.
8126 (vsliq_m_n_u8): Likewise.
8127 (vsliq_m_n_u32): Likewise.
8128 (vsliq_m_n_u16): Likewise.
8129 (vsubq_m_n_s8): Likewise.
8130 (vsubq_m_n_s32): Likewise.
8131 (vsubq_m_n_s16): Likewise.
8132 (vsubq_m_n_u8): Likewise.
8133 (vsubq_m_n_u32): Likewise.
8134 (vsubq_m_n_u16): Likewise.
8135 (__arm_vabdq_m_s8): Define intrinsic.
8136 (__arm_vabdq_m_s32): Likewise.
8137 (__arm_vabdq_m_s16): Likewise.
8138 (__arm_vabdq_m_u8): Likewise.
8139 (__arm_vabdq_m_u32): Likewise.
8140 (__arm_vabdq_m_u16): Likewise.
8141 (__arm_vaddq_m_n_s8): Likewise.
8142 (__arm_vaddq_m_n_s32): Likewise.
8143 (__arm_vaddq_m_n_s16): Likewise.
8144 (__arm_vaddq_m_n_u8): Likewise.
8145 (__arm_vaddq_m_n_u32): Likewise.
8146 (__arm_vaddq_m_n_u16): Likewise.
8147 (__arm_vaddq_m_s8): Likewise.
8148 (__arm_vaddq_m_s32): Likewise.
8149 (__arm_vaddq_m_s16): Likewise.
8150 (__arm_vaddq_m_u8): Likewise.
8151 (__arm_vaddq_m_u32): Likewise.
8152 (__arm_vaddq_m_u16): Likewise.
8153 (__arm_vandq_m_s8): Likewise.
8154 (__arm_vandq_m_s32): Likewise.
8155 (__arm_vandq_m_s16): Likewise.
8156 (__arm_vandq_m_u8): Likewise.
8157 (__arm_vandq_m_u32): Likewise.
8158 (__arm_vandq_m_u16): Likewise.
8159 (__arm_vbicq_m_s8): Likewise.
8160 (__arm_vbicq_m_s32): Likewise.
8161 (__arm_vbicq_m_s16): Likewise.
8162 (__arm_vbicq_m_u8): Likewise.
8163 (__arm_vbicq_m_u32): Likewise.
8164 (__arm_vbicq_m_u16): Likewise.
8165 (__arm_vbrsrq_m_n_s8): Likewise.
8166 (__arm_vbrsrq_m_n_s32): Likewise.
8167 (__arm_vbrsrq_m_n_s16): Likewise.
8168 (__arm_vbrsrq_m_n_u8): Likewise.
8169 (__arm_vbrsrq_m_n_u32): Likewise.
8170 (__arm_vbrsrq_m_n_u16): Likewise.
8171 (__arm_vcaddq_rot270_m_s8): Likewise.
8172 (__arm_vcaddq_rot270_m_s32): Likewise.
8173 (__arm_vcaddq_rot270_m_s16): Likewise.
8174 (__arm_vcaddq_rot270_m_u8): Likewise.
8175 (__arm_vcaddq_rot270_m_u32): Likewise.
8176 (__arm_vcaddq_rot270_m_u16): Likewise.
8177 (__arm_vcaddq_rot90_m_s8): Likewise.
8178 (__arm_vcaddq_rot90_m_s32): Likewise.
8179 (__arm_vcaddq_rot90_m_s16): Likewise.
8180 (__arm_vcaddq_rot90_m_u8): Likewise.
8181 (__arm_vcaddq_rot90_m_u32): Likewise.
8182 (__arm_vcaddq_rot90_m_u16): Likewise.
8183 (__arm_veorq_m_s8): Likewise.
8184 (__arm_veorq_m_s32): Likewise.
8185 (__arm_veorq_m_s16): Likewise.
8186 (__arm_veorq_m_u8): Likewise.
8187 (__arm_veorq_m_u32): Likewise.
8188 (__arm_veorq_m_u16): Likewise.
8189 (__arm_vhaddq_m_n_s8): Likewise.
8190 (__arm_vhaddq_m_n_s32): Likewise.
8191 (__arm_vhaddq_m_n_s16): Likewise.
8192 (__arm_vhaddq_m_n_u8): Likewise.
8193 (__arm_vhaddq_m_n_u32): Likewise.
8194 (__arm_vhaddq_m_n_u16): Likewise.
8195 (__arm_vhaddq_m_s8): Likewise.
8196 (__arm_vhaddq_m_s32): Likewise.
8197 (__arm_vhaddq_m_s16): Likewise.
8198 (__arm_vhaddq_m_u8): Likewise.
8199 (__arm_vhaddq_m_u32): Likewise.
8200 (__arm_vhaddq_m_u16): Likewise.
8201 (__arm_vhcaddq_rot270_m_s8): Likewise.
8202 (__arm_vhcaddq_rot270_m_s32): Likewise.
8203 (__arm_vhcaddq_rot270_m_s16): Likewise.
8204 (__arm_vhcaddq_rot90_m_s8): Likewise.
8205 (__arm_vhcaddq_rot90_m_s32): Likewise.
8206 (__arm_vhcaddq_rot90_m_s16): Likewise.
8207 (__arm_vhsubq_m_n_s8): Likewise.
8208 (__arm_vhsubq_m_n_s32): Likewise.
8209 (__arm_vhsubq_m_n_s16): Likewise.
8210 (__arm_vhsubq_m_n_u8): Likewise.
8211 (__arm_vhsubq_m_n_u32): Likewise.
8212 (__arm_vhsubq_m_n_u16): Likewise.
8213 (__arm_vhsubq_m_s8): Likewise.
8214 (__arm_vhsubq_m_s32): Likewise.
8215 (__arm_vhsubq_m_s16): Likewise.
8216 (__arm_vhsubq_m_u8): Likewise.
8217 (__arm_vhsubq_m_u32): Likewise.
8218 (__arm_vhsubq_m_u16): Likewise.
8219 (__arm_vmaxq_m_s8): Likewise.
8220 (__arm_vmaxq_m_s32): Likewise.
8221 (__arm_vmaxq_m_s16): Likewise.
8222 (__arm_vmaxq_m_u8): Likewise.
8223 (__arm_vmaxq_m_u32): Likewise.
8224 (__arm_vmaxq_m_u16): Likewise.
8225 (__arm_vminq_m_s8): Likewise.
8226 (__arm_vminq_m_s32): Likewise.
8227 (__arm_vminq_m_s16): Likewise.
8228 (__arm_vminq_m_u8): Likewise.
8229 (__arm_vminq_m_u32): Likewise.
8230 (__arm_vminq_m_u16): Likewise.
8231 (__arm_vmladavaq_p_s8): Likewise.
8232 (__arm_vmladavaq_p_s32): Likewise.
8233 (__arm_vmladavaq_p_s16): Likewise.
8234 (__arm_vmladavaq_p_u8): Likewise.
8235 (__arm_vmladavaq_p_u32): Likewise.
8236 (__arm_vmladavaq_p_u16): Likewise.
8237 (__arm_vmladavaxq_p_s8): Likewise.
8238 (__arm_vmladavaxq_p_s32): Likewise.
8239 (__arm_vmladavaxq_p_s16): Likewise.
8240 (__arm_vmlaq_m_n_s8): Likewise.
8241 (__arm_vmlaq_m_n_s32): Likewise.
8242 (__arm_vmlaq_m_n_s16): Likewise.
8243 (__arm_vmlaq_m_n_u8): Likewise.
8244 (__arm_vmlaq_m_n_u32): Likewise.
8245 (__arm_vmlaq_m_n_u16): Likewise.
8246 (__arm_vmlasq_m_n_s8): Likewise.
8247 (__arm_vmlasq_m_n_s32): Likewise.
8248 (__arm_vmlasq_m_n_s16): Likewise.
8249 (__arm_vmlasq_m_n_u8): Likewise.
8250 (__arm_vmlasq_m_n_u32): Likewise.
8251 (__arm_vmlasq_m_n_u16): Likewise.
8252 (__arm_vmlsdavaq_p_s8): Likewise.
8253 (__arm_vmlsdavaq_p_s32): Likewise.
8254 (__arm_vmlsdavaq_p_s16): Likewise.
8255 (__arm_vmlsdavaxq_p_s8): Likewise.
8256 (__arm_vmlsdavaxq_p_s32): Likewise.
8257 (__arm_vmlsdavaxq_p_s16): Likewise.
8258 (__arm_vmulhq_m_s8): Likewise.
8259 (__arm_vmulhq_m_s32): Likewise.
8260 (__arm_vmulhq_m_s16): Likewise.
8261 (__arm_vmulhq_m_u8): Likewise.
8262 (__arm_vmulhq_m_u32): Likewise.
8263 (__arm_vmulhq_m_u16): Likewise.
8264 (__arm_vmullbq_int_m_s8): Likewise.
8265 (__arm_vmullbq_int_m_s32): Likewise.
8266 (__arm_vmullbq_int_m_s16): Likewise.
8267 (__arm_vmullbq_int_m_u8): Likewise.
8268 (__arm_vmullbq_int_m_u32): Likewise.
8269 (__arm_vmullbq_int_m_u16): Likewise.
8270 (__arm_vmulltq_int_m_s8): Likewise.
8271 (__arm_vmulltq_int_m_s32): Likewise.
8272 (__arm_vmulltq_int_m_s16): Likewise.
8273 (__arm_vmulltq_int_m_u8): Likewise.
8274 (__arm_vmulltq_int_m_u32): Likewise.
8275 (__arm_vmulltq_int_m_u16): Likewise.
8276 (__arm_vmulq_m_n_s8): Likewise.
8277 (__arm_vmulq_m_n_s32): Likewise.
8278 (__arm_vmulq_m_n_s16): Likewise.
8279 (__arm_vmulq_m_n_u8): Likewise.
8280 (__arm_vmulq_m_n_u32): Likewise.
8281 (__arm_vmulq_m_n_u16): Likewise.
8282 (__arm_vmulq_m_s8): Likewise.
8283 (__arm_vmulq_m_s32): Likewise.
8284 (__arm_vmulq_m_s16): Likewise.
8285 (__arm_vmulq_m_u8): Likewise.
8286 (__arm_vmulq_m_u32): Likewise.
8287 (__arm_vmulq_m_u16): Likewise.
8288 (__arm_vornq_m_s8): Likewise.
8289 (__arm_vornq_m_s32): Likewise.
8290 (__arm_vornq_m_s16): Likewise.
8291 (__arm_vornq_m_u8): Likewise.
8292 (__arm_vornq_m_u32): Likewise.
8293 (__arm_vornq_m_u16): Likewise.
8294 (__arm_vorrq_m_s8): Likewise.
8295 (__arm_vorrq_m_s32): Likewise.
8296 (__arm_vorrq_m_s16): Likewise.
8297 (__arm_vorrq_m_u8): Likewise.
8298 (__arm_vorrq_m_u32): Likewise.
8299 (__arm_vorrq_m_u16): Likewise.
8300 (__arm_vqaddq_m_n_s8): Likewise.
8301 (__arm_vqaddq_m_n_s32): Likewise.
8302 (__arm_vqaddq_m_n_s16): Likewise.
8303 (__arm_vqaddq_m_n_u8): Likewise.
8304 (__arm_vqaddq_m_n_u32): Likewise.
8305 (__arm_vqaddq_m_n_u16): Likewise.
8306 (__arm_vqaddq_m_s8): Likewise.
8307 (__arm_vqaddq_m_s32): Likewise.
8308 (__arm_vqaddq_m_s16): Likewise.
8309 (__arm_vqaddq_m_u8): Likewise.
8310 (__arm_vqaddq_m_u32): Likewise.
8311 (__arm_vqaddq_m_u16): Likewise.
8312 (__arm_vqdmladhq_m_s8): Likewise.
8313 (__arm_vqdmladhq_m_s32): Likewise.
8314 (__arm_vqdmladhq_m_s16): Likewise.
8315 (__arm_vqdmladhxq_m_s8): Likewise.
8316 (__arm_vqdmladhxq_m_s32): Likewise.
8317 (__arm_vqdmladhxq_m_s16): Likewise.
8318 (__arm_vqdmlahq_m_n_s8): Likewise.
8319 (__arm_vqdmlahq_m_n_s32): Likewise.
8320 (__arm_vqdmlahq_m_n_s16): Likewise.
8321 (__arm_vqdmlahq_m_n_u8): Likewise.
8322 (__arm_vqdmlahq_m_n_u32): Likewise.
8323 (__arm_vqdmlahq_m_n_u16): Likewise.
8324 (__arm_vqdmlsdhq_m_s8): Likewise.
8325 (__arm_vqdmlsdhq_m_s32): Likewise.
8326 (__arm_vqdmlsdhq_m_s16): Likewise.
8327 (__arm_vqdmlsdhxq_m_s8): Likewise.
8328 (__arm_vqdmlsdhxq_m_s32): Likewise.
8329 (__arm_vqdmlsdhxq_m_s16): Likewise.
8330 (__arm_vqdmulhq_m_n_s8): Likewise.
8331 (__arm_vqdmulhq_m_n_s32): Likewise.
8332 (__arm_vqdmulhq_m_n_s16): Likewise.
8333 (__arm_vqdmulhq_m_s8): Likewise.
8334 (__arm_vqdmulhq_m_s32): Likewise.
8335 (__arm_vqdmulhq_m_s16): Likewise.
8336 (__arm_vqrdmladhq_m_s8): Likewise.
8337 (__arm_vqrdmladhq_m_s32): Likewise.
8338 (__arm_vqrdmladhq_m_s16): Likewise.
8339 (__arm_vqrdmladhxq_m_s8): Likewise.
8340 (__arm_vqrdmladhxq_m_s32): Likewise.
8341 (__arm_vqrdmladhxq_m_s16): Likewise.
8342 (__arm_vqrdmlahq_m_n_s8): Likewise.
8343 (__arm_vqrdmlahq_m_n_s32): Likewise.
8344 (__arm_vqrdmlahq_m_n_s16): Likewise.
8345 (__arm_vqrdmlahq_m_n_u8): Likewise.
8346 (__arm_vqrdmlahq_m_n_u32): Likewise.
8347 (__arm_vqrdmlahq_m_n_u16): Likewise.
8348 (__arm_vqrdmlashq_m_n_s8): Likewise.
8349 (__arm_vqrdmlashq_m_n_s32): Likewise.
8350 (__arm_vqrdmlashq_m_n_s16): Likewise.
8351 (__arm_vqrdmlashq_m_n_u8): Likewise.
8352 (__arm_vqrdmlashq_m_n_u32): Likewise.
8353 (__arm_vqrdmlashq_m_n_u16): Likewise.
8354 (__arm_vqrdmlsdhq_m_s8): Likewise.
8355 (__arm_vqrdmlsdhq_m_s32): Likewise.
8356 (__arm_vqrdmlsdhq_m_s16): Likewise.
8357 (__arm_vqrdmlsdhxq_m_s8): Likewise.
8358 (__arm_vqrdmlsdhxq_m_s32): Likewise.
8359 (__arm_vqrdmlsdhxq_m_s16): Likewise.
8360 (__arm_vqrdmulhq_m_n_s8): Likewise.
8361 (__arm_vqrdmulhq_m_n_s32): Likewise.
8362 (__arm_vqrdmulhq_m_n_s16): Likewise.
8363 (__arm_vqrdmulhq_m_s8): Likewise.
8364 (__arm_vqrdmulhq_m_s32): Likewise.
8365 (__arm_vqrdmulhq_m_s16): Likewise.
8366 (__arm_vqrshlq_m_s8): Likewise.
8367 (__arm_vqrshlq_m_s32): Likewise.
8368 (__arm_vqrshlq_m_s16): Likewise.
8369 (__arm_vqrshlq_m_u8): Likewise.
8370 (__arm_vqrshlq_m_u32): Likewise.
8371 (__arm_vqrshlq_m_u16): Likewise.
8372 (__arm_vqshlq_m_n_s8): Likewise.
8373 (__arm_vqshlq_m_n_s32): Likewise.
8374 (__arm_vqshlq_m_n_s16): Likewise.
8375 (__arm_vqshlq_m_n_u8): Likewise.
8376 (__arm_vqshlq_m_n_u32): Likewise.
8377 (__arm_vqshlq_m_n_u16): Likewise.
8378 (__arm_vqshlq_m_s8): Likewise.
8379 (__arm_vqshlq_m_s32): Likewise.
8380 (__arm_vqshlq_m_s16): Likewise.
8381 (__arm_vqshlq_m_u8): Likewise.
8382 (__arm_vqshlq_m_u32): Likewise.
8383 (__arm_vqshlq_m_u16): Likewise.
8384 (__arm_vqsubq_m_n_s8): Likewise.
8385 (__arm_vqsubq_m_n_s32): Likewise.
8386 (__arm_vqsubq_m_n_s16): Likewise.
8387 (__arm_vqsubq_m_n_u8): Likewise.
8388 (__arm_vqsubq_m_n_u32): Likewise.
8389 (__arm_vqsubq_m_n_u16): Likewise.
8390 (__arm_vqsubq_m_s8): Likewise.
8391 (__arm_vqsubq_m_s32): Likewise.
8392 (__arm_vqsubq_m_s16): Likewise.
8393 (__arm_vqsubq_m_u8): Likewise.
8394 (__arm_vqsubq_m_u32): Likewise.
8395 (__arm_vqsubq_m_u16): Likewise.
8396 (__arm_vrhaddq_m_s8): Likewise.
8397 (__arm_vrhaddq_m_s32): Likewise.
8398 (__arm_vrhaddq_m_s16): Likewise.
8399 (__arm_vrhaddq_m_u8): Likewise.
8400 (__arm_vrhaddq_m_u32): Likewise.
8401 (__arm_vrhaddq_m_u16): Likewise.
8402 (__arm_vrmulhq_m_s8): Likewise.
8403 (__arm_vrmulhq_m_s32): Likewise.
8404 (__arm_vrmulhq_m_s16): Likewise.
8405 (__arm_vrmulhq_m_u8): Likewise.
8406 (__arm_vrmulhq_m_u32): Likewise.
8407 (__arm_vrmulhq_m_u16): Likewise.
8408 (__arm_vrshlq_m_s8): Likewise.
8409 (__arm_vrshlq_m_s32): Likewise.
8410 (__arm_vrshlq_m_s16): Likewise.
8411 (__arm_vrshlq_m_u8): Likewise.
8412 (__arm_vrshlq_m_u32): Likewise.
8413 (__arm_vrshlq_m_u16): Likewise.
8414 (__arm_vrshrq_m_n_s8): Likewise.
8415 (__arm_vrshrq_m_n_s32): Likewise.
8416 (__arm_vrshrq_m_n_s16): Likewise.
8417 (__arm_vrshrq_m_n_u8): Likewise.
8418 (__arm_vrshrq_m_n_u32): Likewise.
8419 (__arm_vrshrq_m_n_u16): Likewise.
8420 (__arm_vshlq_m_n_s8): Likewise.
8421 (__arm_vshlq_m_n_s32): Likewise.
8422 (__arm_vshlq_m_n_s16): Likewise.
8423 (__arm_vshlq_m_n_u8): Likewise.
8424 (__arm_vshlq_m_n_u32): Likewise.
8425 (__arm_vshlq_m_n_u16): Likewise.
8426 (__arm_vshrq_m_n_s8): Likewise.
8427 (__arm_vshrq_m_n_s32): Likewise.
8428 (__arm_vshrq_m_n_s16): Likewise.
8429 (__arm_vshrq_m_n_u8): Likewise.
8430 (__arm_vshrq_m_n_u32): Likewise.
8431 (__arm_vshrq_m_n_u16): Likewise.
8432 (__arm_vsliq_m_n_s8): Likewise.
8433 (__arm_vsliq_m_n_s32): Likewise.
8434 (__arm_vsliq_m_n_s16): Likewise.
8435 (__arm_vsliq_m_n_u8): Likewise.
8436 (__arm_vsliq_m_n_u32): Likewise.
8437 (__arm_vsliq_m_n_u16): Likewise.
8438 (__arm_vsubq_m_n_s8): Likewise.
8439 (__arm_vsubq_m_n_s32): Likewise.
8440 (__arm_vsubq_m_n_s16): Likewise.
8441 (__arm_vsubq_m_n_u8): Likewise.
8442 (__arm_vsubq_m_n_u32): Likewise.
8443 (__arm_vsubq_m_n_u16): Likewise.
8444 (vqdmladhq_m): Define polymorphic variant.
8445 (vqdmladhxq_m): Likewise.
8446 (vqdmlsdhq_m): Likewise.
8447 (vqdmlsdhxq_m): Likewise.
8448 (vabdq_m): Likewise.
8449 (vandq_m): Likewise.
8450 (vbicq_m): Likewise.
8451 (vbrsrq_m_n): Likewise.
8452 (vcaddq_rot270_m): Likewise.
8453 (vcaddq_rot90_m): Likewise.
8454 (veorq_m): Likewise.
8455 (vmaxq_m): Likewise.
8456 (vminq_m): Likewise.
8457 (vmladavaq_p): Likewise.
8458 (vmlaq_m_n): Likewise.
8459 (vmlasq_m_n): Likewise.
8460 (vmulhq_m): Likewise.
8461 (vmullbq_int_m): Likewise.
8462 (vmulltq_int_m): Likewise.
8463 (vornq_m): Likewise.
8464 (vorrq_m): Likewise.
8465 (vqdmlahq_m_n): Likewise.
8466 (vqrdmlahq_m_n): Likewise.
8467 (vqrdmlashq_m_n): Likewise.
8468 (vqrshlq_m): Likewise.
8469 (vqshlq_m_n): Likewise.
8470 (vqshlq_m): Likewise.
8471 (vrhaddq_m): Likewise.
8472 (vrmulhq_m): Likewise.
8473 (vrshlq_m): Likewise.
8474 (vrshrq_m_n): Likewise.
8475 (vshlq_m_n): Likewise.
8476 (vshrq_m_n): Likewise.
8477 (vsliq_m): Likewise.
8478 (vaddq_m_n): Likewise.
8479 (vaddq_m): Likewise.
8480 (vhaddq_m_n): Likewise.
8481 (vhaddq_m): Likewise.
8482 (vhcaddq_rot270_m): Likewise.
8483 (vhcaddq_rot90_m): Likewise.
8484 (vhsubq_m): Likewise.
8485 (vhsubq_m_n): Likewise.
8486 (vmulq_m_n): Likewise.
8487 (vmulq_m): Likewise.
8488 (vqaddq_m_n): Likewise.
8489 (vqaddq_m): Likewise.
8490 (vqdmulhq_m_n): Likewise.
8491 (vqdmulhq_m): Likewise.
8492 (vsubq_m_n): Likewise.
8493 (vsliq_m_n): Likewise.
8494 (vqsubq_m_n): Likewise.
8495 (vqsubq_m): Likewise.
8496 (vqrdmulhq_m): Likewise.
8497 (vqrdmulhq_m_n): Likewise.
8498 (vqrdmlsdhxq_m): Likewise.
8499 (vqrdmlsdhq_m): Likewise.
8500 (vqrdmladhq_m): Likewise.
8501 (vqrdmladhxq_m): Likewise.
8502 (vmlsdavaxq_p): Likewise.
8503 (vmlsdavaq_p): Likewise.
8504 (vmladavaxq_p): Likewise.
8505 * config/arm/arm_mve_builtins.def (QUADOP_NONE_NONE_NONE_IMM_UNONE): Use
8507 (QUADOP_NONE_NONE_NONE_NONE_UNONE): Likewise.
8508 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE): Likewise.
8509 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE): Likewise.
8510 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE): Likewise.
8511 * config/arm/mve.md (VHSUBQ_M): Define iterators.
8512 (VSLIQ_M_N): Likewise.
8513 (VQRDMLAHQ_M_N): Likewise.
8514 (VRSHLQ_M): Likewise.
8515 (VMINQ_M): Likewise.
8516 (VMULLBQ_INT_M): Likewise.
8517 (VMULHQ_M): Likewise.
8518 (VMULQ_M): Likewise.
8519 (VHSUBQ_M_N): Likewise.
8520 (VHADDQ_M_N): Likewise.
8521 (VORRQ_M): Likewise.
8522 (VRMULHQ_M): Likewise.
8523 (VQADDQ_M): Likewise.
8524 (VRSHRQ_M_N): Likewise.
8525 (VQSUBQ_M_N): Likewise.
8526 (VADDQ_M): Likewise.
8527 (VORNQ_M): Likewise.
8528 (VQDMLAHQ_M_N): Likewise.
8529 (VRHADDQ_M): Likewise.
8530 (VQSHLQ_M): Likewise.
8531 (VANDQ_M): Likewise.
8532 (VBICQ_M): Likewise.
8533 (VSHLQ_M_N): Likewise.
8534 (VCADDQ_ROT270_M): Likewise.
8535 (VQRSHLQ_M): Likewise.
8536 (VQADDQ_M_N): Likewise.
8537 (VADDQ_M_N): Likewise.
8538 (VMAXQ_M): Likewise.
8539 (VQSUBQ_M): Likewise.
8540 (VMLASQ_M_N): Likewise.
8541 (VMLADAVAQ_P): Likewise.
8542 (VBRSRQ_M_N): Likewise.
8543 (VMULQ_M_N): Likewise.
8544 (VCADDQ_ROT90_M): Likewise.
8545 (VMULLTQ_INT_M): Likewise.
8546 (VEORQ_M): Likewise.
8547 (VSHRQ_M_N): Likewise.
8548 (VSUBQ_M_N): Likewise.
8549 (VHADDQ_M): Likewise.
8550 (VABDQ_M): Likewise.
8551 (VQRDMLASHQ_M_N): Likewise.
8552 (VMLAQ_M_N): Likewise.
8553 (VQSHLQ_M_N): Likewise.
8554 (mve_vabdq_m_<supf><mode>): Define RTL pattern.
8555 (mve_vaddq_m_n_<supf><mode>): Likewise.
8556 (mve_vaddq_m_<supf><mode>): Likewise.
8557 (mve_vandq_m_<supf><mode>): Likewise.
8558 (mve_vbicq_m_<supf><mode>): Likewise.
8559 (mve_vbrsrq_m_n_<supf><mode>): Likewise.
8560 (mve_vcaddq_rot270_m_<supf><mode>): Likewise.
8561 (mve_vcaddq_rot90_m_<supf><mode>): Likewise.
8562 (mve_veorq_m_<supf><mode>): Likewise.
8563 (mve_vhaddq_m_n_<supf><mode>): Likewise.
8564 (mve_vhaddq_m_<supf><mode>): Likewise.
8565 (mve_vhsubq_m_n_<supf><mode>): Likewise.
8566 (mve_vhsubq_m_<supf><mode>): Likewise.
8567 (mve_vmaxq_m_<supf><mode>): Likewise.
8568 (mve_vminq_m_<supf><mode>): Likewise.
8569 (mve_vmladavaq_p_<supf><mode>): Likewise.
8570 (mve_vmlaq_m_n_<supf><mode>): Likewise.
8571 (mve_vmlasq_m_n_<supf><mode>): Likewise.
8572 (mve_vmulhq_m_<supf><mode>): Likewise.
8573 (mve_vmullbq_int_m_<supf><mode>): Likewise.
8574 (mve_vmulltq_int_m_<supf><mode>): Likewise.
8575 (mve_vmulq_m_n_<supf><mode>): Likewise.
8576 (mve_vmulq_m_<supf><mode>): Likewise.
8577 (mve_vornq_m_<supf><mode>): Likewise.
8578 (mve_vorrq_m_<supf><mode>): Likewise.
8579 (mve_vqaddq_m_n_<supf><mode>): Likewise.
8580 (mve_vqaddq_m_<supf><mode>): Likewise.
8581 (mve_vqdmlahq_m_n_<supf><mode>): Likewise.
8582 (mve_vqrdmlahq_m_n_<supf><mode>): Likewise.
8583 (mve_vqrdmlashq_m_n_<supf><mode>): Likewise.
8584 (mve_vqrshlq_m_<supf><mode>): Likewise.
8585 (mve_vqshlq_m_n_<supf><mode>): Likewise.
8586 (mve_vqshlq_m_<supf><mode>): Likewise.
8587 (mve_vqsubq_m_n_<supf><mode>): Likewise.
8588 (mve_vqsubq_m_<supf><mode>): Likewise.
8589 (mve_vrhaddq_m_<supf><mode>): Likewise.
8590 (mve_vrmulhq_m_<supf><mode>): Likewise.
8591 (mve_vrshlq_m_<supf><mode>): Likewise.
8592 (mve_vrshrq_m_n_<supf><mode>): Likewise.
8593 (mve_vshlq_m_n_<supf><mode>): Likewise.
8594 (mve_vshrq_m_n_<supf><mode>): Likewise.
8595 (mve_vsliq_m_n_<supf><mode>): Likewise.
8596 (mve_vsubq_m_n_<supf><mode>): Likewise.
8597 (mve_vhcaddq_rot270_m_s<mode>): Likewise.
8598 (mve_vhcaddq_rot90_m_s<mode>): Likewise.
8599 (mve_vmladavaxq_p_s<mode>): Likewise.
8600 (mve_vmlsdavaq_p_s<mode>): Likewise.
8601 (mve_vmlsdavaxq_p_s<mode>): Likewise.
8602 (mve_vqdmladhq_m_s<mode>): Likewise.
8603 (mve_vqdmladhxq_m_s<mode>): Likewise.
8604 (mve_vqdmlsdhq_m_s<mode>): Likewise.
8605 (mve_vqdmlsdhxq_m_s<mode>): Likewise.
8606 (mve_vqdmulhq_m_n_s<mode>): Likewise.
8607 (mve_vqdmulhq_m_s<mode>): Likewise.
8608 (mve_vqrdmladhq_m_s<mode>): Likewise.
8609 (mve_vqrdmladhxq_m_s<mode>): Likewise.
8610 (mve_vqrdmlsdhq_m_s<mode>): Likewise.
8611 (mve_vqrdmlsdhxq_m_s<mode>): Likewise.
8612 (mve_vqrdmulhq_m_n_s<mode>): Likewise.
8613 (mve_vqrdmulhq_m_s<mode>): Likewise.
8615 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8616 Mihail Ionescu <mihail.ionescu@arm.com>
8617 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8619 * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS):
8620 Define builtin qualifier.
8621 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8622 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8623 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8624 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8625 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8626 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8627 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8628 * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro.
8629 (vsubq_m_s8): Likewise.
8630 (vcvtq_m_n_f16_u16): Likewise.
8631 (vqshluq_m_n_s8): Likewise.
8632 (vabavq_p_s8): Likewise.
8633 (vsriq_m_n_u8): Likewise.
8634 (vshlq_m_u8): Likewise.
8635 (vsubq_m_u8): Likewise.
8636 (vabavq_p_u8): Likewise.
8637 (vshlq_m_s8): Likewise.
8638 (vcvtq_m_n_f16_s16): Likewise.
8639 (vsriq_m_n_s16): Likewise.
8640 (vsubq_m_s16): Likewise.
8641 (vcvtq_m_n_f32_u32): Likewise.
8642 (vqshluq_m_n_s16): Likewise.
8643 (vabavq_p_s16): Likewise.
8644 (vsriq_m_n_u16): Likewise.
8645 (vshlq_m_u16): Likewise.
8646 (vsubq_m_u16): Likewise.
8647 (vabavq_p_u16): Likewise.
8648 (vshlq_m_s16): Likewise.
8649 (vcvtq_m_n_f32_s32): Likewise.
8650 (vsriq_m_n_s32): Likewise.
8651 (vsubq_m_s32): Likewise.
8652 (vqshluq_m_n_s32): Likewise.
8653 (vabavq_p_s32): Likewise.
8654 (vsriq_m_n_u32): Likewise.
8655 (vshlq_m_u32): Likewise.
8656 (vsubq_m_u32): Likewise.
8657 (vabavq_p_u32): Likewise.
8658 (vshlq_m_s32): Likewise.
8659 (__arm_vsriq_m_n_s8): Define intrinsic.
8660 (__arm_vsubq_m_s8): Likewise.
8661 (__arm_vqshluq_m_n_s8): Likewise.
8662 (__arm_vabavq_p_s8): Likewise.
8663 (__arm_vsriq_m_n_u8): Likewise.
8664 (__arm_vshlq_m_u8): Likewise.
8665 (__arm_vsubq_m_u8): Likewise.
8666 (__arm_vabavq_p_u8): Likewise.
8667 (__arm_vshlq_m_s8): Likewise.
8668 (__arm_vsriq_m_n_s16): Likewise.
8669 (__arm_vsubq_m_s16): Likewise.
8670 (__arm_vqshluq_m_n_s16): Likewise.
8671 (__arm_vabavq_p_s16): Likewise.
8672 (__arm_vsriq_m_n_u16): Likewise.
8673 (__arm_vshlq_m_u16): Likewise.
8674 (__arm_vsubq_m_u16): Likewise.
8675 (__arm_vabavq_p_u16): Likewise.
8676 (__arm_vshlq_m_s16): Likewise.
8677 (__arm_vsriq_m_n_s32): Likewise.
8678 (__arm_vsubq_m_s32): Likewise.
8679 (__arm_vqshluq_m_n_s32): Likewise.
8680 (__arm_vabavq_p_s32): Likewise.
8681 (__arm_vsriq_m_n_u32): Likewise.
8682 (__arm_vshlq_m_u32): Likewise.
8683 (__arm_vsubq_m_u32): Likewise.
8684 (__arm_vabavq_p_u32): Likewise.
8685 (__arm_vshlq_m_s32): Likewise.
8686 (__arm_vcvtq_m_n_f16_u16): Likewise.
8687 (__arm_vcvtq_m_n_f16_s16): Likewise.
8688 (__arm_vcvtq_m_n_f32_u32): Likewise.
8689 (__arm_vcvtq_m_n_f32_s32): Likewise.
8690 (vcvtq_m_n): Define polymorphic variant.
8691 (vqshluq_m_n): Likewise.
8692 (vshlq_m): Likewise.
8693 (vsriq_m_n): Likewise.
8694 (vsubq_m): Likewise.
8695 (vabavq_p): Likewise.
8696 * config/arm/arm_mve_builtins.def
8697 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier.
8698 (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
8699 (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8700 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
8701 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
8702 (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8703 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
8704 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
8705 * config/arm/mve.md (VABAVQ_P): Define iterator.
8706 (VSHLQ_M): Likewise.
8707 (VSRIQ_M_N): Likewise.
8708 (VSUBQ_M): Likewise.
8709 (VCVTQ_M_N_TO_F): Likewise.
8710 (mve_vabavq_p_<supf><mode>): Define RTL pattern.
8711 (mve_vqshluq_m_n_s<mode>): Likewise.
8712 (mve_vshlq_m_<supf><mode>): Likewise.
8713 (mve_vsriq_m_n_<supf><mode>): Likewise.
8714 (mve_vsubq_m_<supf><mode>): Likewise.
8715 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
8717 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
8718 Mihail Ionescu <mihail.ionescu@arm.com>
8719 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
8721 * config/arm/arm_mve.h (vrmlaldavhaxq_s32): Define macro.
8722 (vrmlsldavhaq_s32): Likewise.
8723 (vrmlsldavhaxq_s32): Likewise.
8724 (vaddlvaq_p_s32): Likewise.
8725 (vcvtbq_m_f16_f32): Likewise.
8726 (vcvtbq_m_f32_f16): Likewise.
8727 (vcvttq_m_f16_f32): Likewise.
8728 (vcvttq_m_f32_f16): Likewise.
8729 (vrev16q_m_s8): Likewise.
8730 (vrev32q_m_f16): Likewise.
8731 (vrmlaldavhq_p_s32): Likewise.
8732 (vrmlaldavhxq_p_s32): Likewise.
8733 (vrmlsldavhq_p_s32): Likewise.
8734 (vrmlsldavhxq_p_s32): Likewise.
8735 (vaddlvaq_p_u32): Likewise.
8736 (vrev16q_m_u8): Likewise.
8737 (vrmlaldavhq_p_u32): Likewise.
8738 (vmvnq_m_n_s16): Likewise.
8739 (vorrq_m_n_s16): Likewise.
8740 (vqrshrntq_n_s16): Likewise.
8741 (vqshrnbq_n_s16): Likewise.
8742 (vqshrntq_n_s16): Likewise.
8743 (vrshrnbq_n_s16): Likewise.
8744 (vrshrntq_n_s16): Likewise.
8745 (vshrnbq_n_s16): Likewise.
8746 (vshrntq_n_s16): Likewise.
8747 (vcmlaq_f16): Likewise.
8748 (vcmlaq_rot180_f16): Likewise.
8749 (vcmlaq_rot270_f16): Likewise.
8750 (vcmlaq_rot90_f16): Likewise.
8751 (vfmaq_f16): Likewise.
8752 (vfmaq_n_f16): Likewise.
8753 (vfmasq_n_f16): Likewise.
8754 (vfmsq_f16): Likewise.
8755 (vmlaldavaq_s16): Likewise.
8756 (vmlaldavaxq_s16): Likewise.
8757 (vmlsldavaq_s16): Likewise.
8758 (vmlsldavaxq_s16): Likewise.
8759 (vabsq_m_f16): Likewise.
8760 (vcvtmq_m_s16_f16): Likewise.
8761 (vcvtnq_m_s16_f16): Likewise.
8762 (vcvtpq_m_s16_f16): Likewise.
8763 (vcvtq_m_s16_f16): Likewise.
8764 (vdupq_m_n_f16): Likewise.
8765 (vmaxnmaq_m_f16): Likewise.
8766 (vmaxnmavq_p_f16): Likewise.
8767 (vmaxnmvq_p_f16): Likewise.
8768 (vminnmaq_m_f16): Likewise.
8769 (vminnmavq_p_f16): Likewise.
8770 (vminnmvq_p_f16): Likewise.
8771 (vmlaldavq_p_s16): Likewise.
8772 (vmlaldavxq_p_s16): Likewise.
8773 (vmlsldavq_p_s16): Likewise.
8774 (vmlsldavxq_p_s16): Likewise.
8775 (vmovlbq_m_s8): Likewise.
8776 (vmovltq_m_s8): Likewise.
8777 (vmovnbq_m_s16): Likewise.
8778 (vmovntq_m_s16): Likewise.
8779 (vnegq_m_f16): Likewise.
8780 (vpselq_f16): Likewise.
8781 (vqmovnbq_m_s16): Likewise.
8782 (vqmovntq_m_s16): Likewise.
8783 (vrev32q_m_s8): Likewise.
8784 (vrev64q_m_f16): Likewise.
8785 (vrndaq_m_f16): Likewise.
8786 (vrndmq_m_f16): Likewise.
8787 (vrndnq_m_f16): Likewise.
8788 (vrndpq_m_f16): Likewise.
8789 (vrndq_m_f16): Likewise.
8790 (vrndxq_m_f16): Likewise.
8791 (vcmpeqq_m_n_f16): Likewise.
8792 (vcmpgeq_m_f16): Likewise.
8793 (vcmpgeq_m_n_f16): Likewise.
8794 (vcmpgtq_m_f16): Likewise.
8795 (vcmpgtq_m_n_f16): Likewise.
8796 (vcmpleq_m_f16): Likewise.
8797 (vcmpleq_m_n_f16): Likewise.
8798 (vcmpltq_m_f16): Likewise.
8799 (vcmpltq_m_n_f16): Likewise.
8800 (vcmpneq_m_f16): Likewise.
8801 (vcmpneq_m_n_f16): Likewise.
8802 (vmvnq_m_n_u16): Likewise.
8803 (vorrq_m_n_u16): Likewise.
8804 (vqrshruntq_n_s16): Likewise.
8805 (vqshrunbq_n_s16): Likewise.
8806 (vqshruntq_n_s16): Likewise.
8807 (vcvtmq_m_u16_f16): Likewise.
8808 (vcvtnq_m_u16_f16): Likewise.
8809 (vcvtpq_m_u16_f16): Likewise.
8810 (vcvtq_m_u16_f16): Likewise.
8811 (vqmovunbq_m_s16): Likewise.
8812 (vqmovuntq_m_s16): Likewise.
8813 (vqrshrntq_n_u16): Likewise.
8814 (vqshrnbq_n_u16): Likewise.
8815 (vqshrntq_n_u16): Likewise.
8816 (vrshrnbq_n_u16): Likewise.
8817 (vrshrntq_n_u16): Likewise.
8818 (vshrnbq_n_u16): Likewise.
8819 (vshrntq_n_u16): Likewise.
8820 (vmlaldavaq_u16): Likewise.
8821 (vmlaldavaxq_u16): Likewise.
8822 (vmlaldavq_p_u16): Likewise.
8823 (vmlaldavxq_p_u16): Likewise.
8824 (vmovlbq_m_u8): Likewise.
8825 (vmovltq_m_u8): Likewise.
8826 (vmovnbq_m_u16): Likewise.
8827 (vmovntq_m_u16): Likewise.
8828 (vqmovnbq_m_u16): Likewise.
8829 (vqmovntq_m_u16): Likewise.
8830 (vrev32q_m_u8): Likewise.
8831 (vmvnq_m_n_s32): Likewise.
8832 (vorrq_m_n_s32): Likewise.
8833 (vqrshrntq_n_s32): Likewise.
8834 (vqshrnbq_n_s32): Likewise.
8835 (vqshrntq_n_s32): Likewise.
8836 (vrshrnbq_n_s32): Likewise.
8837 (vrshrntq_n_s32): Likewise.
8838 (vshrnbq_n_s32): Likewise.
8839 (vshrntq_n_s32): Likewise.
8840 (vcmlaq_f32): Likewise.
8841 (vcmlaq_rot180_f32): Likewise.
8842 (vcmlaq_rot270_f32): Likewise.
8843 (vcmlaq_rot90_f32): Likewise.
8844 (vfmaq_f32): Likewise.
8845 (vfmaq_n_f32): Likewise.
8846 (vfmasq_n_f32): Likewise.
8847 (vfmsq_f32): Likewise.
8848 (vmlaldavaq_s32): Likewise.
8849 (vmlaldavaxq_s32): Likewise.
8850 (vmlsldavaq_s32): Likewise.
8851 (vmlsldavaxq_s32): Likewise.
8852 (vabsq_m_f32): Likewise.
8853 (vcvtmq_m_s32_f32): Likewise.
8854 (vcvtnq_m_s32_f32): Likewise.
8855 (vcvtpq_m_s32_f32): Likewise.
8856 (vcvtq_m_s32_f32): Likewise.
8857 (vdupq_m_n_f32): Likewise.
8858 (vmaxnmaq_m_f32): Likewise.
8859 (vmaxnmavq_p_f32): Likewise.
8860 (vmaxnmvq_p_f32): Likewise.
8861 (vminnmaq_m_f32): Likewise.
8862 (vminnmavq_p_f32): Likewise.
8863 (vminnmvq_p_f32): Likewise.
8864 (vmlaldavq_p_s32): Likewise.
8865 (vmlaldavxq_p_s32): Likewise.
8866 (vmlsldavq_p_s32): Likewise.
8867 (vmlsldavxq_p_s32): Likewise.
8868 (vmovlbq_m_s16): Likewise.
8869 (vmovltq_m_s16): Likewise.
8870 (vmovnbq_m_s32): Likewise.
8871 (vmovntq_m_s32): Likewise.
8872 (vnegq_m_f32): Likewise.
8873 (vpselq_f32): Likewise.
8874 (vqmovnbq_m_s32): Likewise.
8875 (vqmovntq_m_s32): Likewise.
8876 (vrev32q_m_s16): Likewise.
8877 (vrev64q_m_f32): Likewise.
8878 (vrndaq_m_f32): Likewise.
8879 (vrndmq_m_f32): Likewise.
8880 (vrndnq_m_f32): Likewise.
8881 (vrndpq_m_f32): Likewise.
8882 (vrndq_m_f32): Likewise.
8883 (vrndxq_m_f32): Likewise.
8884 (vcmpeqq_m_n_f32): Likewise.
8885 (vcmpgeq_m_f32): Likewise.
8886 (vcmpgeq_m_n_f32): Likewise.
8887 (vcmpgtq_m_f32): Likewise.
8888 (vcmpgtq_m_n_f32): Likewise.
8889 (vcmpleq_m_f32): Likewise.
8890 (vcmpleq_m_n_f32): Likewise.
8891 (vcmpltq_m_f32): Likewise.
8892 (vcmpltq_m_n_f32): Likewise.
8893 (vcmpneq_m_f32): Likewise.
8894 (vcmpneq_m_n_f32): Likewise.
8895 (vmvnq_m_n_u32): Likewise.
8896 (vorrq_m_n_u32): Likewise.
8897 (vqrshruntq_n_s32): Likewise.
8898 (vqshrunbq_n_s32): Likewise.
8899 (vqshruntq_n_s32): Likewise.
8900 (vcvtmq_m_u32_f32): Likewise.
8901 (vcvtnq_m_u32_f32): Likewise.
8902 (vcvtpq_m_u32_f32): Likewise.
8903 (vcvtq_m_u32_f32): Likewise.
8904 (vqmovunbq_m_s32): Likewise.
8905 (vqmovuntq_m_s32): Likewise.
8906 (vqrshrntq_n_u32): Likewise.
8907 (vqshrnbq_n_u32): Likewise.
8908 (vqshrntq_n_u32): Likewise.
8909 (vrshrnbq_n_u32): Likewise.
8910 (vrshrntq_n_u32): Likewise.
8911 (vshrnbq_n_u32): Likewise.
8912 (vshrntq_n_u32): Likewise.
8913 (vmlaldavaq_u32): Likewise.
8914 (vmlaldavaxq_u32): Likewise.
8915 (vmlaldavq_p_u32): Likewise.
8916 (vmlaldavxq_p_u32): Likewise.
8917 (vmovlbq_m_u16): Likewise.
8918 (vmovltq_m_u16): Likewise.
8919 (vmovnbq_m_u32): Likewise.
8920 (vmovntq_m_u32): Likewise.
8921 (vqmovnbq_m_u32): Likewise.
8922 (vqmovntq_m_u32): Likewise.
8923 (vrev32q_m_u16): Likewise.
8924 (__arm_vrmlaldavhaxq_s32): Define intrinsic.
8925 (__arm_vrmlsldavhaq_s32): Likewise.
8926 (__arm_vrmlsldavhaxq_s32): Likewise.
8927 (__arm_vaddlvaq_p_s32): Likewise.
8928 (__arm_vrev16q_m_s8): Likewise.
8929 (__arm_vrmlaldavhq_p_s32): Likewise.
8930 (__arm_vrmlaldavhxq_p_s32): Likewise.
8931 (__arm_vrmlsldavhq_p_s32): Likewise.
8932 (__arm_vrmlsldavhxq_p_s32): Likewise.
8933 (__arm_vaddlvaq_p_u32): Likewise.
8934 (__arm_vrev16q_m_u8): Likewise.
8935 (__arm_vrmlaldavhq_p_u32): Likewise.
8936 (__arm_vmvnq_m_n_s16): Likewise.
8937 (__arm_vorrq_m_n_s16): Likewise.
8938 (__arm_vqrshrntq_n_s16): Likewise.
8939 (__arm_vqshrnbq_n_s16): Likewise.
8940 (__arm_vqshrntq_n_s16): Likewise.
8941 (__arm_vrshrnbq_n_s16): Likewise.
8942 (__arm_vrshrntq_n_s16): Likewise.
8943 (__arm_vshrnbq_n_s16): Likewise.
8944 (__arm_vshrntq_n_s16): Likewise.
8945 (__arm_vmlaldavaq_s16): Likewise.
8946 (__arm_vmlaldavaxq_s16): Likewise.
8947 (__arm_vmlsldavaq_s16): Likewise.
8948 (__arm_vmlsldavaxq_s16): Likewise.
8949 (__arm_vmlaldavq_p_s16): Likewise.
8950 (__arm_vmlaldavxq_p_s16): Likewise.
8951 (__arm_vmlsldavq_p_s16): Likewise.
8952 (__arm_vmlsldavxq_p_s16): Likewise.
8953 (__arm_vmovlbq_m_s8): Likewise.
8954 (__arm_vmovltq_m_s8): Likewise.
8955 (__arm_vmovnbq_m_s16): Likewise.
8956 (__arm_vmovntq_m_s16): Likewise.
8957 (__arm_vqmovnbq_m_s16): Likewise.
8958 (__arm_vqmovntq_m_s16): Likewise.
8959 (__arm_vrev32q_m_s8): Likewise.
8960 (__arm_vmvnq_m_n_u16): Likewise.
8961 (__arm_vorrq_m_n_u16): Likewise.
8962 (__arm_vqrshruntq_n_s16): Likewise.
8963 (__arm_vqshrunbq_n_s16): Likewise.
8964 (__arm_vqshruntq_n_s16): Likewise.
8965 (__arm_vqmovunbq_m_s16): Likewise.
8966 (__arm_vqmovuntq_m_s16): Likewise.
8967 (__arm_vqrshrntq_n_u16): Likewise.
8968 (__arm_vqshrnbq_n_u16): Likewise.
8969 (__arm_vqshrntq_n_u16): Likewise.
8970 (__arm_vrshrnbq_n_u16): Likewise.
8971 (__arm_vrshrntq_n_u16): Likewise.
8972 (__arm_vshrnbq_n_u16): Likewise.
8973 (__arm_vshrntq_n_u16): Likewise.
8974 (__arm_vmlaldavaq_u16): Likewise.
8975 (__arm_vmlaldavaxq_u16): Likewise.
8976 (__arm_vmlaldavq_p_u16): Likewise.
8977 (__arm_vmlaldavxq_p_u16): Likewise.
8978 (__arm_vmovlbq_m_u8): Likewise.
8979 (__arm_vmovltq_m_u8): Likewise.
8980 (__arm_vmovnbq_m_u16): Likewise.
8981 (__arm_vmovntq_m_u16): Likewise.
8982 (__arm_vqmovnbq_m_u16): Likewise.
8983 (__arm_vqmovntq_m_u16): Likewise.
8984 (__arm_vrev32q_m_u8): Likewise.
8985 (__arm_vmvnq_m_n_s32): Likewise.
8986 (__arm_vorrq_m_n_s32): Likewise.
8987 (__arm_vqrshrntq_n_s32): Likewise.
8988 (__arm_vqshrnbq_n_s32): Likewise.
8989 (__arm_vqshrntq_n_s32): Likewise.
8990 (__arm_vrshrnbq_n_s32): Likewise.
8991 (__arm_vrshrntq_n_s32): Likewise.
8992 (__arm_vshrnbq_n_s32): Likewise.
8993 (__arm_vshrntq_n_s32): Likewise.
8994 (__arm_vmlaldavaq_s32): Likewise.
8995 (__arm_vmlaldavaxq_s32): Likewise.
8996 (__arm_vmlsldavaq_s32): Likewise.
8997 (__arm_vmlsldavaxq_s32): Likewise.
8998 (__arm_vmlaldavq_p_s32): Likewise.
8999 (__arm_vmlaldavxq_p_s32): Likewise.
9000 (__arm_vmlsldavq_p_s32): Likewise.
9001 (__arm_vmlsldavxq_p_s32): Likewise.
9002 (__arm_vmovlbq_m_s16): Likewise.
9003 (__arm_vmovltq_m_s16): Likewise.
9004 (__arm_vmovnbq_m_s32): Likewise.
9005 (__arm_vmovntq_m_s32): Likewise.
9006 (__arm_vqmovnbq_m_s32): Likewise.
9007 (__arm_vqmovntq_m_s32): Likewise.
9008 (__arm_vrev32q_m_s16): Likewise.
9009 (__arm_vmvnq_m_n_u32): Likewise.
9010 (__arm_vorrq_m_n_u32): Likewise.
9011 (__arm_vqrshruntq_n_s32): Likewise.
9012 (__arm_vqshrunbq_n_s32): Likewise.
9013 (__arm_vqshruntq_n_s32): Likewise.
9014 (__arm_vqmovunbq_m_s32): Likewise.
9015 (__arm_vqmovuntq_m_s32): Likewise.
9016 (__arm_vqrshrntq_n_u32): Likewise.
9017 (__arm_vqshrnbq_n_u32): Likewise.
9018 (__arm_vqshrntq_n_u32): Likewise.
9019 (__arm_vrshrnbq_n_u32): Likewise.
9020 (__arm_vrshrntq_n_u32): Likewise.
9021 (__arm_vshrnbq_n_u32): Likewise.
9022 (__arm_vshrntq_n_u32): Likewise.
9023 (__arm_vmlaldavaq_u32): Likewise.
9024 (__arm_vmlaldavaxq_u32): Likewise.
9025 (__arm_vmlaldavq_p_u32): Likewise.
9026 (__arm_vmlaldavxq_p_u32): Likewise.
9027 (__arm_vmovlbq_m_u16): Likewise.
9028 (__arm_vmovltq_m_u16): Likewise.
9029 (__arm_vmovnbq_m_u32): Likewise.
9030 (__arm_vmovntq_m_u32): Likewise.
9031 (__arm_vqmovnbq_m_u32): Likewise.
9032 (__arm_vqmovntq_m_u32): Likewise.
9033 (__arm_vrev32q_m_u16): Likewise.
9034 (__arm_vcvtbq_m_f16_f32): Likewise.
9035 (__arm_vcvtbq_m_f32_f16): Likewise.
9036 (__arm_vcvttq_m_f16_f32): Likewise.
9037 (__arm_vcvttq_m_f32_f16): Likewise.
9038 (__arm_vrev32q_m_f16): Likewise.
9039 (__arm_vcmlaq_f16): Likewise.
9040 (__arm_vcmlaq_rot180_f16): Likewise.
9041 (__arm_vcmlaq_rot270_f16): Likewise.
9042 (__arm_vcmlaq_rot90_f16): Likewise.
9043 (__arm_vfmaq_f16): Likewise.
9044 (__arm_vfmaq_n_f16): Likewise.
9045 (__arm_vfmasq_n_f16): Likewise.
9046 (__arm_vfmsq_f16): Likewise.
9047 (__arm_vabsq_m_f16): Likewise.
9048 (__arm_vcvtmq_m_s16_f16): Likewise.
9049 (__arm_vcvtnq_m_s16_f16): Likewise.
9050 (__arm_vcvtpq_m_s16_f16): Likewise.
9051 (__arm_vcvtq_m_s16_f16): Likewise.
9052 (__arm_vdupq_m_n_f16): Likewise.
9053 (__arm_vmaxnmaq_m_f16): Likewise.
9054 (__arm_vmaxnmavq_p_f16): Likewise.
9055 (__arm_vmaxnmvq_p_f16): Likewise.
9056 (__arm_vminnmaq_m_f16): Likewise.
9057 (__arm_vminnmavq_p_f16): Likewise.
9058 (__arm_vminnmvq_p_f16): Likewise.
9059 (__arm_vnegq_m_f16): Likewise.
9060 (__arm_vpselq_f16): Likewise.
9061 (__arm_vrev64q_m_f16): Likewise.
9062 (__arm_vrndaq_m_f16): Likewise.
9063 (__arm_vrndmq_m_f16): Likewise.
9064 (__arm_vrndnq_m_f16): Likewise.
9065 (__arm_vrndpq_m_f16): Likewise.
9066 (__arm_vrndq_m_f16): Likewise.
9067 (__arm_vrndxq_m_f16): Likewise.
9068 (__arm_vcmpeqq_m_n_f16): Likewise.
9069 (__arm_vcmpgeq_m_f16): Likewise.
9070 (__arm_vcmpgeq_m_n_f16): Likewise.
9071 (__arm_vcmpgtq_m_f16): Likewise.
9072 (__arm_vcmpgtq_m_n_f16): Likewise.
9073 (__arm_vcmpleq_m_f16): Likewise.
9074 (__arm_vcmpleq_m_n_f16): Likewise.
9075 (__arm_vcmpltq_m_f16): Likewise.
9076 (__arm_vcmpltq_m_n_f16): Likewise.
9077 (__arm_vcmpneq_m_f16): Likewise.
9078 (__arm_vcmpneq_m_n_f16): Likewise.
9079 (__arm_vcvtmq_m_u16_f16): Likewise.
9080 (__arm_vcvtnq_m_u16_f16): Likewise.
9081 (__arm_vcvtpq_m_u16_f16): Likewise.
9082 (__arm_vcvtq_m_u16_f16): Likewise.
9083 (__arm_vcmlaq_f32): Likewise.
9084 (__arm_vcmlaq_rot180_f32): Likewise.
9085 (__arm_vcmlaq_rot270_f32): Likewise.
9086 (__arm_vcmlaq_rot90_f32): Likewise.
9087 (__arm_vfmaq_f32): Likewise.
9088 (__arm_vfmaq_n_f32): Likewise.
9089 (__arm_vfmasq_n_f32): Likewise.
9090 (__arm_vfmsq_f32): Likewise.
9091 (__arm_vabsq_m_f32): Likewise.
9092 (__arm_vcvtmq_m_s32_f32): Likewise.
9093 (__arm_vcvtnq_m_s32_f32): Likewise.
9094 (__arm_vcvtpq_m_s32_f32): Likewise.
9095 (__arm_vcvtq_m_s32_f32): Likewise.
9096 (__arm_vdupq_m_n_f32): Likewise.
9097 (__arm_vmaxnmaq_m_f32): Likewise.
9098 (__arm_vmaxnmavq_p_f32): Likewise.
9099 (__arm_vmaxnmvq_p_f32): Likewise.
9100 (__arm_vminnmaq_m_f32): Likewise.
9101 (__arm_vminnmavq_p_f32): Likewise.
9102 (__arm_vminnmvq_p_f32): Likewise.
9103 (__arm_vnegq_m_f32): Likewise.
9104 (__arm_vpselq_f32): Likewise.
9105 (__arm_vrev64q_m_f32): Likewise.
9106 (__arm_vrndaq_m_f32): Likewise.
9107 (__arm_vrndmq_m_f32): Likewise.
9108 (__arm_vrndnq_m_f32): Likewise.
9109 (__arm_vrndpq_m_f32): Likewise.
9110 (__arm_vrndq_m_f32): Likewise.
9111 (__arm_vrndxq_m_f32): Likewise.
9112 (__arm_vcmpeqq_m_n_f32): Likewise.
9113 (__arm_vcmpgeq_m_f32): Likewise.
9114 (__arm_vcmpgeq_m_n_f32): Likewise.
9115 (__arm_vcmpgtq_m_f32): Likewise.
9116 (__arm_vcmpgtq_m_n_f32): Likewise.
9117 (__arm_vcmpleq_m_f32): Likewise.
9118 (__arm_vcmpleq_m_n_f32): Likewise.
9119 (__arm_vcmpltq_m_f32): Likewise.
9120 (__arm_vcmpltq_m_n_f32): Likewise.
9121 (__arm_vcmpneq_m_f32): Likewise.
9122 (__arm_vcmpneq_m_n_f32): Likewise.
9123 (__arm_vcvtmq_m_u32_f32): Likewise.
9124 (__arm_vcvtnq_m_u32_f32): Likewise.
9125 (__arm_vcvtpq_m_u32_f32): Likewise.
9126 (__arm_vcvtq_m_u32_f32): Likewise.
9127 (vcvtq_m): Define polymorphic variant.
9128 (vabsq_m): Likewise.
9130 (vcmlaq_rot180): Likewise.
9131 (vcmlaq_rot270): Likewise.
9132 (vcmlaq_rot90): Likewise.
9133 (vcmpeqq_m_n): Likewise.
9134 (vcmpgeq_m_n): Likewise.
9135 (vrndxq_m): Likewise.
9136 (vrndq_m): Likewise.
9137 (vrndpq_m): Likewise.
9138 (vcmpgtq_m_n): Likewise.
9139 (vcmpgtq_m): Likewise.
9140 (vcmpleq_m): Likewise.
9141 (vcmpleq_m_n): Likewise.
9142 (vcmpltq_m_n): Likewise.
9143 (vcmpltq_m): Likewise.
9144 (vcmpneq_m): Likewise.
9145 (vcmpneq_m_n): Likewise.
9146 (vcvtbq_m): Likewise.
9147 (vcvttq_m): Likewise.
9148 (vcvtmq_m): Likewise.
9149 (vcvtnq_m): Likewise.
9150 (vcvtpq_m): Likewise.
9151 (vdupq_m_n): Likewise.
9152 (vfmaq_n): Likewise.
9154 (vfmasq_n): Likewise.
9156 (vmaxnmaq_m): Likewise.
9157 (vmaxnmavq_m): Likewise.
9158 (vmaxnmvq_m): Likewise.
9159 (vmaxnmavq_p): Likewise.
9160 (vmaxnmvq_p): Likewise.
9161 (vminnmaq_m): Likewise.
9162 (vminnmavq_p): Likewise.
9163 (vminnmvq_p): Likewise.
9164 (vrndnq_m): Likewise.
9165 (vrndaq_m): Likewise.
9166 (vrndmq_m): Likewise.
9167 (vrev64q_m): Likewise.
9168 (vrev32q_m): Likewise.
9170 (vnegq_m): Likewise.
9171 (vcmpgeq_m): Likewise.
9172 (vshrntq_n): Likewise.
9173 (vrshrntq_n): Likewise.
9174 (vmovlbq_m): Likewise.
9175 (vmovnbq_m): Likewise.
9176 (vmovntq_m): Likewise.
9177 (vmvnq_m_n): Likewise.
9178 (vmvnq_m): Likewise.
9179 (vshrnbq_n): Likewise.
9180 (vrshrnbq_n): Likewise.
9181 (vqshruntq_n): Likewise.
9182 (vrev16q_m): Likewise.
9183 (vqshrunbq_n): Likewise.
9184 (vqshrntq_n): Likewise.
9185 (vqrshruntq_n): Likewise.
9186 (vqrshrntq_n): Likewise.
9187 (vqshrnbq_n): Likewise.
9188 (vqmovuntq_m): Likewise.
9189 (vqmovntq_m): Likewise.
9190 (vqmovnbq_m): Likewise.
9191 (vorrq_m_n): Likewise.
9192 (vmovltq_m): Likewise.
9193 (vqmovunbq_m): Likewise.
9194 (vaddlvaq_p): Likewise.
9195 (vmlaldavaq): Likewise.
9196 (vmlaldavaxq): Likewise.
9197 (vmlaldavq_p): Likewise.
9198 (vmlaldavxq_p): Likewise.
9199 (vmlsldavaq): Likewise.
9200 (vmlsldavaxq): Likewise.
9201 (vmlsldavq_p): Likewise.
9202 (vmlsldavxq_p): Likewise.
9203 (vrmlaldavhaxq): Likewise.
9204 (vrmlaldavhq_p): Likewise.
9205 (vrmlaldavhxq_p): Likewise.
9206 (vrmlsldavhaq): Likewise.
9207 (vrmlsldavhaxq): Likewise.
9208 (vrmlsldavhq_p): Likewise.
9209 (vrmlsldavhxq_p): Likewise.
9210 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_IMM_UNONE): Use
9212 (TERNOP_NONE_NONE_NONE_IMM): Likewise.
9213 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
9214 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
9215 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
9216 (TERNOP_UNONE_UNONE_IMM_UNONE): Likewise.
9217 (TERNOP_UNONE_UNONE_NONE_IMM): Likewise.
9218 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
9219 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
9220 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
9221 * config/arm/mve.md (MVE_constraint3): Define mode attribute iterator.
9222 (MVE_pred3): Likewise.
9223 (MVE_constraint1): Likewise.
9224 (MVE_pred1): Likewise.
9225 (VMLALDAVQ_P): Define iterator.
9226 (VQMOVNBQ_M): Likewise.
9227 (VMOVLTQ_M): Likewise.
9228 (VMOVNBQ_M): Likewise.
9229 (VRSHRNTQ_N): Likewise.
9230 (VORRQ_M_N): Likewise.
9231 (VREV32Q_M): Likewise.
9232 (VREV16Q_M): Likewise.
9233 (VQRSHRNTQ_N): Likewise.
9234 (VMOVNTQ_M): Likewise.
9235 (VMOVLBQ_M): Likewise.
9236 (VMLALDAVAQ): Likewise.
9237 (VQSHRNBQ_N): Likewise.
9238 (VSHRNBQ_N): Likewise.
9239 (VRSHRNBQ_N): Likewise.
9240 (VMLALDAVXQ_P): Likewise.
9241 (VQMOVNTQ_M): Likewise.
9242 (VMVNQ_M_N): Likewise.
9243 (VQSHRNTQ_N): Likewise.
9244 (VMLALDAVAXQ): Likewise.
9245 (VSHRNTQ_N): Likewise.
9246 (VCVTMQ_M): Likewise.
9247 (VCVTNQ_M): Likewise.
9248 (VCVTPQ_M): Likewise.
9249 (VCVTQ_M_N_FROM_F): Likewise.
9250 (VCVTQ_M_FROM_F): Likewise.
9251 (VRMLALDAVHQ_P): Likewise.
9252 (VADDLVAQ_P): Likewise.
9253 (mve_vrndq_m_f<mode>): Define RTL pattern.
9254 (mve_vabsq_m_f<mode>): Likewise.
9255 (mve_vaddlvaq_p_<supf>v4si): Likewise.
9256 (mve_vcmlaq_f<mode>): Likewise.
9257 (mve_vcmlaq_rot180_f<mode>): Likewise.
9258 (mve_vcmlaq_rot270_f<mode>): Likewise.
9259 (mve_vcmlaq_rot90_f<mode>): Likewise.
9260 (mve_vcmpeqq_m_n_f<mode>): Likewise.
9261 (mve_vcmpgeq_m_f<mode>): Likewise.
9262 (mve_vcmpgeq_m_n_f<mode>): Likewise.
9263 (mve_vcmpgtq_m_f<mode>): Likewise.
9264 (mve_vcmpgtq_m_n_f<mode>): Likewise.
9265 (mve_vcmpleq_m_f<mode>): Likewise.
9266 (mve_vcmpleq_m_n_f<mode>): Likewise.
9267 (mve_vcmpltq_m_f<mode>): Likewise.
9268 (mve_vcmpltq_m_n_f<mode>): Likewise.
9269 (mve_vcmpneq_m_f<mode>): Likewise.
9270 (mve_vcmpneq_m_n_f<mode>): Likewise.
9271 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
9272 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
9273 (mve_vcvttq_m_f16_f32v8hf): Likewise.
9274 (mve_vcvttq_m_f32_f16v4sf): Likewise.
9275 (mve_vdupq_m_n_f<mode>): Likewise.
9276 (mve_vfmaq_f<mode>): Likewise.
9277 (mve_vfmaq_n_f<mode>): Likewise.
9278 (mve_vfmasq_n_f<mode>): Likewise.
9279 (mve_vfmsq_f<mode>): Likewise.
9280 (mve_vmaxnmaq_m_f<mode>): Likewise.
9281 (mve_vmaxnmavq_p_f<mode>): Likewise.
9282 (mve_vmaxnmvq_p_f<mode>): Likewise.
9283 (mve_vminnmaq_m_f<mode>): Likewise.
9284 (mve_vminnmavq_p_f<mode>): Likewise.
9285 (mve_vminnmvq_p_f<mode>): Likewise.
9286 (mve_vmlaldavaq_<supf><mode>): Likewise.
9287 (mve_vmlaldavaxq_<supf><mode>): Likewise.
9288 (mve_vmlaldavq_p_<supf><mode>): Likewise.
9289 (mve_vmlaldavxq_p_<supf><mode>): Likewise.
9290 (mve_vmlsldavaq_s<mode>): Likewise.
9291 (mve_vmlsldavaxq_s<mode>): Likewise.
9292 (mve_vmlsldavq_p_s<mode>): Likewise.
9293 (mve_vmlsldavxq_p_s<mode>): Likewise.
9294 (mve_vmovlbq_m_<supf><mode>): Likewise.
9295 (mve_vmovltq_m_<supf><mode>): Likewise.
9296 (mve_vmovnbq_m_<supf><mode>): Likewise.
9297 (mve_vmovntq_m_<supf><mode>): Likewise.
9298 (mve_vmvnq_m_n_<supf><mode>): Likewise.
9299 (mve_vnegq_m_f<mode>): Likewise.
9300 (mve_vorrq_m_n_<supf><mode>): Likewise.
9301 (mve_vpselq_f<mode>): Likewise.
9302 (mve_vqmovnbq_m_<supf><mode>): Likewise.
9303 (mve_vqmovntq_m_<supf><mode>): Likewise.
9304 (mve_vqmovunbq_m_s<mode>): Likewise.
9305 (mve_vqmovuntq_m_s<mode>): Likewise.
9306 (mve_vqrshrntq_n_<supf><mode>): Likewise.
9307 (mve_vqrshruntq_n_s<mode>): Likewise.
9308 (mve_vqshrnbq_n_<supf><mode>): Likewise.
9309 (mve_vqshrntq_n_<supf><mode>): Likewise.
9310 (mve_vqshrunbq_n_s<mode>): Likewise.
9311 (mve_vqshruntq_n_s<mode>): Likewise.
9312 (mve_vrev32q_m_fv8hf): Likewise.
9313 (mve_vrev32q_m_<supf><mode>): Likewise.
9314 (mve_vrev64q_m_f<mode>): Likewise.
9315 (mve_vrmlaldavhaxq_sv4si): Likewise.
9316 (mve_vrmlaldavhxq_p_sv4si): Likewise.
9317 (mve_vrmlsldavhaxq_sv4si): Likewise.
9318 (mve_vrmlsldavhq_p_sv4si): Likewise.
9319 (mve_vrmlsldavhxq_p_sv4si): Likewise.
9320 (mve_vrndaq_m_f<mode>): Likewise.
9321 (mve_vrndmq_m_f<mode>): Likewise.
9322 (mve_vrndnq_m_f<mode>): Likewise.
9323 (mve_vrndpq_m_f<mode>): Likewise.
9324 (mve_vrndxq_m_f<mode>): Likewise.
9325 (mve_vrshrnbq_n_<supf><mode>): Likewise.
9326 (mve_vrshrntq_n_<supf><mode>): Likewise.
9327 (mve_vshrnbq_n_<supf><mode>): Likewise.
9328 (mve_vshrntq_n_<supf><mode>): Likewise.
9329 (mve_vcvtmq_m_<supf><mode>): Likewise.
9330 (mve_vcvtpq_m_<supf><mode>): Likewise.
9331 (mve_vcvtnq_m_<supf><mode>): Likewise.
9332 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
9333 (mve_vrev16q_m_<supf>v16qi): Likewise.
9334 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
9335 (mve_vrmlaldavhq_p_<supf>v4si): Likewise.
9336 (mve_vrmlsldavhaq_sv4si): Likewise.
9338 2020-03-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
9339 Mihail Ionescu <mihail.ionescu@arm.com>
9340 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9342 * config/arm/arm_mve.h (vpselq_u8): Define macro.
9343 (vpselq_s8): Likewise.
9344 (vrev64q_m_u8): Likewise.
9345 (vqrdmlashq_n_u8): Likewise.
9346 (vqrdmlahq_n_u8): Likewise.
9347 (vqdmlahq_n_u8): Likewise.
9348 (vmvnq_m_u8): Likewise.
9349 (vmlasq_n_u8): Likewise.
9350 (vmlaq_n_u8): Likewise.
9351 (vmladavq_p_u8): Likewise.
9352 (vmladavaq_u8): Likewise.
9353 (vminvq_p_u8): Likewise.
9354 (vmaxvq_p_u8): Likewise.
9355 (vdupq_m_n_u8): Likewise.
9356 (vcmpneq_m_u8): Likewise.
9357 (vcmpneq_m_n_u8): Likewise.
9358 (vcmphiq_m_u8): Likewise.
9359 (vcmphiq_m_n_u8): Likewise.
9360 (vcmpeqq_m_u8): Likewise.
9361 (vcmpeqq_m_n_u8): Likewise.
9362 (vcmpcsq_m_u8): Likewise.
9363 (vcmpcsq_m_n_u8): Likewise.
9364 (vclzq_m_u8): Likewise.
9365 (vaddvaq_p_u8): Likewise.
9366 (vsriq_n_u8): Likewise.
9367 (vsliq_n_u8): Likewise.
9368 (vshlq_m_r_u8): Likewise.
9369 (vrshlq_m_n_u8): Likewise.
9370 (vqshlq_m_r_u8): Likewise.
9371 (vqrshlq_m_n_u8): Likewise.
9372 (vminavq_p_s8): Likewise.
9373 (vminaq_m_s8): Likewise.
9374 (vmaxavq_p_s8): Likewise.
9375 (vmaxaq_m_s8): Likewise.
9376 (vcmpneq_m_s8): Likewise.
9377 (vcmpneq_m_n_s8): Likewise.
9378 (vcmpltq_m_s8): Likewise.
9379 (vcmpltq_m_n_s8): Likewise.
9380 (vcmpleq_m_s8): Likewise.
9381 (vcmpleq_m_n_s8): Likewise.
9382 (vcmpgtq_m_s8): Likewise.
9383 (vcmpgtq_m_n_s8): Likewise.
9384 (vcmpgeq_m_s8): Likewise.
9385 (vcmpgeq_m_n_s8): Likewise.
9386 (vcmpeqq_m_s8): Likewise.
9387 (vcmpeqq_m_n_s8): Likewise.
9388 (vshlq_m_r_s8): Likewise.
9389 (vrshlq_m_n_s8): Likewise.
9390 (vrev64q_m_s8): Likewise.
9391 (vqshlq_m_r_s8): Likewise.
9392 (vqrshlq_m_n_s8): Likewise.
9393 (vqnegq_m_s8): Likewise.
9394 (vqabsq_m_s8): Likewise.
9395 (vnegq_m_s8): Likewise.
9396 (vmvnq_m_s8): Likewise.
9397 (vmlsdavxq_p_s8): Likewise.
9398 (vmlsdavq_p_s8): Likewise.
9399 (vmladavxq_p_s8): Likewise.
9400 (vmladavq_p_s8): Likewise.
9401 (vminvq_p_s8): Likewise.
9402 (vmaxvq_p_s8): Likewise.
9403 (vdupq_m_n_s8): Likewise.
9404 (vclzq_m_s8): Likewise.
9405 (vclsq_m_s8): Likewise.
9406 (vaddvaq_p_s8): Likewise.
9407 (vabsq_m_s8): Likewise.
9408 (vqrdmlsdhxq_s8): Likewise.
9409 (vqrdmlsdhq_s8): Likewise.
9410 (vqrdmlashq_n_s8): Likewise.
9411 (vqrdmlahq_n_s8): Likewise.
9412 (vqrdmladhxq_s8): Likewise.
9413 (vqrdmladhq_s8): Likewise.
9414 (vqdmlsdhxq_s8): Likewise.
9415 (vqdmlsdhq_s8): Likewise.
9416 (vqdmlahq_n_s8): Likewise.
9417 (vqdmladhxq_s8): Likewise.
9418 (vqdmladhq_s8): Likewise.
9419 (vmlsdavaxq_s8): Likewise.
9420 (vmlsdavaq_s8): Likewise.
9421 (vmlasq_n_s8): Likewise.
9422 (vmlaq_n_s8): Likewise.
9423 (vmladavaxq_s8): Likewise.
9424 (vmladavaq_s8): Likewise.
9425 (vsriq_n_s8): Likewise.
9426 (vsliq_n_s8): Likewise.
9427 (vpselq_u16): Likewise.
9428 (vpselq_s16): Likewise.
9429 (vrev64q_m_u16): Likewise.
9430 (vqrdmlashq_n_u16): Likewise.
9431 (vqrdmlahq_n_u16): Likewise.
9432 (vqdmlahq_n_u16): Likewise.
9433 (vmvnq_m_u16): Likewise.
9434 (vmlasq_n_u16): Likewise.
9435 (vmlaq_n_u16): Likewise.
9436 (vmladavq_p_u16): Likewise.
9437 (vmladavaq_u16): Likewise.
9438 (vminvq_p_u16): Likewise.
9439 (vmaxvq_p_u16): Likewise.
9440 (vdupq_m_n_u16): Likewise.
9441 (vcmpneq_m_u16): Likewise.
9442 (vcmpneq_m_n_u16): Likewise.
9443 (vcmphiq_m_u16): Likewise.
9444 (vcmphiq_m_n_u16): Likewise.
9445 (vcmpeqq_m_u16): Likewise.
9446 (vcmpeqq_m_n_u16): Likewise.
9447 (vcmpcsq_m_u16): Likewise.
9448 (vcmpcsq_m_n_u16): Likewise.
9449 (vclzq_m_u16): Likewise.
9450 (vaddvaq_p_u16): Likewise.
9451 (vsriq_n_u16): Likewise.
9452 (vsliq_n_u16): Likewise.
9453 (vshlq_m_r_u16): Likewise.
9454 (vrshlq_m_n_u16): Likewise.
9455 (vqshlq_m_r_u16): Likewise.
9456 (vqrshlq_m_n_u16): Likewise.
9457 (vminavq_p_s16): Likewise.
9458 (vminaq_m_s16): Likewise.
9459 (vmaxavq_p_s16): Likewise.
9460 (vmaxaq_m_s16): Likewise.
9461 (vcmpneq_m_s16): Likewise.
9462 (vcmpneq_m_n_s16): Likewise.
9463 (vcmpltq_m_s16): Likewise.
9464 (vcmpltq_m_n_s16): Likewise.
9465 (vcmpleq_m_s16): Likewise.
9466 (vcmpleq_m_n_s16): Likewise.
9467 (vcmpgtq_m_s16): Likewise.
9468 (vcmpgtq_m_n_s16): Likewise.
9469 (vcmpgeq_m_s16): Likewise.
9470 (vcmpgeq_m_n_s16): Likewise.
9471 (vcmpeqq_m_s16): Likewise.
9472 (vcmpeqq_m_n_s16): Likewise.
9473 (vshlq_m_r_s16): Likewise.
9474 (vrshlq_m_n_s16): Likewise.
9475 (vrev64q_m_s16): Likewise.
9476 (vqshlq_m_r_s16): Likewise.
9477 (vqrshlq_m_n_s16): Likewise.
9478 (vqnegq_m_s16): Likewise.
9479 (vqabsq_m_s16): Likewise.
9480 (vnegq_m_s16): Likewise.
9481 (vmvnq_m_s16): Likewise.
9482 (vmlsdavxq_p_s16): Likewise.
9483 (vmlsdavq_p_s16): Likewise.
9484 (vmladavxq_p_s16): Likewise.
9485 (vmladavq_p_s16): Likewise.
9486 (vminvq_p_s16): Likewise.
9487 (vmaxvq_p_s16): Likewise.
9488 (vdupq_m_n_s16): Likewise.
9489 (vclzq_m_s16): Likewise.
9490 (vclsq_m_s16): Likewise.
9491 (vaddvaq_p_s16): Likewise.
9492 (vabsq_m_s16): Likewise.
9493 (vqrdmlsdhxq_s16): Likewise.
9494 (vqrdmlsdhq_s16): Likewise.
9495 (vqrdmlashq_n_s16): Likewise.
9496 (vqrdmlahq_n_s16): Likewise.
9497 (vqrdmladhxq_s16): Likewise.
9498 (vqrdmladhq_s16): Likewise.
9499 (vqdmlsdhxq_s16): Likewise.
9500 (vqdmlsdhq_s16): Likewise.
9501 (vqdmlahq_n_s16): Likewise.
9502 (vqdmladhxq_s16): Likewise.
9503 (vqdmladhq_s16): Likewise.
9504 (vmlsdavaxq_s16): Likewise.
9505 (vmlsdavaq_s16): Likewise.
9506 (vmlasq_n_s16): Likewise.
9507 (vmlaq_n_s16): Likewise.
9508 (vmladavaxq_s16): Likewise.
9509 (vmladavaq_s16): Likewise.
9510 (vsriq_n_s16): Likewise.
9511 (vsliq_n_s16): Likewise.
9512 (vpselq_u32): Likewise.
9513 (vpselq_s32): Likewise.
9514 (vrev64q_m_u32): Likewise.
9515 (vqrdmlashq_n_u32): Likewise.
9516 (vqrdmlahq_n_u32): Likewise.
9517 (vqdmlahq_n_u32): Likewise.
9518 (vmvnq_m_u32): Likewise.
9519 (vmlasq_n_u32): Likewise.
9520 (vmlaq_n_u32): Likewise.
9521 (vmladavq_p_u32): Likewise.
9522 (vmladavaq_u32): Likewise.
9523 (vminvq_p_u32): Likewise.
9524 (vmaxvq_p_u32): Likewise.
9525 (vdupq_m_n_u32): Likewise.
9526 (vcmpneq_m_u32): Likewise.
9527 (vcmpneq_m_n_u32): Likewise.
9528 (vcmphiq_m_u32): Likewise.
9529 (vcmphiq_m_n_u32): Likewise.
9530 (vcmpeqq_m_u32): Likewise.
9531 (vcmpeqq_m_n_u32): Likewise.
9532 (vcmpcsq_m_u32): Likewise.
9533 (vcmpcsq_m_n_u32): Likewise.
9534 (vclzq_m_u32): Likewise.
9535 (vaddvaq_p_u32): Likewise.
9536 (vsriq_n_u32): Likewise.
9537 (vsliq_n_u32): Likewise.
9538 (vshlq_m_r_u32): Likewise.
9539 (vrshlq_m_n_u32): Likewise.
9540 (vqshlq_m_r_u32): Likewise.
9541 (vqrshlq_m_n_u32): Likewise.
9542 (vminavq_p_s32): Likewise.
9543 (vminaq_m_s32): Likewise.
9544 (vmaxavq_p_s32): Likewise.
9545 (vmaxaq_m_s32): Likewise.
9546 (vcmpneq_m_s32): Likewise.
9547 (vcmpneq_m_n_s32): Likewise.
9548 (vcmpltq_m_s32): Likewise.
9549 (vcmpltq_m_n_s32): Likewise.
9550 (vcmpleq_m_s32): Likewise.
9551 (vcmpleq_m_n_s32): Likewise.
9552 (vcmpgtq_m_s32): Likewise.
9553 (vcmpgtq_m_n_s32): Likewise.
9554 (vcmpgeq_m_s32): Likewise.
9555 (vcmpgeq_m_n_s32): Likewise.
9556 (vcmpeqq_m_s32): Likewise.
9557 (vcmpeqq_m_n_s32): Likewise.
9558 (vshlq_m_r_s32): Likewise.
9559 (vrshlq_m_n_s32): Likewise.
9560 (vrev64q_m_s32): Likewise.
9561 (vqshlq_m_r_s32): Likewise.
9562 (vqrshlq_m_n_s32): Likewise.
9563 (vqnegq_m_s32): Likewise.
9564 (vqabsq_m_s32): Likewise.
9565 (vnegq_m_s32): Likewise.
9566 (vmvnq_m_s32): Likewise.
9567 (vmlsdavxq_p_s32): Likewise.
9568 (vmlsdavq_p_s32): Likewise.
9569 (vmladavxq_p_s32): Likewise.
9570 (vmladavq_p_s32): Likewise.
9571 (vminvq_p_s32): Likewise.
9572 (vmaxvq_p_s32): Likewise.
9573 (vdupq_m_n_s32): Likewise.
9574 (vclzq_m_s32): Likewise.
9575 (vclsq_m_s32): Likewise.
9576 (vaddvaq_p_s32): Likewise.
9577 (vabsq_m_s32): Likewise.
9578 (vqrdmlsdhxq_s32): Likewise.
9579 (vqrdmlsdhq_s32): Likewise.
9580 (vqrdmlashq_n_s32): Likewise.
9581 (vqrdmlahq_n_s32): Likewise.
9582 (vqrdmladhxq_s32): Likewise.
9583 (vqrdmladhq_s32): Likewise.
9584 (vqdmlsdhxq_s32): Likewise.
9585 (vqdmlsdhq_s32): Likewise.
9586 (vqdmlahq_n_s32): Likewise.
9587 (vqdmladhxq_s32): Likewise.
9588 (vqdmladhq_s32): Likewise.
9589 (vmlsdavaxq_s32): Likewise.
9590 (vmlsdavaq_s32): Likewise.
9591 (vmlasq_n_s32): Likewise.
9592 (vmlaq_n_s32): Likewise.
9593 (vmladavaxq_s32): Likewise.
9594 (vmladavaq_s32): Likewise.
9595 (vsriq_n_s32): Likewise.
9596 (vsliq_n_s32): Likewise.
9597 (vpselq_u64): Likewise.
9598 (vpselq_s64): Likewise.
9599 (__arm_vpselq_u8): Define intrinsic.
9600 (__arm_vpselq_s8): Likewise.
9601 (__arm_vrev64q_m_u8): Likewise.
9602 (__arm_vqrdmlashq_n_u8): Likewise.
9603 (__arm_vqrdmlahq_n_u8): Likewise.
9604 (__arm_vqdmlahq_n_u8): Likewise.
9605 (__arm_vmvnq_m_u8): Likewise.
9606 (__arm_vmlasq_n_u8): Likewise.
9607 (__arm_vmlaq_n_u8): Likewise.
9608 (__arm_vmladavq_p_u8): Likewise.
9609 (__arm_vmladavaq_u8): Likewise.
9610 (__arm_vminvq_p_u8): Likewise.
9611 (__arm_vmaxvq_p_u8): Likewise.
9612 (__arm_vdupq_m_n_u8): Likewise.
9613 (__arm_vcmpneq_m_u8): Likewise.
9614 (__arm_vcmpneq_m_n_u8): Likewise.
9615 (__arm_vcmphiq_m_u8): Likewise.
9616 (__arm_vcmphiq_m_n_u8): Likewise.
9617 (__arm_vcmpeqq_m_u8): Likewise.
9618 (__arm_vcmpeqq_m_n_u8): Likewise.
9619 (__arm_vcmpcsq_m_u8): Likewise.
9620 (__arm_vcmpcsq_m_n_u8): Likewise.
9621 (__arm_vclzq_m_u8): Likewise.
9622 (__arm_vaddvaq_p_u8): Likewise.
9623 (__arm_vsriq_n_u8): Likewise.
9624 (__arm_vsliq_n_u8): Likewise.
9625 (__arm_vshlq_m_r_u8): Likewise.
9626 (__arm_vrshlq_m_n_u8): Likewise.
9627 (__arm_vqshlq_m_r_u8): Likewise.
9628 (__arm_vqrshlq_m_n_u8): Likewise.
9629 (__arm_vminavq_p_s8): Likewise.
9630 (__arm_vminaq_m_s8): Likewise.
9631 (__arm_vmaxavq_p_s8): Likewise.
9632 (__arm_vmaxaq_m_s8): Likewise.
9633 (__arm_vcmpneq_m_s8): Likewise.
9634 (__arm_vcmpneq_m_n_s8): Likewise.
9635 (__arm_vcmpltq_m_s8): Likewise.
9636 (__arm_vcmpltq_m_n_s8): Likewise.
9637 (__arm_vcmpleq_m_s8): Likewise.
9638 (__arm_vcmpleq_m_n_s8): Likewise.
9639 (__arm_vcmpgtq_m_s8): Likewise.
9640 (__arm_vcmpgtq_m_n_s8): Likewise.
9641 (__arm_vcmpgeq_m_s8): Likewise.
9642 (__arm_vcmpgeq_m_n_s8): Likewise.
9643 (__arm_vcmpeqq_m_s8): Likewise.
9644 (__arm_vcmpeqq_m_n_s8): Likewise.
9645 (__arm_vshlq_m_r_s8): Likewise.
9646 (__arm_vrshlq_m_n_s8): Likewise.
9647 (__arm_vrev64q_m_s8): Likewise.
9648 (__arm_vqshlq_m_r_s8): Likewise.
9649 (__arm_vqrshlq_m_n_s8): Likewise.
9650 (__arm_vqnegq_m_s8): Likewise.
9651 (__arm_vqabsq_m_s8): Likewise.
9652 (__arm_vnegq_m_s8): Likewise.
9653 (__arm_vmvnq_m_s8): Likewise.
9654 (__arm_vmlsdavxq_p_s8): Likewise.
9655 (__arm_vmlsdavq_p_s8): Likewise.
9656 (__arm_vmladavxq_p_s8): Likewise.
9657 (__arm_vmladavq_p_s8): Likewise.
9658 (__arm_vminvq_p_s8): Likewise.
9659 (__arm_vmaxvq_p_s8): Likewise.
9660 (__arm_vdupq_m_n_s8): Likewise.
9661 (__arm_vclzq_m_s8): Likewise.
9662 (__arm_vclsq_m_s8): Likewise.
9663 (__arm_vaddvaq_p_s8): Likewise.
9664 (__arm_vabsq_m_s8): Likewise.
9665 (__arm_vqrdmlsdhxq_s8): Likewise.
9666 (__arm_vqrdmlsdhq_s8): Likewise.
9667 (__arm_vqrdmlashq_n_s8): Likewise.
9668 (__arm_vqrdmlahq_n_s8): Likewise.
9669 (__arm_vqrdmladhxq_s8): Likewise.
9670 (__arm_vqrdmladhq_s8): Likewise.
9671 (__arm_vqdmlsdhxq_s8): Likewise.
9672 (__arm_vqdmlsdhq_s8): Likewise.
9673 (__arm_vqdmlahq_n_s8): Likewise.
9674 (__arm_vqdmladhxq_s8): Likewise.
9675 (__arm_vqdmladhq_s8): Likewise.
9676 (__arm_vmlsdavaxq_s8): Likewise.
9677 (__arm_vmlsdavaq_s8): Likewise.
9678 (__arm_vmlasq_n_s8): Likewise.
9679 (__arm_vmlaq_n_s8): Likewise.
9680 (__arm_vmladavaxq_s8): Likewise.
9681 (__arm_vmladavaq_s8): Likewise.
9682 (__arm_vsriq_n_s8): Likewise.
9683 (__arm_vsliq_n_s8): Likewise.
9684 (__arm_vpselq_u16): Likewise.
9685 (__arm_vpselq_s16): Likewise.
9686 (__arm_vrev64q_m_u16): Likewise.
9687 (__arm_vqrdmlashq_n_u16): Likewise.
9688 (__arm_vqrdmlahq_n_u16): Likewise.
9689 (__arm_vqdmlahq_n_u16): Likewise.
9690 (__arm_vmvnq_m_u16): Likewise.
9691 (__arm_vmlasq_n_u16): Likewise.
9692 (__arm_vmlaq_n_u16): Likewise.
9693 (__arm_vmladavq_p_u16): Likewise.
9694 (__arm_vmladavaq_u16): Likewise.
9695 (__arm_vminvq_p_u16): Likewise.
9696 (__arm_vmaxvq_p_u16): Likewise.
9697 (__arm_vdupq_m_n_u16): Likewise.
9698 (__arm_vcmpneq_m_u16): Likewise.
9699 (__arm_vcmpneq_m_n_u16): Likewise.
9700 (__arm_vcmphiq_m_u16): Likewise.
9701 (__arm_vcmphiq_m_n_u16): Likewise.
9702 (__arm_vcmpeqq_m_u16): Likewise.
9703 (__arm_vcmpeqq_m_n_u16): Likewise.
9704 (__arm_vcmpcsq_m_u16): Likewise.
9705 (__arm_vcmpcsq_m_n_u16): Likewise.
9706 (__arm_vclzq_m_u16): Likewise.
9707 (__arm_vaddvaq_p_u16): Likewise.
9708 (__arm_vsriq_n_u16): Likewise.
9709 (__arm_vsliq_n_u16): Likewise.
9710 (__arm_vshlq_m_r_u16): Likewise.
9711 (__arm_vrshlq_m_n_u16): Likewise.
9712 (__arm_vqshlq_m_r_u16): Likewise.
9713 (__arm_vqrshlq_m_n_u16): Likewise.
9714 (__arm_vminavq_p_s16): Likewise.
9715 (__arm_vminaq_m_s16): Likewise.
9716 (__arm_vmaxavq_p_s16): Likewise.
9717 (__arm_vmaxaq_m_s16): Likewise.
9718 (__arm_vcmpneq_m_s16): Likewise.
9719 (__arm_vcmpneq_m_n_s16): Likewise.
9720 (__arm_vcmpltq_m_s16): Likewise.
9721 (__arm_vcmpltq_m_n_s16): Likewise.
9722 (__arm_vcmpleq_m_s16): Likewise.
9723 (__arm_vcmpleq_m_n_s16): Likewise.
9724 (__arm_vcmpgtq_m_s16): Likewise.
9725 (__arm_vcmpgtq_m_n_s16): Likewise.
9726 (__arm_vcmpgeq_m_s16): Likewise.
9727 (__arm_vcmpgeq_m_n_s16): Likewise.
9728 (__arm_vcmpeqq_m_s16): Likewise.
9729 (__arm_vcmpeqq_m_n_s16): Likewise.
9730 (__arm_vshlq_m_r_s16): Likewise.
9731 (__arm_vrshlq_m_n_s16): Likewise.
9732 (__arm_vrev64q_m_s16): Likewise.
9733 (__arm_vqshlq_m_r_s16): Likewise.
9734 (__arm_vqrshlq_m_n_s16): Likewise.
9735 (__arm_vqnegq_m_s16): Likewise.
9736 (__arm_vqabsq_m_s16): Likewise.
9737 (__arm_vnegq_m_s16): Likewise.
9738 (__arm_vmvnq_m_s16): Likewise.
9739 (__arm_vmlsdavxq_p_s16): Likewise.
9740 (__arm_vmlsdavq_p_s16): Likewise.
9741 (__arm_vmladavxq_p_s16): Likewise.
9742 (__arm_vmladavq_p_s16): Likewise.
9743 (__arm_vminvq_p_s16): Likewise.
9744 (__arm_vmaxvq_p_s16): Likewise.
9745 (__arm_vdupq_m_n_s16): Likewise.
9746 (__arm_vclzq_m_s16): Likewise.
9747 (__arm_vclsq_m_s16): Likewise.
9748 (__arm_vaddvaq_p_s16): Likewise.
9749 (__arm_vabsq_m_s16): Likewise.
9750 (__arm_vqrdmlsdhxq_s16): Likewise.
9751 (__arm_vqrdmlsdhq_s16): Likewise.
9752 (__arm_vqrdmlashq_n_s16): Likewise.
9753 (__arm_vqrdmlahq_n_s16): Likewise.
9754 (__arm_vqrdmladhxq_s16): Likewise.
9755 (__arm_vqrdmladhq_s16): Likewise.
9756 (__arm_vqdmlsdhxq_s16): Likewise.
9757 (__arm_vqdmlsdhq_s16): Likewise.
9758 (__arm_vqdmlahq_n_s16): Likewise.
9759 (__arm_vqdmladhxq_s16): Likewise.
9760 (__arm_vqdmladhq_s16): Likewise.
9761 (__arm_vmlsdavaxq_s16): Likewise.
9762 (__arm_vmlsdavaq_s16): Likewise.
9763 (__arm_vmlasq_n_s16): Likewise.
9764 (__arm_vmlaq_n_s16): Likewise.
9765 (__arm_vmladavaxq_s16): Likewise.
9766 (__arm_vmladavaq_s16): Likewise.
9767 (__arm_vsriq_n_s16): Likewise.
9768 (__arm_vsliq_n_s16): Likewise.
9769 (__arm_vpselq_u32): Likewise.
9770 (__arm_vpselq_s32): Likewise.
9771 (__arm_vrev64q_m_u32): Likewise.
9772 (__arm_vqrdmlashq_n_u32): Likewise.
9773 (__arm_vqrdmlahq_n_u32): Likewise.
9774 (__arm_vqdmlahq_n_u32): Likewise.
9775 (__arm_vmvnq_m_u32): Likewise.
9776 (__arm_vmlasq_n_u32): Likewise.
9777 (__arm_vmlaq_n_u32): Likewise.
9778 (__arm_vmladavq_p_u32): Likewise.
9779 (__arm_vmladavaq_u32): Likewise.
9780 (__arm_vminvq_p_u32): Likewise.
9781 (__arm_vmaxvq_p_u32): Likewise.
9782 (__arm_vdupq_m_n_u32): Likewise.
9783 (__arm_vcmpneq_m_u32): Likewise.
9784 (__arm_vcmpneq_m_n_u32): Likewise.
9785 (__arm_vcmphiq_m_u32): Likewise.
9786 (__arm_vcmphiq_m_n_u32): Likewise.
9787 (__arm_vcmpeqq_m_u32): Likewise.
9788 (__arm_vcmpeqq_m_n_u32): Likewise.
9789 (__arm_vcmpcsq_m_u32): Likewise.
9790 (__arm_vcmpcsq_m_n_u32): Likewise.
9791 (__arm_vclzq_m_u32): Likewise.
9792 (__arm_vaddvaq_p_u32): Likewise.
9793 (__arm_vsriq_n_u32): Likewise.
9794 (__arm_vsliq_n_u32): Likewise.
9795 (__arm_vshlq_m_r_u32): Likewise.
9796 (__arm_vrshlq_m_n_u32): Likewise.
9797 (__arm_vqshlq_m_r_u32): Likewise.
9798 (__arm_vqrshlq_m_n_u32): Likewise.
9799 (__arm_vminavq_p_s32): Likewise.
9800 (__arm_vminaq_m_s32): Likewise.
9801 (__arm_vmaxavq_p_s32): Likewise.
9802 (__arm_vmaxaq_m_s32): Likewise.
9803 (__arm_vcmpneq_m_s32): Likewise.
9804 (__arm_vcmpneq_m_n_s32): Likewise.
9805 (__arm_vcmpltq_m_s32): Likewise.
9806 (__arm_vcmpltq_m_n_s32): Likewise.
9807 (__arm_vcmpleq_m_s32): Likewise.
9808 (__arm_vcmpleq_m_n_s32): Likewise.
9809 (__arm_vcmpgtq_m_s32): Likewise.
9810 (__arm_vcmpgtq_m_n_s32): Likewise.
9811 (__arm_vcmpgeq_m_s32): Likewise.
9812 (__arm_vcmpgeq_m_n_s32): Likewise.
9813 (__arm_vcmpeqq_m_s32): Likewise.
9814 (__arm_vcmpeqq_m_n_s32): Likewise.
9815 (__arm_vshlq_m_r_s32): Likewise.
9816 (__arm_vrshlq_m_n_s32): Likewise.
9817 (__arm_vrev64q_m_s32): Likewise.
9818 (__arm_vqshlq_m_r_s32): Likewise.
9819 (__arm_vqrshlq_m_n_s32): Likewise.
9820 (__arm_vqnegq_m_s32): Likewise.
9821 (__arm_vqabsq_m_s32): Likewise.
9822 (__arm_vnegq_m_s32): Likewise.
9823 (__arm_vmvnq_m_s32): Likewise.
9824 (__arm_vmlsdavxq_p_s32): Likewise.
9825 (__arm_vmlsdavq_p_s32): Likewise.
9826 (__arm_vmladavxq_p_s32): Likewise.
9827 (__arm_vmladavq_p_s32): Likewise.
9828 (__arm_vminvq_p_s32): Likewise.
9829 (__arm_vmaxvq_p_s32): Likewise.
9830 (__arm_vdupq_m_n_s32): Likewise.
9831 (__arm_vclzq_m_s32): Likewise.
9832 (__arm_vclsq_m_s32): Likewise.
9833 (__arm_vaddvaq_p_s32): Likewise.
9834 (__arm_vabsq_m_s32): Likewise.
9835 (__arm_vqrdmlsdhxq_s32): Likewise.
9836 (__arm_vqrdmlsdhq_s32): Likewise.
9837 (__arm_vqrdmlashq_n_s32): Likewise.
9838 (__arm_vqrdmlahq_n_s32): Likewise.
9839 (__arm_vqrdmladhxq_s32): Likewise.
9840 (__arm_vqrdmladhq_s32): Likewise.
9841 (__arm_vqdmlsdhxq_s32): Likewise.
9842 (__arm_vqdmlsdhq_s32): Likewise.
9843 (__arm_vqdmlahq_n_s32): Likewise.
9844 (__arm_vqdmladhxq_s32): Likewise.
9845 (__arm_vqdmladhq_s32): Likewise.
9846 (__arm_vmlsdavaxq_s32): Likewise.
9847 (__arm_vmlsdavaq_s32): Likewise.
9848 (__arm_vmlasq_n_s32): Likewise.
9849 (__arm_vmlaq_n_s32): Likewise.
9850 (__arm_vmladavaxq_s32): Likewise.
9851 (__arm_vmladavaq_s32): Likewise.
9852 (__arm_vsriq_n_s32): Likewise.
9853 (__arm_vsliq_n_s32): Likewise.
9854 (__arm_vpselq_u64): Likewise.
9855 (__arm_vpselq_s64): Likewise.
9856 (vcmpneq_m_n): Define polymorphic variant.
9857 (vcmpneq_m): Likewise.
9858 (vqrdmlsdhq): Likewise.
9859 (vqrdmlsdhxq): Likewise.
9860 (vqrshlq_m_n): Likewise.
9861 (vqshlq_m_r): Likewise.
9862 (vrev64q_m): Likewise.
9863 (vrshlq_m_n): Likewise.
9864 (vshlq_m_r): Likewise.
9865 (vsliq_n): Likewise.
9866 (vsriq_n): Likewise.
9867 (vqrdmlashq_n): Likewise.
9868 (vqrdmlahq): Likewise.
9869 (vqrdmladhxq): Likewise.
9870 (vqrdmladhq): Likewise.
9871 (vqnegq_m): Likewise.
9872 (vqdmlsdhxq): Likewise.
9873 (vabsq_m): Likewise.
9874 (vclsq_m): Likewise.
9875 (vclzq_m): Likewise.
9876 (vcmpgeq_m): Likewise.
9877 (vcmpgeq_m_n): Likewise.
9878 (vdupq_m_n): Likewise.
9879 (vmaxaq_m): Likewise.
9880 (vmlaq_n): Likewise.
9881 (vmlasq_n): Likewise.
9882 (vmvnq_m): Likewise.
9883 (vnegq_m): Likewise.
9885 (vqdmlahq_n): Likewise.
9886 (vqrdmlahq_n): Likewise.
9887 (vqdmlsdhq): Likewise.
9888 (vqdmladhq): Likewise.
9889 (vqabsq_m): Likewise.
9890 (vminaq_m): Likewise.
9891 (vrmlaldavhaq): Likewise.
9892 (vmlsdavxq_p): Likewise.
9893 (vmlsdavq_p): Likewise.
9894 (vmlsdavaxq): Likewise.
9895 (vmlsdavaq): Likewise.
9896 (vaddvaq_p): Likewise.
9897 (vcmpcsq_m_n): Likewise.
9898 (vcmpcsq_m): Likewise.
9899 (vcmpeqq_m_n): Likewise.
9900 (vcmpeqq_m): Likewise.
9901 (vmladavxq_p): Likewise.
9902 (vmladavq_p): Likewise.
9903 (vmladavaxq): Likewise.
9904 (vmladavaq): Likewise.
9905 (vminvq_p): Likewise.
9906 (vminavq_p): Likewise.
9907 (vmaxvq_p): Likewise.
9908 (vmaxavq_p): Likewise.
9909 (vcmpltq_m_n): Likewise.
9910 (vcmpltq_m): Likewise.
9911 (vcmpleq_m): Likewise.
9912 (vcmpleq_m_n): Likewise.
9913 (vcmphiq_m_n): Likewise.
9914 (vcmphiq_m): Likewise.
9915 (vcmpgtq_m_n): Likewise.
9916 (vcmpgtq_m): Likewise.
9917 * config/arm/arm_mve_builtins.def (TERNOP_NONE_NONE_NONE_IMM): Use
9919 (TERNOP_NONE_NONE_NONE_NONE): Likewise.
9920 (TERNOP_NONE_NONE_NONE_UNONE): Likewise.
9921 (TERNOP_UNONE_NONE_NONE_UNONE): Likewise.
9922 (TERNOP_UNONE_UNONE_NONE_UNONE): Likewise.
9923 (TERNOP_UNONE_UNONE_UNONE_IMM): Likewise.
9924 (TERNOP_UNONE_UNONE_UNONE_UNONE): Likewise.
9925 * config/arm/constraints.md (Rc): Define constraint to check constant is
9926 in the range of 0 to 15.
9927 (Re): Define constraint to check constant is in the range of 0 to 31.
9928 * config/arm/mve.md (VADDVAQ_P): Define iterator.
9929 (VCLZQ_M): Likewise.
9930 (VCMPEQQ_M_N): Likewise.
9931 (VCMPEQQ_M): Likewise.
9932 (VCMPNEQ_M_N): Likewise.
9933 (VCMPNEQ_M): Likewise.
9934 (VDUPQ_M_N): Likewise.
9935 (VMAXVQ_P): Likewise.
9936 (VMINVQ_P): Likewise.
9937 (VMLADAVAQ): Likewise.
9938 (VMLADAVQ_P): Likewise.
9939 (VMLAQ_N): Likewise.
9940 (VMLASQ_N): Likewise.
9941 (VMVNQ_M): Likewise.
9943 (VQDMLAHQ_N): Likewise.
9944 (VQRDMLAHQ_N): Likewise.
9945 (VQRDMLASHQ_N): Likewise.
9946 (VQRSHLQ_M_N): Likewise.
9947 (VQSHLQ_M_R): Likewise.
9948 (VREV64Q_M): Likewise.
9949 (VRSHLQ_M_N): Likewise.
9950 (VSHLQ_M_R): Likewise.
9951 (VSLIQ_N): Likewise.
9952 (VSRIQ_N): Likewise.
9953 (mve_vabsq_m_s<mode>): Define RTL pattern.
9954 (mve_vaddvaq_p_<supf><mode>): Likewise.
9955 (mve_vclsq_m_s<mode>): Likewise.
9956 (mve_vclzq_m_<supf><mode>): Likewise.
9957 (mve_vcmpcsq_m_n_u<mode>): Likewise.
9958 (mve_vcmpcsq_m_u<mode>): Likewise.
9959 (mve_vcmpeqq_m_n_<supf><mode>): Likewise.
9960 (mve_vcmpeqq_m_<supf><mode>): Likewise.
9961 (mve_vcmpgeq_m_n_s<mode>): Likewise.
9962 (mve_vcmpgeq_m_s<mode>): Likewise.
9963 (mve_vcmpgtq_m_n_s<mode>): Likewise.
9964 (mve_vcmpgtq_m_s<mode>): Likewise.
9965 (mve_vcmphiq_m_n_u<mode>): Likewise.
9966 (mve_vcmphiq_m_u<mode>): Likewise.
9967 (mve_vcmpleq_m_n_s<mode>): Likewise.
9968 (mve_vcmpleq_m_s<mode>): Likewise.
9969 (mve_vcmpltq_m_n_s<mode>): Likewise.
9970 (mve_vcmpltq_m_s<mode>): Likewise.
9971 (mve_vcmpneq_m_n_<supf><mode>): Likewise.
9972 (mve_vcmpneq_m_<supf><mode>): Likewise.
9973 (mve_vdupq_m_n_<supf><mode>): Likewise.
9974 (mve_vmaxaq_m_s<mode>): Likewise.
9975 (mve_vmaxavq_p_s<mode>): Likewise.
9976 (mve_vmaxvq_p_<supf><mode>): Likewise.
9977 (mve_vminaq_m_s<mode>): Likewise.
9978 (mve_vminavq_p_s<mode>): Likewise.
9979 (mve_vminvq_p_<supf><mode>): Likewise.
9980 (mve_vmladavaq_<supf><mode>): Likewise.
9981 (mve_vmladavq_p_<supf><mode>): Likewise.
9982 (mve_vmladavxq_p_s<mode>): Likewise.
9983 (mve_vmlaq_n_<supf><mode>): Likewise.
9984 (mve_vmlasq_n_<supf><mode>): Likewise.
9985 (mve_vmlsdavq_p_s<mode>): Likewise.
9986 (mve_vmlsdavxq_p_s<mode>): Likewise.
9987 (mve_vmvnq_m_<supf><mode>): Likewise.
9988 (mve_vnegq_m_s<mode>): Likewise.
9989 (mve_vpselq_<supf><mode>): Likewise.
9990 (mve_vqabsq_m_s<mode>): Likewise.
9991 (mve_vqdmlahq_n_<supf><mode>): Likewise.
9992 (mve_vqnegq_m_s<mode>): Likewise.
9993 (mve_vqrdmladhq_s<mode>): Likewise.
9994 (mve_vqrdmladhxq_s<mode>): Likewise.
9995 (mve_vqrdmlahq_n_<supf><mode>): Likewise.
9996 (mve_vqrdmlashq_n_<supf><mode>): Likewise.
9997 (mve_vqrdmlsdhq_s<mode>): Likewise.
9998 (mve_vqrdmlsdhxq_s<mode>): Likewise.
9999 (mve_vqrshlq_m_n_<supf><mode>): Likewise.
10000 (mve_vqshlq_m_r_<supf><mode>): Likewise.
10001 (mve_vrev64q_m_<supf><mode>): Likewise.
10002 (mve_vrshlq_m_n_<supf><mode>): Likewise.
10003 (mve_vshlq_m_r_<supf><mode>): Likewise.
10004 (mve_vsliq_n_<supf><mode>): Likewise.
10005 (mve_vsriq_n_<supf><mode>): Likewise.
10006 (mve_vqdmlsdhxq_s<mode>): Likewise.
10007 (mve_vqdmlsdhq_s<mode>): Likewise.
10008 (mve_vqdmladhxq_s<mode>): Likewise.
10009 (mve_vqdmladhq_s<mode>): Likewise.
10010 (mve_vmlsdavaxq_s<mode>): Likewise.
10011 (mve_vmlsdavaq_s<mode>): Likewise.
10012 (mve_vmladavaxq_s<mode>): Likewise.
10013 * config/arm/predicates.md (mve_imm_15):Define predicate to check the
10014 matching constraint Rc.
10015 (mve_imm_31): Define predicate to check the matching constraint Re.
10017 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
10019 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Set operand 1 to DImode.
10020 (vec_cmp<mode>di_dup): Likewise.
10021 * config/gcn/gcn.h (STORE_FLAG_VALUE): Set to -1.
10023 2020-03-18 Andrew Stubbs <ams@codesourcery.com>
10025 * config/gcn/gcn-valu.md (COND_MODE): Delete.
10026 (COND_INT_MODE): Delete.
10027 (cond_op): Add "mult".
10028 (cond_<expander><mode>): Use VEC_ALLREG_MODE.
10029 (cond_<expander><mode>): Use VEC_ALLREG_INT_MODE.
10031 2020-03-18 Richard Biener <rguenther@suse.de>
10033 PR middle-end/94206
10034 * gimple-fold.c (gimple_fold_builtin_memset): Avoid using
10035 partial int modes or not mode-precision integer types for
10038 2020-03-18 Jakub Jelinek <jakub@redhat.com>
10040 * asan.c (get_mem_refs_of_builtin_call): Fix up duplicated word issue
10042 * config/arc/arc.c (frame_stack_add): Likewise.
10043 * gimple-loop-versioning.cc (loop_versioning::analyze_arbitrary_term):
10045 * ipa-predicate.c (predicate::remap_after_inlining): Likewise.
10046 * tree-ssa-strlen.h (handle_printf_call): Likewise.
10047 * tree-ssa-strlen.c (is_strlen_related_p): Likewise.
10048 * optinfo-emit-json.cc (optrecord_json_writer::add_record): Likewise.
10050 2020-03-18 Duan bo <duanbo3@huawei.com>
10053 * config/aarch64/aarch64.md (ldr_got_tiny): Delete.
10054 (@ldr_got_tiny_<mode>): New pattern.
10055 (ldr_got_tiny_sidi): Likewise.
10056 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
10057 them to handle SYMBOL_TINY_GOT for ILP32.
10059 2020-03-18 Richard Sandiford <richard.sandiford@arm.com>
10061 * config/aarch64/aarch64.c (aarch64_sve_abi): Treat p12-p15 as
10062 call-preserved for SVE PCS functions.
10063 (aarch64_layout_frame): Cope with up to 12 predicate save slots.
10064 Optimize the case in which there are no following vector save slots.
10066 2020-03-18 Richard Biener <rguenther@suse.de>
10068 PR middle-end/94188
10069 * fold-const.c (build_fold_addr_expr): Convert address to
10071 * asan.c (maybe_create_ssa_name): Strip useless type conversions.
10072 * gimple-fold.c (gimple_fold_stmt_to_constant_1): Use build1
10073 to build the ADDR_EXPR which we don't really want to simplify.
10074 * tree-ssa-dom.c (record_equivalences_from_stmt): Likewise.
10075 * tree-ssa-loop-im.c (gather_mem_refs_stmt): Likewise.
10076 * tree-ssa-forwprop.c (forward_propagate_addr_expr_1): Likewise.
10077 (simplify_builtin_call): Strip useless type conversions.
10078 * tree-ssa-strlen.c (new_strinfo): Likewise.
10080 2020-03-17 Alexey Neyman <stilor@att.net>
10083 * dwarf2out.c (gen_decl_die): Proceed to generating the DIE if
10084 the debug level is terse and the declaration is public. Do not
10085 generate type info.
10086 (dwarf2out_decl): Same.
10087 (add_type_attribute): Return immediately if debug level is
10090 2020-03-17 Richard Sandiford <richard.sandiford@arm.com>
10092 * config/aarch64/iterators.md (Vmtype): Handle V4BF and V8BF.
10094 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10095 Mihail Ionescu <mihail.ionescu@arm.com>
10096 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10098 * config/arm/arm-builtins.c (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS):
10099 Define qualifier for ternary operands.
10100 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
10101 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10102 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10103 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
10104 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
10105 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
10106 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
10107 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
10108 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
10109 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
10110 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
10111 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
10112 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
10113 * config/arm/arm_mve.h (vabavq_s8): Define macro.
10114 (vabavq_s16): Likewise.
10115 (vabavq_s32): Likewise.
10116 (vbicq_m_n_s16): Likewise.
10117 (vbicq_m_n_s32): Likewise.
10118 (vbicq_m_n_u16): Likewise.
10119 (vbicq_m_n_u32): Likewise.
10120 (vcmpeqq_m_f16): Likewise.
10121 (vcmpeqq_m_f32): Likewise.
10122 (vcvtaq_m_s16_f16): Likewise.
10123 (vcvtaq_m_u16_f16): Likewise.
10124 (vcvtaq_m_s32_f32): Likewise.
10125 (vcvtaq_m_u32_f32): Likewise.
10126 (vcvtq_m_f16_s16): Likewise.
10127 (vcvtq_m_f16_u16): Likewise.
10128 (vcvtq_m_f32_s32): Likewise.
10129 (vcvtq_m_f32_u32): Likewise.
10130 (vqrshrnbq_n_s16): Likewise.
10131 (vqrshrnbq_n_u16): Likewise.
10132 (vqrshrnbq_n_s32): Likewise.
10133 (vqrshrnbq_n_u32): Likewise.
10134 (vqrshrunbq_n_s16): Likewise.
10135 (vqrshrunbq_n_s32): Likewise.
10136 (vrmlaldavhaq_s32): Likewise.
10137 (vrmlaldavhaq_u32): Likewise.
10138 (vshlcq_s8): Likewise.
10139 (vshlcq_u8): Likewise.
10140 (vshlcq_s16): Likewise.
10141 (vshlcq_u16): Likewise.
10142 (vshlcq_s32): Likewise.
10143 (vshlcq_u32): Likewise.
10144 (vabavq_u8): Likewise.
10145 (vabavq_u16): Likewise.
10146 (vabavq_u32): Likewise.
10147 (__arm_vabavq_s8): Define intrinsic.
10148 (__arm_vabavq_s16): Likewise.
10149 (__arm_vabavq_s32): Likewise.
10150 (__arm_vabavq_u8): Likewise.
10151 (__arm_vabavq_u16): Likewise.
10152 (__arm_vabavq_u32): Likewise.
10153 (__arm_vbicq_m_n_s16): Likewise.
10154 (__arm_vbicq_m_n_s32): Likewise.
10155 (__arm_vbicq_m_n_u16): Likewise.
10156 (__arm_vbicq_m_n_u32): Likewise.
10157 (__arm_vqrshrnbq_n_s16): Likewise.
10158 (__arm_vqrshrnbq_n_u16): Likewise.
10159 (__arm_vqrshrnbq_n_s32): Likewise.
10160 (__arm_vqrshrnbq_n_u32): Likewise.
10161 (__arm_vqrshrunbq_n_s16): Likewise.
10162 (__arm_vqrshrunbq_n_s32): Likewise.
10163 (__arm_vrmlaldavhaq_s32): Likewise.
10164 (__arm_vrmlaldavhaq_u32): Likewise.
10165 (__arm_vshlcq_s8): Likewise.
10166 (__arm_vshlcq_u8): Likewise.
10167 (__arm_vshlcq_s16): Likewise.
10168 (__arm_vshlcq_u16): Likewise.
10169 (__arm_vshlcq_s32): Likewise.
10170 (__arm_vshlcq_u32): Likewise.
10171 (__arm_vcmpeqq_m_f16): Likewise.
10172 (__arm_vcmpeqq_m_f32): Likewise.
10173 (__arm_vcvtaq_m_s16_f16): Likewise.
10174 (__arm_vcvtaq_m_u16_f16): Likewise.
10175 (__arm_vcvtaq_m_s32_f32): Likewise.
10176 (__arm_vcvtaq_m_u32_f32): Likewise.
10177 (__arm_vcvtq_m_f16_s16): Likewise.
10178 (__arm_vcvtq_m_f16_u16): Likewise.
10179 (__arm_vcvtq_m_f32_s32): Likewise.
10180 (__arm_vcvtq_m_f32_u32): Likewise.
10181 (vcvtaq_m): Define polymorphic variant.
10182 (vcvtq_m): Likewise.
10183 (vabavq): Likewise.
10184 (vshlcq): Likewise.
10185 (vbicq_m_n): Likewise.
10186 (vqrshrnbq_n): Likewise.
10187 (vqrshrunbq_n): Likewise.
10188 * config/arm/arm_mve_builtins.def
10189 (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the builtin qualifer.
10190 (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise.
10191 (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10192 (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise.
10193 (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise.
10194 (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise.
10195 (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise.
10196 (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
10197 (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise.
10198 (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise.
10199 (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise.
10200 (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
10201 (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
10202 (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise.
10203 * config/arm/mve.md (VBICQ_M_N): Define iterator.
10204 (VCVTAQ_M): Likewise.
10205 (VCVTQ_M_TO_F): Likewise.
10206 (VQRSHRNBQ_N): Likewise.
10207 (VABAVQ): Likewise.
10208 (VSHLCQ): Likewise.
10209 (VRMLALDAVHAQ): Likewise.
10210 (mve_vbicq_m_n_<supf><mode>): Define RTL pattern.
10211 (mve_vcmpeqq_m_f<mode>): Likewise.
10212 (mve_vcvtaq_m_<supf><mode>): Likewise.
10213 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
10214 (mve_vqrshrnbq_n_<supf><mode>): Likewise.
10215 (mve_vqrshrunbq_n_s<mode>): Likewise.
10216 (mve_vrmlaldavhaq_<supf>v4si): Likewise.
10217 (mve_vabavq_<supf><mode>): Likewise.
10218 (mve_vshlcq_<supf><mode>): Likewise.
10219 (mve_vshlcq_<supf><mode>): Likewise.
10220 (mve_vshlcq_vec_<supf><mode>): Define RTL expand.
10221 (mve_vshlcq_carry_<supf><mode>): Likewise.
10223 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10224 Mihail Ionescu <mihail.ionescu@arm.com>
10225 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10227 * config/arm/arm_mve.h (vqmovntq_u16): Define macro.
10228 (vqmovnbq_u16): Likewise.
10229 (vmulltq_poly_p8): Likewise.
10230 (vmullbq_poly_p8): Likewise.
10231 (vmovntq_u16): Likewise.
10232 (vmovnbq_u16): Likewise.
10233 (vmlaldavxq_u16): Likewise.
10234 (vmlaldavq_u16): Likewise.
10235 (vqmovuntq_s16): Likewise.
10236 (vqmovunbq_s16): Likewise.
10237 (vshlltq_n_u8): Likewise.
10238 (vshllbq_n_u8): Likewise.
10239 (vorrq_n_u16): Likewise.
10240 (vbicq_n_u16): Likewise.
10241 (vcmpneq_n_f16): Likewise.
10242 (vcmpneq_f16): Likewise.
10243 (vcmpltq_n_f16): Likewise.
10244 (vcmpltq_f16): Likewise.
10245 (vcmpleq_n_f16): Likewise.
10246 (vcmpleq_f16): Likewise.
10247 (vcmpgtq_n_f16): Likewise.
10248 (vcmpgtq_f16): Likewise.
10249 (vcmpgeq_n_f16): Likewise.
10250 (vcmpgeq_f16): Likewise.
10251 (vcmpeqq_n_f16): Likewise.
10252 (vcmpeqq_f16): Likewise.
10253 (vsubq_f16): Likewise.
10254 (vqmovntq_s16): Likewise.
10255 (vqmovnbq_s16): Likewise.
10256 (vqdmulltq_s16): Likewise.
10257 (vqdmulltq_n_s16): Likewise.
10258 (vqdmullbq_s16): Likewise.
10259 (vqdmullbq_n_s16): Likewise.
10260 (vorrq_f16): Likewise.
10261 (vornq_f16): Likewise.
10262 (vmulq_n_f16): Likewise.
10263 (vmulq_f16): Likewise.
10264 (vmovntq_s16): Likewise.
10265 (vmovnbq_s16): Likewise.
10266 (vmlsldavxq_s16): Likewise.
10267 (vmlsldavq_s16): Likewise.
10268 (vmlaldavxq_s16): Likewise.
10269 (vmlaldavq_s16): Likewise.
10270 (vminnmvq_f16): Likewise.
10271 (vminnmq_f16): Likewise.
10272 (vminnmavq_f16): Likewise.
10273 (vminnmaq_f16): Likewise.
10274 (vmaxnmvq_f16): Likewise.
10275 (vmaxnmq_f16): Likewise.
10276 (vmaxnmavq_f16): Likewise.
10277 (vmaxnmaq_f16): Likewise.
10278 (veorq_f16): Likewise.
10279 (vcmulq_rot90_f16): Likewise.
10280 (vcmulq_rot270_f16): Likewise.
10281 (vcmulq_rot180_f16): Likewise.
10282 (vcmulq_f16): Likewise.
10283 (vcaddq_rot90_f16): Likewise.
10284 (vcaddq_rot270_f16): Likewise.
10285 (vbicq_f16): Likewise.
10286 (vandq_f16): Likewise.
10287 (vaddq_n_f16): Likewise.
10288 (vabdq_f16): Likewise.
10289 (vshlltq_n_s8): Likewise.
10290 (vshllbq_n_s8): Likewise.
10291 (vorrq_n_s16): Likewise.
10292 (vbicq_n_s16): Likewise.
10293 (vqmovntq_u32): Likewise.
10294 (vqmovnbq_u32): Likewise.
10295 (vmulltq_poly_p16): Likewise.
10296 (vmullbq_poly_p16): Likewise.
10297 (vmovntq_u32): Likewise.
10298 (vmovnbq_u32): Likewise.
10299 (vmlaldavxq_u32): Likewise.
10300 (vmlaldavq_u32): Likewise.
10301 (vqmovuntq_s32): Likewise.
10302 (vqmovunbq_s32): Likewise.
10303 (vshlltq_n_u16): Likewise.
10304 (vshllbq_n_u16): Likewise.
10305 (vorrq_n_u32): Likewise.
10306 (vbicq_n_u32): Likewise.
10307 (vcmpneq_n_f32): Likewise.
10308 (vcmpneq_f32): Likewise.
10309 (vcmpltq_n_f32): Likewise.
10310 (vcmpltq_f32): Likewise.
10311 (vcmpleq_n_f32): Likewise.
10312 (vcmpleq_f32): Likewise.
10313 (vcmpgtq_n_f32): Likewise.
10314 (vcmpgtq_f32): Likewise.
10315 (vcmpgeq_n_f32): Likewise.
10316 (vcmpgeq_f32): Likewise.
10317 (vcmpeqq_n_f32): Likewise.
10318 (vcmpeqq_f32): Likewise.
10319 (vsubq_f32): Likewise.
10320 (vqmovntq_s32): Likewise.
10321 (vqmovnbq_s32): Likewise.
10322 (vqdmulltq_s32): Likewise.
10323 (vqdmulltq_n_s32): Likewise.
10324 (vqdmullbq_s32): Likewise.
10325 (vqdmullbq_n_s32): Likewise.
10326 (vorrq_f32): Likewise.
10327 (vornq_f32): Likewise.
10328 (vmulq_n_f32): Likewise.
10329 (vmulq_f32): Likewise.
10330 (vmovntq_s32): Likewise.
10331 (vmovnbq_s32): Likewise.
10332 (vmlsldavxq_s32): Likewise.
10333 (vmlsldavq_s32): Likewise.
10334 (vmlaldavxq_s32): Likewise.
10335 (vmlaldavq_s32): Likewise.
10336 (vminnmvq_f32): Likewise.
10337 (vminnmq_f32): Likewise.
10338 (vminnmavq_f32): Likewise.
10339 (vminnmaq_f32): Likewise.
10340 (vmaxnmvq_f32): Likewise.
10341 (vmaxnmq_f32): Likewise.
10342 (vmaxnmavq_f32): Likewise.
10343 (vmaxnmaq_f32): Likewise.
10344 (veorq_f32): Likewise.
10345 (vcmulq_rot90_f32): Likewise.
10346 (vcmulq_rot270_f32): Likewise.
10347 (vcmulq_rot180_f32): Likewise.
10348 (vcmulq_f32): Likewise.
10349 (vcaddq_rot90_f32): Likewise.
10350 (vcaddq_rot270_f32): Likewise.
10351 (vbicq_f32): Likewise.
10352 (vandq_f32): Likewise.
10353 (vaddq_n_f32): Likewise.
10354 (vabdq_f32): Likewise.
10355 (vshlltq_n_s16): Likewise.
10356 (vshllbq_n_s16): Likewise.
10357 (vorrq_n_s32): Likewise.
10358 (vbicq_n_s32): Likewise.
10359 (vrmlaldavhq_u32): Likewise.
10360 (vctp8q_m): Likewise.
10361 (vctp64q_m): Likewise.
10362 (vctp32q_m): Likewise.
10363 (vctp16q_m): Likewise.
10364 (vaddlvaq_u32): Likewise.
10365 (vrmlsldavhxq_s32): Likewise.
10366 (vrmlsldavhq_s32): Likewise.
10367 (vrmlaldavhxq_s32): Likewise.
10368 (vrmlaldavhq_s32): Likewise.
10369 (vcvttq_f16_f32): Likewise.
10370 (vcvtbq_f16_f32): Likewise.
10371 (vaddlvaq_s32): Likewise.
10372 (__arm_vqmovntq_u16): Define intrinsic.
10373 (__arm_vqmovnbq_u16): Likewise.
10374 (__arm_vmulltq_poly_p8): Likewise.
10375 (__arm_vmullbq_poly_p8): Likewise.
10376 (__arm_vmovntq_u16): Likewise.
10377 (__arm_vmovnbq_u16): Likewise.
10378 (__arm_vmlaldavxq_u16): Likewise.
10379 (__arm_vmlaldavq_u16): Likewise.
10380 (__arm_vqmovuntq_s16): Likewise.
10381 (__arm_vqmovunbq_s16): Likewise.
10382 (__arm_vshlltq_n_u8): Likewise.
10383 (__arm_vshllbq_n_u8): Likewise.
10384 (__arm_vorrq_n_u16): Likewise.
10385 (__arm_vbicq_n_u16): Likewise.
10386 (__arm_vcmpneq_n_f16): Likewise.
10387 (__arm_vcmpneq_f16): Likewise.
10388 (__arm_vcmpltq_n_f16): Likewise.
10389 (__arm_vcmpltq_f16): Likewise.
10390 (__arm_vcmpleq_n_f16): Likewise.
10391 (__arm_vcmpleq_f16): Likewise.
10392 (__arm_vcmpgtq_n_f16): Likewise.
10393 (__arm_vcmpgtq_f16): Likewise.
10394 (__arm_vcmpgeq_n_f16): Likewise.
10395 (__arm_vcmpgeq_f16): Likewise.
10396 (__arm_vcmpeqq_n_f16): Likewise.
10397 (__arm_vcmpeqq_f16): Likewise.
10398 (__arm_vsubq_f16): Likewise.
10399 (__arm_vqmovntq_s16): Likewise.
10400 (__arm_vqmovnbq_s16): Likewise.
10401 (__arm_vqdmulltq_s16): Likewise.
10402 (__arm_vqdmulltq_n_s16): Likewise.
10403 (__arm_vqdmullbq_s16): Likewise.
10404 (__arm_vqdmullbq_n_s16): Likewise.
10405 (__arm_vorrq_f16): Likewise.
10406 (__arm_vornq_f16): Likewise.
10407 (__arm_vmulq_n_f16): Likewise.
10408 (__arm_vmulq_f16): Likewise.
10409 (__arm_vmovntq_s16): Likewise.
10410 (__arm_vmovnbq_s16): Likewise.
10411 (__arm_vmlsldavxq_s16): Likewise.
10412 (__arm_vmlsldavq_s16): Likewise.
10413 (__arm_vmlaldavxq_s16): Likewise.
10414 (__arm_vmlaldavq_s16): Likewise.
10415 (__arm_vminnmvq_f16): Likewise.
10416 (__arm_vminnmq_f16): Likewise.
10417 (__arm_vminnmavq_f16): Likewise.
10418 (__arm_vminnmaq_f16): Likewise.
10419 (__arm_vmaxnmvq_f16): Likewise.
10420 (__arm_vmaxnmq_f16): Likewise.
10421 (__arm_vmaxnmavq_f16): Likewise.
10422 (__arm_vmaxnmaq_f16): Likewise.
10423 (__arm_veorq_f16): Likewise.
10424 (__arm_vcmulq_rot90_f16): Likewise.
10425 (__arm_vcmulq_rot270_f16): Likewise.
10426 (__arm_vcmulq_rot180_f16): Likewise.
10427 (__arm_vcmulq_f16): Likewise.
10428 (__arm_vcaddq_rot90_f16): Likewise.
10429 (__arm_vcaddq_rot270_f16): Likewise.
10430 (__arm_vbicq_f16): Likewise.
10431 (__arm_vandq_f16): Likewise.
10432 (__arm_vaddq_n_f16): Likewise.
10433 (__arm_vabdq_f16): Likewise.
10434 (__arm_vshlltq_n_s8): Likewise.
10435 (__arm_vshllbq_n_s8): Likewise.
10436 (__arm_vorrq_n_s16): Likewise.
10437 (__arm_vbicq_n_s16): Likewise.
10438 (__arm_vqmovntq_u32): Likewise.
10439 (__arm_vqmovnbq_u32): Likewise.
10440 (__arm_vmulltq_poly_p16): Likewise.
10441 (__arm_vmullbq_poly_p16): Likewise.
10442 (__arm_vmovntq_u32): Likewise.
10443 (__arm_vmovnbq_u32): Likewise.
10444 (__arm_vmlaldavxq_u32): Likewise.
10445 (__arm_vmlaldavq_u32): Likewise.
10446 (__arm_vqmovuntq_s32): Likewise.
10447 (__arm_vqmovunbq_s32): Likewise.
10448 (__arm_vshlltq_n_u16): Likewise.
10449 (__arm_vshllbq_n_u16): Likewise.
10450 (__arm_vorrq_n_u32): Likewise.
10451 (__arm_vbicq_n_u32): Likewise.
10452 (__arm_vcmpneq_n_f32): Likewise.
10453 (__arm_vcmpneq_f32): Likewise.
10454 (__arm_vcmpltq_n_f32): Likewise.
10455 (__arm_vcmpltq_f32): Likewise.
10456 (__arm_vcmpleq_n_f32): Likewise.
10457 (__arm_vcmpleq_f32): Likewise.
10458 (__arm_vcmpgtq_n_f32): Likewise.
10459 (__arm_vcmpgtq_f32): Likewise.
10460 (__arm_vcmpgeq_n_f32): Likewise.
10461 (__arm_vcmpgeq_f32): Likewise.
10462 (__arm_vcmpeqq_n_f32): Likewise.
10463 (__arm_vcmpeqq_f32): Likewise.
10464 (__arm_vsubq_f32): Likewise.
10465 (__arm_vqmovntq_s32): Likewise.
10466 (__arm_vqmovnbq_s32): Likewise.
10467 (__arm_vqdmulltq_s32): Likewise.
10468 (__arm_vqdmulltq_n_s32): Likewise.
10469 (__arm_vqdmullbq_s32): Likewise.
10470 (__arm_vqdmullbq_n_s32): Likewise.
10471 (__arm_vorrq_f32): Likewise.
10472 (__arm_vornq_f32): Likewise.
10473 (__arm_vmulq_n_f32): Likewise.
10474 (__arm_vmulq_f32): Likewise.
10475 (__arm_vmovntq_s32): Likewise.
10476 (__arm_vmovnbq_s32): Likewise.
10477 (__arm_vmlsldavxq_s32): Likewise.
10478 (__arm_vmlsldavq_s32): Likewise.
10479 (__arm_vmlaldavxq_s32): Likewise.
10480 (__arm_vmlaldavq_s32): Likewise.
10481 (__arm_vminnmvq_f32): Likewise.
10482 (__arm_vminnmq_f32): Likewise.
10483 (__arm_vminnmavq_f32): Likewise.
10484 (__arm_vminnmaq_f32): Likewise.
10485 (__arm_vmaxnmvq_f32): Likewise.
10486 (__arm_vmaxnmq_f32): Likewise.
10487 (__arm_vmaxnmavq_f32): Likewise.
10488 (__arm_vmaxnmaq_f32): Likewise.
10489 (__arm_veorq_f32): Likewise.
10490 (__arm_vcmulq_rot90_f32): Likewise.
10491 (__arm_vcmulq_rot270_f32): Likewise.
10492 (__arm_vcmulq_rot180_f32): Likewise.
10493 (__arm_vcmulq_f32): Likewise.
10494 (__arm_vcaddq_rot90_f32): Likewise.
10495 (__arm_vcaddq_rot270_f32): Likewise.
10496 (__arm_vbicq_f32): Likewise.
10497 (__arm_vandq_f32): Likewise.
10498 (__arm_vaddq_n_f32): Likewise.
10499 (__arm_vabdq_f32): Likewise.
10500 (__arm_vshlltq_n_s16): Likewise.
10501 (__arm_vshllbq_n_s16): Likewise.
10502 (__arm_vorrq_n_s32): Likewise.
10503 (__arm_vbicq_n_s32): Likewise.
10504 (__arm_vrmlaldavhq_u32): Likewise.
10505 (__arm_vctp8q_m): Likewise.
10506 (__arm_vctp64q_m): Likewise.
10507 (__arm_vctp32q_m): Likewise.
10508 (__arm_vctp16q_m): Likewise.
10509 (__arm_vaddlvaq_u32): Likewise.
10510 (__arm_vrmlsldavhxq_s32): Likewise.
10511 (__arm_vrmlsldavhq_s32): Likewise.
10512 (__arm_vrmlaldavhxq_s32): Likewise.
10513 (__arm_vrmlaldavhq_s32): Likewise.
10514 (__arm_vcvttq_f16_f32): Likewise.
10515 (__arm_vcvtbq_f16_f32): Likewise.
10516 (__arm_vaddlvaq_s32): Likewise.
10517 (vst4q): Define polymorphic variant.
10518 (vrndxq): Likewise.
10520 (vrndpq): Likewise.
10521 (vrndnq): Likewise.
10522 (vrndmq): Likewise.
10523 (vrndaq): Likewise.
10524 (vrev64q): Likewise.
10526 (vdupq_n): Likewise.
10528 (vrev32q): Likewise.
10529 (vcvtbq_f32): Likewise.
10530 (vcvttq_f32): Likewise.
10532 (vsubq_n): Likewise.
10533 (vbrsrq_n): Likewise.
10534 (vcvtq_n): Likewise.
10538 (vaddq_n): Likewise.
10542 (vmulq_n): Likewise.
10544 (vcaddq_rot270): Likewise.
10545 (vcmpeqq_n): Likewise.
10546 (vcmpeqq): Likewise.
10547 (vcaddq_rot90): Likewise.
10548 (vcmpgeq_n): Likewise.
10549 (vcmpgeq): Likewise.
10550 (vcmpgtq_n): Likewise.
10551 (vcmpgtq): Likewise.
10552 (vcmpgtq): Likewise.
10553 (vcmpleq_n): Likewise.
10554 (vcmpleq_n): Likewise.
10555 (vcmpleq): Likewise.
10556 (vcmpleq): Likewise.
10557 (vcmpltq_n): Likewise.
10558 (vcmpltq_n): Likewise.
10559 (vcmpltq): Likewise.
10560 (vcmpltq): Likewise.
10561 (vcmpneq_n): Likewise.
10562 (vcmpneq_n): Likewise.
10563 (vcmpneq): Likewise.
10564 (vcmpneq): Likewise.
10565 (vcmulq): Likewise.
10566 (vcmulq): Likewise.
10567 (vcmulq_rot180): Likewise.
10568 (vcmulq_rot180): Likewise.
10569 (vcmulq_rot270): Likewise.
10570 (vcmulq_rot270): Likewise.
10571 (vcmulq_rot90): Likewise.
10572 (vcmulq_rot90): Likewise.
10575 (vmaxnmaq): Likewise.
10576 (vmaxnmaq): Likewise.
10577 (vmaxnmavq): Likewise.
10578 (vmaxnmavq): Likewise.
10579 (vmaxnmq): Likewise.
10580 (vmaxnmq): Likewise.
10581 (vmaxnmvq): Likewise.
10582 (vmaxnmvq): Likewise.
10583 (vminnmaq): Likewise.
10584 (vminnmaq): Likewise.
10585 (vminnmavq): Likewise.
10586 (vminnmavq): Likewise.
10587 (vminnmq): Likewise.
10588 (vminnmq): Likewise.
10589 (vminnmvq): Likewise.
10590 (vminnmvq): Likewise.
10591 (vbicq_n): Likewise.
10592 (vqmovntq): Likewise.
10593 (vqmovntq): Likewise.
10594 (vqmovnbq): Likewise.
10595 (vqmovnbq): Likewise.
10596 (vmulltq_poly): Likewise.
10597 (vmulltq_poly): Likewise.
10598 (vmullbq_poly): Likewise.
10599 (vmullbq_poly): Likewise.
10600 (vmovntq): Likewise.
10601 (vmovntq): Likewise.
10602 (vmovnbq): Likewise.
10603 (vmovnbq): Likewise.
10604 (vmlaldavxq): Likewise.
10605 (vmlaldavxq): Likewise.
10606 (vqmovuntq): Likewise.
10607 (vqmovuntq): Likewise.
10608 (vshlltq_n): Likewise.
10609 (vshlltq_n): Likewise.
10610 (vshllbq_n): Likewise.
10611 (vshllbq_n): Likewise.
10612 (vorrq_n): Likewise.
10613 (vorrq_n): Likewise.
10614 (vmlaldavq): Likewise.
10615 (vmlaldavq): Likewise.
10616 (vqmovunbq): Likewise.
10617 (vqmovunbq): Likewise.
10618 (vqdmulltq_n): Likewise.
10619 (vqdmulltq_n): Likewise.
10620 (vqdmulltq): Likewise.
10621 (vqdmulltq): Likewise.
10622 (vqdmullbq_n): Likewise.
10623 (vqdmullbq_n): Likewise.
10624 (vqdmullbq): Likewise.
10625 (vqdmullbq): Likewise.
10626 (vaddlvaq): Likewise.
10627 (vaddlvaq): Likewise.
10628 (vrmlaldavhq): Likewise.
10629 (vrmlaldavhq): Likewise.
10630 (vrmlaldavhxq): Likewise.
10631 (vrmlaldavhxq): Likewise.
10632 (vrmlsldavhq): Likewise.
10633 (vrmlsldavhq): Likewise.
10634 (vrmlsldavhxq): Likewise.
10635 (vrmlsldavhxq): Likewise.
10636 (vmlsldavxq): Likewise.
10637 (vmlsldavxq): Likewise.
10638 (vmlsldavq): Likewise.
10639 (vmlsldavq): Likewise.
10640 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
10641 (BINOP_NONE_NONE_NONE): Likewise.
10642 (BINOP_UNONE_NONE_NONE): Likewise.
10643 (BINOP_UNONE_UNONE_IMM): Likewise.
10644 (BINOP_UNONE_UNONE_NONE): Likewise.
10645 (BINOP_UNONE_UNONE_UNONE): Likewise.
10646 * config/arm/mve.md (mve_vabdq_f<mode>): Define RTL pattern.
10647 (mve_vaddlvaq_<supf>v4si): Likewise.
10648 (mve_vaddq_n_f<mode>): Likewise.
10649 (mve_vandq_f<mode>): Likewise.
10650 (mve_vbicq_f<mode>): Likewise.
10651 (mve_vbicq_n_<supf><mode>): Likewise.
10652 (mve_vcaddq_rot270_f<mode>): Likewise.
10653 (mve_vcaddq_rot90_f<mode>): Likewise.
10654 (mve_vcmpeqq_f<mode>): Likewise.
10655 (mve_vcmpeqq_n_f<mode>): Likewise.
10656 (mve_vcmpgeq_f<mode>): Likewise.
10657 (mve_vcmpgeq_n_f<mode>): Likewise.
10658 (mve_vcmpgtq_f<mode>): Likewise.
10659 (mve_vcmpgtq_n_f<mode>): Likewise.
10660 (mve_vcmpleq_f<mode>): Likewise.
10661 (mve_vcmpleq_n_f<mode>): Likewise.
10662 (mve_vcmpltq_f<mode>): Likewise.
10663 (mve_vcmpltq_n_f<mode>): Likewise.
10664 (mve_vcmpneq_f<mode>): Likewise.
10665 (mve_vcmpneq_n_f<mode>): Likewise.
10666 (mve_vcmulq_f<mode>): Likewise.
10667 (mve_vcmulq_rot180_f<mode>): Likewise.
10668 (mve_vcmulq_rot270_f<mode>): Likewise.
10669 (mve_vcmulq_rot90_f<mode>): Likewise.
10670 (mve_vctp<mode1>q_mhi): Likewise.
10671 (mve_vcvtbq_f16_f32v8hf): Likewise.
10672 (mve_vcvttq_f16_f32v8hf): Likewise.
10673 (mve_veorq_f<mode>): Likewise.
10674 (mve_vmaxnmaq_f<mode>): Likewise.
10675 (mve_vmaxnmavq_f<mode>): Likewise.
10676 (mve_vmaxnmq_f<mode>): Likewise.
10677 (mve_vmaxnmvq_f<mode>): Likewise.
10678 (mve_vminnmaq_f<mode>): Likewise.
10679 (mve_vminnmavq_f<mode>): Likewise.
10680 (mve_vminnmq_f<mode>): Likewise.
10681 (mve_vminnmvq_f<mode>): Likewise.
10682 (mve_vmlaldavq_<supf><mode>): Likewise.
10683 (mve_vmlaldavxq_<supf><mode>): Likewise.
10684 (mve_vmlsldavq_s<mode>): Likewise.
10685 (mve_vmlsldavxq_s<mode>): Likewise.
10686 (mve_vmovnbq_<supf><mode>): Likewise.
10687 (mve_vmovntq_<supf><mode>): Likewise.
10688 (mve_vmulq_f<mode>): Likewise.
10689 (mve_vmulq_n_f<mode>): Likewise.
10690 (mve_vornq_f<mode>): Likewise.
10691 (mve_vorrq_f<mode>): Likewise.
10692 (mve_vorrq_n_<supf><mode>): Likewise.
10693 (mve_vqdmullbq_n_s<mode>): Likewise.
10694 (mve_vqdmullbq_s<mode>): Likewise.
10695 (mve_vqdmulltq_n_s<mode>): Likewise.
10696 (mve_vqdmulltq_s<mode>): Likewise.
10697 (mve_vqmovnbq_<supf><mode>): Likewise.
10698 (mve_vqmovntq_<supf><mode>): Likewise.
10699 (mve_vqmovunbq_s<mode>): Likewise.
10700 (mve_vqmovuntq_s<mode>): Likewise.
10701 (mve_vrmlaldavhxq_sv4si): Likewise.
10702 (mve_vrmlsldavhq_sv4si): Likewise.
10703 (mve_vrmlsldavhxq_sv4si): Likewise.
10704 (mve_vshllbq_n_<supf><mode>): Likewise.
10705 (mve_vshlltq_n_<supf><mode>): Likewise.
10706 (mve_vsubq_f<mode>): Likewise.
10707 (mve_vmulltq_poly_p<mode>): Likewise.
10708 (mve_vmullbq_poly_p<mode>): Likewise.
10709 (mve_vrmlaldavhq_<supf>v4si): Likewise.
10711 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
10712 Mihail Ionescu <mihail.ionescu@arm.com>
10713 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
10715 * config/arm/arm_mve.h (vsubq_u8): Define macro.
10716 (vsubq_n_u8): Likewise.
10717 (vrmulhq_u8): Likewise.
10718 (vrhaddq_u8): Likewise.
10719 (vqsubq_u8): Likewise.
10720 (vqsubq_n_u8): Likewise.
10721 (vqaddq_u8): Likewise.
10722 (vqaddq_n_u8): Likewise.
10723 (vorrq_u8): Likewise.
10724 (vornq_u8): Likewise.
10725 (vmulq_u8): Likewise.
10726 (vmulq_n_u8): Likewise.
10727 (vmulltq_int_u8): Likewise.
10728 (vmullbq_int_u8): Likewise.
10729 (vmulhq_u8): Likewise.
10730 (vmladavq_u8): Likewise.
10731 (vminvq_u8): Likewise.
10732 (vminq_u8): Likewise.
10733 (vmaxvq_u8): Likewise.
10734 (vmaxq_u8): Likewise.
10735 (vhsubq_u8): Likewise.
10736 (vhsubq_n_u8): Likewise.
10737 (vhaddq_u8): Likewise.
10738 (vhaddq_n_u8): Likewise.
10739 (veorq_u8): Likewise.
10740 (vcmpneq_n_u8): Likewise.
10741 (vcmphiq_u8): Likewise.
10742 (vcmphiq_n_u8): Likewise.
10743 (vcmpeqq_u8): Likewise.
10744 (vcmpeqq_n_u8): Likewise.
10745 (vcmpcsq_u8): Likewise.
10746 (vcmpcsq_n_u8): Likewise.
10747 (vcaddq_rot90_u8): Likewise.
10748 (vcaddq_rot270_u8): Likewise.
10749 (vbicq_u8): Likewise.
10750 (vandq_u8): Likewise.
10751 (vaddvq_p_u8): Likewise.
10752 (vaddvaq_u8): Likewise.
10753 (vaddq_n_u8): Likewise.
10754 (vabdq_u8): Likewise.
10755 (vshlq_r_u8): Likewise.
10756 (vrshlq_u8): Likewise.
10757 (vrshlq_n_u8): Likewise.
10758 (vqshlq_u8): Likewise.
10759 (vqshlq_r_u8): Likewise.
10760 (vqrshlq_u8): Likewise.
10761 (vqrshlq_n_u8): Likewise.
10762 (vminavq_s8): Likewise.
10763 (vminaq_s8): Likewise.
10764 (vmaxavq_s8): Likewise.
10765 (vmaxaq_s8): Likewise.
10766 (vbrsrq_n_u8): Likewise.
10767 (vshlq_n_u8): Likewise.
10768 (vrshrq_n_u8): Likewise.
10769 (vqshlq_n_u8): Likewise.
10770 (vcmpneq_n_s8): Likewise.
10771 (vcmpltq_s8): Likewise.
10772 (vcmpltq_n_s8): Likewise.
10773 (vcmpleq_s8): Likewise.
10774 (vcmpleq_n_s8): Likewise.
10775 (vcmpgtq_s8): Likewise.
10776 (vcmpgtq_n_s8): Likewise.
10777 (vcmpgeq_s8): Likewise.
10778 (vcmpgeq_n_s8): Likewise.
10779 (vcmpeqq_s8): Likewise.
10780 (vcmpeqq_n_s8): Likewise.
10781 (vqshluq_n_s8): Likewise.
10782 (vaddvq_p_s8): Likewise.
10783 (vsubq_s8): Likewise.
10784 (vsubq_n_s8): Likewise.
10785 (vshlq_r_s8): Likewise.
10786 (vrshlq_s8): Likewise.
10787 (vrshlq_n_s8): Likewise.
10788 (vrmulhq_s8): Likewise.
10789 (vrhaddq_s8): Likewise.
10790 (vqsubq_s8): Likewise.
10791 (vqsubq_n_s8): Likewise.
10792 (vqshlq_s8): Likewise.
10793 (vqshlq_r_s8): Likewise.
10794 (vqrshlq_s8): Likewise.
10795 (vqrshlq_n_s8): Likewise.
10796 (vqrdmulhq_s8): Likewise.
10797 (vqrdmulhq_n_s8): Likewise.
10798 (vqdmulhq_s8): Likewise.
10799 (vqdmulhq_n_s8): Likewise.
10800 (vqaddq_s8): Likewise.
10801 (vqaddq_n_s8): Likewise.
10802 (vorrq_s8): Likewise.
10803 (vornq_s8): Likewise.
10804 (vmulq_s8): Likewise.
10805 (vmulq_n_s8): Likewise.
10806 (vmulltq_int_s8): Likewise.
10807 (vmullbq_int_s8): Likewise.
10808 (vmulhq_s8): Likewise.
10809 (vmlsdavxq_s8): Likewise.
10810 (vmlsdavq_s8): Likewise.
10811 (vmladavxq_s8): Likewise.
10812 (vmladavq_s8): Likewise.
10813 (vminvq_s8): Likewise.
10814 (vminq_s8): Likewise.
10815 (vmaxvq_s8): Likewise.
10816 (vmaxq_s8): Likewise.
10817 (vhsubq_s8): Likewise.
10818 (vhsubq_n_s8): Likewise.
10819 (vhcaddq_rot90_s8): Likewise.
10820 (vhcaddq_rot270_s8): Likewise.
10821 (vhaddq_s8): Likewise.
10822 (vhaddq_n_s8): Likewise.
10823 (veorq_s8): Likewise.
10824 (vcaddq_rot90_s8): Likewise.
10825 (vcaddq_rot270_s8): Likewise.
10826 (vbrsrq_n_s8): Likewise.
10827 (vbicq_s8): Likewise.
10828 (vandq_s8): Likewise.
10829 (vaddvaq_s8): Likewise.
10830 (vaddq_n_s8): Likewise.
10831 (vabdq_s8): Likewise.
10832 (vshlq_n_s8): Likewise.
10833 (vrshrq_n_s8): Likewise.
10834 (vqshlq_n_s8): Likewise.
10835 (vsubq_u16): Likewise.
10836 (vsubq_n_u16): Likewise.
10837 (vrmulhq_u16): Likewise.
10838 (vrhaddq_u16): Likewise.
10839 (vqsubq_u16): Likewise.
10840 (vqsubq_n_u16): Likewise.
10841 (vqaddq_u16): Likewise.
10842 (vqaddq_n_u16): Likewise.
10843 (vorrq_u16): Likewise.
10844 (vornq_u16): Likewise.
10845 (vmulq_u16): Likewise.
10846 (vmulq_n_u16): Likewise.
10847 (vmulltq_int_u16): Likewise.
10848 (vmullbq_int_u16): Likewise.
10849 (vmulhq_u16): Likewise.
10850 (vmladavq_u16): Likewise.
10851 (vminvq_u16): Likewise.
10852 (vminq_u16): Likewise.
10853 (vmaxvq_u16): Likewise.
10854 (vmaxq_u16): Likewise.
10855 (vhsubq_u16): Likewise.
10856 (vhsubq_n_u16): Likewise.
10857 (vhaddq_u16): Likewise.
10858 (vhaddq_n_u16): Likewise.
10859 (veorq_u16): Likewise.
10860 (vcmpneq_n_u16): Likewise.
10861 (vcmphiq_u16): Likewise.
10862 (vcmphiq_n_u16): Likewise.
10863 (vcmpeqq_u16): Likewise.
10864 (vcmpeqq_n_u16): Likewise.
10865 (vcmpcsq_u16): Likewise.
10866 (vcmpcsq_n_u16): Likewise.
10867 (vcaddq_rot90_u16): Likewise.
10868 (vcaddq_rot270_u16): Likewise.
10869 (vbicq_u16): Likewise.
10870 (vandq_u16): Likewise.
10871 (vaddvq_p_u16): Likewise.
10872 (vaddvaq_u16): Likewise.
10873 (vaddq_n_u16): Likewise.
10874 (vabdq_u16): Likewise.
10875 (vshlq_r_u16): Likewise.
10876 (vrshlq_u16): Likewise.
10877 (vrshlq_n_u16): Likewise.
10878 (vqshlq_u16): Likewise.
10879 (vqshlq_r_u16): Likewise.
10880 (vqrshlq_u16): Likewise.
10881 (vqrshlq_n_u16): Likewise.
10882 (vminavq_s16): Likewise.
10883 (vminaq_s16): Likewise.
10884 (vmaxavq_s16): Likewise.
10885 (vmaxaq_s16): Likewise.
10886 (vbrsrq_n_u16): Likewise.
10887 (vshlq_n_u16): Likewise.
10888 (vrshrq_n_u16): Likewise.
10889 (vqshlq_n_u16): Likewise.
10890 (vcmpneq_n_s16): Likewise.
10891 (vcmpltq_s16): Likewise.
10892 (vcmpltq_n_s16): Likewise.
10893 (vcmpleq_s16): Likewise.
10894 (vcmpleq_n_s16): Likewise.
10895 (vcmpgtq_s16): Likewise.
10896 (vcmpgtq_n_s16): Likewise.
10897 (vcmpgeq_s16): Likewise.
10898 (vcmpgeq_n_s16): Likewise.
10899 (vcmpeqq_s16): Likewise.
10900 (vcmpeqq_n_s16): Likewise.
10901 (vqshluq_n_s16): Likewise.
10902 (vaddvq_p_s16): Likewise.
10903 (vsubq_s16): Likewise.
10904 (vsubq_n_s16): Likewise.
10905 (vshlq_r_s16): Likewise.
10906 (vrshlq_s16): Likewise.
10907 (vrshlq_n_s16): Likewise.
10908 (vrmulhq_s16): Likewise.
10909 (vrhaddq_s16): Likewise.
10910 (vqsubq_s16): Likewise.
10911 (vqsubq_n_s16): Likewise.
10912 (vqshlq_s16): Likewise.
10913 (vqshlq_r_s16): Likewise.
10914 (vqrshlq_s16): Likewise.
10915 (vqrshlq_n_s16): Likewise.
10916 (vqrdmulhq_s16): Likewise.
10917 (vqrdmulhq_n_s16): Likewise.
10918 (vqdmulhq_s16): Likewise.
10919 (vqdmulhq_n_s16): Likewise.
10920 (vqaddq_s16): Likewise.
10921 (vqaddq_n_s16): Likewise.
10922 (vorrq_s16): Likewise.
10923 (vornq_s16): Likewise.
10924 (vmulq_s16): Likewise.
10925 (vmulq_n_s16): Likewise.
10926 (vmulltq_int_s16): Likewise.
10927 (vmullbq_int_s16): Likewise.
10928 (vmulhq_s16): Likewise.
10929 (vmlsdavxq_s16): Likewise.
10930 (vmlsdavq_s16): Likewise.
10931 (vmladavxq_s16): Likewise.
10932 (vmladavq_s16): Likewise.
10933 (vminvq_s16): Likewise.
10934 (vminq_s16): Likewise.
10935 (vmaxvq_s16): Likewise.
10936 (vmaxq_s16): Likewise.
10937 (vhsubq_s16): Likewise.
10938 (vhsubq_n_s16): Likewise.
10939 (vhcaddq_rot90_s16): Likewise.
10940 (vhcaddq_rot270_s16): Likewise.
10941 (vhaddq_s16): Likewise.
10942 (vhaddq_n_s16): Likewise.
10943 (veorq_s16): Likewise.
10944 (vcaddq_rot90_s16): Likewise.
10945 (vcaddq_rot270_s16): Likewise.
10946 (vbrsrq_n_s16): Likewise.
10947 (vbicq_s16): Likewise.
10948 (vandq_s16): Likewise.
10949 (vaddvaq_s16): Likewise.
10950 (vaddq_n_s16): Likewise.
10951 (vabdq_s16): Likewise.
10952 (vshlq_n_s16): Likewise.
10953 (vrshrq_n_s16): Likewise.
10954 (vqshlq_n_s16): Likewise.
10955 (vsubq_u32): Likewise.
10956 (vsubq_n_u32): Likewise.
10957 (vrmulhq_u32): Likewise.
10958 (vrhaddq_u32): Likewise.
10959 (vqsubq_u32): Likewise.
10960 (vqsubq_n_u32): Likewise.
10961 (vqaddq_u32): Likewise.
10962 (vqaddq_n_u32): Likewise.
10963 (vorrq_u32): Likewise.
10964 (vornq_u32): Likewise.
10965 (vmulq_u32): Likewise.
10966 (vmulq_n_u32): Likewise.
10967 (vmulltq_int_u32): Likewise.
10968 (vmullbq_int_u32): Likewise.
10969 (vmulhq_u32): Likewise.
10970 (vmladavq_u32): Likewise.
10971 (vminvq_u32): Likewise.
10972 (vminq_u32): Likewise.
10973 (vmaxvq_u32): Likewise.
10974 (vmaxq_u32): Likewise.
10975 (vhsubq_u32): Likewise.
10976 (vhsubq_n_u32): Likewise.
10977 (vhaddq_u32): Likewise.
10978 (vhaddq_n_u32): Likewise.
10979 (veorq_u32): Likewise.
10980 (vcmpneq_n_u32): Likewise.
10981 (vcmphiq_u32): Likewise.
10982 (vcmphiq_n_u32): Likewise.
10983 (vcmpeqq_u32): Likewise.
10984 (vcmpeqq_n_u32): Likewise.
10985 (vcmpcsq_u32): Likewise.
10986 (vcmpcsq_n_u32): Likewise.
10987 (vcaddq_rot90_u32): Likewise.
10988 (vcaddq_rot270_u32): Likewise.
10989 (vbicq_u32): Likewise.
10990 (vandq_u32): Likewise.
10991 (vaddvq_p_u32): Likewise.
10992 (vaddvaq_u32): Likewise.
10993 (vaddq_n_u32): Likewise.
10994 (vabdq_u32): Likewise.
10995 (vshlq_r_u32): Likewise.
10996 (vrshlq_u32): Likewise.
10997 (vrshlq_n_u32): Likewise.
10998 (vqshlq_u32): Likewise.
10999 (vqshlq_r_u32): Likewise.
11000 (vqrshlq_u32): Likewise.
11001 (vqrshlq_n_u32): Likewise.
11002 (vminavq_s32): Likewise.
11003 (vminaq_s32): Likewise.
11004 (vmaxavq_s32): Likewise.
11005 (vmaxaq_s32): Likewise.
11006 (vbrsrq_n_u32): Likewise.
11007 (vshlq_n_u32): Likewise.
11008 (vrshrq_n_u32): Likewise.
11009 (vqshlq_n_u32): Likewise.
11010 (vcmpneq_n_s32): Likewise.
11011 (vcmpltq_s32): Likewise.
11012 (vcmpltq_n_s32): Likewise.
11013 (vcmpleq_s32): Likewise.
11014 (vcmpleq_n_s32): Likewise.
11015 (vcmpgtq_s32): Likewise.
11016 (vcmpgtq_n_s32): Likewise.
11017 (vcmpgeq_s32): Likewise.
11018 (vcmpgeq_n_s32): Likewise.
11019 (vcmpeqq_s32): Likewise.
11020 (vcmpeqq_n_s32): Likewise.
11021 (vqshluq_n_s32): Likewise.
11022 (vaddvq_p_s32): Likewise.
11023 (vsubq_s32): Likewise.
11024 (vsubq_n_s32): Likewise.
11025 (vshlq_r_s32): Likewise.
11026 (vrshlq_s32): Likewise.
11027 (vrshlq_n_s32): Likewise.
11028 (vrmulhq_s32): Likewise.
11029 (vrhaddq_s32): Likewise.
11030 (vqsubq_s32): Likewise.
11031 (vqsubq_n_s32): Likewise.
11032 (vqshlq_s32): Likewise.
11033 (vqshlq_r_s32): Likewise.
11034 (vqrshlq_s32): Likewise.
11035 (vqrshlq_n_s32): Likewise.
11036 (vqrdmulhq_s32): Likewise.
11037 (vqrdmulhq_n_s32): Likewise.
11038 (vqdmulhq_s32): Likewise.
11039 (vqdmulhq_n_s32): Likewise.
11040 (vqaddq_s32): Likewise.
11041 (vqaddq_n_s32): Likewise.
11042 (vorrq_s32): Likewise.
11043 (vornq_s32): Likewise.
11044 (vmulq_s32): Likewise.
11045 (vmulq_n_s32): Likewise.
11046 (vmulltq_int_s32): Likewise.
11047 (vmullbq_int_s32): Likewise.
11048 (vmulhq_s32): Likewise.
11049 (vmlsdavxq_s32): Likewise.
11050 (vmlsdavq_s32): Likewise.
11051 (vmladavxq_s32): Likewise.
11052 (vmladavq_s32): Likewise.
11053 (vminvq_s32): Likewise.
11054 (vminq_s32): Likewise.
11055 (vmaxvq_s32): Likewise.
11056 (vmaxq_s32): Likewise.
11057 (vhsubq_s32): Likewise.
11058 (vhsubq_n_s32): Likewise.
11059 (vhcaddq_rot90_s32): Likewise.
11060 (vhcaddq_rot270_s32): Likewise.
11061 (vhaddq_s32): Likewise.
11062 (vhaddq_n_s32): Likewise.
11063 (veorq_s32): Likewise.
11064 (vcaddq_rot90_s32): Likewise.
11065 (vcaddq_rot270_s32): Likewise.
11066 (vbrsrq_n_s32): Likewise.
11067 (vbicq_s32): Likewise.
11068 (vandq_s32): Likewise.
11069 (vaddvaq_s32): Likewise.
11070 (vaddq_n_s32): Likewise.
11071 (vabdq_s32): Likewise.
11072 (vshlq_n_s32): Likewise.
11073 (vrshrq_n_s32): Likewise.
11074 (vqshlq_n_s32): Likewise.
11075 (__arm_vsubq_u8): Define intrinsic.
11076 (__arm_vsubq_n_u8): Likewise.
11077 (__arm_vrmulhq_u8): Likewise.
11078 (__arm_vrhaddq_u8): Likewise.
11079 (__arm_vqsubq_u8): Likewise.
11080 (__arm_vqsubq_n_u8): Likewise.
11081 (__arm_vqaddq_u8): Likewise.
11082 (__arm_vqaddq_n_u8): Likewise.
11083 (__arm_vorrq_u8): Likewise.
11084 (__arm_vornq_u8): Likewise.
11085 (__arm_vmulq_u8): Likewise.
11086 (__arm_vmulq_n_u8): Likewise.
11087 (__arm_vmulltq_int_u8): Likewise.
11088 (__arm_vmullbq_int_u8): Likewise.
11089 (__arm_vmulhq_u8): Likewise.
11090 (__arm_vmladavq_u8): Likewise.
11091 (__arm_vminvq_u8): Likewise.
11092 (__arm_vminq_u8): Likewise.
11093 (__arm_vmaxvq_u8): Likewise.
11094 (__arm_vmaxq_u8): Likewise.
11095 (__arm_vhsubq_u8): Likewise.
11096 (__arm_vhsubq_n_u8): Likewise.
11097 (__arm_vhaddq_u8): Likewise.
11098 (__arm_vhaddq_n_u8): Likewise.
11099 (__arm_veorq_u8): Likewise.
11100 (__arm_vcmpneq_n_u8): Likewise.
11101 (__arm_vcmphiq_u8): Likewise.
11102 (__arm_vcmphiq_n_u8): Likewise.
11103 (__arm_vcmpeqq_u8): Likewise.
11104 (__arm_vcmpeqq_n_u8): Likewise.
11105 (__arm_vcmpcsq_u8): Likewise.
11106 (__arm_vcmpcsq_n_u8): Likewise.
11107 (__arm_vcaddq_rot90_u8): Likewise.
11108 (__arm_vcaddq_rot270_u8): Likewise.
11109 (__arm_vbicq_u8): Likewise.
11110 (__arm_vandq_u8): Likewise.
11111 (__arm_vaddvq_p_u8): Likewise.
11112 (__arm_vaddvaq_u8): Likewise.
11113 (__arm_vaddq_n_u8): Likewise.
11114 (__arm_vabdq_u8): Likewise.
11115 (__arm_vshlq_r_u8): Likewise.
11116 (__arm_vrshlq_u8): Likewise.
11117 (__arm_vrshlq_n_u8): Likewise.
11118 (__arm_vqshlq_u8): Likewise.
11119 (__arm_vqshlq_r_u8): Likewise.
11120 (__arm_vqrshlq_u8): Likewise.
11121 (__arm_vqrshlq_n_u8): Likewise.
11122 (__arm_vminavq_s8): Likewise.
11123 (__arm_vminaq_s8): Likewise.
11124 (__arm_vmaxavq_s8): Likewise.
11125 (__arm_vmaxaq_s8): Likewise.
11126 (__arm_vbrsrq_n_u8): Likewise.
11127 (__arm_vshlq_n_u8): Likewise.
11128 (__arm_vrshrq_n_u8): Likewise.
11129 (__arm_vqshlq_n_u8): Likewise.
11130 (__arm_vcmpneq_n_s8): Likewise.
11131 (__arm_vcmpltq_s8): Likewise.
11132 (__arm_vcmpltq_n_s8): Likewise.
11133 (__arm_vcmpleq_s8): Likewise.
11134 (__arm_vcmpleq_n_s8): Likewise.
11135 (__arm_vcmpgtq_s8): Likewise.
11136 (__arm_vcmpgtq_n_s8): Likewise.
11137 (__arm_vcmpgeq_s8): Likewise.
11138 (__arm_vcmpgeq_n_s8): Likewise.
11139 (__arm_vcmpeqq_s8): Likewise.
11140 (__arm_vcmpeqq_n_s8): Likewise.
11141 (__arm_vqshluq_n_s8): Likewise.
11142 (__arm_vaddvq_p_s8): Likewise.
11143 (__arm_vsubq_s8): Likewise.
11144 (__arm_vsubq_n_s8): Likewise.
11145 (__arm_vshlq_r_s8): Likewise.
11146 (__arm_vrshlq_s8): Likewise.
11147 (__arm_vrshlq_n_s8): Likewise.
11148 (__arm_vrmulhq_s8): Likewise.
11149 (__arm_vrhaddq_s8): Likewise.
11150 (__arm_vqsubq_s8): Likewise.
11151 (__arm_vqsubq_n_s8): Likewise.
11152 (__arm_vqshlq_s8): Likewise.
11153 (__arm_vqshlq_r_s8): Likewise.
11154 (__arm_vqrshlq_s8): Likewise.
11155 (__arm_vqrshlq_n_s8): Likewise.
11156 (__arm_vqrdmulhq_s8): Likewise.
11157 (__arm_vqrdmulhq_n_s8): Likewise.
11158 (__arm_vqdmulhq_s8): Likewise.
11159 (__arm_vqdmulhq_n_s8): Likewise.
11160 (__arm_vqaddq_s8): Likewise.
11161 (__arm_vqaddq_n_s8): Likewise.
11162 (__arm_vorrq_s8): Likewise.
11163 (__arm_vornq_s8): Likewise.
11164 (__arm_vmulq_s8): Likewise.
11165 (__arm_vmulq_n_s8): Likewise.
11166 (__arm_vmulltq_int_s8): Likewise.
11167 (__arm_vmullbq_int_s8): Likewise.
11168 (__arm_vmulhq_s8): Likewise.
11169 (__arm_vmlsdavxq_s8): Likewise.
11170 (__arm_vmlsdavq_s8): Likewise.
11171 (__arm_vmladavxq_s8): Likewise.
11172 (__arm_vmladavq_s8): Likewise.
11173 (__arm_vminvq_s8): Likewise.
11174 (__arm_vminq_s8): Likewise.
11175 (__arm_vmaxvq_s8): Likewise.
11176 (__arm_vmaxq_s8): Likewise.
11177 (__arm_vhsubq_s8): Likewise.
11178 (__arm_vhsubq_n_s8): Likewise.
11179 (__arm_vhcaddq_rot90_s8): Likewise.
11180 (__arm_vhcaddq_rot270_s8): Likewise.
11181 (__arm_vhaddq_s8): Likewise.
11182 (__arm_vhaddq_n_s8): Likewise.
11183 (__arm_veorq_s8): Likewise.
11184 (__arm_vcaddq_rot90_s8): Likewise.
11185 (__arm_vcaddq_rot270_s8): Likewise.
11186 (__arm_vbrsrq_n_s8): Likewise.
11187 (__arm_vbicq_s8): Likewise.
11188 (__arm_vandq_s8): Likewise.
11189 (__arm_vaddvaq_s8): Likewise.
11190 (__arm_vaddq_n_s8): Likewise.
11191 (__arm_vabdq_s8): Likewise.
11192 (__arm_vshlq_n_s8): Likewise.
11193 (__arm_vrshrq_n_s8): Likewise.
11194 (__arm_vqshlq_n_s8): Likewise.
11195 (__arm_vsubq_u16): Likewise.
11196 (__arm_vsubq_n_u16): Likewise.
11197 (__arm_vrmulhq_u16): Likewise.
11198 (__arm_vrhaddq_u16): Likewise.
11199 (__arm_vqsubq_u16): Likewise.
11200 (__arm_vqsubq_n_u16): Likewise.
11201 (__arm_vqaddq_u16): Likewise.
11202 (__arm_vqaddq_n_u16): Likewise.
11203 (__arm_vorrq_u16): Likewise.
11204 (__arm_vornq_u16): Likewise.
11205 (__arm_vmulq_u16): Likewise.
11206 (__arm_vmulq_n_u16): Likewise.
11207 (__arm_vmulltq_int_u16): Likewise.
11208 (__arm_vmullbq_int_u16): Likewise.
11209 (__arm_vmulhq_u16): Likewise.
11210 (__arm_vmladavq_u16): Likewise.
11211 (__arm_vminvq_u16): Likewise.
11212 (__arm_vminq_u16): Likewise.
11213 (__arm_vmaxvq_u16): Likewise.
11214 (__arm_vmaxq_u16): Likewise.
11215 (__arm_vhsubq_u16): Likewise.
11216 (__arm_vhsubq_n_u16): Likewise.
11217 (__arm_vhaddq_u16): Likewise.
11218 (__arm_vhaddq_n_u16): Likewise.
11219 (__arm_veorq_u16): Likewise.
11220 (__arm_vcmpneq_n_u16): Likewise.
11221 (__arm_vcmphiq_u16): Likewise.
11222 (__arm_vcmphiq_n_u16): Likewise.
11223 (__arm_vcmpeqq_u16): Likewise.
11224 (__arm_vcmpeqq_n_u16): Likewise.
11225 (__arm_vcmpcsq_u16): Likewise.
11226 (__arm_vcmpcsq_n_u16): Likewise.
11227 (__arm_vcaddq_rot90_u16): Likewise.
11228 (__arm_vcaddq_rot270_u16): Likewise.
11229 (__arm_vbicq_u16): Likewise.
11230 (__arm_vandq_u16): Likewise.
11231 (__arm_vaddvq_p_u16): Likewise.
11232 (__arm_vaddvaq_u16): Likewise.
11233 (__arm_vaddq_n_u16): Likewise.
11234 (__arm_vabdq_u16): Likewise.
11235 (__arm_vshlq_r_u16): Likewise.
11236 (__arm_vrshlq_u16): Likewise.
11237 (__arm_vrshlq_n_u16): Likewise.
11238 (__arm_vqshlq_u16): Likewise.
11239 (__arm_vqshlq_r_u16): Likewise.
11240 (__arm_vqrshlq_u16): Likewise.
11241 (__arm_vqrshlq_n_u16): Likewise.
11242 (__arm_vminavq_s16): Likewise.
11243 (__arm_vminaq_s16): Likewise.
11244 (__arm_vmaxavq_s16): Likewise.
11245 (__arm_vmaxaq_s16): Likewise.
11246 (__arm_vbrsrq_n_u16): Likewise.
11247 (__arm_vshlq_n_u16): Likewise.
11248 (__arm_vrshrq_n_u16): Likewise.
11249 (__arm_vqshlq_n_u16): Likewise.
11250 (__arm_vcmpneq_n_s16): Likewise.
11251 (__arm_vcmpltq_s16): Likewise.
11252 (__arm_vcmpltq_n_s16): Likewise.
11253 (__arm_vcmpleq_s16): Likewise.
11254 (__arm_vcmpleq_n_s16): Likewise.
11255 (__arm_vcmpgtq_s16): Likewise.
11256 (__arm_vcmpgtq_n_s16): Likewise.
11257 (__arm_vcmpgeq_s16): Likewise.
11258 (__arm_vcmpgeq_n_s16): Likewise.
11259 (__arm_vcmpeqq_s16): Likewise.
11260 (__arm_vcmpeqq_n_s16): Likewise.
11261 (__arm_vqshluq_n_s16): Likewise.
11262 (__arm_vaddvq_p_s16): Likewise.
11263 (__arm_vsubq_s16): Likewise.
11264 (__arm_vsubq_n_s16): Likewise.
11265 (__arm_vshlq_r_s16): Likewise.
11266 (__arm_vrshlq_s16): Likewise.
11267 (__arm_vrshlq_n_s16): Likewise.
11268 (__arm_vrmulhq_s16): Likewise.
11269 (__arm_vrhaddq_s16): Likewise.
11270 (__arm_vqsubq_s16): Likewise.
11271 (__arm_vqsubq_n_s16): Likewise.
11272 (__arm_vqshlq_s16): Likewise.
11273 (__arm_vqshlq_r_s16): Likewise.
11274 (__arm_vqrshlq_s16): Likewise.
11275 (__arm_vqrshlq_n_s16): Likewise.
11276 (__arm_vqrdmulhq_s16): Likewise.
11277 (__arm_vqrdmulhq_n_s16): Likewise.
11278 (__arm_vqdmulhq_s16): Likewise.
11279 (__arm_vqdmulhq_n_s16): Likewise.
11280 (__arm_vqaddq_s16): Likewise.
11281 (__arm_vqaddq_n_s16): Likewise.
11282 (__arm_vorrq_s16): Likewise.
11283 (__arm_vornq_s16): Likewise.
11284 (__arm_vmulq_s16): Likewise.
11285 (__arm_vmulq_n_s16): Likewise.
11286 (__arm_vmulltq_int_s16): Likewise.
11287 (__arm_vmullbq_int_s16): Likewise.
11288 (__arm_vmulhq_s16): Likewise.
11289 (__arm_vmlsdavxq_s16): Likewise.
11290 (__arm_vmlsdavq_s16): Likewise.
11291 (__arm_vmladavxq_s16): Likewise.
11292 (__arm_vmladavq_s16): Likewise.
11293 (__arm_vminvq_s16): Likewise.
11294 (__arm_vminq_s16): Likewise.
11295 (__arm_vmaxvq_s16): Likewise.
11296 (__arm_vmaxq_s16): Likewise.
11297 (__arm_vhsubq_s16): Likewise.
11298 (__arm_vhsubq_n_s16): Likewise.
11299 (__arm_vhcaddq_rot90_s16): Likewise.
11300 (__arm_vhcaddq_rot270_s16): Likewise.
11301 (__arm_vhaddq_s16): Likewise.
11302 (__arm_vhaddq_n_s16): Likewise.
11303 (__arm_veorq_s16): Likewise.
11304 (__arm_vcaddq_rot90_s16): Likewise.
11305 (__arm_vcaddq_rot270_s16): Likewise.
11306 (__arm_vbrsrq_n_s16): Likewise.
11307 (__arm_vbicq_s16): Likewise.
11308 (__arm_vandq_s16): Likewise.
11309 (__arm_vaddvaq_s16): Likewise.
11310 (__arm_vaddq_n_s16): Likewise.
11311 (__arm_vabdq_s16): Likewise.
11312 (__arm_vshlq_n_s16): Likewise.
11313 (__arm_vrshrq_n_s16): Likewise.
11314 (__arm_vqshlq_n_s16): Likewise.
11315 (__arm_vsubq_u32): Likewise.
11316 (__arm_vsubq_n_u32): Likewise.
11317 (__arm_vrmulhq_u32): Likewise.
11318 (__arm_vrhaddq_u32): Likewise.
11319 (__arm_vqsubq_u32): Likewise.
11320 (__arm_vqsubq_n_u32): Likewise.
11321 (__arm_vqaddq_u32): Likewise.
11322 (__arm_vqaddq_n_u32): Likewise.
11323 (__arm_vorrq_u32): Likewise.
11324 (__arm_vornq_u32): Likewise.
11325 (__arm_vmulq_u32): Likewise.
11326 (__arm_vmulq_n_u32): Likewise.
11327 (__arm_vmulltq_int_u32): Likewise.
11328 (__arm_vmullbq_int_u32): Likewise.
11329 (__arm_vmulhq_u32): Likewise.
11330 (__arm_vmladavq_u32): Likewise.
11331 (__arm_vminvq_u32): Likewise.
11332 (__arm_vminq_u32): Likewise.
11333 (__arm_vmaxvq_u32): Likewise.
11334 (__arm_vmaxq_u32): Likewise.
11335 (__arm_vhsubq_u32): Likewise.
11336 (__arm_vhsubq_n_u32): Likewise.
11337 (__arm_vhaddq_u32): Likewise.
11338 (__arm_vhaddq_n_u32): Likewise.
11339 (__arm_veorq_u32): Likewise.
11340 (__arm_vcmpneq_n_u32): Likewise.
11341 (__arm_vcmphiq_u32): Likewise.
11342 (__arm_vcmphiq_n_u32): Likewise.
11343 (__arm_vcmpeqq_u32): Likewise.
11344 (__arm_vcmpeqq_n_u32): Likewise.
11345 (__arm_vcmpcsq_u32): Likewise.
11346 (__arm_vcmpcsq_n_u32): Likewise.
11347 (__arm_vcaddq_rot90_u32): Likewise.
11348 (__arm_vcaddq_rot270_u32): Likewise.
11349 (__arm_vbicq_u32): Likewise.
11350 (__arm_vandq_u32): Likewise.
11351 (__arm_vaddvq_p_u32): Likewise.
11352 (__arm_vaddvaq_u32): Likewise.
11353 (__arm_vaddq_n_u32): Likewise.
11354 (__arm_vabdq_u32): Likewise.
11355 (__arm_vshlq_r_u32): Likewise.
11356 (__arm_vrshlq_u32): Likewise.
11357 (__arm_vrshlq_n_u32): Likewise.
11358 (__arm_vqshlq_u32): Likewise.
11359 (__arm_vqshlq_r_u32): Likewise.
11360 (__arm_vqrshlq_u32): Likewise.
11361 (__arm_vqrshlq_n_u32): Likewise.
11362 (__arm_vminavq_s32): Likewise.
11363 (__arm_vminaq_s32): Likewise.
11364 (__arm_vmaxavq_s32): Likewise.
11365 (__arm_vmaxaq_s32): Likewise.
11366 (__arm_vbrsrq_n_u32): Likewise.
11367 (__arm_vshlq_n_u32): Likewise.
11368 (__arm_vrshrq_n_u32): Likewise.
11369 (__arm_vqshlq_n_u32): Likewise.
11370 (__arm_vcmpneq_n_s32): Likewise.
11371 (__arm_vcmpltq_s32): Likewise.
11372 (__arm_vcmpltq_n_s32): Likewise.
11373 (__arm_vcmpleq_s32): Likewise.
11374 (__arm_vcmpleq_n_s32): Likewise.
11375 (__arm_vcmpgtq_s32): Likewise.
11376 (__arm_vcmpgtq_n_s32): Likewise.
11377 (__arm_vcmpgeq_s32): Likewise.
11378 (__arm_vcmpgeq_n_s32): Likewise.
11379 (__arm_vcmpeqq_s32): Likewise.
11380 (__arm_vcmpeqq_n_s32): Likewise.
11381 (__arm_vqshluq_n_s32): Likewise.
11382 (__arm_vaddvq_p_s32): Likewise.
11383 (__arm_vsubq_s32): Likewise.
11384 (__arm_vsubq_n_s32): Likewise.
11385 (__arm_vshlq_r_s32): Likewise.
11386 (__arm_vrshlq_s32): Likewise.
11387 (__arm_vrshlq_n_s32): Likewise.
11388 (__arm_vrmulhq_s32): Likewise.
11389 (__arm_vrhaddq_s32): Likewise.
11390 (__arm_vqsubq_s32): Likewise.
11391 (__arm_vqsubq_n_s32): Likewise.
11392 (__arm_vqshlq_s32): Likewise.
11393 (__arm_vqshlq_r_s32): Likewise.
11394 (__arm_vqrshlq_s32): Likewise.
11395 (__arm_vqrshlq_n_s32): Likewise.
11396 (__arm_vqrdmulhq_s32): Likewise.
11397 (__arm_vqrdmulhq_n_s32): Likewise.
11398 (__arm_vqdmulhq_s32): Likewise.
11399 (__arm_vqdmulhq_n_s32): Likewise.
11400 (__arm_vqaddq_s32): Likewise.
11401 (__arm_vqaddq_n_s32): Likewise.
11402 (__arm_vorrq_s32): Likewise.
11403 (__arm_vornq_s32): Likewise.
11404 (__arm_vmulq_s32): Likewise.
11405 (__arm_vmulq_n_s32): Likewise.
11406 (__arm_vmulltq_int_s32): Likewise.
11407 (__arm_vmullbq_int_s32): Likewise.
11408 (__arm_vmulhq_s32): Likewise.
11409 (__arm_vmlsdavxq_s32): Likewise.
11410 (__arm_vmlsdavq_s32): Likewise.
11411 (__arm_vmladavxq_s32): Likewise.
11412 (__arm_vmladavq_s32): Likewise.
11413 (__arm_vminvq_s32): Likewise.
11414 (__arm_vminq_s32): Likewise.
11415 (__arm_vmaxvq_s32): Likewise.
11416 (__arm_vmaxq_s32): Likewise.
11417 (__arm_vhsubq_s32): Likewise.
11418 (__arm_vhsubq_n_s32): Likewise.
11419 (__arm_vhcaddq_rot90_s32): Likewise.
11420 (__arm_vhcaddq_rot270_s32): Likewise.
11421 (__arm_vhaddq_s32): Likewise.
11422 (__arm_vhaddq_n_s32): Likewise.
11423 (__arm_veorq_s32): Likewise.
11424 (__arm_vcaddq_rot90_s32): Likewise.
11425 (__arm_vcaddq_rot270_s32): Likewise.
11426 (__arm_vbrsrq_n_s32): Likewise.
11427 (__arm_vbicq_s32): Likewise.
11428 (__arm_vandq_s32): Likewise.
11429 (__arm_vaddvaq_s32): Likewise.
11430 (__arm_vaddq_n_s32): Likewise.
11431 (__arm_vabdq_s32): Likewise.
11432 (__arm_vshlq_n_s32): Likewise.
11433 (__arm_vrshrq_n_s32): Likewise.
11434 (__arm_vqshlq_n_s32): Likewise.
11435 (vsubq): Define polymorphic variant.
11436 (vsubq_n): Likewise.
11437 (vshlq_r): Likewise.
11438 (vrshlq_n): Likewise.
11439 (vrshlq): Likewise.
11440 (vrmulhq): Likewise.
11441 (vrhaddq): Likewise.
11442 (vqsubq_n): Likewise.
11443 (vqsubq): Likewise.
11444 (vqshlq): Likewise.
11445 (vqshlq_r): Likewise.
11446 (vqshluq): Likewise.
11447 (vrshrq_n): Likewise.
11448 (vshlq_n): Likewise.
11449 (vqshluq_n): Likewise.
11450 (vqshlq_n): Likewise.
11451 (vqrshlq_n): Likewise.
11452 (vqrshlq): Likewise.
11453 (vqrdmulhq_n): Likewise.
11454 (vqrdmulhq): Likewise.
11455 (vqdmulhq_n): Likewise.
11456 (vqdmulhq): Likewise.
11457 (vqaddq_n): Likewise.
11458 (vqaddq): Likewise.
11459 (vorrq_n): Likewise.
11462 (vmulq_n): Likewise.
11464 (vmulltq_int): Likewise.
11465 (vmullbq_int): Likewise.
11466 (vmulhq): Likewise.
11468 (vminaq): Likewise.
11470 (vmaxaq): Likewise.
11471 (vhsubq_n): Likewise.
11472 (vhsubq): Likewise.
11473 (vhcaddq_rot90): Likewise.
11474 (vhcaddq_rot270): Likewise.
11475 (vhaddq_n): Likewise.
11476 (vhaddq): Likewise.
11478 (vcaddq_rot90): Likewise.
11479 (vcaddq_rot270): Likewise.
11480 (vbrsrq_n): Likewise.
11481 (vbicq_n): Likewise.
11484 (vaddq_n): Likewise.
11487 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_IMM): Use it.
11488 (BINOP_NONE_NONE_NONE): Likewise.
11489 (BINOP_NONE_NONE_UNONE): Likewise.
11490 (BINOP_UNONE_NONE_IMM): Likewise.
11491 (BINOP_UNONE_NONE_NONE): Likewise.
11492 (BINOP_UNONE_UNONE_IMM): Likewise.
11493 (BINOP_UNONE_UNONE_NONE): Likewise.
11494 (BINOP_UNONE_UNONE_UNONE): Likewise.
11495 * config/arm/constraints.md (Ra): Define constraint to check constant is
11496 in the range of 0 to 7.
11497 (Rg): Define constriant to check the constant is one among 1, 2, 4
11499 * config/arm/mve.md (mve_vabdq_<supf>): Define RTL pattern.
11500 (mve_vaddq_n_<supf>): Likewise.
11501 (mve_vaddvaq_<supf>): Likewise.
11502 (mve_vaddvq_p_<supf>): Likewise.
11503 (mve_vandq_<supf>): Likewise.
11504 (mve_vbicq_<supf>): Likewise.
11505 (mve_vbrsrq_n_<supf>): Likewise.
11506 (mve_vcaddq_rot270_<supf>): Likewise.
11507 (mve_vcaddq_rot90_<supf>): Likewise.
11508 (mve_vcmpcsq_n_u): Likewise.
11509 (mve_vcmpcsq_u): Likewise.
11510 (mve_vcmpeqq_n_<supf>): Likewise.
11511 (mve_vcmpeqq_<supf>): Likewise.
11512 (mve_vcmpgeq_n_s): Likewise.
11513 (mve_vcmpgeq_s): Likewise.
11514 (mve_vcmpgtq_n_s): Likewise.
11515 (mve_vcmpgtq_s): Likewise.
11516 (mve_vcmphiq_n_u): Likewise.
11517 (mve_vcmphiq_u): Likewise.
11518 (mve_vcmpleq_n_s): Likewise.
11519 (mve_vcmpleq_s): Likewise.
11520 (mve_vcmpltq_n_s): Likewise.
11521 (mve_vcmpltq_s): Likewise.
11522 (mve_vcmpneq_n_<supf>): Likewise.
11523 (mve_vddupq_n_u): Likewise.
11524 (mve_veorq_<supf>): Likewise.
11525 (mve_vhaddq_n_<supf>): Likewise.
11526 (mve_vhaddq_<supf>): Likewise.
11527 (mve_vhcaddq_rot270_s): Likewise.
11528 (mve_vhcaddq_rot90_s): Likewise.
11529 (mve_vhsubq_n_<supf>): Likewise.
11530 (mve_vhsubq_<supf>): Likewise.
11531 (mve_vidupq_n_u): Likewise.
11532 (mve_vmaxaq_s): Likewise.
11533 (mve_vmaxavq_s): Likewise.
11534 (mve_vmaxq_<supf>): Likewise.
11535 (mve_vmaxvq_<supf>): Likewise.
11536 (mve_vminaq_s): Likewise.
11537 (mve_vminavq_s): Likewise.
11538 (mve_vminq_<supf>): Likewise.
11539 (mve_vminvq_<supf>): Likewise.
11540 (mve_vmladavq_<supf>): Likewise.
11541 (mve_vmladavxq_s): Likewise.
11542 (mve_vmlsdavq_s): Likewise.
11543 (mve_vmlsdavxq_s): Likewise.
11544 (mve_vmulhq_<supf>): Likewise.
11545 (mve_vmullbq_int_<supf>): Likewise.
11546 (mve_vmulltq_int_<supf>): Likewise.
11547 (mve_vmulq_n_<supf>): Likewise.
11548 (mve_vmulq_<supf>): Likewise.
11549 (mve_vornq_<supf>): Likewise.
11550 (mve_vorrq_<supf>): Likewise.
11551 (mve_vqaddq_n_<supf>): Likewise.
11552 (mve_vqaddq_<supf>): Likewise.
11553 (mve_vqdmulhq_n_s): Likewise.
11554 (mve_vqdmulhq_s): Likewise.
11555 (mve_vqrdmulhq_n_s): Likewise.
11556 (mve_vqrdmulhq_s): Likewise.
11557 (mve_vqrshlq_n_<supf>): Likewise.
11558 (mve_vqrshlq_<supf>): Likewise.
11559 (mve_vqshlq_n_<supf>): Likewise.
11560 (mve_vqshlq_r_<supf>): Likewise.
11561 (mve_vqshlq_<supf>): Likewise.
11562 (mve_vqshluq_n_s): Likewise.
11563 (mve_vqsubq_n_<supf>): Likewise.
11564 (mve_vqsubq_<supf>): Likewise.
11565 (mve_vrhaddq_<supf>): Likewise.
11566 (mve_vrmulhq_<supf>): Likewise.
11567 (mve_vrshlq_n_<supf>): Likewise.
11568 (mve_vrshlq_<supf>): Likewise.
11569 (mve_vrshrq_n_<supf>): Likewise.
11570 (mve_vshlq_n_<supf>): Likewise.
11571 (mve_vshlq_r_<supf>): Likewise.
11572 (mve_vsubq_n_<supf>): Likewise.
11573 (mve_vsubq_<supf>): Likewise.
11574 * config/arm/predicates.md (mve_imm_7): Define predicate to check
11575 the matching constraint Ra.
11576 (mve_imm_selective_upto_8): Define predicate to check the matching
11579 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11580 Mihail Ionescu <mihail.ionescu@arm.com>
11581 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11583 * config/arm/arm-builtins.c (BINOP_NONE_NONE_UNONE_QUALIFIERS): Define
11584 qualifier for binary operands.
11585 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11586 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11587 * config/arm/arm_mve.h (vaddlvq_p_s32): Define macro.
11588 (vaddlvq_p_u32): Likewise.
11589 (vcmpneq_s8): Likewise.
11590 (vcmpneq_s16): Likewise.
11591 (vcmpneq_s32): Likewise.
11592 (vcmpneq_u8): Likewise.
11593 (vcmpneq_u16): Likewise.
11594 (vcmpneq_u32): Likewise.
11595 (vshlq_s8): Likewise.
11596 (vshlq_s16): Likewise.
11597 (vshlq_s32): Likewise.
11598 (vshlq_u8): Likewise.
11599 (vshlq_u16): Likewise.
11600 (vshlq_u32): Likewise.
11601 (__arm_vaddlvq_p_s32): Define intrinsic.
11602 (__arm_vaddlvq_p_u32): Likewise.
11603 (__arm_vcmpneq_s8): Likewise.
11604 (__arm_vcmpneq_s16): Likewise.
11605 (__arm_vcmpneq_s32): Likewise.
11606 (__arm_vcmpneq_u8): Likewise.
11607 (__arm_vcmpneq_u16): Likewise.
11608 (__arm_vcmpneq_u32): Likewise.
11609 (__arm_vshlq_s8): Likewise.
11610 (__arm_vshlq_s16): Likewise.
11611 (__arm_vshlq_s32): Likewise.
11612 (__arm_vshlq_u8): Likewise.
11613 (__arm_vshlq_u16): Likewise.
11614 (__arm_vshlq_u32): Likewise.
11615 (vaddlvq_p): Define polymorphic variant.
11616 (vcmpneq): Likewise.
11618 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_UNONE_QUALIFIERS):
11620 (BINOP_UNONE_NONE_NONE_QUALIFIERS): Likewise.
11621 (BINOP_UNONE_UNONE_NONE_QUALIFIERS): Likewise.
11622 * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si): Define RTL pattern.
11623 (mve_vcmpneq_<supf><mode>): Likewise.
11624 (mve_vshlq_<supf><mode>): Likewise.
11626 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11627 Mihail Ionescu <mihail.ionescu@arm.com>
11628 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11630 * config/arm/arm-builtins.c (BINOP_UNONE_UNONE_IMM_QUALIFIERS): Define
11631 qualifier for binary operands.
11632 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11633 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11634 * config/arm/arm_mve.h (vcvtq_n_s16_f16): Define macro.
11635 (vcvtq_n_s32_f32): Likewise.
11636 (vcvtq_n_u16_f16): Likewise.
11637 (vcvtq_n_u32_f32): Likewise.
11638 (vcreateq_u8): Likewise.
11639 (vcreateq_u16): Likewise.
11640 (vcreateq_u32): Likewise.
11641 (vcreateq_u64): Likewise.
11642 (vcreateq_s8): Likewise.
11643 (vcreateq_s16): Likewise.
11644 (vcreateq_s32): Likewise.
11645 (vcreateq_s64): Likewise.
11646 (vshrq_n_s8): Likewise.
11647 (vshrq_n_s16): Likewise.
11648 (vshrq_n_s32): Likewise.
11649 (vshrq_n_u8): Likewise.
11650 (vshrq_n_u16): Likewise.
11651 (vshrq_n_u32): Likewise.
11652 (__arm_vcreateq_u8): Define intrinsic.
11653 (__arm_vcreateq_u16): Likewise.
11654 (__arm_vcreateq_u32): Likewise.
11655 (__arm_vcreateq_u64): Likewise.
11656 (__arm_vcreateq_s8): Likewise.
11657 (__arm_vcreateq_s16): Likewise.
11658 (__arm_vcreateq_s32): Likewise.
11659 (__arm_vcreateq_s64): Likewise.
11660 (__arm_vshrq_n_s8): Likewise.
11661 (__arm_vshrq_n_s16): Likewise.
11662 (__arm_vshrq_n_s32): Likewise.
11663 (__arm_vshrq_n_u8): Likewise.
11664 (__arm_vshrq_n_u16): Likewise.
11665 (__arm_vshrq_n_u32): Likewise.
11666 (__arm_vcvtq_n_s16_f16): Likewise.
11667 (__arm_vcvtq_n_s32_f32): Likewise.
11668 (__arm_vcvtq_n_u16_f16): Likewise.
11669 (__arm_vcvtq_n_u32_f32): Likewise.
11670 (vshrq_n): Define polymorphic variant.
11671 * config/arm/arm_mve_builtins.def (BINOP_UNONE_UNONE_IMM_QUALIFIERS):
11673 (BINOP_UNONE_UNONE_UNONE_QUALIFIERS): Likewise.
11674 (BINOP_UNONE_NONE_IMM_QUALIFIERS): Likewise.
11675 * config/arm/constraints.md (Rb): Define constraint to check constant is
11676 in the range of 1 to 8.
11677 (Rf): Define constraint to check constant is in the range of 1 to 32.
11678 * config/arm/mve.md (mve_vcreateq_<supf><mode>): Define RTL pattern.
11679 (mve_vshrq_n_<supf><mode>): Likewise.
11680 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
11681 * config/arm/predicates.md (mve_imm_8): Define predicate to check
11682 the matching constraint Rb.
11683 (mve_imm_32): Define predicate to check the matching constraint Rf.
11685 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11686 Mihail Ionescu <mihail.ionescu@arm.com>
11687 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11689 * config/arm/arm-builtins.c (BINOP_NONE_NONE_NONE_QUALIFIERS): Define
11690 qualifier for binary operands.
11691 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11692 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11693 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11694 * config/arm/arm_mve.h (vsubq_n_f16): Define macro.
11695 (vsubq_n_f32): Likewise.
11696 (vbrsrq_n_f16): Likewise.
11697 (vbrsrq_n_f32): Likewise.
11698 (vcvtq_n_f16_s16): Likewise.
11699 (vcvtq_n_f32_s32): Likewise.
11700 (vcvtq_n_f16_u16): Likewise.
11701 (vcvtq_n_f32_u32): Likewise.
11702 (vcreateq_f16): Likewise.
11703 (vcreateq_f32): Likewise.
11704 (__arm_vsubq_n_f16): Define intrinsic.
11705 (__arm_vsubq_n_f32): Likewise.
11706 (__arm_vbrsrq_n_f16): Likewise.
11707 (__arm_vbrsrq_n_f32): Likewise.
11708 (__arm_vcvtq_n_f16_s16): Likewise.
11709 (__arm_vcvtq_n_f32_s32): Likewise.
11710 (__arm_vcvtq_n_f16_u16): Likewise.
11711 (__arm_vcvtq_n_f32_u32): Likewise.
11712 (__arm_vcreateq_f16): Likewise.
11713 (__arm_vcreateq_f32): Likewise.
11714 (vsubq): Define polymorphic variant.
11715 (vbrsrq): Likewise.
11716 (vcvtq_n): Likewise.
11717 * config/arm/arm_mve_builtins.def (BINOP_NONE_NONE_NONE_QUALIFIERS): Use
11719 (BINOP_NONE_NONE_IMM_QUALIFIERS): Likewise.
11720 (BINOP_NONE_UNONE_IMM_QUALIFIERS): Likewise.
11721 (BINOP_NONE_UNONE_UNONE_QUALIFIERS): Likewise.
11722 * config/arm/constraints.md (Rd): Define constraint to check constant is
11723 in the range of 1 to 16.
11724 * config/arm/mve.md (mve_vsubq_n_f<mode>): Define RTL pattern.
11725 mve_vbrsrq_n_f<mode>: Likewise.
11726 mve_vcvtq_n_to_f_<supf><mode>: Likewise.
11727 mve_vcreateq_f<mode>: Likewise.
11728 * config/arm/predicates.md (mve_imm_16): Define predicate to check
11729 the matching constraint Rd.
11731 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11732 Mihail Ionescu <mihail.ionescu@arm.com>
11733 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11735 * config/arm/arm-builtins.c (hi_UP): Define mode.
11736 * config/arm/arm.h (IS_VPR_REGNUM): Move.
11737 * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
11738 (APSRQ_REGNUM): Modify.
11739 (APSRGE_REGNUM): Modify.
11740 * config/arm/arm_mve.h (vctp16q): Define macro.
11741 (vctp32q): Likewise.
11742 (vctp64q): Likewise.
11743 (vctp8q): Likewise.
11745 (__arm_vctp16q): Define intrinsic.
11746 (__arm_vctp32q): Likewise.
11747 (__arm_vctp64q): Likewise.
11748 (__arm_vctp8q): Likewise.
11749 (__arm_vpnot): Likewise.
11750 * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
11752 * config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
11753 (mve_vpnothi): Likewise.
11755 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
11756 Mihail Ionescu <mihail.ionescu@arm.com>
11757 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
11759 * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS.
11760 * config/arm/arm_mve.h (vdupq_n_s8): Define macro.
11761 (vdupq_n_s16): Likewise.
11762 (vdupq_n_s32): Likewise.
11763 (vabsq_s8): Likewise.
11764 (vabsq_s16): Likewise.
11765 (vabsq_s32): Likewise.
11766 (vclsq_s8): Likewise.
11767 (vclsq_s16): Likewise.
11768 (vclsq_s32): Likewise.
11769 (vclzq_s8): Likewise.
11770 (vclzq_s16): Likewise.
11771 (vclzq_s32): Likewise.
11772 (vnegq_s8): Likewise.
11773 (vnegq_s16): Likewise.
11774 (vnegq_s32): Likewise.
11775 (vaddlvq_s32): Likewise.
11776 (vaddvq_s8): Likewise.
11777 (vaddvq_s16): Likewise.
11778 (vaddvq_s32): Likewise.
11779 (vmovlbq_s8): Likewise.
11780 (vmovlbq_s16): Likewise.
11781 (vmovltq_s8): Likewise.
11782 (vmovltq_s16): Likewise.
11783 (vmvnq_s8): Likewise.
11784 (vmvnq_s16): Likewise.
11785 (vmvnq_s32): Likewise.
11786 (vrev16q_s8): Likewise.
11787 (vrev32q_s8): Likewise.
11788 (vrev32q_s16): Likewise.
11789 (vqabsq_s8): Likewise.
11790 (vqabsq_s16): Likewise.
11791 (vqabsq_s32): Likewise.
11792 (vqnegq_s8): Likewise.
11793 (vqnegq_s16): Likewise.
11794 (vqnegq_s32): Likewise.
11795 (vcvtaq_s16_f16): Likewise.
11796 (vcvtaq_s32_f32): Likewise.
11797 (vcvtnq_s16_f16): Likewise.
11798 (vcvtnq_s32_f32): Likewise.
11799 (vcvtpq_s16_f16): Likewise.
11800 (vcvtpq_s32_f32): Likewise.
11801 (vcvtmq_s16_f16): Likewise.
11802 (vcvtmq_s32_f32): Likewise.
11803 (vmvnq_u8): Likewise.
11804 (vmvnq_u16): Likewise.
11805 (vmvnq_u32): Likewise.
11806 (vdupq_n_u8): Likewise.
11807 (vdupq_n_u16): Likewise.
11808 (vdupq_n_u32): Likewise.
11809 (vclzq_u8): Likewise.
11810 (vclzq_u16): Likewise.
11811 (vclzq_u32): Likewise.
11812 (vaddvq_u8): Likewise.
11813 (vaddvq_u16): Likewise.
11814 (vaddvq_u32): Likewise.
11815 (vrev32q_u8): Likewise.
11816 (vrev32q_u16): Likewise.
11817 (vmovltq_u8): Likewise.
11818 (vmovltq_u16): Likewise.
11819 (vmovlbq_u8): Likewise.
11820 (vmovlbq_u16): Likewise.
11821 (vrev16q_u8): Likewise.
11822 (vaddlvq_u32): Likewise.
11823 (vcvtpq_u16_f16): Likewise.
11824 (vcvtpq_u32_f32): Likewise.
11825 (vcvtnq_u16_f16): Likewise.
11826 (vcvtmq_u16_f16): Likewise.
11827 (vcvtmq_u32_f32): Likewise.
11828 (vcvtaq_u16_f16): Likewise.
11829 (vcvtaq_u32_f32): Likewise.
11830 (__arm_vdupq_n_s8): Define intrinsic.
11831 (__arm_vdupq_n_s16): Likewise.
11832 (__arm_vdupq_n_s32): Likewise.
11833 (__arm_vabsq_s8): Likewise.
11834 (__arm_vabsq_s16): Likewise.
11835 (__arm_vabsq_s32): Likewise.
11836 (__arm_vclsq_s8): Likewise.
11837 (__arm_vclsq_s16): Likewise.
11838 (__arm_vclsq_s32): Likewise.
11839 (__arm_vclzq_s8): Likewise.
11840 (__arm_vclzq_s16): Likewise.
11841 (__arm_vclzq_s32): Likewise.
11842 (__arm_vnegq_s8): Likewise.
11843 (__arm_vnegq_s16): Likewise.
11844 (__arm_vnegq_s32): Likewise.
11845 (__arm_vaddlvq_s32): Likewise.
11846 (__arm_vaddvq_s8): Likewise.
11847 (__arm_vaddvq_s16): Likewise.
11848 (__arm_vaddvq_s32): Likewise.
11849 (__arm_vmovlbq_s8): Likewise.
11850 (__arm_vmovlbq_s16): Likewise.
11851 (__arm_vmovltq_s8): Likewise.
11852 (__arm_vmovltq_s16): Likewise.
11853 (__arm_vmvnq_s8): Likewise.
11854 (__arm_vmvnq_s16): Likewise.
11855 (__arm_vmvnq_s32): Likewise.
11856 (__arm_vrev16q_s8): Likewise.
11857 (__arm_vrev32q_s8): Likewise.
11858 (__arm_vrev32q_s16): Likewise.
11859 (__arm_vqabsq_s8): Likewise.
11860 (__arm_vqabsq_s16): Likewise.
11861 (__arm_vqabsq_s32): Likewise.
11862 (__arm_vqnegq_s8): Likewise.
11863 (__arm_vqnegq_s16): Likewise.
11864 (__arm_vqnegq_s32): Likewise.
11865 (__arm_vmvnq_u8): Likewise.
11866 (__arm_vmvnq_u16): Likewise.
11867 (__arm_vmvnq_u32): Likewise.
11868 (__arm_vdupq_n_u8): Likewise.
11869 (__arm_vdupq_n_u16): Likewise.
11870 (__arm_vdupq_n_u32): Likewise.
11871 (__arm_vclzq_u8): Likewise.
11872 (__arm_vclzq_u16): Likewise.
11873 (__arm_vclzq_u32): Likewise.
11874 (__arm_vaddvq_u8): Likewise.
11875 (__arm_vaddvq_u16): Likewise.
11876 (__arm_vaddvq_u32): Likewise.
11877 (__arm_vrev32q_u8): Likewise.
11878 (__arm_vrev32q_u16): Likewise.
11879 (__arm_vmovltq_u8): Likewise.
11880 (__arm_vmovltq_u16): Likewise.
11881 (__arm_vmovlbq_u8): Likewise.
11882 (__arm_vmovlbq_u16): Likewise.
11883 (__arm_vrev16q_u8): Likewise.
11884 (__arm_vaddlvq_u32): Likewise.
11885 (__arm_vcvtpq_u16_f16): Likewise.
11886 (__arm_vcvtpq_u32_f32): Likewise.
11887 (__arm_vcvtnq_u16_f16): Likewise.
11888 (__arm_vcvtmq_u16_f16): Likewise.
11889 (__arm_vcvtmq_u32_f32): Likewise.
11890 (__arm_vcvtaq_u16_f16): Likewise.
11891 (__arm_vcvtaq_u32_f32): Likewise.
11892 (__arm_vcvtaq_s16_f16): Likewise.
11893 (__arm_vcvtaq_s32_f32): Likewise.
11894 (__arm_vcvtnq_s16_f16): Likewise.
11895 (__arm_vcvtnq_s32_f32): Likewise.
11896 (__arm_vcvtpq_s16_f16): Likewise.
11897 (__arm_vcvtpq_s32_f32): Likewise.
11898 (__arm_vcvtmq_s16_f16): Likewise.
11899 (__arm_vcvtmq_s32_f32): Likewise.
11900 (vdupq_n): Define polymorphic variant.
11905 (vaddlvq): Likewise.
11906 (vaddvq): Likewise.
11907 (vmovlbq): Likewise.
11908 (vmovltq): Likewise.
11910 (vrev16q): Likewise.
11911 (vrev32q): Likewise.
11912 (vqabsq): Likewise.
11913 (vqnegq): Likewise.
11914 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
11915 (UNOP_SNONE_NONE): Likewise.
11916 (UNOP_UNONE_UNONE): Likewise.
11917 (UNOP_UNONE_NONE): Likewise.
11918 * config/arm/constraints.md (e): Define new constriant to allow only
11920 * config/arm/mve.md (mve_vqabsq_s<mode>): Define RTL pattern.
11921 (mve_vnegq_s<mode>): Likewise.
11922 (mve_vmvnq_<supf><mode>): Likewise.
11923 (mve_vdupq_n_<supf><mode>): Likewise.
11924 (mve_vclzq_<supf><mode>): Likewise.
11925 (mve_vclsq_s<mode>): Likewise.
11926 (mve_vaddvq_<supf><mode>): Likewise.
11927 (mve_vabsq_s<mode>): Likewise.
11928 (mve_vrev32q_<supf><mode>): Likewise.
11929 (mve_vmovltq_<supf><mode>): Likewise.
11930 (mve_vmovlbq_<supf><mode>): Likewise.
11931 (mve_vcvtpq_<supf><mode>): Likewise.
11932 (mve_vcvtnq_<supf><mode>): Likewise.
11933 (mve_vcvtmq_<supf><mode>): Likewise.
11934 (mve_vcvtaq_<supf><mode>): Likewise.
11935 (mve_vrev16q_<supf>v16qi): Likewise.
11936 (mve_vaddlvq_<supf>v4si): Likewise.
11938 2020-03-17 Jakub Jelinek <jakub@redhat.com>
11940 * lra-spills.c (remove_pseudos): Fix up duplicated word issue in
11942 * tree-sra.c (create_access_replacement): Fix up duplicated word issue
11944 * read-rtl-function.c (find_param_by_name,
11945 function_reader::parse_enum_value, function_reader::get_insn_by_uid):
11947 * spellcheck.c (get_edit_distance_cutoff): Likewise.
11948 * tree-data-ref.c (create_ifn_alias_checks): Likewise.
11949 * tree.def (SWITCH_EXPR): Likewise.
11950 * selftest.c (assert_str_contains): Likewise.
11951 * ipa-param-manipulation.h (class ipa_param_body_adjustments):
11953 * tree-ssa-math-opts.c (convert_expand_mult_copysign): Likewise.
11954 * tree-ssa-loop-split.c (find_vdef_in_loop): Likewise.
11955 * langhooks.h (struct lang_hooks_for_decls): Likewise.
11956 * ipa-prop.h (struct ipa_param_descriptor): Likewise.
11957 * tree-ssa-strlen.c (handle_builtin_string_cmp, handle_store):
11959 * tree-ssa-dom.c (simplify_stmt_for_jump_threading): Likewise.
11960 * tree-ssa-reassoc.c (reassociate_bb): Likewise.
11961 * tree.c (component_ref_size): Likewise.
11962 * hsa-common.c (hsa_init_compilation_unit_data): Likewise.
11963 * gimple-ssa-sprintf.c (get_string_length, format_string,
11964 format_directive): Likewise.
11965 * omp-grid.c (grid_process_kernel_body_copy): Likewise.
11966 * input.c (string_concat_db::get_string_concatenation,
11967 test_lexer_string_locations_ucn4): Likewise.
11968 * cfgexpand.c (pass_expand::execute): Likewise.
11969 * gimple-ssa-warn-restrict.c (builtin_memref::offset_out_of_bounds,
11970 maybe_diag_overlap): Likewise.
11971 * rtl.c (RTX_CODE_HWINT_P_1): Likewise.
11972 * shrink-wrap.c (spread_components): Likewise.
11973 * tree-ssa-dse.c (initialize_ao_ref_for_dse, valid_ao_ref_for_dse):
11975 * tree-call-cdce.c (shrink_wrap_one_built_in_call_with_conds):
11977 * dwarf2out.c (dwarf2out_early_finish): Likewise.
11978 * gimple-ssa-store-merging.c: Likewise.
11979 * ira-costs.c (record_operand_costs): Likewise.
11980 * tree-vect-loop.c (vectorizable_reduction): Likewise.
11981 * target.def (dispatch): Likewise.
11982 (validate_dims, gen_ccmp_first): Fix up duplicated word issue
11983 in documentation text.
11984 * doc/tm.texi: Regenerated.
11985 * config/i386/x86-tune.def (X86_TUNE_PARTIAL_FLAG_REG_STALL): Fix up
11986 duplicated word issue in a comment.
11987 * config/i386/i386.c (ix86_test_loading_unspec): Likewise.
11988 * config/i386/i386-features.c (remove_partial_avx_dependency):
11990 * config/msp430/msp430.c (msp430_select_section): Likewise.
11991 * config/gcn/gcn-run.c (load_image): Likewise.
11992 * config/aarch64/aarch64-sve.md (sve_ld1r<mode>): Likewise.
11993 * config/aarch64/aarch64.c (aarch64_gen_adjusted_ldpstp): Likewise.
11994 * config/aarch64/falkor-tag-collision-avoidance.c
11995 (single_dest_per_chain): Likewise.
11996 * config/nvptx/nvptx.c (nvptx_record_fndecl): Likewise.
11997 * config/fr30/fr30.c (fr30_arg_partial_bytes): Likewise.
11998 * config/rs6000/rs6000-string.c (expand_cmp_vec_sequence): Likewise.
11999 * config/rs6000/rs6000-p8swap.c (replace_swapped_load_constant):
12001 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Likewise.
12002 * config/rs6000/rs6000.c (rs6000_option_override_internal): Likewise.
12003 * config/rs6000/rs6000-logue.c
12004 (rs6000_emit_probe_stack_range_stack_clash): Likewise.
12005 * config/nds32/nds32-md-auxiliary.c (nds32_split_ashiftdi3): Likewise.
12006 Fix various other issues in the comment.
12008 2020-03-17 Mihail Ionescu <mihail.ionescu@arm.com>
12010 * config/arm/t-rmprofile: create new multilib for
12011 armv8.1-m.main+mve hard float and reuse v8-m.main ones for
12014 2020-03-17 Jakub Jelinek <jakub@redhat.com>
12016 PR tree-optimization/94015
12017 * tree-ssa-strlen.c (count_nonzero_bytes): Split portions of the
12018 function where EXP is address of the bytes being stored rather than
12019 the bytes themselves into count_nonzero_bytes_addr. Punt on zero
12020 sized MEM_REF. Use VAR_P macro and handle CONST_DECL like VAR_DECLs.
12021 Use ctor_for_folding instead of looking at DECL_INITIAL. Punt before
12022 calling native_encode_expr if host or target doesn't have 8-bit
12023 chars. Formatting fixes.
12024 (count_nonzero_bytes_addr): New function.
12026 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
12027 Mihail Ionescu <mihail.ionescu@arm.com>
12028 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12030 * config/arm/arm-builtins.c (UNOP_SNONE_SNONE_QUALIFIERS): Define.
12031 (UNOP_SNONE_NONE_QUALIFIERS): Likewise.
12032 (UNOP_SNONE_IMM_QUALIFIERS): Likewise.
12033 (UNOP_UNONE_NONE_QUALIFIERS): Likewise.
12034 (UNOP_UNONE_UNONE_QUALIFIERS): Likewise.
12035 (UNOP_UNONE_IMM_QUALIFIERS): Likewise.
12036 * config/arm/arm_mve.h (vmvnq_n_s16): Define macro.
12037 (vmvnq_n_s32): Likewise.
12038 (vrev64q_s8): Likewise.
12039 (vrev64q_s16): Likewise.
12040 (vrev64q_s32): Likewise.
12041 (vcvtq_s16_f16): Likewise.
12042 (vcvtq_s32_f32): Likewise.
12043 (vrev64q_u8): Likewise.
12044 (vrev64q_u16): Likewise.
12045 (vrev64q_u32): Likewise.
12046 (vmvnq_n_u16): Likewise.
12047 (vmvnq_n_u32): Likewise.
12048 (vcvtq_u16_f16): Likewise.
12049 (vcvtq_u32_f32): Likewise.
12050 (__arm_vmvnq_n_s16): Define intrinsic.
12051 (__arm_vmvnq_n_s32): Likewise.
12052 (__arm_vrev64q_s8): Likewise.
12053 (__arm_vrev64q_s16): Likewise.
12054 (__arm_vrev64q_s32): Likewise.
12055 (__arm_vrev64q_u8): Likewise.
12056 (__arm_vrev64q_u16): Likewise.
12057 (__arm_vrev64q_u32): Likewise.
12058 (__arm_vmvnq_n_u16): Likewise.
12059 (__arm_vmvnq_n_u32): Likewise.
12060 (__arm_vcvtq_s16_f16): Likewise.
12061 (__arm_vcvtq_s32_f32): Likewise.
12062 (__arm_vcvtq_u16_f16): Likewise.
12063 (__arm_vcvtq_u32_f32): Likewise.
12064 (vrev64q): Define polymorphic variant.
12065 * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it.
12066 (UNOP_SNONE_NONE): Likewise.
12067 (UNOP_SNONE_IMM): Likewise.
12068 (UNOP_UNONE_UNONE): Likewise.
12069 (UNOP_UNONE_NONE): Likewise.
12070 (UNOP_UNONE_IMM): Likewise.
12071 * config/arm/mve.md (mve_vrev64q_<supf><mode>): Define RTL pattern.
12072 (mve_vcvtq_from_f_<supf><mode>): Likewise.
12073 (mve_vmvnq_n_<supf><mode>): Likewise.
12075 2020-03-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
12076 Mihail Ionescu <mihail.ionescu@arm.com>
12077 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12079 * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro.
12080 (UNOP_NONE_SNONE_QUALIFIERS): Likewise.
12081 (UNOP_NONE_UNONE_QUALIFIERS): Likewise.
12082 * config/arm/arm_mve.h (vrndxq_f16): Define macro.
12083 (vrndxq_f32): Likewise.
12084 (vrndq_f16) Likewise.
12085 (vrndq_f32): Likewise.
12086 (vrndpq_f16): Likewise.
12087 (vrndpq_f32): Likewise.
12088 (vrndnq_f16): Likewise.
12089 (vrndnq_f32): Likewise.
12090 (vrndmq_f16): Likewise.
12091 (vrndmq_f32): Likewise.
12092 (vrndaq_f16): Likewise.
12093 (vrndaq_f32): Likewise.
12094 (vrev64q_f16): Likewise.
12095 (vrev64q_f32): Likewise.
12096 (vnegq_f16): Likewise.
12097 (vnegq_f32): Likewise.
12098 (vdupq_n_f16): Likewise.
12099 (vdupq_n_f32): Likewise.
12100 (vabsq_f16): Likewise.
12101 (vabsq_f32): Likewise.
12102 (vrev32q_f16): Likewise.
12103 (vcvttq_f32_f16): Likewise.
12104 (vcvtbq_f32_f16): Likewise.
12105 (vcvtq_f16_s16): Likewise.
12106 (vcvtq_f32_s32): Likewise.
12107 (vcvtq_f16_u16): Likewise.
12108 (vcvtq_f32_u32): Likewise.
12109 (__arm_vrndxq_f16): Define intrinsic.
12110 (__arm_vrndxq_f32): Likewise.
12111 (__arm_vrndq_f16): Likewise.
12112 (__arm_vrndq_f32): Likewise.
12113 (__arm_vrndpq_f16): Likewise.
12114 (__arm_vrndpq_f32): Likewise.
12115 (__arm_vrndnq_f16): Likewise.
12116 (__arm_vrndnq_f32): Likewise.
12117 (__arm_vrndmq_f16): Likewise.
12118 (__arm_vrndmq_f32): Likewise.
12119 (__arm_vrndaq_f16): Likewise.
12120 (__arm_vrndaq_f32): Likewise.
12121 (__arm_vrev64q_f16): Likewise.
12122 (__arm_vrev64q_f32): Likewise.
12123 (__arm_vnegq_f16): Likewise.
12124 (__arm_vnegq_f32): Likewise.
12125 (__arm_vdupq_n_f16): Likewise.
12126 (__arm_vdupq_n_f32): Likewise.
12127 (__arm_vabsq_f16): Likewise.
12128 (__arm_vabsq_f32): Likewise.
12129 (__arm_vrev32q_f16): Likewise.
12130 (__arm_vcvttq_f32_f16): Likewise.
12131 (__arm_vcvtbq_f32_f16): Likewise.
12132 (__arm_vcvtq_f16_s16): Likewise.
12133 (__arm_vcvtq_f32_s32): Likewise.
12134 (__arm_vcvtq_f16_u16): Likewise.
12135 (__arm_vcvtq_f32_u32): Likewise.
12136 (vrndxq): Define polymorphic variants.
12138 (vrndpq): Likewise.
12139 (vrndnq): Likewise.
12140 (vrndmq): Likewise.
12141 (vrndaq): Likewise.
12142 (vrev64q): Likewise.
12145 (vrev32q): Likewise.
12146 (vcvtbq_f32): Likewise.
12147 (vcvttq_f32): Likewise.
12149 * config/arm/arm_mve_builtins.def (VAR2): Define.
12151 * config/arm/mve.md (mve_vrndxq_f<mode>): Add RTL pattern.
12152 (mve_vrndq_f<mode>): Likewise.
12153 (mve_vrndpq_f<mode>): Likewise.
12154 (mve_vrndnq_f<mode>): Likewise.
12155 (mve_vrndmq_f<mode>): Likewise.
12156 (mve_vrndaq_f<mode>): Likewise.
12157 (mve_vrev64q_f<mode>): Likewise.
12158 (mve_vnegq_f<mode>): Likewise.
12159 (mve_vdupq_n_f<mode>): Likewise.
12160 (mve_vabsq_f<mode>): Likewise.
12161 (mve_vrev32q_fv8hf): Likewise.
12162 (mve_vcvttq_f32_f16v4sf): Likewise.
12163 (mve_vcvtbq_f32_f16v4sf): Likewise.
12164 (mve_vcvtq_to_f_<supf><mode>): Likewise.
12166 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12167 Mihail Ionescu <mihail.ionescu@arm.com>
12168 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12170 * config/arm/arm-builtins.c (CF): Define mve_builtin_data.
12172 (ARM_BUILTIN_MVE_PATTERN_START): Define.
12173 (arm_init_mve_builtins): Define function.
12174 (arm_init_builtins): Add TARGET_HAVE_MVE check.
12175 (arm_expand_builtin_1): Check the range of fcode.
12176 (arm_expand_mve_builtin): Define function to expand MVE builtins.
12177 (arm_expand_builtin): Check the range of fcode.
12178 * config/arm/arm_mve.h (__ARM_FEATURE_MVE): Define MVE floating point
12180 (__ARM_MVE_PRESERVE_USER_NAMESPACE): Define to protect user namespace.
12181 (vst4q_s8): Define macro.
12182 (vst4q_s16): Likewise.
12183 (vst4q_s32): Likewise.
12184 (vst4q_u8): Likewise.
12185 (vst4q_u16): Likewise.
12186 (vst4q_u32): Likewise.
12187 (vst4q_f16): Likewise.
12188 (vst4q_f32): Likewise.
12189 (__arm_vst4q_s8): Define inline builtin.
12190 (__arm_vst4q_s16): Likewise.
12191 (__arm_vst4q_s32): Likewise.
12192 (__arm_vst4q_u8): Likewise.
12193 (__arm_vst4q_u16): Likewise.
12194 (__arm_vst4q_u32): Likewise.
12195 (__arm_vst4q_f16): Likewise.
12196 (__arm_vst4q_f32): Likewise.
12197 (__ARM_mve_typeid): Define macro with MVE types.
12198 (__ARM_mve_coerce): Define macro with _Generic feature.
12199 (vst4q): Define polymorphic variant for different vst4q builtins.
12200 * config/arm/arm_mve_builtins.def: New file.
12201 * config/arm/iterators.md (VSTRUCT): Modify to allow XI and OI
12203 * config/arm/mve.md (MVE_VLD_ST): Define iterator.
12204 (unspec): Define unspec.
12205 (mve_vst4q<mode>): Define RTL pattern.
12206 * config/arm/neon.md (mov<mode>): Modify expand to allow XI and OI
12208 (neon_mov<mode>): Modify RTL define_insn to allow XI and OI modes
12210 (define_split): Allow OI mode split for MVE after reload.
12211 (define_split): Allow XI mode split for MVE after reload.
12212 * config/arm/t-arm (arm.o): Add entry for arm_mve_builtins.def.
12213 (arm-builtins.o): Likewise.
12215 2020-03-17 Christophe Lyon <christophe.lyon@linaro.org>
12217 * c-typeck.c (process_init_element): Handle constructor_type with
12218 type size represented by POLY_INT_CST.
12220 2020-03-17 Jakub Jelinek <jakub@redhat.com>
12222 PR tree-optimization/94187
12223 * tree-ssa-strlen.c (count_nonzero_bytes): Punt if
12224 nchars - offset < nbytes.
12226 PR middle-end/94189
12227 * builtins.c (expand_builtin_strnlen): Do return NULL_RTX if we would
12228 emit a warning if it was enabled and don't depend on TREE_NO_WARNING
12229 for code-generation.
12231 2020-03-16 Vladimir Makarov <vmakarov@redhat.com>
12234 * lra-spills.c (remove_pseudos): Do not reuse insn alternative
12235 after changing memory subreg.
12237 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12238 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12240 * config/arm/arm.c (arm_libcall_uses_aapcs_base): Modify function to add
12241 emulator calls for dobule precision arithmetic operations for MVE.
12243 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12244 Mihail Ionescu <mihail.ionescu@arm.com>
12245 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12247 * common/config/arm/arm-common.c (arm_asm_auto_mfpu): When vfp_base
12248 feature bit is on and -mfpu=auto is passed as compiler option, do not
12249 generate error on not finding any matching fpu. Because in this case
12250 fpu is not required.
12251 * config/arm/arm-cpus.in (vfp_base): Define feature bit, this bit is
12252 enabled for MVE and also for all VFP extensions.
12253 (VFPv2): Modify fgroup to enable vfp_base feature bit when ever VFPv2
12255 (MVE): Define fgroup to enable feature bits mve, vfp_base and armv7em.
12256 (MVE_FP): Define fgroup to enable feature bits is fgroup MVE and FPv5
12257 along with feature bits mve_float.
12258 (mve): Modify add options in armv8.1-m.main arch for MVE.
12259 (mve.fp): Modify add options in armv8.1-m.main arch for MVE with
12261 * config/arm/arm.c (use_return_insn): Replace the
12262 check with TARGET_VFP_BASE.
12263 (thumb2_legitimate_index_p): Replace TARGET_HARD_FLOAT with
12265 (arm_rtx_costs_internal): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
12266 with TARGET_VFP_BASE, to allow cost calculations for copies in MVE as
12268 (arm_get_vfp_saved_size): Replace TARGET_HARD_FLOAT with
12269 TARGET_VFP_BASE, to allow space calculation for VFP registers in MVE
12271 (arm_compute_frame_layout): Likewise.
12272 (arm_save_coproc_regs): Likewise.
12273 (arm_fixed_condition_code_regs): Modify to enable using VFPCC_REGNUM
12275 (arm_hard_regno_mode_ok): Replace "TARGET_HARD_FLOAT || TARGET_HAVE_MVE"
12276 with equivalent macro TARGET_VFP_BASE.
12277 (arm_expand_epilogue_apcs_frame): Likewise.
12278 (arm_expand_epilogue): Likewise.
12279 (arm_conditional_register_usage): Likewise.
12280 (arm_declare_function_name): Add check to skip printing .fpu directive
12281 in assembly file when TARGET_VFP_BASE is enabled and fpu_to_print is
12283 * config/arm/arm.h (TARGET_VFP_BASE): Define.
12284 * config/arm/arm.md (arch): Add "mve" to arch.
12285 (eq_attr "arch" "mve"): Enable on TARGET_HAVE_MVE is true.
12286 (vfp_pop_multiple_with_writeback): Replace "TARGET_HARD_FLOAT
12287 || TARGET_HAVE_MVE" with equivalent macro TARGET_VFP_BASE.
12288 * config/arm/constraints.md (Uf): Define to allow modification to FPCCR
12290 * config/arm/thumb2.md (thumb2_movsfcc_soft_insn): Modify target guard
12291 to not allow for MVE.
12292 * config/arm/unspecs.md (UNSPEC_GET_FPSCR): Move to volatile unspecs
12294 (VUNSPEC_GET_FPSCR): Define.
12295 * config/arm/vfp.md (thumb2_movhi_vfp): Add support for VMSR and VMRS
12296 instructions which move to general-purpose Register from Floating-point
12297 Special register and vice-versa.
12298 (thumb2_movhi_fp16): Likewise.
12299 (thumb2_movsi_vfp): Add support for VMSR and VMRS instructions along
12300 with MCR and MRC instructions which set and get Floating-point Status
12301 and Control Register (FPSCR).
12302 (movdi_vfp): Modify pattern to enable Single-precision scalar float move
12304 (thumb2_movdf_vfp): Modify pattern to enable Double-precision scalar
12305 float move patterns in MVE.
12306 (thumb2_movsfcc_vfp): Modify pattern to enable single float conditional
12307 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
12308 (thumb2_movdfcc_vfp): Modify pattern to enable double float conditional
12309 code move patterns of VFP also in MVE by adding TARGET_VFP_BASE check.
12310 (push_multi_vfp): Add support to use VFP VPUSH pattern for MVE by adding
12311 TARGET_VFP_BASE check.
12312 (set_fpscr): Add support to set FPSCR register for MVE. Modify pattern
12313 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
12315 (get_fpscr): Add support to get FPSCR register for MVE. Modify pattern
12316 using VFPCC_REGNUM as few MVE intrinsics use carry bit of FPSCR
12320 2020-03-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
12321 Mihail Ionescu <mihail.ionescu@arm.com>
12322 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
12324 * config.gcc (arm_mve.h): Include mve intrinsics header file.
12325 * config/arm/aout.h (p0): Add new register name for MVE predicated
12327 * config/arm-builtins.c (ARM_BUILTIN_SIMD_LANE_CHECK): Define macro
12328 common to Neon and MVE.
12329 (ARM_BUILTIN_NEON_LANE_CHECK): Renamed to ARM_BUILTIN_SIMD_LANE_CHECK.
12330 (arm_init_simd_builtin_types): Disable poly types for MVE.
12331 (arm_init_neon_builtins): Move a check to arm_init_builtins function.
12332 (arm_init_builtins): Use ARM_BUILTIN_SIMD_LANE_CHECK instead of
12333 ARM_BUILTIN_NEON_LANE_CHECK.
12334 (mve_dereference_pointer): Add function.
12335 (arm_expand_builtin_args): Call to mve_dereference_pointer when MVE is
12337 (arm_expand_neon_builtin): Moved to arm_expand_builtin function.
12338 (arm_expand_builtin): Moved from arm_expand_neon_builtin function.
12339 * config/arm/arm-c.c (__ARM_FEATURE_MVE): Define macro for MVE and MVE
12340 with floating point enabled.
12341 * config/arm/arm-protos.h (neon_immediate_valid_for_move): Renamed to
12342 simd_immediate_valid_for_move.
12343 (simd_immediate_valid_for_move): Renamed from
12344 neon_immediate_valid_for_move function.
12345 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Generate
12346 error if vfpv2 feature bit is disabled and mve feature bit is also
12347 disabled for HARD_FLOAT_ABI.
12348 (use_return_insn): Check to not push VFP regs for MVE.
12349 (aapcs_vfp_allocate): Add MVE check to have same Procedure Call Standard
12351 (aapcs_vfp_allocate_return_reg): Likewise.
12352 (thumb2_legitimate_address_p): Check to return 0 on valid Thumb-2
12353 address operand for MVE.
12354 (arm_rtx_costs_internal): MVE check to determine cost of rtx.
12355 (neon_valid_immediate): Rename to simd_valid_immediate.
12356 (simd_valid_immediate): Rename from neon_valid_immediate.
12357 (simd_valid_immediate): MVE check on size of vector is 128 bits.
12358 (neon_immediate_valid_for_move): Rename to
12359 simd_immediate_valid_for_move.
12360 (simd_immediate_valid_for_move): Rename from
12361 neon_immediate_valid_for_move.
12362 (neon_immediate_valid_for_logic): Modify call to neon_valid_immediate
12364 (neon_make_constant): Modify call to neon_valid_immediate function.
12365 (neon_vector_mem_operand): Return VFP register for POST_INC or PRE_DEC
12367 (output_move_neon): Add MVE check to generate vldm/vstm instrcutions.
12368 (arm_compute_frame_layout): Calculate space for saved VFP registers for
12370 (arm_save_coproc_regs): Save coproc registers for MVE.
12371 (arm_print_operand): Add case 'E' to print memory operands for MVE.
12372 (arm_print_operand_address): Check to print register number for MVE.
12373 (arm_hard_regno_mode_ok): Check for arm hard regno mode ok for MVE.
12374 (arm_modes_tieable_p): Check to allow structure mode for MVE.
12375 (arm_regno_class): Add VPR_REGNUM check.
12376 (arm_expand_epilogue_apcs_frame): MVE check to calculate epilogue code
12378 (arm_expand_epilogue): MVE check for enabling pop instructions in
12380 (arm_print_asm_arch_directives): Modify function to disable print of
12381 .arch_extension "mve" and "fp" for cases where MVE is enabled with
12383 (arm_vector_mode_supported_p): Check for modes available in MVE interger
12384 and MVE floating point.
12385 (arm_array_mode_supported_p): Add TARGET_HAVE_MVE check for array mode
12387 (arm_conditional_register_usage): Enable usage of conditional regsiter
12389 (fixed_regs[VPR_REGNUM]): Enable VPR_REG for MVE.
12390 (arm_declare_function_name): Modify function to disable print of
12391 .arch_extension "mve" and "fp" for cases where MVE is enabled with
12393 * config/arm/arm.h (TARGET_HAVE_MVE): Disable for soft float abi and
12394 when target general registers are required.
12395 (TARGET_HAVE_MVE_FLOAT): Likewise.
12396 (FIXED_REGISTERS): Add bit for VFP_REG class which is enabled in arm.c
12398 (CALL_USED_REGISTERS): Set bit for VFP_REG class in CALL_USED_REGISTERS
12399 which indicate this is not available for across function calls.
12400 (FIRST_PSEUDO_REGISTER): Modify.
12401 (VALID_MVE_MODE): Define valid MVE mode.
12402 (VALID_MVE_SI_MODE): Define valid MVE SI mode.
12403 (VALID_MVE_SF_MODE): Define valid MVE SF mode.
12404 (VALID_MVE_STRUCT_MODE): Define valid MVE struct mode.
12405 (VPR_REGNUM): Add Vector Predication Register in arm_regs_in_sequence
12407 (IS_VPR_REGNUM): Macro to check for VPR_REG register.
12408 (REG_ALLOC_ORDER): Add VPR_REGNUM entry.
12409 (enum reg_class): Add VPR_REG entry.
12410 (REG_CLASS_NAMES): Add VPR_REG entry.
12411 * config/arm/arm.md (VPR_REGNUM): Define.
12412 (conds): Check is_mve_type attrbiute to differentiate "conditional" and
12413 "unconditional" instructions.
12414 (arm_movsf_soft_insn): Modify RTL to not allow for MVE.
12415 (movdf_soft_insn): Modify RTL to not allow for MVE.
12416 (vfp_pop_multiple_with_writeback): Enable for MVE.
12417 (include "mve.md"): Include mve.md file.
12418 * config/arm/arm_mve.h: Add MVE intrinsics head file.
12419 * config/arm/constraints.md (Up): Constraint to enable "p0" register in MVE
12420 for vector predicated operands.
12421 * config/arm/iterators.md (VNIM1): Define.
12422 (VNINOTM1): Define.
12423 (VHFBF_split): Define
12424 * config/arm/mve.md: New file.
12425 (mve_mov<mode>): Define RTL for move, store and load in MVE.
12426 (mve_mov<mode>): Define move RTL pattern with vec_duplicate operator for
12428 * config/arm/neon.md (neon_immediate_valid_for_move): Rename with
12429 simd_immediate_valid_for_move.
12430 (neon_mov<mode>): Split pattern and move expand pattern "movv8hf" which
12431 is common to MVE and NEON to vec-common.md file.
12432 (vec_init<mode><V_elem_l>): Add TARGET_HAVE_MVE check.
12433 * config/arm/predicates.md (vpr_register_operand): Define.
12434 * config/arm/t-arm: Add mve.md file.
12435 * config/arm/types.md (mve_move): Add MVE instructions mve_move to
12437 (mve_store): Add MVE instructions mve_store to attribute "type".
12438 (mve_load): Add MVE instructions mve_load to attribute "type".
12439 (is_mve_type): Define attribute.
12440 * config/arm/vec-common.md (mov<mode>): Modify RTL expand to support
12441 standard move patterns in MVE along with NEON and IWMMXT with mode
12443 (mov<mode>): Modify RTL expand to support standard move patterns in NEON
12444 and IWMMXT with mode iterator V8HF.
12445 (movv8hf): Define RTL expand to support standard "movv8hf" pattern in
12447 * config/arm/vfp.md (neon_immediate_valid_for_move): Rename to
12448 simd_immediate_valid_for_move.
12451 2020-03-16 H.J. Lu <hongjiu.lu@intel.com>
12454 * config/i386/i386.md (*movsi_internal): Call ix86_output_ssemov
12455 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
12457 * config/i386/predicates.md (ext_sse_reg_operand): Removed.
12459 2020-03-16 Jakub Jelinek <jakub@redhat.com>
12462 * tree-inline.c (insert_init_stmt): Don't gimple_regimplify_operands
12465 PR tree-optimization/94166
12466 * tree-ssa-reassoc.c (sort_by_mach_mode): Use SSA_NAME_VERSION
12467 as secondary comparison key.
12469 2020-03-16 Bin Cheng <bin.cheng@linux.alibaba.com>
12471 PR tree-optimization/94125
12472 * tree-loop-distribution.c
12473 (loop_distribution::break_alias_scc_partitions): Update post order
12474 number for merged scc.
12476 2020-03-15 H.J. Lu <hongjiu.lu@intel.com>
12479 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_SI and
12481 * config/i386/i386.md (*movsf_internal): Call ix86_output_ssemov
12482 for TYPE_SSEMOV. Remove TARGET_PREFER_AVX256, TARGET_AVX512VL
12483 and ext_sse_reg_operand check.
12485 2020-03-15 Lewis Hyatt <lhyatt@gmail.com>
12487 * common.opt: Avoid redundancy in the help text.
12488 * config/arc/arc.opt: Likewise.
12489 * config/cr16/cr16.opt: Likewise.
12491 2020-03-14 Jakub Jelinek <jakub@redhat.com>
12493 PR middle-end/93566
12494 * tree-nested.c (convert_nonlocal_omp_clauses,
12495 convert_local_omp_clauses): Handle {,in_,task_}reduction clauses
12496 with C/C++ array sections.
12498 2020-03-14 H.J. Lu <hongjiu.lu@intel.com>
12501 * config/i386/i386.md (*movdi_internal): Call ix86_output_ssemov
12502 for TYPE_SSEMOV. Remove ext_sse_reg_operand and TARGET_AVX512VL
12505 2020-03-14 Jakub Jelinek <jakub@redhat.com>
12507 * gimple-fold.c (gimple_fold_builtin_strncpy): Change
12508 "a an" to "an" in a comment.
12509 * hsa-common.h (is_a_helper): Likewise.
12510 * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Likewise.
12511 * config/arc/arc.c (arc600_corereg_hazard): Likewise.
12512 * config/s390/s390.c (s390_indirect_branch_via_thunk): Likewise.
12514 2020-03-13 Aaron Sawdey <acsawdey@linux.ibm.com>
12517 * config/rs6000/rs6000.c (num_insns_constant_multi): Don't shift a
12518 64-bit value by 64 bits (UB).
12520 2020-03-13 Vladimir Makarov <vmakarov@redhat.com>
12522 PR rtl-optimization/92303
12523 * lra-spills.c (remove_pseudos): Try to simplify memory subreg.
12525 2020-03-13 Segher Boessenkool <segher@kernel.crashing.org>
12527 PR rtl-optimization/94148
12528 PR rtl-optimization/94042
12529 * df-core.c (BB_LAST_CHANGE_AGE): Delete.
12530 (df_worklist_propagate_forward): New parameter last_change_age, use
12531 that instead of bb->aux.
12532 (df_worklist_propagate_backward): Ditto.
12533 (df_worklist_dataflow_doublequeue): Use a local array last_change_age.
12535 2020-03-13 Richard Biener <rguenther@suse.de>
12537 PR tree-optimization/94163
12538 * tree-ssa-pre.c (create_expression_by_pieces): Check
12539 whether alignment would be zero.
12541 2020-03-13 Martin Liska <mliska@suse.cz>
12544 * lto-wrapper.c (run_gcc): Use concat for appending
12545 to collect_gcc_options.
12547 2020-03-13 Jakub Jelinek <jakub@redhat.com>
12550 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use gen_int_mode
12551 instead of GEN_INT.
12553 2020-03-13 H.J. Lu <hongjiu.lu@intel.com>
12556 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DF.
12557 * config/i386/i386.md (*movdf_internal): Call ix86_output_ssemov
12558 for TYPE_SSEMOV. Remove TARGET_AVX512F, TARGET_PREFER_AVX256,
12559 TARGET_AVX512VL and ext_sse_reg_operand check.
12561 2020-03-13 Bu Le <bule1@huawei.com>
12564 * config/aarch64/aarch64.opt (-param=aarch64-float-recp-precision=)
12565 (-param=aarch64-double-recp-precision=): New options.
12566 * doc/invoke.texi: Document them.
12567 * config/aarch64/aarch64.c (aarch64_emit_approx_div): Use them
12568 instead of hard-coding the choice of 1 for float and 2 for double.
12570 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12572 PR rtl-optimization/94119
12573 * resource.h (clear_hashed_info_until_next_barrier): Declare.
12574 * resource.c (clear_hashed_info_until_next_barrier): New function.
12575 * reorg.c (add_to_delay_list): Fix formatting.
12576 (relax_delay_slots): Call clear_hashed_info_until_next_barrier on
12577 the next instruction after removing a BARRIER.
12579 2020-03-13 Eric Botcazou <ebotcazou@adacore.com>
12581 PR middle-end/92071
12582 * expmed.c (store_integral_bit_field): For fields larger than a word,
12583 call extract_bit_field on the value if the mode is BLKmode. Remove
12584 specific path for big-endian targets and tidy things up a little bit.
12586 2020-03-12 Richard Sandiford <richard.sandiford@arm.com>
12588 PR rtl-optimization/90275
12589 * cse.c (cse_insn): Delete no-op register moves too.
12591 2020-03-12 Darius Galis <darius.galis@cyberthorstudios.com>
12593 * config/rx/rx.md (CTRLREG_CPEN): Remove.
12594 * config/rx/rx.c (rx_print_operand): Remove CTRLREG_CPEN support.
12596 2020-03-12 Richard Biener <rguenther@suse.de>
12598 PR tree-optimization/94103
12599 * tree-ssa-sccvn.c (visit_reference_op_load): Avoid type
12600 punning when the mode precision is not sufficient.
12602 2020-03-12 H.J. Lu <hongjiu.lu@intel.com>
12605 * config/i386/i386.c (ix86_output_ssemov): Handle MODE_DI,
12606 MODE_V1DF and MODE_V2SF.
12607 * config/i386/mmx.md (MMXMODE:*mov<mode>_internal): Call
12608 ix86_output_ssemov for TYPE_SSEMOV. Remove ext_sse_reg_operand
12611 2020-03-12 Jakub Jelinek <jakub@redhat.com>
12613 * doc/tm.texi.in (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Change
12614 ASM_OUTPUT_ALIGNED_DECL in description to ASM_OUTPUT_ALIGNED_LOCAL
12615 and ASM_OUTPUT_DECL to ASM_OUTPUT_LOCAL.
12616 * doc/tm.texi: Regenerated.
12618 PR tree-optimization/94130
12619 * tree-ssa-dse.c: Include gimplify.h.
12620 (increment_start_addr): If stmt has lhs, drop the lhs from call and
12621 set it after the call to the original value of the first argument.
12623 (decrement_count): Formatting fix.
12625 2020-03-11 Delia Burduv <delia.burduv@arm.com>
12627 * config/arm/arm-builtins.c
12628 (arm_init_simd_builtin_scalar_types): New.
12629 * config/arm/arm_neon.h (vld2_bf16): Used new builtin type.
12630 (vld2q_bf16): Used new builtin type.
12631 (vld3_bf16): Used new builtin type.
12632 (vld3q_bf16): Used new builtin type.
12633 (vld4_bf16): Used new builtin type.
12634 (vld4q_bf16): Used new builtin type.
12635 (vld2_dup_bf16): Used new builtin type.
12636 (vld2q_dup_bf16): Used new builtin type.
12637 (vld3_dup_bf16): Used new builtin type.
12638 (vld3q_dup_bf16): Used new builtin type.
12639 (vld4_dup_bf16): Used new builtin type.
12640 (vld4q_dup_bf16): Used new builtin type.
12642 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12645 * config/pdp11/pdp11.c (pdp11_asm_output_var): Call switch_to_section
12646 at the start to switch to data section. Don't print extra newline if
12647 .globl directive has not been emitted.
12649 2020-03-11 Richard Biener <rguenther@suse.de>
12651 * match.pd ((T *)(ptr - ptr-cst) -> &MEM[ptr + -ptr-cst]):
12654 2020-03-11 Eric Botcazou <ebotcazou@adacore.com>
12656 PR middle-end/93961
12657 * tree.c (variably_modified_type_p) <RECORD_TYPE>: Recurse into fields
12658 whose type is a qualified union.
12660 2020-03-11 Jakub Jelinek <jakub@redhat.com>
12663 * config/aarch64/aarch64.c (aarch64_add_offset_1): Use absu_hwi
12664 instead of abs_hwi, change moffset type to unsigned HOST_WIDE_INT.
12667 * value-prof.c (dump_histogram_value): Use abs_hwi instead of
12669 (get_nth_most_common_value): Use abs_hwi instead of abs.
12671 PR middle-end/94111
12672 * dfp.c (decimal_to_binary): Only use decimal128ToString if from->cl
12673 is rvc_normal, otherwise use real_to_decimal to print the number to
12676 PR tree-optimization/94114
12677 * tree-loop-distribution.c (generate_memset_builtin): Call
12678 rewrite_to_non_trapping_overflow even on mem.
12679 (generate_memcpy_builtin): Call rewrite_to_non_trapping_overflow even
12682 2020-03-10 Jeff Law <law@redhat.com>
12684 * config/bfin/bfin.md (movsi_insv): Add length attribute.
12686 2020-03-10 Jiufu Guo <guojiufu@linux.ibm.com>
12689 * config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): Check
12690 NAN and SIGNED_ZEROR for smax/smin.
12692 2020-03-10 Will Schmidt <will_schmidt@vnet.ibm.com>
12695 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
12696 clause to handle P9V_BUILTIN_VEC_LXVL with const arguments.
12698 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12700 * loop-iv.c (find_simple_exit): Make it static.
12701 * cfgloop.h: Remove the corresponding prototype.
12703 2020-03-10 Roman Zhuykov <zhroma@ispras.ru>
12705 * ddg.c (create_ddg): Fix intendation.
12706 (set_recurrence_length): Likewise.
12707 (create_ddg_all_sccs): Likewise.
12709 2020-03-10 Jakub Jelinek <jakub@redhat.com>
12712 * config/i386/i386.md (*testqi_ext_3): Call ix86_match_ccmode with
12713 CCZmode instead of CCNOmode if operands[2] has DImode and pos + len
12716 2020-03-09 Jason Merrill <jason@redhat.com>
12718 * gdbinit.in (pgs): Fix typo in documentation.
12720 2020-03-09 Vladimir Makarov <vmakarov@redhat.com>
12724 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
12726 PR rtl-optimization/93564
12727 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
12728 do not honor reg alloc order.
12730 2020-03-09 Andrew Pinski <apinski@marvell.com>
12732 PR inline-asm/94095
12733 * doc/extend.texi (x86 Operand Modifiers): Fix column
12736 2020-03-09 Martin Liska <mliska@suse.cz>
12739 * config/rs6000/rs6000.c (rs6000_option_override_internal):
12740 Remove set of str_align_loops and str_align_jumps as these
12741 should be set in previous 2 conditions in the function.
12743 2020-03-09 Jakub Jelinek <jakub@redhat.com>
12745 PR rtl-optimization/94045
12746 * params.opt (-param=max-find-base-term-values=): New option.
12747 * alias.c (find_base_term): Add cut-off for number of visited VALUEs
12748 in a single toplevel find_base_term call.
12750 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12753 * config/aarch64/aarch64-builtins.c (TYPES_TERNOPU_LANE): Add define.
12754 * config/aarch64/aarch64-simd.md
12755 (aarch64_vec_<su>mult_lane<Qlane>): Add new insn for widening lane mul.
12756 (aarch64_vec_<su>mlal_lane<Qlane>): Likewise.
12757 * config/aarch64/aarch64-simd-builtins.def: Add intrinsics.
12758 * config/aarch64/arm_neon.h:
12759 (vmlal_lane_s16): Expand using intrinsics rather than inline asm.
12760 (vmlal_lane_u16): Likewise.
12761 (vmlal_lane_s32): Likewise.
12762 (vmlal_lane_u32): Likewise.
12763 (vmlal_laneq_s16): Likewise.
12764 (vmlal_laneq_u16): Likewise.
12765 (vmlal_laneq_s32): Likewise.
12766 (vmlal_laneq_u32): Likewise.
12767 (vmull_lane_s16): Likewise.
12768 (vmull_lane_u16): Likewise.
12769 (vmull_lane_s32): Likewise.
12770 (vmull_lane_u32): Likewise.
12771 (vmull_laneq_s16): Likewise.
12772 (vmull_laneq_u16): Likewise.
12773 (vmull_laneq_s32): Likewise.
12774 (vmull_laneq_u32): Likewise.
12775 * config/aarch64/iterators.md (Vcondtype): New iterator for lane mul.
12778 2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
12780 * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
12781 (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
12782 (aarch64_mls_elt<mode>): Likewise.
12783 (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
12784 (aarch64_fma4_elt<mode>): Likewise.
12785 (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
12786 (aarch64_fma4_elt_to_64v2df): Likewise.
12787 (aarch64_fnma4_elt<mode>): Likewise.
12788 (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
12789 (aarch64_fnma4_elt_to_64v2df): Likewise.
12791 2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
12793 * config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
12794 Specify movprfx attribute.
12795 (@aarch64_sve_<sve_int_op>_lane_<mode>): Likewise.
12797 2020-03-06 David Edelsohn <dje.gcc@gmail.com>
12800 * config/rs6000/aix61.h (TARGET_NO_SUM_IN_TOC): Set to 1 for
12802 (TARGET_NO_FP_IN_TOC): Same.
12803 * config/rs6000/aix71.h: Same.
12804 * config/rs6000/aix72.h: Same.
12806 2020-03-06 Andrew Pinski <apinski@marvell.com>
12807 Jeff Law <law@redhat.com>
12809 PR rtl-optimization/93996
12810 * haifa-sched.c (remove_notes): Be more careful when adding
12813 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12815 * config/arm/arm_neon.h (vld2_bf16): New.
12821 (vld2_dup_bf16): New.
12822 (vld2q_dup_bf16): New.
12823 (vld3_dup_bf16): New.
12824 (vld3q_dup_bf16): New.
12825 (vld4_dup_bf16): New.
12826 (vld4q_dup_bf16): New.
12827 * config/arm/arm_neon_builtins.def
12828 (vld2): Changed to VAR13 and added v4bf, v8bf
12829 (vld2_dup): Changed to VAR8 and added v4bf, v8bf
12830 (vld3): Changed to VAR13 and added v4bf, v8bf
12831 (vld3_dup): Changed to VAR8 and added v4bf, v8bf
12832 (vld4): Changed to VAR13 and added v4bf, v8bf
12833 (vld4_dup): Changed to VAR8 and added v4bf, v8bf
12834 * config/arm/iterators.md (VDXBF2): New iterator.
12835 *config/arm/neon.md (neon_vld2): Use new iterators.
12836 (neon_vld2_dup<mode): Use new iterators.
12837 (neon_vld3<mode>): Likewise.
12838 (neon_vld3qa<mode>): Likewise.
12839 (neon_vld3qb<mode>): Likewise.
12840 (neon_vld3_dup<mode>): Likewise.
12841 (neon_vld4<mode>): Likewise.
12842 (neon_vld4qa<mode>): Likewise.
12843 (neon_vld4qb<mode>): Likewise.
12844 (neon_vld4_dup<mode>): Likewise.
12845 (neon_vld2_dupv8bf): New.
12846 (neon_vld3_dupv8bf): Likewise.
12847 (neon_vld4_dupv8bf): Likewise.
12849 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12851 * config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
12852 (bfloat16x8x2_t): New typedef.
12853 (bfloat16x4x3_t): New typedef.
12854 (bfloat16x8x3_t): New typedef.
12855 (bfloat16x4x4_t): New typedef.
12856 (bfloat16x8x4_t): New typedef.
12863 * config/arm/arm-builtins.c (v2bf_UP): Define.
12865 (arm_init_simd_builtin_types): Init Bfloat16x2_t eltype.
12866 * config/arm/arm-modes.def (V2BF): New mode.
12867 * config/arm/arm-simd-builtin-types.def
12868 (Bfloat16x2_t): New entry.
12869 * config/arm/arm_neon_builtins.def
12870 (vst2): Changed to VAR13 and added v4bf, v8bf
12871 (vst3): Changed to VAR13 and added v4bf, v8bf
12872 (vst4): Changed to VAR13 and added v4bf, v8bf
12873 * config/arm/iterators.md (VDXBF): New iterator.
12874 (VQ2BF): New iterator.
12875 *config/arm/neon.md (neon_vst2<mode>): Used new iterators.
12876 (neon_vst2<mode>): Used new iterators.
12877 (neon_vst3<mode>): Used new iterators.
12878 (neon_vst3<mode>): Used new iterators.
12879 (neon_vst3qa<mode>): Used new iterators.
12880 (neon_vst3qb<mode>): Used new iterators.
12881 (neon_vst4<mode>): Used new iterators.
12882 (neon_vst4<mode>): Used new iterators.
12883 (neon_vst4qa<mode>): Used new iterators.
12884 (neon_vst4qb<mode>): Used new iterators.
12886 2020-03-06 Delia Burduv <delia.burduv@arm.com>
12888 * config/aarch64/aarch64-simd-builtins.def
12889 (bfcvtn): New built-in function.
12890 (bfcvtn_q): New built-in function.
12891 (bfcvtn2): New built-in function.
12892 (bfcvt): New built-in function.
12893 * config/aarch64/aarch64-simd.md
12894 (aarch64_bfcvtn<q><mode>): New pattern.
12895 (aarch64_bfcvtn2v8bf): New pattern.
12896 (aarch64_bfcvtbf): New pattern.
12897 * config/aarch64/arm_bf16.h (float32_t): New typedef.
12898 (vcvth_bf16_f32): New intrinsic.
12899 * config/aarch64/arm_bf16.h (vcvt_bf16_f32): New intrinsic.
12900 (vcvtq_low_bf16_f32): New intrinsic.
12901 (vcvtq_high_bf16_f32): New intrinsic.
12902 * config/aarch64/iterators.md (V4SF_TO_BF): New mode iterator.
12903 (UNSPEC_BFCVTN): New UNSPEC.
12904 (UNSPEC_BFCVTN2): New UNSPEC.
12905 (UNSPEC_BFCVT): New UNSPEC.
12906 * config/arm/types.md (bf_cvt): New type.
12908 2020-03-06 Andreas Krebbel <krebbel@linux.ibm.com>
12910 * config/s390/s390.md ("tabort"): Get rid of two consecutive
12911 blanks in format string.
12913 2020-03-05 H.J. Lu <hongjiu.lu@intel.com>
12917 * config/i386/i386-protos.h (ix86_output_ssemov): New prototype.
12918 * config/i386/i386.c (ix86_get_ssemov): New function.
12919 (ix86_output_ssemov): Likewise.
12920 * config/i386/sse.md (VMOVE:mov<mode>_internal): Call
12921 ix86_output_ssemov for TYPE_SSEMOV. Remove TARGET_AVX512VL
12923 (*movxi_internal_avx512f): Call ix86_output_ssemov for TYPE_SSEMOV.
12924 (*movoi_internal_avx): Call ix86_output_ssemov for TYPE_SSEMOV.
12925 Remove ext_sse_reg_operand and TARGET_AVX512VL check.
12926 (*movti_internal): Likewise.
12927 (*movtf_internal): Call ix86_output_ssemov for TYPE_SSEMOV.
12929 2020-03-05 Jeff Law <law@redhat.com>
12931 PR tree-optimization/91890
12932 * gimple-ssa-warn-restrict.c (maybe_diag_overlap): Remove LOC argument.
12933 Use gimple_or_expr_nonartificial_location.
12934 (check_bounds_overlap): Drop LOC argument to maybe_diag_access_bounds.
12935 Use gimple_or_expr_nonartificial_location.
12936 * gimple.c (gimple_or_expr_nonartificial_location): New function.
12937 * gimple.h (gimple_or_expr_nonartificial_location): Declare it.
12938 * tree-ssa-strlen.c (maybe_warn_overflow): Use
12939 gimple_or_expr_nonartificial_location.
12940 (maybe_diag_stxncpy_trunc, handle_builtin_stxncpy_strncat): Likewise.
12941 (maybe_warn_pointless_strcmp): Likewise.
12943 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12946 * config/i386/avx2intrin.h (_mm_mask_i32gather_ps): Fix first cast of
12947 SRC and MASK arguments to __m128 from __m128d.
12948 (_mm256_mask_i32gather_ps): Fix first cast of MASK argument to __m256
12950 (_mm_mask_i64gather_ps): Fix first cast of MASK argument to __m128
12952 * config/i386/xopintrin.h (_mm_permute2_pd): Fix first cast of C
12953 argument to __m128i from __m128d.
12954 (_mm256_permute2_pd): Fix first cast of C argument to __m256i from
12956 (_mm_permute2_ps): Fix first cast of C argument to __m128i from __m128.
12957 (_mm256_permute2_ps): Fix first cast of C argument to __m256i from
12960 2020-03-05 Delia Burduv <delia.burduv@arm.com>
12962 * config/arm/arm_neon.h (vbfmmlaq_f32): New.
12963 (vbfmlalbq_f32): New.
12964 (vbfmlaltq_f32): New.
12965 (vbfmlalbq_lane_f32): New.
12966 (vbfmlaltq_lane_f32): New.
12967 (vbfmlalbq_laneq_f32): New.
12968 (vbfmlaltq_laneq_f32): New.
12969 * config/arm/arm_neon_builtins.def (vmmla): New.
12974 (vfmab_laneq): New.
12975 (vfmat_laneq): New.
12976 * config/arm/iterators.md (BF_MA): New int iterator.
12977 (bt): New int attribute.
12978 (VQXBF): Copy of VQX with V8BF.
12979 * config/arm/neon.md (neon_vmmlav8bf): New insn.
12980 (neon_vfma<bt>v8bf): New insn.
12981 (neon_vfma<bt>_lanev8bf): New insn.
12982 (neon_vfma<bt>_laneqv8bf): New expand.
12983 (neon_vget_high<mode>): Changed iterator to VQXBF.
12984 * config/arm/unspecs.md (UNSPEC_BFMMLA): New UNSPEC.
12985 (UNSPEC_BFMAB): New UNSPEC.
12986 (UNSPEC_BFMAT): New UNSPEC.
12988 2020-03-05 Jakub Jelinek <jakub@redhat.com>
12990 PR middle-end/93399
12991 * tree-pretty-print.h (pretty_print_string): Declare.
12992 * tree-pretty-print.c (pretty_print_string): Remove forward
12993 declaration, no longer static. Change nbytes parameter type
12994 from unsigned to size_t.
12995 * print-rtl.c (print_value) <case CONST_STRING>: Use
12996 pretty_print_string and for shrink way too long strings.
12998 2020-03-05 Richard Biener <rguenther@suse.de>
12999 Jakub Jelinek <jakub@redhat.com>
13001 PR tree-optimization/93582
13002 * tree-ssa-sccvn.c (vn_reference_lookup_3): Treat POINTER_PLUS_EXPR
13003 last operand as signed when looking for memset offset. Formatting
13006 2020-03-04 Andrew Pinski <apinski@marvell.com>
13009 * value-prof.c (dump_histogram_value): Use std::abs.
13011 2020-03-04 Martin Sebor <msebor@redhat.com>
13013 PR tree-optimization/93986
13014 * tree-ssa-strlen.c (maybe_warn_overflow): Convert all wide_int
13015 operands to the same precision widest_int to avoid ICEs.
13017 2020-03-04 Bill Schmidt <wschmidt@linux.ibm.com>
13020 * rs6000-cpus.def (OTHER_ALTIVEC_MASKS): New #define.
13021 * rs6000.c (rs6000_disable_incompatible_switches): Add table entry
13022 for OPTION_MASK_ALTIVEC.
13024 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
13026 * config.gcc: Include the glibc-stdint.h header for zTPF.
13028 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
13030 * config/s390/s390.c (s390_secondary_memory_needed): Disallow
13031 direct FPR-GPR copies.
13032 (s390_register_info_gprtofpr): Disallow GPR content to be saved in
13035 2020-03-04 Andreas Krebbel <krebbel@linux.ibm.com>
13037 * config/s390/s390.c (s390_emit_prologue): Specify the 2 new
13038 operands to the prologue_tpf expander.
13039 (s390_emit_epilogue): Likewise.
13040 (s390_option_override_internal): Do error checking and setup for
13042 * config/s390/tpf.h (TPF_TRACE_PROLOGUE_CHECK)
13043 (TPF_TRACE_EPILOGUE_CHECK, TPF_TRACE_PROLOGUE_TARGET)
13044 (TPF_TRACE_EPILOGUE_TARGET, TPF_TRACE_PROLOGUE_SKIP_TARGET)
13045 (TPF_TRACE_EPILOGUE_SKIP_TARGET): New macro definitions.
13046 * config/s390/tpf.md ("prologue_tpf", "epilogue_tpf"): Add two new
13047 operands for the check flag and the branch target.
13048 * config/s390/tpf.opt ("mtpf-trace-hook-prologue-check")
13049 ("mtpf-trace-hook-prologue-target")
13050 ("mtpf-trace-hook-epilogue-check")
13051 ("mtpf-trace-hook-epilogue-target", "mtpf-trace-skip"): New
13053 * doc/invoke.texi: Document -mtpf-trace-skip option. The other
13054 options are for debugging purposes and will not be documented
13057 2020-03-04 Jakub Jelinek <jakub@redhat.com>
13060 * tree-inline.c (copy_decl_to_var): Copy DECL_BY_REFERENCE flag.
13062 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Add offseti
13063 argument. Change pd argument so that it can be modified. Turn
13064 constant non-CONSTRUCTOR store into non-constant if it is too large.
13065 Adjust offset and size of CONSTRUCTOR or non-constant store to avoid
13067 (vn_walk_cb_data::vn_walk_cb_data, vn_reference_lookup_3): Adjust
13070 2020-02-04 Richard Biener <rguenther@suse.de>
13072 PR tree-optimization/93964
13073 * graphite-isl-ast-to-gimple.c
13074 (gcc_expression_from_isl_ast_expr_id): Add intermediate
13075 conversion for pointer to integer converts.
13076 * graphite-scop-detection.c (assign_parameter_index_in_region):
13079 2020-03-04 Martin Liska <mliska@suse.cz>
13083 * doc/invoke.texi: Clarify --help=language and --help=common
13086 2020-03-04 Jakub Jelinek <jakub@redhat.com>
13088 PR tree-optimization/94001
13089 * tree-tailcall.c (process_assignment): Before comparing op1 to
13090 *ass_var, verify *ass_var is non-NULL.
13092 2020-03-04 Kito Cheng <kito.cheng@sifive.com>
13095 * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
13098 2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
13100 * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
13101 * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
13102 (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
13103 (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
13104 * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
13105 (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
13106 * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
13107 (V_bf_low, V_bf_cvt_m): New mode attributes.
13108 * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
13109 (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
13110 (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
13111 (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
13112 * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
13114 2020-03-03 Jakub Jelinek <jakub@redhat.com>
13116 PR tree-optimization/93582
13117 * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
13118 * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
13119 members, initialize them in the constructor and if mask is non-NULL,
13120 artificially push_partial_def {} for the portions of the mask that
13122 (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
13123 val and return (void *)-1. Formatting fix.
13124 (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
13126 (vn_reference_lookup): Add mask argument. If non-NULL, don't call
13127 fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
13129 (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
13131 (visit_stmt): Formatting fix.
13133 2020-03-03 Richard Biener <rguenther@suse.de>
13135 PR tree-optimization/93946
13136 * alias.h (refs_same_for_tbaa_p): Declare.
13137 * alias.c (refs_same_for_tbaa_p): New function.
13138 * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
13140 * tree-ssa-scopedtables.h
13141 (avail_exprs_stack::lookup_avail_expr): Add output argument
13142 giving access to the hashtable entry.
13143 * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
13145 * tree-ssa-dom.c: Include alias.h.
13146 (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
13147 removing redundant store.
13148 * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
13149 (ao_ref_init_from_vn_reference): Adjust prototype.
13150 (vn_reference_lookup_pieces): Likewise.
13151 (vn_reference_insert_pieces): Likewise.
13152 * tree-ssa-sccvn.c: Track base alias set in addition to alias
13154 (eliminate_dom_walker::eliminate_stmt): Also check base alias
13155 set when removing redundant stores.
13156 (visit_reference_op_store): Likewise.
13157 * dse.c (record_store): Adjust valdity check for redundant
13160 2020-03-03 Jakub Jelinek <jakub@redhat.com>
13163 * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
13165 PR rtl-optimization/94002
13166 * explow.c (plus_constant): Punt if cst has VOIDmode and
13167 get_pool_mode is different from mode.
13169 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
13171 * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
13172 address has an offset which fits the scalling constraint for a
13173 load/store operation.
13174 (legitimate_scaled_address_p): Update use
13175 leigitimate_small_data_address_p.
13176 (arc_print_operand): Likewise.
13177 (arc_legitimate_address_p): Likewise.
13178 (legitimate_small_data_address_p): Likewise.
13180 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
13182 * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
13183 (fnmasf4_fpu): Likewise.
13185 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
13187 * config/arc/arc.md (adddi3): Early expand the 64bit operation into
13189 (subdi3): Likewise.
13190 (adddi3_i): Remove pattern.
13191 (subdi3_i): Likewise.
13193 2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
13195 * config/arc/arc.md (eh_return): Add length info.
13197 2020-03-02 David Malcolm <dmalcolm@redhat.com>
13199 * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
13201 2020-03-02 David Malcolm <dmalcolm@redhat.com>
13203 * doc/invoke.texi (Static Analyzer Options): Add
13204 -Wanalyzer-stale-setjmp-buffer to the list of options enabled
13207 2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
13210 * config/i386/i386.md (movstrict<mode>): Allow only
13211 registers with VALID_INT_MODE_P modes.
13213 2020-03-02 Andrew Stubbs <ams@codesourcery.com>
13215 * config/gcn/gcn-valu.md (dpp_move<mode>): New.
13216 (reduc_insn): Use 'U' and 'B' operand codes.
13217 (reduc_<reduc_op>_scal_<mode>): Allow all types.
13218 (reduc_<reduc_op>_scal_v64di): Delete.
13219 (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
13220 (*plus_carry_dpp_shr_v64si): Change to ...
13221 (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
13222 (mov_from_lane63_v64di): Change to ...
13223 (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
13224 * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
13225 Support UNSPEC_MOV_DPP_SHR output formats.
13226 (gcn_expand_reduc_scalar): Add "use_moves" reductions.
13227 Add "use_extends" reductions.
13228 (print_operand_address): Add 'I' and 'U' codes.
13229 * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
13231 2020-03-02 Martin Liska <mliska@suse.cz>
13233 * lto-wrapper.c: Fix typo in comment about
13234 C++ standard version.
13236 2020-03-01 Martin Sebor <msebor@redhat.com>
13239 * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
13241 2020-03-01 Martin Sebor <msebor@redhat.com>
13243 PR middle-end/93829
13244 * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
13245 of a pointer in the outermost ADDR_EXPRs.
13247 2020-02-28 Jeff Law <law@redhat.com>
13249 * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
13250 * config/v850/v850.c (v850_asm_trampoline_template): Update
13253 2020-02-28 Michael Meissner <meissner@linux.ibm.com>
13256 * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
13259 2020-02-28 Martin Liska <mliska@suse.cz>
13262 * configure.ac: Improve detection of ld_date by requiring
13263 either two dashes or none.
13264 * configure: Regenerate.
13266 2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
13268 PR rtl-optimization/93564
13269 * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
13270 do not honor reg alloc order.
13272 2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
13275 * config/aarch64/aarch64.c (aarch64_override_options): Fix
13276 misleading warning string.
13278 2020-02-27 Martin Sebor <msebor@redhat.com>
13280 * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
13282 2020-02-27 Michael Meissner <meissner@linux.ibm.com>
13285 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
13286 Split the insn into two parts. This insn only does variable
13287 extract from a register.
13288 (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
13289 variable extract from memory.
13290 (vsx_extract_v4sf_var): Split the insn into two parts. This insn
13291 only does variable extract from a register.
13292 (vsx_extract_v4sf_var_load): New insn, do variable extract from
13294 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
13295 into two parts. This insn only does variable extract from a
13297 (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
13298 do variable extract from memory.
13300 2020-02-27 Martin Jambor <mjambor@suse.cz>
13301 Feng Xue <fxue@os.amperecomputing.com>
13304 * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
13305 new function calls_same_node_or_its_all_contexts_clone_p.
13306 (cgraph_edge_brings_value_p): Use it.
13307 (cgraph_edge_brings_value_p): Likewise.
13308 (self_recursive_pass_through_p): Return false if caller is a clone.
13309 (self_recursive_agg_pass_through_p): Likewise.
13311 2020-02-27 Jan Hubicka <hubicka@ucw.cz>
13313 PR middle-end/92152
13314 * alias.c (ends_tbaa_access_path_p): Break out from ...
13315 (component_uses_parent_alias_set_from): ... here.
13316 * alias.h (ends_tbaa_access_path_p): Declare.
13317 * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
13318 handle trailing arrays past end of tbaa access path.
13319 (aliasing_component_refs_p): ... here; likewise.
13320 (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
13321 path; disambiguate also past end of it.
13322 (nonoverlapping_component_refs_p): Use only TBAA segment of the access
13325 2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
13327 * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
13328 beginning of the file.
13329 (vcreate_bf16, vcombine_bf16): New.
13330 (vdup_n_bf16, vdupq_n_bf16): New.
13331 (vdup_lane_bf16, vdup_laneq_bf16): New.
13332 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
13333 (vduph_lane_bf16, vduph_laneq_bf16): New.
13334 (vset_lane_bf16, vsetq_lane_bf16): New.
13335 (vget_lane_bf16, vgetq_lane_bf16): New.
13336 (vget_high_bf16, vget_low_bf16): New.
13337 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
13338 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
13339 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
13340 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
13341 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
13342 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
13343 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
13344 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
13345 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
13346 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
13347 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
13348 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
13349 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
13350 (vreinterpretq_bf16_p128): New.
13351 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
13352 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
13353 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
13354 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
13355 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
13356 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
13357 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
13358 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
13359 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
13360 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
13361 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
13362 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
13363 (vreinterpretq_p128_bf16): New.
13364 * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
13365 (V_elem): Likewise.
13366 (V_elem_l): Likewise.
13367 (VD_LANE): Likewise.
13369 (V_DOUBLE): Likewise.
13370 (VDQX): Add V4BF and V8BF.
13371 (V_two_elem, V_three_elem, V_four_elem): Likewise.
13373 (V_HALF): Likewise.
13374 (V_double_vector_mode): Likewise.
13375 (V_cmp_result): Likewise.
13376 (V_uf_sclr): Likewise.
13377 (V_sz_elem): Likewise.
13378 (Is_d_reg): Likewise.
13379 (V_mode_nunits): Likewise.
13380 * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
13382 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
13384 * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
13385 (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
13386 (<expander><mode>3<exec>): Likewise.
13387 (<expander><mode>3): New.
13388 (v<expander><mode>3): New.
13389 (<expander><mode>3): New.
13390 (<expander><mode>3<exec>): Rename to ...
13391 (<expander>v64si3<exec>): ... this, and change modes to V64SI.
13392 * config/gcn/gcn.md (mnemonic): Use '%B' for not.
13394 2020-02-27 Alexandre Oliva <oliva@adacore.com>
13396 * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
13399 2020-02-27 Richard Biener <rguenther@suse.de>
13401 PR tree-optimization/93508
13402 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
13403 non-_CHK variants. Valueize their length arguments.
13405 2020-02-27 Richard Biener <rguenther@suse.de>
13407 PR tree-optimization/93953
13408 * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
13409 to the hash-map entry.
13411 2020-02-27 Andrew Stubbs <ams@codesourcery.com>
13413 * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
13415 2020-02-27 Mark Williams <mwilliams@fb.com>
13417 * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
13418 * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
13419 -ffile-prefix-map and -fmacro-prefix-map.
13420 * lto-streamer-out.c: Include file-prefix-map.h.
13421 (lto_output_location): Remap the file part of locations.
13423 2020-02-27 Jakub Jelinek <jakub@redhat.com>
13426 * gimplify.c (gimplify_init_constructor): Don't promote readonly
13427 DECL_REGISTER variables to TREE_STATIC.
13429 PR tree-optimization/93582
13430 PR tree-optimization/93945
13431 * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
13432 non-zero INTEGER_CST second argument and ref->offset or ref->size
13433 not a multiple of BITS_PER_UNIT.
13435 2020-02-27 Jonathan Wakely <jwakely@redhat.com>
13437 * doc/install.texi (Binaries): Update description of BullFreeware.
13439 2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
13443 * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
13444 C++ Language Options, Warning Options, and Static Analyzer
13445 Options lists. Document negative form of options enabled by
13446 default. Move some things around to more accurately sort
13447 warnings by category.
13448 (C++ Dialect Options, Warning Options, Static Analyzer
13449 Options): Document negative form of options when enabled by
13450 default. Move some things around to more accurately sort
13451 warnings by category. Add some missing index entries.
13452 Light copy-editing.
13454 2020-02-26 Carl Love <cel@us.ibm.com>
13457 * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
13458 ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
13459 for the vector unsigned short arguments. It is also listed as the
13460 name of the built-in for arguments vector unsigned short,
13461 vector unsigned int and vector unsigned long long built-ins. The
13462 name of the builtins for these arguments should be:
13463 __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
13464 __builtin_crypto_vpmsumd respectively.
13466 2020-02-26 Richard Biener <rguenther@suse.de>
13468 * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
13469 and load permutation.
13471 2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
13473 PR middle-end/93843
13474 * optabs-tree.c (supportable_convert_operation): Reject types with
13477 2020-02-26 David Malcolm <dmalcolm@redhat.com>
13479 * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
13481 2020-02-26 Jakub Jelinek <jakub@redhat.com>
13483 PR tree-optimization/93820
13484 * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
13485 argument to ALL_INTEGER_CST_P boolean.
13486 (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
13487 (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
13488 adjacent INTEGER_CST store into merged_store->only_constants like
13491 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13494 * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
13496 * cfghooks.c (verify_flow_info): Likewise.
13497 * predict.c (combine_predictions_for_bb): Likewise.
13498 * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
13499 sucessor -> successor.
13500 (find_traces_1_round): Fix comment typo, destinarion -> destination.
13501 * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
13503 * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
13504 message typo, sucessors -> successors.
13506 2020-02-25 Martin Sebor <msebor@redhat.com>
13508 * doc/extend.texi (attribute access): Correct an example.
13510 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
13512 * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
13514 (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
13515 (VAR15, VAR16): New.
13516 * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
13517 (VD): Enable for V4BF.
13519 (VQ): Enable for V8BF.
13521 (VQ_NO2E): Likewise.
13522 (VDBL, Vdbl): Add V4BF.
13523 (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
13524 * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
13525 (bfloat16x8x2_t): Likewise.
13526 (bfloat16x4x3_t): Likewise.
13527 (bfloat16x8x3_t): Likewise.
13528 (bfloat16x4x4_t): Likewise.
13529 (bfloat16x8x4_t): Likewise.
13530 (vcombine_bf16): New.
13531 (vld1_bf16, vld1_bf16_x2): New.
13532 (vld1_bf16_x3, vld1_bf16_x4): New.
13533 (vld1q_bf16, vld1q_bf16_x2): New.
13534 (vld1q_bf16_x3, vld1q_bf16_x4): New.
13535 (vld1_lane_bf16): New.
13536 (vld1q_lane_bf16): New.
13537 (vld1_dup_bf16): New.
13538 (vld1q_dup_bf16): New.
13541 (vld2_dup_bf16): New.
13542 (vld2q_dup_bf16): New.
13545 (vld3_dup_bf16): New.
13546 (vld3q_dup_bf16): New.
13549 (vld4_dup_bf16): New.
13550 (vld4q_dup_bf16): New.
13551 (vst1_bf16, vst1_bf16_x2): New.
13552 (vst1_bf16_x3, vst1_bf16_x4): New.
13553 (vst1q_bf16, vst1q_bf16_x2): New.
13554 (vst1q_bf16_x3, vst1q_bf16_x4): New.
13555 (vst1_lane_bf16): New.
13556 (vst1q_lane_bf16): New.
13564 2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
13566 * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
13567 (VALL_F16): Likewise.
13568 (VALLDI_F16): Likewise.
13570 (Vetype): Likewise.
13571 (vswap_width_name): Likewise.
13572 (VSWAP_WIDTH): Likewise.
13576 * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
13577 (vget_lane_bf16, vgetq_lane_bf16): New.
13578 (vcreate_bf16): New.
13579 (vdup_n_bf16, vdupq_n_bf16): New.
13580 (vdup_lane_bf16, vdup_laneq_bf16): New.
13581 (vdupq_lane_bf16, vdupq_laneq_bf16): New.
13582 (vduph_lane_bf16, vduph_laneq_bf16): New.
13583 (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
13584 (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
13585 (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
13586 (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
13587 (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
13588 (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
13589 (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
13590 (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
13591 (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
13592 (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
13593 (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
13594 (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
13595 (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
13596 (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
13597 (vreinterpretq_bf16_p128): New.
13598 (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
13599 (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
13600 (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
13601 (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
13602 (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
13603 (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
13604 (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
13605 (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
13606 (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
13607 (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
13608 (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
13609 (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
13610 (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
13611 (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
13612 (vreinterpretq_p128_bf16): New.
13614 2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
13616 * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
13617 (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
13618 (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
13619 * config/arm/arm_neon_builtins.def (vbfdot): New entry.
13620 (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
13621 * config/arm/iterators.md (VSF2BF): New attribute.
13622 * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
13623 (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
13624 (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
13626 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
13628 * config/arm/arm.md (required_for_purecode): New attribute.
13629 (enabled): Handle required_for_purecode.
13630 * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
13631 work with -mpure-code.
13633 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13635 PR rtl-optimization/93908
13636 * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
13639 2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
13641 * dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
13643 2020-02-25 Roman Zhuykov <zhroma@ispras.ru>
13645 * doc/install.texi (--enable-checking): Adjust wording.
13647 2020-02-25 Richard Biener <rguenther@suse.de>
13649 PR tree-optimization/93868
13650 * tree-vect-slp.c (slp_copy_subtree): New function.
13651 (vect_attempt_slp_rearrange_stmts): Copy the SLP tree before
13652 re-arranging stmts in it.
13654 2020-02-25 Jakub Jelinek <jakub@redhat.com>
13656 PR middle-end/93874
13657 * passes.c (pass_manager::dump_passes): Create a cgraph node for the
13658 dummy function and remove it at the end.
13660 PR translation/93864
13661 * config/lm32/lm32.c (lm32_setup_incoming_varargs): Fix comment typo
13662 paramter -> parameter.
13663 * config/aarch64/aarch64.c (aarch64_is_extend_from_extract): Likewise.
13664 * ipa-prop.h (struct ipa_agg_replacement_value): Likewise.
13666 2020-02-24 Roman Zhuykov <zhroma@ispras.ru>
13668 * doc/install.texi (--enable-checking): Properly document current
13670 (--enable-stage1-checking): Minor clarification about bootstrap.
13672 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13675 * doc/invoke.texi (-Wnanalyzer-tainted-array-index): Note that
13676 -fanalyzer-checker=taint is also required.
13677 (-fanalyzer-checker=): Note that providing this option enables the
13678 given checker, and doing so may be required for checkers that are
13679 disabled by default.
13681 2020-02-24 David Malcolm <dmalcolm@redhat.com>
13683 * doc/invoke.texi (-fanalyzer-verbosity=): "2" only shows
13684 significant control flow events; add a "3" which shows all
13685 control flow events; the old "3" becomes "4".
13687 2020-02-24 Jakub Jelinek <jakub@redhat.com>
13689 PR tree-optimization/93582
13690 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Consider
13691 pd.offset and pd.size to be counted in bits rather than bytes, add
13692 support for maxsizei that is not a multiple of BITS_PER_UNIT and
13693 handle bitfield stores and loads.
13694 (vn_reference_lookup_3): Don't call ranges_known_overlap_p with
13695 uncomparable quantities - bytes vs. bits. Allow push_partial_def
13696 on offsets/sizes that aren't multiple of BITS_PER_UNIT and adjust
13697 pd.offset/pd.size to be counted in bits rather than bytes.
13698 Formatting fix. Rename shadowed len variable to buflen.
13700 2020-02-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
13701 Kugan Vivekandarajah <kugan.vivekanandarajah@linaro.org>
13704 * gcc.c (putenv_COLLECT_AS_OPTIONS): New function.
13705 (driver::main): Call putenv_COLLECT_AS_OPTIONS.
13706 * opts-common.c (parse_options_from_collect_gcc_options): New function.
13707 (prepend_xassembler_to_collect_as_options): Likewise.
13708 * opts.h (parse_options_from_collect_gcc_options): Declare prototype.
13709 (prepend_xassembler_to_collect_as_options): Likewise.
13710 * lto-opts.c (lto_write_options): Stream assembler options
13711 in COLLECT_AS_OPTIONS.
13712 * lto-wrapper.c (xassembler_options_error): New static variable.
13713 (get_options_from_collect_gcc_options): Move parsing options code to
13714 parse_options_from_collect_gcc_options and call it.
13715 (merge_and_complain): Validate -Xassembler options.
13716 (append_compiler_options): Handle OPT_Xassembler.
13717 (run_gcc): Append command line -Xassembler options to
13718 collect_gcc_options.
13719 * doc/invoke.texi: Add documentation about using Xassembler
13722 2020-02-24 Kito Cheng <kito.cheng@sifive.com>
13724 * config/riscv/riscv.c (riscv_emit_float_compare): Change the code gen
13726 (riscv_rtx_costs): Update cost model for LTGT.
13728 2020-02-23 Vladimir Makarov <vmakarov@redhat.com>
13730 PR rtl-optimization/93564
13731 * ira-color.c (struct update_cost_queue_elem): New member start.
13732 (queue_update_cost, get_next_update_cost): Add new arg start.
13733 (allocnos_conflict_p): New function.
13734 (update_costs_from_allocno): Add new arg conflict_cost_update_p.
13735 Add checking conflicts with allocnos_conflict_p.
13736 (update_costs_from_prefs, restore_costs_from_copies): Adjust
13737 update_costs_from_allocno calls.
13738 (update_conflict_hard_regno_costs): Add checking conflicts with
13739 allocnos_conflict_p. Adjust calls of queue_update_cost and
13740 get_next_update_cost.
13741 (assign_hard_reg): Adjust calls of queue_update_cost. Add
13743 (bucket_allocno_compare_func): Restore previous version.
13745 2020-02-21 John David Anglin <danglin@gcc.gnu.org>
13747 * config/pa/pa.c (pa_function_value): Fix check for word and
13748 double-word size when handling aggregate return values.
13749 * config/pa/som.h (ASM_DECLARE_FUNCTION_NAME): Fix to indicate
13750 that homogeneous SFmode and DFmode aggregates are passed and returned
13751 in general registers.
13753 2020-02-21 Jakub Jelinek <jakub@redhat.com>
13755 PR translation/93759
13756 * opts.c (print_filtered_help): Translate help before appending
13757 messages to it rather than after that.
13759 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13761 PR rtl-optimization/PR92989
13762 * lra-lives.c (process_bb_lives): Restore the original order
13763 of the bb liveness update. Call make_hard_regno_dead for each
13764 register clobbered at the start of an EH receiver.
13766 2020-02-18 Feng Xue <fxue@os.amperecomputing.com>
13769 * ipa-cp.c (self_recursively_generated_p): Mark self-dependent value as
13770 self-recursively generated.
13772 2020-02-21 Iain Sandoe <iain@sandoe.co.uk>
13775 * config/darwin-c.c (pop_field_alignment): Adjust quoting of
13778 2020-02-21 Mihail Ionescu <mihail.ionescu@arm.com>
13780 * doc/sourcebuild.texi (arm_v8_1m_mve_ok):
13781 Document new target supports option.
13783 2020-02-21 Dennis Zhang <dennis.zhang@arm.com>
13785 * config/arm/arm_neon.h (vmmlaq_s32, vmmlaq_u32, vusmmlaq_s32): New.
13786 * config/arm/arm_neon_builtins.def (smmla, ummla, usmmla): New.
13787 * config/arm/iterators.md (MATMUL): New iterator.
13788 (sup): Add UNSPEC_MATMUL_S, UNSPEC_MATMUL_U, and UNSPEC_MATMUL_US.
13789 (mmla_sfx): New attribute.
13790 * config/arm/neon.md (neon_<sup>mmlav16qi): New.
13791 * config/arm/unspecs.md (UNSPEC_MATMUL_S, UNSPEC_MATMUL_U): New.
13792 (UNSPEC_MATMUL_US): New.
13794 2020-02-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
13796 * config/arm/arm.md: Prevent scalar shifts from being used when big
13799 2020-02-21 Jan Hubicka <hubicka@ucw.cz>
13800 Richard Biener <rguenther@suse.de>
13802 PR tree-optimization/93586
13803 * tree-ssa-alias.c (nonoverlapping_array_refs_p): Finish array walk
13804 after mismatched array refs; do not sure type size information to
13805 recover from unmatched referneces with !flag_strict_aliasing_p.
13807 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13809 * config/gcn/gcn-valu.md (gather_load<mode>): Rename to ...
13810 (gather_load<mode>v64si): ... this and set operand 2 to V64SI.
13811 (scatter_store<mode>): Rename to ...
13812 (scatter_store<mode>v64si): ... this and set operand 1 to V64SI.
13813 (scatter<mode>_exec): Delete. Move contents ...
13814 (mask_scatter_store<mode>): ... here, and rename that to ...
13815 (mask_gather_load<mode>v64si): ... this. Set operand 2 to V64SI.
13816 Remove mode conversion.
13817 (mask_gather_load<mode>): Rename to ...
13818 (mask_scatter_store<mode>v64si): ... this. Set operand 1 to V64SI.
13819 Remove mode conversion.
13820 * config/gcn/gcn.c (gcn_expand_scaled_offsets): Remove mode conversion.
13822 2020-02-21 Martin Jambor <mjambor@suse.cz>
13824 PR tree-optimization/93845
13825 * tree-sra.c (verify_sra_access_forest): Only test access size of
13828 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13830 * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
13831 * config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
13832 (addv64di3_exec): Likewise.
13833 (subv64di3): Likewise.
13834 (subv64di3_exec): Likewise.
13835 (addv64di3_zext): Likewise.
13836 (addv64di3_zext_exec): Likewise.
13837 (addv64di3_zext_dup): Likewise.
13838 (addv64di3_zext_dup_exec): Likewise.
13839 (addv64di3_zext_dup2): Likewise.
13840 (addv64di3_zext_dup2_exec): Likewise.
13841 (addv64di3_sext_dup2): Likewise.
13842 (addv64di3_sext_dup2_exec): Likewise.
13843 (<expander>v64di3): Likewise.
13844 (<expander>v64di3_exec): Likewise.
13845 (*<reduc_op>_dpp_shr_v64di): Likewise.
13846 (*plus_carry_dpp_shr_v64di): Likewise.
13847 * config/gcn/gcn.md (adddi3): Likewise.
13848 (addptrdi3): Likewise.
13849 (<expander>di3): Likewise.
13851 2020-02-21 Andrew Stubbs <ams@codesourcery.com>
13853 * config/gcn/gcn-valu.md (vec_seriesv64di): Use gen_vec_duplicatev64di.
13855 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13857 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Add SVE
13858 support. Use aarch64_emit_mult instead of emitting multiplication
13859 instructions directly.
13860 * config/aarch64/aarch64-sve.md (sqrt<mode>2, rsqrt<mode>2)
13861 (@aarch64_rsqrte<mode>, @aarch64_rsqrts<mode>): New expanders.
13863 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13865 * config/aarch64/aarch64.c (aarch64_emit_mult): New function.
13866 (aarch64_emit_approx_div): Add SVE support. Use aarch64_emit_mult
13867 instead of emitting multiplication instructions directly.
13868 * config/aarch64/iterators.md (SVE_COND_FP_BINARY_OPTAB): New iterator.
13869 * config/aarch64/aarch64-sve.md (div<mode>3, @aarch64_frecpe<mode>)
13870 (@aarch64_frecps<mode>): New expanders.
13872 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13874 * config/aarch64/aarch64-protos.h (AARCH64_APPROX_MODE): Operate
13875 on and produce uint64_ts rather than ints.
13876 (AARCH64_APPROX_NONE, AARCH64_APPROX_ALL): Change to uint64_ts.
13877 (cpu_approx_modes): Change the fields from unsigned int to uint64_t.
13879 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13881 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Don't create
13882 an unused xmsk register when handling approximate rsqrt.
13884 2020-02-21 Richard Sandiford <richard.sandiford@arm.com>
13886 * config/aarch64/aarch64.c (aarch64_emit_approx_sqrt): Fix inverted
13887 flag_finite_math_only condition.
13889 2020-02-20 Uroš Bizjak <ubizjak@gmail.com>
13892 * config/i386/mmx.md (*vec_extractv2sf_1): Match source operand
13893 to destination operand for shufps alternative.
13894 (*vec_extractv2si_1): Ditto.
13896 2020-02-20 Peter Bergner <bergner@linux.ibm.com>
13899 * config/rs6000/rs6000.c (rs6000_legitimate_address_p): Handle VSX
13902 2020-02-20 Martin Liska <mliska@suse.cz>
13904 PR translation/93831
13905 * config/darwin.c (darwin_override_options): Change 64b to 64-bit mode.
13907 2020-02-20 Martin Liska <mliska@suse.cz>
13909 PR translation/93830
13910 * common/config/avr/avr-common.c: Remote trailing "|".
13912 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13914 * collect2.c (maybe_run_lto_and_relink): Fix typo in
13917 2020-02-19 Richard Sandiford <richard.sandiford@arm.com>
13919 PR tree-optimization/93767
13920 * tree-vect-data-refs.c (vect_compile_time_alias): Remove the
13921 access-size bias from the offset calculations for negative strides.
13923 2020-02-19 Bernd Edlinger <bernd.edlinger@hotmail.de>
13925 * collect2.c (c_file, o_file): Make const again.
13926 (ldout,lderrout, dump_ld_file): Remove.
13927 (tool_cleanup): Avoid calling not signal-safe functions.
13928 (maybe_run_lto_and_relink): Avoid possible signal handler
13929 access to unintialzed memory (lto_o_files).
13930 (main): Avoid leaking temp files in $TMPDIR.
13931 Initialize c_file/o_file with concat, which avoids exposing
13932 uninitialized memory to signal handler, which calls unlink(!).
13933 Avoid calling maybe_unlink when the main function returns,
13934 since the atexit handler is already doing this.
13935 * collect2.h (dump_ld_file, ldout, lderrout): Remove.
13937 2020-02-19 Martin Jambor <mjambor@suse.cz>
13939 PR tree-optimization/93776
13940 * tree-sra.c (create_access): Do not create zero size accesses.
13941 (get_access_for_expr): Do not search for zero sized accesses.
13943 2020-02-19 Martin Jambor <mjambor@suse.cz>
13945 PR tree-optimization/93667
13946 * tree-sra.c (scalarizable_type_p): Return false if record fields
13947 do not follow wach other.
13949 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
13951 * config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
13952 rather than fmv.x.s/fmv.s.x.
13954 2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
13956 * config/aarch64/aarch64-simd-builtins.def
13957 (intrinsic_vec_smult_lo_): New.
13958 (intrinsic_vec_umult_lo_): Likewise.
13959 (vec_widen_smult_hi_): Likewise.
13960 (vec_widen_umult_hi_): Likewise.
13961 * config/aarch64/aarch64-simd.md
13962 (aarch64_intrinsic_vec_<su>mult_lo_<mode>): New.
13963 * config/aarch64/arm_neon.h (vmull_high_s8): Use intrinsics.
13964 (vmull_high_s16): Likewise.
13965 (vmull_high_s32): Likewise.
13966 (vmull_high_u8): Likewise.
13967 (vmull_high_u16): Likewise.
13968 (vmull_high_u32): Likewise.
13969 (vmull_s8): Likewise.
13970 (vmull_s16): Likewise.
13971 (vmull_s32): Likewise.
13972 (vmull_u8): Likewise.
13973 (vmull_u16): Likewise.
13974 (vmull_u32): Likewise.
13976 2020-02-18 Martin Liska <mliska@suse.cz>
13978 * value-prof.c (stream_out_histogram_value): Restore LTO PGO
13979 bootstrap by missing removal of invalid sanity check.
13981 2020-02-18 Martin Liska <mliska@suse.cz>
13984 * ipa-icf-gimple.c (func_checker::compare_gimple_assign):
13985 Always compare LHS of gimple_assign.
13987 2020-02-18 Martin Liska <mliska@suse.cz>
13990 * cgraph.c (cgraph_node::verify_node): Verify MALLOC attribute
13991 and return type of functions.
13992 * ipa-param-manipulation.c (ipa_param_adjustments::adjust_decl):
13993 Drop MALLOC attribute for void functions.
13994 * ipa-pure-const.c (funct_state_summary_t::duplicate): Drop
13995 malloc_state for a new VOID clone.
13997 2020-02-18 Martin Liska <mliska@suse.cz>
14000 * common.opt: Add -fprofile-reproducibility.
14001 * doc/invoke.texi: Document it.
14002 * value-prof.c (dump_histogram_value):
14003 Document and support behavior for counters[0]
14004 being a negative value.
14005 (get_nth_most_common_value): Handle negative
14006 counters[0] in respect to flag_profile_reproducible.
14008 2020-02-18 Jakub Jelinek <jakub@redhat.com>
14011 * cgraph.c (verify_speculative_call): Use speculative_id instead of
14012 speculative_uid in messages. Remove trailing whitespace from error
14013 message. Use num_speculative_call_targets instead of
14014 num_speculative_targets in a message.
14015 (cgraph_node::verify_node): Use call_stmt instead of cal_stmt in
14016 edge messages and stmt instead of cal_stmt in reference message.
14018 PR tree-optimization/93780
14019 * tree-ssa.c (non_rewritable_lvalue_p): Check valid_vector_subparts_p
14020 before calling build_vector_type.
14021 (execute_update_addresses_taken): Likewise.
14024 * params.opt (-param=ipa-max-switch-predicate-bounds=): Fix help
14025 typo, functoin -> function.
14026 * tree.c (free_lang_data_in_decl): Fix comment typo,
14027 functoin -> function.
14028 * ipa-visibility.c (cgraph_externally_visible_p): Likewise.
14030 2020-02-17 David Malcolm <dmalcolm@redhat.com>
14032 * diagnostic.c (print_any_cwe): Don't call get_cwe_url if URLs
14034 (print_option_information): Don't call get_option_url if URLs
14037 2020-02-17 Alexandre Oliva <oliva@adacore.com>
14039 * tree-emutls.c (new_emutls_decl, emutls_common_1): Complete
14040 handling of register_common-less targets.
14042 2020-02-17 Martin Liska <mliska@suse.cz>
14045 * ipa-devirt.c (odr_types_equivalent_p): Fix grammar.
14047 2020-02-17 Martin Liska <mliska@suse.cz>
14049 PR translation/93755
14050 * config/rs6000/rs6000.c (rs6000_option_override_internal):
14053 2020-02-17 Martin Liska <mliska@suse.cz>
14056 * config/rx/elf.opt: Fix typo.
14058 2020-02-17 Richard Biener <rguenther@suse.de>
14061 * opts-global.c (print_ignored_options): Use inform and
14064 2020-02-17 Jiufu Guo <guojiufu@linux.ibm.com>
14067 * config/rs6000/rs6000.md (untyped_call): Add emit_clobber.
14069 2020-02-16 Uroš Bizjak <ubizjak@gmail.com>
14072 * config/i386/i386.md (atan2xf3): Swap operands 1 and 2.
14073 (atan2<mode>3): Update operand order in the call to gen_atan2xf3.
14075 2020-02-15 Jason Merrill <jason@redhat.com>
14077 * doc/invoke.texi (C Dialect Options): Add -std=c++20.
14079 2020-02-15 Jakub Jelinek <jakub@redhat.com>
14081 PR tree-optimization/93744
14082 * match.pd (((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0,
14083 A - ((A - B) & -(C cmp D)) -> (C cmp D) ? B : A,
14084 A + ((B - A) & -(C cmp D)) -> (C cmp D) ? B : A): For GENERIC, make
14085 sure @2 in the first and @1 in the other patterns has no side-effects.
14087 2020-02-15 David Malcolm <dmalcolm@redhat.com>
14088 Bernd Edlinger <bernd.edlinger@hotmail.de>
14092 * config.in (DIAGNOSTICS_URLS_DEFAULT): New define.
14093 * configure.ac (--with-diagnostics-urls): New configuration
14094 option, based on --with-diagnostics-color.
14095 (DIAGNOSTICS_URLS_DEFAULT): New define.
14096 * config.h: Regenerate.
14097 * configure: Regenerate.
14098 * diagnostic.c (diagnostic_urls_init): Handle -1 for
14099 DIAGNOSTICS_URLS_DEFAULT from configure-time
14100 --with-diagnostics-urls=auto-if-env by querying for a GCC_URLS
14101 and TERM_URLS environment variable.
14102 * diagnostic-url.h (diagnostic_url_format): New enum type.
14103 (diagnostic_urls_enabled_p): rename to...
14104 (determine_url_format): ... this, and change return type.
14105 * diagnostic-color.c (parse_env_vars_for_urls): New helper function.
14106 (auto_enable_urls): Disable URLs on xfce4-terminal, gnome-terminal,
14107 the linux console, and mingw.
14108 (diagnostic_urls_enabled_p): rename to...
14109 (determine_url_format): ... this, and adjust.
14110 * pretty-print.h (pretty_printer::show_urls): rename to...
14111 (pretty_printer::url_format): ... this, and change to enum.
14112 * pretty-print.c (pretty_printer::pretty_printer,
14113 pp_begin_url, pp_end_url, test_urls): Adjust.
14114 * doc/install.texi (--with-diagnostics-urls): Document the new
14115 configuration option.
14116 (--with-diagnostics-color): Document the existing interaction
14117 with GCC_COLORS better.
14118 * doc/invoke.texi (-fdiagnostics-urls): Add GCC_URLS and TERM_URLS
14119 vindex reference. Update description of defaults based on the above.
14120 (-fdiagnostics-color): Update description of how -fdiagnostics-color
14121 interacts with GCC_COLORS.
14123 2020-02-14 Eric Botcazou <ebotcazou@adacore.com>
14126 * config/sparc/sparc.c (eligible_for_call_delay): Test HAVE_GNU_LD in
14127 conjunction with TARGET_GNU_TLS in early return.
14129 2020-02-14 Alexander Monakov <amonakov@ispras.ru>
14131 * rtlanal.c (rtx_cost): Handle a SET up front. Avoid division if
14132 the mode is not wider than UNITS_PER_WORD.
14134 2020-02-14 Martin Jambor <mjambor@suse.cz>
14136 PR tree-optimization/93516
14137 * tree-sra.c (propagate_subaccesses_from_rhs): Do not create
14138 access of the same type as the parent.
14139 (propagate_subaccesses_from_lhs): Likewise.
14141 2020-02-14 Hongtao Liu <hongtao.liu@intel.com>
14144 * config/i386/avx512vbmi2intrin.h
14145 (_mm512_shrdi_epi16, _mm512_mask_shrdi_epi16,
14146 _mm512_maskz_shrdi_epi16, _mm512_shrdi_epi32,
14147 _mm512_mask_shrdi_epi32, _mm512_maskz_shrdi_epi32,
14148 _m512_shrdi_epi64, _m512_mask_shrdi_epi64,
14149 _m512_maskz_shrdi_epi64, _mm512_shldi_epi16,
14150 _mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16,
14151 _mm512_shldi_epi32, _mm512_mask_shldi_epi32,
14152 _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
14153 _mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): Fix typo
14154 of lacking a closing parenthesis.
14155 * config/i386/avx512vbmi2vlintrin.h
14156 (_mm256_shrdi_epi16, _mm256_mask_shrdi_epi16,
14157 _mm256_maskz_shrdi_epi16, _mm256_shrdi_epi32,
14158 _mm256_mask_shrdi_epi32, _mm256_maskz_shrdi_epi32,
14159 _m256_shrdi_epi64, _m256_mask_shrdi_epi64,
14160 _m256_maskz_shrdi_epi64, _mm256_shldi_epi16,
14161 _mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
14162 _mm256_shldi_epi32, _mm256_mask_shldi_epi32,
14163 _mm256_maskz_shldi_epi32, _mm256_shldi_epi64,
14164 _mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64,
14165 _mm_shrdi_epi16, _mm_mask_shrdi_epi16,
14166 _mm_maskz_shrdi_epi16, _mm_shrdi_epi32,
14167 _mm_mask_shrdi_epi32, _mm_maskz_shrdi_epi32,
14168 _mm_shrdi_epi64, _mm_mask_shrdi_epi64,
14169 _m_maskz_shrdi_epi64, _mm_shldi_epi16,
14170 _mm_mask_shldi_epi16, _mm_maskz_shldi_epi16,
14171 _mm_shldi_epi32, _mm_mask_shldi_epi32,
14172 _mm_maskz_shldi_epi32, _mm_shldi_epi64,
14173 _mm_mask_shldi_epi64, _mm_maskz_shldi_epi64): Ditto.
14175 2020-02-13 H.J. Lu <hongjiu.lu@intel.com>
14178 * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
14179 the target function entry.
14181 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
14183 * common/config/arc/arc-common.c (arc_option_optimization_table):
14184 Disable if-conversion step when optimized for size.
14186 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
14188 * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
14189 R12-R15 are always in ARCOMPACT16_REGS register class.
14190 * config/arc/arc.opt (mq-class): Deprecate.
14191 * config/arc/constraint.md ("q"): Remove dependency on mq-class
14193 * doc/invoke.texi (mq-class): Update text.
14194 * common/config/arc/arc-common.c (arc_option_optimization_table):
14197 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
14199 * config/arc/arc.c (arc_insn_cost): New function.
14200 (TARGET_INSN_COST): Define.
14201 * config/arc/arc.md (cost): New attribute.
14202 (add_n): Use arc_nonmemory_operand.
14203 (ashlsi3_insn): Likewise, also update constraints.
14204 (ashrsi3_insn): Likewise.
14205 (rotrsi3): Likewise.
14206 (add_shift): Likewise.
14207 * config/arc/predicates.md (arc_nonmemory_operand): New predicate.
14209 2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
14211 * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
14213 (umulsidi_600): Likewise.
14215 2020-02-13 Jakub Jelinek <jakub@redhat.com>
14218 * config/i386/avx512bitalgintrin.h (_mm512_mask_popcnt_epi8,
14219 _mm512_mask_popcnt_epi16, _mm256_mask_popcnt_epi8,
14220 _mm256_mask_popcnt_epi16, _mm_mask_popcnt_epi8,
14221 _mm_mask_popcnt_epi16): Rename __B argument to __A and __A to __W,
14222 pass __A to the builtin followed by __W instead of __A followed by
14224 * config/i386/avx512vpopcntdqintrin.h (_mm512_mask_popcnt_epi32,
14225 _mm512_mask_popcnt_epi64): Likewise.
14226 * config/i386/avx512vpopcntdqvlintrin.h (_mm_mask_popcnt_epi32,
14227 _mm256_mask_popcnt_epi32, _mm_mask_popcnt_epi64,
14228 _mm256_mask_popcnt_epi64): Likewise.
14230 PR tree-optimization/93582
14231 * fold-const.h (shift_bytes_in_array_left,
14232 shift_bytes_in_array_right): Declare.
14233 * fold-const.c (shift_bytes_in_array_left,
14234 shift_bytes_in_array_right): New function, moved from
14235 gimple-ssa-store-merging.c, no longer static.
14236 * gimple-ssa-store-merging.c (shift_bytes_in_array): Move
14237 to gimple-ssa-store-merging.c and rename to shift_bytes_in_array_left.
14238 (shift_bytes_in_array_right): Move to gimple-ssa-store-merging.c.
14239 (encode_tree_to_bitpos): Use shift_bytes_in_array_left instead of
14240 shift_bytes_in_array.
14241 (verify_shift_bytes_in_array): Rename to ...
14242 (verify_shift_bytes_in_array_left): ... this. Use
14243 shift_bytes_in_array_left instead of shift_bytes_in_array.
14244 (store_merging_c_tests): Call verify_shift_bytes_in_array_left
14245 instead of verify_shift_bytes_in_array.
14246 * tree-ssa-sccvn.c (vn_reference_lookup_3): For native_encode_expr
14247 / native_interpret_expr where the store covers all needed bits,
14248 punt on PDP-endian, otherwise allow all involved offsets and sizes
14249 not to be byte-aligned.
14252 * config/i386/sse.md (k<code><mode>): Drop mode from last operand and
14253 use const_0_to_255_operand predicate instead of immediate_operand.
14254 (avx512dq_fpclass<mode><mask_scalar_merge_name>,
14255 avx512dq_vmfpclass<mode><mask_scalar_merge_name>,
14256 vgf2p8affineinvqb_<mode><mask_name>,
14257 vgf2p8affineqb_<mode><mask_name>): Drop mode from
14258 const_0_to_255_operand predicated operands.
14260 2020-02-12 Jeff Law <law@redhat.com>
14262 * config/h8300/h8300.md (comparison shortening peepholes): Use
14263 a mode iterator to merge the HImode and SImode peepholes.
14265 2020-02-12 Jakub Jelinek <jakub@redhat.com>
14267 PR middle-end/93663
14268 * real.c (is_even): Make static. Function comment fix.
14269 (is_halfway_below): Make static, don't assert R is not inf/nan,
14270 instead return false for those. Small formatting fixes.
14272 2020-02-12 Martin Sebor <msebor@redhat.com>
14274 PR middle-end/93646
14275 * tree-ssa-strlen.c (handle_builtin_stxncpy): Rename...
14276 (handle_builtin_stxncpy_strncat): ...to this. Change first argument.
14277 Issue only -Wstringop-overflow strncat, never -Wstringop-truncation.
14278 (strlen_check_and_optimize_call): Adjust callee name.
14280 2020-02-12 Jeff Law <law@redhat.com>
14282 * config/h8300/h8300.md (comparison shortening peepholes): Drop
14283 (and (xor)) variant. Combine other two into single peephole.
14285 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
14287 PR rtl-optimization/93565
14288 * config/aarch64/aarch64.c (aarch64_rtx_costs): Add CTZ costs.
14290 2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
14292 * config/aarch64/aarch64-simd.md
14293 (aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
14294 * config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
14295 generating separate ADDV and zero_extend patterns.
14296 * config/aarch64/iterators.md (VDQV_E): New iterator.
14298 2020-02-12 Jeff Law <law@redhat.com>
14300 * config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,
14301 expanders, splits, etc.
14302 (movmd_internal_<mode>, movmd splitter, movstr, movsd): Likewise.
14303 (stpcpy_internal_<mode>, stpcpy splitter): Likewise.
14304 (peepholes to convert QI/HI mode pushes to SI mode pushes): Likewise.
14305 * config/h8300/h8300.c (h8300_swap_into_er6): Remove unused function.
14306 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise
14307 * config/h8300/h8300-protos.h (h8300_swap_into_er6): Remove unused
14308 function prototype.
14309 (h8300_swap_out_of_er6, h8sx_emit_movmd): Likewise.
14311 2020-02-12 Jakub Jelinek <jakub@redhat.com>
14314 * config/i386/sse.md (VI48F_256_DQ): New mode iterator.
14315 (avx512vl_vextractf128<mode>): Use it instead of VI48F_256. Remove
14316 TARGET_AVX512DQ from condition.
14317 (vec_extract_lo_<mode><mask_name>): Use <mask_avx512dq_condition>
14318 instead of <mask_mode512bit_condition> in condition. If
14319 TARGET_AVX512DQ is false, emit vextract*64x4 instead of
14321 (vec_extract_lo_<mode><mask_name>): Drop <mask_avx512dq_condition>
14324 2020-02-12 Kewen Lin <linkw@gcc.gnu.org>
14327 * ira.c (combine_and_move_insns): Skip multiple_sets def_insn.
14329 2020-02-12 Segher Boessenkool <segher@kernel.crashing.org>
14331 * config/rs6000/rs6000.c (rs6000_debug_print_mode): Don't use sizeof
14332 where strlen is more legible.
14333 (rs6000_builtin_vectorized_libmass): Ditto.
14334 (rs6000_print_options_internal): Ditto.
14336 2020-02-11 Martin Sebor <msebor@redhat.com>
14338 PR tree-optimization/93683
14339 * tree-ssa-alias.c (stmt_kills_ref_p): Avoid using LHS when not set.
14341 2020-02-11 Michael Meissner <meissner@linux.ibm.com>
14343 * config/rs6000/predicates.md (cint34_operand): Rename the
14344 -mprefixed-addr option to be -mprefixed.
14345 * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Rename
14346 the -mprefixed-addr option to be -mprefixed.
14347 (OTHER_FUTURE_MASKS): Likewise.
14348 (POWERPC_MASKS): Likewise.
14349 * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
14350 the -mprefixed-addr option to be -mprefixed. Change error
14351 messages to refer to -mprefixed.
14352 (num_insns_constant_gpr): Rename the -mprefixed-addr option to be
14354 (rs6000_legitimate_offset_address_p): Likewise.
14355 (rs6000_mode_dependent_address): Likewise.
14356 (rs6000_opt_masks): Change the spelling of "-mprefixed-addr" to be
14357 "-mprefixed" for target attributes and pragmas.
14358 (address_to_insn_form): Rename the -mprefixed-addr option to be
14360 (rs6000_adjust_insn_length): Likewise.
14361 * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Rename the
14362 -mprefixed-addr option to be -mprefixed.
14363 (ASM_OUTPUT_OPCODE): Likewise.
14364 * config/rs6000/rs6000.md (prefixed insn attribute): Rename the
14365 -mprefixed-addr option to be -mprefixed.
14366 * config/rs6000/rs6000.opt (-mprefixed): Rename the
14367 -mprefixed-addr option to be prefixed. Change the option from
14368 being undocumented to being documented.
14369 * doc/invoke.texi (RS/6000 and PowerPC Options): Document the
14370 -mprefixed option. Update the -mpcrel documentation to mention
14373 2020-02-11 Hans-Peter Nilsson <hp@axis.com>
14375 * ira-conflicts.c (print_hard_reg_set): Correct output for sets
14376 including FIRST_PSEUDO_REGISTER - 1.
14377 * ira-color.c (print_hard_reg_set): Ditto.
14379 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14381 * config/arm/arm-builtins.c (enum arm_type_qualifiers):
14382 (USTERNOP_QUALIFIERS): New define.
14383 (USMAC_LANE_QUADTUP_QUALIFIERS): New define.
14384 (SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
14385 (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
14386 (arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
14387 * config/arm/arm_neon.h (vusdot_s32): New.
14388 (vusdot_lane_s32): New.
14389 (vusdotq_lane_s32): New.
14390 (vsudot_lane_s32): New.
14391 (vsudotq_lane_s32): New.
14392 * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
14393 * config/arm/iterators.md (DOTPROD_I8MM): New.
14394 (sup, opsuffix): Add <us/su>.
14395 * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
14396 * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
14398 2020-02-11 Richard Biener <rguenther@suse.de>
14400 PR tree-optimization/93661
14401 PR tree-optimization/93662
14402 * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard
14403 tree_to_poly_int64.
14404 * tree-sra.c (get_access_for_expr): Likewise.
14406 2020-02-10 Jakub Jelinek <jakub@redhat.com>
14409 * config/i386/sse.md (VI_256_AVX2): New mode iterator.
14410 (vcond_mask_<mode><sseintvecmodelower>): Use it instead of VI_256.
14411 Change condition from TARGET_AVX2 to TARGET_AVX.
14413 2020-02-10 Iain Sandoe <iain@sandoe.co.uk>
14416 * config/darwin-c.c (darwin_cfstring_ref_p): Fix up last
14417 argument of strncmp.
14419 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
14421 Try to generate zero-based comparisons.
14422 * config/cris/cris.c (cris_reduce_compare): New function.
14423 * config/cris/cris-protos.h (cris_reduce_compare): Add prototype.
14424 * config/cris/cris.md ("cbranch<mode>4", "cbranchdi4", "cstoredi4")
14425 (cstore<mode>4"): Apply cris_reduce_compare in expanders.
14427 2020-02-10 Richard Earnshaw <rearnsha@arm.com>
14430 * config/arm/arm.md (movsi_compare0): Allow SP as a source register
14431 in Thumb state and also as a destination in Arm state. Add T16
14434 2020-02-10 Hans-Peter Nilsson <hp@axis.com>
14436 * md.texi (Define Subst): Match closing paren in example.
14438 2020-02-10 Jakub Jelinek <jakub@redhat.com>
14442 * config/i386/i386.c (x86_64_elf_section_type_flags): Fix up last
14443 arguments of strncmp.
14445 2020-02-10 Feng Xue <fxue@os.amperecomputing.com>
14448 * ipa-cp.c (ipcp_lattice::add_value): Add source with same call edge
14449 but different source value.
14450 (adjust_callers_for_value_intersection): New function.
14451 (gather_edges_for_value): Adjust order of callers to let a
14452 non-self-recursive caller be the first element.
14453 (self_recursive_pass_through_p): Add a new parameter "simple", and
14454 check generalized self-recursive pass-through jump function.
14455 (self_recursive_agg_pass_through_p): Likewise.
14456 (find_more_scalar_values_for_callers_subset): Compute value from
14457 pass-through jump function for self-recursive.
14458 (intersect_with_plats): Cleanup previous implementation code for value
14459 itersection with self-recursive call edge.
14460 (intersect_with_agg_replacements): Likewise.
14461 (intersect_aggregates_with_edge): Deduce value from pass-through jump
14462 function for self-recursive call edge. Cleanup previous implementation
14463 code for value intersection with self-recursive call edge.
14464 (decide_whether_version_node): Remove dead callers and adjust order
14465 to let a non-self-recursive caller be the first element.
14467 2020-02-09 Uroš Bizjak <ubizjak@gmail.com>
14469 * recog.c: Move pass_split_before_sched2 code in front of
14470 pass_split_before_regstack.
14471 (pass_data_split_before_sched2): Rename pass to split3 from split4.
14472 (pass_data_split_before_regstack): Rename pass to split4 from split3.
14473 (rest_of_handle_split_before_sched2): Remove.
14474 (pass_split_before_sched2::execute): Unconditionally call
14476 (enable_split_before_sched2): New function.
14477 (pass_split_before_sched2::gate): Use enable_split_before_sched2.
14478 (pass_split_before_regstack::gate): Ditto.
14479 * config/nds32/nds32.c (nds32_split_double_word_load_store_p):
14480 Update name check for renamed split4 pass.
14481 * config/sh/sh.c (register_sh_passes): Update pass insertion
14482 point for renamed split4 pass.
14484 2020-02-09 Jakub Jelinek <jakub@redhat.com>
14486 * gimplify.c (gimplify_adjust_omp_clauses_1): Promote
14487 DECL_IN_CONSTANT_POOL variables into "omp declare target" to avoid
14488 copying them around between host and target.
14490 2020-02-08 Andrew Pinski <apinski@marvell.com>
14493 * config/aarch64/aarch64-simd.md (movmisalign<mode>): Check
14494 STRICT_ALIGNMENT also.
14496 2020-02-08 Jim Wilson <jimw@sifive.com>
14499 * config/riscv/riscv.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
14501 2020-02-08 Uroš Bizjak <ubizjak@gmail.com>
14502 Jakub Jelinek <jakub@redhat.com>
14505 * config/i386/i386.h (CALL_USED_REGISTERS): Make
14506 xmm16-xmm31 call-used even in 64-bit ms-abi.
14508 2020-02-07 Dennis Zhang <dennis.zhang@arm.com>
14510 * config/aarch64/aarch64-simd-builtins.def (simd_smmla): New entry.
14511 (simd_ummla, simd_usmmla): Likewise.
14512 * config/aarch64/aarch64-simd.md (aarch64_simd_<sur>mmlav16qi): New.
14513 * config/aarch64/arm_neon.h (vmmlaq_s32, vmmlaq_u32): New.
14514 (vusmmlaq_s32): New.
14516 2020-02-07 Richard Biener <rguenther@suse.de>
14518 PR middle-end/93519
14519 * tree-inline.c (fold_marked_statements): Do a PRE walk,
14520 skipping unreachable regions.
14521 (optimize_inline_calls): Skip folding stmts when we didn't
14524 2020-02-07 H.J. Lu <hongjiu.lu@intel.com>
14527 * config/i386/i386.c (function_arg_ms_64): Add a type argument.
14528 Don't return aggregates with only SFmode and DFmode in SSE
14530 (ix86_function_arg): Pass arg.type to function_arg_ms_64.
14532 2020-02-07 Jakub Jelinek <jakub@redhat.com>
14535 * config/rs6000/rs6000-logue.c
14536 (rs6000_emit_probe_stack_range_stack_clash): Always use gen_add3_insn,
14537 if it fails, move rs into end_addr and retry. Add
14538 REG_FRAME_RELATED_EXPR note whenever it returns more than one insn or
14539 the insn pattern doesn't describe well what exactly happens to
14543 * config/i386/predicates.md (avx_identity_operand): Remove.
14544 * config/i386/sse.md (*avx_vec_concat<mode>_1): Remove.
14545 (avx_<castmode><avxsizesuffix>_<castmode>,
14546 avx512f_<castmode><avxsizesuffix>_256<castmode>): Change patterns to
14547 a VEC_CONCAT of the operand and UNSPEC_CAST.
14548 (avx512f_<castmode><avxsizesuffix>_<castmode>): Change pattern to
14549 a VEC_CONCAT of VEC_CONCAT of the operand and UNSPEC_CAST with
14553 * config/i386/i386.c (ix86_lea_outperforms): Make sure to clear
14554 recog_data.insn if distance_non_agu_define changed it.
14556 2020-02-06 Michael Meissner <meissner@linux.ibm.com>
14559 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0
14560 we only had X-FORM (reg+reg) addressing for vectors. Also before
14561 ISA 3.0, we only had X-FORM addressing for scalars in the
14562 traditional Altivec registers.
14564 2020-02-06 <zhongyunde@huawei.com>
14565 Vladimir Makarov <vmakarov@redhat.com>
14567 PR rtl-optimization/93561
14568 * lra-assigns.c (spill_for): Check that tested hard regno is not out of
14569 hard register range.
14571 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14573 * config/aarch64/aarch64.md (aarch64_movk<mode>): Add a type
14576 2020-02-06 Segher Boessenkool <segher@kernel.crashing.org>
14578 * config/rs6000/rs6000.c (rs6000_emit_set_long_const): Handle the case
14579 where the low and the high 32 bits are equal to each other specially,
14580 with an rldimi instruction.
14582 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14584 * config/arm/arm-cpus.in: Set profile M for armv8.1-m.main.
14586 2020-02-06 Mihail Ionescu <mihail.ionescu@arm.com>
14588 * config/arm/arm-tables.opt: Regenerate.
14590 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14593 * config/aarch64/aarch64-protos.h (aarch64_movk_shift): Declare.
14594 * config/aarch64/aarch64.c (aarch64_movk_shift): New function.
14595 * config/aarch64/aarch64.md (aarch64_movk<mode>): New pattern.
14597 2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
14599 PR rtl-optimization/87763
14600 * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
14602 2020-02-06 Delia Burduv <delia.burduv@arm.com>
14604 * config/aarch64/aarch64-simd-builtins.def
14605 (bfmlaq): New built-in function.
14606 (bfmlalb): New built-in function.
14607 (bfmlalt): New built-in function.
14608 (bfmlalb_lane): New built-in function.
14609 (bfmlalt_lane): New built-in function.
14610 * config/aarch64/aarch64-simd.md
14611 (aarch64_bfmmlaqv4sf): New pattern.
14612 (aarch64_bfmlal<bt>v4sf): New pattern.
14613 (aarch64_bfmlal<bt>_lane<q>v4sf): New pattern.
14614 * config/aarch64/arm_neon.h (vbfmmlaq_f32): New intrinsic.
14615 (vbfmlalbq_f32): New intrinsic.
14616 (vbfmlaltq_f32): New intrinsic.
14617 (vbfmlalbq_lane_f32): New intrinsic.
14618 (vbfmlaltq_lane_f32): New intrinsic.
14619 (vbfmlalbq_laneq_f32): New intrinsic.
14620 (vbfmlaltq_laneq_f32): New intrinsic.
14621 * config/aarch64/iterators.md (BF_MLA): New int iterator.
14622 (bt): New int attribute.
14624 2020-02-06 Uroš Bizjak <ubizjak@gmail.com>
14626 * config/i386/i386.md (*pushtf): Emit "#" instead of
14627 calling gcc_unreachable in insn output.
14630 (*pushsf_rex64): Ditto for alternatives other than 1.
14631 (*pushsf): Ditto for alternatives other than 1.
14633 2020-02-06 Martin Liska <mliska@suse.cz>
14635 PR gcov-profile/91971
14636 PR gcov-profile/93466
14637 * coverage.c (coverage_init): Revert mangling of
14638 path into filename. It can lead to huge filename length.
14639 Creation of subfolders seem more natural.
14641 2020-02-06 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14644 * config/arm/arm.c (arm_block_arith_comp_libfuncs_for_mode): New.
14645 (arm_init_libfuncs): Add BFmode support to block spurious BF libfuncs.
14646 Use arm_block_arith_comp_libfuncs_for_mode for HFmode.
14648 2020-02-06 Jakub Jelinek <jakub@redhat.com>
14651 * config/i386/predicates.md (avx_identity_operand): New predicate.
14652 * config/i386/sse.md (*avx_vec_concat<mode>_1): New
14653 define_insn_and_split.
14656 * omp-low.c (use_pointer_for_field): For nested constructs, also
14657 look for map clauses on target construct.
14658 (scan_omp_1_stmt) <case GIMPLE_OMP_TARGET>: Bump temporarily
14659 taskreg_nesting_level.
14662 * gimplify.c (gimplify_scan_omp_clauses) <do_notice>: If adding
14663 shared clause, call omp_notice_variable on outer context if any.
14665 2020-02-05 Jason Merrill <jason@redhat.com>
14668 * symtab.c (symtab_node::nonzero_address): A DECL_COMDAT decl has
14669 non-zero address even if weak and not yet defined.
14671 2020-02-05 Martin Sebor <msebor@redhat.com>
14673 PR tree-optimization/92765
14674 * gimple-fold.c (get_range_strlen_tree): Handle MEM_REF and PARM_DECL.
14675 * tree-ssa-strlen.c (compute_string_length): Remove.
14676 (determine_min_objsize): Remove.
14677 (get_len_or_size): Add an argument. Call get_range_strlen_dynamic.
14678 Avoid using type size as the upper bound on string length.
14679 (handle_builtin_string_cmp): Add an argument. Adjust.
14680 (strlen_check_and_optimize_call): Pass additional argument to
14681 handle_builtin_string_cmp.
14683 2020-02-05 Uroš Bizjak <ubizjak@gmail.com>
14685 * config/i386/i386.md (*pushdi2_rex64 peephole2): Remove.
14686 (*pushdi2_rex64 peephole2): Unconditionally split after
14687 epilogue_completed.
14688 (*ashl<mode>3_doubleword): Ditto.
14689 (*<shift_insn><mode>3_doubleword): Ditto.
14691 2020-02-05 Michael Meissner <meissner@linux.ibm.com>
14694 * config/rs6000/rs6000.c (get_vector_offset): Fix
14696 2020-02-05 Andrew Stubbs <ams@codesourcery.com>
14698 * config/gcn/t-gcn-hsa (MULTILIB_OPTIONS): Use / not space.
14700 2020-02-05 David Malcolm <dmalcolm@redhat.com>
14702 * doc/analyzer.texi
14703 (Special Functions for Debugging the Analyzer): Update description
14704 of __analyzer_dump_exploded_nodes.
14706 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14709 * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Only
14710 include sets and not clobbers in the vzeroupper pattern.
14711 * config/i386/sse.md (*avx_vzeroupper): Require in insn condition that
14712 the parallel has 17 (64-bit) or 9 (32-bit) elts.
14713 (*avx_vzeroupper_1): New define_insn_and_split.
14716 * recog.c (pass_split_after_reload::gate): For STACK_REGS targets,
14717 don't run when !optimize.
14718 (pass_split_before_regstack::gate): For STACK_REGS targets, run even
14721 2020-02-05 Richard Biener <rguenther@suse.de>
14723 PR middle-end/90648
14724 * genmatch.c (dt_node::gen_kids_1): Emit number of argument
14725 checks before matching calls.
14727 2020-02-05 Jakub Jelinek <jakub@redhat.com>
14729 * tree-ssa-alias.c (aliasing_matching_component_refs_p): Fix up
14730 function comment typo.
14732 PR middle-end/93555
14733 * omp-simd-clone.c (expand_simd_clones): If simd_clone_mangle or
14734 simd_clone_create failed when i == 0, adjust clone->nargs by
14737 2020-02-05 Martin Liska <mliska@suse.cz>
14740 * doc/invoke.texi: Document that one should
14741 not combine ASLR and -fpch.
14743 2020-02-04 Richard Biener <rguenther@suse.de>
14745 PR tree-optimization/93538
14746 * match.pd (addr EQ/NE ptr): Amend to handle &ptr->x EQ/NE ptr.
14748 2020-02-04 Richard Biener <rguenther@suse.de>
14750 PR tree-optimization/91123
14751 * tree-ssa-sccvn.c (vn_walk_cb_data::finish): New method.
14752 (vn_walk_cb_data::last_vuse): New member.
14753 (vn_walk_cb_data::saved_operands): Likewsie.
14754 (vn_walk_cb_data::~vn_walk_cb_data): Release saved_operands.
14755 (vn_walk_cb_data::push_partial_def): Use finish.
14756 (vn_reference_lookup_2): Update last_vuse and use finish if
14757 we've saved operands.
14758 (vn_reference_lookup_3): Use finish and update calls to
14759 push_partial_defs everywhere. When translating through
14760 memcpy or aggregate copies save off operands and alias-set.
14761 (eliminate_dom_walker::eliminate_stmt): Restore VN_WALKREWRITE
14762 operation for redundant store removal.
14764 2020-02-04 Richard Biener <rguenther@suse.de>
14766 PR tree-optimization/92819
14767 * tree-ssa-forwprop.c (simplify_vector_constructor): Avoid
14768 generating more stmts than before.
14770 2020-02-04 Martin Liska <mliska@suse.cz>
14772 * config/arm/arm.c (arm_gen_far_branch): Move the function
14773 outside of selftests.
14775 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14777 * config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
14778 function to adjust PC-relative vector addresses.
14779 (rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
14780 handle vectors with PC-relative addresses.
14782 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14784 * config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
14786 (hard_reg_and_mode_to_addr_mask): Delete.
14787 (rs6000_adjust_vec_address): If the original vector address
14788 was REG+REG or REG+OFFSET and the element is not zero, do the add
14789 of the elements in the original address before adding the offset
14790 for the vector element. Use address_to_insn_form to validate the
14791 address using the register being loaded, rather than guessing
14792 whether the address is a DS-FORM or DQ-FORM address.
14794 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14796 * config/rs6000/rs6000.c (get_vector_offset): New helper function
14797 to calculate the offset in memory from the start of a vector of a
14798 particular element. Add code to keep the element number in
14799 bounds if the element number is variable.
14800 (rs6000_adjust_vec_address): Move calculation of offset of the
14801 vector element to get_vector_offset.
14802 (rs6000_split_vec_extract_var): Do not do the initial AND of
14803 element here, move the code to get_vector_offset.
14805 2020-02-03 Michael Meissner <meissner@linux.ibm.com>
14807 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
14810 2020-02-03 Segher Boessenkool <segher@kernel.crashing.org>
14812 * config/rs6000/constraints.md: Improve documentation.
14814 2020-02-03 Richard Earnshaw <rearnsha@arm.com>
14817 * config/arm/t-arm: ($(srcdir)/config/arm/arm-tune.md)
14818 ($(srcdir)/config/arm/arm-tables.opt): Use move-if-change.
14820 2020-02-03 Andrew Stubbs <ams@codesourcery.com>
14822 * config.gcc: Remove "carrizo" support.
14823 * config/gcn/gcn-opts.h (processor_type): Likewise.
14824 * config/gcn/gcn.c (gcn_omp_device_kind_arch_isa): Likewise.
14825 * config/gcn/gcn.opt (gpu_type): Likewise.
14826 * config/gcn/t-omp-device: Likewise.
14828 2020-02-03 Stam Markianos-Wright <stam.markianos-wright@arm.com>
14831 * config/arm/arm-protos.h: New function arm_gen_far_branch prototype.
14832 * config/arm/arm.c (arm_gen_far_branch): New function
14833 arm_gen_far_branch.
14834 * config/arm/arm.md: Update b<cond> for Thumb2 range checks.
14836 2020-02-03 Julian Brown <julian@codesourcery.com>
14837 Tobias Burnus <tobias@codesourcery.com>
14839 * doc/invoke.texi: Update mention of OpenACC version to 2.6.
14841 2020-02-03 Jakub Jelinek <jakub@redhat.com>
14844 * config/s390/s390.md (popcounthi2_z196): Fix up expander to emit
14845 valid RTL to sum up the lowest and second lowest bytes of the popcnt
14848 2020-02-02 Vladimir Makarov <vmakarov@redhat.com>
14850 PR rtl-optimization/91333
14851 * ira-color.c (struct allocno_color_data): Add member
14853 (init_allocno_threads): Set the member up.
14854 (bucket_allocno_compare_func): Add compare hard reg
14857 2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
14859 nios2: Support for GOT-relative DW_EH_PE_datarel encoding.
14861 * configure.ac [nios2-*-*]: Check HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14862 * config.in: Regenerated.
14863 * configure: Regenerated.
14864 * config/nios2/nios2.h (ASM_PREFERRED_EH_DATA_FORMAT): Fix handling
14865 for PIC when HAVE_AS_NIOS2_GOTOFF_RELOCATION.
14866 (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): New.
14868 2020-02-01 Andrew Burgess <andrew.burgess@embecosm.com>
14870 * configure: Regenerate.
14872 2020-01-31 Vladimir Makarov <vmakarov@redhat.com>
14874 PR rtl-optimization/91333
14875 * ira-color.c (bucket_allocno_compare_func): Move conflict hard
14876 reg preferences comparison up.
14878 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14880 * config/aarch64/aarch64.h (TARGET_SVE_BF16): New macro.
14881 * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtnt): Move to
14882 aarch64-sve-builtins-base.h.
14883 * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtnt): Move to
14884 aarch64-sve-builtins-base.cc.
14885 * config/aarch64/aarch64-sve-builtins-base.h (svbfdot, svbfdot_lane)
14886 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14887 (svcvtnt): Declare.
14888 * config/aarch64/aarch64-sve-builtins-base.cc (svbfdot, svbfdot_lane)
14889 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14890 (svcvtnt): New functions.
14891 * config/aarch64/aarch64-sve-builtins-base.def (svbfdot, svbfdot_lane)
14892 (svbfmlalb, svbfmlalb_lane, svbfmlalt, svbfmlalt_lane, svbfmmla)
14893 (svcvtnt): New functions.
14894 (svcvt): Add a form that converts f32 to bf16.
14895 * config/aarch64/aarch64-sve-builtins-shapes.h (ternary_bfloat)
14896 (ternary_bfloat_lane, ternary_bfloat_lanex2, ternary_bfloat_opt_n):
14898 * config/aarch64/aarch64-sve-builtins-shapes.cc (parse_element_type):
14899 Treat B as bfloat16_t.
14900 (ternary_bfloat_lane_base): New class.
14901 (ternary_bfloat_def): Likewise.
14902 (ternary_bfloat): New shape.
14903 (ternary_bfloat_lane_def): New class.
14904 (ternary_bfloat_lane): New shape.
14905 (ternary_bfloat_lanex2_def): New class.
14906 (ternary_bfloat_lanex2): New shape.
14907 (ternary_bfloat_opt_n_def): New class.
14908 (ternary_bfloat_opt_n): New shape.
14909 * config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_bfloat): New macro.
14910 * config/aarch64/aarch64-sve.md (@aarch64_sve_<sve_fp_op>vnx4sf)
14911 (@aarch64_sve_<sve_fp_op>_lanevnx4sf): New patterns.
14912 (@aarch64_sve_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>)
14913 (@cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14914 (*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>): Likewise.
14915 (@aarch64_sve_cvtnt<VNx8BF_ONLY:mode>): Likewise.
14916 * config/aarch64/aarch64-sve2.md (@aarch64_sve2_cvtnt<mode>): Key
14917 the pattern off the narrow mode instead of the wider one.
14918 * config/aarch64/iterators.md (VNx8BF_ONLY): New mode iterator.
14919 (UNSPEC_BFMLALB, UNSPEC_BFMLALT, UNSPEC_BFMMLA): New unspecs.
14920 (sve_fp_op): Handle them.
14921 (SVE_BFLOAT_TERNARY_LONG): New int itertor.
14922 (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
14924 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
14926 * config/aarch64/arm_sve.h: Include arm_bf16.h.
14927 * config/aarch64/aarch64-modes.def (BF): Move definition before
14928 VECTOR_MODES. Remove separate VECTOR_MODES for V4BF and V8BF.
14929 (SVE_MODES): Handle BF modes.
14930 * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Handle
14932 (aarch64_full_sve_mode): Likewise.
14933 * config/aarch64/iterators.md (SVE_STRUCT): Add VNx16BF, VNx24BF
14935 (SVE_FULL, SVE_FULL_HSD, SVE_ALL): Add VNx8BF.
14936 (Vetype, Vesize, Vctype, VEL, Vel, VEL_INT, V128, v128, vwcore)
14937 (V_INT_EQUIV, v_int_equiv, V_FP_EQUIV, v_fp_equiv, vector_count)
14938 (insn_length, VSINGLE, vsingle, VPRED, vpred, VDOUBLE): Handle the
14940 * config/aarch64/aarch64-sve-builtins.h (TYPE_bfloat): New
14942 * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_arith): New macro.
14943 (TYPES_all_data): Add bf16.
14944 (TYPES_reinterpret1, TYPES_reinterpret): Likewise.
14945 (register_tuple_type): Increase buffer size.
14946 * config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): New type.
14947 (bf16): New type suffix.
14948 * config/aarch64/aarch64-sve-builtins-base.def (svabd, svadd, svaddv)
14949 (svcmpeq, svcmpge, svcmpgt, svcmple, svcmplt, svcmpne, svmad, svmax)
14950 (svmaxv, svmin, svminv, svmla, svmls, svmsb, svmul, svsub, svsubr):
14951 Change type from all_data to all_arith.
14952 * config/aarch64/aarch64-sve-builtins-sve2.def (svaddp, svmaxp)
14953 (svminp): Likewise.
14955 2020-01-31 Dennis Zhang <dennis.zhang@arm.com>
14956 Matthew Malcomson <matthew.malcomson@arm.com>
14957 Richard Sandiford <richard.sandiford@arm.com>
14959 * doc/invoke.texi (f32mm): Document new AArch64 -march= extension.
14960 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
14961 __ARM_FEATURE_SVE_MATMUL_INT8, __ARM_FEATURE_SVE_MATMUL_FP32 and
14962 __ARM_FEATURE_SVE_MATMUL_FP64 as appropriate. Don't define
14963 __ARM_FEATURE_MATMUL_FP64.
14964 * config/aarch64/aarch64-option-extensions.def (fp, simd, fp16)
14965 (sve): Add AARCH64_FL_F32MM to the list of extensions that should
14966 be disabled at the same time.
14967 (f32mm): New extension.
14968 * config/aarch64/aarch64.h (AARCH64_FL_F32MM): New macro.
14969 (AARCH64_FL_F64MM): Bump to the next bit up.
14970 (AARCH64_ISA_F32MM, TARGET_SVE_I8MM, TARGET_F32MM, TARGET_SVE_F32MM)
14971 (TARGET_SVE_F64MM): New macros.
14972 * config/aarch64/iterators.md (SVE_MATMULF): New mode iterator.
14973 (UNSPEC_FMMLA, UNSPEC_SMATMUL, UNSPEC_UMATMUL, UNSPEC_USMATMUL)
14974 (UNSPEC_TRN1Q, UNSPEC_TRN2Q, UNSPEC_UZP1Q, UNSPEC_UZP2Q, UNSPEC_ZIP1Q)
14975 (UNSPEC_ZIP2Q): New unspeccs.
14976 (DOTPROD_US_ONLY, PERMUTEQ, MATMUL, FMMLA): New int iterators.
14977 (optab, sur, perm_insn): Handle the new unspecs.
14978 (sve_fp_op): Handle UNSPEC_FMMLA. Resort.
14979 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use
14980 TARGET_SVE_F64MM instead of separate tests.
14981 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod<vsi2qi>): New pattern.
14982 (@aarch64_<DOTPROD_US_ONLY:sur>dot_prod_lane<vsi2qi>): Likewise.
14983 (@aarch64_sve_add_<MATMUL:optab><vsi2qi>): Likewise.
14984 (@aarch64_sve_<FMMLA:sve_fp_op><mode>): Likewise.
14985 (@aarch64_sve_<PERMUTEQ:optab><mode>): Likewise.
14986 * config/aarch64/aarch64-sve-builtins.cc (TYPES_s_float): New macro.
14987 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): Use it.
14988 (TYPES_s_signed): New macro.
14989 (TYPES_s_integer): Use it.
14990 (TYPES_d_float): New macro.
14991 (TYPES_d_data): Use it.
14992 * config/aarch64/aarch64-sve-builtins-shapes.h (mmla): Declare.
14993 (ternary_intq_uintq_lane, ternary_intq_uintq_opt_n, ternary_uintq_intq)
14994 (ternary_uintq_intq_lane, ternary_uintq_intq_opt_n): Likewise.
14995 * config/aarch64/aarch64-sve-builtins-shapes.cc (mmla_def): New class.
14996 (svmmla): New shape.
14997 (ternary_resize2_opt_n_base): Add TYPE_CLASS2 and TYPE_CLASS3
14998 template parameters.
14999 (ternary_resize2_lane_base): Likewise.
15000 (ternary_resize2_base): New class.
15001 (ternary_qq_lane_base): Likewise.
15002 (ternary_intq_uintq_lane_def): Likewise.
15003 (ternary_intq_uintq_lane): New shape.
15004 (ternary_intq_uintq_opt_n_def): New class
15005 (ternary_intq_uintq_opt_n): New shape.
15006 (ternary_qq_lane_def): Inherit from ternary_qq_lane_base.
15007 (ternary_uintq_intq_def): New class.
15008 (ternary_uintq_intq): New shape.
15009 (ternary_uintq_intq_lane_def): New class.
15010 (ternary_uintq_intq_lane): New shape.
15011 (ternary_uintq_intq_opt_n_def): New class.
15012 (ternary_uintq_intq_opt_n): New shape.
15013 * config/aarch64/aarch64-sve-builtins-base.h (svmmla, svsudot)
15014 (svsudot_lane, svtrn1q, svtrn2q, svusdot, svusdot_lane, svusmmla)
15015 (svuzp1q, svuzp2q, svzip1q, svzip2q): Declare.
15016 * config/aarch64/aarch64-sve-builtins-base.cc (svdot_lane_impl):
15018 (svdotprod_lane_impl): ...this new class.
15019 (svmmla_impl, svusdot_impl): New classes.
15020 (svdot_lane): Update to use svdotprod_lane_impl.
15021 (svmmla, svsudot, svsudot_lane, svtrn1q, svtrn2q, svusdot)
15022 (svusdot_lane, svusmmla, svuzp1q, svuzp2q, svzip1q, svzip2q): New
15024 * config/aarch64/aarch64-sve-builtins-base.def (svmmla): New base
15025 function, with no types defined.
15026 (svmmla, svusmmla, svsudot, svsudot_lane, svusdot, svusdot_lane): New
15027 AARCH64_FL_I8MM functions.
15028 (svmmla): New AARCH64_FL_F32MM function.
15029 (svld1ro): Depend only on AARCH64_FL_F64MM, not on AARCH64_FL_V8_6.
15030 (svmmla, svtrn1q, svtrn2q, svuz1q, svuz2q, svzip1q, svzip2q): New
15031 AARCH64_FL_F64MM function.
15032 (REQUIRED_EXTENSIONS):
15034 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
15036 * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
15039 2020-01-31 Uroš Bizjak <ubizjak@gmail.com>
15041 * config/i386/i386.md (*movoi_internal_avx): Do not check for
15042 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL. Remove MODE_V8SF handling.
15043 (*movti_internal): Do not check for
15044 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
15045 (*movtf_internal): Move check for TARGET_SSE2 and size optimization
15046 just after check for TARGET_AVX.
15047 (*movdf_internal): Ditto.
15048 * config/i386/mmx.md (*mov<mode>_internal): Do not check for
15049 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL.
15050 * config/i386/sse.md (mov<mode>_internal): Only check
15051 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL with V2DFmode. Move check
15052 for TARGET_SSE2 and size optimization just after check for TARGET_AVX.
15053 (<sse>_andnot<mode>3<mask_name>): Move check for
15054 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL after check for TARGET_AVX.
15055 (<code><mode>3<mask_name>): Ditto.
15056 (*andnot<mode>3): Ditto.
15057 (*andnottf3): Ditto.
15058 (*<code><mode>3): Ditto.
15059 (*<code>tf3): Ditto.
15060 (*andnot<VI:mode>3): Remove
15061 TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling.
15062 (<mask_codefor><code><VI48_AVX_AVX512F:mode>3<mask_name>): Ditto.
15063 (*<code><VI12_AVX_AVX512F:mode>3): Ditto.
15064 (sse4_1_blendv<ssemodesuffix>): Ditto.
15065 * config/i386/x86-tune.def (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL):
15066 Explain that tune applies to 128bit instructions only.
15068 2020-01-31 Kwok Cheung Yeung <kcy@codesourcery.com>
15070 * config/gcn/mkoffload.c (process_asm): Add sgpr_count and vgpr_count
15071 to definition of hsa_kernel_description. Parse assembly to find SGPR
15072 and VGPR count of kernel and store in hsa_kernel_description.
15074 2020-01-31 Tamar Christina <tamar.christina@arm.com>
15076 PR rtl-optimization/91838
15077 * simplify-rtx.c (simplify_binary_operation_1): Update LSHIFTRT case
15078 to truncate if allowed or reject combination.
15080 2020-01-31 Andrew Stubbs <ams@codesourcery.com>
15082 * tree-ssa-loop-ivopts.c (get_iv): Use sizetype for zero-step.
15083 (find_inv_vars_cb): Likewise.
15085 2020-01-31 David Malcolm <dmalcolm@redhat.com>
15087 * calls.c (special_function_p): Split out the check for DECL_NAME
15088 being non-NULL and fndecl being extern at file scope into a
15089 new maybe_special_function_p and call it. Drop check for fndecl
15090 being non-NULL that was after a usage of DECL_NAME (fndecl).
15091 * tree.h (maybe_special_function_p): New inline function.
15093 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
15095 * config/gcn/gcn-valu.md (gather<mode>_exec): Move contents ...
15096 (mask_gather_load<mode>): ... here, and zero-initialize the
15098 (maskload<mode>di): Zero-initialize the destination.
15099 * config/gcn/gcn.c:
15101 2020-01-30 David Malcolm <dmalcolm@redhat.com>
15104 * doc/analyzer.texi (Limitations): Note that constraints on
15105 floating-point values are currently ignored.
15107 2020-01-30 Jakub Jelinek <jakub@redhat.com>
15110 * symtab.c (symtab_node::noninterposable_alias): If localalias
15111 already exists, but is not usable, append numbers after it until
15112 a unique name is found. Formatting fix.
15114 PR middle-end/93505
15115 * combine.c (simplify_comparison) <case ROTATE>: Punt on out of range
15118 2020-01-30 Andrew Stubbs <ams@codesourcery.com>
15120 * config/gcn/gcn.c (print_operand): Handle LTGT.
15121 * config/gcn/predicates.md (gcn_fp_compare_operator): Allow ltgt.
15123 2020-01-30 Richard Biener <rguenther@suse.de>
15125 * tree-pretty-print.c (dump_generic_node): Wrap VECTOR_CST
15126 and CONSTRUCTOR in _Literal (type) with TDF_GIMPLE.
15128 2020-01-30 John David Anglin <danglin@gcc.gnu.org>
15130 * config/pa/pa.c (pa_elf_select_rtx_section): Place function pointers
15131 without a DECL in .data.rel.ro.local.
15133 2020-01-30 Jakub Jelinek <jakub@redhat.com>
15136 * config/arm/arm.md (uaddvdi4): Actually emit what gen_uaddvsi4
15140 * config/i386/sse.md
15141 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
15142 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
15143 any_extend code iterator instead of always zero_extend.
15144 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
15145 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
15146 Use any_extend code iterator instead of always zero_extend.
15147 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
15148 (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
15149 Use any_extend code iterator instead of always zero_extend.
15150 (*sse2_pmovmskb_ext): New define_insn.
15151 (*sse2_pmovmskb_ext_lt): New define_insn_and_split.
15154 * config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
15155 (*popcountsi2_zext_falsedep): New define_insn.
15157 2020-01-30 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15159 * config.in: Regenerated.
15160 * configure: Regenerated.
15162 2020-01-29 Tobias Burnus <tobias@codesourcery.com>
15165 * config/gcn/gcn-hsa.h (ASM_SPEC): Add -mattr=-code-object-v3 as
15166 LLVM's assembler changed the default in version 9.
15168 2020-01-24 Jeff Law <law@redhat.com>
15170 PR tree-optimization/89689
15171 * builtins.def (BUILT_IN_OBJECT_SIZE): Make it const rather than pure.
15173 2020-01-29 Richard Sandiford <richard.sandiford@arm.com>
15177 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15179 PR rtl-optimization/87763
15180 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
15181 simplification to handle subregs as well as bare regs.
15182 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
15184 2020-01-29 Joel Hutton <Joel.Hutton@arm.com>
15187 * ira.c (ira): Revert use of simplified LRA algorithm.
15189 2020-01-29 Martin Jambor <mjambor@suse.cz>
15191 PR tree-optimization/92706
15192 * tree-sra.c (struct access): Fields first_link, last_link,
15193 next_queued and grp_queued renamed to first_rhs_link, last_rhs_link,
15194 next_rhs_queued and grp_rhs_queued respectively, new fields
15195 first_lhs_link, last_lhs_link, next_lhs_queued and grp_lhs_queued.
15196 (struct assign_link): Field next renamed to next_rhs, new field
15197 next_lhs. Updated comment.
15198 (work_queue_head): Renamed to rhs_work_queue_head.
15199 (lhs_work_queue_head): New variable.
15200 (add_link_to_lhs): New function.
15201 (relink_to_new_repr): Also relink LHS lists.
15202 (add_access_to_work_queue): Renamed to add_access_to_rhs_work_queue.
15203 (add_access_to_lhs_work_queue): New function.
15204 (pop_access_from_work_queue): Renamed to
15205 pop_access_from_rhs_work_queue.
15206 (pop_access_from_lhs_work_queue): New function.
15207 (build_accesses_from_assign): Also add links to LHS lists and to LHS
15209 (child_would_conflict_in_lacc): Renamed to
15210 child_would_conflict_in_acc. Adjusted parameter names.
15211 (create_artificial_child_access): New parameter set_grp_read, use it.
15212 (subtree_mark_written_and_enqueue): Renamed to
15213 subtree_mark_written_and_rhs_enqueue.
15214 (propagate_subaccesses_across_link): Renamed to
15215 propagate_subaccesses_from_rhs.
15216 (propagate_subaccesses_from_lhs): New function.
15217 (propagate_all_subaccesses): Also propagate subaccesses from LHSs to
15220 2020-01-29 Martin Jambor <mjambor@suse.cz>
15222 PR tree-optimization/92706
15223 * tree-sra.c (struct access): Adjust comment of
15224 grp_total_scalarization.
15225 (find_access_in_subtree): Look for single children spanning an entire
15227 (scalarizable_type_p): Allow register accesses, adjust callers.
15228 (completely_scalarize): Remove function.
15229 (scalarize_elem): Likewise.
15230 (create_total_scalarization_access): Likewise.
15231 (sort_and_splice_var_accesses): Do not track total scalarization
15233 (analyze_access_subtree): New parameter totally, adjust to new meaning
15234 of grp_total_scalarization.
15235 (analyze_access_trees): Pass new parameter to analyze_access_subtree.
15236 (can_totally_scalarize_forest_p): New function.
15237 (create_total_scalarization_access): Likewise.
15238 (create_total_access_and_reshape): Likewise.
15239 (total_should_skip_creating_access): Likewise.
15240 (totally_scalarize_subtree): Likewise.
15241 (analyze_all_variable_accesses): Perform total scalarization after
15242 subaccess propagation using the new functions above.
15243 (initialize_constant_pool_replacements): Output initializers by
15244 traversing the access tree.
15246 2020-01-29 Martin Jambor <mjambor@suse.cz>
15248 * tree-sra.c (verify_sra_access_forest): New function.
15249 (verify_all_sra_access_forests): Likewise.
15250 (create_artificial_child_access): Set parent.
15251 (analyze_all_variable_accesses): Call the verifier.
15253 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15255 * cgraph.c (cgraph_edge::resolve_speculation): Only lookup direct edge
15256 if called on indirect edge.
15257 (cgraph_edge::redirect_call_stmt_to_callee): Lookup indirect edge of
15258 speculative call if needed.
15260 2020-01-29 Richard Biener <rguenther@suse.de>
15262 PR tree-optimization/93428
15263 * tree-vect-slp.c (vect_build_slp_tree_2): Compute the load
15264 permutation when the load node is created.
15265 (vect_analyze_slp_instance): Re-use it here.
15267 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15269 * ipa-prop.c (update_indirect_edges_after_inlining): Fix warning.
15271 2020-01-28 Vladimir Makarov <vmakarov@redhat.com>
15273 PR rtl-optimization/93272
15274 * ira-lives.c (process_out_of_region_eh_regs): New function.
15275 (process_bb_node_lives): Call it.
15277 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15279 * coverage.c (read_counts_file): Make error message lowercase.
15281 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15283 * profile-count.c (profile_quality_display_names): Fix ordering.
15285 2020-01-28 Jan Hubicka <hubicka@ucw.cz>
15288 * cgraph.c (cgraph_add_edge_to_call_site_hash): Update call site
15289 hash only when edge is first within the sequence.
15290 (cgraph_edge::set_call_stmt): Update handling of speculative calls.
15291 (symbol_table::create_edge): Do not set target_prob.
15292 (cgraph_edge::remove_caller): Watch for speculative calls when updating
15293 the call site hash.
15294 (cgraph_edge::make_speculative): Drop target_prob parameter.
15295 (cgraph_edge::speculative_call_info): Remove.
15296 (cgraph_edge::first_speculative_call_target): New member function.
15297 (update_call_stmt_hash_for_removing_direct_edge): New function.
15298 (cgraph_edge::resolve_speculation): Rewrite to new API.
15299 (cgraph_edge::speculative_call_for_target): New member function.
15300 (cgraph_edge::make_direct): Rewrite to new API; fix handling of
15301 multiple speculation targets.
15302 (cgraph_edge::redirect_call_stmt_to_callee): Likewise; fix updating
15304 (verify_speculative_call): Verify that targets form an interval.
15305 * cgraph.h (cgraph_edge::speculative_call_info): Remove.
15306 (cgraph_edge::first_speculative_call_target): New member function.
15307 (cgraph_edge::next_speculative_call_target): New member function.
15308 (cgraph_edge::speculative_call_target_ref): New member function.
15309 (cgraph_edge;:speculative_call_indirect_edge): New member funtion.
15310 (cgraph_edge): Remove target_prob.
15311 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
15312 Fix handling of speculative calls.
15313 * ipa-devirt.c (ipa_devirt): Fix handling of speculative cals.
15314 * ipa-fnsummary.c (analyze_function_body): Likewise.
15315 * ipa-inline.c (speculation_useful_p): Use new speculative call API.
15316 * ipa-profile.c (dump_histogram): Fix formating.
15317 (ipa_profile_generate_summary): Watch for overflows.
15318 (ipa_profile): Do not require probablity to be 1/2; update to new API.
15319 * ipa-prop.c (ipa_make_edge_direct_to_target): Update to new API.
15320 (update_indirect_edges_after_inlining): Update to new API.
15321 * ipa-utils.c (ipa_merge_profiles): Rewrite merging of speculative call
15323 * profile-count.h: (profile_probability::adjusted): New.
15324 * tree-inline.c (copy_bb): Update to new speculative call API; fix
15325 updating of profile.
15326 * value-prof.c (gimple_ic_transform): Rename to ...
15327 (dump_ic_profile): ... this one; update dumping.
15328 (stream_in_histogram_value): Fix formating.
15329 (gimple_value_profile_transformations): Update.
15331 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
15334 * config/i386/i386.md (*movoi_internal_avx): Remove
15335 TARGET_SSE_TYPELESS_STORES check.
15336 (*movti_internal): Prefer TARGET_AVX over
15337 TARGET_SSE_TYPELESS_STORES.
15338 (*movtf_internal): Likewise.
15339 * config/i386/sse.md (mov<mode>_internal): Prefer TARGET_AVX over
15340 TARGET_SSE_TYPELESS_STORES. Remove "<MODE_SIZE> == 16" check
15341 from TARGET_SSE_TYPELESS_STORES.
15343 2020-01-28 David Malcolm <dmalcolm@redhat.com>
15345 * diagnostic-core.h (warning_at): Rename overload to...
15346 (warning_meta): ...this.
15347 (emit_diagnostic_valist): Delete decl of overload taking
15348 diagnostic_metadata.
15349 * diagnostic.c (emit_diagnostic_valist): Likewise for defn.
15350 (warning_at): Rename overload taking diagnostic_metadata to...
15351 (warning_meta): ...this.
15353 2020-01-28 Richard Biener <rguenther@suse.de>
15355 PR tree-optimization/93439
15356 * tree-parloops.c (create_loop_fn): Move clique bookkeeping...
15357 * tree-cfg.c (move_sese_region_to_fn): ... here.
15358 (verify_types_in_gimple_reference): Verify used cliques are
15361 2020-01-28 H.J. Lu <hongjiu.lu@intel.com>
15364 * config/i386/i386-options.c (set_ix86_tune_features): Add an
15365 argument of a pointer to struct gcc_options and pass it to
15366 parse_mtune_ctrl_str.
15367 (ix86_function_specific_restore): Pass opts to
15368 set_ix86_tune_features.
15369 (ix86_option_override_internal): Likewise.
15370 (parse_mtune_ctrl_str): Add an argument of a pointer to struct
15371 gcc_options and use it for x_ix86_tune_ctrl_string.
15373 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15375 PR rtl-optimization/87763
15376 * simplify-rtx.c (simplify_truncation): Extend sign/zero_extract
15377 simplification to handle subregs as well as bare regs.
15378 * config/i386/i386.md (*testqi_ext_3): Match QI extracts too.
15380 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15382 * tree-vect-loop.c (vectorizable_reduction): Fail gracefully
15383 for reduction chains that (now) include a call.
15385 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15387 PR tree-optimization/92822
15388 * tree-ssa-forwprop.c (simplify_vector_constructor): When filling
15389 out the don't-care elements of a vector whose significant elements
15390 are duplicates, make the don't-care elements duplicates too.
15392 2020-01-28 Richard Sandiford <richard.sandiford@arm.com>
15394 PR tree-optimization/93434
15395 * tree-predcom.c (split_data_refs_to_components): Record which
15396 components have had aliasing loads removed. Prevent store-store
15397 commoning for all such components.
15399 2020-01-28 Jakub Jelinek <jakub@redhat.com>
15402 * config/i386/i386.c (ix86_fold_builtin) <do_shift>: If mask is not
15403 -1 or is_vshift is true, use new_vector with number of elts npatterns
15404 rather than new_unary_operation.
15406 PR tree-optimization/93454
15407 * gimple-fold.c (fold_array_ctor_reference): Perform
15408 elt_size.to_uhwi () just once, instead of calling it in every
15409 iteration. Punt if that value is above size of the temporary
15410 buffer. Decrease third native_encode_expr argument when
15411 bufoff + elt_sz is above size of buf.
15413 2020-01-27 Joseph Myers <joseph@codesourcery.com>
15415 * config/mips/mips.c (mips_declare_object_name)
15416 [USE_GNU_UNIQUE_OBJECT]: Support use of gnu_unique_object.
15418 2020-01-27 Martin Liska <mliska@suse.cz>
15420 PR gcov-profile/93403
15421 * tree-profile.c (gimple_init_gcov_profiler): Generate
15422 both __gcov_indirect_call_profiler_v4 and
15423 __gcov_indirect_call_profiler_v4_atomic.
15425 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15428 * config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
15430 (@aarch64_split_simd_mov<mode>): Use it.
15431 (aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
15432 Leave the vec_extract patterns to handle 2-element vectors.
15433 (aarch64_simd_mov_from_<mode>high): Likewise.
15434 (vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
15435 (vec_extractv2dfv1df): Likewise.
15437 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15439 * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
15440 jump conditions for *compare_condjump<GPI:mode>.
15442 2020-01-27 David Malcolm <dmalcolm@redhat.com>
15445 * digraph.cc (test_edge::test_edge): Specify template for base
15448 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15450 * config/arc/arc.c (arc_rtx_costs): Update mul64 cost.
15452 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15454 * config/arc/arc-protos.h (gen_mlo): Remove.
15455 (gen_mhi): Likewise.
15456 * config/arc/arc.c (AUX_MULHI): Define.
15457 (arc_must_save_reister): Special handling for r58/59.
15458 (arc_compute_frame_size): Consider mlo/mhi registers.
15459 (arc_save_callee_saves): Emit fp/sp move only when emit_move
15461 (arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
15462 mlo/mhi name selection.
15463 (arc_restore_callee_saves): Don't early restore blink when ISR.
15464 (arc_expand_prologue): Add mlo/mhi saving.
15465 (arc_expand_epilogue): Add mlo/mhi restoring.
15468 * config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
15469 numbering when MUL64 option is used.
15470 (DWARF2_FRAME_REG_OUT): Define.
15471 * config/arc/arc.md (arc600_stall): New pattern.
15472 (VUNSPEC_ARC_ARC600_STALL): Define.
15473 (mulsi64): Use correct mlo/mhi registers.
15474 (mulsi_600): Clean it up.
15475 * config/arc/predicates.md (mlo_operand): Remove any dependency on
15477 (mhi_operand): Likewise.
15479 2020-01-27 Claudiu Zissulescu <claziss@synopsys.com>
15480 Petro Karashchenko <petro.karashchenko@ring.com>
15482 * config/arc/arc.c (arc_is_uncached_mem_p): Check struct
15483 attributes if needed.
15484 (prepare_move_operands): Generate special unspec instruction for
15486 (arc_isuncached_mem_p): Propagate uncached attribute to each
15488 * config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
15489 (VUNSPEC_ARC_STDI): Likewise.
15490 (ALLI): New mode iterator.
15491 (mALLI): New mode attribute.
15492 (lddi): New instruction pattern.
15494 (stdidi_split): Split instruction for architectures which are not
15495 supporting ll64 option.
15496 (lddidi_split): Likewise.
15498 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15500 PR rtl-optimization/92989
15501 * lra-lives.c (process_bb_lives): Update the live-in set before
15502 processing additional clobbers.
15504 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15506 PR rtl-optimization/93170
15507 * cselib.c (cselib_invalidate_regno_val): New function, split out
15509 (cselib_invalidate_regno): ...here.
15510 (cselib_invalidated_by_call_p): New function.
15511 (cselib_process_insn): Iterate over all the hard-register entries in
15512 REG_VALUES and invalidate any that cross call-clobbered registers.
15514 2020-01-27 Richard Sandiford <richard.sandiford@arm.com>
15516 * dojump.c (split_comparison): Use HONOR_NANS rather than
15517 HONOR_SNANS when splitting LTGT.
15519 2020-01-27 Martin Liska <mliska@suse.cz>
15522 * opts.c (print_filtered_help): Exclude language-specific
15523 options from --help=common unless enabled in all FEs.
15525 2020-01-27 Martin Liska <mliska@suse.cz>
15527 * opts.c (print_help): Exclude params from
15528 all except --help=param.
15530 2020-01-27 Martin Liska <mliska@suse.cz>
15533 * config/i386/i386-features.c (make_resolver_func):
15534 Align the code with ppc64 target implementation.
15535 Do not generate a unique name for resolver function.
15537 2020-01-27 Richard Biener <rguenther@suse.de>
15539 PR tree-optimization/93397
15540 * tree-vect-slp.c (vect_analyze_slp_instance): Delay
15541 converted reduction chain SLP graph adjustment.
15543 2020-01-26 Marek Polacek <polacek@redhat.com>
15546 * sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
15549 2020-01-26 Jason Merrill <jason@redhat.com>
15552 * tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
15555 2020-01-26 Darius Galis <darius.galis@cyberthorstudios.com>
15557 * config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
15558 (rx_setmem): Likewise.
15560 2020-01-26 Jakub Jelinek <jakub@redhat.com>
15563 * config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
15564 Use nonimmediate_operand instead of x86_64_hilo_general_operand and
15565 drop <di> from constraint of last operand.
15568 * config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
15569 TARGET_AVX2 and V4DFmode not in the split condition, but in the
15570 pattern condition, though allow { 0, 0, 0, 0 } broadcast always.
15572 2020-01-25 Feng Xue <fxue@os.amperecomputing.com>
15575 * ipa-cp.c (get_info_about_necessary_edges): Remove value
15578 2020-01-24 Jeff Law <law@redhat.com>
15580 PR tree-optimization/92788
15581 * tree-ssa-threadedge.c (thread_across_edge): Check EDGE_COMPLEX
15584 2020-01-24 Jakub Jelinek <jakub@redhat.com>
15587 * config/i386/sse.md (*avx_vperm_broadcast_v4sf,
15588 *avx_vperm_broadcast_<mode>,
15589 <sse2_avx_avx512f>_vpermil<mode><mask_name>,
15590 *<sse2_avx_avx512f>_vpermilp<mode><mask_name>):
15591 Move before avx2_perm<mode>/avx512f_perm<mode>.
15594 * simplify-rtx.c (simplify_const_unary_operation,
15595 simplify_const_binary_operation): Punt for mode precision above
15596 MAX_BITSIZE_MODE_ANY_INT.
15598 2020-01-24 Andrew Pinski <apinski@marvell.com>
15600 * config/arm/aarch-cost-tables.h (cortexa57_extra_costs): Change
15601 alu.shift_reg to 0.
15603 2020-01-24 Jeff Law <law@redhat.com>
15606 * config/h8300/h8300.c (h8300_print_operand): Only call byte_reg
15607 for REGs. Call output_operand_lossage to get more reasonable
15610 2020-01-24 Andrew Stubbs <ams@codesourcery.com>
15612 * config/gcn/gcn-valu.md (vec_cmp<mode>di): Use
15613 gcn_fp_compare_operator.
15614 (vec_cmpu<mode>di): Use gcn_compare_operator.
15615 (vec_cmp<u>v64qidi): Use gcn_compare_operator.
15616 (vec_cmp<mode>di_exec): Use gcn_fp_compare_operator.
15617 (vec_cmpu<mode>di_exec): Use gcn_compare_operator.
15618 (vec_cmp<u>v64qidi_exec): Use gcn_compare_operator.
15619 (vec_cmp<mode>di_dup): Use gcn_fp_compare_operator.
15620 (vec_cmp<mode>di_dup_exec): Use gcn_fp_compare_operator.
15621 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): Use
15622 gcn_fp_compare_operator.
15623 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): Use
15624 gcn_fp_compare_operator.
15625 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): Use
15626 gcn_fp_compare_operator.
15627 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): Use
15628 gcn_fp_compare_operator.
15630 2020-01-24 Maciej W. Rozycki <macro@wdc.com>
15632 * doc/install.texi (Cross-Compiler-Specific Options): Document
15633 `--with-toolexeclibdir' option.
15635 2020-01-24 Hans-Peter Nilsson <hp@axis.com>
15637 * target.def (flags_regnum): Also mention effect on delay slot filling.
15638 * doc/tm.texi: Regenerate.
15640 2020-01-23 Jeff Law <law@redhat.com>
15642 PR translation/90162
15643 * config/h8300/h8300.c (h8300_option_override): Fix diagnostic text.
15645 2020-01-23 Mikael Tillenius <mti-1@tillenius.com>
15648 * config/h8300/h8300.h (FUNCTION_PROFILER): Fix emission of
15651 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15653 PR rtl-optimization/93402
15654 * postreload.c (reload_combine_recognize_pattern): Don't try to adjust
15657 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15659 * config.in: Regenerated.
15660 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to 1
15661 for TARGET_LIBC_GNUSTACK.
15662 * configure: Regenerated.
15663 * configure.ac: Define TARGET_LIBC_GNUSTACK if glibc version is
15664 found to be 2.31 or greater.
15666 2020-01-23 Dragan Mladjenovic <dmladjenovic@wavecomp.com>
15668 * config/mips/linux.h (NEED_INDICATE_EXEC_STACK): Define to
15670 * config/mips/mips.c (TARGET_ASM_FILE_END): Define to ...
15671 (mips_asm_file_end): New function. Delegate to
15672 file_end_indicate_exec_stack if NEED_INDICATE_EXEC_STACK is true.
15673 * config/mips/mips.h (NEED_INDICATE_EXEC_STACK): Define to 0.
15675 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15678 * config/i386/i386-modes.def (POImode): New mode.
15679 (MAX_BITSIZE_MODE_ANY_INT): Change from 128 to 160.
15680 * config/i386/i386.md (DPWI): New mode attribute.
15681 (addv<mode>4, subv<mode>4): Use <DPWI> instead of <DWI>.
15682 (QWI): Rename to...
15683 (QPWI): ... this. Use POI instead of OI for TImode.
15684 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1,
15685 *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1): Use <QPWI>
15688 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15691 * config/aarch64/aarch64.md (UNSPEC_SPECULATION_TRACKER_REV): New
15693 (speculation_tracker_rev): New pattern.
15694 * config/aarch64/aarch64-speculation.cc (aarch64_do_track_speculation):
15695 Use speculation_tracker_rev to track the inverse condition.
15697 2020-01-23 Richard Biener <rguenther@suse.de>
15699 PR tree-optimization/93381
15700 * tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Take
15701 alias-set of the def as argument and record the first one.
15702 (vn_walk_cb_data::first_set): New member.
15703 (vn_reference_lookup_3): Pass the alias-set of the current def
15704 to push_partial_def. Fix alias-set used in the aggregate copy
15706 (vn_reference_lookup): Consistently set *last_vuse_ptr.
15707 * real.c (clear_significand_below): Fix out-of-bound access.
15709 2020-01-23 Jakub Jelinek <jakub@redhat.com>
15712 * config/i386/i386.md (*bmi2_bzhi_<mode>3_2, *bmi2_bzhi_<mode>3_3):
15713 New define_insn patterns.
15715 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15717 * doc/sourcebuild.texi (check-function-bodies): Add an
15718 optional target/xfail selector.
15720 2020-01-23 Richard Sandiford <richard.sandiford@arm.com>
15722 PR rtl-optimization/93124
15723 * auto-inc-dec.c (merge_in_block): Don't add auto inc/decs to
15724 bare USE and CLOBBER insns.
15726 2020-01-22 Andrew Pinski <apinski@marvell.com>
15728 * config/arc/arc.c (output_short_suffix): Check insn for nullness.
15730 2020-01-22 David Malcolm <dmalcolm@redhat.com>
15733 * gdbinit.in (break-on-saved-diagnostic): Update for move of
15734 diagnostic_manager into "ana" namespace.
15735 * selftest-run-tests.c (selftest::run_tests): Update for move of
15736 selftest::run_analyzer_selftests to
15737 ana::selftest::run_analyzer_selftests.
15739 2020-01-22 Richard Sandiford <richard.sandiford@arm.com>
15741 * cfgexpand.c (union_stack_vars): Update the size.
15743 2020-01-22 Richard Biener <rguenther@suse.de>
15745 PR tree-optimization/93381
15746 * tree-ssa-structalias.c (find_func_aliases): Assume offsetting
15747 throughout, handle all conversions the same.
15749 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15752 * config/aarch64/aarch64.c (aarch64_expand_subvti): Only use
15753 gen_subdi3_compare1_imm if low_in2 satisfies aarch64_plus_immediate
15754 predicate, not whenever it is CONST_INT. Otherwise, force_reg it.
15755 Call force_reg on high_in2 unconditionally.
15757 2020-01-22 Martin Liska <mliska@suse.cz>
15759 PR tree-optimization/92924
15760 * profile.c (compute_value_histograms): Divide
15761 all counter values.
15763 2020-01-22 Jakub Jelinek <jakub@redhat.com>
15766 * output.h (assemble_name_resolve): Declare.
15767 * varasm.c (assemble_name_resolve): New function.
15768 (assemble_name): Use it.
15769 * config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Define.
15771 2020-01-22 Joseph Myers <joseph@codesourcery.com>
15773 * doc/sourcebuild.texi (Texinfo Manuals, Front End): Refer to
15774 update_web_docs_git instead of update_web_docs_svn.
15776 2020-01-21 Andrew Pinski <apinski@marvell.com>
15779 * config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
15780 as PTR mode. Have operand 1 as being modeless, it can be P mode.
15781 (*tlsgd_small_<mode>): Likewise.
15782 * config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
15783 <case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
15784 register. Convert that register back to dest using convert_mode.
15786 2020-01-21 Jim Wilson <jimw@sifive.com>
15788 * config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
15791 2020-01-21 H.J. Lu <hongjiu.lu@intel.com>
15792 Uros Bizjak <ubizjak@gmail.com>
15795 * config/i386/i386.c (ix86_tls_module_base): Replace Pmode
15797 (legitimize_tls_address): Do GNU2 TLS address computation in
15798 ptr_mode and zero-extend result to Pmode.
15799 * config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
15800 :P with :PTR and Pmode with ptr_mode.
15801 (*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
15802 (*tls_dynamic_gnu2_call_64_<mode>): Likewise.
15803 (*tls_dynamic_gnu2_combine_64_<mode>): Likewise.
15805 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15808 * config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
15809 the last two operands are CONST_INT_P before using them as such.
15811 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15813 * config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
15814 to get the integer element types.
15816 2020-01-21 Richard Sandiford <richard.sandiford@arm.com>
15818 * config/aarch64/aarch64-sve-builtins.h
15819 (function_expander::convert_to_pmode): Declare.
15820 * config/aarch64/aarch64-sve-builtins.cc
15821 (function_expander::convert_to_pmode): New function.
15822 (function_expander::get_contiguous_base): Use it.
15823 (function_expander::prepare_gather_address_operands): Likewise.
15824 * config/aarch64/aarch64-sve-builtins-sve2.cc
15825 (svwhilerw_svwhilewr_impl::expand): Likewise.
15827 2020-01-21 Szabolcs Nagy <szabolcs.nagy@arm.com>
15830 * config/aarch64/aarch64.c (aarch64_declare_function_name): Set
15831 cfun->machine->label_is_assembled.
15832 (aarch64_print_patchable_function_entry): New.
15833 (TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
15834 * config/aarch64/aarch64.h (struct machine_function): New field,
15835 label_is_assembled.
15837 2020-01-21 David Malcolm <dmalcolm@redhat.com>
15840 * ipa-profile.c (ipa_profile): Delete call_sums and set it to
15843 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15846 * cgraph.c (cgraph_edge::resolve_speculation,
15847 cgraph_edge::redirect_call_stmt_to_callee): Fix update of
15848 call_stmt_site_hash.
15850 2020-01-21 Martin Liska <mliska@suse.cz>
15852 * config/rs6000/rs6000.c (common_mode_defined): Remove
15855 2020-01-21 Richard Biener <rguenther@suse.de>
15857 PR tree-optimization/92328
15858 * tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
15859 type when value-numbering same-sized store by inserting a
15861 (eliminate_dom_walker::eliminate_stmt): When eliminating
15862 a redundant store handle bit-reinterpretation of the same value.
15864 2020-01-21 Andrew Pinski <apinski@marvel.com>
15867 * tree-into-ssa.c (prepare_block_for_update_1): Split out
15869 (prepare_block_for_update): This. Use a worklist instead of
15872 2020-01-21 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
15874 * config/arm/arm.c (clear_operation_p):
15875 Initialise last_regno, skip first iteration
15876 based on the first_set value and use ints instead
15877 of the unnecessary HOST_WIDE_INTs.
15879 2020-01-21 Jakub Jelinek <jakub@redhat.com>
15882 * config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
15883 compare_mode other than SFmode or DFmode.
15885 2020-01-21 Kito Cheng <kito.cheng@sifive.com>
15888 * config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
15889 * config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
15890 * config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
15892 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15894 * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
15896 2020-01-20 Andrew Pinski <apinski@marvell.com>
15898 PR middle-end/93242
15899 * targhooks.c (default_print_patchable_function_entry): Use
15900 output_asm_insn to emit the nop instruction.
15902 2020-01-20 Fangrui Song <maskray@google.com>
15904 PR middle-end/93194
15905 * targhooks.c (default_print_patchable_function_entry): Align to
15908 2020-01-20 H.J. Lu <hongjiu.lu@intel.com>
15911 * config/i386/i386.c (legitimize_tls_address): Pass Pmode to
15912 gen_tls_dynamic_gnu2_64. Compute GNU2 TLS address in ptr_mode.
15913 * config/i386/i386.md (tls_dynamic_gnu2_64): Renamed to ...
15914 (@tls_dynamic_gnu2_64_<mode>): This. Replace DI with P.
15915 (*tls_dynamic_gnu2_lea_64): Renamed to ...
15916 (*tls_dynamic_gnu2_lea_64_<mode>): This. Replace DI with P.
15917 Remove the {q} suffix from lea.
15918 (*tls_dynamic_gnu2_call_64): Renamed to ...
15919 (*tls_dynamic_gnu2_call_64_<mode>): This. Replace DI with P.
15920 (*tls_dynamic_gnu2_combine_64): Renamed to ...
15921 (*tls_dynamic_gnu2_combine_64_<mode>): This. Replace DI with P.
15922 Pass Pmode to gen_tls_dynamic_gnu2_64.
15924 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
15926 * config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
15928 2020-01-20 Richard Sandiford <richard.sandiford@arm.com>
15930 * config/aarch64/aarch64-sve-builtins-base.cc
15931 (svld1ro_impl::memory_vector_mode): Remove parameter name.
15933 2020-01-20 Richard Biener <rguenther@suse.de>
15936 * dwarf2out.c (prune_unused_types): Unconditionally mark
15937 called function DIEs.
15939 2020-01-20 Martin Liska <mliska@suse.cz>
15941 PR tree-optimization/93199
15942 * tree-eh.c (struct leh_state): Add
15943 new field outer_non_cleanup.
15944 (cleanup_is_dead_in): Pass leh_state instead
15945 of eh_region. Add a checking that state->outer_non_cleanup
15946 points to outer non-clean up region.
15947 (lower_try_finally): Record outer_non_cleanup
15949 (lower_catch): Likewise.
15950 (lower_eh_filter): Likewise.
15951 (lower_eh_must_not_throw): Likewise.
15952 (lower_cleanup): Likewise.
15954 2020-01-20 Richard Biener <rguenther@suse.de>
15956 PR tree-optimization/93094
15957 * tree-vectorizer.h (vect_loop_versioning): Adjust.
15958 (vect_transform_loop): Likewise.
15959 * tree-vectorizer.c (try_vectorize_loop_1): Pass down
15960 loop_vectorized_call to vect_transform_loop.
15961 * tree-vect-loop.c (vect_transform_loop): Pass down
15962 loop_vectorized_call to vect_loop_versioning.
15963 * tree-vect-loop-manip.c (vect_loop_versioning): Use
15964 the earlier discovered loop_vectorized_call.
15966 2020-01-19 Eric S. Raymond <esr@thyrsus.com>
15968 * doc/contribute.texi: Update for SVN -> Git transition.
15969 * doc/install.texi: Likewise.
15971 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15974 * cgraph.c (cgraph_edge::make_speculative): Increase number of
15975 speculative targets.
15976 (verify_speculative_call): New function
15977 (cgraph_node::verify_node): Use it.
15978 * ipa-profile.c (ipa_profile): Fix formating; do not set number of
15981 2020-01-18 Jan Hubicka <hubicka@ucw.cz>
15984 * cgraph.c (cgraph_edge::resolve_speculation): Fix foramting.
15985 (cgraph_edge::make_direct): Remove all indirect targets.
15986 (cgraph_edge::redirect_call_stmt_to_callee): Use make_direct..
15987 (cgraph_node::verify_node): Verify that only one call_stmt or
15988 lto_stmt_uid is set.
15989 * cgraphclones.c (cgraph_edge::clone): Set only one call_stmt or
15991 * lto-cgraph.c (lto_output_edge): Simplify streaming of stmt.
15992 (lto_output_ref): Simplify streaming of stmt.
15993 * lto-streamer-in.c (fixup_call_stmt_edges_1): Clear lto_stmt_uid.
15995 2020-01-18 Tamar Christina <tamar.christina@arm.com>
15997 * config/aarch64/aarch64-sve-builtins-base.cc (memory_vector_mode):
15998 Mark parameter unused.
16000 2020-01-18 Hans-Peter Nilsson <hp@axis.com>
16002 * config.gcc <obsolete targets>: Add crisv32-*-* and cris-*-linux*
16004 2019-01-18 Gerald Pfeifer <gerald@pfeifer.com>
16006 * varpool.c (ctor_useable_for_folding_p): Fix grammar.
16008 2020-01-18 Iain Sandoe <iain@sandoe.co.uk>
16010 * Makefile.in: Add coroutine-passes.o.
16011 * builtin-types.def (BT_CONST_SIZE): New.
16012 (BT_FN_BOOL_PTR): New.
16013 (BT_FN_PTR_PTR_CONST_SIZE_BOOL): New.
16014 * builtins.def (DEF_COROUTINE_BUILTIN): New.
16015 * coroutine-builtins.def: New file.
16016 * coroutine-passes.cc: New file.
16017 * function.h (struct GTY function): Add a bit to indicate that the
16018 function is a coroutine component.
16019 * internal-fn.c (expand_CO_FRAME): New.
16020 (expand_CO_YIELD): New.
16021 (expand_CO_SUSPN): New.
16022 (expand_CO_ACTOR): New.
16023 * internal-fn.def (CO_ACTOR): New.
16027 * passes.def: Add pass_coroutine_lower_builtins,
16028 pass_coroutine_early_expand_ifns.
16029 * tree-pass.h (make_pass_coroutine_lower_builtins): New.
16030 (make_pass_coroutine_early_expand_ifns): New.
16031 * doc/invoke.texi: Document the fcoroutines command line
16034 2020-01-18 Jakub Jelinek <jakub@redhat.com>
16036 * config/arm/vfp.md (*clear_vfp_multiple): Remove unused variable.
16039 * config/arm/arm.c (clear_operation_p): Don't use REGNO until
16040 after checking the argument is a REG. Don't use REGNO (reg)
16041 again to set last_regno, reuse regno variable instead.
16043 2020-01-17 David Malcolm <dmalcolm@redhat.com>
16045 * doc/analyzer.texi (Limitations): Add note about NaN.
16047 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16048 Sudakshina Das <sudi.das@arm.com>
16050 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
16051 and valid immediate.
16052 (ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
16053 (lshrdi3): Generate thumb2_lsrl for valid immediates.
16054 * config/arm/constraints.md (Pg): New.
16055 * config/arm/predicates.md (long_shift_imm): New.
16056 (arm_reg_or_long_shift_imm): Likewise.
16057 * config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
16058 (thumb2_lsll): Likewise.
16059 (thumb2_lsrl): New.
16061 2020-01-17 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16062 Sudakshina Das <sudi.das@arm.com>
16064 * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
16065 (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
16066 * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
16067 register pairs for doubleword quantities for ARMv8.1M-Mainline.
16068 * config/arm/thumb2.md (thumb2_asrl): New.
16069 (thumb2_lsll): Likewise.
16071 2020-01-17 Jakub Jelinek <jakub@redhat.com>
16073 * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove
16076 2020-01-17 Alexander Monakov <amonakov@ispras.ru>
16078 * gdbinit.in (help-gcc-hooks): New command.
16079 (pp, pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, ptc, pdn, ptn, pdd, prc,
16080 pi, pbm, pel, trt): Take $arg0 instead of $ if supplied. Update
16083 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
16085 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): Use the
16086 correct target macro.
16088 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
16090 * config/aarch64/aarch64-protos.h
16091 (aarch64_sve_ld1ro_operand_p): New.
16092 * config/aarch64/aarch64-sve-builtins-base.cc
16093 (class load_replicate): New.
16094 (class svld1ro_impl): New.
16095 (class svld1rq_impl): Change to inherit from load_replicate.
16096 (svld1ro): New sve intrinsic function base.
16097 * config/aarch64/aarch64-sve-builtins-base.def (svld1ro):
16098 New DEF_SVE_FUNCTION.
16099 * config/aarch64/aarch64-sve-builtins-base.h
16100 (svld1ro): New decl.
16101 * config/aarch64/aarch64-sve-builtins.cc
16102 (function_expander::add_mem_operand): Modify assert to allow
16104 * config/aarch64/aarch64-sve.md (@aarch64_sve_ld1ro<mode>): New
16106 * config/aarch64/aarch64.c
16107 (aarch64_sve_ld1rq_operand_p): Implement in terms of ...
16108 (aarch64_sve_ld1rq_ld1ro_operand_p): This.
16109 (aarch64_sve_ld1ro_operand_p): New.
16110 * config/aarch64/aarch64.md (UNSPEC_LD1RO): New unspec.
16111 * config/aarch64/constraints.md (UOb,UOh,UOw,UOd): New.
16112 * config/aarch64/predicates.md
16113 (aarch64_sve_ld1ro_operand_{b,h,w,d}): New.
16115 2020-01-17 Matthew Malcomson <matthew.malcomson@arm.com>
16117 * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
16118 Introduce this ACLE specified predefined macro.
16119 * config/aarch64/aarch64-option-extensions.def (f64mm): New.
16120 (fp): Disabling this disables f64mm.
16121 (simd): Disabling this disables f64mm.
16122 (fp16): Disabling this disables f64mm.
16123 (sve): Disabling this disables f64mm.
16124 * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
16125 (AARCH64_ISA_F64MM): New.
16126 (TARGET_F64MM): New.
16127 * doc/invoke.texi (f64mm): Document new option.
16129 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
16131 * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.
16132 (neoversen1_tunings): Likewise.
16134 2020-01-17 Wilco Dijkstra <wdijkstr@arm.com>
16137 * config/aarch64/aarch64.c (aarch64_split_compare_and_swap)
16138 Add assert to ensure prolog has been emitted.
16139 (aarch64_split_atomic_op): Likewise.
16140 * config/aarch64/atomics.md (aarch64_compare_and_swap<mode>)
16141 Use epilogue_completed rather than reload_completed.
16142 (aarch64_atomic_exchange<mode>): Likewise.
16143 (aarch64_atomic_<atomic_optab><mode>): Likewise.
16144 (atomic_nand<mode>): Likewise.
16145 (aarch64_atomic_fetch_<atomic_optab><mode>): Likewise.
16146 (atomic_fetch_nand<mode>): Likewise.
16147 (aarch64_atomic_<atomic_optab>_fetch<mode>): Likewise.
16148 (atomic_nand_fetch<mode>): Likewise.
16150 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
16153 * config/aarch64/aarch64.h (REVERSIBLE_CC_MODE): Return false
16155 (REVERSE_CONDITION): Delete.
16156 * config/aarch64/iterators.md (CC_ONLY): New mode iterator.
16157 (CCFP_CCFPE): Likewise.
16158 (e): New mode attribute.
16159 * config/aarch64/aarch64.md (ccmp<GPI:mode>): Rename to...
16160 (@ccmp<CC_ONLY:mode><GPI:mode>): ...this, using CC_ONLY instead of CC.
16161 (fccmp<GPF:mode>, fccmpe<GPF:mode>): Merge into...
16162 (@ccmp<CCFP_CCFPE:mode><GPF:mode>): ...this combined pattern.
16163 (@ccmp<CC_ONLY:mode><GPI:mode>_rev): New pattern.
16164 (@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev): Likewise.
16165 * config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update
16166 name of generator from gen_ccmpdi to gen_ccmpccdi.
16167 (aarch64_gen_ccmp_next): Use code_for_ccmp. If we want to reverse
16168 the previous comparison but aren't able to, use the new ccmp_rev
16171 2020-01-17 Richard Sandiford <richard.sandiford@arm.com>
16173 * gimplify.c (gimplify_return_expr): Use poly_int_tree_p rather
16174 than testing directly for INTEGER_CST.
16175 (gimplify_target_expr, gimplify_omp_depend): Likewise.
16177 2020-01-17 Jakub Jelinek <jakub@redhat.com>
16179 PR tree-optimization/93292
16180 * tree-vect-stmts.c (vectorizable_comparison): Punt also if
16181 get_vectype_for_scalar_type returns NULL.
16183 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
16185 * params.opt (-param=max-predicted-iterations): Increase range from 0.
16186 * predict.c (estimate_loops): Add 1 to param_max_predicted_iterations.
16188 2020-01-16 Jan Hubicka <hubicka@ucw.cz>
16190 * ipa-fnsummary.c (estimate_calls_size_and_time): Fix formating of
16192 * params.opt: (max-predicted-iterations): Set bounds.
16193 * predict.c (real_almost_one, real_br_prob_base,
16194 real_inv_br_prob_base, real_one_half, real_bb_freq_max): Remove.
16195 (propagate_freq): Add max_cyclic_prob parameter; cap cyclic
16196 probabilities; do not truncate to reg_br_prob_bases.
16197 (estimate_loops_at_level): Pass max_cyclic_prob.
16198 (estimate_loops): Compute max_cyclic_prob.
16199 (estimate_bb_frequencies): Do not initialize real_*; update calculation
16201 * profile-count.c (profile_probability::to_sreal): New.
16202 * profile-count.h (class sreal): Move up in file.
16203 (profile_probability::to_sreal): Declare.
16205 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16208 (arm_invalid_conversion): New function for target hook.
16209 (arm_invalid_unary_op): New function for target hook.
16210 (arm_invalid_binary_op): New function for target hook.
16212 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16214 * config.gcc: Add arm_bf16.h.
16215 * config/arm/arm-builtins.c (arm_mangle_builtin_type): Fix comment.
16216 (arm_simd_builtin_std_type): Add BFmode.
16217 (arm_init_simd_builtin_types): Define element types for vector types.
16218 (arm_init_bf16_types): New function.
16219 (arm_init_builtins): Add arm_init_bf16_types function call.
16220 * config/arm/arm-modes.def: Add BFmode and V4BF, V8BF vector modes.
16221 * config/arm/arm-simd-builtin-types.def: Add V4BF, V8BF.
16222 * config/arm/arm.c (aapcs_vfp_sub_candidate): Add BFmode.
16223 (arm_hard_regno_mode_ok): Add BFmode and tidy up statements.
16224 (arm_vector_mode_supported_p): Add V4BF, V8BF.
16225 (arm_mangle_type): Add __bf16.
16226 * config/arm/arm.h: Add V4BF, V8BF to VALID_NEON_DREG_MODE,
16227 VALID_NEON_QREG_MODE respectively. Add export arm_bf16_type_node,
16228 arm_bf16_ptr_type_node.
16229 * config/arm/arm.md: Add BFmode to movhf expand, mov pattern and
16230 define_split between ARM registers.
16231 * config/arm/arm_bf16.h: New file.
16232 * config/arm/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
16233 * config/arm/iterators.md: (ANY64_BF, VDXMOV, VHFBF, HFBF, fporbf): New.
16234 (VQXMOV): Add V8BF.
16235 * config/arm/neon.md: Add BF vector types to movhf NEON move patterns.
16236 * config/arm/vfp.md: Add BFmode to movhf patterns.
16238 2020-01-16 Mihail Ionescu <mihail.ionescu@arm.com>
16239 Andre Vieira <andre.simoesdiasvieira@arm.com>
16241 * config/arm/arm-cpus.in (mve, mve_float): New features.
16242 (dsp, mve, mve.fp): New options.
16243 * config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAVE_MVE_FLOAT): Define.
16244 * config/arm/t-rmprofile: Map v8.1-M multilibs to v8-M.
16245 * doc/invoke.texi: Document the armv8.1-m mve and dps options.
16247 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16248 Thomas Preud'homme <thomas.preudhomme@arm.com>
16250 * config/arm/arm-cpus.in (ARMv8_1m_main): Redefine as an extension to
16252 * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Remove
16253 error for using -mcmse when targeting Armv8.1-M Mainline.
16255 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16256 Thomas Preud'homme <thomas.preudhomme@arm.com>
16258 * config/arm/arm.md (nonsecure_call_internal): Do not force memory
16259 address in r4 when targeting Armv8.1-M Mainline.
16260 (nonsecure_call_value_internal): Likewise.
16261 * config/arm/thumb2.md (nonsecure_call_reg_thumb2): Make memory address
16262 a register match_operand again. Emit BLXNS when targeting
16263 Armv8.1-M Mainline.
16264 (nonsecure_call_value_reg_thumb2): Likewise.
16266 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16267 Thomas Preud'homme <thomas.preudhomme@arm.com>
16269 * config/arm/arm.c (arm_add_cfa_adjust_cfa_note): Declare early.
16270 (cmse_nonsecure_call_inline_register_clear): Define new lazy_fpclear
16271 variable as true when floating-point ABI is not hard. Replace
16272 check against TARGET_HARD_FLOAT_ABI by checks against lazy_fpclear.
16273 Generate VLSTM and VLLDM instruction respectively before and
16274 after a function call to cmse_nonsecure_call function.
16275 * config/arm/unspecs.md (VUNSPEC_VLSTM): Define unspec.
16276 (VUNSPEC_VLLDM): Likewise.
16277 * config/arm/vfp.md (lazy_store_multiple_insn): New define_insn.
16278 (lazy_load_multiple_insn): Likewise.
16280 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16281 Thomas Preud'homme <thomas.preudhomme@arm.com>
16283 * config/arm/arm.c (vfp_emit_fstmd): Declare early.
16284 (arm_emit_vfp_multi_reg_pop): Likewise.
16285 (cmse_nonsecure_call_inline_register_clear): Abstract number of VFP
16286 registers to clear in max_fp_regno. Emit VPUSH and VPOP to save and
16287 restore callee-saved VFP registers.
16289 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16290 Thomas Preud'homme <thomas.preudhomme@arm.com>
16292 * config/arm/arm.c (arm_emit_multi_reg_pop): Declare early.
16293 (cmse_nonsecure_call_clear_caller_saved): Rename into ...
16294 (cmse_nonsecure_call_inline_register_clear): This. Save and clear
16295 callee-saved GPRs as well as clear ip register before doing a nonsecure
16296 call then restore callee-saved GPRs after it when targeting
16297 Armv8.1-M Mainline.
16298 (arm_reorg): Adapt to function rename.
16300 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16301 Thomas Preud'homme <thomas.preudhomme@arm.com>
16303 * config/arm/arm-protos.h (clear_operation_p): Adapt prototype.
16304 * config/arm/arm.c (clear_operation_p): Extend to be able to check a
16305 clear_vfp_multiple pattern based on a new vfp parameter.
16306 (cmse_clear_registers): Generate VSCCLRM to clear VFP registers when
16307 targeting Armv8.1-M Mainline.
16308 (cmse_nonsecure_entry_clear_before_return): Clear VFP registers
16309 unconditionally when targeting Armv8.1-M Mainline architecture. Check
16310 whether VFP registers are available before looking call_used_regs for a
16312 * config/arm/predicates.md (clear_multiple_operation): Adapt to change
16313 of prototype of clear_operation_p.
16314 (clear_vfp_multiple_operation): New predicate.
16315 * config/arm/unspecs.md (VUNSPEC_VSCCLRM_VPR): New volatile unspec.
16316 * config/arm/vfp.md (clear_vfp_multiple): New define_insn.
16318 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16319 Thomas Preud'homme <thomas.preudhomme@arm.com>
16321 * config/arm/arm-protos.h (clear_operation_p): Declare.
16322 * config/arm/arm.c (clear_operation_p): New function.
16323 (cmse_clear_registers): Generate clear_multiple instruction pattern if
16324 targeting Armv8.1-M Mainline or successor.
16325 (output_return_instruction): Only output APSR register clearing if
16326 Armv8.1-M Mainline instructions not available.
16327 (thumb_exit): Likewise.
16328 * config/arm/predicates.md (clear_multiple_operation): New predicate.
16329 * config/arm/thumb2.md (clear_apsr): New define_insn.
16330 (clear_multiple): Likewise.
16331 * config/arm/unspecs.md (VUNSPEC_CLRM_APSR): New volatile unspec.
16333 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16334 Thomas Preud'homme <thomas.preudhomme@arm.com>
16336 * config/arm/arm.c (fp_sysreg_names): Declare and define.
16337 (use_return_insn): Also return false for Armv8.1-M Mainline.
16338 (output_return_instruction): Skip FPSCR clearing if Armv8.1-M
16339 Mainline instructions are available.
16340 (arm_compute_frame_layout): Allocate space in frame for FPCXTNS
16341 when targeting Armv8.1-M Mainline Security Extensions.
16342 (arm_expand_prologue): Save FPCXTNS if this is an Armv8.1-M
16343 Mainline entry function.
16344 (cmse_nonsecure_entry_clear_before_return): Clear IP and r4 if
16345 targeting Armv8.1-M Mainline or successor.
16346 (arm_expand_epilogue): Fix indentation of caller-saved register
16347 clearing. Restore FPCXTNS if this is an Armv8.1-M Mainline
16349 * config/arm/arm.h (TARGET_HAVE_FP_CMSE): New macro.
16350 (FP_SYSREGS): Likewise.
16351 (enum vfp_sysregs_encoding): Define enum.
16352 (fp_sysreg_names): Declare.
16353 * config/arm/unspecs.md (VUNSPEC_VSTR_VLDR): New volatile unspec.
16354 * config/arm/vfp.md (push_fpsysreg_insn): New define_insn.
16355 (pop_fpsysreg_insn): Likewise.
16357 2020-01-16 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
16358 Thomas Preud'homme <thomas.preudhomme@arm.com>
16360 * config/arm/arm-cpus.in (armv8_1m_main): New feature.
16361 (ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
16362 ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
16363 ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
16364 ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
16365 (ARMv8_1m_main): New feature group.
16366 (armv8.1-m.main): New architecture.
16367 * config/arm/arm-tables.opt: Regenerate.
16368 * config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
16369 (arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
16370 (arm_options_perform_arch_sanity_checks): Error out when targeting
16371 Armv8.1-M Mainline Security Extensions.
16372 * config/arm/arm.h (arm_arch8_1m_main): Declare.
16374 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16376 * config/aarch64/aarch64-simd-builtins.def (aarch64_bfdot,
16377 aarch64_bfdot_lane, aarch64_bfdot_laneq): New.
16378 * config/aarch64/aarch64-simd.md (aarch64_bfdot, aarch64_bfdot_lane,
16379 aarch64_bfdot_laneq): New.
16380 * config/aarch64/arm_bf16.h (vbfdot_f32, vbfdotq_f32,
16381 vbfdot_lane_f32, vbfdotq_lane_f32, vbfdot_laneq_f32,
16382 vbfdotq_laneq_f32): New.
16383 * config/aarch64/iterators.md (UNSPEC_BFDOT, Vbfdottype,
16384 VBFMLA_W, VBF): New.
16385 (isquadop): Add V4BF, V8BF.
16387 2020-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16389 * config/aarch64/aarch64-builtins.c: (enum aarch64_type_qualifiers):
16390 New qualifier_lane_quadtup_index, TYPES_TERNOP_SSUS,
16391 TYPES_QUADOPSSUS_LANE_QUADTUP, TYPES_QUADOPSSSU_LANE_QUADTUP.
16392 (aarch64_simd_expand_args): Add case SIMD_ARG_LANE_QUADTUP_INDEX.
16393 (aarch64_simd_expand_builtin): Add qualifier_lane_quadtup_index.
16394 * config/aarch64/aarch64-simd-builtins.def (usdot, usdot_lane,
16395 usdot_laneq, sudot_lane,sudot_laneq): New.
16396 * config/aarch64/aarch64-simd.md (aarch64_usdot): New.
16397 (aarch64_<sur>dot_lane): New.
16398 * config/aarch64/arm_neon.h (vusdot_s32): New.
16399 (vusdotq_s32): New.
16400 (vusdot_lane_s32): New.
16401 (vsudot_lane_s32): New.
16402 * config/aarch64/iterators.md (DOTPROD_I8MM): New iterator.
16403 (UNSPEC_USDOT, UNSPEC_SUDOT): New unspecs.
16405 2020-01-16 Martin Liska <mliska@suse.cz>
16407 * value-prof.c (dump_histogram_value): Fix
16408 obvious spacing issue.
16410 2020-01-16 Andrew Pinski <apinski@marvell.com>
16412 * tree-ssa-sccvn.c(vn_reference_lookup_3): Check lhs for
16413 !storage_order_barrier_p.
16415 2020-01-16 Andrew Pinski <apinski@marvell.com>
16417 * sched-int.h (_dep): Add unused bit-field field for the padding.
16418 * sched-deps.c (init_dep_1): Init unused field.
16420 2020-01-16 Andrew Pinski <apinski@marvell.com>
16422 * optabs.h (create_expand_operand): Initialize target field also.
16424 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
16426 PR tree-optimization/92429
16427 * tree-ssa-loop-niter.h (simplify_replace_tree): Add parameter.
16428 * tree-ssa-loop-niter.c (simplify_replace_tree): Add parameter to
16430 * tree-vect-loop.c (update_epilogue_vinfo): Do not fold when replacing
16433 2020-01-16 Richard Sandiford <richard.sandiford@arm.com>
16435 * config/aarch64/aarch64.c (aarch64_split_sve_subreg_move): Apply
16436 aarch64_sve_int_mode to each mode.
16438 2020-01-15 David Malcolm <dmalcolm@redhat.com>
16440 * doc/analyzer.texi (Overview): Add note about
16441 -fdump-ipa-analyzer.
16443 2020-01-15 Wilco Dijkstra <wdijkstr@arm.com>
16445 PR tree-optimization/93231
16446 * tree-ssa-forwprop.c (optimize_count_trailing_zeroes): Check
16447 input_type is unsigned. Use tree_to_shwi for shift constant.
16448 Check CST_STRING element size is CHAR_TYPE_SIZE bits.
16449 (simplify_count_trailing_zeroes): Add test to handle known non-zero
16450 inputs more efficiently.
16452 2020-01-15 Uroš Bizjak <ubizjak@gmail.com>
16454 * config/i386/i386.md (*movsf_internal): Do not require
16455 SSE2 ISA for alternatives 14 and 15.
16457 2020-01-15 Richard Biener <rguenther@suse.de>
16459 PR middle-end/93273
16460 * tree-eh.c (sink_clobbers): If we already visited the destination
16461 block do not defer insertion.
16462 (pass_lower_eh_dispatch::execute): Maintain BB_VISITED for
16463 the purpose of defered insertion.
16465 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16467 * BASE-VER: Bump to 10.0.1.
16469 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
16471 PR tree-optimization/93247
16472 * tree-vect-loop.c (update_epilogue_loop_vinfo): Check the access
16473 type of the stmt that we're going to vectorize.
16475 2020-01-15 Richard Sandiford <richard.sandiford@arm.com>
16477 * tree-vect-slp.c (vectorize_slp_instance_root_stmt): Use a
16478 VIEW_CONVERT_EXPR if the vectorized constructor has a diffeent
16481 2020-01-15 Martin Liska <mliska@suse.cz>
16483 * ipa-profile.c (ipa_profile_read_edge_summary): Do not allow
16484 2 calls of streamer_read_hwi in a function call.
16486 2020-01-15 Richard Biener <rguenther@suse.de>
16488 * alias.c (record_alias_subset): Avoid redundant work when
16489 subset is already recorded.
16491 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16493 * doc/invoke.texi (-fdiagnostics-show-cwe): Add note that some of
16494 the analyzer options provide CWE identifiers.
16496 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16498 * tree-diagnostic-path.cc (path_summary::event_range::print):
16499 When testing for UNKNOWN_LOCATION, look through ad-hoc wrappers
16500 using get_pure_location.
16502 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16504 PR tree-optimization/93262
16505 * tree-ssa-dse.c (maybe_trim_memstar_call): For *_chk builtins,
16506 perform head trimming only if the last argument is constant,
16507 either all ones, or larger or equal to head trim, in the latter
16508 case decrease the last argument by head_trim.
16510 PR tree-optimization/93249
16511 * tree-ssa-dse.c: Include builtins.h and gimple-fold.h.
16512 (maybe_trim_memstar_call): Move head_trim and tail_trim vars to
16513 function body scope, reindent. For BUILTIN_IN_STRNCPY*, don't
16514 perform head trim unless we can prove there are no '\0' chars
16515 from the source among the first head_trim chars.
16517 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16519 * Makefile.in (ANALYZER_OBJS): Add analyzer/function-set.o.
16521 2020-01-15 Jakub Jelinek <jakub@redhat.com>
16524 * config/i386/sse.md
16525 (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1,
16526 *<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1,
16527 *<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1,
16528 *<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Use
16529 just a single alternative instead of two, make operands 1 and 2
16532 2020-01-14 Jan Hubicka <hubicka@ucw.cz>
16535 * ipa-devirt.c (odr_types_equivalent_p): Compare TREE_ADDRESSABLE and
16538 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16540 * Makefile.in (lang_opt_files): Add analyzer.opt.
16541 (ANALYZER_OBJS): New.
16542 (OBJS): Add digraph.o, graphviz.o, ordered-hash-map-tests.o,
16543 tristate.o and ANALYZER_OBJS.
16544 (TEXI_GCCINT_FILES): Add analyzer.texi.
16545 * common.opt (-fanalyzer): New driver option.
16546 * config.in: Regenerate.
16547 * configure: Regenerate.
16548 * configure.ac (--disable-analyzer, ENABLE_ANALYZER): New option.
16549 (gccdepdir): Also create depdir for "analyzer" subdir.
16550 * digraph.cc: New file.
16551 * digraph.h: New file.
16552 * doc/analyzer.texi: New file.
16553 * doc/gccint.texi ("Static Analyzer") New menu item.
16554 (analyzer.texi): Include it.
16555 * doc/invoke.texi ("Static Analyzer Options"): New list and new section.
16556 ("Warning Options"): Add static analysis warnings to the list.
16557 (-Wno-analyzer-double-fclose): New option.
16558 (-Wno-analyzer-double-free): New option.
16559 (-Wno-analyzer-exposure-through-output-file): New option.
16560 (-Wno-analyzer-file-leak): New option.
16561 (-Wno-analyzer-free-of-non-heap): New option.
16562 (-Wno-analyzer-malloc-leak): New option.
16563 (-Wno-analyzer-possible-null-argument): New option.
16564 (-Wno-analyzer-possible-null-dereference): New option.
16565 (-Wno-analyzer-null-argument): New option.
16566 (-Wno-analyzer-null-dereference): New option.
16567 (-Wno-analyzer-stale-setjmp-buffer): New option.
16568 (-Wno-analyzer-tainted-array-index): New option.
16569 (-Wno-analyzer-use-after-free): New option.
16570 (-Wno-analyzer-use-of-pointer-in-stale-stack-frame): New option.
16571 (-Wno-analyzer-use-of-uninitialized-value): New option.
16572 (-Wanalyzer-too-complex): New option.
16573 (-fanalyzer-call-summaries): New warning.
16574 (-fanalyzer-checker=): New warning.
16575 (-fanalyzer-fine-grained): New warning.
16576 (-fno-analyzer-state-merge): New warning.
16577 (-fno-analyzer-state-purge): New warning.
16578 (-fanalyzer-transitivity): New warning.
16579 (-fanalyzer-verbose-edges): New warning.
16580 (-fanalyzer-verbose-state-changes): New warning.
16581 (-fanalyzer-verbosity=): New warning.
16582 (-fdump-analyzer): New warning.
16583 (-fdump-analyzer-callgraph): New warning.
16584 (-fdump-analyzer-exploded-graph): New warning.
16585 (-fdump-analyzer-exploded-nodes): New warning.
16586 (-fdump-analyzer-exploded-nodes-2): New warning.
16587 (-fdump-analyzer-exploded-nodes-3): New warning.
16588 (-fdump-analyzer-supergraph): New warning.
16589 * doc/sourcebuild.texi (dg-require-dot): New.
16590 (dg-check-dot): New.
16591 * gdbinit.in (break-on-saved-diagnostic): New command.
16592 * graphviz.cc: New file.
16593 * graphviz.h: New file.
16594 * ordered-hash-map-tests.cc: New file.
16595 * ordered-hash-map.h: New file.
16596 * passes.def (pass_analyzer): Add before
16597 pass_ipa_whole_program_visibility.
16598 * selftest-run-tests.c (selftest::run_tests): Call
16599 selftest::ordered_hash_map_tests_cc_tests.
16600 * selftest.h (selftest::ordered_hash_map_tests_cc_tests): New
16602 * shortest-paths.h: New file.
16603 * timevar.def (TV_ANALYZER): New timevar.
16604 (TV_ANALYZER_SUPERGRAPH): Likewise.
16605 (TV_ANALYZER_STATE_PURGE): Likewise.
16606 (TV_ANALYZER_PLAN): Likewise.
16607 (TV_ANALYZER_SCC): Likewise.
16608 (TV_ANALYZER_WORKLIST): Likewise.
16609 (TV_ANALYZER_DUMP): Likewise.
16610 (TV_ANALYZER_DIAGNOSTICS): Likewise.
16611 (TV_ANALYZER_SHORTEST_PATHS): Likewise.
16612 * tree-pass.h (make_pass_analyzer): New decl.
16613 * tristate.cc: New file.
16614 * tristate.h: New file.
16616 2020-01-14 Uroš Bizjak <ubizjak@gmail.com>
16619 * config/i386/i386.md (*movsf_internal): Require SSE2 ISA for
16620 alternatives 9 and 10.
16622 2020-01-14 David Malcolm <dmalcolm@redhat.com>
16624 * attribs.c (excl_hash_traits::empty_zero_p): New static constant.
16625 * gcov.c (function_start_pair_hash::empty_zero_p): Likewise.
16626 * graphite.c (struct sese_scev_hash::empty_zero_p): Likewise.
16627 * hash-map-tests.c (selftest::test_nonzero_empty_key): New selftest.
16628 (selftest::hash_map_tests_c_tests): Call it.
16629 * hash-map-traits.h (simple_hashmap_traits::empty_zero_p):
16630 New static constant, using the value of = H::empty_zero_p.
16631 (unbounded_hashmap_traits::empty_zero_p): Likewise, using the value
16632 from default_hash_traits <Value>.
16633 * hash-map.h (hash_map::empty_zero_p): Likewise, using the value
16635 * hash-set-tests.c (value_hash_traits::empty_zero_p): Likewise.
16636 * hash-table.h (hash_table::alloc_entries): Guard the loop of
16637 calls to mark_empty with !Descriptor::empty_zero_p.
16638 (hash_table::empty_slow): Conditionalize the memset call with a
16639 check that Descriptor::empty_zero_p; otherwise, loop through the
16640 entries calling mark_empty on them.
16641 * hash-traits.h (int_hash::empty_zero_p): New static constant.
16642 (pointer_hash::empty_zero_p): Likewise.
16643 (pair_hash::empty_zero_p): Likewise.
16644 * ipa-devirt.c (default_hash_traits <type_pair>::empty_zero_p):
16646 * ipa-prop.c (ipa_bit_ggc_hash_traits::empty_zero_p): Likewise.
16647 (ipa_vr_ggc_hash_traits::empty_zero_p): Likewise.
16648 * profile.c (location_triplet_hash::empty_zero_p): Likewise.
16649 * sanopt.c (sanopt_tree_triplet_hash::empty_zero_p): Likewise.
16650 (sanopt_tree_couple_hash::empty_zero_p): Likewise.
16651 * tree-hasher.h (int_tree_hasher::empty_zero_p): Likewise.
16652 * tree-ssa-sccvn.c (vn_ssa_aux_hasher::empty_zero_p): Likewise.
16653 * tree-vect-slp.c (bst_traits::empty_zero_p): Likewise.
16654 * tree-vectorizer.h
16655 (default_hash_traits<scalar_cond_masked_key>::empty_zero_p):
16658 2020-01-14 Kewen Lin <linkw@gcc.gnu.org>
16660 * cfgloopanal.c (average_num_loop_insns): Free bbs when early return,
16661 fix typo on return value.
16663 2020-01-14 Xiong Hu Luo <luoxhu@linux.ibm.com>
16666 * cgraph.c (symbol_table::create_edge): Init speculative_id and
16668 (cgraph_edge::make_speculative): Add param for setting speculative_id
16670 (cgraph_edge::speculative_call_info): Update comments and find reference
16671 by speculative_id for multiple indirect targets.
16672 (cgraph_edge::resolve_speculation): Decrease the speculations
16673 for indirect edge, drop it's speculative if not direct target
16674 left. Update comments.
16675 (cgraph_edge::redirect_call_stmt_to_callee): Likewise.
16676 (cgraph_node::dump): Print num_speculative_call_targets.
16677 (cgraph_node::verify_node): Don't report error if speculative
16678 edge not include statement.
16679 (cgraph_edge::num_speculative_call_targets_p): New function.
16680 * cgraph.h (int common_target_id): Remove.
16681 (int common_target_probability): Remove.
16682 (num_speculative_call_targets): New variable.
16683 (make_speculative): Add param for setting speculative_id.
16684 (cgraph_edge::num_speculative_call_targets_p): New declare.
16685 (target_prob): New variable.
16686 (speculative_id): New variable.
16687 * ipa-fnsummary.c (analyze_function_body): Create and duplicate
16688 call summaries for multiple speculative call targets.
16689 * cgraphclones.c (cgraph_node::create_clone): Clone speculative_id.
16690 * ipa-profile.c (struct speculative_call_target): New struct.
16691 (class speculative_call_summary): New class.
16692 (class speculative_call_summaries): New class.
16693 (call_sums): New variable.
16694 (ipa_profile_generate_summary): Generate indirect multiple targets summaries.
16695 (ipa_profile_write_edge_summary): New function.
16696 (ipa_profile_write_summary): Stream out indirect multiple targets summaries.
16697 (ipa_profile_dump_all_summaries): New function.
16698 (ipa_profile_read_edge_summary): New function.
16699 (ipa_profile_read_summary_section): New function.
16700 (ipa_profile_read_summary): Stream in indirect multiple targets summaries.
16701 (ipa_profile): Generate num_speculative_call_targets from
16703 * ipa-ref.h (speculative_id): New variable.
16704 * ipa-utils.c (ipa_merge_profiles): Update with target_prob.
16705 * lto-cgraph.c (lto_output_edge): Remove indirect common_target_id and
16706 common_target_probability. Stream out speculative_id and
16707 num_speculative_call_targets.
16708 (input_edge): Likewise.
16709 * predict.c (dump_prediction): Remove edges count assert to be
16711 * symtab.c (symtab_node::create_reference): Init speculative_id.
16712 (symtab_node::clone_references): Clone speculative_id.
16713 (symtab_node::clone_referring): Clone speculative_id.
16714 (symtab_node::clone_reference): Clone speculative_id.
16715 (symtab_node::clear_stmts_in_references): Clear speculative_id.
16716 * tree-inline.c (copy_bb): Duplicate all the speculative edges
16717 if indirect call contains multiple speculative targets.
16718 * value-prof.h (check_ic_target): Remove.
16719 * value-prof.c (gimple_value_profile_transformations):
16720 Use void function gimple_ic_transform.
16721 * value-prof.c (gimple_ic_transform): Handle topn case.
16722 Fix comment typos. Change it to a void function.
16724 2020-01-13 Andrew Pinski <apinski@marvell.com>
16726 * config/aarch64/aarch64-cores.def (octeontx2): New define.
16727 (octeontx2t98): New define.
16728 (octeontx2t96): New define.
16729 (octeontx2t93): New define.
16730 (octeontx2f95): New define.
16731 (octeontx2f95n): New define.
16732 (octeontx2f95mm): New define.
16733 * config/aarch64/aarch64-tune.md: Regenerate.
16734 * doc/invoke.texi (-mcpu=): Document the new cpu types.
16736 2020-01-13 Jason Merrill <jason@redhat.com>
16738 PR c++/33799 - destroy return value if local cleanup throws.
16739 * gimplify.c (gimplify_return_expr): Handle COMPOUND_EXPR.
16741 2020-01-13 Martin Liska <mliska@suse.cz>
16743 * ipa-cp.c (get_max_overall_size): Use newly
16744 renamed param param_ipa_cp_unit_growth.
16745 * params.opt: Remove legacy param name.
16747 2020-01-13 Martin Sebor <msebor@redhat.com>
16749 PR tree-optimization/93213
16750 * tree-ssa-strlen.c (handle_store): Only allow single-byte nul-over-nul
16751 stores to be eliminated.
16753 2020-01-13 Martin Liska <mliska@suse.cz>
16755 * opts.c (print_help): Do not print CL_PARAM
16756 and CL_WARNING for CL_OPTIMIZATION.
16758 2020-01-13 Jonathan Wakely <jwakely@redhat.com>
16761 * doc/invoke.texi (Warning Options): Add caveat about some warnings
16762 depending on optimization settings.
16764 2020-01-13 Jakub Jelinek <jakub@redhat.com>
16766 PR tree-optimization/90838
16767 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16768 SCALAR_INT_TYPE_MODE directly in CTZ_DEFINED_VALUE_AT_ZERO macro
16769 argument rather than to initialize temporary for targets that
16770 don't use the mode argument at all. Initialize ctzval to avoid
16773 2020-01-10 Thomas Schwinge <thomas@codesourcery.com>
16775 * tree.h (OMP_CLAUSE_USE_DEVICE_PTR_IF_PRESENT): New definition.
16776 * tree-core.h: Document it.
16777 * gimplify.c (gimplify_omp_workshare): Set it.
16778 * omp-low.c (lower_omp_target): Use it.
16779 * tree-pretty-print.c (dump_omp_clause): Print it.
16781 * omp-low.c (lower_omp_target) <OMP_CLAUSE_USE_DEVICE_PTR etc.>:
16782 Assert that for OpenACC we always have 'GOMP_MAP_USE_DEVICE_PTR'.
16784 2020-01-10 David Malcolm <dmalcolm@redhat.com>
16786 * Makefile.in (OBJS): Add tree-diagnostic-path.o.
16787 * common.opt (fdiagnostics-path-format=): New option.
16788 (diagnostic_path_format): New enum.
16789 (fdiagnostics-show-path-depths): New option.
16790 * coretypes.h (diagnostic_event_id_t): New forward decl.
16791 * diagnostic-color.c (color_dict): Add "path".
16792 * diagnostic-event-id.h: New file.
16793 * diagnostic-format-json.cc (json_from_expanded_location): Make
16795 (json_end_diagnostic): Call context->make_json_for_path if it
16796 exists and the diagnostic has a path.
16797 (diagnostic_output_format_init): Clear context->print_path.
16798 * diagnostic-path.h: New file.
16799 * diagnostic-show-locus.c (colorizer::set_range): Special-case
16800 when printing a run of events in a diagnostic_path so that they
16801 all get the same color.
16802 (layout::m_diagnostic_path_p): New field.
16803 (layout::layout): Initialize it.
16804 (layout::print_any_labels): Don't colorize the label text for an
16805 event in a diagnostic_path.
16806 (gcc_rich_location::add_location_if_nearby): Add
16807 "restrict_to_current_line_spans" and "label" params. Pass the
16808 former to layout.maybe_add_location_range; pass the latter
16809 when calling add_range.
16810 * diagnostic.c: Include "diagnostic-path.h".
16811 (diagnostic_initialize): Initialize context->path_format and
16812 context->show_path_depths.
16813 (diagnostic_show_any_path): New function.
16814 (diagnostic_path::interprocedural_p): New function.
16815 (diagnostic_report_diagnostic): Call diagnostic_show_any_path.
16816 (simple_diagnostic_path::num_events): New function.
16817 (simple_diagnostic_path::get_event): New function.
16818 (simple_diagnostic_path::add_event): New function.
16819 (simple_diagnostic_event::simple_diagnostic_event): New ctor.
16820 (simple_diagnostic_event::~simple_diagnostic_event): New dtor.
16821 (debug): New overload taking a diagnostic_path *.
16822 * diagnostic.def (DK_DIAGNOSTIC_PATH): New.
16823 * diagnostic.h (enum diagnostic_path_format): New enum.
16824 (json::value): New forward decl.
16825 (diagnostic_context::path_format): New field.
16826 (diagnostic_context::show_path_depths): New field.
16827 (diagnostic_context::print_path): New callback field.
16828 (diagnostic_context::make_json_for_path): New callback field.
16829 (diagnostic_show_any_path): New decl.
16830 (json_from_expanded_location): New decl.
16831 * doc/invoke.texi (-fdiagnostics-path-format=): New option.
16832 (-fdiagnostics-show-path-depths): New option.
16833 (-fdiagnostics-color): Add "path" to description of default
16834 GCC_COLORS; describe it.
16835 (-fdiagnostics-format=json): Document how diagnostic paths are
16836 represented in the JSON output format.
16837 * gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
16838 Add optional params "restrict_to_current_line_spans" and "label".
16839 * opts.c (common_handle_option): Handle
16840 OPT_fdiagnostics_path_format_ and
16841 OPT_fdiagnostics_show_path_depths.
16842 * pretty-print.c: Include "diagnostic-event-id.h".
16843 (pp_format): Implement "%@" format code for printing
16844 diagnostic_event_id_t *.
16845 (selftest::test_pp_format): Add tests for "%@".
16846 * selftest-run-tests.c (selftest::run_tests): Call
16847 selftest::tree_diagnostic_path_cc_tests.
16848 * selftest.h (selftest::tree_diagnostic_path_cc_tests): New decl.
16849 * toplev.c (general_init): Initialize global_dc->path_format and
16850 global_dc->show_path_depths.
16851 * tree-diagnostic-path.cc: New file.
16852 * tree-diagnostic.c (maybe_unwind_expanded_macro_loc): Make
16853 non-static. Drop "diagnostic" param in favor of storing the
16854 original value of "where" and re-using it.
16855 (virt_loc_aware_diagnostic_finalizer): Update for dropped param of
16856 maybe_unwind_expanded_macro_loc.
16857 (tree_diagnostics_defaults): Initialize context->print_path and
16858 context->make_json_for_path.
16859 * tree-diagnostic.h (default_tree_diagnostic_path_printer): New
16861 (default_tree_make_json_for_path): New decl.
16862 (maybe_unwind_expanded_macro_loc): New decl.
16864 2020-01-10 Jakub Jelinek <jakub@redhat.com>
16866 PR tree-optimization/93210
16867 * fold-const.h (native_encode_initializer,
16868 can_native_interpret_type_p): Declare.
16869 * fold-const.c (native_encode_string): Fix up handling with off != -1,
16871 (native_encode_initializer): New function, moved from dwarf2out.c.
16872 Adjust to native_encode_expr compatible arguments, including dry-run
16873 and partial extraction modes. Don't handle STRING_CST.
16874 (can_native_interpret_type_p): No longer static.
16875 * gimple-fold.c (fold_ctor_reference): For native_encode_expr, verify
16876 offset / BITS_PER_UNIT fits into int and don't call it if
16877 can_native_interpret_type_p fails. If suboff is NULL and for
16878 CONSTRUCTOR fold_{,non}array_ctor_reference returns NULL, retry with
16879 native_encode_initializer.
16880 (fold_const_aggregate_ref_1): Formatting fix.
16881 * dwarf2out.c (native_encode_initializer): Moved to fold-const.c.
16882 (tree_add_const_value_attribute): Adjust caller.
16884 PR tree-optimization/90838
16885 * tree-ssa-forwprop.c (simplify_count_trailing_zeroes): Use
16886 SCALAR_INT_TYPE_MODE instead of TYPE_MODE as operand of
16887 CTZ_DEFINED_VALUE_AT_ZERO.
16889 2020-01-10 Vladimir Makarov <vmakarov@redhat.com>
16891 PR inline-asm/93027
16892 * lra-constraints.c (match_reload): Permit input operands have the
16893 same mode as output while other input operands have a different
16896 2020-01-10 Wilco Dijkstra <wdijkstr@arm.com>
16898 PR tree-optimization/90838
16899 * tree-ssa-forwprop.c (check_ctz_array): Add new function.
16900 (check_ctz_string): Likewise.
16901 (optimize_count_trailing_zeroes): Likewise.
16902 (simplify_count_trailing_zeroes): Likewise.
16903 (pass_forwprop::execute): Try ctz simplification.
16904 * match.pd: Add matching for ctz idioms.
16906 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16908 * config/aarch64/aarch64.c (aarch64_invalid_conversion): New function
16910 (aarch64_invalid_unary_op): New function for target hook.
16911 (aarch64_invalid_binary_op): New function for target hook.
16913 2020-01-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
16915 * config.gcc: Add arm_bf16.h.
16916 * config/aarch64/aarch64-builtins.c
16917 (aarch64_simd_builtin_std_type): Add BFmode.
16918 (aarch64_init_simd_builtin_types): Define element types for vector
16920 (aarch64_init_bf16_types): New function.
16921 (aarch64_general_init_builtins): Add arm_init_bf16_types function call.
16922 * config/aarch64/aarch64-modes.def: Add BFmode and V4BF, V8BF vector
16924 * config/aarch64/aarch64-simd-builtin-types.def: Add BF SIMD types.
16925 * config/aarch64/aarch64-simd.md: Add BF vector types to NEON move
16927 * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): Add V4BF.
16928 (AARCH64_VALID_SIMD_QREG_MODE): Add V8BF.
16929 * config/aarch64/aarch64.c
16930 (aarch64_classify_vector_mode): Add support for BF types.
16931 (aarch64_gimplify_va_arg_expr): Add support for BF types.
16932 (aarch64_vq_mode): Add support for BF types.
16933 (aarch64_simd_container_mode): Add support for BF types.
16934 (aarch64_mangle_type): Add support for BF scalar type.
16935 * config/aarch64/aarch64.md: Add BFmode to movhf pattern.
16936 * config/aarch64/arm_bf16.h: New file.
16937 * config/aarch64/arm_neon.h: Add arm_bf16.h and Bfloat vector types.
16938 * config/aarch64/iterators.md: Add BF types to mode attributes.
16939 (HFBF, GPF_TF_F16_MOV, VDMOV, VQMOV, VQMOV_NO2Em VALL_F16MOV): New.
16941 2020-01-10 Jason Merrill <jason@redhat.com>
16943 PR c++/93173 - incorrect tree sharing.
16944 * gimplify.c (copy_if_shared): No longer static.
16945 * gimplify.h: Declare it.
16947 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16949 * doc/invoke.texi (-msve-vector-bits=): Document that
16950 -msve-vector-bits=128 now generates VL-specific code for
16951 little-endian targets.
16952 * config/aarch64/aarch64-sve-builtins.cc (register_builtin_types): Use
16953 build_vector_type_for_mode to construct the data vector types.
16954 * config/aarch64/aarch64.c (aarch64_convert_sve_vector_bits): Generate
16955 VL-specific code for -msve-vector-bits=128 on little-endian targets.
16956 (aarch64_simd_container_mode): Always prefer Advanced SIMD modes
16957 for 128-bit vectors.
16959 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16961 * config/aarch64/aarch64.c (aarch64_evpc_sel): Fix gen_vcond_mask
16964 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16966 * config/aarch64/aarch64-builtins.c
16967 (aarch64_builtin_vectorized_function): Check for specific vector modes,
16968 rather than checking the number of elements and the element mode.
16970 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16972 * tree-vect-loop.c (vect_create_epilog_for_reduction): Use
16973 get_related_vectype_for_scalar_type rather than build_vector_type
16974 to create the index type for a conditional reduction.
16976 2020-01-10 Richard Sandiford <richard.sandiford@arm.com>
16978 * tree-vect-loop.c (update_epilogue_loop_vinfo): Update DR_REF
16979 for any type of gather or scatter, including strided accesses.
16981 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16983 * tree-vectorizer.h (get_dr_vinfo_offset): Add missing function
16986 2020-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
16988 * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Use
16989 get_dr_vinfo_offset
16990 * tree-vect-loop.c (update_epilogue_loop_vinfo): Remove orig_drs_init
16991 parameter and its use to reset DR_OFFSET's.
16992 (vect_transform_loop): Remove orig_drs_init argument.
16993 * tree-vect-loop-manip.c (vect_update_init_of_dr): Update the offset
16994 member of dr_vec_info rather than the offset of the associated
16995 data_reference's innermost_loop_behavior.
16996 (vect_update_init_of_dr): Pass dr_vec_info instead of data_reference.
16997 (vect_do_peeling): Remove orig_drs_init parameter and its construction.
16998 * tree-vect-stmts.c (check_scan_store): Replace use of DR_OFFSET with
16999 get_dr_vinfo_offset.
17000 (vectorizable_store): Likewise.
17001 (vectorizable_load): Likewise.
17003 2020-01-10 Richard Biener <rguenther@suse.de>
17005 * gimple-ssa-store-merging
17006 (pass_store_merging::terminate_all_aliasing_chains): Cache alias info.
17008 2020-01-10 Martin Liska <mliska@suse.cz>
17011 * ipa-inline-analysis.c (offline_size): Make proper parenthesis
17012 encapsulation that was there before r280040.
17014 2020-01-10 Richard Biener <rguenther@suse.de>
17016 PR middle-end/93199
17017 * tree-eh.c (sink_clobbers): Move clobbers to out-of-IL
17018 sequences to avoid walking them again for secondary opportunities.
17019 (pass_lower_eh_dispatch::execute): Instead actually insert
17022 2020-01-10 Richard Biener <rguenther@suse.de>
17024 PR middle-end/93199
17025 * tree-eh.c (redirect_eh_edge_1): Avoid some work if possible.
17026 (cleanup_all_empty_eh): Walk landing pads in reverse order to
17027 avoid quadraticness.
17029 2020-01-10 Martin Jambor <mjambor@suse.cz>
17031 * params.opt (param_ipa_sra_max_replacements): Mark as Optimization.
17032 * ipa-sra.c (pull_accesses_from_callee): New parameter caller, use it
17033 to get param_ipa_sra_max_replacements.
17034 (param_splitting_across_edge): Pass the caller to
17035 pull_accesses_from_callee.
17037 2020-01-10 Martin Jambor <mjambor@suse.cz>
17039 * params.opt (param_ipcp_unit_growth): Mark as Optimization.
17040 * ipa-cp.c (max_new_size): Removed.
17041 (orig_overall_size): New variable.
17042 (get_max_overall_size): New function.
17043 (estimate_local_effects): Use it. Adjust dump.
17044 (decide_about_value): Likewise.
17045 (ipcp_propagate_stage): Do not calculate max_new_size, just store
17046 orig_overall_size. Adjust dump.
17047 (ipa_cp_c_finalize): Clear orig_overall_size instead of max_new_size.
17049 2020-01-10 Martin Jambor <mjambor@suse.cz>
17051 * params.opt (param_ipa_max_agg_items): Mark as Optimization
17052 * ipa-cp.c (merge_agg_lats_step): New parameter max_agg_items, use
17053 instead of param_ipa_max_agg_items.
17054 (merge_aggregate_lattices): Extract param_ipa_max_agg_items from
17055 optimization info for the callee.
17057 2020-01-09 Kwok Cheung Yeung <kcy@codesourcery.com>
17059 * lto-streamer-in.c (input_function): Remove streamed-in inline debug
17060 markers if debug_inline_points is false.
17062 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17064 * config.gcc (aarch64*-*-*): Add aarch64-sve-builtins-sve2.o to
17066 * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
17067 aarch64-sve-builtins-base.def, aarch64-sve-builtins-sve2.def and
17068 aarch64-sve-builtins-sve2.h.
17069 (aarch64-sve-builtins-sve2.o): New rule.
17070 * config/aarch64/aarch64.h (AARCH64_ISA_SVE2_AES): New macro.
17071 (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3): Likewise.
17072 (AARCH64_ISA_SVE2_SM4, TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Likewise.
17073 (TARGET_SVE2_SHA, TARGET_SVE2_SM4): Likewise.
17074 * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Handle
17075 TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3 and
17077 * config/aarch64/aarch64-sve.md: Update comments with SVE2
17078 instructions that are handled here.
17079 (@cond_asrd<mode>): Generalize to...
17080 (@cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>): ...this.
17081 (*cond_asrd<mode>_2): Generalize to...
17082 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_2): ...this.
17083 (*cond_asrd<mode>_z): Generalize to...
17084 (*cond_<SVE_INT_SHIFT_IMM:sve_int_op><mode>_z): ...this.
17085 * config/aarch64/aarch64.md (UNSPEC_LDNT1_GATHER): New unspec.
17086 (UNSPEC_STNT1_SCATTER, UNSPEC_WHILEGE, UNSPEC_WHILEGT): Likewise.
17087 (UNSPEC_WHILEHI, UNSPEC_WHILEHS): Likewise.
17088 * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): New
17090 (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
17091 (@aarch64_scatter_stnt<mode>): Likewise.
17092 (@aarch64_scatter_stnt_<SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>)
17093 (@aarch64_mul_lane_<mode>): Likewise.
17094 (@aarch64_sve_suqadd<mode>_const): Likewise.
17095 (*<sur>h<addsub><mode>): Generalize to...
17096 (@aarch64_pred_<SVE2_COND_INT_BINARY_REV:sve_int_op><mode>): ...this
17098 (@cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>): New expander.
17099 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_2): New pattern.
17100 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_3): Likewise.
17101 (*cond_<SVE2_COND_INT_BINARY:sve_int_op><mode>_any): Likewise.
17102 (*cond_<SVE2_COND_INT_BINARY_NOREV:sve_int_op><mode>_z): Likewise.
17103 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op><mode>):: Likewise.
17104 (@aarch64_sve_<SVE2_INT_BINARY:sve_int_op>_lane_<mode>): Likewise.
17105 (@aarch64_pred_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): Likewise.
17106 (@cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>): New expander.
17107 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_2): New pattern.
17108 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_3): Likewise.
17109 (*cond_<SVE2_COND_INT_SHIFT:sve_int_op><mode>_any): Likewise.
17110 (@aarch64_sve_<SVE2_INT_TERNARY:sve_int_op><mode>): Likewise.
17111 (@aarch64_sve_<SVE2_INT_TERNARY_LANE:sve_int_op>_lane_<mode>)
17112 (@aarch64_sve_add_mul_lane_<mode>): Likewise.
17113 (@aarch64_sve_sub_mul_lane_<mode>): Likewise.
17114 (@aarch64_sve2_xar<mode>): Likewise.
17115 (@aarch64_sve2_bcax<mode>): Likewise.
17116 (*aarch64_sve2_eor3<mode>): Rename to...
17117 (@aarch64_sve2_eor3<mode>): ...this.
17118 (@aarch64_sve2_bsl<mode>): New expander.
17119 (@aarch64_sve2_nbsl<mode>): Likewise.
17120 (@aarch64_sve2_bsl1n<mode>): Likewise.
17121 (@aarch64_sve2_bsl2n<mode>): Likewise.
17122 (@aarch64_sve_add_<SHIFTRT:sve_int_op><mode>): Likewise.
17123 (*aarch64_sve2_sra<mode>): Add MOVPRFX support.
17124 (@aarch64_sve_add_<VRSHR_N:sve_int_op><mode>): New pattern.
17125 (@aarch64_sve_<SVE2_INT_SHIFT_INSERT:sve_int_op><mode>): Likewise.
17126 (@aarch64_sve2_<USMAX:su>aba<mode>): New expander.
17127 (*aarch64_sve2_<USMAX:su>aba<mode>): New pattern.
17128 (@aarch64_sve_<SVE2_INT_BINARY_WIDE:sve_int_op><mode>): Likewise.
17129 (<su>mull<bt><Vwide>): Generalize to...
17130 (@aarch64_sve_<SVE2_INT_BINARY_LONG:sve_int_op><mode>): ...this new
17132 (@aarch64_sve_<SVE2_INT_BINARY_LONG_lANE:sve_int_op>_lane_<mode>)
17133 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_LONG:sve_int_op><mode>)
17134 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG:sve_int_op><mode>)
17135 (@aarch64_sve_add_<SVE2_INT_ADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
17136 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG:sve_int_op><mode>)
17137 (@aarch64_sve_qadd_<SVE2_INT_QADD_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
17138 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG:sve_int_op><mode>)
17139 (@aarch64_sve_sub_<SVE2_INT_SUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
17140 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG:sve_int_op><mode>)
17141 (@aarch64_sve_qsub_<SVE2_INT_QSUB_BINARY_LONG_LANE:sve_int_op>_lane_<mode>)
17142 (@aarch64_sve_<SVE2_FP_TERNARY_LONG:sve_fp_op><mode>): New patterns.
17143 (@aarch64_<SVE2_FP_TERNARY_LONG_LANE:sve_fp_op>_lane_<mode>)
17144 (@aarch64_sve_<SVE2_INT_UNARY_NARROWB:sve_int_op><mode>): Likewise.
17145 (@aarch64_sve_<SVE2_INT_UNARY_NARROWT:sve_int_op><mode>): Likewise.
17146 (@aarch64_sve_<SVE2_INT_BINARY_NARROWB:sve_int_op><mode>): Likewise.
17147 (@aarch64_sve_<SVE2_INT_BINARY_NARROWT:sve_int_op><mode>): Likewise.
17148 (<SHRNB:r>shrnb<mode>): Generalize to...
17149 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWB:sve_int_op><mode>): ...this
17151 (<SHRNT:r>shrnt<mode>): Generalize to...
17152 (@aarch64_sve_<SVE2_INT_SHIFT_IMM_NARROWT:sve_int_op><mode>): ...this
17154 (@aarch64_pred_<SVE2_INT_BINARY_PAIR:sve_int_op><mode>): New pattern.
17155 (@aarch64_pred_<SVE2_FP_BINARY_PAIR:sve_fp_op><mode>): Likewise.
17156 (@cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>): New expander.
17157 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_2): New pattern.
17158 (*cond_<SVE2_INT_BINARY_PAIR_LONG:sve_int_op><mode>_z): Likewise.
17159 (@aarch64_sve_<SVE2_INT_CADD:optab><mode>): Likewise.
17160 (@aarch64_sve_<SVE2_INT_CMLA:optab><mode>): Likewise.
17161 (@aarch64_<SVE2_INT_CMLA:optab>_lane_<mode>): Likewise.
17162 (@aarch64_sve_<SVE2_INT_CDOT:optab><mode>): Likewise.
17163 (@aarch64_<SVE2_INT_CDOT:optab>_lane_<mode>): Likewise.
17164 (@aarch64_pred_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): Likewise.
17165 (@cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New expander.
17166 (*cond_<SVE2_COND_FP_UNARY_LONG:sve_fp_op><mode>): New pattern.
17167 (@aarch64_sve2_cvtnt<mode>): Likewise.
17168 (@aarch64_pred_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): Likewise.
17169 (@cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>): New expander.
17170 (*cond_<SVE2_COND_FP_UNARY_NARROWB:sve_fp_op><mode>_any): New pattern.
17171 (@aarch64_sve2_cvtxnt<mode>): Likewise.
17172 (@aarch64_pred_<SVE2_U32_UNARY:sve_int_op><mode>): Likewise.
17173 (@cond_<SVE2_U32_UNARY:sve_int_op><mode>): New expander.
17174 (*cond_<SVE2_U32_UNARY:sve_int_op><mode>): New pattern.
17175 (@aarch64_pred_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): Likewise.
17176 (@cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New expander.
17177 (*cond_<SVE2_COND_INT_UNARY_FP:sve_fp_op><mode>): New pattern.
17178 (@aarch64_sve2_pmul<mode>): Likewise.
17179 (@aarch64_sve_<SVE2_PMULL:optab><mode>): Likewise.
17180 (@aarch64_sve_<SVE2_PMULL_PAIR:optab><mode>): Likewise.
17181 (@aarch64_sve2_tbl2<mode>): Likewise.
17182 (@aarch64_sve2_tbx<mode>): Likewise.
17183 (@aarch64_sve_<SVE2_INT_BITPERM:sve_int_op><mode>): Likewise.
17184 (@aarch64_sve2_histcnt<mode>): Likewise.
17185 (@aarch64_sve2_histseg<mode>): Likewise.
17186 (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
17187 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
17188 (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
17189 (aarch64_sve2_aes<CRYPTO_AES:aes_op>): Likewise.
17190 (aarch64_sve2_aes<CRYPTO_AESMC:aesmc_op>): Likewise.
17191 (*aarch64_sve2_aese_fused, *aarch64_sve2_aesd_fused): Likewise.
17192 (aarch64_sve2_rax1, aarch64_sve2_sm4e, aarch64_sve2_sm4ekey): Likewise.
17193 (<su>mulh<r>s<mode>3): Update after above pattern name changes.
17194 * config/aarch64/iterators.md (VNx16QI_ONLY, VNx4SF_ONLY)
17195 (SVE_STRUCT2, SVE_FULL_BHI, SVE_FULL_HSI, SVE_FULL_HDI)
17196 (SVE2_PMULL_PAIR_I): New mode iterators.
17197 (UNSPEC_ADCLB, UNSPEC_ADCLT, UNSPEC_ADDHNB, UNSPEC_ADDHNT, UNSPEC_BDEP)
17198 (UNSPEC_BEXT, UNSPEC_BGRP, UNSPEC_CADD90, UNSPEC_CADD270, UNSPEC_CDOT)
17199 (UNSPEC_CDOT90, UNSPEC_CDOT180, UNSPEC_CDOT270, UNSPEC_CMLA)
17200 (UNSPEC_CMLA90, UNSPEC_CMLA180, UNSPEC_CMLA270, UNSPEC_COND_FCVTLT)
17201 (UNSPEC_COND_FCVTNT, UNSPEC_COND_FCVTX, UNSPEC_COND_FCVTXNT)
17202 (UNSPEC_COND_FLOGB, UNSPEC_EORBT, UNSPEC_EORTB, UNSPEC_FADDP)
17203 (UNSPEC_FMAXP, UNSPEC_FMAXNMP, UNSPEC_FMLALB, UNSPEC_FMLALT)
17204 (UNSPEC_FMLSLB, UNSPEC_FMLSLT, UNSPEC_FMINP, UNSPEC_FMINNMP)
17205 (UNSPEC_HISTCNT, UNSPEC_HISTSEG, UNSPEC_MATCH, UNSPEC_NMATCH)
17206 (UNSPEC_PMULLB, UNSPEC_PMULLB_PAIR, UNSPEC_PMULLT, UNSPEC_PMULLT_PAIR)
17207 (UNSPEC_RADDHNB, UNSPEC_RADDHNT, UNSPEC_RSUBHNB, UNSPEC_RSUBHNT)
17208 (UNSPEC_SLI, UNSPEC_SRI, UNSPEC_SABDLB, UNSPEC_SABDLT, UNSPEC_SADDLB)
17209 (UNSPEC_SADDLBT, UNSPEC_SADDLT, UNSPEC_SADDWB, UNSPEC_SADDWT)
17210 (UNSPEC_SBCLB, UNSPEC_SBCLT, UNSPEC_SMAXP, UNSPEC_SMINP)
17211 (UNSPEC_SQCADD90, UNSPEC_SQCADD270, UNSPEC_SQDMULLB, UNSPEC_SQDMULLBT)
17212 (UNSPEC_SQDMULLT, UNSPEC_SQRDCMLAH, UNSPEC_SQRDCMLAH90)
17213 (UNSPEC_SQRDCMLAH180, UNSPEC_SQRDCMLAH270, UNSPEC_SQRSHRNB)
17214 (UNSPEC_SQRSHRNT, UNSPEC_SQRSHRUNB, UNSPEC_SQRSHRUNT, UNSPEC_SQSHRNB)
17215 (UNSPEC_SQSHRNT, UNSPEC_SQSHRUNB, UNSPEC_SQSHRUNT, UNSPEC_SQXTNB)
17216 (UNSPEC_SQXTNT, UNSPEC_SQXTUNB, UNSPEC_SQXTUNT, UNSPEC_SSHLLB)
17217 (UNSPEC_SSHLLT, UNSPEC_SSUBLB, UNSPEC_SSUBLBT, UNSPEC_SSUBLT)
17218 (UNSPEC_SSUBLTB, UNSPEC_SSUBWB, UNSPEC_SSUBWT, UNSPEC_SUBHNB)
17219 (UNSPEC_SUBHNT, UNSPEC_TBL2, UNSPEC_UABDLB, UNSPEC_UABDLT)
17220 (UNSPEC_UADDLB, UNSPEC_UADDLT, UNSPEC_UADDWB, UNSPEC_UADDWT)
17221 (UNSPEC_UMAXP, UNSPEC_UMINP, UNSPEC_UQRSHRNB, UNSPEC_UQRSHRNT)
17222 (UNSPEC_UQSHRNB, UNSPEC_UQSHRNT, UNSPEC_UQXTNB, UNSPEC_UQXTNT)
17223 (UNSPEC_USHLLB, UNSPEC_USHLLT, UNSPEC_USUBLB, UNSPEC_USUBLT)
17224 (UNSPEC_USUBWB, UNSPEC_USUBWT): New unspecs.
17225 (UNSPEC_SMULLB, UNSPEC_SMULLT, UNSPEC_UMULLB, UNSPEC_UMULLT)
17226 (UNSPEC_SMULHS, UNSPEC_SMULHRS, UNSPEC_UMULHS, UNSPEC_UMULHRS)
17227 (UNSPEC_RSHRNB, UNSPEC_RSHRNT, UNSPEC_SHRNB, UNSPEC_SHRNT): Move
17229 (VNARROW, Ventype): New mode attributes.
17230 (Vewtype): Handle VNx2DI. Fix typo in comment.
17231 (VDOUBLE): New mode attribute.
17232 (sve_lane_con): Handle VNx8HI.
17233 (SVE_INT_UNARY): Include ss_abs and ss_neg for TARGET_SVE2.
17234 (SVE_INT_BINARY): Likewise ss_plus, us_plus, ss_minus and us_minus.
17235 (sve_int_op, sve_int_op_rev): Handle the above codes.
17236 (sve_pred_int_rhs2_operand): Likewise.
17237 (MULLBT, SHRNB, SHRNT): Delete.
17238 (SVE_INT_SHIFT_IMM): New int iterator.
17239 (SVE_WHILE): Add UNSPEC_WHILEGE, UNSPEC_WHILEGT, UNSPEC_WHILEHI
17240 and UNSPEC_WHILEHS for TARGET_SVE2.
17241 (SVE2_U32_UNARY, SVE2_INT_UNARY_NARROWB, SVE2_INT_UNARY_NARROWT)
17242 (SVE2_INT_BINARY, SVE2_INT_BINARY_LANE, SVE2_INT_BINARY_LONG)
17243 (SVE2_INT_BINARY_LONG_LANE, SVE2_INT_BINARY_NARROWB)
17244 (SVE2_INT_BINARY_NARROWT, SVE2_INT_BINARY_PAIR, SVE2_FP_BINARY_PAIR)
17245 (SVE2_INT_BINARY_PAIR_LONG, SVE2_INT_BINARY_WIDE): New int iterators.
17246 (SVE2_INT_SHIFT_IMM_LONG, SVE2_INT_SHIFT_IMM_NARROWB): Likewise.
17247 (SVE2_INT_SHIFT_IMM_NARROWT, SVE2_INT_SHIFT_INSERT, SVE2_INT_CADD)
17248 (SVE2_INT_BITPERM, SVE2_INT_TERNARY, SVE2_INT_TERNARY_LANE): Likewise.
17249 (SVE2_FP_TERNARY_LONG, SVE2_FP_TERNARY_LONG_LANE, SVE2_INT_CMLA)
17250 (SVE2_INT_CDOT, SVE2_INT_ADD_BINARY_LONG, SVE2_INT_QADD_BINARY_LONG)
17251 (SVE2_INT_SUB_BINARY_LONG, SVE2_INT_QSUB_BINARY_LONG): Likewise.
17252 (SVE2_INT_ADD_BINARY_LONG_LANE, SVE2_INT_QADD_BINARY_LONG_LANE)
17253 (SVE2_INT_SUB_BINARY_LONG_LANE, SVE2_INT_QSUB_BINARY_LONG_LANE)
17254 (SVE2_COND_INT_UNARY_FP, SVE2_COND_FP_UNARY_LONG): Likewise.
17255 (SVE2_COND_FP_UNARY_NARROWB, SVE2_COND_INT_BINARY): Likewise.
17256 (SVE2_COND_INT_BINARY_NOREV, SVE2_COND_INT_BINARY_REV): Likewise.
17257 (SVE2_COND_INT_SHIFT, SVE2_MATCH, SVE2_PMULL): Likewise.
17258 (optab): Handle the new unspecs.
17259 (su, r): Remove entries for UNSPEC_SHRNB, UNSPEC_SHRNT, UNSPEC_RSHRNB
17261 (lr): Handle the new unspecs.
17263 (cmp_op, while_optab_cmp, sve_int_op): Handle the new unspecs.
17264 (sve_int_op_rev, sve_int_add_op, sve_int_qadd_op, sve_int_sub_op)
17265 (sve_int_qsub_op): New int attributes.
17266 (sve_fp_op, rot): Handle the new unspecs.
17267 * config/aarch64/aarch64-sve-builtins.h
17268 (function_resolver::require_matching_pointer_type): Declare.
17269 (function_resolver::resolve_unary): Add an optional boolean argument.
17270 (function_resolver::finish_opt_n_resolution): Add an optional
17271 type_suffix_index argument.
17272 (gimple_folder::redirect_call): Declare.
17273 (gimple_expander::prepare_gather_address_operands): Add an optional
17275 * config/aarch64/aarch64-sve-builtins.cc: Include
17276 aarch64-sve-builtins-sve2.h.
17277 (TYPES_b_unsigned, TYPES_b_integer, TYPES_bh_integer): New macros.
17278 (TYPES_bs_unsigned, TYPES_hs_signed, TYPES_hs_integer): Likewise.
17279 (TYPES_hd_unsigned, TYPES_hsd_signed): Likewise.
17280 (TYPES_hsd_integer): Use TYPES_hsd_signed.
17281 (TYPES_s_float_hsd_integer, TYPES_s_float_sd_integer): New macros.
17282 (TYPES_s_unsigned): Likewise.
17283 (TYPES_s_integer): Use TYPES_s_unsigned.
17284 (TYPES_sd_signed, TYPES_sd_unsigned): New macros.
17285 (TYPES_sd_integer): Use them.
17286 (TYPES_d_unsigned): New macro.
17287 (TYPES_d_integer): Use it.
17288 (TYPES_d_data, TYPES_cvt_long, TYPES_cvt_narrow_s): New macros.
17289 (TYPES_cvt_narrow): Likewise.
17290 (DEF_SVE_TYPES_ARRAY): Include the new types macros above.
17291 (preds_mx): New variable.
17292 (function_builder::add_overloaded_function): Allow the new feature
17293 set to be more restrictive than the original one.
17294 (function_resolver::infer_pointer_type): Remove qualifiers from
17295 the pointer type before printing it.
17296 (function_resolver::require_matching_pointer_type): New function.
17297 (function_resolver::resolve_sv_displacement): Handle functions
17298 that don't support 32-bit vector indices or svint32_t vector offsets.
17299 (function_resolver::finish_opt_n_resolution): Take the inferred type
17300 as a separate argument.
17301 (function_resolver::resolve_unary): Optionally treat all forms in
17302 the same way as normal merging functions.
17303 (gimple_folder::redirect_call): New function.
17304 (function_expander::prepare_gather_address_operands): Add an argument
17305 that says whether scaled forms are available. If they aren't,
17306 handle scaling of vector indices and don't add the extension and
17308 (function_expander::map_to_unspecs): If aarch64_sve isn't available,
17309 fall back to using cond_* instead.
17310 * config/aarch64/aarch64-sve-builtins-functions.h (rtx_code_function):
17311 Split out the member variables into...
17312 (rtx_code_function_base): ...this new base class.
17313 (rtx_code_function_rotated): Inherit rtx_code_function_base.
17314 (unspec_based_function): Split out the member variables into...
17315 (unspec_based_function_base): ...this new base class.
17316 (unspec_based_function_rotated): Inherit unspec_based_function_base.
17317 (unspec_based_function_exact_insn): New class.
17318 (unspec_based_add_function, unspec_based_add_lane_function)
17319 (unspec_based_lane_function, unspec_based_pred_function)
17320 (unspec_based_qadd_function, unspec_based_qadd_lane_function)
17321 (unspec_based_qsub_function, unspec_based_qsub_lane_function)
17322 (unspec_based_sub_function, unspec_based_sub_lane_function): New
17324 (unspec_based_fused_function): New class.
17325 (unspec_based_mla_function, unspec_based_mls_function): New typedefs.
17326 (unspec_based_fused_lane_function): New class.
17327 (unspec_based_mla_lane_function, unspec_based_mls_lane_function): New
17329 (CODE_FOR_MODE1): New macro.
17330 (fixed_insn_function): New class.
17331 (while_comparison): Likewise.
17332 * config/aarch64/aarch64-sve-builtins-shapes.h (binary_long_lane)
17333 (binary_long_opt_n, binary_narrowb_opt_n, binary_narrowt_opt_n)
17334 (binary_to_uint, binary_wide, binary_wide_opt_n, compare, compare_ptr)
17335 (load_ext_gather_index_restricted, load_ext_gather_offset_restricted)
17336 (load_gather_sv_restricted, shift_left_imm_long): Declare.
17337 (shift_left_imm_to_uint, shift_right_imm_narrowb): Likewise.
17338 (shift_right_imm_narrowt, shift_right_imm_narrowb_to_uint): Likewise.
17339 (shift_right_imm_narrowt_to_uint, store_scatter_index_restricted)
17340 (store_scatter_offset_restricted, tbl_tuple, ternary_long_lane)
17341 (ternary_long_opt_n, ternary_qq_lane_rotate, ternary_qq_rotate)
17342 (ternary_shift_left_imm, ternary_shift_right_imm, ternary_uint)
17343 (unary_convert_narrowt, unary_long, unary_narrowb, unary_narrowt)
17344 (unary_narrowb_to_uint, unary_narrowt_to_uint, unary_to_int): Likewise.
17345 * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
17346 Also add an initial argument for unary_convert_narrowt, regardless
17347 of the predication type.
17348 (build_32_64): Allow loads and stores to specify MODE_none.
17349 (build_sv_index64, build_sv_uint_offset): New functions.
17350 (long_type_suffix): New function.
17351 (binary_imm_narrowb_base, binary_imm_narrowt_base): New classes.
17352 (binary_imm_long_base, load_gather_sv_base): Likewise.
17353 (shift_right_imm_narrow_wrapper, ternary_shift_imm_base): Likewise.
17354 (ternary_resize2_opt_n_base, ternary_resize2_lane_base): Likewise.
17355 (unary_narrowb_base, unary_narrowt_base): Likewise.
17356 (binary_long_lane_def, binary_long_lane): New shape.
17357 (binary_long_opt_n_def, binary_long_opt_n): Likewise.
17358 (binary_narrowb_opt_n_def, binary_narrowb_opt_n): Likewise.
17359 (binary_narrowt_opt_n_def, binary_narrowt_opt_n): Likewise.
17360 (binary_to_uint_def, binary_to_uint): Likewise.
17361 (binary_wide_def, binary_wide): Likewise.
17362 (binary_wide_opt_n_def, binary_wide_opt_n): Likewise.
17363 (compare_def, compare): Likewise.
17364 (compare_ptr_def, compare_ptr): Likewise.
17365 (load_ext_gather_index_restricted_def,
17366 load_ext_gather_index_restricted): Likewise.
17367 (load_ext_gather_offset_restricted_def,
17368 load_ext_gather_offset_restricted): Likewise.
17369 (load_gather_sv_def): Inherit from load_gather_sv_base.
17370 (load_gather_sv_restricted_def, load_gather_sv_restricted): New shape.
17371 (shift_left_imm_def, shift_left_imm): Likewise.
17372 (shift_left_imm_long_def, shift_left_imm_long): Likewise.
17373 (shift_left_imm_to_uint_def, shift_left_imm_to_uint): Likewise.
17374 (store_scatter_index_restricted_def,
17375 store_scatter_index_restricted): Likewise.
17376 (store_scatter_offset_restricted_def,
17377 store_scatter_offset_restricted): Likewise.
17378 (tbl_tuple_def, tbl_tuple): Likewise.
17379 (ternary_long_lane_def, ternary_long_lane): Likewise.
17380 (ternary_long_opt_n_def, ternary_long_opt_n): Likewise.
17381 (ternary_qq_lane_def): Inherit from ternary_resize2_lane_base.
17382 (ternary_qq_lane_rotate_def, ternary_qq_lane_rotate): New shape
17383 (ternary_qq_opt_n_def): Inherit from ternary_resize2_opt_n_base.
17384 (ternary_qq_rotate_def, ternary_qq_rotate): New shape.
17385 (ternary_shift_left_imm_def, ternary_shift_left_imm): Likewise.
17386 (ternary_shift_right_imm_def, ternary_shift_right_imm): Likewise.
17387 (ternary_uint_def, ternary_uint): Likewise.
17388 (unary_convert): Fix typo in comment.
17389 (unary_convert_narrowt_def, unary_convert_narrowt): New shape.
17390 (unary_long_def, unary_long): Likewise.
17391 (unary_narrowb_def, unary_narrowb): Likewise.
17392 (unary_narrowt_def, unary_narrowt): Likewise.
17393 (unary_narrowb_to_uint_def, unary_narrowb_to_uint): Likewise.
17394 (unary_narrowt_to_uint_def, unary_narrowt_to_uint): Likewise.
17395 (unary_to_int_def, unary_to_int): Likewise.
17396 * config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla)
17397 (unspec_fcmla, unspec_cond_fcmla, expand_mla_mls_lane): New functions.
17398 (svasrd_impl): Delete.
17399 (svcadd_impl::expand): Handle integer operations too.
17400 (svcmla_impl::expand, svcmla_lane::expand): Likewise, using the
17401 new functions to derive the unspec numbers.
17402 (svmla_svmls_lane_impl): Replace with...
17403 (svmla_lane_impl, svmls_lane_impl): ...these new classes. Handle
17404 integer operations too.
17405 (svwhile_impl): Rename to...
17406 (svwhilelx_impl): ...this and inherit from while_comparison.
17407 (svasrd): Use unspec_based_function.
17408 (svmla_lane): Use svmla_lane_impl.
17409 (svmls_lane): Use svmls_lane_impl.
17410 (svrecpe, svrsqrte): Handle unsigned integer operations too.
17411 (svwhilele, svwhilelt): Use svwhilelx_impl.
17412 * config/aarch64/aarch64-sve-builtins-sve2.h: New file.
17413 * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
17414 * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
17415 * config/aarch64/aarch64-sve-builtins.def: Include
17416 aarch64-sve-builtins-sve2.def.
17418 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17420 * config/aarch64/aarch64-protos.h (aarch64_sve_arith_immediate_p)
17421 (aarch64_sve_sqadd_sqsub_immediate_p): Add a machine_mode argument.
17422 * config/aarch64/aarch64.c (aarch64_sve_arith_immediate_p)
17423 (aarch64_sve_sqadd_sqsub_immediate_p): Likewise. Handle scalar
17424 immediates as well as vector ones.
17425 * config/aarch64/predicates.md (aarch64_sve_arith_immediate)
17426 (aarch64_sve_sub_arith_immediate, aarch64_sve_qadd_immediate)
17427 (aarch64_sve_qsub_immediate): Update calls accordingly.
17429 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17431 * config/aarch64/aarch64-sve2.md: Add banner comments.
17432 (<su>mulh<r>s<mode>3): Move further up file.
17433 (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
17434 (*aarch64_sve2_sra<mode>): Move further down file.
17435 * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
17437 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17439 * config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
17440 and UNSPEC_WHILEWR.
17441 (while_optab_cmp): Handle them.
17442 * config/aarch64/aarch64-sve.md
17443 (*while_<while_optab_cmp><GPI:mode><PRED_ALL:mode>_ptest): Make public
17444 and add a "@" marker.
17445 * config/aarch64/aarch64-sve2.md (check_<raw_war>_ptrs<mode>): Use it
17446 instead of gen_aarch64_sve2_while_ptest.
17447 (@aarch64_sve2_while<cmp_op><GPI:mode><PRED_ALL:mode>_ptest): Delete.
17449 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17451 * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to...
17452 (UNSPEC_WHILELE): ...this.
17453 (UNSPEC_WHILE_LO): Rename to...
17454 (UNSPEC_WHILELO): ...this.
17455 (UNSPEC_WHILE_LS): Rename to...
17456 (UNSPEC_WHILELS): ...this.
17457 (UNSPEC_WHILE_LT): Rename to...
17458 (UNSPEC_WHILELT): ...this.
17459 * config/aarch64/iterators.md (SVE_WHILE): Update accordingly.
17460 (cmp_op, while_optab_cmp): Likewise.
17461 * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise.
17462 * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise.
17463 (svwhilelt): Likewise.
17465 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17467 * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete.
17468 (unary_to_uint): Define.
17469 * config/aarch64/aarch64-sve-builtins-shapes.cc (unary_count_def)
17470 (unary_count): Rename to...
17471 (unary_to_uint_def, unary_to_uint): ...this.
17472 * config/aarch64/aarch64-sve-builtins-base.def: Update accordingly.
17474 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17476 * config/aarch64/aarch64-sve-builtins-functions.h
17477 (code_for_mode_function): New class.
17478 (CODE_FOR_MODE0, QUIET_CODE_FOR_MODE0): New macros.
17479 * config/aarch64/aarch64-sve-builtins-base.cc (svcompact_impl)
17480 (svext_impl, svmul_lane_impl, svsplice_impl, svtmad_impl): Delete.
17481 (svcompact, svext, svsplice): Use QUIET_CODE_FOR_MODE0.
17482 (svmul_lane, svtmad): Use CODE_FOR_MODE0.
17484 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17486 * config/aarch64/iterators.md (addsub): New code attribute.
17487 * config/aarch64/aarch64-simd.md (aarch64_<su_optab><optab><mode>):
17489 (aarch64_<su_optab>q<addsub><mode>): ...this, making the same change
17490 in the asm string and attributes. Fix indentation.
17491 * config/aarch64/aarch64-sve.md (@aarch64_<su_optab><optab><mode>):
17493 (@aarch64_sve_<optab><mode>): ...this.
17494 * config/aarch64/aarch64-sve-builtins.h
17495 (function_expander::expand_signed_unpred_op): Delete.
17496 * config/aarch64/aarch64-sve-builtins.cc
17497 (function_expander::expand_signed_unpred_op): Likewise.
17498 (function_expander::map_to_rtx_codes): If the optab isn't defined,
17499 try using code_for_aarch64_sve instead.
17500 * config/aarch64/aarch64-sve-builtins-base.cc (svqadd_impl): Delete.
17501 (svqsub_impl): Likewise.
17502 (svqadd, svqsub): Use rtx_code_function instead.
17504 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17506 * config/aarch64/iterators.md (SRHSUB, URHSUB): Delete.
17507 (HADDSUB, sur, addsub): Remove them.
17509 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17511 * tree-nrv.c (pass_return_slot::execute): Handle all internal
17512 functions the same way, rather than singling out those that
17513 aren't mapped directly to optabs.
17515 2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
17517 * target.def (compatible_vector_types_p): New target hook.
17518 * hooks.h (hook_bool_const_tree_const_tree_true): Declare.
17519 * hooks.c (hook_bool_const_tree_const_tree_true): New function.
17520 * doc/tm.texi.in (TARGET_COMPATIBLE_VECTOR_TYPES_P): New hook.
17521 * doc/tm.texi: Regenerate.
17522 * gimple-expr.c: Include target.h.
17523 (useless_type_conversion_p): Use targetm.compatible_vector_types_p.
17524 * config/aarch64/aarch64.c (aarch64_compatible_vector_types_p): New
17526 (TARGET_COMPATIBLE_VECTOR_TYPES_P): Define.
17527 * config/aarch64/aarch64-sve-builtins.cc (gimple_folder::convert_pred):
17528 Use the original predicate if it already has a suitable type.
17530 2020-01-09 Martin Jambor <mjambor@suse.cz>
17532 * cgraph.h (cgraph_edge): Make remove, set_call_stmt, make_direct,
17533 resolve_speculation and redirect_call_stmt_to_callee static. Change
17534 return type of set_call_stmt to cgraph_edge *.
17535 * auto-profile.c (afdo_indirect_call): Adjust call to
17536 redirect_call_stmt_to_callee.
17537 * cgraph.c (cgraph_edge::set_call_stmt): Make return cgraph-edge *,
17538 make the this pointer explicit, adjust self-recursive calls and the
17539 call top make_direct. Return the resulting edge.
17540 (cgraph_edge::remove): Make this pointer explicit.
17541 (cgraph_edge::resolve_speculation): Likewise, adjust call to remove.
17542 (cgraph_edge::make_direct): Likewise, adjust call to
17543 resolve_speculation.
17544 (cgraph_edge::redirect_call_stmt_to_callee): Likewise, also adjust
17545 call to set_call_stmt.
17546 (cgraph_update_edges_for_call_stmt_node): Update call to
17547 set_call_stmt and remove.
17548 * cgraphclones.c (cgraph_node::set_call_stmt_including_clones):
17549 Renamed edge to master_edge. Adjusted calls to set_call_stmt.
17550 (cgraph_node::create_edge_including_clones): Moved "first" definition
17551 of edge to the block where it was used. Adjusted calls to
17553 (cgraph_node::remove_symbol_and_inline_clones): Adjust call to
17554 cgraph_edge::remove.
17555 * cgraphunit.c (walk_polymorphic_call_targets): Adjusted calls to
17556 make_direct and redirect_call_stmt_to_callee.
17557 * ipa-fnsummary.c (redirect_to_unreachable): Adjust calls to
17558 resolve_speculation and make_direct.
17559 * ipa-inline-transform.c (inline_transform): Adjust call to
17560 redirect_call_stmt_to_callee.
17561 (check_speculations_1):: Adjust call to resolve_speculation.
17562 * ipa-inline.c (resolve_noninline_speculation): Adjust call to
17563 resolve-speculation.
17564 (inline_small_functions): Adjust call to resolve_speculation.
17565 (ipa_inline): Likewise.
17566 * ipa-prop.c (ipa_make_edge_direct_to_target): Adjust call to
17568 * ipa-visibility.c (function_and_variable_visibility): Make iteration
17569 safe with regards to edge removal, adjust calls to
17570 redirect_call_stmt_to_callee.
17571 * ipa.c (walk_polymorphic_call_targets): Adjust calls to make_direct
17572 and redirect_call_stmt_to_callee.
17573 * multiple_target.c (create_dispatcher_calls): Adjust call to
17574 redirect_call_stmt_to_callee
17575 (redirect_to_specific_clone): Likewise.
17576 * tree-cfgcleanup.c (delete_unreachable_blocks_update_callgraph):
17577 Adjust calls to cgraph_edge::remove.
17578 * tree-inline.c (copy_bb): Adjust call to set_call_stmt.
17579 (redirect_all_calls): Adjust call to redirect_call_stmt_to_callee.
17580 (expand_call_inline): Adjust call to cgraph_edge::remove.
17582 2020-01-09 Martin Liska <mliska@suse.cz>
17584 * params.opt: Set Optimization for
17585 param_max_speculative_devirt_maydefs.
17587 2020-01-09 Martin Sebor <msebor@redhat.com>
17589 PR middle-end/93200
17591 * builtins.c (compute_objsize): Avoid handling MEM_REFs of vector type.
17593 2020-01-09 Martin Liska <mliska@suse.cz>
17595 * auto-profile.c (auto_profile): Use opt_for_fn
17597 * ipa-cp.c (ipcp_lattice::add_value): Likewise.
17598 (propagate_vals_across_arith_jfunc): Likewise.
17599 (hint_time_bonus): Likewise.
17600 (incorporate_penalties): Likewise.
17601 (good_cloning_opportunity_p): Likewise.
17602 (perform_estimation_of_a_value): Likewise.
17603 (estimate_local_effects): Likewise.
17604 (ipcp_propagate_stage): Likewise.
17605 * ipa-fnsummary.c (decompose_param_expr): Likewise.
17606 (set_switch_stmt_execution_predicate): Likewise.
17607 (analyze_function_body): Likewise.
17608 * ipa-inline-analysis.c (offline_size): Likewise.
17609 * ipa-inline.c (early_inliner): Likewise.
17610 * ipa-prop.c (ipa_analyze_node): Likewise.
17611 (ipcp_transform_function): Likewise.
17612 * ipa-sra.c (process_scan_results): Likewise.
17613 (ipa_sra_summarize_function): Likewise.
17614 * params.opt: Rename ipcp-unit-growth to
17615 ipa-cp-unit-growth. Add Optimization for various
17616 IPA-related parameters.
17618 2020-01-09 Richard Biener <rguenther@suse.de>
17620 PR middle-end/93054
17621 * gimplify.c (gimplify_expr): Deal with NOP definitions.
17623 2020-01-09 Richard Biener <rguenther@suse.de>
17625 PR tree-optimization/93040
17626 * gimple-ssa-store-merging.c (find_bswap_or_nop): Raise search limit.
17628 2020-01-09 Georg-Johann Lay <avr@gjlay.de>
17630 * common/config/avr/avr-common.c (avr_option_optimization_table)
17631 [OPT_LEVELS_1_PLUS]: Set -fsplit-wide-types-early.
17633 2020-01-09 Martin Liska <mliska@suse.cz>
17635 * cgraphclones.c (symbol_table::materialize_all_clones):
17636 Use cgraph_node::dump_name.
17638 2020-01-09 Jakub Jelinek <jakub@redhat.com>
17640 PR inline-asm/93202
17641 * config/riscv/riscv.c (riscv_print_operand_reloc): Use
17642 output_operand_lossage instead of gcc_unreachable.
17643 * doc/md.texi (riscv f constraint): Fix typo.
17646 * config/i386/i386.md (subv<mode>4): Use SWIDWI iterator instead of
17647 SWI. Use <general_hilo_operand> instead of <general_operand>. Use
17648 CONST_SCALAR_INT_P instead of CONST_INT_P.
17649 (*subv<mode>4_1): Rename to ...
17650 (subv<mode>4_1): ... this.
17651 (*subv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
17652 define_insn_and_split patterns.
17653 (*subv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
17656 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17658 * vec.c (class selftest::count_dtor): New class.
17659 (selftest::test_auto_delete_vec): New test.
17660 (selftest::vec_c_tests): Call it.
17661 * vec.h (class auto_delete_vec): New class template.
17662 (auto_delete_vec<T>::~auto_delete_vec): New dtor.
17664 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17666 * sbitmap.h (auto_sbitmap): Add operator const_sbitmap.
17668 2020-01-08 Jim Wilson <jimw@sifive.com>
17670 * config/riscv/riscv.c (riscv_legitimize_tls_address): Ifdef out
17671 use of TLS_MODEL_LOCAL_EXEC when not pic.
17673 2020-01-08 David Malcolm <dmalcolm@redhat.com>
17675 * hash-map-tests.c (selftest::test_map_of_strings_to_int): Fix
17678 2020-01-08 Jakub Jelinek <jakub@redhat.com>
17681 * config/i386/i386.md (*stack_protect_set_2_<mode> peephole2,
17682 *stack_protect_set_3 peephole2): Also check that the second
17683 insns source is general_operand.
17686 * config/i386/i386.md (addcarry<mode>_0): Use nonimmediate_operand
17687 predicate for output operand instead of register_operand.
17688 (addcarry<mode>, addcarry<mode>_1): Likewise. Add alternative with
17689 memory destination and non-memory operands[2].
17691 2020-01-08 Martin Liska <mliska@suse.cz>
17693 * cgraph.c (cgraph_node::dump): Use ::dump_name or
17694 ::dump_asm_name instead of (::name or ::asm_name).
17695 * cgraphclones.c (symbol_table::materialize_all_clones): Likewise.
17696 * cgraphunit.c (walk_polymorphic_call_targets): Likewise.
17697 (analyze_functions): Likewise.
17698 (expand_all_functions): Likewise.
17699 * ipa-cp.c (ipcp_cloning_candidate_p): Likewise.
17700 (propagate_bits_across_jump_function): Likewise.
17701 (dump_profile_updates): Likewise.
17702 (ipcp_store_bits_results): Likewise.
17703 (ipcp_store_vr_results): Likewise.
17704 * ipa-devirt.c (dump_targets): Likewise.
17705 * ipa-fnsummary.c (analyze_function_body): Likewise.
17706 * ipa-hsa.c (check_warn_node_versionable): Likewise.
17707 (process_hsa_functions): Likewise.
17708 * ipa-icf.c (sem_item_optimizer::merge_classes): Likewise.
17709 (set_alias_uids): Likewise.
17710 * ipa-inline-transform.c (save_inline_function_body): Likewise.
17711 * ipa-inline.c (recursive_inlining): Likewise.
17712 (inline_to_all_callers_1): Likewise.
17713 (ipa_inline): Likewise.
17714 * ipa-profile.c (ipa_propagate_frequency_1): Likewise.
17715 (ipa_propagate_frequency): Likewise.
17716 * ipa-prop.c (ipa_make_edge_direct_to_target): Likewise.
17717 (remove_described_reference): Likewise.
17718 * ipa-pure-const.c (worse_state): Likewise.
17719 (check_retval_uses): Likewise.
17720 (analyze_function): Likewise.
17721 (propagate_pure_const): Likewise.
17722 (propagate_nothrow): Likewise.
17723 (dump_malloc_lattice): Likewise.
17724 (propagate_malloc): Likewise.
17725 (pass_local_pure_const::execute): Likewise.
17726 * ipa-visibility.c (optimize_weakref): Likewise.
17727 (function_and_variable_visibility): Likewise.
17728 * ipa.c (symbol_table::remove_unreachable_nodes): Likewise.
17729 (ipa_discover_variable_flags): Likewise.
17730 * lto-streamer-out.c (output_function): Likewise.
17731 (output_constructor): Likewise.
17732 * tree-inline.c (copy_bb): Likewise.
17733 * tree-ssa-structalias.c (ipa_pta_execute): Likewise.
17734 * varpool.c (symbol_table::remove_unreferenced_decls): Likewise.
17736 2020-01-08 Richard Biener <rguenther@suse.de>
17738 PR middle-end/93199
17739 * tree-eh.c (sink_clobbers): Update virtual operands for
17740 the first and last stmt only. Add a dry-run capability.
17741 (pass_lower_eh_dispatch::execute): Perform clobber sinking
17742 after CFG manipulations and in RPO order to catch all
17743 secondary opportunities reliably.
17745 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17748 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17750 2019-01-08 Richard Biener <rguenther@suse.de>
17752 PR middle-end/93199
17753 * gimple-fold.c (rewrite_to_defined_overflow): Mark stmt modified.
17754 * tree-ssa-loop-im.c (move_computations_worker): Properly adjust
17755 virtual operand, also updating SSA use.
17756 * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction):
17757 Update stmt after resetting virtual operand.
17758 (tree_loop_interchange::move_code_to_inner_loop): Likewise.
17759 * gimple-iterator.c (gsi_remove): When not removing the stmt
17760 permanently do not delink immediate uses or mark the stmt modified.
17762 2020-01-08 Martin Liska <mliska@suse.cz>
17764 * ipa-fnsummary.c (dump_ipa_call_summary): Use symtab_node::dump_name.
17765 (ipa_call_context::estimate_size_and_time): Likewise.
17766 (inline_analyze_function): Likewise.
17768 2020-01-08 Martin Liska <mliska@suse.cz>
17770 * cgraph.c (cgraph_node::dump): Use systematically
17773 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17775 Add -nodevicespecs option for avr.
17778 * config/avr/avr.opt (-nodevicespecs): New driver option.
17779 * config/avr/driver-avr.c (avr_devicespecs_file): Only issue
17780 "-specs=device-specs/..." if that option is not set.
17781 * doc/invoke.texi (AVR Options) <-nodevicespecs>: Document.
17783 2020-01-08 Georg-Johann Lay <avr@gjlay.de>
17785 Implement 64-bit double functions for avr.
17788 * config.gcc (tm_defines) [target=avr]: Support --with-libf7,
17789 --with-double-comparison.
17790 * doc/install.texi: Document them.
17791 * config/avr/avr-c.c (avr_cpu_cpp_builtins)
17792 <WITH_LIBF7_LIBGCC, WITH_LIBF7_MATH, WITH_LIBF7_MATH_SYMBOLS>
17793 <WITH_DOUBLE_COMPARISON>: New built-in defines.
17794 * doc/invoke.texi (AVR Built-in Macros): Document them.
17795 * config/avr/avr-protos.h (avr_float_lib_compare_returns_bool): New.
17796 * config/avr/avr.c (avr_float_lib_compare_returns_bool): New function.
17797 * config/avr/avr.h (FLOAT_LIB_COMPARE_RETURNS_BOOL): New macro.
17799 2020-01-08 Richard Earnshaw <rearnsha@arm.com>
17802 * config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
17803 armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
17804 when only building rm-profile multilibs.
17806 2020-01-08 Feng Xue <fxue@os.amperecomputing.com>
17809 * ipa-cp.c (self_recursively_generated_p): Find matched aggregate
17810 lattice for a value to check.
17811 (propagate_vals_across_arith_jfunc): Add an assertion to ensure
17812 finite propagation in self-recursive scc.
17814 2020-01-08 Luo Xiong Hu <luoxhu@linux.ibm.com>
17816 * ipa-inline.c (caller_growth_limits): Restore the AND.
17818 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17820 * config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
17821 (VEC_ALLREG_ALT): New iterator.
17822 (VEC_ALLREG_INT_MODE): New iterator.
17823 (VCMP_MODE): New iterator.
17824 (VCMP_MODE_INT): New iterator.
17825 (vec_cmpu<mode>di): Use VCMP_MODE_INT.
17826 (vec_cmp<u>v64qidi): New define_expand.
17827 (vec_cmp<mode>di_exec): Use VCMP_MODE.
17828 (vec_cmpu<mode>di_exec): New define_expand.
17829 (vec_cmp<u>v64qidi_exec): New define_expand.
17830 (vec_cmp<mode>di_dup): Use VCMP_MODE.
17831 (vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
17832 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
17833 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
17834 (vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
17835 (vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
17836 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
17837 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
17838 (vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
17839 (vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
17841 * config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
17842 * config/gcn/gcn.md (expander): Add sign_extend and zero_extend.
17844 2020-01-07 Andrew Stubbs <ams@codesourcery.com>
17846 * config/gcn/constraints.md (DA): Update description and match.
17848 (Db): New constraint.
17849 * config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
17851 * config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
17852 Implement 'Db' mixed immediate type.
17853 * config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
17854 (addcv64si3_dup<exec_vcc>): Delete.
17855 (subcv64si3<exec_vcc>): Rework constraints.
17856 (addv64di3): Rework constraints.
17857 (addv64di3_exec): Rework constraints.
17858 (subv64di3): Rework constraints.
17859 (addv64di3_dup): Delete.
17860 (addv64di3_dup_exec): Delete.
17861 (addv64di3_zext): Rework constraints.
17862 (addv64di3_zext_exec): Rework constraints.
17863 (addv64di3_zext_dup): Rework constraints.
17864 (addv64di3_zext_dup_exec): Rework constraints.
17865 (addv64di3_zext_dup2): Rework constraints.
17866 (addv64di3_zext_dup2_exec): Rework constraints.
17867 (addv64di3_sext_dup2): Rework constraints.
17868 (addv64di3_sext_dup2_exec): Rework constraints.
17870 2020-01-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
17872 * doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
17873 existing target checks.
17875 2020-01-07 Richard Biener <rguenther@suse.de>
17877 * doc/install.texi: Bump minimal supported MPC version.
17879 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17881 * langhooks-def.h (lhd_simulate_enum_decl): Declare.
17882 (LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
17883 * langhooks.c: Include stor-layout.h.
17884 (lhd_simulate_enum_decl): New function.
17885 * config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
17886 handle_arm_sve_h for the LTO frontend.
17887 (register_vector_type): Cope with null returns from pushdecl.
17889 2020-01-07 Richard Sandiford <richard.sandiford@arm.com>
17891 * config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
17892 (aarch64_sve::nvectors_if_data_type): Replace with...
17893 (aarch64_sve::builtin_type_p): ...this.
17894 * config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
17895 (find_vector_type): Delete.
17896 (add_sve_type_attribute): New function.
17897 (lookup_sve_type_attribute): Likewise.
17898 (register_builtin_types): Add an "SVE type" attribute to each type.
17899 (register_tuple_type): Likewise.
17900 (svbool_type_p, nvectors_if_data_type): Delete.
17901 (mangle_builtin_type): Use lookup_sve_type_attribute.
17902 (builtin_type_p): Likewise. Add an overload that returns the
17903 number of constituent vector and predicate registers.
17904 * config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
17905 (aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
17906 instead of aarch64_sve_argument_p.
17907 (aarch64_takes_arguments_in_sve_regs_p): Likewise.
17908 (aarch64_pass_by_reference): Likewise.
17909 (aarch64_function_value_1): Likewise.
17910 (aarch64_return_in_memory): Likewise.
17911 (aarch64_layout_arg): Likewise.
17913 2020-01-07 Jakub Jelinek <jakub@redhat.com>
17915 PR tree-optimization/93156
17916 * tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
17917 least significant bit is always clear.
17919 PR tree-optimization/93118
17920 * match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?. Add new
17921 simplifier with two intermediate conversions.
17923 2020-01-07 Martin Liska <mliska@suse.cz>
17925 * params.opt: Add Optimization for various parameters.
17927 2020-01-07 Martin Liska <mliska@suse.cz>
17930 * doc/extend.texi: Explain cloning for target_clone
17933 2020-01-07 Martin Liska <mliska@suse.cz>
17935 PR tree-optimization/92860
17936 * common.opt: Make in Optimization option
17937 as it is affected by -O0, which is an Optimization
17939 * tree-inline.c (tree_inlinable_function_p):
17940 Use opt_for_fn for warn_inline.
17941 (expand_call_inline): Likewise.
17943 2020-01-07 Martin Liska <mliska@suse.cz>
17945 PR tree-optimization/92860
17946 * common.opt: Make flag_ree as optimization
17949 2020-01-07 Martin Liska <mliska@suse.cz>
17951 PR optimization/92860
17952 * params.opt: Mark param_min_crossjump_insns with Optimization
17955 2020-01-07 Luo Xiong Hu <luoxhu@linux.ibm.com>
17957 * ipa-inline-analysis.c (estimate_growth): Fix typo.
17958 * ipa-inline.c (caller_growth_limits): Use OR instead of AND.
17960 2020-01-06 Michael Meissner <meissner@linux.ibm.com>
17962 * config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
17963 helper function to return the valid addressing formats for a given
17964 hard register and mode.
17965 (rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.
17967 * config/rs6000/constraints.md (Q constraint): Update
17969 * doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
17972 * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
17973 Use 'Q' for doing vector extract from memory.
17974 (vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
17976 (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
17977 doing vector extract from memory.
17978 (vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
17979 extract from memory.
17981 * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
17982 for the offset being 34-bits when -mcpu=future is used.
17984 2020-01-06 John David Anglin <danglin@gcc.gnu.org>
17986 * config/pa/pa.md: Revert change to use ordered_comparison_operator
17987 instead of cmpib_comparison_operator in cmpib patterns.
17988 * config/pa/predicates.md (cmpib_comparison_operator): Revert removal
17989 of cmpib_comparison_operator. Revise comment.
17991 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17993 * tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
17994 in an IFN_DIV_POW2 node to be equal.
17996 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
17998 * tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
17999 (vect_check_scalar_mask): ...this.
18000 (vectorizable_store, vectorizable_load): Update call accordingly.
18001 (vectorizable_call): Use vect_check_scalar_mask to check the mask
18002 argument in calls to conditional internal functions.
18004 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
18006 * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
18007 '0' matching inputs.
18008 (subv64di3_exec): Likewise.
18010 2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
18012 * config/mips/mips.c (vr4130_align_insns): Fix typo.
18013 * doc/md.texi (movstr): Likewise.
18015 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
18017 * config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
18020 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
18022 * config/aarch64/t-aarch64 ($(srcdir)/config/aarch64/aarch64-tune.md):
18024 (s-aarch64-tune-md): ...this new stamp file. Pipe the new contents
18025 to a temporary file and use move-if-change to update the real
18026 file where necessary.
18028 2020-01-06 Richard Sandiford <richard.sandiford@arm.com>
18030 * config/aarch64/aarch64-sve.md (@aarch64_sel_dup<mode>): Use Upl
18031 rather than Upa for CPY /M.
18033 2020-01-06 Andrew Stubbs <ams@codesourcery.com>
18035 * config/gcn/gcn.c (gcn_inline_constant_p): Allow 64 as an inline
18038 2020-01-06 Martin Liska <mliska@suse.cz>
18040 PR tree-optimization/92860
18041 * params.opt: Mark param_max_combine_insns with Optimization
18044 2020-01-05 Jakub Jelinek <jakub@redhat.com>
18047 * config/i386/i386.md (SWIDWI): New mode iterator.
18048 (DWI, dwi): Add TImode variants.
18049 (addv<mode>4): Use SWIDWI iterator instead of SWI. Use
18050 <general_hilo_operand> instead of <general_operand>. Use
18051 CONST_SCALAR_INT_P instead of CONST_INT_P.
18052 (*addv<mode>4_1): Rename to ...
18053 (addv<mode>4_1): ... this.
18054 (QWI): New mode attribute.
18055 (*addv<dwi>4_doubleword, *addv<dwi>4_doubleword_1): New
18056 define_insn_and_split patterns.
18057 (*addv<mode>4_overflow_1, *addv<mode>4_overflow_2): New define_insn
18059 (uaddv<mode>4): Use SWIDWI iterator instead of SWI. Use
18060 <general_hilo_operand> instead of <general_operand>.
18061 (*addcarry<mode>_1): New define_insn.
18062 (*add<dwi>3_doubleword_cc_overflow_1): New define_insn_and_split.
18064 2020-01-03 Konstantin Kharlamov <Hi-Angel@yandex.ru>
18066 * gdbinit.in (pr, prl, pt, pct, pgg, pgq, pgs, pge, pmz, pdd, pbs, pbm):
18067 Use "call" instead of "set".
18069 2020-01-03 Martin Jambor <mjambor@suse.cz>
18072 * ipa-cp.c (print_all_lattices): Skip functions without info.
18074 2020-01-03 Jakub Jelinek <jakub@redhat.com>
18077 * config/i386/i386-options.c (ix86_simd_clone_adjust): If
18078 TARGET_PREFER_AVX128, use prefer-vector-width=256 for 'c' and 'd'
18079 simd clones. If TARGET_PREFER_AVX256, use prefer-vector-width=512
18080 for 'e' simd clones.
18083 * config/i386/i386.opt (x_prefer_vector_width_type): Remove TargetSave
18085 (mprefer-vector-width=): Add Save.
18086 * config/i386/i386-options.c (ix86_target_string): Add PVW argument, print
18087 -mprefer-vector-width= if non-zero. Fix up -mfpmath= comment.
18088 (ix86_debug_options, ix86_function_specific_print): Adjust
18089 ix86_target_string callers.
18090 (ix86_valid_target_attribute_inner_p): Handle prefer-vector-width=.
18091 (ix86_valid_target_attribute_tree): Likewise.
18092 * config/i386/i386-options.h (ix86_target_string): Add PVW argument.
18093 * config/i386/i386-expand.c (ix86_expand_builtin): Adjust
18094 ix86_target_string caller.
18097 * config/i386/i386.md (abs<mode>2): Use expand_simple_binop instead of
18098 emitting ASHIFTRT, XOR and MINUS by hand. Use gen_int_mode with QImode
18099 instead of gen_int_shift_amount + convert_modes.
18101 PR rtl-optimization/93088
18102 * loop-iv.c (find_single_def_src): Punt after looking through
18103 128 reg copies for regs with single definitions. Move definitions
18106 2020-01-02 Dennis Zhang <dennis.zhang@arm.com>
18108 * config/arm/arm-c.c (arm_cpu_builtins): Define
18109 __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC,
18110 __ARM_FEATURE_BF16_SCALAR_ARITHMETIC, and
18111 __ARM_BF16_FORMAT_ALTERNATIVE when enabled.
18112 * config/arm/arm-cpus.in (armv8_6, i8mm, bf16): New features.
18113 * config/arm/arm-tables.opt: Regenerated.
18114 * config/arm/arm.c (arm_option_reconfigure_globals): Initialize
18115 arm_arch_i8mm and arm_arch_bf16 when enabled.
18116 * config/arm/arm.h (TARGET_I8MM): New macro.
18117 (TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
18118 * config/arm/t-aprofile: Add matching rules for -march=armv8.6-a.
18119 * config/arm/t-arm-elf (all_v8_archs): Add armv8.6-a.
18120 * config/arm/t-multilib: Add matching rules for -march=armv8.6-a.
18121 (v8_6_a_simd_variants): New.
18122 (v8_*_a_simd_variants): Add i8mm and bf16.
18123 * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options.
18125 2020-01-02 Jakub Jelinek <jakub@redhat.com>
18128 * predict.c (compute_function_frequency): Don't call
18129 warn_function_cold on functions that already have cold attribute.
18131 2020-01-01 John David Anglin <danglin@gcc.gnu.org>
18134 * config/pa/pa.c (pa_elf_select_rtx_section): New. Put references to
18135 COMDAT group function labels in .data.rel.ro.local section.
18136 * config/pa/pa32-linux.h (TARGET_ASM_SELECT_RTX_SECTION): Define.
18139 * config/pa/pa.md (scc): Use ordered_comparison_operator instead of
18140 comparison_operator in B and S integer comparisons. Likewise, use
18141 ordered_comparison_operator instead of cmpib_comparison_operator in
18143 * config/pa/predicates.md (cmpib_comparison_operator): Remove.
18145 2020-01-01 Jakub Jelinek <jakub@redhat.com>
18147 Update copyright years.
18149 * gcc.c (process_command): Update copyright notice dates.
18150 * gcov-dump.c (print_version): Ditto.
18151 * gcov.c (print_version): Ditto.
18152 * gcov-tool.c (print_version): Ditto.
18153 * gengtype.c (create_file): Ditto.
18154 * doc/cpp.texi: Bump @copying's copyright year.
18155 * doc/cppinternals.texi: Ditto.
18156 * doc/gcc.texi: Ditto.
18157 * doc/gccint.texi: Ditto.
18158 * doc/gcov.texi: Ditto.
18159 * doc/install.texi: Ditto.
18160 * doc/invoke.texi: Ditto.
18162 2020-01-01 Jan Hubicka <hubicka@ucw.cz>
18164 * ipa.c (walk_polymorphic_call_targets): Fix updating of overall
18167 2020-01-01 Jakub Jelinek <jakub@redhat.com>
18169 PR tree-optimization/93098
18170 * match.pd (popcount): For shift amounts, use integer_onep
18171 or wi::to_widest () == cst instead of tree_to_uhwi () == cst
18172 tests. Make sure that precision is power of two larger than or equal
18173 to 16. Ensure shift is never negative. Use HOST_WIDE_INT_UC macro
18174 instead of ULL suffixed constants. Formatting fixes.
18176 Copyright (C) 2020 Free Software Foundation, Inc.
18178 Copying and distribution of this file, with or without modification,
18179 are permitted in any medium without royalty provided the copyright
18180 notice and this notice are preserved.