Daily bump.

[thirdparty/gcc.git] / gcc / ChangeLog

2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>

        * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
        Add missing ":SI" to the match_operator.

2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>

        * config/xtensa/xtensa.md (SHI): New mode iterator.
        (2 split patterns related to constsynth):
        Change to also accept HImode operands.

2024-02-04  Jeff Law  <jlaw@ventanamicro.com>

        * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
        similarly.

2024-02-04  Xi Ruoyao  <xry111@xry111.site>

        * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
        incorrect expand.
        * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
        (elmsgnbit): Likewise.
        (neg<mode:FVEC>2): New define_insn.
        * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
        are now instantiated in simd.md.

2024-02-04  Xi Ruoyao  <xry111@xry111.site>

        * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
        use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
        MAX_MACHINE_MODE.

2024-02-04  Li Wei  <liwei@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
        (loongarch_expand_vselect_vconcat): Ditto.
        (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
        all 128-bit constant permutation situations.
        (loongarch_expand_lsx_shuffle): Adjust and rename function name.
        (loongarch_is_imm_set_shuffle): Renamed function name.
        (loongarch_expand_vec_perm_even_odd): Function forward declaration.
        (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
        extract-even and extract-odd permutations.
        (loongarch_is_odd_extraction): Delete.
        (loongarch_is_even_extraction): Ditto.
        (loongarch_expand_vec_perm_const): Adjust.

2024-02-03  Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/113722
        * wide-int.cc (wi::bswap_large): Rename third argument from
        len to xlen and adjust use in safe_uhwi.  Add len variable, set
        it to BLOCKS_NEEDED (precision) and use it for clearing of val
        and as canonize argument.  Clear val using memset instead of
        a loop.

2024-02-03  Jakub Jelinek  <jakub@redhat.com>

        * ggc-common.cc (gt_pch_save): Allow addr to be equal to
        mmi.preferred_base + mmi.size - sizeof (void *).

2024-02-03  Xi Ruoyao  <xry111@xry111.site>

        * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
        * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
        the ODR-violating locale declaration.

2024-02-02  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113588
        PR tree-optimization/113467
        * tree-vect-data-refs.cc
        (vect_analyze_data_ref_dependence):  Choose correct dest and fix checks.
        (vect_analyze_early_break_dependences): Update comments.

2024-02-02  John David Anglin  <danglin@gcc.gnu.org>

        PR target/59778
        * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
        and PA_BUILTIN_SET_FPSR builtins.
        * (pa_builtins_icode): Declare.
        * (def_builtin, pa_fpu_init_builtins): New.
        * (pa_init_builtins): Initialize FPU builtins.
        * (pa_builtin_decl, pa_expand_builtin_1): New.
        * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
        PA_BUILTIN_SET_FPSR builtins.
        * (pa_atomic_assign_expand_fenv): New.
        * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
        UNSPECV constants.
        (get_fpsr, put_fpsr): New expanders.
        (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
        insn patterns.

2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113697
        * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.

2024-02-02  Jonathan Wakely  <jwakely@redhat.com>

        * doc/extend.texi (Common Type Attributes): Fix typo in
        description of hardbool.

2024-02-02  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113692
        * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
        from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
        final_cast_p.

2024-02-02  Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/113699
        * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
        uninitialized large/huge _BitInt SSA_NAME inputs.

2024-02-02  Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/113705
        * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
        around wi::to_wide in order to compare value in prec precision.

2024-02-02  Lehua Ding  <lehua.ding@rivai.ai>

        Revert:
        2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.

2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.

2024-02-02  Pan Li  <pan2.li@intel.com>

        * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
        (riscv_pass_by_reference): Ditto.
        (riscv_fntype_abi): Ditto.

2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
        (pre_vsetvl::cleaup): Remove vsetvl_pre.
        (pre_vsetvl::remove_vsetvl_pre_insns): New function.

2024-02-02  Jiahao Xu  <xujiahao@loongson.cn>

        * config/loongarch/larchintrin.h
        (__frecipe_s): Update function return type.
        (__frecipe_d): Ditto.
        (__frsqrte_s): Ditto.
        (__frsqrte_d): Ditto.

2024-02-02  Li Wei  <liwei@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
        (loongarch_vector_costs::add_stmt_cost): Adjust.

2024-02-02  Xi Ruoyao  <xry111@xry111.site>

        * config/loongarch/loongarch.md (unspec): Add
        UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
        (la_pcrel64_two_parts): New define_insn.
        * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
        typo in the comment.
        (loongarch_call_tls_get_addr): If -mcmodel=extreme
        -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
        addressing the TLS symbol and __tls_get_addr.  Emit an REG_EQUAL
        note to allow CSE addressing __tls_get_addr.
        (loongarch_legitimize_tls_address): If -mcmodel=extreme
        -mexplicit-relocs={always,auto}, address TLS IE symbols with
        la_pcrel64_two_parts.
        (loongarch_split_symbol): If -mcmodel=extreme
        -mexplicit-relocs={always,auto}, address symbols with
        la_pcrel64_two_parts.
        (loongarch_output_mi_thunk): Clean up unreachable code.  If
        -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
        thunks with la_pcrel64_two_parts.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
        Add support for call36.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
        When the code model of the symbol is extreme and -mexplicit-relocs=auto,
        the macro instruction loading symbol address is not applicable.
        (loongarch_call_tls_get_addr): Adjust code.
        (loongarch_legitimize_tls_address): Likewise.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

        * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
        Add function declaration.
        * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
        For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
        is not allowed
        (loongarch_load_tls): Added macro support in extreme mode.
        (loongarch_call_tls_get_addr): Likewise.
        (loongarch_legitimize_tls_address): Likewise.
        (loongarch_force_address): Likewise.
        (loongarch_legitimize_move): Likewise.
        (loongarch_output_mi_thunk): Likewise.
        (loongarch_option_override_internal): Remove the code that detects
        explicit relocs status.
        (loongarch_handle_model_attribute): Likewise.
        * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
        * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
        (symbolic_off64_or_reg_operand): Likewise.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_load_tls):
        Load all types of tls symbols through one function.
        (loongarch_got_load_tls_gd): Delete.
        (loongarch_got_load_tls_ld): Delete.
        (loongarch_got_load_tls_ie): Delete.
        (loongarch_got_load_tls_le): Delete.
        (loongarch_call_tls_get_addr): Modify the called function name.
        (loongarch_legitimize_tls_address): Likewise.
        * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
        (@load_tls<mode>): New template.
        (@got_load_tls_ld<mode>): Delete.
        (@got_load_tls_le<mode>): Delete.
        (@got_load_tls_ie<mode>): Delete.

2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>

        * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
        (loongarch_legitimize_address): Add logical transformation code.

2024-02-01  Marek Polacek  <polacek@redhat.com>

        * doc/invoke.texi: Update -Wdangling-reference documentation.

2024-02-01  Uros Bizjak  <ubizjak@gmail.com>

        PR target/113701
        * config/i386/i386.md (*cmp<dwi>_doubleword):
        Do not force SUBREG pieces to pseudos.

2024-02-01  John David Anglin  <danglin@gcc.gnu.org>

        * config/pa/pa.md (atomic_storedi_1): Fix bug in
        alternative 1.

2024-02-01  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/avr.cc: Tabify.

2024-02-01  Richard Ball  <richard.ball@arm.com>

        PR tree-optimization/111268
        * tree-vect-slp.cc (vectorizable_slp_permutation_1):
        Add variable-length check for vector input arguments
        to a function.

2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>

        * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
        hard-code number of SGPR/VGPR/AVGPR registers.
        * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
        SGPR/VGPR/AVGPR registers.

2024-02-01  Monk Chiang  <monk.chiang@sifive.com>

        * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
        attribute, and include sifive-p600.md.
        * config/riscv/generic-ooo.md: Update type attribute.
        * config/riscv/generic.md: Update type attribute.
        * config/riscv/sifive-7.md: Update type attribute.
        * config/riscv/sifive-p600.md: New file.
        * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
        * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
        Add sifive_p600.
        * config/riscv/riscv.cc (sifive_p600_tune_info): New.
        * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
        * doc/invoke.texi (RISC-V Options): Add sifive-p600-series

2024-02-01  Monk Chiang  <monk.chiang@sifive.com>

        * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
        Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
        * config/riscv/riscv.opt: New macro for 7 new unprivileged
        extensions.
        * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
        Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.

2024-02-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

        * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
        -static-libasan.  Add missing whitespace.

2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>

        * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
        (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
        Don't 'define_constants'.

2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>

        * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.

2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>

        * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
        [TARGET_RDNA3]: Adjust.

2024-02-01  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113693
        * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
        data when available.

2024-02-01  Jakub Jelinek  <jakub@redhat.com>
            Jason Merrill  <jason@redhat.com>

        PR c++/113531
        * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
        on variables which were promoted to TREE_STATIC.

2024-02-01  Roger Sayle  <roger@nextmovesoftware.com>
            Richard Biener  <rguenther@suse.de>

        PR target/113560
        * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
        information via tree_non_zero_bits to check if this operand
        is suitably extended for a widening (or highpart) multiplication.
        (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
        isn't already of the claimed type.

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

        Revert:
        2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

        * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
        (generic_ooo_branch): ditto
        * config/riscv/generic.md (generic_sfb_alu): ditto
        (generic_fmul_half): ditto
        * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
        * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
        (sifive_7_popcount): ditto
        * config/riscv/vector.md: change rdfrm to fmove
        * config/riscv/zc.md: change pushpop to load/store

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

        Revert:
        2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
                    Robin Dapp  <rdapp.gcc@gmail.com>

        * config/riscv/generic-ooo.md (generic_ooo): Move reservation
        (generic_ooo_vec_load): ditto
        (generic_ooo_vec_store): ditto
        (generic_ooo_vec_loadstore_seg): ditto
        (generic_ooo_vec_alu): ditto
        (generic_ooo_vec_fcmp): ditto
        (generic_ooo_vec_imul): ditto
        (generic_ooo_vec_fadd): ditto
        (generic_ooo_vec_fmul): ditto
        (generic_ooo_crypto): ditto
        (generic_ooo_perm): ditto
        (generic_ooo_vec_reduction): ditto
        (generic_ooo_vec_ordered_reduction): ditto
        (generic_ooo_vec_idiv): ditto
        (generic_ooo_vec_float_divsqrt): ditto
        (generic_ooo_vec_mask): ditto
        (generic_ooo_vec_vesetvl): ditto
        (generic_ooo_vec_setrm): ditto
        (generic_ooo_vec_readlen): ditto
        * config/riscv/riscv.md: include generic-vector-ooo
        * config/riscv/generic-vector-ooo.md: New file. to here

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

        Revert:
        2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

        * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

        * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
            Robin Dapp  <rdapp.gcc@gmail.com>

        * config/riscv/generic-ooo.md (generic_ooo): Move reservation
        (generic_ooo_vec_load): ditto
        (generic_ooo_vec_store): ditto
        (generic_ooo_vec_loadstore_seg): ditto
        (generic_ooo_vec_alu): ditto
        (generic_ooo_vec_fcmp): ditto
        (generic_ooo_vec_imul): ditto
        (generic_ooo_vec_fadd): ditto
        (generic_ooo_vec_fmul): ditto
        (generic_ooo_crypto): ditto
        (generic_ooo_perm): ditto
        (generic_ooo_vec_reduction): ditto
        (generic_ooo_vec_ordered_reduction): ditto
        (generic_ooo_vec_idiv): ditto
        (generic_ooo_vec_float_divsqrt): ditto
        (generic_ooo_vec_mask): ditto
        (generic_ooo_vec_vesetvl): ditto
        (generic_ooo_vec_setrm): ditto
        (generic_ooo_vec_readlen): ditto
        * config/riscv/riscv.md: include generic-vector-ooo
        * config/riscv/generic-vector-ooo.md: New file. to here

2024-02-01  Edwin Lu  <ewlu@rivosinc.com>

        * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
        (generic_ooo_branch): ditto
        * config/riscv/generic.md (generic_sfb_alu): ditto
        (generic_fmul_half): ditto
        * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
        * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
        (sifive_7_popcount): ditto
        * config/riscv/vector.md: change rdfrm to fmove
        * config/riscv/zc.md: change pushpop to load/store

2024-02-01  Andrew Pinski  <quic_apinski@quicinc.com>

        PR target/113657
        * config/aarch64/aarch64-simd.md (split for movv8di):
        For strict aligned mode, use DImode instead of TImode.

2024-01-31  Robin Dapp  <rdapp@ventanamicro.com>

        PR middle-end/113607
        * match.pd: Make sure else values match when folding a
        vec_cond into a conditional operation.

2024-01-31  Marek Polacek  <polacek@redhat.com>

        * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.

2024-01-31  Tamar Christina  <tamar.christina@arm.com>
            Matthew Malcomson  <matthew.malcomson@arm.com>

        PR sanitizer/112644
        * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
        memcmp.
        * builtins.cc (expand_builtin): Include HWASAN when checking for
        builtin inlining.

2024-01-31  Richard Biener  <rguenther@suse.de>

        PR middle-end/110176
        * match.pd (zext (bool) <= (int) 4294967295u): Make sure
        to match INTEGER_CST only without outstanding conversion.

2024-01-31  Alex Coplan  <alex.coplan@arm.com>

        PR target/111677
        * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
        V16QImode for the full 16-byte FPR saves in the vector PCS case.

2024-01-31  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/111444
        * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
        vn_reference_lookup_2 when optimistically skipping may-defs.

2024-01-31  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113630
        * tree-ssa-pre.cc (compute_avail): Avoid registering a
        reference with a representation with not matching base
        access size.

2024-01-31  Jakub Jelinek  <jakub@redhat.com>

        PR rtl-optimization/113656
        * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
        <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.

2024-01-31  Jakub Jelinek  <jakub@redhat.com>

        PR debug/113637
        * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
        with BLKmode are larger than DWARF2_ADDR_SIZE.

2024-01-31  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113639
        * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
        For VIEW_CONVERT_EXPR set rhs1 to its operand.

2024-01-31  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113670
        * tree-vect-data-refs.cc (vect_check_gather_scatter):
        Make sure we can take the address of the reference base.

2024-01-31  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
        ATA5835, ATtiny64AUTO, ATA5700M322.
        * doc/avr-mmcu.texi: Rebuild.

2024-01-31  Alexandre Oliva  <oliva@adacore.com>

        PR debug/113394
        * ipa-strub.cc (build_ref_type_for): Drop nonaliased.  Adjust
        caller.

2024-01-31  Alexandre Oliva  <oliva@adacore.com>

        PR middle-end/112917
        PR middle-end/113100
        * builtins.cc (expand_builtin_stack_address): Use
        STACK_ADDRESS_OFFSET.
        * doc/extend.texi (__builtin_stack_address): Adjust.
        * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
        * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
        * doc/tm.texi: Rebuilt.

2024-01-31  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113495
        * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
        (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
        (pre_vsetvl::compute_transparent): New function.
        (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.

2024-01-30  Fangrui Song  <maskray@google.com>

        PR target/105576
        * config/i386/constraints.md: Define constraint "Ws".
        * doc/md.texi: Document it.

2024-01-30  Marek Polacek  <polacek@redhat.com>

        PR c++/110358
        PR c++/109640
        * doc/invoke.texi: Update -Wdangling-reference description.

2024-01-30  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>

        * config/xtensa/constraints.md (R, T, U):
        Change define_constraint to define_memory_constraint.
        * config/xtensa/predicates.md (move_operand): Don't check that a
        constant pool operand size is a multiple of UNITS_PER_WORD.
        * config/xtensa/xtensa.cc
        (xtensa_lra_p, TARGET_LRA_P): Remove.
        (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
        clause as it can no longer be true.
        (fixup_subreg_mem): Drop function.
        (xtensa_output_integer_literal_parts): Consider 16-bit wide
        constants.
        (xtensa_legitimate_constant_p): Add short-circuit path for
        integer load instructions. Don't check that mode size is
        at least UNITS_PER_WORD.
        * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
        rather reload_in_progress and reload_completed.
        (doloop_end): Drop operand 2.
        (movhi_internal): Add alternative loading constant from a
        literal pool.
        (define_split for DI register_operand): Don't limit to
        !TARGET_AUTO_LITPOOLS.
        * config/xtensa/xtensa.opt (mlra): Change to no effect.

2024-01-30  Pan Li  <pan2.li@intel.com>

        * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
        calculate the gpr count required by vls mode.
        (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
        (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
        for vls mode.
        (riscv_get_arg_info): Add vls mode handling.
        (riscv_pass_by_reference): Return false if arg info has no zero gpr count.

2024-01-30  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113659
        * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
        Handle main exit without virtual use.

2024-01-30  Christoph Müllner  <christoph.muellner@vrull.eu>

        * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.

2024-01-30  Iain Sandoe  <iain@sandoe.co.uk>

        PR libgcc/113403
        * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
        (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
        * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
        * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
        * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
        * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.

2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/113623
        * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
        Mark all registers that occur in addresses as needing a GPR.

2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/113636
        * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
        the containing insn as an extra parameter.  Reset debug instructions
        if they reference a register that is no longer used by real insns.
        (early_ra::apply_allocation): Update calls accordingly.

2024-01-30  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113603
        * tree-ssa-strlen.cc (strlen_pass::handle_store): After
        count_nonzero_bytes call refetch si using get_strinfo in case it
        has been unshared in the meantime.

2024-01-30  Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/101195
        * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
        fit into unsigned HOST_WIDE_INT, return constm1_rtx.

2024-01-30  Jin Ma  <jinma@linux.alibaba.com>

        * config/riscv/thead.cc (th_print_operand_address): Change %ld
        to %lld.

2024-01-29  Manos Anagnostakis  <manos.anagnostakis@vrull.eu>
            Manolis Tsamis  <manolis.tsamis@vrull.eu>
            Philipp Tomsich  <philipp.tomsich@vrull.eu>

        * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
        * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
        Likewise.
        * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
        Call on framework moved later.

2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>

        * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
        instruction in naked function epilogues.

2024-01-29  YunQiang Su  <syq@gcc.gnu.org>

        PR target/113655
        * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
        gcc_cv_as_mips_explicit_relocs.
        * configure: Regnerated.

2024-01-29  Matthieu Longo  <matthieu.longo@arm.com>

        PR target/108933
        * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
        Correct generated RTL.
        (arm_rev16si2_alt1): Correctly handle conditional execution.
        (arm_rev16si2_alt2): Likewise.

2024-01-29  Richard Biener  <rguenther@suse.de>

        PR middle-end/113622
        * expr.cc (expand_assignment): Spill hard registers if
        we index them with a variable offset.

2024-01-29  Richard Biener  <rguenther@suse.de>

        PR middle-end/113622
        * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
        Also allow DECL_HARD_REGISTER variables.

2024-01-29  Alex Coplan  <alex.coplan@arm.com>

        PR target/113616
        * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
        Use iterate_safely when iterating over debug uses.
        (fixup_debug_uses): Likewise.
        (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
        over nondebug insns instead of manually maintaining the next insn.
        * iterator-utils.h (class safe_iterator): New.
        (iterate_safely): New.

2024-01-29  H.J. Lu  <hjl.tools@gmail.com>

        PR target/38534
        * config/i386/i386-options.cc (ix86_set_func_type): Save
        callee-saved registers in noreturn functions for -O0/-Og.

2024-01-29  Tobias Burnus  <tburnus@baylibre.com>

        PR target/113615
        * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
        define for !TARGET_RDNA2_PLUS.

2024-01-29  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/113281
        * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
        workaround for right shifts.
        (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
        (vect_determine_precisions_from_range): Be more selective about
        which codes can be narrowed based on their input and output ranges.
        For shifts, require at least one more bit of precision than the
        maximum shift amount.

2024-01-29  Tobias Burnus  <tburnus@baylibre.com>

        * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.

2024-01-29  Tobias Burnus  <tburnus@baylibre.com>

        * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
        but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
        LLVM 13.0.1+.

2024-01-29  Tobias Burnus  <tburnus@baylibre.com>

        PR other/111966
        * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
        (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
        (SET_SRAM_ECC_UNSET): ... this.
        (copy_early_debug_info): Remove gfx900 special case, now handled as
        part of the generic handling.
        (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.

2024-01-29  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/110603
        * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
        setting of pdata->maxlen to vr.upper_bound (which is unconditionally
        overwritten anyway).  Avoid creating invalid range with minlen
        larger than maxlen.  Formatting fix.

2024-01-29  Richard Biener  <rguenther@suse.de>

        PR debug/103047
        * tree-inline.cc (initialize_inlined_parameters): Reverse
        the decl chain of inlined parameters.

2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>

        * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
        alignment of CFString constants by setting DECL_USER_ALIGN.

2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
            Jakub Jelinek   <jakub@redhat.com>

        PR libgcc/113402
        * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
        and BUILT_IN_GCC_NESTED_PTR_DELETED.
        * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
        BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
        rename the library fallbacks to __gcc_nested_func_ptr_created and
        __gcc_nested_func_ptr_deleted.
        * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
        and __gcc_nested_func_ptr_deleted.
        * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
        BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
        * tree.cc (build_common_builtin_nodes): Build the
        BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
        builtins only for non-explicit.

2024-01-28  YunQiang Su  <syq@gcc.gnu.org>

        * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.

2024-01-27  H.J. Lu  <hjl.tools@gmail.com>

        PR target/38534
        * config/i386/i386-options.cc (ix86_set_func_type): Don't
        save and restore callee saved registers for a noreturn function
        with nothrow or compiled with -fno-exceptions.

2024-01-27  H.J. Lu  <hjl.tools@gmail.com>

        PR target/103503
        PR target/113312
        * config/i386/i386-expand.cc (ix86_expand_call): Replace
        no_caller_saved_registers check with call_saved_registers check.
        Clobber all registers that are not used by the callee with
        no_callee_saved_registers attribute.
        * config/i386/i386-options.cc (ix86_set_func_type): Set
        call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
        noreturn function.  Disallow no_callee_saved_registers with
        interrupt or no_caller_saved_registers attributes together.
        (ix86_set_current_function): Replace no_caller_saved_registers
        check with call_saved_registers check.
        (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
        (ix86_handle_call_saved_registers_attribute): This.
        (ix86_gnu_attributes): Add
        ix86_handle_call_saved_registers_attribute.
        * config/i386/i386.cc (ix86_conditional_register_usage): Replace
        no_caller_saved_registers check with call_saved_registers check.
        (ix86_function_ok_for_sibcall): Don't allow callee with
        no_callee_saved_registers attribute when the calling function
        has callee-saved registers.
        (ix86_comp_type_attributes): Also check
        no_callee_saved_registers.
        (ix86_epilogue_uses): Replace no_caller_saved_registers check
        with call_saved_registers check.
        (ix86_hard_regno_scratch_ok): Likewise.
        (ix86_save_reg): Replace no_caller_saved_registers check with
        call_saved_registers check.  Don't save any registers for
        TYPE_NO_CALLEE_SAVED_REGISTERS.  Save all registers with
        TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
        no_callee_saved_registers attribute is called.
        (find_drap_reg): Replace no_caller_saved_registers check with
        call_saved_registers check.
        * config/i386/i386.h (call_saved_registers_type): New enum.
        (machine_function): Replace no_caller_saved_registers with
        call_saved_registers.
        * doc/extend.texi: Document no_callee_saved_registers attribute.

2024-01-27  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113614
        * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
        widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
        TRUNC_MOD_EXPR or FLOAT_EXPR uses.

2024-01-27  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113568
        * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
        For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
        in the widening extension checks.

2024-01-27  Jakub Jelinek  <jakub@redhat.com>

        * gimple-lower-bitint.cc (gimple_lower_bitint): For
        TDF_DETAILS dump mapping of SSA_NAMEs to decls.

2024-01-26  Hans-Peter Nilsson  <hp@axis.com>

        * cgraphunit.cc (process_function_and_variable_attributes): Tweak
        the warning for an attribute-always_inline without inline declaration.

2024-01-26  Robin Dapp  <rdapp@ventanamicro.com>

        PR other/113575
        * genopinit.cc (main): Split init_all_optabs into functions
        of 1000 patterns each.

2024-01-26  Tobias Burnus  <tburnus@baylibre.com>

        * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
        TM_MULTILIB_CONFIG.
        * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
        * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
        -march/-mtune.

2024-01-26  Andrew Stubbs  <ams@baylibre.com>

        * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
        * config/gcn/gcn-valu.md (all_convert): New iterator.
        (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
        define_expand, and rename the old one to ...
        (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
        (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
        (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
        (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
        * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
        (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
        * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
        (<u>mulqihi3_scalar): Likewise.

2024-01-26  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113602
        * tree-data-ref.cc (dr_analyze_innermost): Fail when
        the base object isn't addressable.

2024-01-26  Tobias Burnus  <tburnus@baylibre.com>

        * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
        "--amdhsa-code-object-version=" argument.
        (ASM_SPEC): Use it; replace previous version of it.

2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
        (pre_vsetvl::emit_vsetvl): Ditto.

2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>

        * config/loongarch/lasx.md (vec_extract<mode>_0):
        New define_insn_and_split patten.

2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>

        * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.

2024-01-26  Li Wei  <liwei@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.

2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113469
        * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.

2024-01-26  Andrew Pinski  <quic_apinski@quicinc.com>

        PR target/100212
        * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
        undefined shift after the call to exact_log2.

2024-01-25  Andrew Pinski  <quic_apinski@quicinc.com>

        PR target/100204
        * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
        before taking the negative of it.

2024-01-25  Vladimir N. Makarov  <vmakarov@redhat.com>

        PR target/113526
        * lra-constraints.cc (curr_insn_transform): Change class even for
        spilled pseudo successfully matched with with NO_REGS.

2024-01-25  Georg-Johann Lay  <avr@gjlay.de>

        PR target/113601
        * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.

2024-01-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>

        PR target/112987
        * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
        (aarch64_expand_epilogue): Use the new function.
        (aarch64_split_compare_and_swap): Likewise.
        (aarch64_split_atomic_op): Likewise.

2024-01-25  Robin Dapp  <rdapp.gcc@gmail.com>

        PR middle-end/112971
        * fold-const.cc (simplify_const_binop): New function for binop
        simplification of two constant vectors when element-wise
        handling is not necessary.
        (const_binop): Call new function.

2024-01-25  Mary Bennett  <mary.bennett@embecosm.com>

        * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
        * config/riscv/constraints.md: Likewise.
        * config/riscv/corev.def: Likewise.
        * config/riscv/corev.md: Likewise.
        * config/riscv/predicates.md: Likewise.
        * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
        * config/riscv/riscv-ftypes.def: Likewise.
        * config/riscv/riscv.opt: Likewise.
        * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
        * doc/extend.texi: Add XCVbitmanip builtin documentation.
        * doc/sourcebuild.texi: Likewise.

2024-01-25  Tobias Burnus  <tburnus@baylibre.com>

        * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.

2024-01-25  Yanzhang Wang  <yanzhang.wang@intel.com>

        PR target/113538
        * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
        (riscv_fntype_abi): Ditto.
        * config/riscv/riscv.opt: Ditto.

2024-01-25  Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/113574
        * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
        count against TYPE_PRECISION rather than TYPE_SIZE.

2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/113572
        * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
        Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT

2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/113550
        * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
        whether each split instruction is a load that clobbers the source
        address.  Emit that instruction last if so.

2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/113485
        * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
        pattern.
        (<optab><Vnarrowq><mode>2): Use it instead of generating a
        paradoxical subreg for the input.

2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
        (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
        predecessors dump information.

2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
        redundant full available computation.
        (pre_vsetvl::pre_global_vsetvl_info): Ditto.

2024-01-25  Jakub Jelinek  <jakub@redhat.com>

        * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
        * doc/rtl.texi (CONST_VECTOR): Likewise.

2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
        * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
        (pass_vsetvl::execute): Ditto.
        * config/riscv/riscv.opt: Ditto.

2024-01-25  Jiahao Xu  <xujiahao@loongson.cn>

        * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
        * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.

2024-01-25  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113576
        * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
        exits with may_be_zero niters when its the last one.

2024-01-25  Lulu Cheng  <chenglulu@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
        For symbols of type tls, non-zero Offset is not generated.

2024-01-25  Haochen Gui  <guihaoc@gcc.gnu.org>

        * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
        P9 with m32 and mpowerpc64.

2024-01-25  liuhongt  <hongtao.liu@intel.com>

        * config/i386/i386-options.cc (ix86_option_override_internal):
        Enable -mlam=u57 by default when compiled with
        -fsanitize=hwaddress.

2024-01-25  Palmer Dabbelt  <palmer@rivosinc.com>

        * common/config/riscv/riscv-common.cc (riscv_implied_info):
        Remove {"ztso", "a"}.

2024-01-24  Martin Jambor  <mjambor@suse.cz>

        PR ipa/108007
        PR ipa/112616
        * cgraph.h (cgraph_edge): Add a parameter to
        redirect_call_stmt_to_callee.
        * ipa-param-manipulation.h (ipa_param_adjustments): Add a
        parameter to modify_call.
        (ipa_release_ssas_in_hash): Declare.
        * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
        parameter killed_ssas, pass it to padjs->modify_call.
        * ipa-param-manipulation.cc (purge_all_uses): New function.
        (ipa_param_adjustments::modify_call): New parameter killed_ssas.
        Instead of substituting uses, invoke purge_all_uses.  If
        hash of killed SSAs has not been provided, create a temporary one
        and release SSAs that have been added to it.
        (compare_ssa_versions): New function.
        (ipa_release_ssas_in_hash): Likewise.
        * tree-inline.cc (redirect_all_calls): Create
        id->killed_new_ssa_names earlier, pass it to edge redirection,
        adjust a comment.
        (copy_body): Release SSAs in id->killed_new_ssa_names.

2024-01-24  Andrew Pinski  <quic_apinski@quicinc.com>

        PR target/113486
        * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
        TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.

2024-01-24  Monk Chiang  <monk.chiang@sifive.com>

        PR target/113095
        * config/riscv/sfb.md: New splitters to rewrite single bit
        sign extension as the condition to SFB instructions.

2024-01-24  Jan Hubicka  <jh@suse.cz>

        PR middle-end/88345
        * common.opt: (flimit-function-alignment): Reorder alphabeticaly
        (fmin-function-alignment): New parameter.
        * doc/invoke.texi: (-fmin-function-alignment): Document.
        (-falign-functions,-falign-loops,-falign-labels): Mention that
        aglinments are ignored in cold code.
        * varasm.cc (assemble_start_function): Handle min-function-alignment.

2024-01-24  Tamar Christina  <tamar.christina@arm.com>

        PR target/109636
        * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
        mulv2di3): Remove.
        * config/aarch64/iterators.md (VQDIV): Remove.
        (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
        SVE_I_SIMD_DI): New.
        (VPRED, sve_lane_con): Add V4SI and V2DI.
        * config/aarch64/aarch64-sve.md (<optab><mode>3,
        @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
        (mul<mode>3): New, split from <optab><mode>3.
        (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
        * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
        *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
        SVE_FULL_HSDI_SIMD_DI.

2024-01-24  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113552
        * config/aarch64/aarch64.cc
        (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.

2024-01-24  Martin Jambor  <mjambor@suse.cz>

        PR ipa/113490
        * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
        count is equal or greater than the limit.  Use the limit from the
        callee.

2024-01-24  YunQiang Su  <syq@gcc.gnu.org>

        * configure.ac: Detect the explicit relocs support for
        mips, and define C macro MIPS_EXPLICIT_RELOCS.
        * config.in: Regenerated.
        * configure: Regenerated.
        * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
        * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
        * config/mips/mips.cc(mips_set_compression_mode): Sorry if
        !TARGET_EXPLICIT_RELOCS instead of just set it.
        * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
        TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
        * config/mips/mips.opt: Introduce -mexplicit-relocs= option
        and define -m(no-)explicit-relocs as aliases.

2024-01-24  Alex Coplan  <alex.coplan@arm.com>

        * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
        to 1.
        (-mlate-ldp-fusion): Likewise.

2024-01-24  Tamar Christina  <tamar.christina@arm.com>

        * tree-vect-loop.cc (vect_get_vect_def,
        vect_create_epilog_for_reduction): Rename main_exit_p to
        last_val_reduc_p.

2024-01-24  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113364
        * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
        early exits then we must reduce from the first offset for all of them.

2024-01-24  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113495
        * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
        (get_regno): Ditto.
        (get_bb_index): Ditto.
        (pre_vsetvl::compute_avl_def_data): Ditto.
        (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
        (pre_vsetvl::pre_global_vsetvl_info): Ditto.

2024-01-23  Andrew Pinski  <quic_apinski@quicinc.com>
            Richard Sandiford  <richard.sandiford@arm.com>

        PR target/100942
        * ccmp.cc (ccmp_candidate_p): Add outer argument.
        Allow if the outer is true and the lhs is used more
        than once.
        (expand_ccmp_expr): Update call to ccmp_candidate_p.
        * expr.h (expand_expr_real_gassign): Declare.
        * expr.cc (expand_expr_real_gassign): New function, split out from...
        (expand_expr_real_1): ...here.
        * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

        PR target/113089
        * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
        (fixup_debug_use): New.
        (fixup_debug_uses_trailing_add): New.
        (fixup_debug_uses): New. Use it ...
        (ldp_bb_info::fuse_pair): ... here.
        (try_promote_writeback): Call fixup_debug_uses_trailing_add to
        fix up debug uses of the base register that are affected by
        folding in the trailing add insn.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

        PR target/113089
        * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
        Update trailing nondebug uses of the base register in the case
        of cancelling writeback.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

        PR target/113089
        * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
        (debug_insn_use_iterator): New.
        (set_info::first_debug_insn_use): New.
        (set_info::debug_insn_uses): New.
        * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
        (set_info::first_debug_insn_use): New.
        (set_info::debug_insn_uses): New.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

        PR target/113356
        * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
        Don't record hazards against the opposite insn in the pair.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

        PR target/113070
        * config/aarch64/aarch64-ldp-fusion.cc
        (struct stp_change_builder): New.
        (decide_stp_strategy): Reanme to ...
        (try_repurpose_store): ... this.
        (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
        construct stp changes.  Fix up uses when inserting new stp insns.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

        PR target/113070
        * rtl-ssa.h: Include hash-set.h.
        * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
        new_sets parameter and use it to keep track of new user-created sets.
        (function_info::apply_changes_to_insn): Also call add_def on new sets.
        (function_info::change_insns): Add hash_set to keep track of new
        user-created defs.  Plumb it through.
        * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
        apply_changes_to_insn.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

        PR target/113070
        * rtl-ssa/accesses.cc (function_info::create_use): New.
        * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
        Ensure new uses end up referring to permanent defs.
        * rtl-ssa/functions.h (function_info::create_use): Declare.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

        PR target/113070
        * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
        to finalize_new_accesses from the backwards placement loop, run it
        forwards in a separate loop.

2024-01-23  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113552
        * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
        floor_log2 instead of exact_log2 on the number of calls.

2024-01-23  Jeff Law  <jlaw@ventanamicro.com>
            Jakub Jelinek  <jakub@redhat.com>

        * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
        decl.

2024-01-23  Richard Biener  <rguenther@suse.de>

        * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
        Separate single and multi-exit case when creating PHIs between
        the main and epilogue.

2024-01-23  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/112989
        * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
        MODE_single variants of functions that don't take tuple arguments.

2024-01-23  Alex Coplan  <alex.coplan@arm.com>

        PR target/113114
        * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
        Don't assert recog success, just punt if the writeback pair
        isn't recognized.

2024-01-23  Jakub Jelinek  <jakub@redhat.com>

        * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
        ATTRIBUTE_UNUSED to decl.

2024-01-23  Richard Biener  <rguenther@suse.de>

        PR debug/107058
        * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
        handle unexpected but bogus DIE contexts when not checking
        enabled.

2024-01-23  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113462
        * fold-const.cc (native_interpret_int): Don't punt if total_bytes
        is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
        (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
        sizes between 129 and 8192 bytes.

2024-01-23  Xi Ruoyao  <xry111@xry111.site>

        * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
        If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
        for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
        (loongarch_call_tls_get_addr): Do not split symbols of
        SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
        EXPLICIT_RELOCS_AUTO.

2024-01-23  Richard Biener  <rguenther@suse.de>

        * alias.cc (known_base_value_p): Remove.
        (find_base_value): Remove PLUS/MINUS handling
        when both operands are not CONST_INT_P.

2024-01-23  Richard Biener  <rguenther@suse.de>

        PR rtl-optimization/113255
        * alias.cc (find_base_term): Remove PLUS/MINUS handling
        when both operands are not CONST_INT_P.

2024-01-23  Richard Biener  <rguenther@suse.de>

        PR debug/112718
        * dwarf2out.cc (dwarf2out_finish): Reset all type units
        for the fat part of an LTO compile.

2024-01-23  chenxiaolong  <chenxiaolong@loongson.cn>

        * doc/sourcebuild.texi: Add attributes for keywords.

2024-01-23  Sandra Loosemore  <sandra@codesourcery.com>

        PR c++/90463
        * doc/invoke.texi (Warning Options): Correct lists of options
        enabled by -Wall and -Wextra by checking against common.opt
        and c-family/c.opt.

2024-01-22  Andrew Pinski  <quic_apinski@quicinc.com>

        PR target/113030
        * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
        instead of cpu_optaliases.
        (check_arch): Use arch_opt_alias instead of arch_optaliases.

2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
        * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
        * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.

2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/109092
        * config/riscv/riscv.md: Use reg instead of subreg.

2024-01-22  Tobias Burnus  <tburnus@baylibre.com>

        PR other/111966
        * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
        to match the compiler default.
        (simple_object_copy_lto_debug_sections): Never unlink the outfile
        on error as the caller does so.
        (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
        (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.

2024-01-22  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113373
        * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
        Create LC PHIs in the exit blocks where necessary.
        * tree-vect-loop.cc (vectorizable_live_operation): Do not try
        to handle missing LC PHIs.
        (find_connected_edge): Remove.
        (vect_create_epilog_for_reduction): Cleanup use of auto_vec.

2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.

2024-01-22  xuli  <xuli1@eswincomputing.com>

        PR target/113420
        * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
        (registered_function::overloaded_hash):refactor.
        (resolve_overloaded_builtin):avoid internal ICE.

2024-01-21  Mikael Pettersson  <mikpelinux@gmail.com>

        PR target/82420
        PR target/111279
        * calls.cc (emit_library_call_value_1): Pass valid TYPE
        to emit_push_insn.
        * expr.cc (emit_push_insn): Likewise.

2024-01-21  Jeff Law  <jlaw@ventanamicro.com>

        * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
        correcction version of last change.

2024-01-21  Jeff Law  <jlaw@ventanamicro.com>

        * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
        fix bugs in signature.

2024-01-21  Roger Sayle  <roger@nextmovesoftware.com>
            Richard Biener  <rguenther@suse.de>

        PR rtl-optimization/111267
        * fwprop.cc (fwprop_propagation::profitabe_p): Rename
        profitable_p method to likely_profitable_p.
        (try_fwprop_subst_node): Update call to likely_profitable_p.
        Only bail-out early when !prop.likely_profitable_p for instructions
        that are not single sets.  When comparing costs, bail-out if the
        cost is unchanged and !prop.likely_profitable_p.

2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>

        PR c++/90464
        * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
        isn't enabled by -Wunused unless -Wextra is provided, and that
        -Wunused does enable -Wunused-const-variable=1 for C.  Clarify that
        -Wunused doesn't enable -Wunused-* options documented as behaving
        otherwise, and list them explicitly.

2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>

        PR c/109708
        * doc/invoke.texi (Warning Options): Fix broken example and
        clean up/reorganize the others.  Also describe what the short-form
        options mean.

2024-01-20  Sandra Loosemore  <sandra@codesourcery.com>

        PR c/102998
        * doc/invoke.texi (Option Summary): Add -Warray-parameter.
        (Warning Options): Correct/edit discussion of -Warray-parameter
        to make the first example less confusing, and fill in missing info.

2024-01-20  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113462
        * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
        Handle rhs1 INTEGER_CST like SSA_NAME.

2024-01-20  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113491
        * tree-switch-conversion.cc (switch_conversion::build_constructors):
        If elt.index has precision higher than sizetype, fold_convert it to
        sizetype.
        (switch_conversion::array_value_type): Return type if type is
        BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
        (switch_conversion::build_arrays): Use unsigned_type_for rather than
        lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
        above MAX_FIXED_MODE_SIZE or with BLKmode.  If utype has precision
        higher than sizetype, use sizetype as tidx type and fold_convert the
        subtraction to sizetype.

2024-01-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
        (riscv_vector_mode_supported_any_target_p): Ditto.

2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>

        PR target/110934
        * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
        (TARGET_ZERO_CALL_USED_REGS): Define.

2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>

        PR target/108640
        * config/m68k/m68k.cc (output_andsi3): Use QImode for
        address adjusted for 1-byte RMW access.
        (output_iorsi3): Likewise.
        (output_xorsi3): Likewise.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

        * doc/invoke.texi (RISC-V Options): Add list of supported
        extensions.

2024-01-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113495
        * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
        (RVV_VUNDEF): Ditto.
        * config/riscv/riscv-vsetvl.cc: Add timevar.

2024-01-19  Richard Biener  <rguenther@suse.de>

        PR debug/113488
        * lto-streamer-in.cc (lto_read_tree_1): When there isn't
        an early DIE but there should be, do not pretend there is.

2024-01-19  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113494
        * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
        Handle endless loop on exit.  Handle re-allocated PHI.

2024-01-19  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113464
        * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
        optimize loads into GIMPLE_ASM stmts.

2024-01-19  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113463
        * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
        Only look through NOP_EXPRs if rhs1 doesn't have wider type than
        lhs.

2024-01-19  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113459
        * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
        TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
        of SCALAR_INT_TYPE_MODE if type has BLKmode.
        (vn_reference_lookup_3): Likewise.  Formatting fix.

2024-01-19  Jakub Jelinek  <jakub@redhat.com>
            Richard Biener  <rguenther@suse.de>

        * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
        VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
        * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
        but adjust_address also for BLKmode mode and MEM op0.

2024-01-19  Palmer Dabbelt  <palmer@rivosinc.com>

        * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
        extensions.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

        * doc/invoke.texi (RISC-V Options): Document the syntax of -march.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

        * common/config/riscv/riscv-common.cc
        (riscv_subset_list::parse_std_ext): Remove.
        (riscv_subset_list::parse_multiletter_ext): Remove.
        * config/riscv/riscv-subset.h
        (riscv_subset_list::parse_std_ext): Remove.
        (riscv_subset_list::parse_multiletter_ext): Remove.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

        * common/config/riscv/riscv-common.cc
        (riscv_subset_list::parse_single_std_ext): New parameter.
        (riscv_subset_list::parse_single_multiletter_ext): Ditto.
        (riscv_subset_list::parse_single_ext): Ditto.
        (riscv_subset_list::parse): Relax the order for the input of ISA
        string.
        * config/riscv/riscv-subset.h
        (riscv_subset_list::parse_single_std_ext): New parameter.
        (riscv_subset_list::parse_single_multiletter_ext): Ditto.
        (riscv_subset_list::parse_single_ext): Ditto.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

        * common/config/riscv/riscv-common.cc
        (riscv_subset_list::parse_base_ext): New.
        (riscv_subset_list::parse): Extract part of logic into
        riscv_subset_list::parse_base_ext.
        * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
        New.

2024-01-19  Kito Cheng  <kito.cheng@sifive.com>

        * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
        sorry message.

2024-01-19  Kuan-Lin Chen  <rufus@andestech.com>

        * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
        UNSPEC_CLMUL_VC.

2024-01-19  Sandra Loosemore  <sandra@codesourcery.com>

        PR c/110029
        * doc/extend.texi (Common Variable Attributes): Explain what
        happens when multiple variables with cleanups are in the same scope.

2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>

        PR ipa/108470
        * doc/extend.texi (Common Function Attributes): Document that
        noinline also disables some interprocedural optimizations and
        improve flow to the part about using inline asm instead to
        disable calls from being optimized away completely.  Remove the
        sentence that says noipa is mainly for internal compiler testing.

2024-01-18  John David Anglin  <danglin@gcc.gnu.org>

        PR tree-optimization/69807
        * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.

2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>

        PR target/108521
        * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
        from x86 Windows Options.

2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>

        PR c/107942
        * doc/extend.texi (C Extensions): Add new section to menu.
        (Function Attributes):  Move dangling index entries to....
        (Const and Volatile Functions): New section.

2024-01-18  David Malcolm  <dmalcolm@redhat.com>

        PR middle-end/112684
        * toplev.cc (toplev::main): Don't ICE in
        -fdiagnostics-generate-patch when exiting after options,
        since no edit context will have been created.

2024-01-18  Richard Biener  <rguenther@suse.de>

        * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
        operands vector.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

        * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
        when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
            Jin Ma  <jinma@linux.alibaba.com>
            Xianmiao Qu  <cooper.qu@linux.alibaba.com>
            Christoph Müllner  <christoph.muellner@vrull.eu>

        * config/riscv/thead.cc
        (th_asm_output_opcode): Rewrite some instructions.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
            Jin Ma  <jinma@linux.alibaba.com>
            Xianmiao Qu  <cooper.qu@linux.alibaba.com>
            Christoph Müllner  <christoph.muellner@vrull.eu>

        * config/riscv/riscv.md (none,thv,rvv): New attribute.
        (no,yes): Add an attribute to disable alternative
        for xtheadvector or RVV1.0.
        * config/riscv/vector.md:
        Disable alternatives that destination register overlaps
        source register group for xtheadvector.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
            Jin Ma  <jinma@linux.alibaba.com>
            Xianmiao Qu  <cooper.qu@linux.alibaba.com>
            Christoph Müllner  <christoph.muellner@vrull.eu>

        * config/riscv/riscv-vector-builtins-bases.cc
        (class th_loadstore_width): Define new builtin bases.
        (class th_extract): Define new builtin bases.
        (BASE): Define new builtin bases.
        * config/riscv/riscv-vector-builtins-bases.h:
        Define new builtin class.
        * config/riscv/riscv-vector-builtins-shapes.cc
        (struct th_loadstore_width_def): Define new builtin shapes.
        (struct th_indexed_loadstore_width_def):
        Define new builtin shapes.
        (struct th_extract_def): Define new builtin shapes.
        (SHAPE): Define new builtin shapes.
        * config/riscv/riscv-vector-builtins-shapes.h:
        Define new builtin shapes.
        * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
        Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
        * config/riscv/riscv-vector-builtins.h
        (enum required_ext): Add new XTheadVector member.
        (struct function_group_info): Likewise.
        * config/riscv/t-riscv:
        Add thead-vector-builtins-functions.def
        * config/riscv/thead-vector.md
        (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
        (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
        (@pred_store_width<vlmem_op_attr><mode>): Likewise.
        (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
        (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
        (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
        (@pred_th_extract<mode>): Likewise.
        (*pred_th_extract<mode>): Likewise.
        * config/riscv/thead-vector-builtins-functions.def: New file.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
            Jin Ma  <jinma@linux.alibaba.com>
            Xianmiao Qu  <cooper.qu@linux.alibaba.com>
            Christoph Müllner  <christoph.muellner@vrull.eu>

        * config.gcc:  Add files for XTheadVector intrinsics.
        * config/riscv/autovec.md: Guard XTheadVector.
        * config/riscv/predicates.md: Disable immediate vl
        for XTheadVector.
        * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
        Add pragma for XTheadVector.
        * config/riscv/riscv-string.cc (riscv_expand_block_move):
        Guard XTheadVector.
        * config/riscv/riscv-v.cc (vls_mode_valid_p):
        Avoid autovec.
        * config/riscv/riscv-vector-builtins-bases.cc:
        Do not normalize vsetvl instructions for XTheadVector.
        * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
        New check type function.
        (build_one): Adjust for XTheadVector.
        * config/riscv/riscv-vector-switch.def (ENTRY):
        Disable fractional mode for the XTheadVector extension.
        (TUPLE_ENTRY): Likewise.
        * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
        Guard XTheadVector.
        (riscv_preferred_simd_mode): Likewsie.
        (riscv_autovectorize_vector_modes): Likewise.
        (riscv_vector_mode_supported_any_target_p): Likewise.
        (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
        * config/riscv/thead.cc (th_asm_output_opcode):
        Rewrite vsetvl instructions.
        * config/riscv/vector.md:
        Include thead-vector.md and change fractional LMUL
        into 1 for vbool.
        * config/riscv/riscv_th_vector.h: New file.
        * config/riscv/thead-vector.md: New file.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
            Jin Ma  <jinma@linux.alibaba.com>
            Xianmiao Qu  <cooper.qu@linux.alibaba.com>
            Christoph Müllner  <christoph.muellner@vrull.eu>

        * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
        Add new function to add assembler insn code prefix/suffix.
        (th_asm_output_opcode):
        Add Thead function to add assembler insn code prefix/suffix.
        * config/riscv/riscv.cc (riscv_asm_output_opcode):
        Implement function to add assembler insn code prefix/suffix.
        * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
        Add new function to add assembler insn code prefix/suffix.
        * config/riscv/thead.cc (th_asm_output_opcode):
        Implement Thead function to add assembler insn code
        prefix/suffix.

2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
            Jin Ma  <jinma@linux.alibaba.com>
            Xianmiao Qu  <cooper.qu@linux.alibaba.com>
            Christoph Müllner  <christoph.muellner@vrull.eu>

        * common/config/riscv/riscv-common.cc
        (riscv_subset_list::parse): Add new vendor extension.
        * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
        Add test marco.
        * config/riscv/riscv.opt:  Add new mask.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

        * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
        to be conditional on macosx-version-min.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

        * config/darwin.cc (darwin_objc1_section): Use the correct
        meta-data version for constant strings.
        (machopic_select_section): Assert if we fail to handle CFString
        sections as Obejctive-C meta-data or drectly.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

        * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
        OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
        OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
        versions when the object format is Mach-O.

2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>

        PR target/105522
        * config/darwin.cc (machopic_select_section): Handle C and C++
        CFStrings.
        (darwin_rename_builtins): Move this out of the CFString code.
        (darwin_libc_has_function): Likewise.
        (darwin_build_constant_cfstring): Create an anonymous var to
        hold each CFString.
        * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
        CFstrings.

2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>

        PR bootstrap/113445
        * haifa-sched.cc (dep_list_size): Make global.
        * sched-deps.cc (find_inc): Use instead of sd_lists_size().
        * sched-int.h (dep_list_size): Declare.

2024-01-18  Martin Jambor  <mjambor@suse.cz>

        PR tree-optimization/110422
        * tree-sra.cc (scan_function): Disqualify bases of operands of asm
        gotos.

2024-01-18  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113475
        * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
        * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
        (phi_analyzer::~phi_analyzer): Deallocate and free collected
        phi_grous.
        (phi_analyzer::process_phi): Record allocated phi_groups.

2024-01-18  Richard Biener  <rguenther@suse.de>

        * tree-vect-stmts.cc (vectorizable_store): Do not allocate
        storage for gvec_oprnds elements.

2024-01-18  Richard Biener  <rguenther@suse.de>

        * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
        prefer all later exits we can handle.
        (vect_analyze_loop_form): Free the allocated loop body.
        Adjust comments.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/avr-log.cc: Tabify.

2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/autovec.md: Support vi variant.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/avr-devices.cc: Tabify.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/avr-c.cc: Tabify.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/driver-avr.cc: Tabify.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/gen-avr-mmcu-texi.cc: Tabify.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/gen-avr-mmcu-specs.cc: Tabify.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

        * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
        minline-strcmp, minline-strncmp, minline-strlen,
        -param=riscv-vector-abi): Remove Bool keywords.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

        PR target/113122
        * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
        support.  Add missing space after , in emitted assembly in some
        cases.  Formatting fixes.

2024-01-18  Xi Ruoyao  <xry111@xry111.site>

        * config/loongarch/loongarch.md (movsi_internal): Remove
        constraint z.

2024-01-18  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
        in the diagnostic, and capitalize the device name.
        (print_mcu): Generate specs such that:
        <*check_rodata_in_ram>: New.
        <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
        <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
        <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.

2024-01-18  Jakub Jelinek  <jakub@redhat.com>

        PR other/113399
        * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
        Common and Optimization.

2024-01-18  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113431
        * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
        When there is an invariant load we might not preserve
        scalar order.

2024-01-18  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113374
        * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
        * tree-vect-loop.cc (move_early_exit_stmts): Update
        virtual LC PHIs.
        * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
        Refactor.  Preserve virtual LC PHIs on all exits.

2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_split_symbol):
        Assign the '/u' attribute to the mem.

2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>

        PR middle-end/110847
        * doc/invoke.texi (Option Summary): Document negative forms of
        -Wtsan and -Wxor-used-as-pow.
        (Warning Options): Likewise.

2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113429
        * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.

2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>

        * doc/extend.texi (Common Function Attributes): Re-alphabetize
        the table.
        (Common Variable Attributes): Likewise.
        (Common Type Attributes): Likewise.

2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>

        PR middle-end/111659
        * doc/extend.texi (Common Variable Attributes): Fix long lines
        in documentation of strict_flex_array + other minor copy-editing.
        Add a cross-reference to -Wstrict-flex-arrays.
        * doc/invoke.texi (Option Summary): Fix whitespace in tables
        before -fstrict-flex-arrays and -Wstrict-flex-arrays.
        (C Dialect Options): Combine the docs for the two
        -fstrict-flex-arrays forms into a single entry.  Note this option
        is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
        (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
        Minor copy-editing.  Add cross references to the strict_flex_array
        attribute and -fstrict-flex-arrays option.  Add note that this
        option depends on -ftree-vrp.

2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>

        PR target/113221
        * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
        only allow REG operands instead of allowing all.

2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>

        * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
        Remove redundant checks in else condition for readablity.
        (earliest_fuse_vsetvl_info) Print iteration count in debug
        prints.
        (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
        dump details in certain cases.

2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>

        * config/riscv/riscv.opt: New -param=vsetvl-strategy.
        * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
        * config/riscv/riscv-vsetvl.cc
        (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
        (pass_vsetvl::execute): Use vsetvl_strategy.

2024-01-17  Jan Hubicka  <jh@suse.cz>

        * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
        accidental hack reseting offset.

2024-01-17  Jan Hubicka  <jh@suse.cz>

        * config/i386/i386-options.cc (ix86_option_override_internal): Fix
        handling of X86_TUNE_AVOID_512FMA_CHAINS.

2024-01-17  Jan Hubicka  <jh@suse.cz>
            Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/110852
        * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
        binary operations
        (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
        PRED_COMBINED_VALUE_PREDICTIONS_PHI
        * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
        (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113421
        * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
        comment.
        (bitint_dom_walker::before_dom_children): Add g temporary to simplify
        formatting.  Start at vop rather than cvop even if stmt is a store
        and needs_operand_addr.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/113410
        * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
        If access_nelts is integral with larger precision than sizetype,
        fold_convert it to sizetype.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113408
        * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
        VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
        to handle_cast.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/113406
        * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
        regardless of whether is_gimple_reg_type (restype) or not.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

        * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
        funcions -> functions, and use were instead of was.
        * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
        and guaranteee -> guarantee.
        * attribs.h (struct attr_access): Fix comment typo funcion -> function.

2024-01-17  Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/113409
        * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
        INTEGER_TYPE.
        (omp_extract_for_data): Use build_bitint_type rather than
        build_nonstandard_integer_type if either iter_type or loop->v type
        is BITINT_TYPE.
        * omp-expand.cc (expand_omp_for_generic,
        expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
        BITINT_TYPE like INTEGER_TYPE.

2024-01-17  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113371
        * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
        Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
        * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
        not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.

2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>

        PR rtl-optimization/96388
        PR rtl-optimization/111554
        * sched-deps.cc (find_inc): Avoid exponential behavior.

2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>

        PR c/111693
        * doc/invoke.texi (Option Summary): Move -Wuseless-cast
        from C++ Language Options to Warning Options.  Add entry for
        -Wuse-after-free.
        (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
        from here....
        (Warning Options): ...to here.  Minor copy-editing to fix typo
        and grammar.

2024-01-17  YunQiang Su  <syq@gcc.gnu.org>

        * config/mips/mips.cc (mips_compute_frame_info): If another
        register is used as global_pointer, mark $GP live false.

2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>

        PR target/112973
        * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
        give the section a light copy-editing pass.

2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>

        * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
        * config/aarch64/aarch64-tune.md: Regenerated.
        * doc/invoke.texi (-mcpu): Add cobalt-100 core.

2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>

        PR target/112573
        * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
        badly formed CONST expressions.

2024-01-16  Daniel Cederman  <cederman@gaisler.com>

        * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty

2024-01-16  Daniel Cederman  <cederman@gaisler.com>

        * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
        * config/sparc/sync.md (membar_storeload): Turn into named insn
        and add GR712RC errata workaround.
        (membar_v8): Add GR712RC errata workaround.

2024-01-16  Andreas Larsson  <andreas@gaisler.com>

        * config/sparc/sync.md (*membar_storeload_leon3): Remove
        (*membar_storeload): Enable for LEON

2024-01-16  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113372
        PR middle-end/90348
        PR middle-end/110115
        PR middle-end/111422
        * cfgexpand.cc (add_scope_conflicts_2): New function.
        (add_scope_conflicts_1): Use it.

2024-01-16  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
        (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
        * doc/avr-mmcu.texi: Regenerate.

2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>

        PR tree-optimization/113091
        * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
        (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
        scalar use with new function.
        (vect_bb_slp_mark_live_stmts): New function as entry to existing
        overriden functions with same name.
        (vect_slp_analyze_operations): Call new entry function to mark
        live statements.

2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113404
        * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
        for RVV in big-endian mode.

2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>

        * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
        (riscv_pass_in_vector_p): Delete.
        (riscv_init_cumulative_args): Delete the checking.
        (riscv_get_arg_info): Delete the checking.
        (riscv_function_value): Delete the checking.
        * config/riscv/riscv.h: Delete the member for checking.

2024-01-15  Georg-Johann Lay  <avr@gjlay.de>

        * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.

2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>

        * config.gcc: Include riscv_bitmanip.h.
        * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
        * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
        * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
        (RISCV_BUILTIN_NO_PREFIX): New helper macro.
        * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
        * config/riscv/riscv-ftypes.def (2): New ftypes.
        * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
        (RISCV_BUILTIN_NO_PREFIX): Likewise.
        * config/riscv/riscv_bitmanip.h: New file.

2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>

        * config.gcc: Include riscv_crypto.h.
        * config/riscv/riscv_crypto.h: New file.

2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>

        PR middle-end/113354
        * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
        in the insn if the corresponding operand does not require hard
        register anymore.

2024-01-15  Georg-Johann Lay  <avr@gjlay.de>

        PR target/107201
        * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
        * config/avr/driver-avr.cc (avr_no_devlib): New function.
        (avr_devicespecs_file): Use it to remove -nodevicelib from the
        options for cores only.
        * config/avr/avr-arch.h (avr_get_parch): New prototype.
        * config/avr/avr-devices.cc (avr_get_parch): New function.

2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113247
        * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
        * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
        * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.

2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113281
        * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
        (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
        * config/riscv/riscv-vector-costs.h: New function.

2024-01-15  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113385
        * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
        First redirect, then split the exit edge.

2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
        Remove m_num_vector_iterations.
        * config/riscv/riscv-vector-costs.h: Ditto.

2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>

        PR target/113156
        * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
        (-mbranch-cost): Set "Optimization" flag.

2024-01-15  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113370
        * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
        set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
        set it to just prec % limb_prec.

2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113393
        * config/riscv/vector.md: Fix ternary attributes.

2024-01-14  Georg-Johann Lay  <avr@gjlay.de>

        PR target/112944
        * configure.ac [target=avr]: Check availability of emulations
        avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
        HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
        * configure: Regenerate.
        * config.in: Regenerate.
        * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
        __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
        * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
        * config/avr/avr-arch.h (enum avr_device_specific_features):
        Add AVR_ISA_FLMAP.
        * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
        AVR_ISA_FLMAP.
        * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
        (avr_set_core_architecture): Set avr_arch_index.
        (have_avrxmega2_flmap, have_avrxmega4_flmap)
        (have_avrxmega3_rodata_in_flash): Set new static const bool according
        to configure results.
        (avr_rodata_in_flash_p): New function using them.
        (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
        track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
        (avr_asm_named_section): Track avr_has_rodata_p.
        (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
        and not avr_rodata_in_flash_p ().
        * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
        (LINK_SPEC): Add %(link_rodata_in_ram).
        (LINK_ARCH_SPEC): Remove.
        * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
        (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
        const bool according to configure results.
        (diagnose_mrodata_in_ram): New function.
        (print_mcu): Generate specs with the following changes:
        <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
        need to extend avr/specs.h each time we add a new bell or whistle.
        <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
        -m[no-]rodata-in-ram.
        <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
        <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
        <*cpp>: Add %(cpp_rodata_in_ram).
        <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
        requested.
        <*self_spec>: Add -mflmap or %<mflmap as needed.

2024-01-14  Jeff Law  <jlaw@ventanamicro.com>

        * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
        not the GPR iterator.  Adjust pattern name and mode attribute
        accordingly.

2024-01-13  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113361
        * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
        Fix up determination of the type for > limb_prec constants.

2024-01-12  Georg-Johann Lay  <avr@gjlay.de>

        * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
        Add web-link to the avr-gcc wiki.

2024-01-12  Georg-Johann Lay  <avr@gjlay.de>

        * doc/extend.texi (AVR Variable Attributes) [address]: Remove
        documentation for a version without argument, which is not supported.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
        (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
        (vld1_f16_x4, vld1_f32_x4): New.
        (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
        (vld1_bf16_x4): New.
        (vld1q_types_x4): Updated to use vld1q_x4
        from arm_neon_builtins.def
        * config/arm/arm_neon_builtins.def
        (vld1_x4): Updated entries.
        (vld1q_x4): New entries, but comes from the old vld1_x4
        * config/arm/neon.md
        (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
        (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
        (vld1_f16_x3, vld1_f32_x3): New.
        (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
        (vld1_bf16_x3): New.
        (vld1q_types_x3): Updated to use vld1q_x3 from
        arm_neon_builtins.def
        * config/arm/arm_neon_builtins.def
        (vld1_x3): Updated entries.
        (vld1q_x3): New entries, but comes from the old vld1_x2
        * config/arm/neon.md
        (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
        (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
        (vld1_f16_x2, vld1_f32_x2): New.
        (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
        (vld1_bf16_x2): New.
        (vld1q_types_x2): Updated to use vld1q_x2 from
        arm_neon_builtins.def
        * config/arm/arm_neon_builtins.def
        (vld1_x2): Updated entries.
        (vld1q_x2): New entries, but comes from the old vld1_x2
        * config/arm/neon.md
        (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
        neon_vld1_x2<mode>.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
        (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
        (vst1q_f16_x4, vst1q_f32_x4): New.
        (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
        (vst1q_bf16_x4): New.
        * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
        * config/arm/neon.md
        (neon_vst1q_x4<mode>): New.
        (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
        * config/arm/unspecs.md
        (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
        (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
        (vst1q_f16_x3, vst1q_f32_x3): New.
        (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
        (vst1q_bf16_x3): New.
        * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
        * config/arm/neon.md
        (neon_vst1q_x3<mode>): New.
        (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
        * config/arm/unspecs.md
        (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
        (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
        (vst1q_f16_x2, vst1q_f32_x2): New.
        (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
        (vst1q_bf16_x2): New.
        * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
        * config/arm/neon.md
        (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
        neon_vst1_x2<mode>.
        * config/arm/iterators.md
        (VMEMX2): New mode iterator.
        (VMEMX2_q): New mode attribute.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
        (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
        (vst1_f16_x4, vst1_f32_x4): New.
        (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
        (vst1_bf16_x4): New.
        * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
        * config/arm/neon.md (vst1_x4<mode>): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
        (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
        (vst1_f16_x3, vst1_f32_x3): New.
        (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
        (vst1_bf16_x3): New.
        * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
        * config/arm/neon.md (vst1_x3<mode>): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
        (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
        (vst1_f16_x2, vst1_f32_x2): New.
        (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
        (vst1_bf16_x2): New.
        * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
        * config/arm/neon.md (vst1_x2<mode>): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
        (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
        (vld1q_f16_x4, vld1q_f32_x4): New.
        (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
        (vld1q_bf16_x4): New.
        * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
        * config/arm/neon.md
        (neon_vld1_x4<mode>): New.
        (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
        * config/arm/unspecs.md
        (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
        (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
        (vld1q_f16_x3, vld1q_f32_x3): New.
        (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
        (vld1q_bf16_x3): New.
        * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
        * config/arm/neon.md
        (neon_vld1_x3<mode>): New.
        (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
        * config/arm/unspecs.md
        (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.

2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>

        * config/arm/arm_neon.h
        (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
        (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
        (vld1q_f16_x2, vld1q_f32_x2): New.
        (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
        (vld1q_bf16_x2): New.
        * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
        * config/arm/neon.md (vld1_x2<mode>): New.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113287
        * doc/sourcebuild.texi (check_effective_target_bitint65535): New.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

        * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
        * tree-vect-loop.cc (vect_transform_loop): Likewise.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113178
        * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
        alternate exits.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113237
        * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
        existing LCSSA variable for exit when all exits are early break.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113137
        PR tree-optimization/113136
        PR tree-optimization/113172
        PR tree-optimization/113178
        * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
        Maintain PHIs on inverted loops.
        (vect_do_peeling): Maintain virtual PHIs on inverted loops.
        * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
        latch.
        (vect_create_loop_vinfo): Record all conds instead of only alt ones.

2024-01-12  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113135
        * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
        dependency analysis.

2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>

        * config/rs6000/host-darwin.cc (segv_handler): Use the revised
        diagnostics class member name for abort of error.

2024-01-12  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
        format string to %s argument.

2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
            Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/113182
        * varasm.cc (process_pending_assemble_externals,
        assemble_external_libcall): Use targetm.strip_name_encoding
        before calling get_identifier.

2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/113196
        * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
        New member variable.
        * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
        Declare.
        * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
        * config/aarch64/aarch64-simd.md
        (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
        (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
        zip2 for zero-extends to...
        (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
        instruction.  Fix big-endian handling.
        (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
        (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
        zip1 for zero-extends to...
        (<optab><Vnarrowq><mode>2): ...a split of this instruction.
        Fix big-endian handling.
        (*aarch64_zip1_uxtl): New pattern.
        (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
        (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
        * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
        (aarch64_gen_shareable_zero): Use it.
        (aarch64_split_simd_shift_p): New function.

2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>

        * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
        (function_beg_insn): New macro.
        * function.cc (expand_function_start): Initialize function_beg_insn.

2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/112989
        * config/aarch64/aarch64-sve-builtins.h
        (function_builder::m_overload_names): Replace with...
        * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
        new global.
        (add_overloaded_function): Update accordingly, using get_identifier
        to get a GGC-friendly record of the name.

2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/112989
        * config/aarch64/aarch64-sve-builtins.def: Don't include
        aarch64-sve-builtins-sme.def.
        (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
        * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
        (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
        instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
        requires AARCH64_FL_SME2.
        * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
        AARCH64_FL_SME adjustment here.
        * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
        include SME intrinsics.
        (sme_function_groups): New array.
        (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
        (handle_arm_sme_h): Use sme_function_groups instead of function_groups.

2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113281
        * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
        (struct cpu_vector_cost): Add regmove struct.
        (get_vector_costs): Export as global.
        * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
        (costs::add_stmt_cost): Ditto.
        * config/riscv/riscv.cc (get_common_costs): Export global function.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113334
        * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
        wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
        to determine if number should be extended by all ones rather than zero
        extended.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113330
        * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
        too large size.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113323
        * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
        check for lhs being large/huge _BitInt not in m_names.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113316
        * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
        uninitialized large/huge _BitInt arguments to calls.

2024-01-12  Jakub Jelinek  <jakub@redhat.com>

        * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
        TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
        CEIL (TYPE_PRECISION (t), limb_prec).
        (bitint_large_huge::handle_cast): Likewise.

2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>

        PR sanitizer/113284
        * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
        Use assemble_function_label_final () for Power ELF V1 ABI.
        * output.h (assemble_function_label_final): New function.
        * varasm.cc (assemble_function_label_raw): Use
        assemble_function_label_final ().
        (assemble_function_label_final): New function.

2024-01-12  Richard Biener  <rguenther@suse.de>

        PR middle-end/113344
        * match.pd ((double)float CMP (double)float -> float CMP float):
        Perform result type check only for vectors.
        * fold-const.cc (fold_binary_loc): Likewise.

2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>

        * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
        (usdot_prod<mode>): Ditto.
        (sdot_prod<mode>): Ditto.
        (udot_prod<mode>): Ditto.

2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>

        PR target/113288
        * config/i386/i386-c.cc (ix86_target_macros_internal):
        Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.

2024-01-12  Richard Biener  <rguenther@suse.de>

        PR target/112280
        * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
        Do not generate code when d.testing_p.

2024-01-12  liuhongt  <hongtao.liu@intel.com>

        PR target/113039
        * doc/invoke.texi (fcf-protection=): Update documents.

2024-01-12  Pan Li  <pan2.li@intel.com>

        * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
        comments of predicate func riscv_v_ext_mode_p.

2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>

        * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
                        Modify ABI-name length of vfloat16m8_t

2024-01-12  Li Wei  <liwei@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
        Adjust.

2024-01-12  Li Wei  <liwei@loongson.cn>

        * config/loongarch/loongarch.md (add<mode>3): Removed.
        (*addsi3): New.
        (addsi3): Ditto.
        (adddi3): Ditto.
        (*addsi3_extended): Removed.
        (addsi3_extended): New.

2024-01-11  Jin Ma  <jinma@linux.alibaba.com>

        * config/riscv/thead.md: Add limits for splits.

2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>

        PR middle-end/113322
        * expr.cc (do_store_flag): Don't try single bit tests with
        comparison on vector types.

2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>

        PR tree-optimization/113301
        * match.pd (`1/x`): Delay signed case until late.

2024-01-11  Georg-Johann Lay  <avr@gjlay.de>

        * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
        and -msp8 to...
        (AVR Internal Options): ...this new @subsubsection.

2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>

        PR rtl-optimization/112918
        * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
        (in_class_p): Restrict condition for narrowing class in case of
        allow_all_reload_class_changes_p.
        (process_alt_operands): Try to match operand without and with
        narrowing reg class.  Discourage narrowing the class.  Finish insn
        matching only if there is no class narrowing.
        (curr_insn_transform): Pass true to in_class_p for reg operand win.

2024-01-11  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/112505
        * tree-vect-loop.cc (vectorizable_induction): Reject
        bit-precision induction.

2024-01-11  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113126
        * match.pd ((double)float CMP (double)float -> float CMP float):
        Make sure the boolean type is the same.
        * fold-const.cc (fold_binary_loc): Likewise.

2024-01-11  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/112636
        * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
        estimate_numbers_of_iterations before querying
        get_max_loop_iterations_int.
        (pass_ch::execute): Initialize SCEV and loops appropriately.

2024-01-11  Georg-Johann Lay  <avr@gjlay.de>

        * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
        Reduced Tiny.
        * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
        * doc/extend.texi (AVR Variable Attributes): Improve documentation
        of io, io_low and address attributes.
        * doc/invoke.texi (AVR Options): Add some anchors for external refs.
        * doc/avr-mmcu.texi: Rebuild.

2024-01-11  Yang Yujie  <yangyujie@loongson.cn>

        PR target/113233
        * config/loongarch/genopts/loongarch.opt.in: Mark options with
        the "Save" property.
        * config/loongarch/loongarch.opt: Same.
        * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
        according to la_target.
        * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
        RESTORE} for the la_target structure; Rename option conditions
        to have the same "la_" prefix.
        * config/loongarch/loongarch.h: Same.

2024-01-11  Pan Li  <pan2.li@intel.com>

        * loop-unroll.cc (insert_var_expansion_initialization): Leverage
        MODE_HAS_SIGNED_ZEROS for expansion variable initialization.

2024-01-11  Alex Coplan  <alex.coplan@arm.com>

        PR target/113077
        * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
        fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
        (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
        synthesize these if needed.  Update caller ...
        (ldp_bb_info::fuse_pair): ... here.
        (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
        and either insn is frame-related.
        (find_trailing_add): Punt on frame-related insns.
        * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
        REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.

2024-01-11  YunQiang Su  <syq@gcc.gnu.org>

        * config/mips/mips.cc (mips_start_function_definition):
        Add ATTRIBUTE_UNUSED.

2024-01-11  Richard Biener  <rguenther@suse.de>

        PR middle-end/112740
        * expr.cc (store_constructor): Check the integer vector
        mask has a single bit per element before using sign-extension
        to expand an uniform vector.

2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
        preempt VLS on unknown NITERS loop.

2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>

        * doc/invoke.texi: Add -mevex512.

2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>

        * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
        (*nor<mode>3): Likewise.
        (nor<mode>3): Likewise.
        (*negsi2_extended): New template.
        (*<optab>si3_internal): Likewise.
        (*one_cmplsi2_internal): Likewise.
        (*norsi3_internal): Likewise.
        (*<optab>nsi_internal): Likewise.
        (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
        modified bit operation to make the optimization work.

2024-01-11  liuhongt  <hongtao.liu@intel.com>

        PR target/104401
        * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.

2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
        (get_vector_costs): Ditto.
        (riscv_builtin_vectorization_cost): Ditto.

2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.

2024-01-10  Antoni Boucher  <bouanto@zoho.com>

        PR jit/111396
        * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
        ipa_free_size_summary.
        * ipa-icf.cc (ipa_icf_cc_finalize): New function.
        * ipa-profile.cc (ipa_profile_cc_finalize): New function.
        * ipa-prop.cc (ipa_prop_cc_finalize): New function.
        * ipa-prop.h (ipa_prop_cc_finalize): New function.
        * ipa-sra.cc (ipa_sra_cc_finalize): New function.
        * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
        ipa_sra_cc_finalize): New functions.
        * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
        ipa_prop_cc_finalize, ipa_profile_cc_finalize and
        ipa_sra_cc_finalize
        Include ipa-utils.h.

2024-01-10  Jin Ma  <jinma@linux.alibaba.com>

        * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
        (th_int_get_save_adjustment): Likewise.
        (th_int_adjust_cfi_prologue): Likewise.
        * config/riscv/riscv.cc (BITSET_P): Moved away from here.
        (TH_INT_INTERRUPT): New macro.
        (riscv_expand_prologue): Add the processing of XTheadInt.
        (riscv_expand_epilogue): Likewise.
        * config/riscv/riscv.h (BITSET_P): Moved to here.
        * config/riscv/riscv.md: New unspec.
        * config/riscv/thead.cc (th_int_get_mask): New function.
        (th_int_get_save_adjustment): Likewise.
        (th_int_adjust_cfi_prologue): Likewise.
        * config/riscv/thead.md (th_int_push): New pattern.
        (th_int_pop): new pattern.

2024-01-10  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/112468
        * doc/sourcebuild.texi: Document ifn_copysign.
        * match.pd: Only apply transformation if target supports the IFN.

2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>

        PR tree-optimization/112581
        * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
        mark_ssa_maybe_undefs.
        * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
        variables can not be reassociated.
        (init_range_entry): Check for uninitialized variables too.
        (init_reassoc): Call mark_ssa_maybe_undefs.

2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>

        * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
        Also handle sign extension.

2024-01-10  Alex Coplan  <alex.coplan@arm.com>

        * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
        to 0.
        (-mlate-ldp-fusion): Likewise.

2024-01-10  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113287
        * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
        instead of using BRANCH_EDGE to determine true edge.

2024-01-10  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113078
        * tree-vect-loop.cc (check_reduction_path): Canonicalize
        .COND_SUB to .COND_ADD.

2024-01-10  David Malcolm  <dmalcolm@redhat.com>

        * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
        Handle prefix mappings before calling find_opt.
        (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
        "-fno-"-prefixed command-line option.
        * opts-common.cc (get_option_prefix_remapping): New.
        * opts.h (get_option_prefix_remapping): New decl.

2024-01-10  David Malcolm  <dmalcolm@redhat.com>

        * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
        m_urlifier to pp_output_formatted_text.
        * pretty-print.cc: Add #define of INCLUDE_VECTOR.
        (obstack_append_string): New overload, taking a length.
        (urlify_quoted_string): Pass in an obstack ptr, rather than using
        that of the pp's buffer.  Generalize to handle trailing text in
        the buffer beyond the run of quoted text.
        (class quoting_info): New.
        (on_begin_quote): New.
        (on_end_quote): New.
        (pp_format): Refactor phase 1 and phase 2 quoting support, moving
        it to calls to on_begin_quote and on_end_quote.
        (struct auto_obstack): New.
        (quoting_info::handle_phase_3): New.
        (pp_output_formatted_text): Add urlifier param.  Use it if there
        is deferred urlification.  Delete m_quotes.
        (selftest::pp_printf_with_urlifier): Pass urlifier to
        pp_output_formatted_text.
        (selftest::test_urlification): Update results for the existing
        case of quoted text stradding chunks; add more such test cases.
        * pretty-print.h (class quoting_info): New forward decl.
        (chunk_info::m_quotes): New field.
        (pp_output_formatted_text): Add optional urlifier param.

2024-01-10  David Malcolm  <dmalcolm@redhat.com>

        * pretty-print.cc (selftest::test_pp_format): Add selftest
        coverage for numbered args.

2024-01-10  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113144
        PR tree-optimization/113145
        * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
        Update all BB that the original exits dominated.

2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>

        * dwarf2out.cc (modified_type_die): Extend the support of reverse
        storage order to enumeration types if -gstrict-dwarf is not passed.
        (gen_enumeration_type_die): Add REVERSE parameter and generate the
        DIE immediately after the existing one if it is true.
        (gen_tagged_type_die): Add REVERSE parameter and pass it in the
        call to gen_enumeration_type_die.
        (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
        first recursive call as well as the call to gen_tagged_type_die.
        (gen_type_die): Add REVERSE parameter and pass it in the call to
        gen_type_die_with_usage.

2024-01-10  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113120
        * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
        with root->size TYPE_PRECISION don't build anything new.
        Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
        rather than build_nonstandard_integer_type.

2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>

        * config/i386/i386.opt: Adjust document.
        * doc/invoke.texi: Add description for
        -mapx-inline-asm-use-gpr32.

2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
        (avg<v_double_trunc>3_floor): New pattern.
        (<u>avg<v_double_trunc>3_ceil): Remove.
        (avg<v_double_trunc>3_ceil): New pattern.
        (uavg<mode>3_floor): Ditto.
        (uavg<mode>3_ceil): Ditto.
        * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
        (enum insn_type): Ditto.
        * config/riscv/riscv-v.cc: Ditto.
        * config/riscv/vector-iterators.md (ashiftrt): Remove.
        (ASHIFTRT): Ditto.
        * config/riscv/vector.md: Add VLS modes.

2024-01-10  Kewen Lin  <linkw@linux.ibm.com>

        PR target/111480
        * config/rs6000/vsx.md (VCZLSBB): New int iterator.
        (vczlsbb_char): New int attribute.
        (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
        (vc<vczlsbb_char>zlsbb_<mode>): ... this.
        (*vctzlsbb_zext_<mode>): Rename to ...
        (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
        cover vclzlsbb.

2024-01-10  Kewen Lin  <linkw@linux.ibm.com>

        PR target/112606
        * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
        of the last argument from altivec_register_operand to any_operand.  If
        operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
        otherwise if it doesn't satisfy altivec_register_operand, force it to
        REG using copy_to_mode_reg.

2024-01-10  Kewen Lin  <linkw@linux.ibm.com>

        PR middle-end/113100
        * builtins.cc (expand_builtin_stack_address): Guard stack point
        adjustment with SPARC_STACK_BOUNDARY_HACK.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

        * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
        argument string definitions.
        * config/loongarch/loongarch-str.h: Same.
        * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
        as aliases to -mexplicit-relocs={always,none}
        * config/loongarch/loongarch.opt: Regenerate.
        * config/loongarch/loongarch.cc: Same.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

        * config/loongarch/loongarch-def.h: Define constants with
        enums instead of Macros.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

        * config/loongarch/genopts/loongarch-strings: Rename.
        * config/loongarch/genopts/loongarch.opt.in: Same.
        * config/loongarch/loongarch-cpu.cc: Same.
        * config/loongarch/loongarch-def.cc: Same.
        * config/loongarch/loongarch-def.h: Same.
        * config/loongarch/loongarch-opts.cc: Same.
        * config/loongarch/loongarch-opts.h: Same.
        * config/loongarch/loongarch-str.h: Same.
        * config/loongarch/loongarch.opt: Same.

2024-01-10  Yang Yujie  <yangyujie@loongson.cn>

        * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
        variable with the common la_ prefix.
        * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
        flags as saved using TargetVariable.
        * config/loongarch/loongarch.opt: Same.
        * config/loongarch/loongarch-def.h: Define evolution_set to
        mark changes to the -march default.
        * config/loongarch/loongarch-driver.cc: Same.
        * config/loongarch/loongarch-opts.cc: Same.
        * config/loongarch/loongarch-opts.h: Define and use ISA evolution
        conditions around the la_target structure.
        * config/loongarch/loongarch.cc: Same.
        * config/loongarch/loongarch.md: Same.
        * config/loongarch/loongarch-builtins.cc: Same.
        * config/loongarch/loongarch-c.cc: Same.
        * config/loongarch/lasx.md: Same.
        * config/loongarch/lsx.md: Same.
        * config/loongarch/sync.md: Same.

2024-01-09  Jeff Law  <jlaw@ventanamicro.com>

        * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
        no less.

2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>

        * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.

2024-01-09  Tamar Christina  <tamar.christina@arm.com>

        * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
        restart_loop.
        (vectorizable_live_operation): Likewise.

2024-01-09  Tamar Christina  <tamar.christina@arm.com>

        PR tree-optimization/113199
        * tree-vect-loop.cc (vectorizable_live_operation_1): Use
        BIT_FIELD_REF.

2024-01-09  Jakub Jelinek  <jakub@redhat.com>

        PR target/113270
        * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
        * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
        GTY(()) declaration before the definition, drop GTY(()) drom the
        definition.

2024-01-09  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113026
        * tree-vect-loop-manip.cc (vect_do_peeling): Remove
        redundant and wrong niter bound setting.  Move niter
        bound adjustment down.

2024-01-09  Tamar Christina  <tamar.christina@arm.com>

        PR middle-end/113163
        * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
        Reject non-linear inductions that aren't supported.

2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>

        * config/arc/arc.cc (arc_shift_alg): New enumerated type for
        left shift implementation strategies.
        (arc_shift_info): Type for each entry of the shift strategy table.
        (arc_shift_context_idx): Return a integer value for each code
        generation context, used as an index
        (arc_ashl_alg): Table indexed by context and shifted bit count.
        (arc_split_ashl): Use the arc_ashl_alg table to select SImode
        left shift implementation.
        (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
        provide accurate costs, when optimizing for speed or size.

2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.

2024-01-09  Julian Brown  <julian@codesourcery.com>

        * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
        processed out before gimplification.
        * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
        * tree.def (OMP_ARRAY_SECTION): New tree code.

2024-01-09  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113210
        * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
        value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
        INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
        minus 1.

2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>

        PR rtl-optimization/113140
        * reorg.cc (fill_slots_from_thread): If we are to branch after the
        last instruction of the function, create an end label.

2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
            Hongtao Liu  <hongtao.liu@intel.com>

        PR target/112992
        * config/i386/i386-expand.cc
        (ix86_convert_const_wide_int_to_broadcast): Allow call to
        ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
        (ix86_broadcast_from_constant): Revert recent change; Return a
        suitable MEMREF independently of mode/target combinations.
        (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
        to decide whether expansion is possible/preferrable.  Only try
        forcing DImode constants to memory (and trying again) if calling
        ix86_expand_vector_init_duplicate fails with an DImode immediate
        constant.
        (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
        V4SImode for suitable immediate constants.
        <case E_V4DImode>: Try using V8SImode for suitable constants.
        <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
        <case E_V2HImode>: Likewise.
        <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
        <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
        <label widen>: Handle CONT_INTs via simplify_binary_operation.
        Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
        <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
        <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
        (ix86_expand_vector_init): Move try using a broadcast for all_same
        with ix86_expand_vector_init_duplicate before using constant pool.

2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>

        * doc/invoke.texi (Arm Options): Document Cortex-M52 options.

2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>

        * config/arm/arm-cpus.in (cortex-m52): New cpu.
        * config/arm/arm-tables.opt: Regenerate.
        * config/arm/arm-tune.md: Regenerate.

2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>

        * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
        (vec_init<mode><lasxhalf>): .. this, and extend to mode.
        (@vec_concatz<mode>): New insn pattern.
        * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
        Handle VALS containing two vectors.

2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
        (vundefined): Ditto.

2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>

        * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
                                Add new function_base for crypto vector.
        (class bitmanip): Ditto.
        (class b_reverse):Ditto.
        (class vwsll):   Ditto.
        (class clmul):   Ditto.
        (class vg_nhab):  Ditto.
        (class crypto_vv):Ditto.
        (class crypto_vi):Ditto.
        (class vaeskf2_vsm3c):Ditto.
        (class vsm3me): Ditto.
        (BASE): Add BASE declaration for crypto vector.
        * config/riscv/riscv-vector-builtins-bases.h: Ditto.
        * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
                                Add crypto vector intrinsic definition.
        (vbrev): Ditto.
        (vclz): Ditto.
        (vctz): Ditto.
        (vwsll): Ditto.
        (vandn): Ditto.
        (vbrev8): Ditto.
        (vrev8): Ditto.
        (vrol): Ditto.
        (vror): Ditto.
        (vclmul): Ditto.
        (vclmulh): Ditto.
        (vghsh): Ditto.
        (vgmul): Ditto.
        (vaesef): Ditto.
        (vaesem): Ditto.
        (vaesdf): Ditto.
        (vaesdm): Ditto.
        (vaesz): Ditto.
        (vaeskf1): Ditto.
        (vaeskf2): Ditto.
        (vsha2ms): Ditto.
        (vsha2ch): Ditto.
        (vsha2cl): Ditto.
        (vsm4k): Ditto.
        (vsm4r): Ditto.
        (vsm3me): Ditto.
        (vsm3c): Ditto.
        * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
                                Add new function_shape for crypto vector.
        (struct crypto_vi_def): Ditto.
        (struct crypto_vv_no_op_type_def): Ditto.
        (SHAPE): Add SHAPE declaration of crypto vector.
        * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
        * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
                                Add new data type for crypto vector.
        (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
        (vuint32mf2_t): Ditto.
        (vuint32m1_t): Ditto.
        (vuint32m2_t): Ditto.
        (vuint32m4_t): Ditto.
        (vuint32m8_t): Ditto.
        (vuint64m1_t): Ditto.
        (vuint64m2_t): Ditto.
        (vuint64m4_t): Ditto.
        (vuint64m8_t): Ditto.
        * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
                                Add new data struct for crypto vector.
        (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
        (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
        * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.

2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>

        PR sanitizer/113251
        * varasm.cc (assemble_function_label_raw): Do not call
        asan_function_start () without the current function.

2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>

        PR target/113225
        * btfout.cc (btf_collect_datasec): Skip creating BTF info for
        extern and kernel_helper attributed function decls.

2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>

        * btfout.cc (output_btf_strs): Changed.

2024-01-08  Tobias Burnus  <tobias@codesourcery.com>

        * config/gcn/mkoffload.cc (main): Handle gfx1100
        when setting the default XNACK.

2024-01-08  Tobias Burnus  <tobias@codesourcery.com>

        * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
        * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
        (ASM_SPEC): Handle gfx1100.
        * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
        (enum gcn_isa): Add ISA_RDNA3.
        (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
        * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
        * config/gcn/gcn.cc (gcn_option_override,
        gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
        (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
        TARGET_RDNA2 to TARGET_RDNA2_PLUS.
        (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
        with gfx1100.
        * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
        (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
        __gfx1100__.
        * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
        * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
        * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
        (isa_has_combined_avgprs, main): Handle gfx1100.
        * config/gcn/t-omp-device (isa): Add gfx1100.

2024-01-08  Richard Biener  <rguenther@suse.de>

        * doc/invoke.texi (-mmovbe): Clarify.

2024-01-08  Richard Biener  <rguenther@suse.de>

        PR tree-optimization/113026
        * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
        Avoid an epilog in more cases.
        * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
        epilogues niter upper bounds and estimates.

2024-01-08  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113228
        * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.

2024-01-08  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113120
        * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
        large _BitInt zero INTEGER_CST PHI argument.

2024-01-08  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113119
        * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
        both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
        is before REALPART_EXPR.

2024-01-08  Georg-Johann Lay  <avr@gjlay.de>

        PR target/112952
        * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
        range when diagnosing attribute "io" and "io_low" are out of range.
        (avr_eval_addr_attrib): Don't ICE on empty address at that place.
        (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
        in contexts other than static storage.
        (avr_asm_output_aligned_decl_common): Move output of decls with
        attribute "address", "io", and "io_low" to...
        (avr_output_addr_attrib): ...this new function.
        (avr_asm_asm_output_aligned_bss): Remove output for decls with
        attribute "address", "io", and "io_low".
        (avr_encode_section_info): Rectify handling of decls with attribute
        "address", "io", and "io_low".

2024-01-08  Andrew Stubbs  <ams@codesourcery.com>

        * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
        (elf_flags): Remove XNACK from the default value.
        (main): Set a default XNACK according to the arch.

2024-01-08  Andrew Stubbs  <ams@codesourcery.com>

        * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
        (process_asm): Don't count avgprs.

2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>

        * config/i386/i386.opt: Add supported sub-features.
        * doc/extend.texi: Add description for target attribute.

2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>

        * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.

2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
            Uros Bizjak  <ubizjak@gmail.com>

        PR target/113231
        * config/i386/i386-features.cc (compute_convert_gain): Include
        the overhead of explicit load and store (movd) instructions when
        converting non-store scalar operations with memory destinations.
        Various indentation whitespace fixes.

2024-01-07  Tamar Christina  <tamar.christina@arm.com>

        * config/arm/neon.md (cbranch<mode>4): New.

2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.

2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>

        * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.

2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113248
        * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
        Update the MAX_SEW.

2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
        (variable_vectorized_p): Teach loop invariant.
        (has_unexpected_spills_p): Ditto.

2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
        * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
        * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.

2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>

        PR target/113104
        * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
        (aarch64-vect-compare-costs): ...this.
        * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
        Replace with...
        (-param=aarch64-vect-compare-costs=): ...this new param.
        * config/aarch64/aarch64.cc (aarch64_override_options_internal):
        Don't disable it when vectorizing for Advanced SIMD only.
        (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
        whenever aarch64_vect_compare_costs is true.

2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>

        * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
        Modify the method of determining the memory offset of [x]vld/[x]vst.
        (lasx_mxst_<lasxfmt_f>): Likewise.
        * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
        (loongarch_address_insns): Likewise.
        * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
        (lsx_st_<lsxfmt_f>): Likewise.
        * config/loongarch/predicates.md (aq10b_operand): Likewise.
        (aq10h_operand): Likewise.
        (aq10w_operand): Likewise.
        (aq10d_operand): Likewise.

2024-01-05  Alex Coplan  <alex.coplan@arm.com>

        PR target/113217
        * config/aarch64/aarch64-ldp-fusion.cc
        (ldp_bb_info::try_fuse_pair): If the second access can throw,
        narrow the move range to exactly that insn.

2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>

        * asan.cc (asan_function_start): Drop switch_to_section ().
        (asan_emit_stack_protection): Set .LASANPC alignment.
        * config/i386/i386.cc: Use assemble_function_label_raw ()
        instead of ASM_OUTPUT_LABEL ().
        * config/s390/s390.cc (s390_asm_output_function_label):
        Likewise.
        * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
        * final.cc (final_start_function_1): Drop
        asan_function_start ().
        * output.h (assemble_function_label_raw): New function.
        * varasm.cc (assemble_function_label_raw): Likewise.

2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>

        * config/aarch64/aarch64.cc (aarch64_declare_function_name):
        Use ASM_OUTPUT_FUNCTION_LABEL ().
        * config/alpha/alpha.cc (alpha_start_function): Likewise.
        * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
        * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
        * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
        * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
        * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
        * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
        * config/ia64/ia64.cc (ia64_start_function): Likewise.
        * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
        Likewise.
        * config/microblaze/microblaze.cc (microblaze_function_prologue):
        Likewise.
        * config/mips/mips.cc (mips_start_unique_function): Return the
        tree.
        (mips_start_function_definition): Use
        ASM_OUTPUT_FUNCTION_LABEL ().
        (mips_finish_stub): Pass the tree to
        mips_start_function_definition ().
        (mips16_build_function_stub): Likewise.
        (mips16_build_call_stub): Likewise.
        (mips_output_function_prologue): Likewise.
        * config/pa/pa.cc (pa_output_function_label): Use
        ASM_OUTPUT_FUNCTION_LABEL ().
        * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
        * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
        Likewise.
        (rs6000_xcoff_declare_function_name): Likewise.

2024-01-05  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/113201
        * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
        replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.

2024-01-05  Jakub Jelinek  <jakub@redhat.com>

        PR tree-optimization/90693
        * tree-ssa-math-opts.cc (match_single_bit_test): If
        tree_expr_nonzero_p (arg), remember it in the second argument to
        IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
        arg ^ (arg - 1) > arg - 1.
        * internal-fn.cc (expand_POPCOUNT): If second argument to
        IFN_POPCOUNT suggests arg is non-zero, try to expand it as
        arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.

2024-01-05  Kito Cheng  <kito.cheng@sifive.com>

        * config/riscv/riscv-v.cc (expand_load_store):
        Remove `value`.
        (expand_cond_len_op): Ditto.
        (expand_gather_scatter): Ditto.
        (expand_lanes_load_store): Ditto.
        (expand_fold_extract_last): Ditto.

2024-01-05  Pan Li  <pan2.li@intel.com>

        Revert:
        2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>

        * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
                                Add new function_base for crypto vector.
        (class bitmanip): Ditto.
        (class b_reverse):Ditto.
        (class vwsll):   Ditto.
        (class clmul):   Ditto.
        (class vg_nhab):  Ditto.
        (class crypto_vv):Ditto.
        (class crypto_vi):Ditto.
        (class vaeskf2_vsm3c):Ditto.
        (class vsm3me): Ditto.
        (BASE): Add BASE declaration for crypto vector.
        * config/riscv/riscv-vector-builtins-bases.h: Ditto.
        * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
                                Add crypto vector intrinsic definition.
        (vbrev): Ditto.
        (vclz): Ditto.
        (vctz): Ditto.
        (vwsll): Ditto.
        (vandn): Ditto.
        (vbrev8): Ditto.
        (vrev8): Ditto.
        (vrol): Ditto.
        (vror): Ditto.
        (vclmul): Ditto.
        (vclmulh): Ditto.
        (vghsh): Ditto.
        (vgmul): Ditto.
        (vaesef): Ditto.
        (vaesem): Ditto.
        (vaesdf): Ditto.
        (vaesdm): Ditto.
        (vaesz): Ditto.
        (vaeskf1): Ditto.
        (vaeskf2): Ditto.
        (vsha2ms): Ditto.
        (vsha2ch): Ditto.
        (vsha2cl): Ditto.
        (vsm4k): Ditto.
        (vsm4r): Ditto.
        (vsm3me): Ditto.
        (vsm3c): Ditto.
        * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
                                Add new function_shape for crypto vector.
        (struct crypto_vi_def): Ditto.
        (struct crypto_vv_no_op_type_def): Ditto.
        (SHAPE): Add SHAPE declaration of crypto vector.
        * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
        * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
                                Add new data type for crypto vector.
        (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
        (vuint32mf2_t): Ditto.
        (vuint32m1_t): Ditto.
        (vuint32m2_t): Ditto.
        (vuint32m4_t): Ditto.
        (vuint32m8_t): Ditto.
        (vuint64m1_t): Ditto.
        (vuint64m2_t): Ditto.
        (vuint64m4_t): Ditto.
        (vuint64m8_t): Ditto.
        * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
                                Add new data struct for crypto vector.
        (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
        (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
        * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.

2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>

        * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
                                Add new function_base for crypto vector.
        (class bitmanip): Ditto.
        (class b_reverse):Ditto.
        (class vwsll):   Ditto.
        (class clmul):   Ditto.
        (class vg_nhab):  Ditto.
        (class crypto_vv):Ditto.
        (class crypto_vi):Ditto.
        (class vaeskf2_vsm3c):Ditto.
        (class vsm3me): Ditto.
        (BASE): Add BASE declaration for crypto vector.
        * config/riscv/riscv-vector-builtins-bases.h: Ditto.
        * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
                                Add crypto vector intrinsic definition.
        (vbrev): Ditto.
        (vclz): Ditto.
        (vctz): Ditto.
        (vwsll): Ditto.
        (vandn): Ditto.
        (vbrev8): Ditto.
        (vrev8): Ditto.
        (vrol): Ditto.
        (vror): Ditto.
        (vclmul): Ditto.
        (vclmulh): Ditto.
        (vghsh): Ditto.
        (vgmul): Ditto.
        (vaesef): Ditto.
        (vaesem): Ditto.
        (vaesdf): Ditto.
        (vaesdm): Ditto.
        (vaesz): Ditto.
        (vaeskf1): Ditto.
        (vaeskf2): Ditto.
        (vsha2ms): Ditto.
        (vsha2ch): Ditto.
        (vsha2cl): Ditto.
        (vsm4k): Ditto.
        (vsm4r): Ditto.
        (vsm3me): Ditto.
        (vsm3c): Ditto.
        * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
                                Add new function_shape for crypto vector.
        (struct crypto_vi_def): Ditto.
        (struct crypto_vv_no_op_type_def): Ditto.
        (SHAPE): Add SHAPE declaration of crypto vector.
        * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
        * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
                                Add new data type for crypto vector.
        (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
        (vuint32mf2_t): Ditto.
        (vuint32m1_t): Ditto.
        (vuint32m2_t): Ditto.
        (vuint32m4_t): Ditto.
        (vuint32m8_t): Ditto.
        (vuint64m1_t): Ditto.
        (vuint64m2_t): Ditto.
        (vuint64m4_t): Ditto.
        (vuint64m8_t): Ditto.
        * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
                                Add new data struct for crypto vector.
        (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
        (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
        * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.

2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>

        PR tree-optimization/113186
        * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
        Match `^` with the `==` for 1bit integral types.
        * match.pd (maybe_cmp): Allow for bit_xor for 1bit
        integral types.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

        * toplev.cc (general_init): Pass lang_mask to urlifier.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

        * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
        param.
        (diagnostic_context::make_option_url): Update for lang_mask param.
        * gcc-urlifier.cc: Include "opts.h" and "options.h".
        (gcc_urlifier::gcc_urlifier): Add lang_mask param.
        (gcc_urlifier::m_lang_mask): New field.
        (doc_urls): Make static.
        (gcc_urlifier::get_url_for_quoted_text): Use label_text.
        (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
        Look for an option by name before trying a binary search in
        doc_urls.
        (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
        (gcc_urlifier::get_url_suffix_for_option): New.
        (make_gcc_urlifier): Add lang_mask param.
        (selftest::gcc_urlifier_cc_tests): Update for above changes.
        Verify that a URL is found for "-fpack-struct".
        * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
        * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
        * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
        to make_gcc_urlifier.
        * opts-diagnostic.h (get_option_url): Add lang_mask param.
        * opts.cc (get_option_html_page): Remove special-casing for
        analyzer and LTO.
        (get_option_url_suffix): New.
        (get_option_url): Reimplement.
        (selftest::test_get_option_html_page): Rename to...
        (selftest::test_get_option_url_suffix): ...this and update for
        above changes.
        (selftest::opts_cc_tests): Update for renaming.
        * opts.h: Include "rich-location.h".
        (get_option_url_suffix): New decl.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

        * Makefile.in (ALL_OPT_URL_FILES): New.
        (GCC_OBJS): Add options-urls.o.
        (OBJS): Likewise.
        (OBJS-libcommon): Likewise.
        (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
        inputs to opt-gather.awk.
        (options-urls.cc): New Makefile target.
        * opt-functions.awk (url_suffix): New function.
        (lang_url_suffix): New function.
        * options-urls-cc-gen.awk: New file.
        * opts.h (get_opt_url_suffix): New decl.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

        * params.opt.urls: New file, autogenerated by
        regenerate-opt-urls.py.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

        * common.opt.urls: New file, autogenerated by
        regenerate-opt-urls.py.
        * config/aarch64/aarch64.opt.urls: Likewise.
        * config/alpha/alpha.opt.urls: Likewise.
        * config/alpha/elf.opt.urls: Likewise.
        * config/arc/arc-tables.opt.urls: Likewise.
        * config/arc/arc.opt.urls: Likewise.
        * config/arm/arm-tables.opt.urls: Likewise.
        * config/arm/arm.opt.urls: Likewise.
        * config/arm/vxworks.opt.urls: Likewise.
        * config/avr/avr.opt.urls: Likewise.
        * config/bpf/bpf.opt.urls: Likewise.
        * config/c6x/c6x-tables.opt.urls: Likewise.
        * config/c6x/c6x.opt.urls: Likewise.
        * config/cris/cris.opt.urls: Likewise.
        * config/cris/elf.opt.urls: Likewise.
        * config/csky/csky.opt.urls: Likewise.
        * config/csky/csky_tables.opt.urls: Likewise.
        * config/darwin.opt.urls: Likewise.
        * config/dragonfly.opt.urls: Likewise.
        * config/epiphany/epiphany.opt.urls: Likewise.
        * config/fr30/fr30.opt.urls: Likewise.
        * config/freebsd.opt.urls: Likewise.
        * config/frv/frv.opt.urls: Likewise.
        * config/ft32/ft32.opt.urls: Likewise.
        * config/fused-madd.opt.urls: Likewise.
        * config/g.opt.urls: Likewise.
        * config/gcn/gcn.opt.urls: Likewise.
        * config/gnu-user.opt.urls: Likewise.
        * config/h8300/h8300.opt.urls: Likewise.
        * config/hpux11.opt.urls: Likewise.
        * config/i386/cygming.opt.urls: Likewise.
        * config/i386/cygwin.opt.urls: Likewise.
        * config/i386/djgpp.opt.urls: Likewise.
        * config/i386/i386.opt.urls: Likewise.
        * config/i386/mingw-w64.opt.urls: Likewise.
        * config/i386/mingw.opt.urls: Likewise.
        * config/i386/nto.opt.urls: Likewise.
        * config/ia64/ia64.opt.urls: Likewise.
        * config/ia64/ilp32.opt.urls: Likewise.
        * config/ia64/vms.opt.urls: Likewise.
        * config/iq2000/iq2000.opt.urls: Likewise.
        * config/linux-android.opt.urls: Likewise.
        * config/linux.opt.urls: Likewise.
        * config/lm32/lm32.opt.urls: Likewise.
        * config/loongarch/loongarch.opt.urls: Likewise.
        * config/lynx.opt.urls: Likewise.
        * config/m32c/m32c.opt.urls: Likewise.
        * config/m32r/m32r.opt.urls: Likewise.
        * config/m68k/ieee.opt.urls: Likewise.
        * config/m68k/m68k-tables.opt.urls: Likewise.
        * config/m68k/m68k.opt.urls: Likewise.
        * config/m68k/uclinux.opt.urls: Likewise.
        * config/mcore/mcore.opt.urls: Likewise.
        * config/microblaze/microblaze.opt.urls: Likewise.
        * config/mips/mips-tables.opt.urls: Likewise.
        * config/mips/mips.opt.urls: Likewise.
        * config/mips/sde.opt.urls: Likewise.
        * config/mmix/mmix.opt.urls: Likewise.
        * config/mn10300/mn10300.opt.urls: Likewise.
        * config/moxie/moxie.opt.urls: Likewise.
        * config/msp430/msp430.opt.urls: Likewise.
        * config/nds32/nds32-elf.opt.urls: Likewise.
        * config/nds32/nds32-linux.opt.urls: Likewise.
        * config/nds32/nds32.opt.urls: Likewise.
        * config/netbsd-elf.opt.urls: Likewise.
        * config/netbsd.opt.urls: Likewise.
        * config/nios2/elf.opt.urls: Likewise.
        * config/nios2/nios2.opt.urls: Likewise.
        * config/nvptx/nvptx-gen.opt.urls: Likewise.
        * config/nvptx/nvptx.opt.urls: Likewise.
        * config/openbsd.opt.urls: Likewise.
        * config/or1k/elf.opt.urls: Likewise.
        * config/or1k/or1k.opt.urls: Likewise.
        * config/pa/pa-hpux.opt.urls: Likewise.
        * config/pa/pa-hpux1010.opt.urls: Likewise.
        * config/pa/pa-hpux1111.opt.urls: Likewise.
        * config/pa/pa-hpux1131.opt.urls: Likewise.
        * config/pa/pa.opt.urls: Likewise.
        * config/pa/pa64-hpux.opt.urls: Likewise.
        * config/pdp11/pdp11.opt.urls: Likewise.
        * config/pru/pru.opt.urls: Likewise.
        * config/riscv/riscv.opt.urls: Likewise.
        * config/rl78/rl78.opt.urls: Likewise.
        * config/rpath.opt.urls: Likewise.
        * config/rs6000/476.opt.urls: Likewise.
        * config/rs6000/aix64.opt.urls: Likewise.
        * config/rs6000/darwin.opt.urls: Likewise.
        * config/rs6000/linux64.opt.urls: Likewise.
        * config/rs6000/rs6000-tables.opt.urls: Likewise.
        * config/rs6000/rs6000.opt.urls: Likewise.
        * config/rs6000/sysv4.opt.urls: Likewise.
        * config/rtems.opt.urls: Likewise.
        * config/rx/elf.opt.urls: Likewise.
        * config/rx/rx.opt.urls: Likewise.
        * config/s390/s390.opt.urls: Likewise.
        * config/s390/tpf.opt.urls: Likewise.
        * config/sh/sh.opt.urls: Likewise.
        * config/sh/superh.opt.urls: Likewise.
        * config/sol2.opt.urls: Likewise.
        * config/sparc/long-double-switch.opt.urls: Likewise.
        * config/sparc/sparc.opt.urls: Likewise.
        * config/stormy16/stormy16.opt.urls: Likewise.
        * config/v850/v850.opt.urls: Likewise.
        * config/vax/elf.opt.urls: Likewise.
        * config/vax/vax.opt.urls: Likewise.
        * config/visium/visium.opt.urls: Likewise.
        * config/vms/vms.opt.urls: Likewise.
        * config/vxworks-smp.opt.urls: Likewise.
        * config/vxworks.opt.urls: Likewise.
        * config/xtensa/elf.opt.urls: Likewise.
        * config/xtensa/uclinux.opt.urls: Likewise.
        * config/xtensa/xtensa.opt.urls: Likewise.
        * config/bfin/bfin.opt.urls: New file.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

        * Makefile.in (OPT_URLS_HTML_DEPS): New.
        (regenerate-opt-urls): New target.
        (regenerate-opt-urls-unit-test): New target.
        * doc/options.texi (Option properties): Add UrlSuffix and
        description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
        * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
        reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
        and Makefile.in's OPT_URLS_HTML_DEPS.
        (Anatomy of a Target Back End): Add
        reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
        * regenerate-opt-urls.py: New file.

2024-01-04  David Malcolm  <dmalcolm@redhat.com>

        * diagnostic-format-sarif.cc
        (sarif_builder::make_logical_location_object): Convert to...
        (make_sarif_logical_location_object): ...this.
        (sarif_builder::set_any_logical_locs_arr): Update for above
        change.
        (sarif_builder::make_thread_flow_location_object): Call
        maybe_add_sarif_properties on each diagnostic_event.
        * diagnostic-format-sarif.h (class logical_location): New forward
        decl.
        (make_sarif_logical_location_object): New decl.
        * diagnostic-path.h (class sarif_object): New forward decl.
        (diagnostic_event::maybe_add_sarif_properties): New vfunc.

2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
            Patrick Lin  <patrick@andestech.com>
            Rufus Chen  <rufus@andestech.com>
            Monk Chiang  <monk.chiang@sifive.com>

        * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
        with Nan-boxing value.
        * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.

2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
            Jeff Law  <jlaw@ventanamicro.com>

        PR rtl-optimization/104914
        * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
        a sign or zero extension is only required if the modified field
        overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
        targets, don't refer to the temporarily incorrectly extended value
        using a SUBREG, but instead generate an explicit TRUNCATE rtx.

2024-01-04  Pan Li  <pan2.li@intel.com>

        Revert:
        2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.

2024-01-04  Kito Cheng  <kito.cheng@sifive.com>

        * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
        offset of fcsr.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
        (compute_nregs_for_mode): Refine LMUL.
        (max_number_of_live_regs): Ditto.
        (compute_estimated_lmul): Ditto.
        (has_unexpected_spills_p): Ditto.

2024-01-04  Li Wei  <liwei@loongson.cn>

        * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
        Remove useless forward declaration.
        (loongarch_is_even_extraction): Remove useless forward declaration.
        (loongarch_try_expand_lsx_vshuf_const): Removed.
        (loongarch_expand_vec_perm_const_1): Merged.
        (loongarch_is_double_duplicate): Removed.
        (loongarch_is_center_extraction): Ditto.
        (loongarch_is_reversing_permutation): Ditto.
        (loongarch_is_di_misalign_extract): Ditto.
        (loongarch_is_si_misalign_extract): Ditto.
        (loongarch_is_lasx_lowpart_extract): Ditto.
        (loongarch_is_op_reverse_perm): Ditto.
        (loongarch_is_single_op_perm): Ditto.
        (loongarch_is_divisible_perm): Ditto.
        (loongarch_is_triple_stride_extract): Ditto.
        (loongarch_expand_vec_perm_const_2): Merged.
        (loongarch_expand_vec_perm_const): New.
        (loongarch_vectorize_vec_perm_const): Adjust.

2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>

        * omp-general.cc: Fix comment typos and misplaced/confusing
        comments.  Delete redundant include of omp-general.h.

2024-01-04  YunQiang Su  <syq@gcc.gnu.org>

        PR rtl-optimization/104914
        * config/mips/mips.md (insqisi_extended): New patterns.
        (inshisi_extended): Ditto.

2024-01-04  YunQiang Su  <syq@gcc.gnu.org>

        * config/mips/mips.cc (mips_insn_cost): New function.

2024-01-04  YunQiang Su  <syq@gcc.gnu.org>

        * config/mips/mips.md (perf_ratio): New attribute.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113206
        PR target/113209
        * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
        (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
        blocks belong to infinite loop.
        (pre_vsetvl::emit_vsetvl): Remove fake edges.
        * config/riscv/t-riscv: Add a new include file.

2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/vector.md: Fix indent.

2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>

        * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
        OMP_CLAUSE__SIMDUID_.
        * tree.cc (omp_clause_num_ops): Update position of entry for
        OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
        (omp_clause_code_name): Likewise.

2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>

        * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
        printing of FUNC_MAP/IND_FUNC_MAP labels.

2024-01-03  Jakub Jelinek  <jakub@redhat.com>

        * gcc.cc (process_command): Update copyright notice dates.
        * gcov-dump.cc (print_version): Ditto.
        * gcov.cc (print_version): Ditto.
        * gcov-tool.cc (print_version): Ditto.
        * gengtype.cc (create_file): Ditto.
        * doc/cpp.texi: Bump @copying's copyright year.
        * doc/cppinternals.texi: Ditto.
        * doc/gcc.texi: Ditto.
        * doc/gccint.texi: Ditto.
        * doc/gcov.texi: Ditto.
        * doc/install.texi: Ditto.
        * doc/invoke.texi: Ditto.

2024-01-03  Xi Ruoyao  <xry111@xry111.site>

        * config/loongarch/simd.md (fmax<mode>3): New define_insn.
        (fmin<mode>3): Likewise.
        (reduc_fmax_scal_<mode>3): New define_expand.
        (reduc_fmin_scal_<mode>3): Likewise.

2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113112
        * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
        (max_number_of_live_regs): Ditto.
        (has_unexpected_spills_p): Ditto.

2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
            Jin Ma  <jinma@linux.alibaba.com>
            Xianmiao Qu  <cooper.qu@linux.alibaba.com>
            Christoph Müllner  <christoph.muellner@vrull.eu>

        * config/riscv/vector.md:
        Use vector_length_operand for vsetvl patterns.

2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
        (expand_cond_len_op): Add simplification of dummy len and dummy mask.

2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>

        * config/aarch64/aarch64-tuning-flags.def
        (AARCH64_EXTRA_TUNING_OPTION): New tuning option
        AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
        * config/aarch64/aarch64.cc
        (aarch64_override_options_internal): Set
        param_fully_pipelined_fma according to tuning option.
        * config/aarch64/tuning_models/ampere1.h: Add
        AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
        * config/aarch64/tuning_models/ampere1a.h: Likewise.
        * config/aarch64/tuning_models/ampere1b.h: Likewise.

2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>

        * config/riscv/vector-crypto.md: Modify copyright year.

2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.

2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>

        * config.in: Regenerate.
        * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
        * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
        Added TLS Le Relax support.
        (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
        * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
        * configure: Regenerate.
        * configure.ac: Check if binutils supports TLS le relax.

2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>

        * config/riscv/iterators.md: Add rotate insn name.
        * config/riscv/riscv.md: Add new insns name for crypto vector.
        * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
        * config/riscv/vector.md: Add the corresponding attr for crypto vector.
        * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.

2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>

        PR target/113112
        * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
        pointer type liveness count.
\f
Copyright (C) 2024 Free Software Foundation, Inc.

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are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.