gcc/ChangeLog

   1 2024-03-23  John David Anglin  <danglin@gcc.gnu.org>
   2
   3         * config/pa/pa.cc (pa_output_global_address): Handle
   4         UNSPEC_DLTIND14R addresses.
   5         * config/pa/pa.h (PRINT_OPERAND_ADDRESS): Output "RT'" for
   6         UNSPEC_DLTIND14R address.
   7
   8 2024-03-23  Jakub Jelinek  <jakub@redhat.com>
   9
  10         PR tree-optimization/114433
  11         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
  12         m_bitfld_load check save_first rather than m_first.
  13
  14 2024-03-23  Jakub Jelinek  <jakub@redhat.com>
  15
  16         PR tree-optimization/114425
  17         * gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Handle
  18         _Complex large/huge _BitInt types like the large/huge _BitInt types.
  19
  20 2024-03-23  Jakub Jelinek  <jakub@redhat.com>
  21
  22         PR middle-end/111683
  23         * tree-predcom.cc (pcom_worker::suitable_component_p): If has_write
  24         and comp_step is RS_NONZERO, return false if any reference in the
  25         component doesn't have DR_STEP a multiple of access size.
  26
  27 2024-03-23  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
  28
  29         * config/xtensa/xtensa.md: Add new split pattern described above.
  30
  31 2024-03-22  Georg-Johann Lay  <avr@gjlay.de>
  32
  33         * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
  34         for deprecated SIGNAL and INTERRUPT usage without respective header.
  35
  36 2024-03-22  Andrew Stubbs  <ams@baylibre.com>
  37
  38         * config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
  39         (atomic_load<mode>): Adjust RDNA cache settings.
  40         (atomic_store<mode>): Likewise.
  41         (atomic_exchange<mode>): Likewise.
  42
  43 2024-03-22  Andrew Stubbs  <ams@baylibre.com>
  44
  45         * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
  46         RDNA devices.
  47
  48 2024-03-22  Andrew Stubbs  <ams@baylibre.com>
  49
  50         * config.gcc (amdgcn): Add gfx1103 entries.
  51         * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
  52         (gcn_local_sym_hash): Likewise.
  53         * config/gcn/gcn-opts.h (enum processor_type): Likewise.
  54         (TARGET_GFX1103): New macro.
  55         * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
  56         (gcn_omp_device_kind_arch_isa): Likewise.
  57         (output_file_start): Likewise.
  58         (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
  59         * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
  60         * config/gcn/gcn.opt: Add gfx1103.
  61         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
  62         (main): Handle gfx1103.
  63         * config/gcn/t-omp-device: Add gfx1103 isa.
  64         * doc/install.texi (amdgcn): Add gfx1103.
  65         * doc/invoke.texi (-march): Likewise.
  66
  67 2024-03-22  Andrew Stubbs  <ams@baylibre.com>
  68
  69         * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
  70         bitmasks.
  71         (do_compare_and_jump): Remove now-redundant similar code.
  72         * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
  73         bitmasks.
  74         (add_mask_and_len_args): Likewise.
  75
  76 2024-03-22  Pan Li  <pan2.li@intel.com>
  77
  78         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
  79         macro __riscv_v_fixed_vlen when zvl.
  80         * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
  81         New static func to take care of the RVV types decorated by
  82         the attributes.
  83
  84 2024-03-22  Andrew Pinski  <quic_apinski@quicinc.com>
  85
  86         PR c/109619
  87         * builtins.cc (fold_builtin_1): Use error_operand_p
  88         instead of checking against ERROR_MARK.
  89         (fold_builtin_2): Likewise.
  90         (fold_builtin_3): Likewise.
  91
  92 2024-03-22  Jakub Jelinek  <jakub@redhat.com>
  93
  94         PR sanitizer/111736
  95         * ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
  96         SANITIZE_NULL instrumentation for non-generic address spaces
  97         for which targetm.addr_space.zero_address_valid (as) is true.
  98
  99 2024-03-22  Jakub Jelinek  <jakub@redhat.com>
 100
 101         PR tree-optimization/114405
 102         * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
 103         Set rprec to limb_prec rather than 0 if tprec is divisible by
 104         limb_prec.  In the last bf_cur handling, set rprec to (tprec + bo_bit)
 105         % limb_prec rather than tprec % limb_prec and use just rprec instead
 106         of rprec + bo_bit.  For build_bit_field_ref offset, divide
 107         (tprec + bo_bit) by limb_prec rather than just tprec.
 108
 109 2024-03-22  Christoph Müllner  <christoph.muellner@vrull.eu>
 110
 111         PR target/114194
 112         * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
 113         Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.
 114
 115 2024-03-22  Jeff Law  <jlaw@ventanamicro.com>
 116
 117         * config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
 118         tie for scalable and final stack adjustment if needed.
 119         Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
 120
 121 2024-03-22  Pan Li  <pan2.li@intel.com>
 122
 123         PR target/114352
 124         * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
 125         New struct for func decl and target name.
 126         (struct riscv_func_target_hasher): New hasher for hash table mapping
 127         from the fn_decl to fn_target_name.
 128         (riscv_func_decl_hash): New func to compute the hash for fn_decl.
 129         (riscv_func_target_hasher::hash): New func to impl hash interface.
 130         (riscv_func_target_hasher::equal): New func to impl equal interface.
 131         (riscv_cmdline_subset_list): New static var for cmdline subset list.
 132         (riscv_func_target_table_lazy_init): New func to lazy init the func
 133         target hash table.
 134         (riscv_func_target_get): New func to get target name from hash table.
 135         (riscv_func_target_put): New func to put target name into hash table.
 136         (riscv_func_target_remove_and_destory): New func to remove target
 137         info from the hash table and destory it.
 138         (riscv_parse_arch_string): Set the static var cmdline_subset_list.
 139         * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
 140         var for cmdline subset list.
 141         (riscv_func_target_get): New func decl.
 142         (riscv_func_target_put): Ditto.
 143         (riscv_func_target_remove_and_destory): Ditto.
 144         * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
 145         Take cmdline_subset_list instead of current_subset_list when clone.
 146         (riscv_process_target_attr): Record the func target info to hash table.
 147         (riscv_option_valid_attribute_p): Add new arg tree fndel.
 148         * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
 149         func target info and print the arch message.
 150
 151 2024-03-22  Pan Li  <pan2.li@intel.com>
 152
 153         PR target/114352
 154         * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
 155         Replace implied, combine and check to func finalize.
 156         (riscv_subset_list::finalize): New func impl to take care of
 157         implied, combine ext and related checks.
 158         * config/riscv/riscv-subset.h: Add func decl for finalize.
 159         * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
 160         Finalize the ext before return succeed.
 161         * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
 162         machine mode before when set cur function.
 163
 164 2024-03-21  Andrew Stubbs  <ams@baylibre.com>
 165
 166         * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
 167
 168 2024-03-21  Andrew Stubbs  <ams@baylibre.com>
 169
 170         * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
 171
 172 2024-03-21  Andrew Stubbs  <ams@baylibre.com>
 173
 174         * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
 175         device_malloc call.
 176
 177 2024-03-21  liuhongt  <hongtao.liu@intel.com>
 178
 179         PR tree-optimization/114396
 180         * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
 181         and true to wi::from_mpz.
 182
 183 2024-03-21  Richard Biener  <rguenther@suse.de>
 184
 185         PR tree-optimization/111736
 186         * asan.cc (instrument_derefs): Do not instrument accesses
 187         to non-generic address-spaces.
 188
 189 2024-03-21  Richard Biener  <rguenther@suse.de>
 190
 191         PR tree-optimization/113727
 192         * tree-sra.cc (analyze_access_subtree): Do not allow
 193         replacements in subtrees when grp_partial_lhs.
 194
 195 2024-03-21  liuhongt  <hongtao.liu@intel.com>
 196
 197         PR middle-end/114347
 198         * doc/invoke.texi: Document -fexcess-precision=16.
 199
 200 2024-03-20  Cupertino Miranda  <cupertino.miranda@oracle.com>
 201
 202         * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
 203         field contains a DECL_NAME.
 204
 205 2024-03-20  Cupertino Miranda  <cupertino.miranda@oracle.com>
 206
 207         * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
 208         Add assert to validate the string is set.
 209         * config/bpf/core-builtins.cc (cr_final): Make string struct
 210         field as const.
 211         (process_enum_value): Correct for field type change.
 212         (process_type): Set access string to "0".
 213
 214 2024-03-20  Cupertino Miranda  <cupertino.miranda@oracle.com>
 215
 216         * config/bpf/core-builtins.cc (core_field_info): Add
 217         support for POINTER_PLUS_EXPR in the root of the field expression.
 218         (bpf_core_get_index): Likewise.
 219         (pack_field_expr): Make the BTF type to point to the structure
 220         related node, instead of its pointer type.
 221         (make_core_safe_access_index): Correct to new code.
 222
 223 2024-03-20  Xi Ruoyao  <xry111@xry111.site>
 224
 225         PR target/114407
 226         * config/loongarch/loongarch-opts.cc (loongarch_config_target):
 227         Fix typo in diagnostic message, enabing -> enabling.
 228
 229 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 230
 231         PR target/114175
 232         * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
 233         TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
 234         if arg.type is NULL.
 235
 236 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 237
 238         PR target/114175
 239         * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
 240         nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 241         if arg.type is NULL.
 242
 243 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 244
 245         PR target/114175
 246         * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
 247         function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 248         if arg.type is NULL.
 249
 250 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 251
 252         PR target/114175
 253         * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
 254         function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 255         if arg.type is NULL.
 256
 257 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 258
 259         PR target/114175
 260         * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
 261         function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 262         if arg.type is NULL.
 263
 264 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 265
 266         PR target/114175
 267         * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
 268         skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 269         if arg.type is NULL.
 270
 271 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 272
 273         PR target/114175
 274         * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
 275         csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 276         if arg.type is NULL.
 277
 278 2024-03-20  Yury Khrustalev  <yury.khrustalev@arm.com>
 279
 280         * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
 281
 282 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 283
 284         PR tree-optimization/114365
 285         * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
 286         a PHI node, set iv2 to its result afterwards.
 287
 288 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 289
 290         * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
 291         probabbility -> probability.
 292         (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
 293
 294 2024-03-20  Jakub Jelinek  <jakub@redhat.com>
 295
 296         PR bootstrap/114369
 297         * system.h (vec_step): Define to vec_step_ when compiling
 298         with clang on PowerPC.
 299
 300 2024-03-20  demin.han  <demin.han@starfivetech.com>
 301
 302         PR target/112651
 303         * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
 304         (enum rvv_max_lmul_enum): Ditto
 305         (TARGET_MAX_LMUL): Ditto
 306         * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
 307         * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
 308         (costs::better_main_loop_than_p): Ditto
 309         * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
 310
 311 2024-03-20  Richard Biener  <rguenther@suse.de>
 312
 313         PR middle-end/113396
 314         * tree-dfa.cc (get_ref_base_and_extent): Use index range
 315         bounds only if they fit within the address-range constraints
 316         of offset_int.
 317
 318 2024-03-20  Chenghui Pan  <panchenghui@loongson.cn>
 319
 320         * config/loongarch/loongarch.cc
 321         (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
 322         UNITS_PER_FPREG macros.
 323         (loongarch_hard_regno_nregs): Ditto.
 324         (loongarch_class_max_nregs): Ditto.
 325         (loongarch_get_separate_components): Ditto.
 326         (loongarch_process_components): Ditto.
 327         * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
 328         (UNITS_PER_HWFPVALUE): Ditto.
 329         (UNITS_PER_FPVALUE): Ditto.
 330
 331 2024-03-20  Chenghui Pan  <panchenghui@loongson.cn>
 332
 333         * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
 334         of loongarch_expand_vec_cmp()'s return value.
 335         (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
 336         * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
 337         (vec_cmpu<ILSX:mode><mode_i>): Ditto.
 338         * config/loongarch/loongarch-protos.h
 339         (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
 340         type from bool to void.
 341         * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
 342
 343 2024-03-20  Chenghui Pan  <panchenghui@loongson.cn>
 344
 345         * config/loongarch/loongarch-protos.h
 346         (loongarch_cfun_has_cprestore_slot_p): Delete.
 347         (loongarch_adjust_insn_length): Delete.
 348         (current_section_name): Delete.
 349         (loongarch_split_symbol_type): Delete.
 350         * config/loongarch/loongarch.cc
 351         (loongarch_case_values_threshold): Delete.
 352         (loongarch_spill_class): Delete.
 353         (TARGET_OPTAB_SUPPORTED_P): Delete.
 354         (TARGET_CASE_VALUES_THRESHOLD): Delete.
 355         (TARGET_SPILL_CLASS): Delete.
 356
 357 2024-03-20  Lewis Hyatt  <lhyatt@gmail.com>
 358
 359         PR c++/111918
 360         * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
 361         * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
 362         Make use of DK_ANY to indicate a diagnostic was initially enabled.
 363         (diagnostic_context::diagnostic_enabled): Do not change the type of
 364         a diagnostic if the saved classification is type DK_ANY.
 365
 366 2024-03-19  Martin Jambor  <mjambor@suse.cz>
 367
 368         PR ipa/108802
 369         PR ipa/114254
 370         * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
 371         at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
 372         a pointer parameter.
 373         (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
 374         parameter, also recognize the case when pfn pointer is loaded in its
 375         own BB.
 376
 377 2024-03-19  Vladimir N. Makarov  <vmakarov@redhat.com>
 378
 379         PR target/99829
 380         * lra-constraints.cc (lra_constraints): Prevent removing insn
 381         with reverse equivalence to memory if the memory was reloaded.
 382
 383 2024-03-19  David Malcolm  <dmalcolm@redhat.com>
 384
 385         PR middle-end/114348
 386         * diagnostic-format-json.cc
 387         (json_stderr_output_format::machine_readable_stderr_p): New.
 388         (json_file_output_format::machine_readable_stderr_p): New.
 389         * diagnostic-format-sarif.cc
 390         (sarif_stream_output_format::machine_readable_stderr_p): New.
 391         (sarif_file_output_format::machine_readable_stderr_p): New.
 392         * diagnostic.cc (diagnostic_context::action_after_output): Move
 393         "fnotice" to before "finish" call, so that we still have the
 394         diagnostic_context.
 395         (fnotice): Bail out if the user requested one of the
 396         machine-readable diagnostic output formats on stderr.
 397         * diagnostic.h
 398         (diagnostic_output_format::machine_readable_stderr_p): New pure
 399         virtual function.
 400         (diagnostic_text_output_format::machine_readable_stderr_p): New.
 401         (diagnostic_context::get_output_format): New accessor.
 402
 403 2024-03-19  Edwin Lu  <ewlu@rivosinc.com>
 404
 405         PR target/114175
 406         * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
 407         riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 408         if arg.type is NULL
 409
 410 2024-03-19  Jonathan Wakely  <jwakely@redhat.com>
 411
 412         * doc/install.texi (Prerequisites): Document use of autogen for
 413         libstdc++.
 414
 415 2024-03-19  Richard Biener  <rguenther@suse.de>
 416
 417         PR tree-optimization/114151
 418         PR tree-optimization/114269
 419         PR tree-optimization/114322
 420         PR tree-optimization/114074
 421         * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
 422         unsigned arithmetic when actual overflow on constant operands
 423         is observed.
 424
 425 2024-03-19  Jakub Jelinek  <jakub@redhat.com>
 426
 427         PR target/114175
 428         * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
 429         arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 430         if arg.type is NULL.
 431
 432 2024-03-19  Xi Ruoyao  <xry111@xry111.site>
 433
 434         PR target/114175
 435         * config/loongarch/loongarch.cc
 436         (loongarch_setup_incoming_varargs): Only skip
 437         loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
 438         functions if arg.type is NULL.
 439
 440 2024-03-19  Christophe Lyon  <christophe.lyon@linaro.org>
 441
 442         PR target/114323
 443         * config/arm/arm-mve-builtins.cc
 444         (function_instance::reads_global_state_p): Take CP_READ_MEMORY
 445         into account.
 446
 447 2024-03-19  Jakub Jelinek  <jakub@redhat.com>
 448
 449         PR target/114175
 450         * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
 451         function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 452         if arg.type is NULL.
 453
 454 2024-03-19  Jakub Jelinek  <jakub@redhat.com>
 455
 456         PR target/114175
 457         * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
 458         rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
 459         if arg.type is NULL.
 460
 461 2024-03-19  Richard Biener  <rguenther@suse.de>
 462
 463         PR tree-optimization/114375
 464         * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
 465         load permutation for masked loads but reject it when any
 466         such is necessary.
 467         * tree-vect-stmts.cc (vectorizable_load): Reject masked
 468         VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
 469         supported.
 470
 471 2024-03-19  Mary Bennett  <mary.bennett@embecosm.com>
 472
 473         * common/config/riscv/riscv-common.cc: Create XCVbi extension
 474         support.
 475         * config/riscv/riscv.opt: Likewise.
 476         * config/riscv/corev.md: Implement cv_branch<mode> pattern
 477         for cv.beqimm and cv.bneimm.
 478         * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
 479         branch instruction pattern.
 480         * config/riscv/constraints.md: Implement constraints
 481         cv_bi_s5 - signed 5-bit immediate.
 482         * config/riscv/predicates.md: Implement predicate
 483         const_int5s_operand - signed 5 bit immediate.
 484         * doc/sourcebuild.texi: Add XCVbi documentation.
 485
 486 2024-03-19  Chen Jiawei  <jiawei@iscas.ac.cn>
 487
 488         * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
 489         (RISCV_CORE): Ditto.
 490         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
 491         option.
 492         * config/riscv/riscv.cc: New def.
 493         * config/riscv/riscv.md: New include.
 494         * config/riscv/xiangshan.md: New file.
 495
 496 2024-03-18  David Malcolm  <dmalcolm@redhat.com>
 497
 498         PR analyzer/110902
 499         PR analyzer/110928
 500         PR analyzer/111305
 501         PR analyzer/111441
 502         * selftest.h (ASSERT_NE_AT): New macro.
 503
 504 2024-03-18  Uros Bizjak  <ubizjak@gmail.com>
 505
 506         PR target/111822
 507         * config/i386/i386-features.cc (smode_convert_cst): New function
 508         to handle SImode, DImode and TImode immediates, generalized from
 509         timode_convert_cst.
 510         (timode_convert_cst): Remove.
 511         (scalar_chain::convert_op): Unify from
 512         general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
 513         (general_scalar_chain::convert_op): Remove.
 514         (timode_scalar_chain::convert_op): Remove.
 515         (timode_scalar_chain::convert_insn): Update the call to
 516         renamed timode_convert_cst.
 517         * config/i386/i386-features.h (class scalar_chain):
 518         Redeclare convert_op as protected class member.
 519         (class general_calar_chain): Remove convert_op.
 520         (class timode_scalar_chain): Ditto.
 521
 522 2024-03-18  Jan Hubicka  <jh@suse.cz>
 523
 524         * config/i386/zn4zn5.md: Add file missed in the previous commit.
 525
 526 2024-03-18  Jan Hubicka  <jh@suse.cz>
 527             Karthiban Anbazhagan  <Karthiban.Anbazhagan@amd.com>
 528
 529         * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
 530         * common/config/i386/i386-common.cc (processor_names): Add znver5.
 531         (processor_alias_table): Likewise.
 532         * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
 533         family.
 534         (processor_subtypes): Add znver5.
 535         * config.gcc (x86_64-*-* |...): Likewise.
 536         * config/i386/driver-i386.cc (host_detect_local_cpu): Let
 537         march=native detect znver5 cpu's.
 538         * config/i386/i386-c.cc (ix86_target_macros_internal): Add
 539         znver5.
 540         * config/i386/i386-options.cc (m_ZNVER5): New definition
 541         (processor_cost_table): Add znver5.
 542         * config/i386/i386.cc (ix86_reassociation_width): Likewise.
 543         * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
 544         (PTA_ZNVER5): New definition.
 545         * config/i386/i386.md (define_attr "cpu"): Add znver5.
 546         (Scheduling descriptions) Add znver5.md.
 547         * config/i386/x86-tune-costs.h (znver5_cost): New definition.
 548         * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
 549         (ix86_adjust_cost): Likewise.
 550         * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
 551         (avx512_store_by_pieces): Add m_ZNVER5.
 552         * doc/extend.texi: Add znver5.
 553         * doc/invoke.texi: Likewise.
 554         * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
 555
 556 2024-03-18  Georg-Johann Lay  <avr@gjlay.de>
 557
 558         * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
 559         * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
 560         * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
 561         * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
 562         (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
 563         (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
 564
 565 2024-03-18  liuhongt  <hongtao.liu@intel.com>
 566
 567         PR target/114334
 568         * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
 569         (MODEF248): New mode iterator.
 570         (ssevecmodesuffix): Hanlde BF and HF.
 571         * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
 572         (<code><mode>3): Ditto.
 573
 574 2024-03-18  John David Anglin  <danglin@gcc.gnu.org>
 575
 576         PR rtl-optimization/112415
 577         * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
 578         for symbolic memory operands.
 579         (pa_legitimate_address_p): Revise LO_SUM condition.
 580         * config/pa/pa.h (INT14_OK_STRICT): Revise define.  Move
 581         comment about GNU linker to predicates.md.
 582         * config/pa/predicates.md (floating_point_store_memory_operand):
 583         Revise condition for symbolic memory operands.  Update
 584         comment.
 585
 586 2024-03-17  John David Anglin  <danglin@gcc.gnu.org>
 587
 588         * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
 589
 590 2024-03-16  Jakub Jelinek  <jakub@redhat.com>
 591
 592         PR target/114175
 593         * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
 594         ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
 595         if arg.type is NULL.
 596
 597 2024-03-16  Jakub Jelinek  <jakub@redhat.com>
 598
 599         PR tree-optimization/114329
 600         * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
 601         build_bit_field_ref method.
 602         (bitint_large_huge::build_bit_field_ref): New method.
 603         (bitint_large_huge::lower_mergeable_stmt): Use it.
 604
 605 2024-03-15  YunQiang Su  <syq@gcc.gnu.org>
 606
 607         * config/riscv/riscv.opt.urls: Regenerated.
 608         * config/rs6000/sysv4.opt.urls: Likewise.
 609         * config/xtensa/xtensa.opt.urls: Likewise.
 610
 611 2024-03-15  Jakub Jelinek  <jakub@redhat.com>
 612
 613         * lower-subreg.cc (resolve_simple_move): Fix comment typo,
 614         betwee -> between.
 615         * edit-context.cc (class line_event): Fix comment typo,
 616         betweeen -> between.
 617
 618 2024-03-15  Jakub Jelinek  <jakub@redhat.com>
 619
 620         PR target/114339
 621         * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
 622         a pasto, compare code against LE rather than GE.
 623
 624 2024-03-15  Joe Ramsay  <Joe.Ramsay@arm.com>
 625
 626         * match.pd: Fix truncation pattern for -fno-signed-zeroes
 627
 628 2024-03-15  Jakub Jelinek  <jakub@redhat.com>
 629
 630         PR middle-end/114332
 631         * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
 632
 633 2024-03-15  Jakub Jelinek  <jakub@redhat.com>
 634
 635         PR tree-optimization/113466
 636         * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
 637         member.
 638         (bitint_large_huge::bitint_large_huge): Initialize it.
 639         (bitint_large_huge::~bitint_large_huge): Release it.
 640         (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
 641         before which at least one statement has been inserted.
 642         (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
 643         calls to a different block and add corresponding PHIs.
 644
 645 2024-03-15  YunQiang Su  <syq@gcc.gnu.org>
 646
 647         * config/mips/mips.opt: Support -mstrict-align, and use
 648         TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
 649         as alias.
 650         * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
 651         * config/mips/mips.opt.urls: Regenerate.
 652         * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
 653
 654 2024-03-15  Tejas Belagod  <tejas.belagod@arm.com>
 655
 656         PR middle-end/114108
 657         * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
 658         vect_convert_output with the correct vecitype.
 659
 660 2024-03-15  Chenghui Pan  <panchenghui@loongson.cn>
 661
 662         * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
 663         Remove masking of operand 3.
 664
 665 2024-03-14  Jason Merrill  <jason@redhat.com>
 666
 667         * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
 668         comments.
 669
 670 2024-03-14  John David Anglin  <danglin@gcc.gnu.org>
 671
 672         PR target/114288
 673         * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
 674         14-bit displacements before reload for modes that may use
 675         a floating-point load or store.
 676
 677 2024-03-14  David Faust  <david.faust@oracle.com>
 678
 679         * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
 680
 681 2024-03-14  Max Filippov  <jcmvbkbc@gmail.com>
 682
 683         * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
 684         patterns ahead of the l32i.n and s32i.n.
 685
 686 2024-03-14  Jakub Jelinek  <jakub@redhat.com>
 687
 688         * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
 689
 690 2024-03-14  Jakub Jelinek  <jakub@redhat.com>
 691
 692         PR middle-end/113907
 693         * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
 694         SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
 695         functions.
 696
 697 2024-03-14  Xi Ruoyao  <xry111@xry111.site>
 698
 699         * config/loongarch/loongarch.md (any_ge): Remove.
 700         (sge<u>_<X:mode><GPR:mode>): Remove.
 701
 702 2024-03-14  Jakub Jelinek  <jakub@redhat.com>
 703
 704         PR target/114310
 705         * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
 706         TImode force newval into a register.
 707
 708 2024-03-14  Chung-Lin Tang  <cltang@baylibre.com>
 709
 710         * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
 711         (OMP_CLAUSE__CACHE__READONLY): New macro.
 712         * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
 713         uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
 714         OMP_CLAUSE__CACHE__READONLY.
 715         * tree-pretty-print.cc (dump_omp_clause): Add support for printing
 716         OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
 717
 718 2024-03-14  Andreas Krebbel  <krebbel@linux.ibm.com>
 719
 720         * config/s390/s390.cc (s390_encode_section_info): Adjust the check
 721         for misaligned symbols.
 722         * config/s390/s390.opt: Improve documentation.
 723
 724 2024-03-14  Jakub Jelinek  <jakub@redhat.com>
 725
 726         * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
 727         flags and probability from ad_edge to e edge.  If CDI_DOMINATORS
 728         are computed, recompute immediate dominator of other_edge->src
 729         and other_edge->dest.
 730         (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
 731         for the returns_twice call case to the gsi_for_stmt (stmt) to deal
 732         with update it for bb splitting.
 733
 734 2024-03-14  liuhongt  <hongtao.liu@intel.com>
 735
 736         * config/i386/i386-features.cc
 737         (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
 738         (convert_scalars_to_vector): Ditto.
 739         * config/i386/i386-features.h (class scalar_chain): New
 740         memeber control_flow_insns.
 741
 742 2024-03-13  Jakub Jelinek  <jakub@redhat.com>
 743
 744         PR middle-end/114319
 745         * gimple-ssa-store-merging.cc
 746         (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
 747         allow matching __builtin_bswap64 if there is bswapsi2 optab.
 748
 749 2024-03-13  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 750
 751         * config/s390/s390.cc (s390_secondary_reload): Guard
 752         SYMBOL_FLAG_NOTALIGN2_P.
 753
 754 2024-03-13  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 755
 756         * config/s390/s390-builtin-types.def: Update to reflect latest
 757         changes.
 758         * config/s390/s390-builtins.def: Streamline vector builtins with
 759         LLVM.
 760
 761 2024-03-13  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 762
 763         * config/s390/s390-builtins.def (vec_permi): Deprecate.
 764         (vec_ctd): Deprecate.
 765         (vec_ctd_s64): Deprecate.
 766         (vec_ctd_u64): Deprecate.
 767         (vec_ctsl): Deprecate.
 768         (vec_ctul): Deprecate.
 769         (vec_ld2f): Deprecate.
 770         (vec_st2f): Deprecate.
 771         (vec_insert): Deprecate overloads with bool vectors.
 772
 773 2024-03-13  Jakub Jelinek  <jakub@redhat.com>
 774
 775         PR middle-end/114313
 776         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
 777         TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
 778         (bitint_large_huge::handle_load): Pass NULL_TREE rather than
 779         rhs_type to limb_access for the bitfield load cases.
 780         (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
 781         lhs_type to limb_access if nlhs is non-NULL.
 782
 783 2024-03-13  Jakub Jelinek  <jakub@redhat.com>
 784
 785         PR sanitizer/112709
 786         * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
 787         build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
 788         gsi_safe_insert_before instead of gsi_insert_before.
 789
 790 2024-03-13  Jakub Jelinek  <jakub@redhat.com>
 791
 792         PR sanitizer/112709
 793         * gimple-iterator.h (gsi_safe_insert_before,
 794         gsi_safe_insert_seq_before): Declare.
 795         * gimple-iterator.cc: Include gimplify.h.
 796         (edge_before_returns_twice_call, adjust_before_returns_twice_call,
 797         gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
 798         * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
 799         instrument_nonnull_arg, instrument_nonnull_return): Use
 800         gsi_safe_insert_before instead of gsi_insert_before.
 801         (maybe_instrument_pointer_overflow): Use force_gimple_operand,
 802         gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
 803         instead of force_gimple_operand_gsi.
 804         (instrument_object_size): Likewise.  Use gsi_safe_insert_before
 805         instead of gsi_insert_before.
 806
 807 2024-03-12  Richard Biener  <rguenther@suse.de>
 808
 809         PR tree-optimization/114121
 810         * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
 811         converted operand properly.
 812         (chrec_fold_multiply): Likewise.  Handle missed recursion.
 813
 814 2024-03-12  Jakub Jelinek  <jakub@redhat.com>
 815
 816         PR sanitizer/112709
 817         * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
 818         stores on the caller side unless it is a call to a builtin or
 819         internal function or function doesn't return by hidden reference.
 820         (maybe_instrument_call): Likewise.
 821         (instrument_derefs): Instrument stores to RESULT_DECL if
 822         returning by hidden reference.
 823
 824 2024-03-12  Jakub Jelinek  <jakub@redhat.com>
 825
 826         PR tree-optimization/114293
 827         * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
 828         max is smaller than min, set max to ~(size_t)0.
 829
 830 2024-03-12  Pan Li  <pan2.li@intel.com>
 831
 832         * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
 833         code style greater than 80 chars.
 834         (riscv_cpu_cpp_builtins): Fix useless empty line, indent
 835         with 3 space(s) and argument unalignment.
 836
 837 2024-03-12  Richard Biener  <rguenther@suse.de>
 838
 839         PR tree-optimization/114297
 840         * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
 841         live stmts SLP node to vect_create_epilog_for_reduction.
 842
 843 2024-03-12  Andrew Pinski  <quic_apinski@quicinc.com>
 844
 845         PR driver/114314
 846         * common.opt (fmultiflags): Add RejectNegative.
 847
 848 2024-03-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 849
 850         * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
 851         * config/aarch64/aarch64.opt: Likewise.
 852         * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
 853         * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
 854         (aarch64_expand_epilogue): Likewise.
 855         (aarch64_post_cfi_startproc): Likewise.
 856         (aarch64_handle_no_branch_protection): Copy and rename.
 857         (aarch64_handle_standard_branch_protection): Likewise.
 858         (aarch64_handle_pac_ret_protection): Likewise.
 859         (aarch64_handle_pac_ret_leaf): Likewise.
 860         (aarch64_handle_pac_ret_b_key): Likewise.
 861         (aarch64_handle_bti_protection): Likewise.
 862         (aarch64_override_options): Update branch protection validation.
 863         (aarch64_handle_attr_branch_protection): Likewise.
 864         * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
 865         Pass branch protection type description as argument.
 866         (struct aarch_branch_protect_type): Move from aarch-common.h.
 867         * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
 868         Remove.
 869         (aarch_handle_standard_branch_protection): Remove.
 870         (aarch_handle_pac_ret_protection): Remove.
 871         (aarch_handle_pac_ret_leaf): Remove.
 872         (aarch_handle_pac_ret_b_key): Remove.
 873         (aarch_handle_bti_protection): Remove.
 874         (aarch_validate_mbranch_protection): Pass branch protection type
 875         description as argument.
 876         * config/arm/aarch-common.h (enum aarch_key_type): Remove.
 877         (struct aarch_branch_protect_type): Remove.
 878         * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
 879         * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
 880         (arm_handle_standard_branch_protection): Likewise.
 881         (arm_handle_pac_ret_protection): Likewise.
 882         (arm_handle_pac_ret_leaf): Likewise.
 883         (arm_handle_bti_protection): Likewise.
 884         (arm_configure_build_target): Update branch protection validation.
 885         * config/arm/arm.opt: Remove aarch_ra_sign_key.
 886
 887 2024-03-11  Richard Biener  <rguenther@suse.de>
 888
 889         PR middle-end/114299
 890         * gimplify.cc (internal_get_tmp_var): When gimplification
 891         of VAL failed, return a decl.
 892
 893 2024-03-11  Jakub Jelinek  <jakub@redhat.com>
 894
 895         PR tree-optimization/114278
 896         * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
 897         longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
 898
 899 2024-03-11  Eric Botcazou  <ebotcazou@adacore.com>
 900
 901         PR debug/113519
 902         PR debug/113777
 903         * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
 904         generate the DIE with the same parent as in the regular case.
 905
 906 2024-03-11  Andrew Pinski  <quic_apinski@quicinc.com>
 907
 908         PR middle-end/95351
 909         * fold-const.cc (merge_truthop_with_opposite_arm): Use
 910         the type of the operands of the comparison and not the type
 911         of the comparison.
 912
 913 2024-03-10  jlaw  <jeffreyalaw@gmail.com>
 914
 915         PR tree-optimization/110199
 916         * tree-ssa-scopedtables.cc
 917         (avail_exprs_stack::simplify_binary_operation): Generalize handling
 918         of MIN_EXPR/MAX_EXPR to allow additional simplifications.  Canonicalize
 919         comparison operands for other cases.
 920
 921 2024-03-10  Pan Li  <pan2.li@intel.com>
 922
 923         * tree-vect-stmts.cc (vectorizable_store): Enable the assert
 924         during transform process.
 925         (vectorizable_load): Ditto.
 926
 927 2024-03-10  jlaw  <jeffreyalaw@gmail.com>
 928
 929         PR target/102250
 930         * doc/install.texi: Document need for python when building
 931         RISC-V compilers.
 932
 933 2024-03-10  jlaw  <jeffreyalaw@gmail.com>
 934
 935         PR target/111362
 936         * mode-switching.cc (optimize_mode_switching): Only process
 937         NONDEBUG insns.
 938
 939 2024-03-09  Georg-Johann Lay  <avr@gjlay.de>
 940
 941         * config/avr/avr.md: Fix typos in comment, indentation glitches
 942         and some other nits.
 943
 944 2024-03-09  Jakub Jelinek  <jakub@redhat.com>
 945
 946         PR target/114284
 947         * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
 948         src containing MEMs unless prop.likely_profitable_p ().
 949
 950 2024-03-09  Xi Ruoyao  <xry111@xry111.site>
 951
 952         * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
 953         Support 'Q' for R_LARCH_RELAX for TLS IE.
 954         (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
 955         IE.
 956         * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
 957
 958 2024-03-09  Georg-Johann Lay  <avr@gjlay.de>
 959
 960         * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
 961         usum_widenqihi and add_zero_extend1.
 962         [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
 963         sub+sign_extend.
 964         * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
 965         Compute exact insn lengths.
 966         (*usum_widenqihi3): Allow input operands to commute.
 967
 968 2024-03-09  Jakub Jelinek  <jakub@redhat.com>
 969
 970         * config/i386/i386.opt.urls: Regenerate.
 971
 972 2024-03-09  Lulu Cheng  <chenglulu@loongson.cn>
 973
 974         * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
 975         In loongarch64, a sign extension operation is added when
 976         operands[2] is a register operand and the mode is SImode.
 977
 978 2024-03-08  Martin Jambor  <mjambor@suse.cz>
 979
 980         PR ipa/113757
 981         * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
 982         id->killed_new_ssa_names.
 983
 984 2024-03-08  Vladimir N. Makarov  <vmakarov@redhat.com>
 985
 986         PR target/113790
 987         * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
 988         for non-reload pseudo too.
 989
 990 2024-03-08  David Faust  <david.faust@oracle.com>
 991
 992         * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
 993         not attempt inline expansion if size is above threshold.
 994         * config/bpf/bpf.opt (-minline-memops-threshold): New option.
 995         * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
 996         Document.
 997
 998 2024-03-08  Richard Biener  <rguenther@suse.de>
 999
1000         PR tree-optimization/114269
1001         PR tree-optimization/114074
1002         * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
1003         in the third CASE_CONVERT case as well.
1004         (chrec_fold_multiply): Handle sign-conversions from unsigned
1005         by performing the operation in the unsigned type.
1006
1007 2024-03-08  Georg-Johann Lay  <avr@gjlay.de>
1008
1009         * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
1010         * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
1011
1012 2024-03-08  Jakub Jelinek  <jakub@redhat.com>
1013
1014         * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
1015         asm_noperands < 0 means it is not asm goto too.
1016
1017 2024-03-08  Jakub Jelinek  <jakub@redhat.com>
1018
1019         PR target/38534
1020         * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
1021         option.
1022         * config/i386/i386-options.cc (ix86_set_func_type): Don't use
1023         TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
1024         ix86_noreturn_no_callee_saved_registers is enabled.
1025         * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
1026
1027 2024-03-08  Jakub Jelinek  <jakub@redhat.com>
1028
1029         PR debug/113918
1030         * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
1031         on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
1032
1033 2024-03-08  demin.han  <demin.han@starfivetech.com>
1034
1035         PR target/114264
1036         * config/riscv/riscv-vector-costs.cc: Fix ICE
1037
1038 2024-03-08  Haochen Gui  <guihaoc@gcc.gnu.org>
1039
1040         * fwprop.cc (forward_propagate_into): Return false for volatile set
1041         source rtx.
1042
1043 2024-03-07  Wilco Dijkstra  <wilco.dijkstra@arm.com>
1044
1045         PR target/113618
1046         * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
1047         (aarch64_expand_cpymem): Emit single load/store only.
1048         (aarch64_set_one_block): Emit single stores only.
1049
1050 2024-03-07  Robin Dapp  <rdapp@ventanamicro.com>
1051
1052         PR middle-end/114196
1053         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
1054         vectorization guards.
1055
1056 2024-03-07  Jonathan Wakely  <jwakely@redhat.com>
1057
1058         * doc/cppopts.texi: Remove incorrect claim about -dD not
1059         outputting predefined macros.
1060
1061 2024-03-07  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>
1062
1063         PR target/113950
1064         * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
1065         and simplify else if with else.
1066
1067 2024-03-07  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
1068
1069         * system.h: Include safe-ctype.h after C++ standard headers.
1070
1071 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
1072
1073         PR rtl-optimization/110079
1074         * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
1075         asm goto.
1076
1077 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
1078
1079         PR middle-end/105533
1080         * expmed.cc (choose_mult_variant): Only try the val - 1 variant
1081         if val is not HOST_WIDE_INT_MIN or if mode has exactly
1082         HOST_BITS_PER_WIDE_INT precision.  Avoid triggering UB while computing
1083         val - 1.
1084
1085 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
1086
1087         PR middle-end/105533
1088         * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
1089         Multiple op->off by BITS_PER_UNIT instead of shifting it left by
1090         LOG2_BITS_PER_UNIT.
1091
1092 2024-03-07  Yang Yujie  <yangyujie@loongson.cn>
1093
1094         * config.gcc: Add a case for loongarch*-*-linux-musl*.
1095         * config/loongarch/linux.h: Disable the multilib-compatible
1096         treatment for *musl* targets.
1097         * config/loongarch/musl.h: New file.
1098
1099 2024-03-07  Jakub Jelinek  <jakub@redhat.com>
1100
1101         PR tree-optimization/114009
1102         * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
1103         argument even for GENERIC, not just for GIMPLE.
1104         * match.pd (a * !a -> 0): New simplifications.
1105
1106 2024-03-07  demin.han  <demin.han@starfivetech.com>
1107
1108         * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
1109         * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
1110         (expand_vec_cmp_float): Adapt arguments
1111
1112 2024-03-06  Uros Bizjak  <ubizjak@gmail.com>
1113
1114         PR target/114232
1115         * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
1116         of optimize_function_for_size_p.  Explictily enable for TARGET_SSE2.
1117         (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1118         (<plusminus:insn>v2qi3): Enable for optimize_size instead
1119         of optimize_function_for_size_p.  Explictily enable for TARGET_SSE2.
1120         (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1121         (<any_shift:insn>v2qi3): Enable for optimize_size instead
1122         of optimize_function_for_size_p.
1123
1124 2024-03-06  Robin Dapp  <rdapp@ventanamicro.com>
1125
1126         PR target/114200
1127         PR target/114202
1128         * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
1129
1130 2024-03-06  Robin Dapp  <rdapp@ventanamicro.com>
1131
1132         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
1133         (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
1134         offset handling.
1135         (costs::add_stmt_cost): Also adjust cost for statements without
1136         stmt_info.
1137         * config/riscv/riscv-vector-costs.h: Define zero constant.
1138
1139 2024-03-06  Wilco Dijkstra  <wilco.dijkstra@arm.com>
1140
1141         PR target/113915
1142         * config/arm/arm.md (NOCOND): Improve comment.
1143         (arm_rev*) Add predicable.
1144         * config/arm/arm.cc (arm_final_prescan_insn): Add check for
1145         PREDICABLE_YES.
1146
1147 2024-03-06  Jeff Law  <jlaw@ventanamicro.com>
1148
1149         PR target/113001
1150         PR target/112871
1151         * config/riscv/riscv.cc (expand_conditional_move): Do not swap
1152         operands when the comparison operand is the same as the false
1153         arm for a NE test.
1154
1155 2024-03-06  Uros Bizjak  <ubizjak@gmail.com>
1156
1157         * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
1158         Eliminate common code and use generic code instead.
1159
1160 2024-03-06  Georg-Johann Lay  <avr@gjlay.de>
1161
1162         * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
1163         rtx cost.
1164
1165 2024-03-06  Richard Biener  <rguenther@suse.de>
1166
1167         PR tree-optimization/114239
1168         * tree-vect-loop.cc (vect_get_vect_def): Remove.
1169         (vect_create_epilog_for_reduction): The passed in stmt_info
1170         should now be the live stmt that produces the scalar reduction
1171         result.  Revert PR114192 fix.  Base reduction info off
1172         info_for_reduction.  Remove special handling of
1173         early-break/peeled, restore original vector def gathering.
1174         Make sure to pick the correct exit PHIs.
1175         (vectorizable_live_operation): Pass in the proper stmt_info
1176         for early break exits.
1177
1178 2024-03-06  Richard Sandiford  <richard.sandiford@arm.com>
1179
1180         * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
1181         out-of-class definitions of static constants.
1182
1183 2024-03-06  Richard Biener  <rguenther@suse.de>
1184
1185         PR tree-optimization/114249
1186         * tree-vect-slp.cc (vect_build_slp_instance): Move making
1187         a BB reduction lane number even ...
1188         (vect_slp_check_for_roots): ... here to avoid leaking
1189         pattern defs.
1190
1191 2024-03-06  Richard Biener  <rguenther@suse.de>
1192
1193         PR tree-optimization/114246
1194         * tree-ssa-dse.cc (increment_start_addr): Strip useless
1195         type conversions from the adjusted address.
1196
1197 2024-03-06  Jakub Jelinek  <jakub@redhat.com>
1198
1199         PR rtl-optimization/114190
1200         * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1201         Call df_remove_problem for df_note before calling df_analyze.
1202
1203 2024-03-05  Cupertino Miranda  <cupertino.miranda@oracle.com>
1204             Indu Bhagat  <indu.bhagat@oracle.com>
1205
1206         PR debug/114186
1207         * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
1208         in the correct order of the dimensions.
1209         (gen_ctf_subrange_type): Refactor out handling of
1210         DW_TAG_subrange_type DIE to here.
1211
1212 2024-03-05  Richard Sandiford  <richard.sandiford@arm.com>
1213
1214         PR sanitizer/97696
1215         * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
1216
1217 2024-03-05  Richard Sandiford  <richard.sandiford@arm.com>
1218
1219         * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
1220         and luti_strided.
1221         * config/aarch64/aarch64-sme.md
1222         (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
1223         (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
1224         (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
1225         * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
1226         (early_ra::maybe_convert_to_strided_access): Remove support for
1227         strided LUTI2 and LUTI4.
1228
1229 2024-03-05  Richard Earnshaw  <rearnsha@arm.com>
1230
1231         PR target/113510
1232         * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
1233         low_register_operand.
1234
1235 2024-03-05  Georg-Johann Lay  <avr@gjlay.de>
1236
1237         * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
1238         in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
1239         to "X = Y, X o= CST".
1240
1241 2024-03-05  Xi Ruoyao  <xry111@xry111.site>
1242
1243         * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
1244         s9 as an alias of r22.
1245
1246 2024-03-05  Roger Sayle  <roger@nextmovesoftware.com>
1247
1248         * config/avr/avr-protos.h (avr_out_insv): New proto.
1249         * config/avr/avr.cc (avr_out_insv): New function.
1250         (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
1251         (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
1252         * config/avr/avr.md (define_attr "adjust_len") Add insv.
1253         (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
1254         Add constraint alternative where the 3rd operand is a power
1255         of 2, and the source register may differ from the destination.
1256         (*insv.any_shift.<mode>_split): Call avr_out_insv to output
1257         instructions.  Set attr "length" to "insv".
1258         * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
1259
1260 2024-03-05  Richard Biener  <rguenther@suse.de>
1261
1262         PR tree-optimization/114231
1263         * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
1264         processing a BB SLP root.
1265
1266 2024-03-05  Jakub Jelinek  <jakub@redhat.com>
1267
1268         PR rtl-optimization/114211
1269         * lower-subreg.cc (resolve_simple_move): For double-word
1270         rotates by BITS_PER_WORD if there is overlap between source
1271         and destination use a temporary.
1272
1273 2024-03-05  Jakub Jelinek  <jakub@redhat.com>
1274
1275         PR middle-end/114157
1276         * gimple-lower-bitint.cc: Include stor-layout.h.
1277         (mergeable_op): Return true for BIT_FIELD_REF.
1278         (struct bitint_large_huge): Declare handle_bit_field_ref method.
1279         (bitint_large_huge::handle_bit_field_ref): New method.
1280         (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
1281
1282 2024-03-05  Jakub Jelinek  <jakub@redhat.com>
1283
1284         PR target/114116
1285         * config/i386/i386.h (enum call_saved_registers_type): Add
1286         TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
1287         * config/i386/i386-options.cc (ix86_set_func_type): Remove
1288         has_no_callee_saved_registers variable, add no_callee_saved_registers
1289         instead, initialize it depending on whether it is
1290         no_callee_saved_registers function or not.  Don't set it if
1291         no_caller_saved_registers attribute is present.  Adjust users.
1292         * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
1293         TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
1294         TYPE_NO_CALLEE_SAVED_REGISTERS.
1295         (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
1296
1297 2024-03-05  Pan Li  <pan2.li@intel.com>
1298
1299         * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
1300         mode_size related code.
1301
1302 2024-03-05  Patrick Palka  <ppalka@redhat.com>
1303
1304         * doc/invoke.texi (-Wno-global-module): Document.
1305
1306 2024-03-04  David Faust  <david.faust@oracle.com>
1307
1308         * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
1309         * config/bpf/bpf.cc (bpf_expand_setmem): New.
1310         * config/bpf/bpf.md (setmemdi): New define_expand.
1311
1312 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
1313
1314         PR rtl-optimization/113010
1315         * combine.cc (simplify_comparison): Guard the
1316         WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
1317         and initialize inner_mode.
1318
1319 2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1320
1321         * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1322         VMLALDAVAXQ_U cases.
1323         (VMLALDAVXQ): Remove iterator.
1324         (VMLALDAVXQ_P): Likewise.
1325         (VMLALDAVAXQ): Likewise.
1326         * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
1327         mode iterator attribute with V4BI mode.
1328         * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1329         VMLALDAVAXQ_U): Remove unused unspecs.
1330
1331 2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1332
1333         * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
1334         * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
1335         attribute.
1336         * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
1337         vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
1338         vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
1339         vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
1340         vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
1341         vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
1342         vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
1343         vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
1344         vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
1345         vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
1346
1347 2024-03-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1348
1349         * config/arm/arm.md (mve_unpredicated_insn): New attribute.
1350         * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
1351         (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
1352         (MVE_VPT_PREDICABLE_INSN_P): Likewise.
1353         * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
1354         * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
1355         (arm_vcx1q<a>v16qi): Likewise.
1356         (arm_vcx1qav16qi): Likewise.
1357         (arm_vcx1qv16qi): Likewise.
1358         (arm_vcx2q<a>_p_v16qi): Likewise.
1359         (arm_vcx2q<a>v16qi): Likewise.
1360         (arm_vcx2qav16qi): Likewise.
1361         (arm_vcx2qv16qi): Likewise.
1362         (arm_vcx3q<a>_p_v16qi): Likewise.
1363         (arm_vcx3q<a>v16qi): Likewise.
1364         (arm_vcx3qav16qi): Likewise.
1365         (arm_vcx3qv16qi): Likewise.
1366         (@mve_<mve_insn>q_<supf><mode>): Likewise.
1367         (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
1368         (@mve_<mve_insn>q_<supf>v4si): Likewise.
1369         (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
1370         (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
1371         (@mve_<mve_insn>q_f<mode>): Likewise.
1372         (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
1373         (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
1374         (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
1375         (@mve_<mve_insn>q_m_f<mode>): Likewise.
1376         (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
1377         (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
1378         (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
1379         (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
1380         (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
1381         (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
1382         (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
1383         (mve_v<absneg_str>q_f<mode>): Likewise.
1384         (mve_<mve_addsubmul>q<mode>): Likewise.
1385         (mve_<mve_addsubmul>q_f<mode>): Likewise.
1386         (mve_vadciq_<supf>v4si): Likewise.
1387         (mve_vadciq_m_<supf>v4si): Likewise.
1388         (mve_vadcq_<supf>v4si): Likewise.
1389         (mve_vadcq_m_<supf>v4si): Likewise.
1390         (mve_vandq_<supf><mode>): Likewise.
1391         (mve_vandq_f<mode>): Likewise.
1392         (mve_vandq_m_<supf><mode>): Likewise.
1393         (mve_vandq_m_f<mode>): Likewise.
1394         (mve_vandq_s<mode>): Likewise.
1395         (mve_vandq_u<mode>): Likewise.
1396         (mve_vbicq_<supf><mode>): Likewise.
1397         (mve_vbicq_f<mode>): Likewise.
1398         (mve_vbicq_m_<supf><mode>): Likewise.
1399         (mve_vbicq_m_f<mode>): Likewise.
1400         (mve_vbicq_m_n_<supf><mode>): Likewise.
1401         (mve_vbicq_n_<supf><mode>): Likewise.
1402         (mve_vbicq_s<mode>): Likewise.
1403         (mve_vbicq_u<mode>): Likewise.
1404         (@mve_vclzq_s<mode>): Likewise.
1405         (mve_vclzq_u<mode>): Likewise.
1406         (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
1407         (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
1408         (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
1409         (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
1410         (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
1411         (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
1412         (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
1413         (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
1414         (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
1415         (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
1416         (mve_vcvtaq_<supf><mode>): Likewise.
1417         (mve_vcvtaq_m_<supf><mode>): Likewise.
1418         (mve_vcvtbq_f16_f32v8hf): Likewise.
1419         (mve_vcvtbq_f32_f16v4sf): Likewise.
1420         (mve_vcvtbq_m_f16_f32v8hf): Likewise.
1421         (mve_vcvtbq_m_f32_f16v4sf): Likewise.
1422         (mve_vcvtmq_<supf><mode>): Likewise.
1423         (mve_vcvtmq_m_<supf><mode>): Likewise.
1424         (mve_vcvtnq_<supf><mode>): Likewise.
1425         (mve_vcvtnq_m_<supf><mode>): Likewise.
1426         (mve_vcvtpq_<supf><mode>): Likewise.
1427         (mve_vcvtpq_m_<supf><mode>): Likewise.
1428         (mve_vcvtq_from_f_<supf><mode>): Likewise.
1429         (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
1430         (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
1431         (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
1432         (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
1433         (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
1434         (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
1435         (mve_vcvtq_to_f_<supf><mode>): Likewise.
1436         (mve_vcvttq_f16_f32v8hf): Likewise.
1437         (mve_vcvttq_f32_f16v4sf): Likewise.
1438         (mve_vcvttq_m_f16_f32v8hf): Likewise.
1439         (mve_vcvttq_m_f32_f16v4sf): Likewise.
1440         (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
1441         (mve_vdwdupq_wb_u<mode>_insn): Likewise.
1442         (mve_veorq_s><mode>): Likewise.
1443         (mve_veorq_u><mode>): Likewise.
1444         (mve_veorq_f<mode>): Likewise.
1445         (mve_vidupq_m_wb_u<mode>_insn): Likewise.
1446         (mve_vidupq_u<mode>_insn): Likewise.
1447         (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
1448         (mve_viwdupq_wb_u<mode>_insn): Likewise.
1449         (mve_vldrbq_<supf><mode>): Likewise.
1450         (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
1451         (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
1452         (mve_vldrbq_z_<supf><mode>): Likewise.
1453         (mve_vldrdq_gather_base_<supf>v2di): Likewise.
1454         (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
1455         (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
1456         (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
1457         (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
1458         (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
1459         (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
1460         (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
1461         (mve_vldrhq_<supf><mode>): Likewise.
1462         (mve_vldrhq_fv8hf): Likewise.
1463         (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
1464         (mve_vldrhq_gather_offset_fv8hf): Likewise.
1465         (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
1466         (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
1467         (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
1468         (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
1469         (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
1470         (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
1471         (mve_vldrhq_z_<supf><mode>): Likewise.
1472         (mve_vldrhq_z_fv8hf): Likewise.
1473         (mve_vldrwq_<supf>v4si): Likewise.
1474         (mve_vldrwq_fv4sf): Likewise.
1475         (mve_vldrwq_gather_base_<supf>v4si): Likewise.
1476         (mve_vldrwq_gather_base_fv4sf): Likewise.
1477         (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
1478         (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
1479         (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
1480         (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
1481         (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
1482         (mve_vldrwq_gather_base_z_fv4sf): Likewise.
1483         (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
1484         (mve_vldrwq_gather_offset_fv4sf): Likewise.
1485         (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
1486         (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
1487         (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
1488         (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
1489         (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
1490         (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
1491         (mve_vldrwq_z_<supf>v4si): Likewise.
1492         (mve_vldrwq_z_fv4sf): Likewise.
1493         (mve_vmvnq_s<mode>): Likewise.
1494         (mve_vmvnq_u<mode>): Likewise.
1495         (mve_vornq_<supf><mode>): Likewise.
1496         (mve_vornq_f<mode>): Likewise.
1497         (mve_vornq_m_<supf><mode>): Likewise.
1498         (mve_vornq_m_f<mode>): Likewise.
1499         (mve_vornq_s<mode>): Likewise.
1500         (mve_vornq_u<mode>): Likewise.
1501         (mve_vorrq_<supf><mode>): Likewise.
1502         (mve_vorrq_f<mode>): Likewise.
1503         (mve_vorrq_m_<supf><mode>): Likewise.
1504         (mve_vorrq_m_f<mode>): Likewise.
1505         (mve_vorrq_m_n_<supf><mode>): Likewise.
1506         (mve_vorrq_n_<supf><mode>): Likewise.
1507         (mve_vorrq_s<mode>): Likewise.
1508         (mve_vorrq_s<mode>): Likewise.
1509         (mve_vsbciq_<supf>v4si): Likewise.
1510         (mve_vsbciq_m_<supf>v4si): Likewise.
1511         (mve_vsbcq_<supf>v4si): Likewise.
1512         (mve_vsbcq_m_<supf>v4si): Likewise.
1513         (mve_vshlcq_<supf><mode>): Likewise.
1514         (mve_vshlcq_m_<supf><mode>): Likewise.
1515         (mve_vshrq_m_n_<supf><mode>): Likewise.
1516         (mve_vshrq_n_<supf><mode>): Likewise.
1517         (mve_vstrbq_<supf><mode>): Likewise.
1518         (mve_vstrbq_p_<supf><mode>): Likewise.
1519         (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
1520         (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
1521         (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
1522         (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
1523         (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
1524         (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
1525         (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
1526         (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
1527         (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
1528         (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
1529         (mve_vstrhq_<supf><mode>): Likewise.
1530         (mve_vstrhq_fv8hf): Likewise.
1531         (mve_vstrhq_p_<supf><mode>): Likewise.
1532         (mve_vstrhq_p_fv8hf): Likewise.
1533         (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
1534         (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
1535         (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
1536         (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
1537         (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
1538         (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
1539         (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
1540         (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
1541         (mve_vstrwq_<supf>v4si): Likewise.
1542         (mve_vstrwq_fv4sf): Likewise.
1543         (mve_vstrwq_p_<supf>v4si): Likewise.
1544         (mve_vstrwq_p_fv4sf): Likewise.
1545         (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
1546         (mve_vstrwq_scatter_base_fv4sf): Likewise.
1547         (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
1548         (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
1549         (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
1550         (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
1551         (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
1552         (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
1553         (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
1554         (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
1555         (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
1556         (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
1557         (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
1558         (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
1559         (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
1560         (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
1561
1562 2024-03-04  Marek Polacek  <polacek@redhat.com>
1563
1564         * doc/extend.texi: Update [[gnu::no_dangling]].
1565
1566 2024-03-04  Andrew Stubbs  <ams@baylibre.com>
1567
1568         * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
1569         * expr.cc (store_constructor): Likewise.
1570         (do_store_flag): Likewise.
1571
1572 2024-03-04  Mark Wielaard  <mark@klomp.org>
1573
1574         * common.opt.urls: Regenerate.
1575         * config/avr/avr.opt.urls: Likewise.
1576         * config/i386/i386.opt.urls: Likewise.
1577         * config/pru/pru.opt.urls: Likewise.
1578         * config/riscv/riscv.opt.urls: Likewise.
1579         * config/rs6000/rs6000.opt.urls: Likewise.
1580
1581 2024-03-04  Richard Biener  <rguenther@suse.de>
1582
1583         PR tree-optimization/114197
1584         * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
1585         there are volatile bitfield accesses.
1586         (pass_if_conversion::execute): Throw away result if the
1587         if-converted and original loops are not nested as expected.
1588
1589 2024-03-04  Richard Biener  <rguenther@suse.de>
1590
1591         PR tree-optimization/114164
1592         * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
1593         the code generated for mask argument setup is not supported.
1594
1595 2024-03-04  Richard Biener  <rguenther@suse.de>
1596
1597         PR tree-optimization/114203
1598         * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
1599         adjustment before making the result defined at zero.
1600
1601 2024-03-04  Richard Biener  <rguenther@suse.de>
1602
1603         PR tree-optimization/114192
1604         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
1605         appropriate def for the live out stmt in case of an alternate
1606         exit.
1607
1608 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
1609
1610         PR middle-end/114209
1611         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
1612         unshare_expr when creating a MEM_REF from MEM_REF.
1613         (bitint_large_huge::lower_stmt): Call unshare_expr.
1614
1615 2024-03-04  Jakub Jelinek  <jakub@redhat.com>
1616
1617         PR target/114184
1618         * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
1619         is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
1620         register.
1621
1622 2024-03-04  Roger Sayle  <roger@nextmovesoftware.com>
1623
1624         PR target/114187
1625         * simplify-rtx.cc (simplify_context::simplify_subreg): Call
1626         lowpart_subreg to perform type conversion, to avoid confusion
1627         over the offset to use in the call to simplify_reg_subreg.
1628
1629 2024-03-03  Greg McGary  <gkm@rivosinc.com>
1630
1631         PR rtl-optimization/113010
1632         * combine.cc (simplify_comparison): Simplify a SUBREG on
1633         WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
1634         MEM load.
1635
1636 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
1637
1638         * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
1639         Use bool in place of int for boolean logic (if possible).
1640         Move declarations to definitions (if possible).
1641         * config/avr/avr.md: Use C++ comments.  Fix some indentation glitches.
1642         * config/avr/avr-dimode.md: Same.
1643         * config/avr/constraints.md: Same.
1644         * config/avr/predicates.md: Same.
1645
1646 2024-03-03  Uros Bizjak  <ubizjak@gmail.com>
1647
1648         PR target/113720
1649         * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
1650         (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
1651         simplify insn RTX using UMUL_HIGHPART rtx_code.
1652         (*umuldi3_highpart_const): Remove.
1653
1654 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
1655
1656         PR target/114100
1657         * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
1658         * config/avr/avr.cc (_reg_unused_after): Make static.  And
1659         add 3rd argument to skip the current insn.
1660         (reg_unused_after): Adjust call of reg_unused_after.
1661         (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
1662         unneeded frame pointer adjustments.
1663
1664 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
1665
1666         PR target/92729
1667         * config/avr/avr.md (define_attr "cc"): Remove.
1668         * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
1669         from prototype.
1670         * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
1671         its uses.  Add insn argument.
1672         (avr_out_plus_symbol): Remove pcc argument and its uses.
1673         (avr_out_plus): Remove pcc argument and its uses.
1674         Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
1675         (avr_out_round): Adjust call of avr_out_plus.
1676
1677 2024-03-03  Georg-Johann Lay  <avr@gjlay.de>
1678
1679         * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
1680         from  r14-9273.
1681
1682 2024-03-03  Oleg Endo  <olegendo@gcc.gnu.org>
1683
1684         PR target/101737
1685         * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
1686         is not an insn, but e.g. a code label.
1687
1688 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
1689
1690         * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
1691         * config/avr/avr.cc: Use them instead of magic numbers when it
1692         means a register number.
1693
1694 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
1695
1696         * config/avr/avr.cc: Adjust some comments.
1697
1698 2024-03-02  Georg-Johann Lay  <avr@gjlay.de>
1699
1700         PR target/114100
1701         * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
1702         the low part of the frame pointer with 8-bit stack pointer.
1703
1704 2024-03-01  Patrick Palka  <ppalka@redhat.com>
1705
1706         PR c++/104919
1707         PR c++/106009
1708         * tree-inline.cc (remap_decl): Handle copy_decl returning the
1709         original decl.
1710         (remap_decls): Handle remap_decl returning the original decl.
1711         (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
1712         CONST_DECL.
1713
1714 2024-03-01  Jeff Law  <jlaw@ventanamicro.com>
1715
1716         * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
1717         type attribute.
1718         (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
1719         (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
1720         (movhi_internal, movqi_internal): Likewise.
1721         (movsf_softfloat, movsf_hardfloat): Likewise.
1722         (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
1723         (movdf_softfloat): Likewise.
1724
1725 2024-03-01  Marek Polacek  <polacek@redhat.com>
1726
1727         PR c++/110358
1728         PR c++/109642
1729         * doc/extend.texi: Document gnu::no_dangling.
1730         * doc/invoke.texi: Mention that gnu::no_dangling disables
1731         -Wdangling-reference.
1732
1733 2024-03-01  Georg-Johann Lay  <avr@gjlay.de>
1734
1735         * config/avr/avr.opt: Overhaul help screen.
1736
1737 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
1738             Tobias Burnus  <tburnus@baylibre.com>
1739
1740         PR c++/110347
1741         * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
1742         lang_hooks.decls.omp_disregard_value_expr for
1743         (first)private in target regions.
1744
1745 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
1746
1747         PR middle-end/114136
1748         * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
1749         n_named_args initially before INIT_CUMULATIVE_ARGS to
1750         structure_value_addr_parm rather than 0, after it don't modify
1751         it if strict_argument_naming and clear only if
1752         !pretend_outgoing_varargs_named.
1753
1754 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
1755
1756         PR debug/114015
1757         * dwarf2out.cc (should_move_die_to_comdat): Return false for
1758         aggregates without DW_AT_byte_size attribute or with non-constant
1759         DW_AT_byte_size.
1760
1761 2024-03-01  Georg-Johann Lay  <avr@gjlay.de>
1762
1763         * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
1764         valid values for level.
1765
1766 2024-03-01  Richard Biener  <rguenther@suse.de>
1767
1768         PR middle-end/114070
1769         * match.pd ((c ? a : b) op d  -->  c ? (a op d) : (b op d)):
1770         Allow the folding if before lowering and the current IL
1771         isn't supported with vcond_mask.
1772
1773 2024-03-01  xuli  <xuli1@eswincomputing.com>
1774
1775         * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
1776         attribute to riscv_attribute_table.
1777         (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
1778         (riscv_fntype_abi): Add riscv_vector_cc attribute check.
1779         * doc/extend.texi: Add riscv_vector_cc attribute description.
1780
1781 2024-03-01  Pan Li  <pan2.li@intel.com>
1782
1783         PR target/112817
1784         * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
1785         RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
1786         * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
1787         (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
1788         * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
1789         comments for option replacement.
1790         * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
1791         riscv_autovec_preference to rvv_vector_bits.
1792         (vls_mode_valid_p): Ditto.
1793         (estimated_poly_value): Ditto.
1794         * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
1795         vector chunks and honor new option mrvv-vector-bits.
1796         (riscv_override_options_internal): Update comments and rename the
1797         vector chunks.
1798         * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
1799         internal option param=riscv-autovec-preference.
1800
1801 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
1802
1803         * function.cc (assign_parms): Only call assign_parms_setup_varargs
1804         early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
1805
1806 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
1807
1808         PR middle-end/114156
1809         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
1810         rhs1 of a VCE to have no underlying variable if it is a load and
1811         handle that case.
1812
1813 2024-02-29  David Malcolm  <dmalcolm@redhat.com>
1814
1815         PR analyzer/114159
1816         * function.cc (function_name): Make param const.
1817         * function.h (function_name): Likewise.
1818
1819 2024-02-29  Georg-Johann Lay  <avr@gjlay.de>
1820
1821         PR target/114100
1822         * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
1823         * config/avr/avr.opt (-mfuse-add=): New target option.
1824         * common/config/avr/avr-common.cc (avr_option_optimization_table)
1825         [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
1826         [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
1827         * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
1828         * config/avr/avr-protos.h (avr_split_tiny_move)
1829         (make_avr_pass_fuse_add): New protos.
1830         * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
1831         avr_split_tiny_move to split indirect memory accesses.
1832         (gen_move_clobbercc): New define_expand helper.
1833         * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
1834         (avr_pass_fuse_add): New class from rtl_opt_pass.
1835         (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
1836         (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
1837         (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
1838         of PLUS addressing for AVR_TINY.
1839         (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
1840         (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
1841         (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
1842
1843 2024-02-29  Georg-Johann Lay  <avr@gjlay.de>
1844
1845         PR target/114132
1846         * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
1847         * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
1848         (avr_function_arg): Set it.
1849         (avr_frame_pointer_required_p): Use it instead of .nregs.
1850
1851 2024-02-29  Andrew Pinski  <quic_apinski@quicinc.com>
1852
1853         PR target/108174
1854         * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
1855         static and mark with GTY.
1856
1857 2024-02-29  Xi Ruoyao  <xry111@xry111.site>
1858
1859         * config/loongarch/loongarch.md
1860         (loongarch_<crc>_w_<size>_w_extended): New define_insn.
1861
1862 2024-02-29  Xi Ruoyao  <xry111@xry111.site>
1863
1864         * config/loongarch/loongarch.md (CRC): New define_int_iterator.
1865         (crc): New define_int_attr.
1866         (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
1867         into ...
1868         (loongarch_<crc>_w_<size>_w): ... here.
1869
1870 2024-02-29  Kito Cheng  <kito.cheng@sifive.com>
1871
1872         PR target/114130
1873         * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
1874         extend the expected value if needed.
1875
1876 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
1877
1878         * config.gcc (target_gtfiles): Change coreout to btfext-out.
1879         (extra_objs): Change coreout to btfext-out.
1880         * config/bpf/coreout.cc: Rename to btfext-out.cc.
1881         * config/bpf/btfext-out.cc: Add.
1882         * config/bpf/coreout.h: Rename to btfext-out.h.
1883         * config/bpf/btfext-out.h: Add.
1884         * config/bpf/core-builtins.cc: Change include.
1885         * config/bpf/core-builtins.h: Change include.
1886         * config/bpf/t-bpf: Accomodate renamed files.
1887
1888 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
1889
1890         PR target/113453
1891         * config/bpf/bpf.cc (bpf_function_prologue): Define target
1892         hook.
1893         * config/bpf/coreout.cc (brf_ext_info_section)
1894         (btf_ext_info): Move from coreout.h
1895         (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
1896         (bpf_core_reloc): Rename to btf_ext_core_reloc.
1897         (btf_ext): Add static variable.
1898         (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
1899         (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
1900         (btf_ext_add_string, btf_funcinfo_type_callback)
1901         (btf_add_func_info_for, btf_validate_funcinfo)
1902         (btf_ext_info_len, output_btfext_func_info): Add function.
1903         (output_btfext_header, bpf_core_reloc_add)
1904         (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
1905         Change to support new structs.
1906         * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
1907         Move and change in coreout.cc.
1908         (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
1909
1910 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
1911
1912         * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
1913         enabled by default for BPF.
1914         (bpf_file_end): Call BTF deallocation.
1915         (bpf_asm_init_sections): Correct condition.
1916         * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
1917         deallocation.
1918         (ctf_debuf_finish): Correct condition for calling
1919         ctf_debug_finalize.
1920
1921 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
1922
1923         * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
1924         (traverse_btf_func_types): Define function.
1925         * ctfc.h (funcs_traverse_callback): Typedef for function
1926         prototype.
1927         (traverse_btf_func_types): Add prototype.
1928
1929 2024-02-28  Cupertino Miranda  <cupertino.miranda@oracle.com>
1930
1931         * btfout.cc (btf_collect_dataset): Corrects BTF type id.
1932
1933 2024-02-28  Richard Biener  <rguenther@suse.de>
1934
1935         PR tree-optimization/113831
1936         PR tree-optimization/108355
1937         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
1938         PR113831 fix.
1939
1940 2024-02-28  Richard Biener  <rguenther@suse.de>
1941
1942         PR tree-optimization/114121
1943         * tree-ssa-sccvn.h (vn_reference_s::offset,
1944         vn_reference_s::max_size): New fields.
1945         (vn_reference_insert_pieces): Adjust prototype.
1946         * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
1947         * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
1948         size, allow using "don't know" state.
1949         (vn_walk_cb_data::finish): Pass along offset/max_size.
1950         (vn_reference_lookup_or_insert_for_pieces): Take offset and
1951         max_size as argument and use it.
1952         (vn_reference_lookup_3): Properly adjust offset and max_size
1953         according to the adjusted ao_ref.
1954         (vn_reference_lookup_pieces): Initialize offset and max_size.
1955         (vn_reference_lookup): Likewise.
1956         (vn_reference_lookup_call): Likewise.
1957         (vn_reference_insert): Likewise.
1958         (visit_reference_op_call): Likewise.
1959         (vn_reference_insert_pieces): Take offset and max_size
1960         as argument and use it.
1961
1962 2024-02-28  Juergen Christ  <jchrist@linux.ibm.com>
1963
1964         PR tree-optimization/114075
1965         * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
1966         point vectors
1967
1968 2024-02-28  Jakub Jelinek  <jakub@redhat.com>
1969
1970         PR tree-optimization/114041
1971         * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
1972         INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
1973
1974 2024-02-28  Jakub Jelinek  <jakub@redhat.com>
1975
1976         PR tree-optimization/113988
1977         * stor-layout.h (bitwise_mode_for_size): Declare.
1978         * stor-layout.cc (bitwise_mode_for_size): New function.
1979         * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
1980         Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
1981         Use BITS_PER_UNIT instead of 8.
1982
1983 2024-02-27  Uros Bizjak  <ubizjak@gmail.com>
1984
1985         PR target/113871
1986         * config/i386/mmx.md (V248FI): Add V2BF mode.
1987         (V24FI_32): Ditto.
1988
1989 2024-02-27  Eric Botcazou  <ebotcazou@adacore.com>
1990
1991         * tree-ssa-dse.cc (compute_trims): Fix description.  Return early
1992         if either ref->offset is not byte aligned or ref->size is not known
1993         to be equal to ref->max_size.
1994         (maybe_trim_complex_store): Fix description.
1995         (maybe_trim_constructor_store): Likewise.
1996         (maybe_trim_partially_dead_store): Likewise.
1997
1998 2024-02-27  Richard Earnshaw  <rearnsha@arm.com>
1999
2000         * config/arm/mmintrin.h: Warn if this header is included without
2001         defining __ENABLE_DEPRECATED_IWMMXT.
2002
2003 2024-02-27  Richard Biener  <rguenther@suse.de>
2004
2005         PR tree-optimization/114074
2006         * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
2007         * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
2008         Handle poly vs. non-poly multiplication correctly with respect
2009         to undefined behavior on overflow.
2010
2011 2024-02-27  Jakub Jelinek  <jakub@redhat.com>
2012
2013         PR rtl-optimization/114044
2014         * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
2015         DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
2016         * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
2017         expand_PARITY): Declare.
2018         * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
2019         expand_CTZ, expand_FFS, expand_PARITY): New functions.
2020         (expand_POPCOUNT): Use expand_bitquery.
2021
2022 2024-02-27  Richard Biener  <rguenther@suse.de>
2023
2024         PR tree-optimization/114081
2025         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2026         Perform manual dominator update for prologue peeling.
2027         (vect_do_peeling): Properly update dominators after adding the
2028         prologue-around guard.
2029
2030 2024-02-26  Georg-Johann Lay  <avr@gjlay.de>
2031
2032         * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
2033         (mstrict-X): Tag as "Optimization".
2034
2035 2024-02-26  Georg-Johann Lay  <avr@gjlay.de>
2036
2037         * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
2038         an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
2039
2040 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
2041             H.J. Lu  <hjl.tools@gmail.com>
2042
2043         PR rtl-optimization/113617
2044         * varasm.cc (default_elf_select_rtx_section): For
2045         references to private symbols in comdat sections
2046         use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
2047         or .rodata.<comdat> comdat sections.
2048
2049 2024-02-26  Richard Biener  <rguenther@suse.de>
2050
2051         PR tree-optimization/114099
2052         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2053         Create and fill in a needed virtual LC PHI for the alternate
2054         exits.  Remove code dealing with that missing.
2055
2056 2024-02-26  Richard Biener  <rguenther@suse.de>
2057
2058         PR tree-optimization/114068
2059         * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
2060         New function.
2061         (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
2062         on the main exit if needed.  Remove band-aid for the case
2063         it was missing.
2064
2065 2024-02-26  H.J. Lu  <hjl.tools@gmail.com>
2066
2067         PR target/114097
2068         * config/i386/i386-options.cc (ix86_set_func_type): Check
2069         interrupt instead of noreturn attribute.
2070
2071 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
2072
2073         * config/i386/i386.cc (ix86_bitint_type_info): Add support for
2074         !TARGET_64BIT.
2075
2076 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
2077
2078         PR tree-optimization/114090
2079         * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
2080         Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
2081         types.
2082         ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
2083
2084 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
2085
2086         PR middle-end/114084
2087         * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
2088         if all subtrees of var0 come from one of the op0 or op1 operands
2089         and all subtrees of con0 come from the other one.  Don't clear
2090         variables which are never used afterwards.
2091
2092 2024-02-26  Richard Biener  <rguenther@suse.de>
2093
2094         PR middle-end/114070
2095         * genmatch.cc (parser::parse_c_expr): Do not record operand
2096         lists but only mark operators used.
2097         * match.pd ((c ? a : b) op (c ? d : e)  -->  c ? (a op d) : (b op e)):
2098         Properly guard the case of tcc_comparison changing the VEC_COND
2099         value operand type.
2100
2101 2024-02-26  Jakub Jelinek  <jakub@redhat.com>
2102
2103         PR target/114094
2104         * config/i386/i386.cc (x86_function_profiler): Add missing new-line
2105         to printed instruction.
2106
2107 2024-02-26  H.J. Lu  <hjl.tools@gmail.com>
2108
2109         PR target/114098
2110         * config/i386/amxtileintrin.h (_tile_loadconfig): Use
2111         __builtin_ia32_ldtilecfg.
2112         (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
2113         * config/i386/i386-builtin.def (BDESC): Add
2114         __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
2115         * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
2116         IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
2117         * config/i386/i386.md (ldtilecfg): New pattern.
2118         (sttilecfg): Likewise.
2119
2120 2024-02-24  Richard Sandiford  <richard.sandiford@arm.com>
2121
2122         PR tree-optimization/113205
2123         * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
2124         the proposed layout if it does not allow a source partition with
2125         layout 2 to keep that layout.
2126
2127 2024-02-24  Jakub Jelinek  <jakub@redhat.com>
2128
2129         * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
2130         * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
2131         * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
2132         * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
2133         (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
2134         * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
2135         macros.
2136         * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
2137         * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
2138         * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
2139         HOST_WIDE_INT_UC macros.
2140         * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
2141         * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
2142         * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
2143         * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
2144         macros.
2145         * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
2146         * config/i386/constraints.md (define_constraint "L"): Use
2147         HOST_WIDE_INT_C macro.
2148         * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
2149         macro.
2150         (movl + movb peephole2): Likewise.
2151         * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
2152         (const_32bit_mask): Likewise.
2153
2154 2024-02-24  Jakub Jelinek  <jakub@redhat.com>
2155
2156         PR middle-end/114073
2157         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
2158         VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
2159         types like vector or complex types.
2160         (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
2161         types.  Fix up VIEW_CONVERT_EXPR handling.  Allow merging
2162         VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
2163
2164 2024-02-23  Robin Dapp  <rdapp@ventanamicro.com>
2165
2166         PR target/114028
2167         * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
2168         Return false if inner mode is already Pmode.
2169         (rvv_builder::is_all_same_sequence): New function.
2170         (expand_vec_init): Emit broadcast if sequence is all same.
2171
2172 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
2173
2174         PR target/113613
2175         * config/aarch64/aarch64-early-ra.cc
2176         (early_ra::m_current_region): New member variable.
2177         (early_ra::m_fpr_recency): Likewise.
2178         (early_ra::start_new_region): Bump m_current_region.
2179         (early_ra::allocate_colors): Prefer less recently used registers
2180         in the event of a tie.  Add a comment to explain why we prefer(ed)
2181         higher-numbered registers.
2182         (early_ra::find_oldest_color): Prefer less recently used registers
2183         here too.
2184         (early_ra::finalize_allocation): Update recency information for
2185         allocated registers.
2186         (early_ra::process_blocks): Initialize m_current_region and
2187         m_fpr_recency.
2188
2189 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
2190
2191         PR target/113295
2192         * config/aarch64/aarch64-early-ra.cc
2193         (early_ra::test_strictness): New enum.
2194         (early_ra::is_chain_candidate): Add a strictness parameter to
2195         control whether only correctness matters, or whether both correctness
2196         and heuristics should be used.  Handle multiple levels of equivalence.
2197         (early_ra::find_related_start): Update call accordingly.
2198         (early_ra::strided_polarity_pref): Likewise.
2199         (early_ra::form_chains): Likewise.
2200         (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
2201         correctness mode rather than trying to inline the test.
2202
2203 2024-02-23  Richard Sandiford  <richard.sandiford@arm.com>
2204
2205         PR target/113295
2206         * config/aarch64/aarch64-early-ra.cc
2207         (early_ra::find_related_start): Account for definitions by shared
2208         registers when testing for a single register definition.
2209         (early_ra::accumulate_defs): New function.
2210         (early_ra::record_copy): If A shares B's register, fold A's
2211         definition information into B's.  Fold A's use information into B's.
2212
2213 2024-02-23  H.J. Lu  <hjl.tools@gmail.com>
2214
2215         * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
2216         if R_X86_64_CODE_6_GOTTPOFF is supported.
2217         * config.in: Regenerated.
2218         * configure: Likewise.
2219         * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
2220         UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
2221
2222 2024-02-23  Richard Earnshaw  <rearnsha@arm.com>
2223
2224         PR target/108120
2225         * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
2226         Gate with ARM_HAVE_NEON_<MODE>_ARITH.
2227
2228 2024-02-23  Jakub Jelinek  <jakub@redhat.com>
2229
2230         PR rtl-optimization/114054
2231         * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
2232         temp variable instead of target parameter for result.
2233
2234 2024-02-23  Jakub Jelinek  <jakub@redhat.com>
2235
2236         PR tree-optimization/114040
2237         * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
2238         Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
2239         probability from likely to unlikely.  When handling the true true
2240         store, first cast to limb_access_type and then to l's type.
2241
2242 2024-02-23  Richard Biener  <rguenther@suse.de>
2243
2244         PR target/90785
2245         * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
2246
2247 2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>
2248
2249         PR other/109668
2250         * config/riscv/arch-canonicalize: Move to python3
2251         * config/riscv/multilib-generator: Likewise
2252
2253 2024-02-23  Palmer Dabbelt  <palmer@rivosinc.com>
2254
2255         * doc/invoke.texi: Document -mcpu.
2256
2257 2024-02-23  Lulu Cheng  <chenglulu@loongson.cn>
2258
2259         * configure: Regenerate.
2260         * configure.ac: Add parameter "--fatal-warnings" to assemble
2261         when checking whether the assemble support conditional branch
2262         relaxation.
2263
2264 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
2265
2266         PR c/114007
2267         * doc/extend.texi: (__extension__): Remove comments about scope
2268         tokens vs. two colons.
2269
2270 2024-02-22  Andrew Pinski  <quic_apinski@quicinc.com>
2271
2272         PR tree-optimization/109804
2273         * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
2274         DEMANGLE_COMPONENT_UNNAMED_TYPE.
2275
2276 2024-02-22  Richard Biener  <rguenther@suse.de>
2277
2278         PR tree-optimization/114048
2279         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
2280         can also produce -1 off.
2281
2282 2024-02-22  Richard Biener  <rguenther@suse.de>
2283
2284         PR tree-optimization/114027
2285         * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
2286         condition reduction classification only for single-element
2287         chains.
2288
2289 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
2290
2291         PR ipa/111960
2292         * profile-count.h (profile_count::dump): Remove overload with
2293         char * first argument.
2294         * profile-count.cc (profile_count::dump): Change overload with char *
2295         first argument which uses sprintf into the overfload with FILE *
2296         first argument and use fprintf instead.  Remove overload which wrapped
2297         it.
2298
2299 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
2300
2301         PR tree-optimization/113993
2302         * tree-call-cdce.cc (get_no_error_domain): Handle
2303         BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}.  Handle
2304         BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
2305         REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2306         the as the F128 suffixed cases, otherwise as non-suffixed ones.
2307         Handle BUILT_IN_{EXP,POW}10L for
2308         REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2309         as (-inf, 4932).
2310
2311 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
2312
2313         PR tree-optimization/114038
2314         * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
2315         loop exit condition if end is divisible by limb_prec.
2316
2317 2024-02-22  YunQiang Su  <syq@gcc.gnu.org>
2318
2319         * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
2320         problem of mabi=, mno-flush-func, mexplicit-relocs;
2321         add missing leading - of mbranch-cost option.
2322         * config/mips/mips.opt.urls: Regenerate.
2323
2324 2024-02-22  Kewen Lin  <linkw@linux.ibm.com>
2325
2326         PR target/109987
2327         * config/rs6000/constraints.md (we): Update internal doc without
2328         referring to option -mpower9-vector.
2329         * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
2330         special handlings.
2331         * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
2332         OTHER_P8_VECTOR_MASKS): Merge to ...
2333         (OTHER_VSX_VECTOR_MASKS): ... here.
2334         * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
2335         some error message handlings and explicit option mask adjustments on
2336         explicit option power{8,9}-vector conflicting with other options.
2337         (rs6000_print_isa_options): Update comments.
2338         (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
2339         related array items and handlings.
2340         * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
2341         special handlings.
2342         * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
2343         WarnRemoved.
2344         * doc/extend.texi: Remove documentation referring to option
2345         -mpower8-vector.
2346         * doc/invoke.texi: Remove documentation for option
2347         -mpower{8,9}-vector and adjust some documentation referring to them.
2348         * doc/md.texi: Update documentation for constraint we.
2349         * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
2350
2351 2024-02-22  Pan Li  <pan2.li@intel.com>
2352
2353         PR target/114017
2354         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
2355         the version to 0.12.
2356
2357 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
2358
2359         * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
2360
2361 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
2362             Robin Dapp  <rdapp.gcc@gmail.com>
2363
2364         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2365         (generic_ooo_vec_load): Ditto
2366         (generic_ooo_vec_store): Ditto
2367         (generic_ooo_vec_loadstore_seg): Ditto
2368         (generic_ooo_vec_alu): Ditto
2369         (generic_ooo_vec_fcmp): Ditto
2370         (generic_ooo_vec_imul): Ditto
2371         (generic_ooo_vec_fadd): Ditto
2372         (generic_ooo_vec_fmul): Ditto
2373         (generic_ooo_crypto): Ditto
2374         (generic_ooo_perm): Ditto
2375         (generic_ooo_vec_reduction): Ditto
2376         (generic_ooo_vec_ordered_reduction): Ditto
2377         (generic_ooo_vec_idiv): Ditto
2378         (generic_ooo_vec_float_divsqrt): Ditto
2379         (generic_ooo_vec_mask): Ditto
2380         (generic_ooo_vec_vesetvl): Ditto
2381         (generic_ooo_vec_setrm): Ditto
2382         (generic_ooo_vec_readlen): Ditto
2383         * config/riscv/riscv.md: Include generic-vector-ooo
2384         * config/riscv/generic-vector-ooo.md: New file. To here
2385
2386 2024-02-21  Edwin Lu  <ewlu@rivosinc.com>
2387
2388         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2389         (generic_ooo_branch): Ditto
2390         * config/riscv/generic.md (generic_sfb_alu): Ditto
2391         (generic_fmul_half): Ditto
2392         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2393         * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
2394         (sifive_7_popcount): Ditto
2395         * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
2396         * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
2397         * config/riscv/vector.md: Change rdfrm to fmove
2398         * config/riscv/zc.md: Change pushpop to load/store
2399
2400 2024-02-21  Jonathan Wakely  <jwakely@redhat.com>
2401
2402         * doc/invoke.texi (Warning Options): Fix typos.
2403
2404 2024-02-21  David Faust  <david.faust@oracle.com>
2405
2406         * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
2407         * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
2408         * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
2409
2410 2024-02-21  Martin Jambor  <mjambor@suse.cz>
2411
2412         PR ipa/113476
2413         * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
2414         initializers in the contructor.
2415         (ipa_node_params::~ipa_node_params): Release lattices as a vector.
2416         * ipa-cp.h: New file.
2417         * ipa-cp.cc: Include sreal.h and ipa-cp.h.
2418         (ipcp_value_source): Move to ipa-cp.h.
2419         (ipcp_value_base): Likewise.
2420         (ipcp_value): Likewise.
2421         (ipcp_lattice): Likewise.
2422         (ipcp_agg_lattice): Likewise.
2423         (ipcp_bits_lattice): Likewise.
2424         (ipcp_vr_lattice): Likewise.
2425         (ipcp_param_lattices): Likewise.
2426         (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
2427         (ipa_value_from_jfunc): Adjust a check for empty lattices.
2428         (ipa_context_from_jfunc): Likewise.
2429         (ipa_agg_value_from_jfunc): Likewise.
2430         (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
2431         (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
2432         just in contiguous memory.
2433         (ipcp_store_vr_results): Adjust a check for empty lattices.
2434         * auto-profile.cc: Include sreal.h and ipa-cp.h.
2435         * cgraph.cc: Likewise.
2436         * cgraphclones.cc: Likewise.
2437         * cgraphunit.cc: Likewise.
2438         * config/aarch64/aarch64.cc: Likewise.
2439         * config/i386/i386-builtins.cc: Likewise.
2440         * config/i386/i386-expand.cc: Likewise.
2441         * config/i386/i386-features.cc: Likewise.
2442         * config/i386/i386-options.cc: Likewise.
2443         * config/i386/i386.cc: Likewise.
2444         * config/rs6000/rs6000.cc: Likewise.
2445         * config/s390/s390.cc: Likewise.
2446         * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
2447         files to be included in gtype-desc.cc.
2448         * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
2449         * ipa-devirt.cc: Likewise.
2450         * ipa-fnsummary.cc: Likewise.
2451         * ipa-icf.cc: Likewise.
2452         * ipa-inline-analysis.cc: Likewise.
2453         * ipa-inline-transform.cc: Likewise.
2454         * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
2455         * ipa-modref.cc: Include sreal.h and ipa-cp.h.
2456         * ipa-param-manipulation.cc: Likewise.
2457         * ipa-predicate.cc: Likewise.
2458         * ipa-profile.cc: Likewise.
2459         * ipa-prop.cc: Likewise.
2460         (ipa_node_params_t::duplicate): Assert new lattices remain empty
2461         instead of setting them to NULL.
2462         * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
2463         * ipa-split.cc: Likewise.
2464         * ipa-sra.cc: Likewise.
2465         * ipa-strub.cc: Likewise.
2466         * ipa-utils.cc: Likewise.
2467         * ipa.cc: Likewise.
2468         * toplev.cc: Likewise.
2469         * tree-ssa-ccp.cc: Likewise.
2470         * tree-ssa-sccvn.cc: Likewise.
2471         * tree-vrp.cc: Likewise.
2472
2473 2024-02-21  Tamar Christina  <tamar.christina@arm.com>
2474
2475         * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
2476         Armv8.7-a.
2477
2478 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
2479
2480         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2481         Use aarch64_gen_compare_zero_and_branch rather than emitting
2482         a CBZ directly.
2483
2484 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
2485
2486         * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
2487         Remove duplicated call.
2488
2489 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
2490
2491         * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
2492         Check that each individual piece of state is shared in the same
2493         way, rather than using an aggregate check for PSTATE.ZA.
2494
2495 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
2496
2497         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2498         In the code that commits a lazy save, only zero ZA if the function
2499         has ZA state.  Similarly zero ZT0 if the function has ZT0 state.
2500
2501 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
2502
2503         * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
2504         directly inserting the associated sequence
2505         * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2506         ...here instead.
2507
2508 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
2509
2510         PR target/113995
2511         * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
2512         fold the SVE allocation into the initial allocation if the
2513         initial allocation includes a VG save.
2514
2515 2024-02-21  Richard Sandiford  <richard.sandiford@arm.com>
2516
2517         PR target/113220
2518         * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
2519         contain jumps even if called after initial RTL expansion.
2520         * mode-switching.cc: Include cfgbuild.h.
2521         (optimize_mode_switching): Allow the sequence returned by the
2522         emit hook to contain internal jumps.  Record which blocks
2523         contain such jumps and split the blocks at the end.
2524         * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
2525         non-debug insns when scanning the sequence.
2526
2527 2024-02-21  Tobias Burnus  <tburnus@baylibre.com>
2528
2529         * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
2530         * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
2531
2532 2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
2533
2534         * doc/invoke.texi (-mmcu): Add information about MCU specs.
2535
2536 2024-02-21  Dimitar Dimitrov  <dimitar@dinux.eu>
2537
2538         * doc/invoke.texi (-minrt): Clarify that main
2539         must take no arguments.
2540
2541 2024-02-20  Georg-Johann Lay  <avr@gjlay.de>
2542
2543         * config/avr/builtins.def: Use function prototypes of given size
2544         and signedness.
2545         * config/avr/avr.cc (avr_init_builtins): Adjust types required
2546         by builtins.def.
2547         * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
2548
2549 2024-02-20  Georg-Johann Lay  <avr@gjlay.de>
2550
2551         * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
2552         instead of @table.
2553
2554 2024-02-20  Will Hawkins  <hawkinsw@obs.cr>
2555
2556         * config/bpf/bpf.opt: Add help information for -mcpu.
2557
2558 2024-02-20  Richard Sandiford  <richard.sandiford@arm.com>
2559
2560         PR target/113805
2561         * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
2562         New pass.
2563         * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
2564         Declare.
2565         * config/aarch64/aarch64.md (is_call): New attribute.
2566         (*and<mode>3nr_compare0): Rename to...
2567         (@aarch64_and<mode>3nr_compare0): ...this.
2568         * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
2569         (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
2570         * config/aarch64/aarch64-speculation.cc: Update file comment to
2571         describe the new late pass.
2572         (aarch64_do_track_speculation): Handle is_call insns like other calls.
2573         (pass_track_speculation): Add an is_late member variable.
2574         (pass_track_speculation::gate): Run the late pass for streaming-
2575         compatible functions and the early pass for other functions.
2576         (make_pass_track_speculation): Update accordingly.
2577         (make_pass_late_track_speculation): New function.
2578         * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
2579         function.
2580         (aarch64_guard_switch_pstate_sm): Use it.
2581
2582 2024-02-19  Iain Sandoe  <iain@sandoe.co.uk>
2583
2584         * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
2585         Register these builtins with a pointer to uint64_t rather than unsigned
2586         DI mode.
2587
2588 2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>
2589
2590         PR target/113615
2591         * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
2592         Conditionalize on '!TARGET_RDNA2_PLUS'.
2593         * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
2594         (gcn_expand_reduc_scalar):
2595         'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
2596
2597 2024-02-19  Thomas Schwinge  <tschwinge@baylibre.com>
2598
2599         * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
2600         '__gfx90a__' target CPU definition.  Add some safeguards for the future.
2601
2602 2024-02-19  Richard Biener  <rguenther@suse.de>
2603
2604         PR rtl-optimization/54052
2605         * rtl-ssa/blocks.cc (function_info::place_phis): Filter
2606         local defs by LR_OUT.
2607
2608 2024-02-19  Jakub Jelinek  <jakub@redhat.com>
2609
2610         PR tree-optimization/113967
2611         * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
2612         in condition that @rpos is multiple of vector element size.
2613
2614 2024-02-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2615
2616         PR target/113696
2617         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
2618         Suppress vsetvl fusion.
2619
2620 2024-02-18  H.J. Lu  <hjl.tools@gmail.com>
2621
2622         PR target/113912
2623         * config/i386/i386.cc (ix86_can_use_push2pop2): New.
2624         (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
2625         (ix86_emit_save_regs): Don't generate push2 if
2626         ix86_can_use_push2pop2 return false.
2627         (ix86_expand_epilogue): Don't generate pop2 if
2628         ix86_can_use_push2pop2 return false.
2629
2630 2024-02-18  Georg-Johann Lay  <avr@gjlay.de>
2631
2632         * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
2633         Note on complete device support.
2634
2635 2024-02-18  Georg-Johann Lay  <avr@gjlay.de>
2636
2637         * doc/extend.texi (AVR Function Attributes): Fuse description
2638         of "signal" and "interrupt" attribute.  Link pseudo instruction.
2639
2640 2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>
2641
2642         * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
2643         symbol type conversions.
2644         (__cacop_d): Likewise.
2645         (__cpucfg): Likewise.
2646         (__asrtle_d): Likewise.
2647         (__asrtgt_d): Likewise.
2648         (__lddir_d): Likewise.
2649         (__ldpte_d): Likewise.
2650         (__crc_w_b_w): Likewise.
2651         (__crc_w_h_w): Likewise.
2652         (__crc_w_w_w): Likewise.
2653         (__crc_w_d_w): Likewise.
2654         (__crcc_w_b_w): Likewise.
2655         (__crcc_w_h_w): Likewise.
2656         (__crcc_w_w_w): Likewise.
2657         (__crcc_w_d_w): Likewise.
2658         (__csrrd_w): Likewise.
2659         (__csrwr_w): Likewise.
2660         (__csrxchg_w): Likewise.
2661         (__csrrd_d): Likewise.
2662         (__csrwr_d): Likewise.
2663         (__csrxchg_d): Likewise.
2664         (__iocsrrd_b): Likewise.
2665         (__iocsrrd_h): Likewise.
2666         (__iocsrrd_w): Likewise.
2667         (__iocsrrd_d): Likewise.
2668         (__iocsrwr_b): Likewise.
2669         (__iocsrwr_h): Likewise.
2670         (__iocsrwr_w): Likewise.
2671         (__iocsrwr_d): Likewise.
2672         (__frecipe_s): Likewise.
2673         (__frecipe_d): Likewise.
2674         (__frsqrte_s): Likewise.
2675         (__frsqrte_d): Likewise.
2676
2677 2024-02-18  Lulu Cheng  <chenglulu@loongson.cn>
2678
2679         * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
2680         function return value type to unsigned short.
2681
2682 2024-02-16  Edwin Lu  <ewlu@rivosinc.com>
2683
2684         * doc/sourcebuild.texi: add scan-assembler-bound
2685
2686 2024-02-16  Jason Merrill  <jason@redhat.com>
2687
2688         * gdbhooks.py: Fix regex syntax.
2689
2690 2024-02-16  Richard Biener  <rguenther@suse.de>
2691
2692         PR tree-optimization/113895
2693         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
2694         consistency checking when there are out-of-bound array
2695         accesses.  Allow -1 off when from an array reference with
2696         constant index.
2697
2698 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
2699
2700         PR target/106543
2701         * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
2702         pattern.
2703
2704 2024-02-16  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
2705
2706         * doc/sourcebuild.texi (Effective-Target Keywords, Other
2707         attribugs): Document linker_plugin.
2708         (Require Support): Document dg-require-linker-plugin.
2709
2710 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
2711
2712         PR target/109349
2713         * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
2714         * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
2715         (RISCV_MINOR_VERSION_BASE): Ditto.
2716         (RISCV_REVISION_VERSION_BASE): Ditto.
2717         * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
2718         rather than magic number.
2719         * config/riscv/riscv.h (riscv_arch_help): New.
2720         (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
2721         (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
2722         --print-supported-extensions.
2723         * config/riscv/riscv.opt (march=help): New.
2724         (print-supported-extensions): New.
2725         (-print-supported-extensions): New.
2726         * doc/invoke.texi (RISC-V Options): Document -march=help.
2727
2728 2024-02-16  Tejas Belagod  <tejas.belagod@arm.com>
2729
2730         PR target/113780
2731         * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
2732         for indirect calls with 4 or more arguments in pac-enabled functions.
2733
2734 2024-02-15  David Faust  <david.faust@oracle.com>
2735
2736         * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
2737         use ldxb instead of ldxh.
2738
2739 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
2740
2741         PR middle-end/113921
2742         * cfgrtl.h (prepend_insn_to_edge): New declaration.
2743         * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
2744         comment.
2745         (prepend_insn_to_edge): New function.
2746         * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
2747         insert_insn_on_edge.
2748
2749 2024-02-15  Richard Biener  <rguenther@suse.de>
2750
2751         PR tree-optimization/111156
2752         * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
2753         at the pattern stmt if any.
2754
2755 2024-02-15  Georg-Johann Lay  <avr@gjlay.de>
2756
2757         PR target/113927
2758         * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
2759         * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
2760         * config/avr/avr.cc (avr_adiw_reg_p): New function.
2761         (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
2762         Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
2763         * config/avr/avr.md: Same.
2764         (attr "isa") <tiny, no_tiny>: Remove.
2765         <adiw, no_adiw>: Add.
2766         (define_insn, define_insn_and_split): When an alternative has
2767         constraint "w", then set attribute "isa" to "adiw".
2768         * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
2769         Built-in define __AVR_HAVE_ADIW__.
2770         * doc/invoke.texi (AVR Options): Document it.
2771
2772 2024-02-15  Andrew Stubbs  <ams@baylibre.com>
2773
2774         * config/gcn/gcn-valu.md
2775         (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
2776         * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
2777         details are supported on RDNA devices.
2778
2779 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
2780
2781         PR middle-end/113508
2782         * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
2783         usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
2784         smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
2785         Add sentence about what the mode m is.
2786
2787 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
2788
2789         * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
2790         smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
2791         var.
2792
2793 2024-02-15  Richard Biener  <rguenther@suse.de>
2794
2795         * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
2796         stmts.
2797
2798 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
2799
2800         PR tree-optimization/113567
2801         * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
2802         _BitInt multiplication, division or modulo with
2803         SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
2804         force the affected inputs into a new SSA_NAME.
2805
2806 2024-02-14  Uros Bizjak  <ubizjak@gmail.com>
2807
2808         PR target/113871
2809         * config/i386/mmx.md (V248FI): New mode iterator.
2810         (V24FI_32): DItto.
2811         (vec_shl_<V248FI:mode>): New expander.
2812         (vec_shl_<V24FI_32:mode>): Ditto.
2813         (vec_shr_<V248FI:mode>): Ditto.
2814         (vec_shr_<V24FI_32:mode>): Ditto.
2815         * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
2816         (vec_shr_<V248FI:mode>): Ditto.
2817
2818 2024-02-14  Jan Hubicka  <jh@suse.cz>
2819
2820         PR tree-optimization/111054
2821         * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
2822
2823 2024-02-14  Tamar Christina  <tamar.christina@arm.com>
2824
2825         * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
2826
2827 2024-02-14  Richard Biener  <rguenther@suse.de>
2828
2829         PR tree-optimization/113910
2830         * bitmap.cc (bitmap_hash): Mix the full element "hash" to
2831         the hashval_t hash.
2832
2833 2024-02-14  Jakub Jelinek  <jakub@redhat.com>
2834
2835         * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
2836         (pp_integer_with_precision): For unsigned ptrdiff_t printing
2837         with u, o or x print ptrdiff_t argument converted to
2838         unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
2839
2840 2024-02-14  Richard Biener  <rguenther@suse.de>
2841
2842         PR middle-end/113576
2843         * expr.cc (do_store_flag): For vector bool compares of vectors
2844         with padding zero that.
2845         * dojump.cc (do_compare_and_jump): Likewise.
2846
2847 2024-02-14  Gerald Pfeifer  <gerald@pfeifer.com>
2848
2849         * doc/install.texi (Prerequisites): Update gettext link.
2850
2851 2024-02-13  H.J. Lu  <hjl.tools@gmail.com>
2852
2853         PR target/113876
2854         * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
2855         Return false if the incoming stack isn't 16-byte aligned.
2856
2857 2024-02-13  Tobias Burnus  <tburnus@baylibre.com>
2858
2859         PR middle-end/113904
2860         * omp-general.cc (struct omp_ts_info): Update for splitting of
2861         OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2862         * omp-selectors.h (enum omp_tp_type): Replace
2863         OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2864
2865 2024-02-13  Monk Chiang  <monk.chiang@sifive.com>
2866
2867         PR target/113742
2868         * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
2869         recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
2870
2871 2024-02-13  Richard Biener  <rguenther@suse.de>
2872
2873         PR tree-optimization/113895
2874         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
2875         offset to discover constant array indices in bits, handle
2876         COMPONENT_REF to bitfields.
2877
2878 2024-02-13  Richard Biener  <rguenther@suse.de>
2879
2880         PR tree-optimization/113831
2881         * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
2882         typo in comment.
2883
2884 2024-02-13  Richard Biener  <rguenther@suse.de>
2885
2886         PR tree-optimization/113902
2887         * tree-vect-loop.cc (move_early_exit_stmts): Track
2888         last_seen_vuse for VUSE updating.
2889
2890 2024-02-13  Tamar Christina  <tamar.christina@arm.com>
2891
2892         PR tree-optimization/113734
2893         * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
2894         an early break loop as partial.
2895
2896 2024-02-13  Richard Biener  <rguenther@suse.de>
2897
2898         PR tree-optimization/113898
2899         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
2900         missing accumulated off adjustment.
2901
2902 2024-02-13  Jakub Jelinek  <jakub@redhat.com>
2903
2904         * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
2905         instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
2906         it against UINT_MAX and ULONG_MAX.
2907
2908 2024-02-13  David Malcolm  <dmalcolm@redhat.com>
2909
2910         * diagnostic-core.h (emit_diagnostic_valist): Rename overload
2911         to...
2912         (emit_diagnostic_valist_meta): ...this.
2913         * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
2914         (emit_diagnostic_valist_meta): ...this.
2915
2916 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
2917
2918         PR tree-optimization/113849
2919         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
2920         fast path for widening casts where !m_upwards_2limb and lhs_type
2921         has precision which is a multiple of limb_prec.
2922
2923 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
2924
2925         PR c++/113674
2926         * attribs.cc (extract_attribute_substring): Remove.
2927         (lookup_scoped_attribute_spec): Don't call it.
2928
2929 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
2930
2931         * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
2932         and cast to fmt_size_t instead of %lu and cast to unsigned long.
2933
2934 2024-02-12  Christophe Lyon  <christophe.lyon@linaro.org>
2935
2936         * Makefile.in: Add no-info dependency.
2937         * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
2938         available.
2939         * configure: Regenerate.
2940
2941 2024-02-12  Iain Sandoe  <iain@sandoe.co.uk>
2942
2943         PR target/113855
2944         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
2945         available to all sub-targets.
2946         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2947         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2948
2949 2024-02-12  Richard Biener  <rguenther@suse.de>
2950
2951         PR tree-optimization/113831
2952         PR tree-optimization/108355
2953         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
2954         we see variable array indices and get_ref_base_and_extent
2955         can resolve those to constants fix up the ops to constants
2956         as well.
2957         (ao_ref_init_from_vn_reference): Use 'off' member for
2958         ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
2959         (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
2960
2961 2024-02-12  Pan Li  <pan2.li@intel.com>
2962
2963         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
2964         Replace args to arguments for misspelled term.
2965
2966 2024-02-12  Georg-Johann Lay  <avr@gjlay.de>
2967
2968         PR target/112944
2969         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
2970         <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
2971         when not linked with -mrodata-in-ram.
2972
2973 2024-02-12  Richard Biener  <rguenther@suse.de>
2974
2975         PR tree-optimization/113863
2976         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2977         Record crossed virtual PHIs.
2978         * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
2979         virtual PHIs.
2980
2981 2024-02-10  Marek Polacek  <polacek@redhat.com>
2982
2983         DR 2237
2984         PR c++/107126
2985         PR c++/97202
2986         * doc/invoke.texi: Document -Wtemplate-id-cdtor.
2987
2988 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
2989
2990         * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
2991         computation of idx for i == 4 of bitint_prec_huge.
2992
2993 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
2994
2995         PR middle-end/110754
2996         * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
2997         decls create PARM_DECL with pointer to original type, set
2998         TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
2999         DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
3000         (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
3001         wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
3002         (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
3003         of the var as argument.
3004
3005 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
3006
3007         * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
3008         size_t and precision 4 for ptrdiff_t.  Formatting fix.
3009         (pp_format): Document %{t,z}{d,i,u,o,x}.  Implement t and z modifiers.
3010         Formatting fixes.
3011         (test_pp_format): Test t and z modifiers.
3012         * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
3013
3014 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
3015
3016         * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
3017         sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
3018         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3019         * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
3020         and casts to fmt_size_t instead of "%ld" and casts to long.
3021         (print_value_expr_statistics, print_type_hash_statistics): Likewise.
3022         * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
3023         instead of "%lu" and casts to unsigned long.
3024         * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
3025         unsigned long.
3026         * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3027         and casts to fmt_size_t instead of "%ld" and casts to long.
3028         * cfgexpand.cc (dump_stack_var_partition): Use
3029         HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
3030         and casts to unsigned long.
3031         * gengtype.cc (adjust_field_rtx_def): Likewise.
3032         * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3033         and casts to fmt_size_t instead of "%ld" and casts to long.
3034         * postreload-gcse.cc (dump_hash_table): Likewise.
3035         * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
3036         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3037         (ggc_internal_alloc, ggc_free): Likewise.
3038         * genpreds.cc (write_lookup_constraint_1): Likewise.
3039         (write_insn_constraint_len): Likewise.
3040         * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
3041         and casts to fmt_size_t instead of "%ld" and casts to long.
3042         * varasm.cc (output_constant_pool_contents): Use
3043         HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
3044         * var-tracking.cc (dump_var): Likewise.
3045
3046 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
3047
3048         PR tree-optimization/113783
3049         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
3050         through VIEW_CONVERT_EXPR for final cast checks.  Handle
3051         VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
3052         INTEGER_TYPEs.
3053         (gimple_lower_bitint): Don't merge mergeable operations or other
3054         casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
3055         * expr.cc (expand_expr_real_1): Don't use convert_modes if either
3056         mode is BLKmode.
3057
3058 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
3059
3060         * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
3061         HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
3062         HOST_SIZE_T_PRINT_HEX_PURE): Define.
3063         * ira-conflicts.cc (build_conflict_bit_table): Use it.  Formatting
3064         fixes.
3065
3066 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
3067
3068         PR middle-end/113415
3069         * cfgexpand.cc (expand_asm_stmt): For asm goto, use
3070         duplicate_insn_chain to duplicate after_rtl_seq sequence instead
3071         of hand written loop with emit_insn of copy_insn and emit original
3072         after_rtl_seq on the last edge.
3073
3074 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
3075
3076         PR tree-optimization/113818
3077         * gimple-lower-bitint.cc (add_eh_edge): New function.
3078         (bitint_large_huge::handle_load,
3079         bitint_large_huge::lower_mergeable_stmt,
3080         bitint_large_huge::lower_muldiv_stmt): Use it.
3081
3082 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
3083
3084         PR tree-optimization/113774
3085         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
3086         emit any comparison if m_first and low + 1 is equal to
3087         m_upwards_2limb, simplify condition for that.  If not
3088         single_comparison, not m_first and we can prove that the idx <= low
3089         comparison will be always true, emit instead of idx <= low
3090         comparison low <= low such that cfg cleanup will optimize it at
3091         the end of the pass.
3092
3093 2024-02-08  Aldy Hernandez  <aldyh@redhat.com>
3094
3095         PR tree-optimization/113735
3096         * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
3097         limit_check().
3098
3099 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
3100
3101         * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
3102         (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
3103
3104 2024-02-08  H.J. Lu  <hjl.tools@gmail.com>
3105
3106         PR target/113711
3107         PR target/113733
3108         * config/i386/constraints.md: List all constraints with j prefix.
3109         (j>): Change auto-dec to auto-inc in documentation.
3110         (je): Changed to a memory constraint with APX NDD TLS operand
3111         check.
3112         (jM): New memory constraint for APX NDD instructions.
3113         (jO): Likewise.
3114         * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
3115         * config/i386/i386.cc (x86_poff_operand_p): Likewise.
3116         * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
3117         (*add<mode>_1[SWI48]): Use je and jM.
3118         (addsi_1_zext): Use jM.
3119         (*addv<dwi>4_doubleword_1[DWI]): Likewise.
3120         (*sub<mode>_1[SWI]): Use jM.
3121         (@add<mode>3_cc_overflow_1[SWI]): Likewise.
3122         (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
3123         (*and<dwi>3_doubleword): Likewise.
3124         (*anddi_1): Use jM.
3125         (*andsi_1_zext): Likewise.
3126         (*and<mode>_1[SWI24]): Likewise.
3127         (*<code><dwi>3_doubleword[any_or]): Use rjO
3128         (*code<mode>_1[any_or SWI248]): Use jM.
3129         (*<code>si_1_zext[zero_extend + any_or]): Likewise.
3130         * config/i386/predicates.md (apx_ndd_memory_operand): New.
3131         (apx_ndd_add_memory_operand): Likewise.
3132
3133 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
3134
3135         PR target/113824
3136         * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
3137         * doc/avr-mmcu.texi: Rebuild.
3138
3139 2024-02-08  Tamar Christina  <tamar.christina@arm.com>
3140
3141         PR tree-optimization/113808
3142         * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
3143         value cross iterations.
3144
3145 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
3146
3147         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
3148         defines __AVR_PM_BASE_ADDRESS__ if the core has it.
3149
3150 2024-02-08  Richard Biener  <rguenther@suse.de>
3151
3152         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3153         Revert last change to dr_may_alias_p.
3154
3155 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
3156
3157         * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
3158         cc1_rodata_in_ram.  Rename spec link_misc to link_rodata_in_ram.
3159         Remove spec asm_misc.
3160         * config/avr/specs.h: Same.
3161
3162 2024-02-08  Pan Li  <pan2.li@intel.com>
3163
3164         PR target/113766
3165         * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
3166         sure the c.arg_num is >= 2 before checking.
3167         (struct build_frm_base): Ditto.
3168         (struct narrow_alu_def): Ditto.
3169
3170 2024-02-07  Richard Biener  <rguenther@suse.de>
3171
3172         PR tree-optimization/113796
3173         * tree-if-conv.cc (combine_blocks): Wipe range-info before
3174         replacing PHIs and inserting predicates.
3175
3176 2024-02-07  Roger Sayle  <roger@nextmovesoftware.com>
3177             Uros Bizjak  <ubizjak@gmail.com>
3178
3179         PR target/113690
3180         * config/i386/i386-features.cc (timode_convert_cst): New helper
3181         function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
3182         CONST_VECTOR.
3183         (timode_scalar_chain::convert_op): Use timode_convert_cst.
3184         (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
3185         Use timode_convert_cst.
3186
3187 2024-02-07  Victor Do Nascimento  <victor.donascimento@arm.com>
3188
3189         * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
3190         * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
3191         (AARCH64_FL_DEBUGv8p9): Likewise.
3192         (AARCH64_FL_FGT2): Likewise.Likewise.
3193         (AARCH64_FL_ITE): Likewise.
3194         (AARCH64_FL_PFAR): Likewise.
3195         (AARCH64_FL_PMUv3_ICNTR): Likewise.
3196         (AARCH64_FL_PMUv3_SS): Likewise.
3197         (AARCH64_FL_PMUv3p9): Likewise.
3198         (AARCH64_FL_RASv2): Likewise.
3199         (AARCH64_FL_S1PIE): Likewise.
3200         (AARCH64_FL_S1POE): Likewise.
3201         (AARCH64_FL_S2PIE): Likewise.
3202         (AARCH64_FL_S2POE): Likewise.
3203         (AARCH64_FL_SCTLR2): Likewise.
3204         (AARCH64_FL_SEBEP): Likewise.
3205         (AARCH64_FL_SPE_FDS): Likewise.
3206         (AARCH64_FL_TCR2): Likewise.
3207
3208 2024-02-07  Richard Biener  <rguenther@suse.de>
3209
3210         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3211         Only check whether reads are in-bound in places that are not safe.
3212         Fix dependence check.  Add missing newline.  Clarify comments.
3213
3214 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
3215
3216         PR tree-optimization/113750
3217         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
3218         for single predecessor when doing early break vect.
3219         * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
3220         after labels.
3221
3222 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
3223
3224         PR tree-optimization/113731
3225         * gimple-iterator.cc (gsi_move_before): Take new parameter for update
3226         method.
3227         * gimple-iterator.h (gsi_move_before): Default new param to
3228         GSI_SAME_STMT.
3229         * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
3230         GSI_NEW_STMT.
3231
3232 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
3233
3234         PR tree-optimization/113756
3235         * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
3236         use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
3237         of lh_bits value and mask.
3238
3239 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
3240
3241         PR tree-optimization/113753
3242         * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
3243         UNSIGNED rather than SIGNED.  If high or needs_overflow and prec is
3244         not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
3245         so that they start with r[half_blocks_needed] lowest bit.  Fix up
3246         computation of top mask for SIGNED.
3247
3248 2024-02-07  Pan Li  <pan2.li@intel.com>
3249
3250         PR target/113766
3251         * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
3252         the signature of func.
3253         * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
3254         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
3255         overloaded func with empty args error.
3256
3257 2024-02-06  H.J. Lu  <hjl.tools@gmail.com>
3258
3259         PR target/113689
3260         * config/i386/i386.cc (x86_64_select_profile_regnum): Return
3261         R10_REG after sorry.
3262
3263 2024-02-06  Andrew Carlotti  <andrew.carlotti@arm.com>
3264
3265         * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
3266         Move before new caller, and add ".default" suffix.
3267         (get_suffixed_assembler_name): New.
3268         (make_resolver_func): Use get_suffixed_assembler_name.
3269         (aarch64_generate_version_dispatcher_body): Redo name mangling.
3270
3271 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
3272
3273         PR target/113763
3274         * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
3275         element from std::pair<unsigned int, char> to an unnamed struct.
3276         Adjust uses of tile range variable.
3277
3278 2024-02-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3279
3280         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
3281         (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
3282
3283 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
3284
3285         PR sanitizer/110676
3286         * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
3287         reset maxlen to sizetype maximum.
3288
3289 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
3290
3291         PR tree-optimization/113736
3292         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
3293         var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
3294
3295 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
3296
3297         PR tree-optimization/113759
3298         * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
3299         or from_unsignedN differs from properties of typeN, update typeN
3300         to build_nonstandard_integer_type.  If TREE_TYPE (rhsN) is not
3301         uselessly convertible to typeN, convert it using fold_convert or
3302         build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
3303         (convert_plusminus_to_widen): Likewise.
3304
3305 2024-02-06  Tejas Belagod  <tejas.belagod@arm.com>
3306
3307         PR target/112577
3308         * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
3309         vector structure modes correctly.
3310
3311 2024-02-05  Christoph Müllner  <christoph.muellner@vrull.eu>
3312
3313         * config/riscv/thead.cc (th_print_operand_address): Fix compiler
3314         warning.
3315
3316 2024-02-05  H.J. Lu  <hjl.tools@gmail.com>
3317
3318         PR target/113689
3319         * config/i386/i386.cc (x86_64_select_profile_regnum): New.
3320         (x86_function_profiler): Call x86_64_select_profile_regnum to
3321         get a scratch register for large model profiling.
3322
3323 2024-02-05  Richard Ball  <richard.ball@arm.com>
3324
3325         * config/arm/arm.cc (arm_output_mi_thunk): Emit
3326         insn for bti_c when bti is enabled.
3327
3328 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
3329
3330         * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
3331         neg.
3332
3333 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
3334
3335         * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
3336         (neg<mode>2): Change the mode iterator from MSA to IMSA because
3337         in FP arithmetic we cannot use (0 - x) for -x.
3338         (neg<mode>2): New define_insn to implement FP vector negation,
3339         using a bnegi instruction to negate the sign bit.
3340
3341 2024-02-05  Richard Biener  <rguenther@suse.de>
3342
3343         PR tree-optimization/113707
3344         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
3345         checking the avail set treat out-of-region defines as
3346         available.
3347
3348 2024-02-05  Richard Biener  <rguenther@suse.de>
3349
3350         * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
3351         the default mode when building a pointer.
3352
3353 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
3354
3355         PR tree-optimization/113737
3356         * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
3357         has just a single label, remove it and make single successor edge
3358         EDGE_FALLTHRU.
3359
3360 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
3361
3362         PR target/113059
3363         * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
3364         Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
3365         df_analyze call.
3366
3367 2024-02-05  Richard Biener  <rguenther@suse.de>
3368
3369         PR target/113255
3370         * config/i386/i386-expand.cc
3371         (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
3372         Use a new pseudo for the skipped number of bytes.
3373
3374 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
3375
3376         * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
3377         * doc/invoke.texi (RISC-V Options): Add sifive-p450,
3378         sifive-p670.
3379
3380 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
3381
3382         * config/riscv/riscv.md: Include sifive-p400.md.
3383         * config/riscv/sifive-p400.md: New file.
3384         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3385         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3386         Add sifive_p400.
3387         * config/riscv/riscv.cc (sifive_p400_tune_info): New.
3388         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3389         * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
3390
3391 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
3392
3393         * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
3394         Add missing ":SI" to the match_operator.
3395
3396 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
3397
3398         * config/xtensa/xtensa.md (SHI): New mode iterator.
3399         (2 split patterns related to constsynth):
3400         Change to also accept HImode operands.
3401
3402 2024-02-04  Jeff Law  <jlaw@ventanamicro.com>
3403
3404         * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
3405         similarly.
3406
3407 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
3408
3409         * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
3410         incorrect expand.
3411         * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
3412         (elmsgnbit): Likewise.
3413         (neg<mode:FVEC>2): New define_insn.
3414         * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
3415         are now instantiated in simd.md.
3416
3417 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
3418
3419         * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
3420         use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
3421         MAX_MACHINE_MODE.
3422
3423 2024-02-04  Li Wei  <liwei@loongson.cn>
3424
3425         * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
3426         (loongarch_expand_vselect_vconcat): Ditto.
3427         (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
3428         all 128-bit constant permutation situations.
3429         (loongarch_expand_lsx_shuffle): Adjust and rename function name.
3430         (loongarch_is_imm_set_shuffle): Renamed function name.
3431         (loongarch_expand_vec_perm_even_odd): Function forward declaration.
3432         (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
3433         extract-even and extract-odd permutations.
3434         (loongarch_is_odd_extraction): Delete.
3435         (loongarch_is_even_extraction): Ditto.
3436         (loongarch_expand_vec_perm_const): Adjust.
3437
3438 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
3439
3440         PR middle-end/113722
3441         * wide-int.cc (wi::bswap_large): Rename third argument from
3442         len to xlen and adjust use in safe_uhwi.  Add len variable, set
3443         it to BLOCKS_NEEDED (precision) and use it for clearing of val
3444         and as canonize argument.  Clear val using memset instead of
3445         a loop.
3446
3447 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
3448
3449         * ggc-common.cc (gt_pch_save): Allow addr to be equal to
3450         mmi.preferred_base + mmi.size - sizeof (void *).
3451
3452 2024-02-03  Xi Ruoyao  <xry111@xry111.site>
3453
3454         * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
3455         * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
3456         the ODR-violating locale declaration.
3457
3458 2024-02-02  Tamar Christina  <tamar.christina@arm.com>
3459
3460         PR tree-optimization/113588
3461         PR tree-optimization/113467
3462         * tree-vect-data-refs.cc
3463         (vect_analyze_data_ref_dependence):  Choose correct dest and fix checks.
3464         (vect_analyze_early_break_dependences): Update comments.
3465
3466 2024-02-02  John David Anglin  <danglin@gcc.gnu.org>
3467
3468         PR target/59778
3469         * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
3470         and PA_BUILTIN_SET_FPSR builtins.
3471         * (pa_builtins_icode): Declare.
3472         * (def_builtin, pa_fpu_init_builtins): New.
3473         * (pa_init_builtins): Initialize FPU builtins.
3474         * (pa_builtin_decl, pa_expand_builtin_1): New.
3475         * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
3476         PA_BUILTIN_SET_FPSR builtins.
3477         * (pa_atomic_assign_expand_fenv): New.
3478         * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
3479         UNSPECV constants.
3480         (get_fpsr, put_fpsr): New expanders.
3481         (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
3482         insn patterns.
3483
3484 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3485
3486         PR target/113697
3487         * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
3488
3489 2024-02-02  Jonathan Wakely  <jwakely@redhat.com>
3490
3491         * doc/extend.texi (Common Type Attributes): Fix typo in
3492         description of hardbool.
3493
3494 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
3495
3496         PR tree-optimization/113692
3497         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
3498         from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
3499         final_cast_p.
3500
3501 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
3502
3503         PR middle-end/113699
3504         * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
3505         uninitialized large/huge _BitInt SSA_NAME inputs.
3506
3507 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
3508
3509         PR middle-end/113705
3510         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
3511         around wi::to_wide in order to compare value in prec precision.
3512
3513 2024-02-02  Lehua Ding  <lehua.ding@rivai.ai>
3514
3515         Revert:
3516         2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3517
3518         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3519
3520 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3521
3522         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3523
3524 2024-02-02  Pan Li  <pan2.li@intel.com>
3525
3526         * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
3527         (riscv_pass_by_reference): Ditto.
3528         (riscv_fntype_abi): Ditto.
3529
3530 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3531
3532         * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
3533         (pre_vsetvl::cleaup): Remove vsetvl_pre.
3534         (pre_vsetvl::remove_vsetvl_pre_insns): New function.
3535
3536 2024-02-02  Jiahao Xu  <xujiahao@loongson.cn>
3537
3538         * config/loongarch/larchintrin.h
3539         (__frecipe_s): Update function return type.
3540         (__frecipe_d): Ditto.
3541         (__frsqrte_s): Ditto.
3542         (__frsqrte_d): Ditto.
3543
3544 2024-02-02  Li Wei  <liwei@loongson.cn>
3545
3546         * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
3547         (loongarch_vector_costs::add_stmt_cost): Adjust.
3548
3549 2024-02-02  Xi Ruoyao  <xry111@xry111.site>
3550
3551         * config/loongarch/loongarch.md (unspec): Add
3552         UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
3553         (la_pcrel64_two_parts): New define_insn.
3554         * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
3555         typo in the comment.
3556         (loongarch_call_tls_get_addr): If -mcmodel=extreme
3557         -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
3558         addressing the TLS symbol and __tls_get_addr.  Emit an REG_EQUAL
3559         note to allow CSE addressing __tls_get_addr.
3560         (loongarch_legitimize_tls_address): If -mcmodel=extreme
3561         -mexplicit-relocs={always,auto}, address TLS IE symbols with
3562         la_pcrel64_two_parts.
3563         (loongarch_split_symbol): If -mcmodel=extreme
3564         -mexplicit-relocs={always,auto}, address symbols with
3565         la_pcrel64_two_parts.
3566         (loongarch_output_mi_thunk): Clean up unreachable code.  If
3567         -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
3568         thunks with la_pcrel64_two_parts.
3569
3570 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
3571
3572         * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
3573         Add support for call36.
3574
3575 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
3576
3577         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3578         When the code model of the symbol is extreme and -mexplicit-relocs=auto,
3579         the macro instruction loading symbol address is not applicable.
3580         (loongarch_call_tls_get_addr): Adjust code.
3581         (loongarch_legitimize_tls_address): Likewise.
3582
3583 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
3584
3585         * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
3586         Add function declaration.
3587         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3588         For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
3589         is not allowed
3590         (loongarch_load_tls): Added macro support in extreme mode.
3591         (loongarch_call_tls_get_addr): Likewise.
3592         (loongarch_legitimize_tls_address): Likewise.
3593         (loongarch_force_address): Likewise.
3594         (loongarch_legitimize_move): Likewise.
3595         (loongarch_output_mi_thunk): Likewise.
3596         (loongarch_option_override_internal): Remove the code that detects
3597         explicit relocs status.
3598         (loongarch_handle_model_attribute): Likewise.
3599         * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
3600         * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
3601         (symbolic_off64_or_reg_operand): Likewise.
3602
3603 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
3604
3605         * config/loongarch/loongarch.cc (loongarch_load_tls):
3606         Load all types of tls symbols through one function.
3607         (loongarch_got_load_tls_gd): Delete.
3608         (loongarch_got_load_tls_ld): Delete.
3609         (loongarch_got_load_tls_ie): Delete.
3610         (loongarch_got_load_tls_le): Delete.
3611         (loongarch_call_tls_get_addr): Modify the called function name.
3612         (loongarch_legitimize_tls_address): Likewise.
3613         * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
3614         (@load_tls<mode>): New template.
3615         (@got_load_tls_ld<mode>): Delete.
3616         (@got_load_tls_le<mode>): Delete.
3617         (@got_load_tls_ie<mode>): Delete.
3618
3619 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
3620
3621         * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
3622         (loongarch_legitimize_address): Add logical transformation code.
3623
3624 2024-02-01  Marek Polacek  <polacek@redhat.com>
3625
3626         * doc/invoke.texi: Update -Wdangling-reference documentation.
3627
3628 2024-02-01  Uros Bizjak  <ubizjak@gmail.com>
3629
3630         PR target/113701
3631         * config/i386/i386.md (*cmp<dwi>_doubleword):
3632         Do not force SUBREG pieces to pseudos.
3633
3634 2024-02-01  John David Anglin  <danglin@gcc.gnu.org>
3635
3636         * config/pa/pa.md (atomic_storedi_1): Fix bug in
3637         alternative 1.
3638
3639 2024-02-01  Georg-Johann Lay  <avr@gjlay.de>
3640
3641         * config/avr/avr.cc: Tabify.
3642
3643 2024-02-01  Richard Ball  <richard.ball@arm.com>
3644
3645         PR tree-optimization/111268
3646         * tree-vect-slp.cc (vectorizable_slp_permutation_1):
3647         Add variable-length check for vector input arguments
3648         to a function.
3649
3650 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
3651
3652         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
3653         hard-code number of SGPR/VGPR/AVGPR registers.
3654         * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
3655         SGPR/VGPR/AVGPR registers.
3656
3657 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
3658
3659         * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
3660         attribute, and include sifive-p600.md.
3661         * config/riscv/generic-ooo.md: Update type attribute.
3662         * config/riscv/generic.md: Update type attribute.
3663         * config/riscv/sifive-7.md: Update type attribute.
3664         * config/riscv/sifive-p600.md: New file.
3665         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3666         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3667         Add sifive_p600.
3668         * config/riscv/riscv.cc (sifive_p600_tune_info): New.
3669         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3670         * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
3671
3672 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
3673
3674         * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
3675         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
3676         * config/riscv/riscv.opt: New macro for 7 new unprivileged
3677         extensions.
3678         * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
3679         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
3680
3681 2024-02-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
3682
3683         * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
3684         -static-libasan.  Add missing whitespace.
3685
3686 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
3687
3688         * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
3689         (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
3690         Don't 'define_constants'.
3691
3692 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
3693
3694         * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
3695
3696 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
3697
3698         * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
3699         [TARGET_RDNA3]: Adjust.
3700
3701 2024-02-01  Richard Biener  <rguenther@suse.de>
3702
3703         PR tree-optimization/113693
3704         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
3705         data when available.
3706
3707 2024-02-01  Jakub Jelinek  <jakub@redhat.com>
3708             Jason Merrill  <jason@redhat.com>
3709
3710         PR c++/113531
3711         * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
3712         on variables which were promoted to TREE_STATIC.
3713
3714 2024-02-01  Roger Sayle  <roger@nextmovesoftware.com>
3715             Richard Biener  <rguenther@suse.de>
3716
3717         PR target/113560
3718         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
3719         information via tree_non_zero_bits to check if this operand
3720         is suitably extended for a widening (or highpart) multiplication.
3721         (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
3722         isn't already of the claimed type.
3723
3724 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
3725
3726         Revert:
3727         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
3728
3729         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3730         (generic_ooo_branch): ditto
3731         * config/riscv/generic.md (generic_sfb_alu): ditto
3732         (generic_fmul_half): ditto
3733         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3734         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3735         (sifive_7_popcount): ditto
3736         * config/riscv/vector.md: change rdfrm to fmove
3737         * config/riscv/zc.md: change pushpop to load/store
3738
3739 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
3740
3741         Revert:
3742         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
3743                     Robin Dapp  <rdapp.gcc@gmail.com>
3744
3745         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3746         (generic_ooo_vec_load): ditto
3747         (generic_ooo_vec_store): ditto
3748         (generic_ooo_vec_loadstore_seg): ditto
3749         (generic_ooo_vec_alu): ditto
3750         (generic_ooo_vec_fcmp): ditto
3751         (generic_ooo_vec_imul): ditto
3752         (generic_ooo_vec_fadd): ditto
3753         (generic_ooo_vec_fmul): ditto
3754         (generic_ooo_crypto): ditto
3755         (generic_ooo_perm): ditto
3756         (generic_ooo_vec_reduction): ditto
3757         (generic_ooo_vec_ordered_reduction): ditto
3758         (generic_ooo_vec_idiv): ditto
3759         (generic_ooo_vec_float_divsqrt): ditto
3760         (generic_ooo_vec_mask): ditto
3761         (generic_ooo_vec_vesetvl): ditto
3762         (generic_ooo_vec_setrm): ditto
3763         (generic_ooo_vec_readlen): ditto
3764         * config/riscv/riscv.md: include generic-vector-ooo
3765         * config/riscv/generic-vector-ooo.md: New file. to here
3766
3767 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
3768
3769         Revert:
3770         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
3771
3772         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3773
3774 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
3775
3776         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3777
3778 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
3779             Robin Dapp  <rdapp.gcc@gmail.com>
3780
3781         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3782         (generic_ooo_vec_load): ditto
3783         (generic_ooo_vec_store): ditto
3784         (generic_ooo_vec_loadstore_seg): ditto
3785         (generic_ooo_vec_alu): ditto
3786         (generic_ooo_vec_fcmp): ditto
3787         (generic_ooo_vec_imul): ditto
3788         (generic_ooo_vec_fadd): ditto
3789         (generic_ooo_vec_fmul): ditto
3790         (generic_ooo_crypto): ditto
3791         (generic_ooo_perm): ditto
3792         (generic_ooo_vec_reduction): ditto
3793         (generic_ooo_vec_ordered_reduction): ditto
3794         (generic_ooo_vec_idiv): ditto
3795         (generic_ooo_vec_float_divsqrt): ditto
3796         (generic_ooo_vec_mask): ditto
3797         (generic_ooo_vec_vesetvl): ditto
3798         (generic_ooo_vec_setrm): ditto
3799         (generic_ooo_vec_readlen): ditto
3800         * config/riscv/riscv.md: include generic-vector-ooo
3801         * config/riscv/generic-vector-ooo.md: New file. to here
3802
3803 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
3804
3805         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3806         (generic_ooo_branch): ditto
3807         * config/riscv/generic.md (generic_sfb_alu): ditto
3808         (generic_fmul_half): ditto
3809         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3810         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3811         (sifive_7_popcount): ditto
3812         * config/riscv/vector.md: change rdfrm to fmove
3813         * config/riscv/zc.md: change pushpop to load/store
3814
3815 2024-02-01  Andrew Pinski  <quic_apinski@quicinc.com>
3816
3817         PR target/113657
3818         * config/aarch64/aarch64-simd.md (split for movv8di):
3819         For strict aligned mode, use DImode instead of TImode.
3820
3821 2024-01-31  Robin Dapp  <rdapp@ventanamicro.com>
3822
3823         PR middle-end/113607
3824         * match.pd: Make sure else values match when folding a
3825         vec_cond into a conditional operation.
3826
3827 2024-01-31  Marek Polacek  <polacek@redhat.com>
3828
3829         * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
3830
3831 2024-01-31  Tamar Christina  <tamar.christina@arm.com>
3832             Matthew Malcomson  <matthew.malcomson@arm.com>
3833
3834         PR sanitizer/112644
3835         * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
3836         memcmp.
3837         * builtins.cc (expand_builtin): Include HWASAN when checking for
3838         builtin inlining.
3839
3840 2024-01-31  Richard Biener  <rguenther@suse.de>
3841
3842         PR middle-end/110176
3843         * match.pd (zext (bool) <= (int) 4294967295u): Make sure
3844         to match INTEGER_CST only without outstanding conversion.
3845
3846 2024-01-31  Alex Coplan  <alex.coplan@arm.com>
3847
3848         PR target/111677
3849         * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
3850         V16QImode for the full 16-byte FPR saves in the vector PCS case.
3851
3852 2024-01-31  Richard Biener  <rguenther@suse.de>
3853
3854         PR tree-optimization/111444
3855         * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
3856         vn_reference_lookup_2 when optimistically skipping may-defs.
3857
3858 2024-01-31  Richard Biener  <rguenther@suse.de>
3859
3860         PR tree-optimization/113630
3861         * tree-ssa-pre.cc (compute_avail): Avoid registering a
3862         reference with a representation with not matching base
3863         access size.
3864
3865 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
3866
3867         PR rtl-optimization/113656
3868         * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
3869         <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
3870
3871 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
3872
3873         PR debug/113637
3874         * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
3875         with BLKmode are larger than DWARF2_ADDR_SIZE.
3876
3877 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
3878
3879         PR tree-optimization/113639
3880         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
3881         For VIEW_CONVERT_EXPR set rhs1 to its operand.
3882
3883 2024-01-31  Richard Biener  <rguenther@suse.de>
3884
3885         PR tree-optimization/113670
3886         * tree-vect-data-refs.cc (vect_check_gather_scatter):
3887         Make sure we can take the address of the reference base.
3888
3889 2024-01-31  Georg-Johann Lay  <avr@gjlay.de>
3890
3891         * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
3892         ATA5835, ATtiny64AUTO, ATA5700M322.
3893         * doc/avr-mmcu.texi: Rebuild.
3894
3895 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
3896
3897         PR debug/113394
3898         * ipa-strub.cc (build_ref_type_for): Drop nonaliased.  Adjust
3899         caller.
3900
3901 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
3902
3903         PR middle-end/112917
3904         PR middle-end/113100
3905         * builtins.cc (expand_builtin_stack_address): Use
3906         STACK_ADDRESS_OFFSET.
3907         * doc/extend.texi (__builtin_stack_address): Adjust.
3908         * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
3909         * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
3910         * doc/tm.texi: Rebuilt.
3911
3912 2024-01-31  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3913
3914         PR target/113495
3915         * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
3916         (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
3917         (pre_vsetvl::compute_transparent): New function.
3918         (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
3919
3920 2024-01-30  Fangrui Song  <maskray@google.com>
3921
3922         PR target/105576
3923         * config/i386/constraints.md: Define constraint "Ws".
3924         * doc/md.texi: Document it.
3925
3926 2024-01-30  Marek Polacek  <polacek@redhat.com>
3927
3928         PR c++/110358
3929         PR c++/109640
3930         * doc/invoke.texi: Update -Wdangling-reference description.
3931
3932 2024-01-30  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
3933
3934         * config/xtensa/constraints.md (R, T, U):
3935         Change define_constraint to define_memory_constraint.
3936         * config/xtensa/predicates.md (move_operand): Don't check that a
3937         constant pool operand size is a multiple of UNITS_PER_WORD.
3938         * config/xtensa/xtensa.cc
3939         (xtensa_lra_p, TARGET_LRA_P): Remove.
3940         (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
3941         clause as it can no longer be true.
3942         (fixup_subreg_mem): Drop function.
3943         (xtensa_output_integer_literal_parts): Consider 16-bit wide
3944         constants.
3945         (xtensa_legitimate_constant_p): Add short-circuit path for
3946         integer load instructions. Don't check that mode size is
3947         at least UNITS_PER_WORD.
3948         * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
3949         rather reload_in_progress and reload_completed.
3950         (doloop_end): Drop operand 2.
3951         (movhi_internal): Add alternative loading constant from a
3952         literal pool.
3953         (define_split for DI register_operand): Don't limit to
3954         !TARGET_AUTO_LITPOOLS.
3955         * config/xtensa/xtensa.opt (mlra): Change to no effect.
3956
3957 2024-01-30  Pan Li  <pan2.li@intel.com>
3958
3959         * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
3960         calculate the gpr count required by vls mode.
3961         (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
3962         (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
3963         for vls mode.
3964         (riscv_get_arg_info): Add vls mode handling.
3965         (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
3966
3967 2024-01-30  Richard Biener  <rguenther@suse.de>
3968
3969         PR tree-optimization/113659
3970         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3971         Handle main exit without virtual use.
3972
3973 2024-01-30  Christoph Müllner  <christoph.muellner@vrull.eu>
3974
3975         * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
3976
3977 2024-01-30  Iain Sandoe  <iain@sandoe.co.uk>
3978
3979         PR libgcc/113403
3980         * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
3981         (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
3982         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
3983         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
3984         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
3985         * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
3986
3987 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
3988
3989         PR target/113623
3990         * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
3991         Mark all registers that occur in addresses as needing a GPR.
3992
3993 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
3994
3995         PR target/113636
3996         * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
3997         the containing insn as an extra parameter.  Reset debug instructions
3998         if they reference a register that is no longer used by real insns.
3999         (early_ra::apply_allocation): Update calls accordingly.
4000
4001 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
4002
4003         PR tree-optimization/113603
4004         * tree-ssa-strlen.cc (strlen_pass::handle_store): After
4005         count_nonzero_bytes call refetch si using get_strinfo in case it
4006         has been unshared in the meantime.
4007
4008 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
4009
4010         PR middle-end/101195
4011         * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
4012         fit into unsigned HOST_WIDE_INT, return constm1_rtx.
4013
4014 2024-01-30  Jin Ma  <jinma@linux.alibaba.com>
4015
4016         * config/riscv/thead.cc (th_print_operand_address): Change %ld
4017         to %lld.
4018
4019 2024-01-29  Manos Anagnostakis  <manos.anagnostakis@vrull.eu>
4020             Manolis Tsamis  <manolis.tsamis@vrull.eu>
4021             Philipp Tomsich  <philipp.tomsich@vrull.eu>
4022
4023         * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
4024         * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
4025         Likewise.
4026         * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
4027         Call on framework moved later.
4028
4029 2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>
4030
4031         * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
4032         instruction in naked function epilogues.
4033
4034 2024-01-29  YunQiang Su  <syq@gcc.gnu.org>
4035
4036         PR target/113655
4037         * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
4038         gcc_cv_as_mips_explicit_relocs.
4039         * configure: Regnerated.
4040
4041 2024-01-29  Matthieu Longo  <matthieu.longo@arm.com>
4042
4043         PR target/108933
4044         * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
4045         Correct generated RTL.
4046         (arm_rev16si2_alt1): Correctly handle conditional execution.
4047         (arm_rev16si2_alt2): Likewise.
4048
4049 2024-01-29  Richard Biener  <rguenther@suse.de>
4050
4051         PR middle-end/113622
4052         * expr.cc (expand_assignment): Spill hard registers if
4053         we index them with a variable offset.
4054
4055 2024-01-29  Richard Biener  <rguenther@suse.de>
4056
4057         PR middle-end/113622
4058         * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
4059         Also allow DECL_HARD_REGISTER variables.
4060
4061 2024-01-29  Alex Coplan  <alex.coplan@arm.com>
4062
4063         PR target/113616
4064         * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
4065         Use iterate_safely when iterating over debug uses.
4066         (fixup_debug_uses): Likewise.
4067         (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
4068         over nondebug insns instead of manually maintaining the next insn.
4069         * iterator-utils.h (class safe_iterator): New.
4070         (iterate_safely): New.
4071
4072 2024-01-29  H.J. Lu  <hjl.tools@gmail.com>
4073
4074         PR target/38534
4075         * config/i386/i386-options.cc (ix86_set_func_type): Save
4076         callee-saved registers in noreturn functions for -O0/-Og.
4077
4078 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
4079
4080         PR target/113615
4081         * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
4082         define for !TARGET_RDNA2_PLUS.
4083
4084 2024-01-29  Richard Sandiford  <richard.sandiford@arm.com>
4085
4086         PR target/113281
4087         * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
4088         workaround for right shifts.
4089         (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
4090         (vect_determine_precisions_from_range): Be more selective about
4091         which codes can be narrowed based on their input and output ranges.
4092         For shifts, require at least one more bit of precision than the
4093         maximum shift amount.
4094
4095 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
4096
4097         * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
4098
4099 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
4100
4101         * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
4102         but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
4103         LLVM 13.0.1+.
4104
4105 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
4106
4107         PR other/111966
4108         * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
4109         (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
4110         (SET_SRAM_ECC_UNSET): ... this.
4111         (copy_early_debug_info): Remove gfx900 special case, now handled as
4112         part of the generic handling.
4113         (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
4114
4115 2024-01-29  Jakub Jelinek  <jakub@redhat.com>
4116
4117         PR tree-optimization/110603
4118         * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
4119         setting of pdata->maxlen to vr.upper_bound (which is unconditionally
4120         overwritten anyway).  Avoid creating invalid range with minlen
4121         larger than maxlen.  Formatting fix.
4122
4123 2024-01-29  Richard Biener  <rguenther@suse.de>
4124
4125         PR debug/103047
4126         * tree-inline.cc (initialize_inlined_parameters): Reverse
4127         the decl chain of inlined parameters.
4128
4129 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
4130
4131         * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
4132         alignment of CFString constants by setting DECL_USER_ALIGN.
4133
4134 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
4135             Jakub Jelinek   <jakub@redhat.com>
4136
4137         PR libgcc/113402
4138         * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
4139         and BUILT_IN_GCC_NESTED_PTR_DELETED.
4140         * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
4141         BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
4142         rename the library fallbacks to __gcc_nested_func_ptr_created and
4143         __gcc_nested_func_ptr_deleted.
4144         * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
4145         and __gcc_nested_func_ptr_deleted.
4146         * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
4147         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
4148         * tree.cc (build_common_builtin_nodes): Build the
4149         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
4150         builtins only for non-explicit.
4151
4152 2024-01-28  YunQiang Su  <syq@gcc.gnu.org>
4153
4154         * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
4155
4156 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
4157
4158         PR target/38534
4159         * config/i386/i386-options.cc (ix86_set_func_type): Don't
4160         save and restore callee saved registers for a noreturn function
4161         with nothrow or compiled with -fno-exceptions.
4162
4163 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
4164
4165         PR target/103503
4166         PR target/113312
4167         * config/i386/i386-expand.cc (ix86_expand_call): Replace
4168         no_caller_saved_registers check with call_saved_registers check.
4169         Clobber all registers that are not used by the callee with
4170         no_callee_saved_registers attribute.
4171         * config/i386/i386-options.cc (ix86_set_func_type): Set
4172         call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
4173         noreturn function.  Disallow no_callee_saved_registers with
4174         interrupt or no_caller_saved_registers attributes together.
4175         (ix86_set_current_function): Replace no_caller_saved_registers
4176         check with call_saved_registers check.
4177         (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
4178         (ix86_handle_call_saved_registers_attribute): This.
4179         (ix86_gnu_attributes): Add
4180         ix86_handle_call_saved_registers_attribute.
4181         * config/i386/i386.cc (ix86_conditional_register_usage): Replace
4182         no_caller_saved_registers check with call_saved_registers check.
4183         (ix86_function_ok_for_sibcall): Don't allow callee with
4184         no_callee_saved_registers attribute when the calling function
4185         has callee-saved registers.
4186         (ix86_comp_type_attributes): Also check
4187         no_callee_saved_registers.
4188         (ix86_epilogue_uses): Replace no_caller_saved_registers check
4189         with call_saved_registers check.
4190         (ix86_hard_regno_scratch_ok): Likewise.
4191         (ix86_save_reg): Replace no_caller_saved_registers check with
4192         call_saved_registers check.  Don't save any registers for
4193         TYPE_NO_CALLEE_SAVED_REGISTERS.  Save all registers with
4194         TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
4195         no_callee_saved_registers attribute is called.
4196         (find_drap_reg): Replace no_caller_saved_registers check with
4197         call_saved_registers check.
4198         * config/i386/i386.h (call_saved_registers_type): New enum.
4199         (machine_function): Replace no_caller_saved_registers with
4200         call_saved_registers.
4201         * doc/extend.texi: Document no_callee_saved_registers attribute.
4202
4203 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
4204
4205         PR tree-optimization/113614
4206         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
4207         widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
4208         TRUNC_MOD_EXPR or FLOAT_EXPR uses.
4209
4210 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
4211
4212         PR tree-optimization/113568
4213         * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
4214         For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
4215         in the widening extension checks.
4216
4217 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
4218
4219         * gimple-lower-bitint.cc (gimple_lower_bitint): For
4220         TDF_DETAILS dump mapping of SSA_NAMEs to decls.
4221
4222 2024-01-26  Hans-Peter Nilsson  <hp@axis.com>
4223
4224         * cgraphunit.cc (process_function_and_variable_attributes): Tweak
4225         the warning for an attribute-always_inline without inline declaration.
4226
4227 2024-01-26  Robin Dapp  <rdapp@ventanamicro.com>
4228
4229         PR other/113575
4230         * genopinit.cc (main): Split init_all_optabs into functions
4231         of 1000 patterns each.
4232
4233 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
4234
4235         * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
4236         TM_MULTILIB_CONFIG.
4237         * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
4238         * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
4239         -march/-mtune.
4240
4241 2024-01-26  Andrew Stubbs  <ams@baylibre.com>
4242
4243         * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
4244         * config/gcn/gcn-valu.md (all_convert): New iterator.
4245         (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
4246         define_expand, and rename the old one to ...
4247         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
4248         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
4249         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
4250         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
4251         * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
4252         (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
4253         * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
4254         (<u>mulqihi3_scalar): Likewise.
4255
4256 2024-01-26  Richard Biener  <rguenther@suse.de>
4257
4258         PR tree-optimization/113602
4259         * tree-data-ref.cc (dr_analyze_innermost): Fail when
4260         the base object isn't addressable.
4261
4262 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
4263
4264         * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
4265         "--amdhsa-code-object-version=" argument.
4266         (ASM_SPEC): Use it; replace previous version of it.
4267
4268 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4269
4270         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
4271         (pre_vsetvl::emit_vsetvl): Ditto.
4272
4273 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
4274
4275         * config/loongarch/lasx.md (vec_extract<mode>_0):
4276         New define_insn_and_split patten.
4277
4278 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
4279
4280         * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
4281
4282 2024-01-26  Li Wei  <liwei@loongson.cn>
4283
4284         * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
4285
4286 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4287
4288         PR target/113469
4289         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
4290
4291 2024-01-26  Andrew Pinski  <quic_apinski@quicinc.com>
4292
4293         PR target/100212
4294         * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
4295         undefined shift after the call to exact_log2.
4296
4297 2024-01-25  Andrew Pinski  <quic_apinski@quicinc.com>
4298
4299         PR target/100204
4300         * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
4301         before taking the negative of it.
4302
4303 2024-01-25  Vladimir N. Makarov  <vmakarov@redhat.com>
4304
4305         PR target/113526
4306         * lra-constraints.cc (curr_insn_transform): Change class even for
4307         spilled pseudo successfully matched with with NO_REGS.
4308
4309 2024-01-25  Georg-Johann Lay  <avr@gjlay.de>
4310
4311         PR target/113601
4312         * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
4313
4314 2024-01-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
4315
4316         PR target/112987
4317         * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
4318         (aarch64_expand_epilogue): Use the new function.
4319         (aarch64_split_compare_and_swap): Likewise.
4320         (aarch64_split_atomic_op): Likewise.
4321
4322 2024-01-25  Robin Dapp  <rdapp.gcc@gmail.com>
4323
4324         PR middle-end/112971
4325         * fold-const.cc (simplify_const_binop): New function for binop
4326         simplification of two constant vectors when element-wise
4327         handling is not necessary.
4328         (const_binop): Call new function.
4329
4330 2024-01-25  Mary Bennett  <mary.bennett@embecosm.com>
4331
4332         * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
4333         * config/riscv/constraints.md: Likewise.
4334         * config/riscv/corev.def: Likewise.
4335         * config/riscv/corev.md: Likewise.
4336         * config/riscv/predicates.md: Likewise.
4337         * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
4338         * config/riscv/riscv-ftypes.def: Likewise.
4339         * config/riscv/riscv.opt: Likewise.
4340         * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
4341         * doc/extend.texi: Add XCVbitmanip builtin documentation.
4342         * doc/sourcebuild.texi: Likewise.
4343
4344 2024-01-25  Tobias Burnus  <tburnus@baylibre.com>
4345
4346         * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
4347
4348 2024-01-25  Yanzhang Wang  <yanzhang.wang@intel.com>
4349
4350         PR target/113538
4351         * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
4352         (riscv_fntype_abi): Ditto.
4353         * config/riscv/riscv.opt: Ditto.
4354
4355 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
4356
4357         PR middle-end/113574
4358         * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
4359         count against TYPE_PRECISION rather than TYPE_SIZE.
4360
4361 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
4362
4363         PR target/113572
4364         * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
4365         Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
4366
4367 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
4368
4369         PR target/113550
4370         * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
4371         whether each split instruction is a load that clobbers the source
4372         address.  Emit that instruction last if so.
4373
4374 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
4375
4376         PR target/113485
4377         * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
4378         pattern.
4379         (<optab><Vnarrowq><mode>2): Use it instead of generating a
4380         paradoxical subreg for the input.
4381
4382 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4383
4384         * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
4385         (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
4386         predecessors dump information.
4387
4388 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4389
4390         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
4391         redundant full available computation.
4392         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4393
4394 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
4395
4396         * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
4397         * doc/rtl.texi (CONST_VECTOR): Likewise.
4398
4399 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4400
4401         * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
4402         * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
4403         (pass_vsetvl::execute): Ditto.
4404         * config/riscv/riscv.opt: Ditto.
4405
4406 2024-01-25  Jiahao Xu  <xujiahao@loongson.cn>
4407
4408         * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
4409         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
4410
4411 2024-01-25  Richard Biener  <rguenther@suse.de>
4412
4413         PR tree-optimization/113576
4414         * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
4415         exits with may_be_zero niters when its the last one.
4416
4417 2024-01-25  Lulu Cheng  <chenglulu@loongson.cn>
4418
4419         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
4420         For symbols of type tls, non-zero Offset is not generated.
4421
4422 2024-01-25  Haochen Gui  <guihaoc@gcc.gnu.org>
4423
4424         * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
4425         P9 with m32 and mpowerpc64.
4426
4427 2024-01-25  liuhongt  <hongtao.liu@intel.com>
4428
4429         * config/i386/i386-options.cc (ix86_option_override_internal):
4430         Enable -mlam=u57 by default when compiled with
4431         -fsanitize=hwaddress.
4432
4433 2024-01-25  Palmer Dabbelt  <palmer@rivosinc.com>
4434
4435         * common/config/riscv/riscv-common.cc (riscv_implied_info):
4436         Remove {"ztso", "a"}.
4437
4438 2024-01-24  Martin Jambor  <mjambor@suse.cz>
4439
4440         PR ipa/108007
4441         PR ipa/112616
4442         * cgraph.h (cgraph_edge): Add a parameter to
4443         redirect_call_stmt_to_callee.
4444         * ipa-param-manipulation.h (ipa_param_adjustments): Add a
4445         parameter to modify_call.
4446         (ipa_release_ssas_in_hash): Declare.
4447         * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
4448         parameter killed_ssas, pass it to padjs->modify_call.
4449         * ipa-param-manipulation.cc (purge_all_uses): New function.
4450         (ipa_param_adjustments::modify_call): New parameter killed_ssas.
4451         Instead of substituting uses, invoke purge_all_uses.  If
4452         hash of killed SSAs has not been provided, create a temporary one
4453         and release SSAs that have been added to it.
4454         (compare_ssa_versions): New function.
4455         (ipa_release_ssas_in_hash): Likewise.
4456         * tree-inline.cc (redirect_all_calls): Create
4457         id->killed_new_ssa_names earlier, pass it to edge redirection,
4458         adjust a comment.
4459         (copy_body): Release SSAs in id->killed_new_ssa_names.
4460
4461 2024-01-24  Andrew Pinski  <quic_apinski@quicinc.com>
4462
4463         PR target/113486
4464         * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
4465         TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
4466
4467 2024-01-24  Monk Chiang  <monk.chiang@sifive.com>
4468
4469         PR target/113095
4470         * config/riscv/sfb.md: New splitters to rewrite single bit
4471         sign extension as the condition to SFB instructions.
4472
4473 2024-01-24  Jan Hubicka  <jh@suse.cz>
4474
4475         PR middle-end/88345
4476         * common.opt: (flimit-function-alignment): Reorder alphabeticaly
4477         (fmin-function-alignment): New parameter.
4478         * doc/invoke.texi: (-fmin-function-alignment): Document.
4479         (-falign-functions,-falign-loops,-falign-labels): Mention that
4480         aglinments are ignored in cold code.
4481         * varasm.cc (assemble_start_function): Handle min-function-alignment.
4482
4483 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
4484
4485         PR target/109636
4486         * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
4487         mulv2di3): Remove.
4488         * config/aarch64/iterators.md (VQDIV): Remove.
4489         (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
4490         SVE_I_SIMD_DI): New.
4491         (VPRED, sve_lane_con): Add V4SI and V2DI.
4492         * config/aarch64/aarch64-sve.md (<optab><mode>3,
4493         @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
4494         (mul<mode>3): New, split from <optab><mode>3.
4495         (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
4496         * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
4497         *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
4498         SVE_FULL_HSDI_SIMD_DI.
4499
4500 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
4501
4502         PR tree-optimization/113552
4503         * config/aarch64/aarch64.cc
4504         (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
4505
4506 2024-01-24  Martin Jambor  <mjambor@suse.cz>
4507
4508         PR ipa/113490
4509         * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
4510         count is equal or greater than the limit.  Use the limit from the
4511         callee.
4512
4513 2024-01-24  YunQiang Su  <syq@gcc.gnu.org>
4514
4515         * configure.ac: Detect the explicit relocs support for
4516         mips, and define C macro MIPS_EXPLICIT_RELOCS.
4517         * config.in: Regenerated.
4518         * configure: Regenerated.
4519         * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
4520         * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
4521         * config/mips/mips.cc(mips_set_compression_mode): Sorry if
4522         !TARGET_EXPLICIT_RELOCS instead of just set it.
4523         * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
4524         TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
4525         * config/mips/mips.opt: Introduce -mexplicit-relocs= option
4526         and define -m(no-)explicit-relocs as aliases.
4527
4528 2024-01-24  Alex Coplan  <alex.coplan@arm.com>
4529
4530         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4531         to 1.
4532         (-mlate-ldp-fusion): Likewise.
4533
4534 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
4535
4536         * tree-vect-loop.cc (vect_get_vect_def,
4537         vect_create_epilog_for_reduction): Rename main_exit_p to
4538         last_val_reduc_p.
4539
4540 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
4541
4542         PR tree-optimization/113364
4543         * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
4544         early exits then we must reduce from the first offset for all of them.
4545
4546 2024-01-24  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4547
4548         PR target/113495
4549         * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
4550         (get_regno): Ditto.
4551         (get_bb_index): Ditto.
4552         (pre_vsetvl::compute_avl_def_data): Ditto.
4553         (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
4554         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4555
4556 2024-01-23  Andrew Pinski  <quic_apinski@quicinc.com>
4557             Richard Sandiford  <richard.sandiford@arm.com>
4558
4559         PR target/100942
4560         * ccmp.cc (ccmp_candidate_p): Add outer argument.
4561         Allow if the outer is true and the lhs is used more
4562         than once.
4563         (expand_ccmp_expr): Update call to ccmp_candidate_p.
4564         * expr.h (expand_expr_real_gassign): Declare.
4565         * expr.cc (expand_expr_real_gassign): New function, split out from...
4566         (expand_expr_real_1): ...here.
4567         * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
4568
4569 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
4570
4571         PR target/113089
4572         * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
4573         (fixup_debug_use): New.
4574         (fixup_debug_uses_trailing_add): New.
4575         (fixup_debug_uses): New. Use it ...
4576         (ldp_bb_info::fuse_pair): ... here.
4577         (try_promote_writeback): Call fixup_debug_uses_trailing_add to
4578         fix up debug uses of the base register that are affected by
4579         folding in the trailing add insn.
4580
4581 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
4582
4583         PR target/113089
4584         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
4585         Update trailing nondebug uses of the base register in the case
4586         of cancelling writeback.
4587
4588 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
4589
4590         PR target/113089
4591         * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
4592         (debug_insn_use_iterator): New.
4593         (set_info::first_debug_insn_use): New.
4594         (set_info::debug_insn_uses): New.
4595         * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
4596         (set_info::first_debug_insn_use): New.
4597         (set_info::debug_insn_uses): New.
4598
4599 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
4600
4601         PR target/113356
4602         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
4603         Don't record hazards against the opposite insn in the pair.
4604
4605 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
4606
4607         PR target/113070
4608         * config/aarch64/aarch64-ldp-fusion.cc
4609         (struct stp_change_builder): New.
4610         (decide_stp_strategy): Reanme to ...
4611         (try_repurpose_store): ... this.
4612         (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
4613         construct stp changes.  Fix up uses when inserting new stp insns.
4614
4615 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
4616
4617         PR target/113070
4618         * rtl-ssa.h: Include hash-set.h.
4619         * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
4620         new_sets parameter and use it to keep track of new user-created sets.
4621         (function_info::apply_changes_to_insn): Also call add_def on new sets.
4622         (function_info::change_insns): Add hash_set to keep track of new
4623         user-created defs.  Plumb it through.
4624         * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
4625         apply_changes_to_insn.
4626
4627 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
4628
4629         PR target/113070
4630         * rtl-ssa/accesses.cc (function_info::create_use): New.
4631         * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
4632         Ensure new uses end up referring to permanent defs.
4633         * rtl-ssa/functions.h (function_info::create_use): Declare.
4634
4635 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
4636
4637         PR target/113070
4638         * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
4639         to finalize_new_accesses from the backwards placement loop, run it
4640         forwards in a separate loop.
4641
4642 2024-01-23  Richard Biener  <rguenther@suse.de>
4643
4644         PR tree-optimization/113552
4645         * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
4646         floor_log2 instead of exact_log2 on the number of calls.
4647
4648 2024-01-23  Jeff Law  <jlaw@ventanamicro.com>
4649             Jakub Jelinek  <jakub@redhat.com>
4650
4651         * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
4652         decl.
4653
4654 2024-01-23  Richard Biener  <rguenther@suse.de>
4655
4656         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4657         Separate single and multi-exit case when creating PHIs between
4658         the main and epilogue.
4659
4660 2024-01-23  Richard Sandiford  <richard.sandiford@arm.com>
4661
4662         PR target/112989
4663         * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
4664         MODE_single variants of functions that don't take tuple arguments.
4665
4666 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
4667
4668         PR target/113114
4669         * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
4670         Don't assert recog success, just punt if the writeback pair
4671         isn't recognized.
4672
4673 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
4674
4675         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
4676         ATTRIBUTE_UNUSED to decl.
4677
4678 2024-01-23  Richard Biener  <rguenther@suse.de>
4679
4680         PR debug/107058
4681         * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
4682         handle unexpected but bogus DIE contexts when not checking
4683         enabled.
4684
4685 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
4686
4687         PR tree-optimization/113462
4688         * fold-const.cc (native_interpret_int): Don't punt if total_bytes
4689         is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
4690         (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
4691         sizes between 129 and 8192 bytes.
4692
4693 2024-01-23  Xi Ruoyao  <xry111@xry111.site>
4694
4695         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
4696         If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
4697         for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
4698         (loongarch_call_tls_get_addr): Do not split symbols of
4699         SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
4700         EXPLICIT_RELOCS_AUTO.
4701
4702 2024-01-23  Richard Biener  <rguenther@suse.de>
4703
4704         * alias.cc (known_base_value_p): Remove.
4705         (find_base_value): Remove PLUS/MINUS handling
4706         when both operands are not CONST_INT_P.
4707
4708 2024-01-23  Richard Biener  <rguenther@suse.de>
4709
4710         PR rtl-optimization/113255
4711         * alias.cc (find_base_term): Remove PLUS/MINUS handling
4712         when both operands are not CONST_INT_P.
4713
4714 2024-01-23  Richard Biener  <rguenther@suse.de>
4715
4716         PR debug/112718
4717         * dwarf2out.cc (dwarf2out_finish): Reset all type units
4718         for the fat part of an LTO compile.
4719
4720 2024-01-23  chenxiaolong  <chenxiaolong@loongson.cn>
4721
4722         * doc/sourcebuild.texi: Add attributes for keywords.
4723
4724 2024-01-23  Sandra Loosemore  <sandra@codesourcery.com>
4725
4726         PR c++/90463
4727         * doc/invoke.texi (Warning Options): Correct lists of options
4728         enabled by -Wall and -Wextra by checking against common.opt
4729         and c-family/c.opt.
4730
4731 2024-01-22  Andrew Pinski  <quic_apinski@quicinc.com>
4732
4733         PR target/113030
4734         * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
4735         instead of cpu_optaliases.
4736         (check_arch): Use arch_opt_alias instead of arch_optaliases.
4737
4738 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4739
4740         * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
4741         * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
4742         * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
4743
4744 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4745
4746         PR target/109092
4747         * config/riscv/riscv.md: Use reg instead of subreg.
4748
4749 2024-01-22  Tobias Burnus  <tburnus@baylibre.com>
4750
4751         PR other/111966
4752         * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
4753         to match the compiler default.
4754         (simple_object_copy_lto_debug_sections): Never unlink the outfile
4755         on error as the caller does so.
4756         (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
4757         (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
4758
4759 2024-01-22  Richard Biener  <rguenther@suse.de>
4760
4761         PR tree-optimization/113373
4762         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4763         Create LC PHIs in the exit blocks where necessary.
4764         * tree-vect-loop.cc (vectorizable_live_operation): Do not try
4765         to handle missing LC PHIs.
4766         (find_connected_edge): Remove.
4767         (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
4768
4769 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4770
4771         * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
4772
4773 2024-01-22  xuli  <xuli1@eswincomputing.com>
4774
4775         PR target/113420
4776         * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
4777         (registered_function::overloaded_hash):refactor.
4778         (resolve_overloaded_builtin):avoid internal ICE.
4779
4780 2024-01-21  Mikael Pettersson  <mikpelinux@gmail.com>
4781
4782         PR target/82420
4783         PR target/111279
4784         * calls.cc (emit_library_call_value_1): Pass valid TYPE
4785         to emit_push_insn.
4786         * expr.cc (emit_push_insn): Likewise.
4787
4788 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
4789
4790         * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
4791         correcction version of last change.
4792
4793 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
4794
4795         * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
4796         fix bugs in signature.
4797
4798 2024-01-21  Roger Sayle  <roger@nextmovesoftware.com>
4799             Richard Biener  <rguenther@suse.de>
4800
4801         PR rtl-optimization/111267
4802         * fwprop.cc (fwprop_propagation::profitabe_p): Rename
4803         profitable_p method to likely_profitable_p.
4804         (try_fwprop_subst_node): Update call to likely_profitable_p.
4805         Only bail-out early when !prop.likely_profitable_p for instructions
4806         that are not single sets.  When comparing costs, bail-out if the
4807         cost is unchanged and !prop.likely_profitable_p.
4808
4809 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
4810
4811         PR c++/90464
4812         * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
4813         isn't enabled by -Wunused unless -Wextra is provided, and that
4814         -Wunused does enable -Wunused-const-variable=1 for C.  Clarify that
4815         -Wunused doesn't enable -Wunused-* options documented as behaving
4816         otherwise, and list them explicitly.
4817
4818 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
4819
4820         PR c/109708
4821         * doc/invoke.texi (Warning Options): Fix broken example and
4822         clean up/reorganize the others.  Also describe what the short-form
4823         options mean.
4824
4825 2024-01-20  Sandra Loosemore  <sandra@codesourcery.com>
4826
4827         PR c/102998
4828         * doc/invoke.texi (Option Summary): Add -Warray-parameter.
4829         (Warning Options): Correct/edit discussion of -Warray-parameter
4830         to make the first example less confusing, and fill in missing info.
4831
4832 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
4833
4834         PR tree-optimization/113462
4835         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
4836         Handle rhs1 INTEGER_CST like SSA_NAME.
4837
4838 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
4839
4840         PR tree-optimization/113491
4841         * tree-switch-conversion.cc (switch_conversion::build_constructors):
4842         If elt.index has precision higher than sizetype, fold_convert it to
4843         sizetype.
4844         (switch_conversion::array_value_type): Return type if type is
4845         BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
4846         (switch_conversion::build_arrays): Use unsigned_type_for rather than
4847         lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
4848         above MAX_FIXED_MODE_SIZE or with BLKmode.  If utype has precision
4849         higher than sizetype, use sizetype as tidx type and fold_convert the
4850         subtraction to sizetype.
4851
4852 2024-01-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4853
4854         * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
4855         (riscv_vector_mode_supported_any_target_p): Ditto.
4856
4857 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
4858
4859         PR target/110934
4860         * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
4861         (TARGET_ZERO_CALL_USED_REGS): Define.
4862
4863 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
4864
4865         PR target/108640
4866         * config/m68k/m68k.cc (output_andsi3): Use QImode for
4867         address adjusted for 1-byte RMW access.
4868         (output_iorsi3): Likewise.
4869         (output_xorsi3): Likewise.
4870
4871 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4872
4873         * doc/invoke.texi (RISC-V Options): Add list of supported
4874         extensions.
4875
4876 2024-01-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4877
4878         PR target/113495
4879         * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
4880         (RVV_VUNDEF): Ditto.
4881         * config/riscv/riscv-vsetvl.cc: Add timevar.
4882
4883 2024-01-19  Richard Biener  <rguenther@suse.de>
4884
4885         PR debug/113488
4886         * lto-streamer-in.cc (lto_read_tree_1): When there isn't
4887         an early DIE but there should be, do not pretend there is.
4888
4889 2024-01-19  Richard Biener  <rguenther@suse.de>
4890
4891         PR tree-optimization/113494
4892         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4893         Handle endless loop on exit.  Handle re-allocated PHI.
4894
4895 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
4896
4897         PR tree-optimization/113464
4898         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
4899         optimize loads into GIMPLE_ASM stmts.
4900
4901 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
4902
4903         PR tree-optimization/113463
4904         * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
4905         Only look through NOP_EXPRs if rhs1 doesn't have wider type than
4906         lhs.
4907
4908 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
4909
4910         PR tree-optimization/113459
4911         * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
4912         TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
4913         of SCALAR_INT_TYPE_MODE if type has BLKmode.
4914         (vn_reference_lookup_3): Likewise.  Formatting fix.
4915
4916 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
4917             Richard Biener  <rguenther@suse.de>
4918
4919         * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
4920         VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
4921         * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
4922         but adjust_address also for BLKmode mode and MEM op0.
4923
4924 2024-01-19  Palmer Dabbelt  <palmer@rivosinc.com>
4925
4926         * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
4927         extensions.
4928
4929 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4930
4931         * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
4932
4933 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4934
4935         * common/config/riscv/riscv-common.cc
4936         (riscv_subset_list::parse_std_ext): Remove.
4937         (riscv_subset_list::parse_multiletter_ext): Remove.
4938         * config/riscv/riscv-subset.h
4939         (riscv_subset_list::parse_std_ext): Remove.
4940         (riscv_subset_list::parse_multiletter_ext): Remove.
4941
4942 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4943
4944         * common/config/riscv/riscv-common.cc
4945         (riscv_subset_list::parse_single_std_ext): New parameter.
4946         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4947         (riscv_subset_list::parse_single_ext): Ditto.
4948         (riscv_subset_list::parse): Relax the order for the input of ISA
4949         string.
4950         * config/riscv/riscv-subset.h
4951         (riscv_subset_list::parse_single_std_ext): New parameter.
4952         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4953         (riscv_subset_list::parse_single_ext): Ditto.
4954
4955 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4956
4957         * common/config/riscv/riscv-common.cc
4958         (riscv_subset_list::parse_base_ext): New.
4959         (riscv_subset_list::parse): Extract part of logic into
4960         riscv_subset_list::parse_base_ext.
4961         * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
4962         New.
4963
4964 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
4965
4966         * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
4967         sorry message.
4968
4969 2024-01-19  Kuan-Lin Chen  <rufus@andestech.com>
4970
4971         * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
4972         UNSPEC_CLMUL_VC.
4973
4974 2024-01-19  Sandra Loosemore  <sandra@codesourcery.com>
4975
4976         PR c/110029
4977         * doc/extend.texi (Common Variable Attributes): Explain what
4978         happens when multiple variables with cleanups are in the same scope.
4979
4980 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
4981
4982         PR ipa/108470
4983         * doc/extend.texi (Common Function Attributes): Document that
4984         noinline also disables some interprocedural optimizations and
4985         improve flow to the part about using inline asm instead to
4986         disable calls from being optimized away completely.  Remove the
4987         sentence that says noipa is mainly for internal compiler testing.
4988
4989 2024-01-18  John David Anglin  <danglin@gcc.gnu.org>
4990
4991         PR tree-optimization/69807
4992         * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
4993
4994 2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>
4995
4996         PR target/108521
4997         * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
4998         from x86 Windows Options.
4999
5000 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
5001
5002         PR c/107942
5003         * doc/extend.texi (C Extensions): Add new section to menu.
5004         (Function Attributes):  Move dangling index entries to....
5005         (Const and Volatile Functions): New section.
5006
5007 2024-01-18  David Malcolm  <dmalcolm@redhat.com>
5008
5009         PR middle-end/112684
5010         * toplev.cc (toplev::main): Don't ICE in
5011         -fdiagnostics-generate-patch when exiting after options,
5012         since no edit context will have been created.
5013
5014 2024-01-18  Richard Biener  <rguenther@suse.de>
5015
5016         * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
5017         operands vector.
5018
5019 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
5020
5021         * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
5022         when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
5023
5024 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
5025             Jin Ma  <jinma@linux.alibaba.com>
5026             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
5027             Christoph Müllner  <christoph.muellner@vrull.eu>
5028
5029         * config/riscv/thead.cc
5030         (th_asm_output_opcode): Rewrite some instructions.
5031
5032 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
5033             Jin Ma  <jinma@linux.alibaba.com>
5034             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
5035             Christoph Müllner  <christoph.muellner@vrull.eu>
5036
5037         * config/riscv/riscv.md (none,thv,rvv): New attribute.
5038         (no,yes): Add an attribute to disable alternative
5039         for xtheadvector or RVV1.0.
5040         * config/riscv/vector.md:
5041         Disable alternatives that destination register overlaps
5042         source register group for xtheadvector.
5043
5044 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
5045             Jin Ma  <jinma@linux.alibaba.com>
5046             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
5047             Christoph Müllner  <christoph.muellner@vrull.eu>
5048
5049         * config/riscv/riscv-vector-builtins-bases.cc
5050         (class th_loadstore_width): Define new builtin bases.
5051         (class th_extract): Define new builtin bases.
5052         (BASE): Define new builtin bases.
5053         * config/riscv/riscv-vector-builtins-bases.h:
5054         Define new builtin class.
5055         * config/riscv/riscv-vector-builtins-shapes.cc
5056         (struct th_loadstore_width_def): Define new builtin shapes.
5057         (struct th_indexed_loadstore_width_def):
5058         Define new builtin shapes.
5059         (struct th_extract_def): Define new builtin shapes.
5060         (SHAPE): Define new builtin shapes.
5061         * config/riscv/riscv-vector-builtins-shapes.h:
5062         Define new builtin shapes.
5063         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
5064         Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
5065         * config/riscv/riscv-vector-builtins.h
5066         (enum required_ext): Add new XTheadVector member.
5067         (struct function_group_info): Likewise.
5068         * config/riscv/t-riscv:
5069         Add thead-vector-builtins-functions.def
5070         * config/riscv/thead-vector.md
5071         (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
5072         (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
5073         (@pred_store_width<vlmem_op_attr><mode>): Likewise.
5074         (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
5075         (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
5076         (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
5077         (@pred_th_extract<mode>): Likewise.
5078         (*pred_th_extract<mode>): Likewise.
5079         * config/riscv/thead-vector-builtins-functions.def: New file.
5080
5081 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
5082             Jin Ma  <jinma@linux.alibaba.com>
5083             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
5084             Christoph Müllner  <christoph.muellner@vrull.eu>
5085
5086         * config.gcc:  Add files for XTheadVector intrinsics.
5087         * config/riscv/autovec.md: Guard XTheadVector.
5088         * config/riscv/predicates.md: Disable immediate vl
5089         for XTheadVector.
5090         * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
5091         Add pragma for XTheadVector.
5092         * config/riscv/riscv-string.cc (riscv_expand_block_move):
5093         Guard XTheadVector.
5094         * config/riscv/riscv-v.cc (vls_mode_valid_p):
5095         Avoid autovec.
5096         * config/riscv/riscv-vector-builtins-bases.cc:
5097         Do not normalize vsetvl instructions for XTheadVector.
5098         * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
5099         New check type function.
5100         (build_one): Adjust for XTheadVector.
5101         * config/riscv/riscv-vector-switch.def (ENTRY):
5102         Disable fractional mode for the XTheadVector extension.
5103         (TUPLE_ENTRY): Likewise.
5104         * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
5105         Guard XTheadVector.
5106         (riscv_preferred_simd_mode): Likewsie.
5107         (riscv_autovectorize_vector_modes): Likewise.
5108         (riscv_vector_mode_supported_any_target_p): Likewise.
5109         (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
5110         * config/riscv/thead.cc (th_asm_output_opcode):
5111         Rewrite vsetvl instructions.
5112         * config/riscv/vector.md:
5113         Include thead-vector.md and change fractional LMUL
5114         into 1 for vbool.
5115         * config/riscv/riscv_th_vector.h: New file.
5116         * config/riscv/thead-vector.md: New file.
5117
5118 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
5119             Jin Ma  <jinma@linux.alibaba.com>
5120             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
5121             Christoph Müllner  <christoph.muellner@vrull.eu>
5122
5123         * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
5124         Add new function to add assembler insn code prefix/suffix.
5125         (th_asm_output_opcode):
5126         Add Thead function to add assembler insn code prefix/suffix.
5127         * config/riscv/riscv.cc (riscv_asm_output_opcode):
5128         Implement function to add assembler insn code prefix/suffix.
5129         * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
5130         Add new function to add assembler insn code prefix/suffix.
5131         * config/riscv/thead.cc (th_asm_output_opcode):
5132         Implement Thead function to add assembler insn code
5133         prefix/suffix.
5134
5135 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
5136             Jin Ma  <jinma@linux.alibaba.com>
5137             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
5138             Christoph Müllner  <christoph.muellner@vrull.eu>
5139
5140         * common/config/riscv/riscv-common.cc
5141         (riscv_subset_list::parse): Add new vendor extension.
5142         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
5143         Add test marco.
5144         * config/riscv/riscv.opt:  Add new mask.
5145
5146 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
5147
5148         * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
5149         to be conditional on macosx-version-min.
5150
5151 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
5152
5153         * config/darwin.cc (darwin_objc1_section): Use the correct
5154         meta-data version for constant strings.
5155         (machopic_select_section): Assert if we fail to handle CFString
5156         sections as Obejctive-C meta-data or drectly.
5157
5158 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
5159
5160         * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
5161         OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
5162         OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
5163         versions when the object format is Mach-O.
5164
5165 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
5166
5167         PR target/105522
5168         * config/darwin.cc (machopic_select_section): Handle C and C++
5169         CFStrings.
5170         (darwin_rename_builtins): Move this out of the CFString code.
5171         (darwin_libc_has_function): Likewise.
5172         (darwin_build_constant_cfstring): Create an anonymous var to
5173         hold each CFString.
5174         * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
5175         CFstrings.
5176
5177 2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
5178
5179         PR bootstrap/113445
5180         * haifa-sched.cc (dep_list_size): Make global.
5181         * sched-deps.cc (find_inc): Use instead of sd_lists_size().
5182         * sched-int.h (dep_list_size): Declare.
5183
5184 2024-01-18  Martin Jambor  <mjambor@suse.cz>
5185
5186         PR tree-optimization/110422
5187         * tree-sra.cc (scan_function): Disqualify bases of operands of asm
5188         gotos.
5189
5190 2024-01-18  Richard Biener  <rguenther@suse.de>
5191
5192         PR tree-optimization/113475
5193         * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
5194         * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
5195         (phi_analyzer::~phi_analyzer): Deallocate and free collected
5196         phi_grous.
5197         (phi_analyzer::process_phi): Record allocated phi_groups.
5198
5199 2024-01-18  Richard Biener  <rguenther@suse.de>
5200
5201         * tree-vect-stmts.cc (vectorizable_store): Do not allocate
5202         storage for gvec_oprnds elements.
5203
5204 2024-01-18  Richard Biener  <rguenther@suse.de>
5205
5206         * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
5207         prefer all later exits we can handle.
5208         (vect_analyze_loop_form): Free the allocated loop body.
5209         Adjust comments.
5210
5211 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
5212
5213         * config/avr/avr-log.cc: Tabify.
5214
5215 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5216
5217         * config/riscv/autovec.md: Support vi variant.
5218
5219 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
5220
5221         * config/avr/avr-devices.cc: Tabify.
5222
5223 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
5224
5225         * config/avr/avr-c.cc: Tabify.
5226
5227 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
5228
5229         * config/avr/driver-avr.cc: Tabify.
5230
5231 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
5232
5233         * config/avr/gen-avr-mmcu-texi.cc: Tabify.
5234
5235 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
5236
5237         * config/avr/gen-avr-mmcu-specs.cc: Tabify.
5238
5239 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
5240
5241         * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
5242         minline-strcmp, minline-strncmp, minline-strlen,
5243         -param=riscv-vector-abi): Remove Bool keywords.
5244
5245 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
5246
5247         PR target/113122
5248         * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
5249         support.  Add missing space after , in emitted assembly in some
5250         cases.  Formatting fixes.
5251
5252 2024-01-18  Xi Ruoyao  <xry111@xry111.site>
5253
5254         * config/loongarch/loongarch.md (movsi_internal): Remove
5255         constraint z.
5256
5257 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
5258
5259         * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
5260         in the diagnostic, and capitalize the device name.
5261         (print_mcu): Generate specs such that:
5262         <*check_rodata_in_ram>: New.
5263         <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
5264         <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
5265         <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
5266
5267 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
5268
5269         PR other/113399
5270         * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
5271         Common and Optimization.
5272
5273 2024-01-18  Richard Biener  <rguenther@suse.de>
5274
5275         PR tree-optimization/113431
5276         * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
5277         When there is an invariant load we might not preserve
5278         scalar order.
5279
5280 2024-01-18  Richard Biener  <rguenther@suse.de>
5281
5282         PR tree-optimization/113374
5283         * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
5284         * tree-vect-loop.cc (move_early_exit_stmts): Update
5285         virtual LC PHIs.
5286         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5287         Refactor.  Preserve virtual LC PHIs on all exits.
5288
5289 2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>
5290
5291         * config/loongarch/loongarch.cc (loongarch_split_symbol):
5292         Assign the '/u' attribute to the mem.
5293
5294 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
5295
5296         PR middle-end/110847
5297         * doc/invoke.texi (Option Summary): Document negative forms of
5298         -Wtsan and -Wxor-used-as-pow.
5299         (Warning Options): Likewise.
5300
5301 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5302
5303         PR target/113429
5304         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
5305
5306 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
5307
5308         * doc/extend.texi (Common Function Attributes): Re-alphabetize
5309         the table.
5310         (Common Variable Attributes): Likewise.
5311         (Common Type Attributes): Likewise.
5312
5313 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
5314
5315         PR middle-end/111659
5316         * doc/extend.texi (Common Variable Attributes): Fix long lines
5317         in documentation of strict_flex_array + other minor copy-editing.
5318         Add a cross-reference to -Wstrict-flex-arrays.
5319         * doc/invoke.texi (Option Summary): Fix whitespace in tables
5320         before -fstrict-flex-arrays and -Wstrict-flex-arrays.
5321         (C Dialect Options): Combine the docs for the two
5322         -fstrict-flex-arrays forms into a single entry.  Note this option
5323         is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
5324         (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
5325         Minor copy-editing.  Add cross references to the strict_flex_array
5326         attribute and -fstrict-flex-arrays option.  Add note that this
5327         option depends on -ftree-vrp.
5328
5329 2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>
5330
5331         PR target/113221
5332         * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
5333         only allow REG operands instead of allowing all.
5334
5335 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
5336
5337         * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
5338         Remove redundant checks in else condition for readablity.
5339         (earliest_fuse_vsetvl_info) Print iteration count in debug
5340         prints.
5341         (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
5342         dump details in certain cases.
5343
5344 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
5345
5346         * config/riscv/riscv.opt: New -param=vsetvl-strategy.
5347         * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
5348         * config/riscv/riscv-vsetvl.cc
5349         (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
5350         (pass_vsetvl::execute): Use vsetvl_strategy.
5351
5352 2024-01-17  Jan Hubicka  <jh@suse.cz>
5353
5354         * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
5355         accidental hack reseting offset.
5356
5357 2024-01-17  Jan Hubicka  <jh@suse.cz>
5358
5359         * config/i386/i386-options.cc (ix86_option_override_internal): Fix
5360         handling of X86_TUNE_AVOID_512FMA_CHAINS.
5361
5362 2024-01-17  Jan Hubicka  <jh@suse.cz>
5363             Jakub Jelinek  <jakub@redhat.com>
5364
5365         PR tree-optimization/110852
5366         * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
5367         binary operations
5368         (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
5369         PRED_COMBINED_VALUE_PREDICTIONS_PHI
5370         * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
5371         (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
5372
5373 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
5374
5375         PR tree-optimization/113421
5376         * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
5377         comment.
5378         (bitint_dom_walker::before_dom_children): Add g temporary to simplify
5379         formatting.  Start at vop rather than cvop even if stmt is a store
5380         and needs_operand_addr.
5381
5382 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
5383
5384         PR middle-end/113410
5385         * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
5386         If access_nelts is integral with larger precision than sizetype,
5387         fold_convert it to sizetype.
5388
5389 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
5390
5391         PR tree-optimization/113408
5392         * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
5393         VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
5394         to handle_cast.
5395
5396 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
5397
5398         PR middle-end/113406
5399         * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
5400         regardless of whether is_gimple_reg_type (restype) or not.
5401
5402 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
5403
5404         * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
5405         funcions -> functions, and use were instead of was.
5406         * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
5407         and guaranteee -> guarantee.
5408         * attribs.h (struct attr_access): Fix comment typo funcion -> function.
5409
5410 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
5411
5412         PR middle-end/113409
5413         * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
5414         INTEGER_TYPE.
5415         (omp_extract_for_data): Use build_bitint_type rather than
5416         build_nonstandard_integer_type if either iter_type or loop->v type
5417         is BITINT_TYPE.
5418         * omp-expand.cc (expand_omp_for_generic,
5419         expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
5420         BITINT_TYPE like INTEGER_TYPE.
5421
5422 2024-01-17  Richard Biener  <rguenther@suse.de>
5423
5424         PR tree-optimization/113371
5425         * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
5426         Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5427         * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
5428         not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5429
5430 2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
5431
5432         PR rtl-optimization/96388
5433         PR rtl-optimization/111554
5434         * sched-deps.cc (find_inc): Avoid exponential behavior.
5435
5436 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
5437
5438         PR c/111693
5439         * doc/invoke.texi (Option Summary): Move -Wuseless-cast
5440         from C++ Language Options to Warning Options.  Add entry for
5441         -Wuse-after-free.
5442         (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
5443         from here....
5444         (Warning Options): ...to here.  Minor copy-editing to fix typo
5445         and grammar.
5446
5447 2024-01-17  YunQiang Su  <syq@gcc.gnu.org>
5448
5449         * config/mips/mips.cc (mips_compute_frame_info): If another
5450         register is used as global_pointer, mark $GP live false.
5451
5452 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
5453
5454         PR target/112973
5455         * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
5456         give the section a light copy-editing pass.
5457
5458 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
5459
5460         * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
5461         * config/aarch64/aarch64-tune.md: Regenerated.
5462         * doc/invoke.texi (-mcpu): Add cobalt-100 core.
5463
5464 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
5465
5466         PR target/112573
5467         * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
5468         badly formed CONST expressions.
5469
5470 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
5471
5472         * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
5473
5474 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
5475
5476         * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
5477         * config/sparc/sync.md (membar_storeload): Turn into named insn
5478         and add GR712RC errata workaround.
5479         (membar_v8): Add GR712RC errata workaround.
5480
5481 2024-01-16  Andreas Larsson  <andreas@gaisler.com>
5482
5483         * config/sparc/sync.md (*membar_storeload_leon3): Remove
5484         (*membar_storeload): Enable for LEON
5485
5486 2024-01-16  Jakub Jelinek  <jakub@redhat.com>
5487
5488         PR tree-optimization/113372
5489         PR middle-end/90348
5490         PR middle-end/110115
5491         PR middle-end/111422
5492         * cfgexpand.cc (add_scope_conflicts_2): New function.
5493         (add_scope_conflicts_1): Use it.
5494
5495 2024-01-16  Georg-Johann Lay  <avr@gjlay.de>
5496
5497         * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
5498         (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
5499         * doc/avr-mmcu.texi: Regenerate.
5500
5501 2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>
5502
5503         PR tree-optimization/113091
5504         * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
5505         (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
5506         scalar use with new function.
5507         (vect_bb_slp_mark_live_stmts): New function as entry to existing
5508         overriden functions with same name.
5509         (vect_slp_analyze_operations): Call new entry function to mark
5510         live statements.
5511
5512 2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5513
5514         PR target/113404
5515         * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
5516         for RVV in big-endian mode.
5517
5518 2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>
5519
5520         * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
5521         (riscv_pass_in_vector_p): Delete.
5522         (riscv_init_cumulative_args): Delete the checking.
5523         (riscv_get_arg_info): Delete the checking.
5524         (riscv_function_value): Delete the checking.
5525         * config/riscv/riscv.h: Delete the member for checking.
5526
5527 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
5528
5529         * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
5530
5531 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
5532
5533         * config.gcc: Include riscv_bitmanip.h.
5534         * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
5535         * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
5536         * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
5537         (RISCV_BUILTIN_NO_PREFIX): New helper macro.
5538         * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
5539         * config/riscv/riscv-ftypes.def (2): New ftypes.
5540         * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
5541         (RISCV_BUILTIN_NO_PREFIX): Likewise.
5542         * config/riscv/riscv_bitmanip.h: New file.
5543
5544 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
5545
5546         * config.gcc: Include riscv_crypto.h.
5547         * config/riscv/riscv_crypto.h: New file.
5548
5549 2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>
5550
5551         PR middle-end/113354
5552         * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
5553         in the insn if the corresponding operand does not require hard
5554         register anymore.
5555
5556 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
5557
5558         PR target/107201
5559         * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
5560         * config/avr/driver-avr.cc (avr_no_devlib): New function.
5561         (avr_devicespecs_file): Use it to remove -nodevicelib from the
5562         options for cores only.
5563         * config/avr/avr-arch.h (avr_get_parch): New prototype.
5564         * config/avr/avr-devices.cc (avr_get_parch): New function.
5565
5566 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5567
5568         PR target/113247
5569         * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
5570         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
5571         * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
5572
5573 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5574
5575         PR target/113281
5576         * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
5577         (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
5578         * config/riscv/riscv-vector-costs.h: New function.
5579
5580 2024-01-15  Richard Biener  <rguenther@suse.de>
5581
5582         PR tree-optimization/113385
5583         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5584         First redirect, then split the exit edge.
5585
5586 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5587
5588         * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
5589         Remove m_num_vector_iterations.
5590         * config/riscv/riscv-vector-costs.h: Ditto.
5591
5592 2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>
5593
5594         PR target/113156
5595         * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
5596         (-mbranch-cost): Set "Optimization" flag.
5597
5598 2024-01-15  Jakub Jelinek  <jakub@redhat.com>
5599
5600         PR tree-optimization/113370
5601         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
5602         set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
5603         set it to just prec % limb_prec.
5604
5605 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5606
5607         PR target/113393
5608         * config/riscv/vector.md: Fix ternary attributes.
5609
5610 2024-01-14  Georg-Johann Lay  <avr@gjlay.de>
5611
5612         PR target/112944
5613         * configure.ac [target=avr]: Check availability of emulations
5614         avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
5615         HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
5616         * configure: Regenerate.
5617         * config.in: Regenerate.
5618         * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
5619         __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
5620         * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
5621         * config/avr/avr-arch.h (enum avr_device_specific_features):
5622         Add AVR_ISA_FLMAP.
5623         * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
5624         AVR_ISA_FLMAP.
5625         * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
5626         (avr_set_core_architecture): Set avr_arch_index.
5627         (have_avrxmega2_flmap, have_avrxmega4_flmap)
5628         (have_avrxmega3_rodata_in_flash): Set new static const bool according
5629         to configure results.
5630         (avr_rodata_in_flash_p): New function using them.
5631         (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
5632         track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
5633         (avr_asm_named_section): Track avr_has_rodata_p.
5634         (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
5635         and not avr_rodata_in_flash_p ().
5636         * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
5637         (LINK_SPEC): Add %(link_rodata_in_ram).
5638         (LINK_ARCH_SPEC): Remove.
5639         * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
5640         (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
5641         const bool according to configure results.
5642         (diagnose_mrodata_in_ram): New function.
5643         (print_mcu): Generate specs with the following changes:
5644         <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
5645         need to extend avr/specs.h each time we add a new bell or whistle.
5646         <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
5647         -m[no-]rodata-in-ram.
5648         <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
5649         <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
5650         <*cpp>: Add %(cpp_rodata_in_ram).
5651         <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
5652         requested.
5653         <*self_spec>: Add -mflmap or %<mflmap as needed.
5654
5655 2024-01-14  Jeff Law  <jlaw@ventanamicro.com>
5656
5657         * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
5658         not the GPR iterator.  Adjust pattern name and mode attribute
5659         accordingly.
5660
5661 2024-01-13  Jakub Jelinek  <jakub@redhat.com>
5662
5663         PR tree-optimization/113361
5664         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
5665         Fix up determination of the type for > limb_prec constants.
5666
5667 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
5668
5669         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
5670         Add web-link to the avr-gcc wiki.
5671
5672 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
5673
5674         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
5675         documentation for a version without argument, which is not supported.
5676
5677 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5678
5679         * config/arm/arm_neon.h
5680         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
5681         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
5682         (vld1_f16_x4, vld1_f32_x4): New.
5683         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
5684         (vld1_bf16_x4): New.
5685         (vld1q_types_x4): Updated to use vld1q_x4
5686         from arm_neon_builtins.def
5687         * config/arm/arm_neon_builtins.def
5688         (vld1_x4): Updated entries.
5689         (vld1q_x4): New entries, but comes from the old vld1_x4
5690         * config/arm/neon.md
5691         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
5692
5693 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5694
5695         * config/arm/arm_neon.h
5696         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
5697         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
5698         (vld1_f16_x3, vld1_f32_x3): New.
5699         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
5700         (vld1_bf16_x3): New.
5701         (vld1q_types_x3): Updated to use vld1q_x3 from
5702         arm_neon_builtins.def
5703         * config/arm/arm_neon_builtins.def
5704         (vld1_x3): Updated entries.
5705         (vld1q_x3): New entries, but comes from the old vld1_x2
5706         * config/arm/neon.md
5707         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
5708
5709 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5710
5711         * config/arm/arm_neon.h
5712         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
5713         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
5714         (vld1_f16_x2, vld1_f32_x2): New.
5715         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
5716         (vld1_bf16_x2): New.
5717         (vld1q_types_x2): Updated to use vld1q_x2 from
5718         arm_neon_builtins.def
5719         * config/arm/arm_neon_builtins.def
5720         (vld1_x2): Updated entries.
5721         (vld1q_x2): New entries, but comes from the old vld1_x2
5722         * config/arm/neon.md
5723         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5724         neon_vld1_x2<mode>.
5725
5726 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5727
5728         * config/arm/arm_neon.h
5729         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
5730         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
5731         (vst1q_f16_x4, vst1q_f32_x4): New.
5732         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
5733         (vst1q_bf16_x4): New.
5734         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
5735         * config/arm/neon.md
5736         (neon_vst1q_x4<mode>): New.
5737         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
5738         * config/arm/unspecs.md
5739         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
5740
5741 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5742
5743         * config/arm/arm_neon.h
5744         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
5745         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
5746         (vst1q_f16_x3, vst1q_f32_x3): New.
5747         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
5748         (vst1q_bf16_x3): New.
5749         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
5750         * config/arm/neon.md
5751         (neon_vst1q_x3<mode>): New.
5752         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
5753         * config/arm/unspecs.md
5754         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
5755
5756 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5757
5758         * config/arm/arm_neon.h
5759         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
5760         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
5761         (vst1q_f16_x2, vst1q_f32_x2): New.
5762         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
5763         (vst1q_bf16_x2): New.
5764         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
5765         * config/arm/neon.md
5766         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5767         neon_vst1_x2<mode>.
5768         * config/arm/iterators.md
5769         (VMEMX2): New mode iterator.
5770         (VMEMX2_q): New mode attribute.
5771
5772 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5773
5774         * config/arm/arm_neon.h
5775         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
5776         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
5777         (vst1_f16_x4, vst1_f32_x4): New.
5778         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
5779         (vst1_bf16_x4): New.
5780         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
5781         * config/arm/neon.md (vst1_x4<mode>): New.
5782
5783 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5784
5785         * config/arm/arm_neon.h
5786         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
5787         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
5788         (vst1_f16_x3, vst1_f32_x3): New.
5789         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
5790         (vst1_bf16_x3): New.
5791         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
5792         * config/arm/neon.md (vst1_x3<mode>): New.
5793
5794 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5795
5796         * config/arm/arm_neon.h
5797         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
5798         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
5799         (vst1_f16_x2, vst1_f32_x2): New.
5800         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
5801         (vst1_bf16_x2): New.
5802         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
5803         * config/arm/neon.md (vst1_x2<mode>): New.
5804
5805 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5806
5807         * config/arm/arm_neon.h
5808         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
5809         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
5810         (vld1q_f16_x4, vld1q_f32_x4): New.
5811         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
5812         (vld1q_bf16_x4): New.
5813         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
5814         * config/arm/neon.md
5815         (neon_vld1_x4<mode>): New.
5816         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
5817         * config/arm/unspecs.md
5818         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
5819
5820 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5821
5822         * config/arm/arm_neon.h
5823         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
5824         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
5825         (vld1q_f16_x3, vld1q_f32_x3): New.
5826         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
5827         (vld1q_bf16_x3): New.
5828         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
5829         * config/arm/neon.md
5830         (neon_vld1_x3<mode>): New.
5831         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
5832         * config/arm/unspecs.md
5833         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
5834
5835 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
5836
5837         * config/arm/arm_neon.h
5838         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
5839         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
5840         (vld1q_f16_x2, vld1q_f32_x2): New.
5841         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
5842         (vld1q_bf16_x2): New.
5843         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
5844         * config/arm/neon.md (vld1_x2<mode>): New.
5845
5846 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
5847
5848         PR tree-optimization/113287
5849         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
5850
5851 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
5852
5853         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
5854         * tree-vect-loop.cc (vect_transform_loop): Likewise.
5855
5856 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
5857
5858         PR tree-optimization/113178
5859         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
5860         alternate exits.
5861
5862 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
5863
5864         PR tree-optimization/113237
5865         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
5866         existing LCSSA variable for exit when all exits are early break.
5867
5868 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
5869
5870         PR tree-optimization/113137
5871         PR tree-optimization/113136
5872         PR tree-optimization/113172
5873         PR tree-optimization/113178
5874         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5875         Maintain PHIs on inverted loops.
5876         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
5877         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
5878         latch.
5879         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
5880
5881 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
5882
5883         PR tree-optimization/113135
5884         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
5885         dependency analysis.
5886
5887 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
5888
5889         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
5890         diagnostics class member name for abort of error.
5891
5892 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
5893
5894         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
5895         format string to %s argument.
5896
5897 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
5898             Jakub Jelinek  <jakub@redhat.com>
5899
5900         PR middle-end/113182
5901         * varasm.cc (process_pending_assemble_externals,
5902         assemble_external_libcall): Use targetm.strip_name_encoding
5903         before calling get_identifier.
5904
5905 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
5906
5907         PR target/113196
5908         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
5909         New member variable.
5910         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
5911         Declare.
5912         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
5913         * config/aarch64/aarch64-simd.md
5914         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
5915         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
5916         zip2 for zero-extends to...
5917         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
5918         instruction.  Fix big-endian handling.
5919         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
5920         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
5921         zip1 for zero-extends to...
5922         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
5923         Fix big-endian handling.
5924         (*aarch64_zip1_uxtl): New pattern.
5925         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
5926         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
5927         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
5928         (aarch64_gen_shareable_zero): Use it.
5929         (aarch64_split_simd_shift_p): New function.
5930
5931 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
5932
5933         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
5934         (function_beg_insn): New macro.
5935         * function.cc (expand_function_start): Initialize function_beg_insn.
5936
5937 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
5938
5939         PR target/112989
5940         * config/aarch64/aarch64-sve-builtins.h
5941         (function_builder::m_overload_names): Replace with...
5942         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
5943         new global.
5944         (add_overloaded_function): Update accordingly, using get_identifier
5945         to get a GGC-friendly record of the name.
5946
5947 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
5948
5949         PR target/112989
5950         * config/aarch64/aarch64-sve-builtins.def: Don't include
5951         aarch64-sve-builtins-sme.def.
5952         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
5953         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
5954         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
5955         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
5956         requires AARCH64_FL_SME2.
5957         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
5958         AARCH64_FL_SME adjustment here.
5959         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
5960         include SME intrinsics.
5961         (sme_function_groups): New array.
5962         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
5963         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
5964
5965 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
5966
5967         PR target/113281
5968         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
5969         (struct cpu_vector_cost): Add regmove struct.
5970         (get_vector_costs): Export as global.
5971         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
5972         (costs::add_stmt_cost): Ditto.
5973         * config/riscv/riscv.cc (get_common_costs): Export global function.
5974
5975 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
5976
5977         PR tree-optimization/113334
5978         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
5979         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
5980         to determine if number should be extended by all ones rather than zero
5981         extended.
5982
5983 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
5984
5985         PR tree-optimization/113330
5986         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
5987         too large size.
5988
5989 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
5990
5991         PR tree-optimization/113323
5992         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
5993         check for lhs being large/huge _BitInt not in m_names.
5994
5995 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
5996
5997         PR tree-optimization/113316
5998         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
5999         uninitialized large/huge _BitInt arguments to calls.
6000
6001 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
6002
6003         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
6004         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
6005         CEIL (TYPE_PRECISION (t), limb_prec).
6006         (bitint_large_huge::handle_cast): Likewise.
6007
6008 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
6009
6010         PR sanitizer/113284
6011         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6012         Use assemble_function_label_final () for Power ELF V1 ABI.
6013         * output.h (assemble_function_label_final): New function.
6014         * varasm.cc (assemble_function_label_raw): Use
6015         assemble_function_label_final ().
6016         (assemble_function_label_final): New function.
6017
6018 2024-01-12  Richard Biener  <rguenther@suse.de>
6019
6020         PR middle-end/113344
6021         * match.pd ((double)float CMP (double)float -> float CMP float):
6022         Perform result type check only for vectors.
6023         * fold-const.cc (fold_binary_loc): Likewise.
6024
6025 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
6026
6027         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
6028         (usdot_prod<mode>): Ditto.
6029         (sdot_prod<mode>): Ditto.
6030         (udot_prod<mode>): Ditto.
6031
6032 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
6033
6034         PR target/113288
6035         * config/i386/i386-c.cc (ix86_target_macros_internal):
6036         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
6037
6038 2024-01-12  Richard Biener  <rguenther@suse.de>
6039
6040         PR target/112280
6041         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
6042         Do not generate code when d.testing_p.
6043
6044 2024-01-12  liuhongt  <hongtao.liu@intel.com>
6045
6046         PR target/113039
6047         * doc/invoke.texi (fcf-protection=): Update documents.
6048
6049 2024-01-12  Pan Li  <pan2.li@intel.com>
6050
6051         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
6052         comments of predicate func riscv_v_ext_mode_p.
6053
6054 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
6055
6056         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
6057                         Modify ABI-name length of vfloat16m8_t
6058
6059 2024-01-12  Li Wei  <liwei@loongson.cn>
6060
6061         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
6062         Adjust.
6063
6064 2024-01-12  Li Wei  <liwei@loongson.cn>
6065
6066         * config/loongarch/loongarch.md (add<mode>3): Removed.
6067         (*addsi3): New.
6068         (addsi3): Ditto.
6069         (adddi3): Ditto.
6070         (*addsi3_extended): Removed.
6071         (addsi3_extended): New.
6072
6073 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
6074
6075         * config/riscv/thead.md: Add limits for splits.
6076
6077 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
6078
6079         PR middle-end/113322
6080         * expr.cc (do_store_flag): Don't try single bit tests with
6081         comparison on vector types.
6082
6083 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
6084
6085         PR tree-optimization/113301
6086         * match.pd (`1/x`): Delay signed case until late.
6087
6088 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
6089
6090         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
6091         and -msp8 to...
6092         (AVR Internal Options): ...this new @subsubsection.
6093
6094 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
6095
6096         PR rtl-optimization/112918
6097         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
6098         (in_class_p): Restrict condition for narrowing class in case of
6099         allow_all_reload_class_changes_p.
6100         (process_alt_operands): Try to match operand without and with
6101         narrowing reg class.  Discourage narrowing the class.  Finish insn
6102         matching only if there is no class narrowing.
6103         (curr_insn_transform): Pass true to in_class_p for reg operand win.
6104
6105 2024-01-11  Richard Biener  <rguenther@suse.de>
6106
6107         PR tree-optimization/112505
6108         * tree-vect-loop.cc (vectorizable_induction): Reject
6109         bit-precision induction.
6110
6111 2024-01-11  Richard Biener  <rguenther@suse.de>
6112
6113         PR tree-optimization/113126
6114         * match.pd ((double)float CMP (double)float -> float CMP float):
6115         Make sure the boolean type is the same.
6116         * fold-const.cc (fold_binary_loc): Likewise.
6117
6118 2024-01-11  Richard Biener  <rguenther@suse.de>
6119
6120         PR tree-optimization/112636
6121         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
6122         estimate_numbers_of_iterations before querying
6123         get_max_loop_iterations_int.
6124         (pass_ch::execute): Initialize SCEV and loops appropriately.
6125
6126 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
6127
6128         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
6129         Reduced Tiny.
6130         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
6131         * doc/extend.texi (AVR Variable Attributes): Improve documentation
6132         of io, io_low and address attributes.
6133         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
6134         * doc/avr-mmcu.texi: Rebuild.
6135
6136 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
6137
6138         PR target/113233
6139         * config/loongarch/genopts/loongarch.opt.in: Mark options with
6140         the "Save" property.
6141         * config/loongarch/loongarch.opt: Same.
6142         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
6143         according to la_target.
6144         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
6145         RESTORE} for the la_target structure; Rename option conditions
6146         to have the same "la_" prefix.
6147         * config/loongarch/loongarch.h: Same.
6148
6149 2024-01-11  Pan Li  <pan2.li@intel.com>
6150
6151         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
6152         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
6153
6154 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
6155
6156         PR target/113077
6157         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
6158         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
6159         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
6160         synthesize these if needed.  Update caller ...
6161         (ldp_bb_info::fuse_pair): ... here.
6162         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
6163         and either insn is frame-related.
6164         (find_trailing_add): Punt on frame-related insns.
6165         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
6166         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
6167
6168 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
6169
6170         * config/mips/mips.cc (mips_start_function_definition):
6171         Add ATTRIBUTE_UNUSED.
6172
6173 2024-01-11  Richard Biener  <rguenther@suse.de>
6174
6175         PR middle-end/112740
6176         * expr.cc (store_constructor): Check the integer vector
6177         mask has a single bit per element before using sign-extension
6178         to expand an uniform vector.
6179
6180 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6181
6182         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
6183         preempt VLS on unknown NITERS loop.
6184
6185 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
6186
6187         * doc/invoke.texi: Add -mevex512.
6188
6189 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
6190
6191         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
6192         (*nor<mode>3): Likewise.
6193         (nor<mode>3): Likewise.
6194         (*negsi2_extended): New template.
6195         (*<optab>si3_internal): Likewise.
6196         (*one_cmplsi2_internal): Likewise.
6197         (*norsi3_internal): Likewise.
6198         (*<optab>nsi_internal): Likewise.
6199         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
6200         modified bit operation to make the optimization work.
6201
6202 2024-01-11  liuhongt  <hongtao.liu@intel.com>
6203
6204         PR target/104401
6205         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
6206
6207 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6208
6209         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
6210         (get_vector_costs): Ditto.
6211         (riscv_builtin_vectorization_cost): Ditto.
6212
6213 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6214
6215         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
6216
6217 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
6218
6219         PR jit/111396
6220         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
6221         ipa_free_size_summary.
6222         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
6223         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
6224         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
6225         * ipa-prop.h (ipa_prop_cc_finalize): New function.
6226         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
6227         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
6228         ipa_sra_cc_finalize): New functions.
6229         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
6230         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
6231         ipa_sra_cc_finalize
6232         Include ipa-utils.h.
6233
6234 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
6235
6236         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
6237         (th_int_get_save_adjustment): Likewise.
6238         (th_int_adjust_cfi_prologue): Likewise.
6239         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
6240         (TH_INT_INTERRUPT): New macro.
6241         (riscv_expand_prologue): Add the processing of XTheadInt.
6242         (riscv_expand_epilogue): Likewise.
6243         * config/riscv/riscv.h (BITSET_P): Moved to here.
6244         * config/riscv/riscv.md: New unspec.
6245         * config/riscv/thead.cc (th_int_get_mask): New function.
6246         (th_int_get_save_adjustment): Likewise.
6247         (th_int_adjust_cfi_prologue): Likewise.
6248         * config/riscv/thead.md (th_int_push): New pattern.
6249         (th_int_pop): new pattern.
6250
6251 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
6252
6253         PR tree-optimization/112468
6254         * doc/sourcebuild.texi: Document ifn_copysign.
6255         * match.pd: Only apply transformation if target supports the IFN.
6256
6257 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
6258
6259         PR tree-optimization/112581
6260         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
6261         mark_ssa_maybe_undefs.
6262         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
6263         variables can not be reassociated.
6264         (init_range_entry): Check for uninitialized variables too.
6265         (init_reassoc): Call mark_ssa_maybe_undefs.
6266
6267 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
6268
6269         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
6270         Also handle sign extension.
6271
6272 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
6273
6274         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
6275         to 0.
6276         (-mlate-ldp-fusion): Likewise.
6277
6278 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
6279
6280         PR tree-optimization/113287
6281         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
6282         instead of using BRANCH_EDGE to determine true edge.
6283
6284 2024-01-10  Richard Biener  <rguenther@suse.de>
6285
6286         PR tree-optimization/113078
6287         * tree-vect-loop.cc (check_reduction_path): Canonicalize
6288         .COND_SUB to .COND_ADD.
6289
6290 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
6291
6292         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
6293         Handle prefix mappings before calling find_opt.
6294         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
6295         "-fno-"-prefixed command-line option.
6296         * opts-common.cc (get_option_prefix_remapping): New.
6297         * opts.h (get_option_prefix_remapping): New decl.
6298
6299 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
6300
6301         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
6302         m_urlifier to pp_output_formatted_text.
6303         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
6304         (obstack_append_string): New overload, taking a length.
6305         (urlify_quoted_string): Pass in an obstack ptr, rather than using
6306         that of the pp's buffer.  Generalize to handle trailing text in
6307         the buffer beyond the run of quoted text.
6308         (class quoting_info): New.
6309         (on_begin_quote): New.
6310         (on_end_quote): New.
6311         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
6312         it to calls to on_begin_quote and on_end_quote.
6313         (struct auto_obstack): New.
6314         (quoting_info::handle_phase_3): New.
6315         (pp_output_formatted_text): Add urlifier param.  Use it if there
6316         is deferred urlification.  Delete m_quotes.
6317         (selftest::pp_printf_with_urlifier): Pass urlifier to
6318         pp_output_formatted_text.
6319         (selftest::test_urlification): Update results for the existing
6320         case of quoted text stradding chunks; add more such test cases.
6321         * pretty-print.h (class quoting_info): New forward decl.
6322         (chunk_info::m_quotes): New field.
6323         (pp_output_formatted_text): Add optional urlifier param.
6324
6325 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
6326
6327         * pretty-print.cc (selftest::test_pp_format): Add selftest
6328         coverage for numbered args.
6329
6330 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
6331
6332         PR tree-optimization/113144
6333         PR tree-optimization/113145
6334         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6335         Update all BB that the original exits dominated.
6336
6337 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
6338
6339         * dwarf2out.cc (modified_type_die): Extend the support of reverse
6340         storage order to enumeration types if -gstrict-dwarf is not passed.
6341         (gen_enumeration_type_die): Add REVERSE parameter and generate the
6342         DIE immediately after the existing one if it is true.
6343         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
6344         call to gen_enumeration_type_die.
6345         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
6346         first recursive call as well as the call to gen_tagged_type_die.
6347         (gen_type_die): Add REVERSE parameter and pass it in the call to
6348         gen_type_die_with_usage.
6349
6350 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
6351
6352         PR tree-optimization/113120
6353         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
6354         with root->size TYPE_PRECISION don't build anything new.
6355         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
6356         rather than build_nonstandard_integer_type.
6357
6358 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
6359
6360         * config/i386/i386.opt: Adjust document.
6361         * doc/invoke.texi: Add description for
6362         -mapx-inline-asm-use-gpr32.
6363
6364 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6365
6366         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
6367         (avg<v_double_trunc>3_floor): New pattern.
6368         (<u>avg<v_double_trunc>3_ceil): Remove.
6369         (avg<v_double_trunc>3_ceil): New pattern.
6370         (uavg<mode>3_floor): Ditto.
6371         (uavg<mode>3_ceil): Ditto.
6372         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
6373         (enum insn_type): Ditto.
6374         * config/riscv/riscv-v.cc: Ditto.
6375         * config/riscv/vector-iterators.md (ashiftrt): Remove.
6376         (ASHIFTRT): Ditto.
6377         * config/riscv/vector.md: Add VLS modes.
6378
6379 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
6380
6381         PR target/111480
6382         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
6383         (vczlsbb_char): New int attribute.
6384         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
6385         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
6386         (*vctzlsbb_zext_<mode>): Rename to ...
6387         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
6388         cover vclzlsbb.
6389
6390 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
6391
6392         PR target/112606
6393         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
6394         of the last argument from altivec_register_operand to any_operand.  If
6395         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
6396         otherwise if it doesn't satisfy altivec_register_operand, force it to
6397         REG using copy_to_mode_reg.
6398
6399 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
6400
6401         PR middle-end/113100
6402         * builtins.cc (expand_builtin_stack_address): Guard stack point
6403         adjustment with SPARC_STACK_BOUNDARY_HACK.
6404
6405 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
6406
6407         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
6408         argument string definitions.
6409         * config/loongarch/loongarch-str.h: Same.
6410         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
6411         as aliases to -mexplicit-relocs={always,none}
6412         * config/loongarch/loongarch.opt: Regenerate.
6413         * config/loongarch/loongarch.cc: Same.
6414
6415 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
6416
6417         * config/loongarch/loongarch-def.h: Define constants with
6418         enums instead of Macros.
6419
6420 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
6421
6422         * config/loongarch/genopts/loongarch-strings: Rename.
6423         * config/loongarch/genopts/loongarch.opt.in: Same.
6424         * config/loongarch/loongarch-cpu.cc: Same.
6425         * config/loongarch/loongarch-def.cc: Same.
6426         * config/loongarch/loongarch-def.h: Same.
6427         * config/loongarch/loongarch-opts.cc: Same.
6428         * config/loongarch/loongarch-opts.h: Same.
6429         * config/loongarch/loongarch-str.h: Same.
6430         * config/loongarch/loongarch.opt: Same.
6431
6432 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
6433
6434         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
6435         variable with the common la_ prefix.
6436         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
6437         flags as saved using TargetVariable.
6438         * config/loongarch/loongarch.opt: Same.
6439         * config/loongarch/loongarch-def.h: Define evolution_set to
6440         mark changes to the -march default.
6441         * config/loongarch/loongarch-driver.cc: Same.
6442         * config/loongarch/loongarch-opts.cc: Same.
6443         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
6444         conditions around the la_target structure.
6445         * config/loongarch/loongarch.cc: Same.
6446         * config/loongarch/loongarch.md: Same.
6447         * config/loongarch/loongarch-builtins.cc: Same.
6448         * config/loongarch/loongarch-c.cc: Same.
6449         * config/loongarch/lasx.md: Same.
6450         * config/loongarch/lsx.md: Same.
6451         * config/loongarch/sync.md: Same.
6452
6453 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
6454
6455         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
6456         no less.
6457
6458 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
6459
6460         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
6461
6462 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
6463
6464         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
6465         restart_loop.
6466         (vectorizable_live_operation): Likewise.
6467
6468 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
6469
6470         PR tree-optimization/113199
6471         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
6472         BIT_FIELD_REF.
6473
6474 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
6475
6476         PR target/113270
6477         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
6478         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
6479         GTY(()) declaration before the definition, drop GTY(()) drom the
6480         definition.
6481
6482 2024-01-09  Richard Biener  <rguenther@suse.de>
6483
6484         PR tree-optimization/113026
6485         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
6486         redundant and wrong niter bound setting.  Move niter
6487         bound adjustment down.
6488
6489 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
6490
6491         PR middle-end/113163
6492         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
6493         Reject non-linear inductions that aren't supported.
6494
6495 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
6496
6497         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
6498         left shift implementation strategies.
6499         (arc_shift_info): Type for each entry of the shift strategy table.
6500         (arc_shift_context_idx): Return a integer value for each code
6501         generation context, used as an index
6502         (arc_ashl_alg): Table indexed by context and shifted bit count.
6503         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
6504         left shift implementation.
6505         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
6506         provide accurate costs, when optimizing for speed or size.
6507
6508 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6509
6510         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
6511
6512 2024-01-09  Julian Brown  <julian@codesourcery.com>
6513
6514         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
6515         processed out before gimplification.
6516         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
6517         * tree.def (OMP_ARRAY_SECTION): New tree code.
6518
6519 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
6520
6521         PR tree-optimization/113210
6522         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
6523         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
6524         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
6525         minus 1.
6526
6527 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
6528
6529         PR rtl-optimization/113140
6530         * reorg.cc (fill_slots_from_thread): If we are to branch after the
6531         last instruction of the function, create an end label.
6532
6533 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
6534             Hongtao Liu  <hongtao.liu@intel.com>
6535
6536         PR target/112992
6537         * config/i386/i386-expand.cc
6538         (ix86_convert_const_wide_int_to_broadcast): Allow call to
6539         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
6540         (ix86_broadcast_from_constant): Revert recent change; Return a
6541         suitable MEMREF independently of mode/target combinations.
6542         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
6543         to decide whether expansion is possible/preferrable.  Only try
6544         forcing DImode constants to memory (and trying again) if calling
6545         ix86_expand_vector_init_duplicate fails with an DImode immediate
6546         constant.
6547         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
6548         V4SImode for suitable immediate constants.
6549         <case E_V4DImode>: Try using V8SImode for suitable constants.
6550         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
6551         <case E_V2HImode>: Likewise.
6552         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
6553         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
6554         <label widen>: Handle CONT_INTs via simplify_binary_operation.
6555         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
6556         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
6557         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
6558         (ix86_expand_vector_init): Move try using a broadcast for all_same
6559         with ix86_expand_vector_init_duplicate before using constant pool.
6560
6561 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
6562
6563         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
6564
6565 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
6566
6567         * config/arm/arm-cpus.in (cortex-m52): New cpu.
6568         * config/arm/arm-tables.opt: Regenerate.
6569         * config/arm/arm-tune.md: Regenerate.
6570
6571 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
6572
6573         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
6574         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
6575         (@vec_concatz<mode>): New insn pattern.
6576         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
6577         Handle VALS containing two vectors.
6578
6579 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6580
6581         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
6582         (vundefined): Ditto.
6583
6584 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
6585
6586         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6587                                 Add new function_base for crypto vector.
6588         (class bitmanip): Ditto.
6589         (class b_reverse):Ditto.
6590         (class vwsll):   Ditto.
6591         (class clmul):   Ditto.
6592         (class vg_nhab):  Ditto.
6593         (class crypto_vv):Ditto.
6594         (class crypto_vi):Ditto.
6595         (class vaeskf2_vsm3c):Ditto.
6596         (class vsm3me): Ditto.
6597         (BASE): Add BASE declaration for crypto vector.
6598         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6599         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6600                                 Add crypto vector intrinsic definition.
6601         (vbrev): Ditto.
6602         (vclz): Ditto.
6603         (vctz): Ditto.
6604         (vwsll): Ditto.
6605         (vandn): Ditto.
6606         (vbrev8): Ditto.
6607         (vrev8): Ditto.
6608         (vrol): Ditto.
6609         (vror): Ditto.
6610         (vclmul): Ditto.
6611         (vclmulh): Ditto.
6612         (vghsh): Ditto.
6613         (vgmul): Ditto.
6614         (vaesef): Ditto.
6615         (vaesem): Ditto.
6616         (vaesdf): Ditto.
6617         (vaesdm): Ditto.
6618         (vaesz): Ditto.
6619         (vaeskf1): Ditto.
6620         (vaeskf2): Ditto.
6621         (vsha2ms): Ditto.
6622         (vsha2ch): Ditto.
6623         (vsha2cl): Ditto.
6624         (vsm4k): Ditto.
6625         (vsm4r): Ditto.
6626         (vsm3me): Ditto.
6627         (vsm3c): Ditto.
6628         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6629                                 Add new function_shape for crypto vector.
6630         (struct crypto_vi_def): Ditto.
6631         (struct crypto_vv_no_op_type_def): Ditto.
6632         (SHAPE): Add SHAPE declaration of crypto vector.
6633         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6634         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6635                                 Add new data type for crypto vector.
6636         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6637         (vuint32mf2_t): Ditto.
6638         (vuint32m1_t): Ditto.
6639         (vuint32m2_t): Ditto.
6640         (vuint32m4_t): Ditto.
6641         (vuint32m8_t): Ditto.
6642         (vuint64m1_t): Ditto.
6643         (vuint64m2_t): Ditto.
6644         (vuint64m4_t): Ditto.
6645         (vuint64m8_t): Ditto.
6646         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6647                                 Add new data struct for crypto vector.
6648         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6649         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6650         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6651
6652 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
6653
6654         PR sanitizer/113251
6655         * varasm.cc (assemble_function_label_raw): Do not call
6656         asan_function_start () without the current function.
6657
6658 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
6659
6660         PR target/113225
6661         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
6662         extern and kernel_helper attributed function decls.
6663
6664 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
6665
6666         * btfout.cc (output_btf_strs): Changed.
6667
6668 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
6669
6670         * config/gcn/mkoffload.cc (main): Handle gfx1100
6671         when setting the default XNACK.
6672
6673 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
6674
6675         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
6676         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
6677         (ASM_SPEC): Handle gfx1100.
6678         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
6679         (enum gcn_isa): Add ISA_RDNA3.
6680         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
6681         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6682         * config/gcn/gcn.cc (gcn_option_override,
6683         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
6684         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
6685         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6686         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
6687         with gfx1100.
6688         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
6689         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
6690         __gfx1100__.
6691         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6692         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
6693         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
6694         (isa_has_combined_avgprs, main): Handle gfx1100.
6695         * config/gcn/t-omp-device (isa): Add gfx1100.
6696
6697 2024-01-08  Richard Biener  <rguenther@suse.de>
6698
6699         * doc/invoke.texi (-mmovbe): Clarify.
6700
6701 2024-01-08  Richard Biener  <rguenther@suse.de>
6702
6703         PR tree-optimization/113026
6704         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
6705         Avoid an epilog in more cases.
6706         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
6707         epilogues niter upper bounds and estimates.
6708
6709 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
6710
6711         PR tree-optimization/113228
6712         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
6713
6714 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
6715
6716         PR tree-optimization/113120
6717         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
6718         large _BitInt zero INTEGER_CST PHI argument.
6719
6720 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
6721
6722         PR tree-optimization/113119
6723         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
6724         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
6725         is before REALPART_EXPR.
6726
6727 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
6728
6729         PR target/112952
6730         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
6731         range when diagnosing attribute "io" and "io_low" are out of range.
6732         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
6733         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
6734         in contexts other than static storage.
6735         (avr_asm_output_aligned_decl_common): Move output of decls with
6736         attribute "address", "io", and "io_low" to...
6737         (avr_output_addr_attrib): ...this new function.
6738         (avr_asm_asm_output_aligned_bss): Remove output for decls with
6739         attribute "address", "io", and "io_low".
6740         (avr_encode_section_info): Rectify handling of decls with attribute
6741         "address", "io", and "io_low".
6742
6743 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
6744
6745         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
6746         (elf_flags): Remove XNACK from the default value.
6747         (main): Set a default XNACK according to the arch.
6748
6749 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
6750
6751         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
6752         (process_asm): Don't count avgprs.
6753
6754 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
6755
6756         * config/i386/i386.opt: Add supported sub-features.
6757         * doc/extend.texi: Add description for target attribute.
6758
6759 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
6760
6761         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
6762
6763 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
6764             Uros Bizjak  <ubizjak@gmail.com>
6765
6766         PR target/113231
6767         * config/i386/i386-features.cc (compute_convert_gain): Include
6768         the overhead of explicit load and store (movd) instructions when
6769         converting non-store scalar operations with memory destinations.
6770         Various indentation whitespace fixes.
6771
6772 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
6773
6774         * config/arm/neon.md (cbranch<mode>4): New.
6775
6776 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6777
6778         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
6779
6780 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
6781
6782         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
6783
6784 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6785
6786         PR target/113248
6787         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
6788         Update the MAX_SEW.
6789
6790 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6791
6792         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
6793         (variable_vectorized_p): Teach loop invariant.
6794         (has_unexpected_spills_p): Ditto.
6795
6796 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
6797
6798         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
6799         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
6800         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
6801
6802 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
6803
6804         PR target/113104
6805         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
6806         (aarch64-vect-compare-costs): ...this.
6807         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
6808         Replace with...
6809         (-param=aarch64-vect-compare-costs=): ...this new param.
6810         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
6811         Don't disable it when vectorizing for Advanced SIMD only.
6812         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
6813         whenever aarch64_vect_compare_costs is true.
6814
6815 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
6816
6817         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
6818         Modify the method of determining the memory offset of [x]vld/[x]vst.
6819         (lasx_mxst_<lasxfmt_f>): Likewise.
6820         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
6821         (loongarch_address_insns): Likewise.
6822         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
6823         (lsx_st_<lsxfmt_f>): Likewise.
6824         * config/loongarch/predicates.md (aq10b_operand): Likewise.
6825         (aq10h_operand): Likewise.
6826         (aq10w_operand): Likewise.
6827         (aq10d_operand): Likewise.
6828
6829 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
6830
6831         PR target/113217
6832         * config/aarch64/aarch64-ldp-fusion.cc
6833         (ldp_bb_info::try_fuse_pair): If the second access can throw,
6834         narrow the move range to exactly that insn.
6835
6836 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
6837
6838         * asan.cc (asan_function_start): Drop switch_to_section ().
6839         (asan_emit_stack_protection): Set .LASANPC alignment.
6840         * config/i386/i386.cc: Use assemble_function_label_raw ()
6841         instead of ASM_OUTPUT_LABEL ().
6842         * config/s390/s390.cc (s390_asm_output_function_label):
6843         Likewise.
6844         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
6845         * final.cc (final_start_function_1): Drop
6846         asan_function_start ().
6847         * output.h (assemble_function_label_raw): New function.
6848         * varasm.cc (assemble_function_label_raw): Likewise.
6849
6850 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
6851
6852         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
6853         Use ASM_OUTPUT_FUNCTION_LABEL ().
6854         * config/alpha/alpha.cc (alpha_start_function): Likewise.
6855         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6856         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
6857         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6858         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6859         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
6860         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6861         * config/ia64/ia64.cc (ia64_start_function): Likewise.
6862         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
6863         Likewise.
6864         * config/microblaze/microblaze.cc (microblaze_function_prologue):
6865         Likewise.
6866         * config/mips/mips.cc (mips_start_unique_function): Return the
6867         tree.
6868         (mips_start_function_definition): Use
6869         ASM_OUTPUT_FUNCTION_LABEL ().
6870         (mips_finish_stub): Pass the tree to
6871         mips_start_function_definition ().
6872         (mips16_build_function_stub): Likewise.
6873         (mips16_build_call_stub): Likewise.
6874         (mips_output_function_prologue): Likewise.
6875         * config/pa/pa.cc (pa_output_function_label): Use
6876         ASM_OUTPUT_FUNCTION_LABEL ().
6877         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
6878         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6879         Likewise.
6880         (rs6000_xcoff_declare_function_name): Likewise.
6881
6882 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
6883
6884         PR tree-optimization/113201
6885         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
6886         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
6887
6888 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
6889
6890         PR tree-optimization/90693
6891         * tree-ssa-math-opts.cc (match_single_bit_test): If
6892         tree_expr_nonzero_p (arg), remember it in the second argument to
6893         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
6894         arg ^ (arg - 1) > arg - 1.
6895         * internal-fn.cc (expand_POPCOUNT): If second argument to
6896         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
6897         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
6898
6899 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
6900
6901         * config/riscv/riscv-v.cc (expand_load_store):
6902         Remove `value`.
6903         (expand_cond_len_op): Ditto.
6904         (expand_gather_scatter): Ditto.
6905         (expand_lanes_load_store): Ditto.
6906         (expand_fold_extract_last): Ditto.
6907
6908 2024-01-05  Pan Li  <pan2.li@intel.com>
6909
6910         Revert:
6911         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
6912
6913         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6914                                 Add new function_base for crypto vector.
6915         (class bitmanip): Ditto.
6916         (class b_reverse):Ditto.
6917         (class vwsll):   Ditto.
6918         (class clmul):   Ditto.
6919         (class vg_nhab):  Ditto.
6920         (class crypto_vv):Ditto.
6921         (class crypto_vi):Ditto.
6922         (class vaeskf2_vsm3c):Ditto.
6923         (class vsm3me): Ditto.
6924         (BASE): Add BASE declaration for crypto vector.
6925         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6926         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6927                                 Add crypto vector intrinsic definition.
6928         (vbrev): Ditto.
6929         (vclz): Ditto.
6930         (vctz): Ditto.
6931         (vwsll): Ditto.
6932         (vandn): Ditto.
6933         (vbrev8): Ditto.
6934         (vrev8): Ditto.
6935         (vrol): Ditto.
6936         (vror): Ditto.
6937         (vclmul): Ditto.
6938         (vclmulh): Ditto.
6939         (vghsh): Ditto.
6940         (vgmul): Ditto.
6941         (vaesef): Ditto.
6942         (vaesem): Ditto.
6943         (vaesdf): Ditto.
6944         (vaesdm): Ditto.
6945         (vaesz): Ditto.
6946         (vaeskf1): Ditto.
6947         (vaeskf2): Ditto.
6948         (vsha2ms): Ditto.
6949         (vsha2ch): Ditto.
6950         (vsha2cl): Ditto.
6951         (vsm4k): Ditto.
6952         (vsm4r): Ditto.
6953         (vsm3me): Ditto.
6954         (vsm3c): Ditto.
6955         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6956                                 Add new function_shape for crypto vector.
6957         (struct crypto_vi_def): Ditto.
6958         (struct crypto_vv_no_op_type_def): Ditto.
6959         (SHAPE): Add SHAPE declaration of crypto vector.
6960         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6961         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6962                                 Add new data type for crypto vector.
6963         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6964         (vuint32mf2_t): Ditto.
6965         (vuint32m1_t): Ditto.
6966         (vuint32m2_t): Ditto.
6967         (vuint32m4_t): Ditto.
6968         (vuint32m8_t): Ditto.
6969         (vuint64m1_t): Ditto.
6970         (vuint64m2_t): Ditto.
6971         (vuint64m4_t): Ditto.
6972         (vuint64m8_t): Ditto.
6973         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6974                                 Add new data struct for crypto vector.
6975         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6976         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6977         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6978
6979 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
6980
6981         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6982                                 Add new function_base for crypto vector.
6983         (class bitmanip): Ditto.
6984         (class b_reverse):Ditto.
6985         (class vwsll):   Ditto.
6986         (class clmul):   Ditto.
6987         (class vg_nhab):  Ditto.
6988         (class crypto_vv):Ditto.
6989         (class crypto_vi):Ditto.
6990         (class vaeskf2_vsm3c):Ditto.
6991         (class vsm3me): Ditto.
6992         (BASE): Add BASE declaration for crypto vector.
6993         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6994         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6995                                 Add crypto vector intrinsic definition.
6996         (vbrev): Ditto.
6997         (vclz): Ditto.
6998         (vctz): Ditto.
6999         (vwsll): Ditto.
7000         (vandn): Ditto.
7001         (vbrev8): Ditto.
7002         (vrev8): Ditto.
7003         (vrol): Ditto.
7004         (vror): Ditto.
7005         (vclmul): Ditto.
7006         (vclmulh): Ditto.
7007         (vghsh): Ditto.
7008         (vgmul): Ditto.
7009         (vaesef): Ditto.
7010         (vaesem): Ditto.
7011         (vaesdf): Ditto.
7012         (vaesdm): Ditto.
7013         (vaesz): Ditto.
7014         (vaeskf1): Ditto.
7015         (vaeskf2): Ditto.
7016         (vsha2ms): Ditto.
7017         (vsha2ch): Ditto.
7018         (vsha2cl): Ditto.
7019         (vsm4k): Ditto.
7020         (vsm4r): Ditto.
7021         (vsm3me): Ditto.
7022         (vsm3c): Ditto.
7023         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7024                                 Add new function_shape for crypto vector.
7025         (struct crypto_vi_def): Ditto.
7026         (struct crypto_vv_no_op_type_def): Ditto.
7027         (SHAPE): Add SHAPE declaration of crypto vector.
7028         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7029         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7030                                 Add new data type for crypto vector.
7031         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7032         (vuint32mf2_t): Ditto.
7033         (vuint32m1_t): Ditto.
7034         (vuint32m2_t): Ditto.
7035         (vuint32m4_t): Ditto.
7036         (vuint32m8_t): Ditto.
7037         (vuint64m1_t): Ditto.
7038         (vuint64m2_t): Ditto.
7039         (vuint64m4_t): Ditto.
7040         (vuint64m8_t): Ditto.
7041         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7042                                 Add new data struct for crypto vector.
7043         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7044         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7045         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7046
7047 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7048
7049         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7050
7051 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
7052
7053         PR tree-optimization/113186
7054         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
7055         Match `^` with the `==` for 1bit integral types.
7056         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
7057         integral types.
7058
7059 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
7060
7061         * toplev.cc (general_init): Pass lang_mask to urlifier.
7062
7063 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
7064
7065         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
7066         param.
7067         (diagnostic_context::make_option_url): Update for lang_mask param.
7068         * gcc-urlifier.cc: Include "opts.h" and "options.h".
7069         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
7070         (gcc_urlifier::m_lang_mask): New field.
7071         (doc_urls): Make static.
7072         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
7073         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7074         Look for an option by name before trying a binary search in
7075         doc_urls.
7076         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7077         (gcc_urlifier::get_url_suffix_for_option): New.
7078         (make_gcc_urlifier): Add lang_mask param.
7079         (selftest::gcc_urlifier_cc_tests): Update for above changes.
7080         Verify that a URL is found for "-fpack-struct".
7081         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
7082         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
7083         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
7084         to make_gcc_urlifier.
7085         * opts-diagnostic.h (get_option_url): Add lang_mask param.
7086         * opts.cc (get_option_html_page): Remove special-casing for
7087         analyzer and LTO.
7088         (get_option_url_suffix): New.
7089         (get_option_url): Reimplement.
7090         (selftest::test_get_option_html_page): Rename to...
7091         (selftest::test_get_option_url_suffix): ...this and update for
7092         above changes.
7093         (selftest::opts_cc_tests): Update for renaming.
7094         * opts.h: Include "rich-location.h".
7095         (get_option_url_suffix): New decl.
7096
7097 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
7098
7099         * Makefile.in (ALL_OPT_URL_FILES): New.
7100         (GCC_OBJS): Add options-urls.o.
7101         (OBJS): Likewise.
7102         (OBJS-libcommon): Likewise.
7103         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
7104         inputs to opt-gather.awk.
7105         (options-urls.cc): New Makefile target.
7106         * opt-functions.awk (url_suffix): New function.
7107         (lang_url_suffix): New function.
7108         * options-urls-cc-gen.awk: New file.
7109         * opts.h (get_opt_url_suffix): New decl.
7110
7111 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
7112
7113         * params.opt.urls: New file, autogenerated by
7114         regenerate-opt-urls.py.
7115
7116 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
7117
7118         * common.opt.urls: New file, autogenerated by
7119         regenerate-opt-urls.py.
7120         * config/aarch64/aarch64.opt.urls: Likewise.
7121         * config/alpha/alpha.opt.urls: Likewise.
7122         * config/alpha/elf.opt.urls: Likewise.
7123         * config/arc/arc-tables.opt.urls: Likewise.
7124         * config/arc/arc.opt.urls: Likewise.
7125         * config/arm/arm-tables.opt.urls: Likewise.
7126         * config/arm/arm.opt.urls: Likewise.
7127         * config/arm/vxworks.opt.urls: Likewise.
7128         * config/avr/avr.opt.urls: Likewise.
7129         * config/bpf/bpf.opt.urls: Likewise.
7130         * config/c6x/c6x-tables.opt.urls: Likewise.
7131         * config/c6x/c6x.opt.urls: Likewise.
7132         * config/cris/cris.opt.urls: Likewise.
7133         * config/cris/elf.opt.urls: Likewise.
7134         * config/csky/csky.opt.urls: Likewise.
7135         * config/csky/csky_tables.opt.urls: Likewise.
7136         * config/darwin.opt.urls: Likewise.
7137         * config/dragonfly.opt.urls: Likewise.
7138         * config/epiphany/epiphany.opt.urls: Likewise.
7139         * config/fr30/fr30.opt.urls: Likewise.
7140         * config/freebsd.opt.urls: Likewise.
7141         * config/frv/frv.opt.urls: Likewise.
7142         * config/ft32/ft32.opt.urls: Likewise.
7143         * config/fused-madd.opt.urls: Likewise.
7144         * config/g.opt.urls: Likewise.
7145         * config/gcn/gcn.opt.urls: Likewise.
7146         * config/gnu-user.opt.urls: Likewise.
7147         * config/h8300/h8300.opt.urls: Likewise.
7148         * config/hpux11.opt.urls: Likewise.
7149         * config/i386/cygming.opt.urls: Likewise.
7150         * config/i386/cygwin.opt.urls: Likewise.
7151         * config/i386/djgpp.opt.urls: Likewise.
7152         * config/i386/i386.opt.urls: Likewise.
7153         * config/i386/mingw-w64.opt.urls: Likewise.
7154         * config/i386/mingw.opt.urls: Likewise.
7155         * config/i386/nto.opt.urls: Likewise.
7156         * config/ia64/ia64.opt.urls: Likewise.
7157         * config/ia64/ilp32.opt.urls: Likewise.
7158         * config/ia64/vms.opt.urls: Likewise.
7159         * config/iq2000/iq2000.opt.urls: Likewise.
7160         * config/linux-android.opt.urls: Likewise.
7161         * config/linux.opt.urls: Likewise.
7162         * config/lm32/lm32.opt.urls: Likewise.
7163         * config/loongarch/loongarch.opt.urls: Likewise.
7164         * config/lynx.opt.urls: Likewise.
7165         * config/m32c/m32c.opt.urls: Likewise.
7166         * config/m32r/m32r.opt.urls: Likewise.
7167         * config/m68k/ieee.opt.urls: Likewise.
7168         * config/m68k/m68k-tables.opt.urls: Likewise.
7169         * config/m68k/m68k.opt.urls: Likewise.
7170         * config/m68k/uclinux.opt.urls: Likewise.
7171         * config/mcore/mcore.opt.urls: Likewise.
7172         * config/microblaze/microblaze.opt.urls: Likewise.
7173         * config/mips/mips-tables.opt.urls: Likewise.
7174         * config/mips/mips.opt.urls: Likewise.
7175         * config/mips/sde.opt.urls: Likewise.
7176         * config/mmix/mmix.opt.urls: Likewise.
7177         * config/mn10300/mn10300.opt.urls: Likewise.
7178         * config/moxie/moxie.opt.urls: Likewise.
7179         * config/msp430/msp430.opt.urls: Likewise.
7180         * config/nds32/nds32-elf.opt.urls: Likewise.
7181         * config/nds32/nds32-linux.opt.urls: Likewise.
7182         * config/nds32/nds32.opt.urls: Likewise.
7183         * config/netbsd-elf.opt.urls: Likewise.
7184         * config/netbsd.opt.urls: Likewise.
7185         * config/nios2/elf.opt.urls: Likewise.
7186         * config/nios2/nios2.opt.urls: Likewise.
7187         * config/nvptx/nvptx-gen.opt.urls: Likewise.
7188         * config/nvptx/nvptx.opt.urls: Likewise.
7189         * config/openbsd.opt.urls: Likewise.
7190         * config/or1k/elf.opt.urls: Likewise.
7191         * config/or1k/or1k.opt.urls: Likewise.
7192         * config/pa/pa-hpux.opt.urls: Likewise.
7193         * config/pa/pa-hpux1010.opt.urls: Likewise.
7194         * config/pa/pa-hpux1111.opt.urls: Likewise.
7195         * config/pa/pa-hpux1131.opt.urls: Likewise.
7196         * config/pa/pa.opt.urls: Likewise.
7197         * config/pa/pa64-hpux.opt.urls: Likewise.
7198         * config/pdp11/pdp11.opt.urls: Likewise.
7199         * config/pru/pru.opt.urls: Likewise.
7200         * config/riscv/riscv.opt.urls: Likewise.
7201         * config/rl78/rl78.opt.urls: Likewise.
7202         * config/rpath.opt.urls: Likewise.
7203         * config/rs6000/476.opt.urls: Likewise.
7204         * config/rs6000/aix64.opt.urls: Likewise.
7205         * config/rs6000/darwin.opt.urls: Likewise.
7206         * config/rs6000/linux64.opt.urls: Likewise.
7207         * config/rs6000/rs6000-tables.opt.urls: Likewise.
7208         * config/rs6000/rs6000.opt.urls: Likewise.
7209         * config/rs6000/sysv4.opt.urls: Likewise.
7210         * config/rtems.opt.urls: Likewise.
7211         * config/rx/elf.opt.urls: Likewise.
7212         * config/rx/rx.opt.urls: Likewise.
7213         * config/s390/s390.opt.urls: Likewise.
7214         * config/s390/tpf.opt.urls: Likewise.
7215         * config/sh/sh.opt.urls: Likewise.
7216         * config/sh/superh.opt.urls: Likewise.
7217         * config/sol2.opt.urls: Likewise.
7218         * config/sparc/long-double-switch.opt.urls: Likewise.
7219         * config/sparc/sparc.opt.urls: Likewise.
7220         * config/stormy16/stormy16.opt.urls: Likewise.
7221         * config/v850/v850.opt.urls: Likewise.
7222         * config/vax/elf.opt.urls: Likewise.
7223         * config/vax/vax.opt.urls: Likewise.
7224         * config/visium/visium.opt.urls: Likewise.
7225         * config/vms/vms.opt.urls: Likewise.
7226         * config/vxworks-smp.opt.urls: Likewise.
7227         * config/vxworks.opt.urls: Likewise.
7228         * config/xtensa/elf.opt.urls: Likewise.
7229         * config/xtensa/uclinux.opt.urls: Likewise.
7230         * config/xtensa/xtensa.opt.urls: Likewise.
7231         * config/bfin/bfin.opt.urls: New file.
7232
7233 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
7234
7235         * Makefile.in (OPT_URLS_HTML_DEPS): New.
7236         (regenerate-opt-urls): New target.
7237         (regenerate-opt-urls-unit-test): New target.
7238         * doc/options.texi (Option properties): Add UrlSuffix and
7239         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
7240         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
7241         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
7242         and Makefile.in's OPT_URLS_HTML_DEPS.
7243         (Anatomy of a Target Back End): Add
7244         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
7245         * regenerate-opt-urls.py: New file.
7246
7247 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
7248
7249         * diagnostic-format-sarif.cc
7250         (sarif_builder::make_logical_location_object): Convert to...
7251         (make_sarif_logical_location_object): ...this.
7252         (sarif_builder::set_any_logical_locs_arr): Update for above
7253         change.
7254         (sarif_builder::make_thread_flow_location_object): Call
7255         maybe_add_sarif_properties on each diagnostic_event.
7256         * diagnostic-format-sarif.h (class logical_location): New forward
7257         decl.
7258         (make_sarif_logical_location_object): New decl.
7259         * diagnostic-path.h (class sarif_object): New forward decl.
7260         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
7261
7262 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
7263             Patrick Lin  <patrick@andestech.com>
7264             Rufus Chen  <rufus@andestech.com>
7265             Monk Chiang  <monk.chiang@sifive.com>
7266
7267         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
7268         with Nan-boxing value.
7269         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
7270
7271 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
7272             Jeff Law  <jlaw@ventanamicro.com>
7273
7274         PR rtl-optimization/104914
7275         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
7276         a sign or zero extension is only required if the modified field
7277         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
7278         targets, don't refer to the temporarily incorrectly extended value
7279         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
7280
7281 2024-01-04  Pan Li  <pan2.li@intel.com>
7282
7283         Revert:
7284         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7285
7286         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7287
7288 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7289
7290         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7291
7292 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
7293
7294         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
7295         offset of fcsr.
7296
7297 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7298
7299         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
7300         (compute_nregs_for_mode): Refine LMUL.
7301         (max_number_of_live_regs): Ditto.
7302         (compute_estimated_lmul): Ditto.
7303         (has_unexpected_spills_p): Ditto.
7304
7305 2024-01-04  Li Wei  <liwei@loongson.cn>
7306
7307         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
7308         Remove useless forward declaration.
7309         (loongarch_is_even_extraction): Remove useless forward declaration.
7310         (loongarch_try_expand_lsx_vshuf_const): Removed.
7311         (loongarch_expand_vec_perm_const_1): Merged.
7312         (loongarch_is_double_duplicate): Removed.
7313         (loongarch_is_center_extraction): Ditto.
7314         (loongarch_is_reversing_permutation): Ditto.
7315         (loongarch_is_di_misalign_extract): Ditto.
7316         (loongarch_is_si_misalign_extract): Ditto.
7317         (loongarch_is_lasx_lowpart_extract): Ditto.
7318         (loongarch_is_op_reverse_perm): Ditto.
7319         (loongarch_is_single_op_perm): Ditto.
7320         (loongarch_is_divisible_perm): Ditto.
7321         (loongarch_is_triple_stride_extract): Ditto.
7322         (loongarch_expand_vec_perm_const_2): Merged.
7323         (loongarch_expand_vec_perm_const): New.
7324         (loongarch_vectorize_vec_perm_const): Adjust.
7325
7326 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
7327
7328         * omp-general.cc: Fix comment typos and misplaced/confusing
7329         comments.  Delete redundant include of omp-general.h.
7330
7331 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
7332
7333         PR rtl-optimization/104914
7334         * config/mips/mips.md (insqisi_extended): New patterns.
7335         (inshisi_extended): Ditto.
7336
7337 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
7338
7339         * config/mips/mips.cc (mips_insn_cost): New function.
7340
7341 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
7342
7343         * config/mips/mips.md (perf_ratio): New attribute.
7344
7345 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7346
7347         PR target/113206
7348         PR target/113209
7349         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
7350         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
7351         blocks belong to infinite loop.
7352         (pre_vsetvl::emit_vsetvl): Remove fake edges.
7353         * config/riscv/t-riscv: Add a new include file.
7354
7355 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7356
7357         * config/riscv/vector.md: Fix indent.
7358
7359 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
7360
7361         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
7362         OMP_CLAUSE__SIMDUID_.
7363         * tree.cc (omp_clause_num_ops): Update position of entry for
7364         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
7365         (omp_clause_code_name): Likewise.
7366
7367 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
7368
7369         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
7370         printing of FUNC_MAP/IND_FUNC_MAP labels.
7371
7372 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
7373
7374         * gcc.cc (process_command): Update copyright notice dates.
7375         * gcov-dump.cc (print_version): Ditto.
7376         * gcov.cc (print_version): Ditto.
7377         * gcov-tool.cc (print_version): Ditto.
7378         * gengtype.cc (create_file): Ditto.
7379         * doc/cpp.texi: Bump @copying's copyright year.
7380         * doc/cppinternals.texi: Ditto.
7381         * doc/gcc.texi: Ditto.
7382         * doc/gccint.texi: Ditto.
7383         * doc/gcov.texi: Ditto.
7384         * doc/install.texi: Ditto.
7385         * doc/invoke.texi: Ditto.
7386
7387 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
7388
7389         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
7390         (fmin<mode>3): Likewise.
7391         (reduc_fmax_scal_<mode>3): New define_expand.
7392         (reduc_fmin_scal_<mode>3): Likewise.
7393
7394 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7395
7396         PR target/113112
7397         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
7398         (max_number_of_live_regs): Ditto.
7399         (has_unexpected_spills_p): Ditto.
7400
7401 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
7402             Jin Ma  <jinma@linux.alibaba.com>
7403             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
7404             Christoph Müllner  <christoph.muellner@vrull.eu>
7405
7406         * config/riscv/vector.md:
7407         Use vector_length_operand for vsetvl patterns.
7408
7409 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7410
7411         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
7412         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
7413
7414 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
7415
7416         * config/aarch64/aarch64-tuning-flags.def
7417         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
7418         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
7419         * config/aarch64/aarch64.cc
7420         (aarch64_override_options_internal): Set
7421         param_fully_pipelined_fma according to tuning option.
7422         * config/aarch64/tuning_models/ampere1.h: Add
7423         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
7424         * config/aarch64/tuning_models/ampere1a.h: Likewise.
7425         * config/aarch64/tuning_models/ampere1b.h: Likewise.
7426
7427 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
7428
7429         * config/riscv/vector-crypto.md: Modify copyright year.
7430
7431 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7432
7433         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
7434
7435 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
7436
7437         * config.in: Regenerate.
7438         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
7439         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
7440         Added TLS Le Relax support.
7441         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
7442         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
7443         * configure: Regenerate.
7444         * configure.ac: Check if binutils supports TLS le relax.
7445
7446 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
7447
7448         * config/riscv/iterators.md: Add rotate insn name.
7449         * config/riscv/riscv.md: Add new insns name for crypto vector.
7450         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
7451         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
7452         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
7453
7454 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
7455
7456         PR target/113112
7457         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
7458         pointer type liveness count.
7459 \f
7460 Copyright (C) 2024 Free Software Foundation, Inc.
7461
7462 Copying and distribution of this file, with or without modification,
7463 are permitted in any medium without royalty provided the copyright
7464 notice and this notice are preserved.