gcc/ChangeLog

   1 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
   2
   3         PR ipa/108470
   4         * doc/extend.texi (Common Function Attributes): Document that
   5         noinline also disables some interprocedural optimizations and
   6         improve flow to the part about using inline asm instead to
   7         disable calls from being optimized away completely.  Remove the
   8         sentence that says noipa is mainly for internal compiler testing.
   9
  10 2024-01-18  John David Anglin  <danglin@gcc.gnu.org>
  11
  12         PR tree-optimization/69807
  13         * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
  14
  15 2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>
  16
  17         PR target/108521
  18         * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
  19         from x86 Windows Options.
  20
  21 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
  22
  23         PR c/107942
  24         * doc/extend.texi (C Extensions): Add new section to menu.
  25         (Function Attributes):  Move dangling index entries to....
  26         (Const and Volatile Functions): New section.
  27
  28 2024-01-18  David Malcolm  <dmalcolm@redhat.com>
  29
  30         PR middle-end/112684
  31         * toplev.cc (toplev::main): Don't ICE in
  32         -fdiagnostics-generate-patch when exiting after options,
  33         since no edit context will have been created.
  34
  35 2024-01-18  Richard Biener  <rguenther@suse.de>
  36
  37         * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
  38         operands vector.
  39
  40 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
  41
  42         * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
  43         when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
  44
  45 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
  46             Jin Ma  <jinma@linux.alibaba.com>
  47             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
  48             Christoph Müllner  <christoph.muellner@vrull.eu>
  49
  50         * config/riscv/thead.cc
  51         (th_asm_output_opcode): Rewrite some instructions.
  52
  53 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
  54             Jin Ma  <jinma@linux.alibaba.com>
  55             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
  56             Christoph Müllner  <christoph.muellner@vrull.eu>
  57
  58         * config/riscv/riscv.md (none,thv,rvv): New attribute.
  59         (no,yes): Add an attribute to disable alternative
  60         for xtheadvector or RVV1.0.
  61         * config/riscv/vector.md:
  62         Disable alternatives that destination register overlaps
  63         source register group for xtheadvector.
  64
  65 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
  66             Jin Ma  <jinma@linux.alibaba.com>
  67             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
  68             Christoph Müllner  <christoph.muellner@vrull.eu>
  69
  70         * config/riscv/riscv-vector-builtins-bases.cc
  71         (class th_loadstore_width): Define new builtin bases.
  72         (class th_extract): Define new builtin bases.
  73         (BASE): Define new builtin bases.
  74         * config/riscv/riscv-vector-builtins-bases.h:
  75         Define new builtin class.
  76         * config/riscv/riscv-vector-builtins-shapes.cc
  77         (struct th_loadstore_width_def): Define new builtin shapes.
  78         (struct th_indexed_loadstore_width_def):
  79         Define new builtin shapes.
  80         (struct th_extract_def): Define new builtin shapes.
  81         (SHAPE): Define new builtin shapes.
  82         * config/riscv/riscv-vector-builtins-shapes.h:
  83         Define new builtin shapes.
  84         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
  85         Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
  86         * config/riscv/riscv-vector-builtins.h
  87         (enum required_ext): Add new XTheadVector member.
  88         (struct function_group_info): Likewise.
  89         * config/riscv/t-riscv:
  90         Add thead-vector-builtins-functions.def
  91         * config/riscv/thead-vector.md
  92         (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
  93         (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
  94         (@pred_store_width<vlmem_op_attr><mode>): Likewise.
  95         (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
  96         (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
  97         (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
  98         (@pred_th_extract<mode>): Likewise.
  99         (*pred_th_extract<mode>): Likewise.
 100         * config/riscv/thead-vector-builtins-functions.def: New file.
 101
 102 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 103             Jin Ma  <jinma@linux.alibaba.com>
 104             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 105             Christoph Müllner  <christoph.muellner@vrull.eu>
 106
 107         * config.gcc:  Add files for XTheadVector intrinsics.
 108         * config/riscv/autovec.md: Guard XTheadVector.
 109         * config/riscv/predicates.md: Disable immediate vl
 110         for XTheadVector.
 111         * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
 112         Add pragma for XTheadVector.
 113         * config/riscv/riscv-string.cc (riscv_expand_block_move):
 114         Guard XTheadVector.
 115         * config/riscv/riscv-v.cc (vls_mode_valid_p):
 116         Avoid autovec.
 117         * config/riscv/riscv-vector-builtins-bases.cc:
 118         Do not normalize vsetvl instructions for XTheadVector.
 119         * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
 120         New check type function.
 121         (build_one): Adjust for XTheadVector.
 122         * config/riscv/riscv-vector-switch.def (ENTRY):
 123         Disable fractional mode for the XTheadVector extension.
 124         (TUPLE_ENTRY): Likewise.
 125         * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
 126         Guard XTheadVector.
 127         (riscv_preferred_simd_mode): Likewsie.
 128         (riscv_autovectorize_vector_modes): Likewise.
 129         (riscv_vector_mode_supported_any_target_p): Likewise.
 130         (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
 131         * config/riscv/thead.cc (th_asm_output_opcode):
 132         Rewrite vsetvl instructions.
 133         * config/riscv/vector.md:
 134         Include thead-vector.md and change fractional LMUL
 135         into 1 for vbool.
 136         * config/riscv/riscv_th_vector.h: New file.
 137         * config/riscv/thead-vector.md: New file.
 138
 139 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 140             Jin Ma  <jinma@linux.alibaba.com>
 141             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 142             Christoph Müllner  <christoph.muellner@vrull.eu>
 143
 144         * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
 145         Add new function to add assembler insn code prefix/suffix.
 146         (th_asm_output_opcode):
 147         Add Thead function to add assembler insn code prefix/suffix.
 148         * config/riscv/riscv.cc (riscv_asm_output_opcode):
 149         Implement function to add assembler insn code prefix/suffix.
 150         * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
 151         Add new function to add assembler insn code prefix/suffix.
 152         * config/riscv/thead.cc (th_asm_output_opcode):
 153         Implement Thead function to add assembler insn code
 154         prefix/suffix.
 155
 156 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
 157             Jin Ma  <jinma@linux.alibaba.com>
 158             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
 159             Christoph Müllner  <christoph.muellner@vrull.eu>
 160
 161         * common/config/riscv/riscv-common.cc
 162         (riscv_subset_list::parse): Add new vendor extension.
 163         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
 164         Add test marco.
 165         * config/riscv/riscv.opt:  Add new mask.
 166
 167 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 168
 169         * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
 170         to be conditional on macosx-version-min.
 171
 172 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 173
 174         * config/darwin.cc (darwin_objc1_section): Use the correct
 175         meta-data version for constant strings.
 176         (machopic_select_section): Assert if we fail to handle CFString
 177         sections as Obejctive-C meta-data or drectly.
 178
 179 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 180
 181         * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
 182         OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
 183         OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
 184         versions when the object format is Mach-O.
 185
 186 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
 187
 188         PR target/105522
 189         * config/darwin.cc (machopic_select_section): Handle C and C++
 190         CFStrings.
 191         (darwin_rename_builtins): Move this out of the CFString code.
 192         (darwin_libc_has_function): Likewise.
 193         (darwin_build_constant_cfstring): Create an anonymous var to
 194         hold each CFString.
 195         * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
 196         CFstrings.
 197
 198 2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
 199
 200         PR bootstrap/113445
 201         * haifa-sched.cc (dep_list_size): Make global.
 202         * sched-deps.cc (find_inc): Use instead of sd_lists_size().
 203         * sched-int.h (dep_list_size): Declare.
 204
 205 2024-01-18  Martin Jambor  <mjambor@suse.cz>
 206
 207         PR tree-optimization/110422
 208         * tree-sra.cc (scan_function): Disqualify bases of operands of asm
 209         gotos.
 210
 211 2024-01-18  Richard Biener  <rguenther@suse.de>
 212
 213         PR tree-optimization/113475
 214         * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
 215         * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
 216         (phi_analyzer::~phi_analyzer): Deallocate and free collected
 217         phi_grous.
 218         (phi_analyzer::process_phi): Record allocated phi_groups.
 219
 220 2024-01-18  Richard Biener  <rguenther@suse.de>
 221
 222         * tree-vect-stmts.cc (vectorizable_store): Do not allocate
 223         storage for gvec_oprnds elements.
 224
 225 2024-01-18  Richard Biener  <rguenther@suse.de>
 226
 227         * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
 228         prefer all later exits we can handle.
 229         (vect_analyze_loop_form): Free the allocated loop body.
 230         Adjust comments.
 231
 232 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 233
 234         * config/avr/avr-log.cc: Tabify.
 235
 236 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 237
 238         * config/riscv/autovec.md: Support vi variant.
 239
 240 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 241
 242         * config/avr/avr-devices.cc: Tabify.
 243
 244 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 245
 246         * config/avr/avr-c.cc: Tabify.
 247
 248 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 249
 250         * config/avr/driver-avr.cc: Tabify.
 251
 252 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 253
 254         * config/avr/gen-avr-mmcu-texi.cc: Tabify.
 255
 256 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 257
 258         * config/avr/gen-avr-mmcu-specs.cc: Tabify.
 259
 260 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
 261
 262         * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
 263         minline-strcmp, minline-strncmp, minline-strlen,
 264         -param=riscv-vector-abi): Remove Bool keywords.
 265
 266 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
 267
 268         PR target/113122
 269         * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
 270         support.  Add missing space after , in emitted assembly in some
 271         cases.  Formatting fixes.
 272
 273 2024-01-18  Xi Ruoyao  <xry111@xry111.site>
 274
 275         * config/loongarch/loongarch.md (movsi_internal): Remove
 276         constraint z.
 277
 278 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
 279
 280         * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
 281         in the diagnostic, and capitalize the device name.
 282         (print_mcu): Generate specs such that:
 283         <*check_rodata_in_ram>: New.
 284         <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
 285         <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
 286         <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
 287
 288 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
 289
 290         PR other/113399
 291         * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
 292         Common and Optimization.
 293
 294 2024-01-18  Richard Biener  <rguenther@suse.de>
 295
 296         PR tree-optimization/113431
 297         * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
 298         When there is an invariant load we might not preserve
 299         scalar order.
 300
 301 2024-01-18  Richard Biener  <rguenther@suse.de>
 302
 303         PR tree-optimization/113374
 304         * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
 305         * tree-vect-loop.cc (move_early_exit_stmts): Update
 306         virtual LC PHIs.
 307         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 308         Refactor.  Preserve virtual LC PHIs on all exits.
 309
 310 2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>
 311
 312         * config/loongarch/loongarch.cc (loongarch_split_symbol):
 313         Assign the '/u' attribute to the mem.
 314
 315 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 316
 317         PR middle-end/110847
 318         * doc/invoke.texi (Option Summary): Document negative forms of
 319         -Wtsan and -Wxor-used-as-pow.
 320         (Warning Options): Likewise.
 321
 322 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 323
 324         PR target/113429
 325         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
 326
 327 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
 328
 329         * doc/extend.texi (Common Function Attributes): Re-alphabetize
 330         the table.
 331         (Common Variable Attributes): Likewise.
 332         (Common Type Attributes): Likewise.
 333
 334 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
 335
 336         PR middle-end/111659
 337         * doc/extend.texi (Common Variable Attributes): Fix long lines
 338         in documentation of strict_flex_array + other minor copy-editing.
 339         Add a cross-reference to -Wstrict-flex-arrays.
 340         * doc/invoke.texi (Option Summary): Fix whitespace in tables
 341         before -fstrict-flex-arrays and -Wstrict-flex-arrays.
 342         (C Dialect Options): Combine the docs for the two
 343         -fstrict-flex-arrays forms into a single entry.  Note this option
 344         is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
 345         (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
 346         Minor copy-editing.  Add cross references to the strict_flex_array
 347         attribute and -fstrict-flex-arrays option.  Add note that this
 348         option depends on -ftree-vrp.
 349
 350 2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>
 351
 352         PR target/113221
 353         * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
 354         only allow REG operands instead of allowing all.
 355
 356 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
 357
 358         * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
 359         Remove redundant checks in else condition for readablity.
 360         (earliest_fuse_vsetvl_info) Print iteration count in debug
 361         prints.
 362         (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
 363         dump details in certain cases.
 364
 365 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
 366
 367         * config/riscv/riscv.opt: New -param=vsetvl-strategy.
 368         * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
 369         * config/riscv/riscv-vsetvl.cc
 370         (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
 371         (pass_vsetvl::execute): Use vsetvl_strategy.
 372
 373 2024-01-17  Jan Hubicka  <jh@suse.cz>
 374
 375         * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
 376         accidental hack reseting offset.
 377
 378 2024-01-17  Jan Hubicka  <jh@suse.cz>
 379
 380         * config/i386/i386-options.cc (ix86_option_override_internal): Fix
 381         handling of X86_TUNE_AVOID_512FMA_CHAINS.
 382
 383 2024-01-17  Jan Hubicka  <jh@suse.cz>
 384             Jakub Jelinek  <jakub@redhat.com>
 385
 386         PR tree-optimization/110852
 387         * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
 388         binary operations
 389         (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
 390         PRED_COMBINED_VALUE_PREDICTIONS_PHI
 391         * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
 392         (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
 393
 394 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 395
 396         PR tree-optimization/113421
 397         * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
 398         comment.
 399         (bitint_dom_walker::before_dom_children): Add g temporary to simplify
 400         formatting.  Start at vop rather than cvop even if stmt is a store
 401         and needs_operand_addr.
 402
 403 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 404
 405         PR middle-end/113410
 406         * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
 407         If access_nelts is integral with larger precision than sizetype,
 408         fold_convert it to sizetype.
 409
 410 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 411
 412         PR tree-optimization/113408
 413         * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
 414         VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
 415         to handle_cast.
 416
 417 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 418
 419         PR middle-end/113406
 420         * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
 421         regardless of whether is_gimple_reg_type (restype) or not.
 422
 423 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 424
 425         * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
 426         funcions -> functions, and use were instead of was.
 427         * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
 428         and guaranteee -> guarantee.
 429         * attribs.h (struct attr_access): Fix comment typo funcion -> function.
 430
 431 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
 432
 433         PR middle-end/113409
 434         * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
 435         INTEGER_TYPE.
 436         (omp_extract_for_data): Use build_bitint_type rather than
 437         build_nonstandard_integer_type if either iter_type or loop->v type
 438         is BITINT_TYPE.
 439         * omp-expand.cc (expand_omp_for_generic,
 440         expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
 441         BITINT_TYPE like INTEGER_TYPE.
 442
 443 2024-01-17  Richard Biener  <rguenther@suse.de>
 444
 445         PR tree-optimization/113371
 446         * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
 447         Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
 448         * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
 449         not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
 450
 451 2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
 452
 453         PR rtl-optimization/96388
 454         PR rtl-optimization/111554
 455         * sched-deps.cc (find_inc): Avoid exponential behavior.
 456
 457 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
 458
 459         PR c/111693
 460         * doc/invoke.texi (Option Summary): Move -Wuseless-cast
 461         from C++ Language Options to Warning Options.  Add entry for
 462         -Wuse-after-free.
 463         (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
 464         from here....
 465         (Warning Options): ...to here.  Minor copy-editing to fix typo
 466         and grammar.
 467
 468 2024-01-17  YunQiang Su  <syq@gcc.gnu.org>
 469
 470         * config/mips/mips.cc (mips_compute_frame_info): If another
 471         register is used as global_pointer, mark $GP live false.
 472
 473 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
 474
 475         PR target/112973
 476         * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
 477         give the section a light copy-editing pass.
 478
 479 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
 480
 481         * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
 482         * config/aarch64/aarch64-tune.md: Regenerated.
 483         * doc/invoke.texi (-mcpu): Add cobalt-100 core.
 484
 485 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
 486
 487         PR target/112573
 488         * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
 489         badly formed CONST expressions.
 490
 491 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
 492
 493         * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
 494
 495 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
 496
 497         * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
 498         * config/sparc/sync.md (membar_storeload): Turn into named insn
 499         and add GR712RC errata workaround.
 500         (membar_v8): Add GR712RC errata workaround.
 501
 502 2024-01-16  Andreas Larsson  <andreas@gaisler.com>
 503
 504         * config/sparc/sync.md (*membar_storeload_leon3): Remove
 505         (*membar_storeload): Enable for LEON
 506
 507 2024-01-16  Jakub Jelinek  <jakub@redhat.com>
 508
 509         PR tree-optimization/113372
 510         PR middle-end/90348
 511         PR middle-end/110115
 512         PR middle-end/111422
 513         * cfgexpand.cc (add_scope_conflicts_2): New function.
 514         (add_scope_conflicts_1): Use it.
 515
 516 2024-01-16  Georg-Johann Lay  <avr@gjlay.de>
 517
 518         * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
 519         (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
 520         * doc/avr-mmcu.texi: Regenerate.
 521
 522 2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>
 523
 524         PR tree-optimization/113091
 525         * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
 526         (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
 527         scalar use with new function.
 528         (vect_bb_slp_mark_live_stmts): New function as entry to existing
 529         overriden functions with same name.
 530         (vect_slp_analyze_operations): Call new entry function to mark
 531         live statements.
 532
 533 2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 534
 535         PR target/113404
 536         * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
 537         for RVV in big-endian mode.
 538
 539 2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>
 540
 541         * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
 542         (riscv_pass_in_vector_p): Delete.
 543         (riscv_init_cumulative_args): Delete the checking.
 544         (riscv_get_arg_info): Delete the checking.
 545         (riscv_function_value): Delete the checking.
 546         * config/riscv/riscv.h: Delete the member for checking.
 547
 548 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
 549
 550         * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
 551
 552 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
 553
 554         * config.gcc: Include riscv_bitmanip.h.
 555         * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
 556         * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
 557         * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
 558         (RISCV_BUILTIN_NO_PREFIX): New helper macro.
 559         * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
 560         * config/riscv/riscv-ftypes.def (2): New ftypes.
 561         * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
 562         (RISCV_BUILTIN_NO_PREFIX): Likewise.
 563         * config/riscv/riscv_bitmanip.h: New file.
 564
 565 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
 566
 567         * config.gcc: Include riscv_crypto.h.
 568         * config/riscv/riscv_crypto.h: New file.
 569
 570 2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>
 571
 572         PR middle-end/113354
 573         * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
 574         in the insn if the corresponding operand does not require hard
 575         register anymore.
 576
 577 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
 578
 579         PR target/107201
 580         * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
 581         * config/avr/driver-avr.cc (avr_no_devlib): New function.
 582         (avr_devicespecs_file): Use it to remove -nodevicelib from the
 583         options for cores only.
 584         * config/avr/avr-arch.h (avr_get_parch): New prototype.
 585         * config/avr/avr-devices.cc (avr_get_parch): New function.
 586
 587 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 588
 589         PR target/113247
 590         * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
 591         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
 592         * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
 593
 594 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 595
 596         PR target/113281
 597         * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
 598         (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
 599         * config/riscv/riscv-vector-costs.h: New function.
 600
 601 2024-01-15  Richard Biener  <rguenther@suse.de>
 602
 603         PR tree-optimization/113385
 604         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 605         First redirect, then split the exit edge.
 606
 607 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 608
 609         * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
 610         Remove m_num_vector_iterations.
 611         * config/riscv/riscv-vector-costs.h: Ditto.
 612
 613 2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>
 614
 615         PR target/113156
 616         * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
 617         (-mbranch-cost): Set "Optimization" flag.
 618
 619 2024-01-15  Jakub Jelinek  <jakub@redhat.com>
 620
 621         PR tree-optimization/113370
 622         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
 623         set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
 624         set it to just prec % limb_prec.
 625
 626 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 627
 628         PR target/113393
 629         * config/riscv/vector.md: Fix ternary attributes.
 630
 631 2024-01-14  Georg-Johann Lay  <avr@gjlay.de>
 632
 633         PR target/112944
 634         * configure.ac [target=avr]: Check availability of emulations
 635         avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
 636         HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
 637         * configure: Regenerate.
 638         * config.in: Regenerate.
 639         * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
 640         __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
 641         * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
 642         * config/avr/avr-arch.h (enum avr_device_specific_features):
 643         Add AVR_ISA_FLMAP.
 644         * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
 645         AVR_ISA_FLMAP.
 646         * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
 647         (avr_set_core_architecture): Set avr_arch_index.
 648         (have_avrxmega2_flmap, have_avrxmega4_flmap)
 649         (have_avrxmega3_rodata_in_flash): Set new static const bool according
 650         to configure results.
 651         (avr_rodata_in_flash_p): New function using them.
 652         (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
 653         track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
 654         (avr_asm_named_section): Track avr_has_rodata_p.
 655         (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
 656         and not avr_rodata_in_flash_p ().
 657         * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
 658         (LINK_SPEC): Add %(link_rodata_in_ram).
 659         (LINK_ARCH_SPEC): Remove.
 660         * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
 661         (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
 662         const bool according to configure results.
 663         (diagnose_mrodata_in_ram): New function.
 664         (print_mcu): Generate specs with the following changes:
 665         <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
 666         need to extend avr/specs.h each time we add a new bell or whistle.
 667         <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
 668         -m[no-]rodata-in-ram.
 669         <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
 670         <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
 671         <*cpp>: Add %(cpp_rodata_in_ram).
 672         <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
 673         requested.
 674         <*self_spec>: Add -mflmap or %<mflmap as needed.
 675
 676 2024-01-14  Jeff Law  <jlaw@ventanamicro.com>
 677
 678         * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
 679         not the GPR iterator.  Adjust pattern name and mode attribute
 680         accordingly.
 681
 682 2024-01-13  Jakub Jelinek  <jakub@redhat.com>
 683
 684         PR tree-optimization/113361
 685         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
 686         Fix up determination of the type for > limb_prec constants.
 687
 688 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
 689
 690         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
 691         Add web-link to the avr-gcc wiki.
 692
 693 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
 694
 695         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
 696         documentation for a version without argument, which is not supported.
 697
 698 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 699
 700         * config/arm/arm_neon.h
 701         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
 702         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
 703         (vld1_f16_x4, vld1_f32_x4): New.
 704         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
 705         (vld1_bf16_x4): New.
 706         (vld1q_types_x4): Updated to use vld1q_x4
 707         from arm_neon_builtins.def
 708         * config/arm/arm_neon_builtins.def
 709         (vld1_x4): Updated entries.
 710         (vld1q_x4): New entries, but comes from the old vld1_x4
 711         * config/arm/neon.md
 712         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
 713
 714 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 715
 716         * config/arm/arm_neon.h
 717         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
 718         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
 719         (vld1_f16_x3, vld1_f32_x3): New.
 720         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
 721         (vld1_bf16_x3): New.
 722         (vld1q_types_x3): Updated to use vld1q_x3 from
 723         arm_neon_builtins.def
 724         * config/arm/arm_neon_builtins.def
 725         (vld1_x3): Updated entries.
 726         (vld1q_x3): New entries, but comes from the old vld1_x2
 727         * config/arm/neon.md
 728         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
 729
 730 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 731
 732         * config/arm/arm_neon.h
 733         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
 734         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
 735         (vld1_f16_x2, vld1_f32_x2): New.
 736         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
 737         (vld1_bf16_x2): New.
 738         (vld1q_types_x2): Updated to use vld1q_x2 from
 739         arm_neon_builtins.def
 740         * config/arm/arm_neon_builtins.def
 741         (vld1_x2): Updated entries.
 742         (vld1q_x2): New entries, but comes from the old vld1_x2
 743         * config/arm/neon.md
 744         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
 745         neon_vld1_x2<mode>.
 746
 747 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 748
 749         * config/arm/arm_neon.h
 750         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
 751         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
 752         (vst1q_f16_x4, vst1q_f32_x4): New.
 753         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
 754         (vst1q_bf16_x4): New.
 755         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
 756         * config/arm/neon.md
 757         (neon_vst1q_x4<mode>): New.
 758         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
 759         * config/arm/unspecs.md
 760         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
 761
 762 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 763
 764         * config/arm/arm_neon.h
 765         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
 766         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
 767         (vst1q_f16_x3, vst1q_f32_x3): New.
 768         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
 769         (vst1q_bf16_x3): New.
 770         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
 771         * config/arm/neon.md
 772         (neon_vst1q_x3<mode>): New.
 773         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
 774         * config/arm/unspecs.md
 775         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
 776
 777 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 778
 779         * config/arm/arm_neon.h
 780         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
 781         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
 782         (vst1q_f16_x2, vst1q_f32_x2): New.
 783         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
 784         (vst1q_bf16_x2): New.
 785         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
 786         * config/arm/neon.md
 787         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
 788         neon_vst1_x2<mode>.
 789         * config/arm/iterators.md
 790         (VMEMX2): New mode iterator.
 791         (VMEMX2_q): New mode attribute.
 792
 793 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 794
 795         * config/arm/arm_neon.h
 796         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
 797         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
 798         (vst1_f16_x4, vst1_f32_x4): New.
 799         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
 800         (vst1_bf16_x4): New.
 801         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
 802         * config/arm/neon.md (vst1_x4<mode>): New.
 803
 804 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 805
 806         * config/arm/arm_neon.h
 807         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
 808         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
 809         (vst1_f16_x3, vst1_f32_x3): New.
 810         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
 811         (vst1_bf16_x3): New.
 812         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
 813         * config/arm/neon.md (vst1_x3<mode>): New.
 814
 815 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 816
 817         * config/arm/arm_neon.h
 818         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
 819         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
 820         (vst1_f16_x2, vst1_f32_x2): New.
 821         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
 822         (vst1_bf16_x2): New.
 823         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
 824         * config/arm/neon.md (vst1_x2<mode>): New.
 825
 826 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 827
 828         * config/arm/arm_neon.h
 829         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
 830         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
 831         (vld1q_f16_x4, vld1q_f32_x4): New.
 832         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
 833         (vld1q_bf16_x4): New.
 834         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
 835         * config/arm/neon.md
 836         (neon_vld1_x4<mode>): New.
 837         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
 838         * config/arm/unspecs.md
 839         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
 840
 841 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 842
 843         * config/arm/arm_neon.h
 844         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
 845         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
 846         (vld1q_f16_x3, vld1q_f32_x3): New.
 847         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
 848         (vld1q_bf16_x3): New.
 849         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
 850         * config/arm/neon.md
 851         (neon_vld1_x3<mode>): New.
 852         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
 853         * config/arm/unspecs.md
 854         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
 855
 856 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
 857
 858         * config/arm/arm_neon.h
 859         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
 860         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
 861         (vld1q_f16_x2, vld1q_f32_x2): New.
 862         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
 863         (vld1q_bf16_x2): New.
 864         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
 865         * config/arm/neon.md (vld1_x2<mode>): New.
 866
 867 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 868
 869         PR tree-optimization/113287
 870         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
 871
 872 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 873
 874         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
 875         * tree-vect-loop.cc (vect_transform_loop): Likewise.
 876
 877 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 878
 879         PR tree-optimization/113178
 880         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
 881         alternate exits.
 882
 883 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 884
 885         PR tree-optimization/113237
 886         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
 887         existing LCSSA variable for exit when all exits are early break.
 888
 889 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 890
 891         PR tree-optimization/113137
 892         PR tree-optimization/113136
 893         PR tree-optimization/113172
 894         PR tree-optimization/113178
 895         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
 896         Maintain PHIs on inverted loops.
 897         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
 898         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
 899         latch.
 900         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
 901
 902 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
 903
 904         PR tree-optimization/113135
 905         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
 906         dependency analysis.
 907
 908 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
 909
 910         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
 911         diagnostics class member name for abort of error.
 912
 913 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
 914
 915         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
 916         format string to %s argument.
 917
 918 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
 919             Jakub Jelinek  <jakub@redhat.com>
 920
 921         PR middle-end/113182
 922         * varasm.cc (process_pending_assemble_externals,
 923         assemble_external_libcall): Use targetm.strip_name_encoding
 924         before calling get_identifier.
 925
 926 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 927
 928         PR target/113196
 929         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
 930         New member variable.
 931         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
 932         Declare.
 933         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
 934         * config/aarch64/aarch64-simd.md
 935         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
 936         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
 937         zip2 for zero-extends to...
 938         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
 939         instruction.  Fix big-endian handling.
 940         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
 941         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
 942         zip1 for zero-extends to...
 943         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
 944         Fix big-endian handling.
 945         (*aarch64_zip1_uxtl): New pattern.
 946         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
 947         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
 948         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
 949         (aarch64_gen_shareable_zero): Use it.
 950         (aarch64_split_simd_shift_p): New function.
 951
 952 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 953
 954         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
 955         (function_beg_insn): New macro.
 956         * function.cc (expand_function_start): Initialize function_beg_insn.
 957
 958 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 959
 960         PR target/112989
 961         * config/aarch64/aarch64-sve-builtins.h
 962         (function_builder::m_overload_names): Replace with...
 963         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
 964         new global.
 965         (add_overloaded_function): Update accordingly, using get_identifier
 966         to get a GGC-friendly record of the name.
 967
 968 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
 969
 970         PR target/112989
 971         * config/aarch64/aarch64-sve-builtins.def: Don't include
 972         aarch64-sve-builtins-sme.def.
 973         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
 974         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
 975         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
 976         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
 977         requires AARCH64_FL_SME2.
 978         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
 979         AARCH64_FL_SME adjustment here.
 980         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
 981         include SME intrinsics.
 982         (sme_function_groups): New array.
 983         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
 984         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
 985
 986 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 987
 988         PR target/113281
 989         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
 990         (struct cpu_vector_cost): Add regmove struct.
 991         (get_vector_costs): Export as global.
 992         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
 993         (costs::add_stmt_cost): Ditto.
 994         * config/riscv/riscv.cc (get_common_costs): Export global function.
 995
 996 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
 997
 998         PR tree-optimization/113334
 999         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
1000         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
1001         to determine if number should be extended by all ones rather than zero
1002         extended.
1003
1004 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1005
1006         PR tree-optimization/113330
1007         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
1008         too large size.
1009
1010 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1011
1012         PR tree-optimization/113323
1013         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
1014         check for lhs being large/huge _BitInt not in m_names.
1015
1016 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1017
1018         PR tree-optimization/113316
1019         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
1020         uninitialized large/huge _BitInt arguments to calls.
1021
1022 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
1023
1024         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
1025         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
1026         CEIL (TYPE_PRECISION (t), limb_prec).
1027         (bitint_large_huge::handle_cast): Likewise.
1028
1029 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
1030
1031         PR sanitizer/113284
1032         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
1033         Use assemble_function_label_final () for Power ELF V1 ABI.
1034         * output.h (assemble_function_label_final): New function.
1035         * varasm.cc (assemble_function_label_raw): Use
1036         assemble_function_label_final ().
1037         (assemble_function_label_final): New function.
1038
1039 2024-01-12  Richard Biener  <rguenther@suse.de>
1040
1041         PR middle-end/113344
1042         * match.pd ((double)float CMP (double)float -> float CMP float):
1043         Perform result type check only for vectors.
1044         * fold-const.cc (fold_binary_loc): Likewise.
1045
1046 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
1047
1048         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
1049         (usdot_prod<mode>): Ditto.
1050         (sdot_prod<mode>): Ditto.
1051         (udot_prod<mode>): Ditto.
1052
1053 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
1054
1055         PR target/113288
1056         * config/i386/i386-c.cc (ix86_target_macros_internal):
1057         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
1058
1059 2024-01-12  Richard Biener  <rguenther@suse.de>
1060
1061         PR target/112280
1062         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
1063         Do not generate code when d.testing_p.
1064
1065 2024-01-12  liuhongt  <hongtao.liu@intel.com>
1066
1067         PR target/113039
1068         * doc/invoke.texi (fcf-protection=): Update documents.
1069
1070 2024-01-12  Pan Li  <pan2.li@intel.com>
1071
1072         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
1073         comments of predicate func riscv_v_ext_mode_p.
1074
1075 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
1076
1077         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
1078                         Modify ABI-name length of vfloat16m8_t
1079
1080 2024-01-12  Li Wei  <liwei@loongson.cn>
1081
1082         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
1083         Adjust.
1084
1085 2024-01-12  Li Wei  <liwei@loongson.cn>
1086
1087         * config/loongarch/loongarch.md (add<mode>3): Removed.
1088         (*addsi3): New.
1089         (addsi3): Ditto.
1090         (adddi3): Ditto.
1091         (*addsi3_extended): Removed.
1092         (addsi3_extended): New.
1093
1094 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
1095
1096         * config/riscv/thead.md: Add limits for splits.
1097
1098 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
1099
1100         PR middle-end/113322
1101         * expr.cc (do_store_flag): Don't try single bit tests with
1102         comparison on vector types.
1103
1104 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
1105
1106         PR tree-optimization/113301
1107         * match.pd (`1/x`): Delay signed case until late.
1108
1109 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
1110
1111         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
1112         and -msp8 to...
1113         (AVR Internal Options): ...this new @subsubsection.
1114
1115 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
1116
1117         PR rtl-optimization/112918
1118         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
1119         (in_class_p): Restrict condition for narrowing class in case of
1120         allow_all_reload_class_changes_p.
1121         (process_alt_operands): Try to match operand without and with
1122         narrowing reg class.  Discourage narrowing the class.  Finish insn
1123         matching only if there is no class narrowing.
1124         (curr_insn_transform): Pass true to in_class_p for reg operand win.
1125
1126 2024-01-11  Richard Biener  <rguenther@suse.de>
1127
1128         PR tree-optimization/112505
1129         * tree-vect-loop.cc (vectorizable_induction): Reject
1130         bit-precision induction.
1131
1132 2024-01-11  Richard Biener  <rguenther@suse.de>
1133
1134         PR tree-optimization/113126
1135         * match.pd ((double)float CMP (double)float -> float CMP float):
1136         Make sure the boolean type is the same.
1137         * fold-const.cc (fold_binary_loc): Likewise.
1138
1139 2024-01-11  Richard Biener  <rguenther@suse.de>
1140
1141         PR tree-optimization/112636
1142         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
1143         estimate_numbers_of_iterations before querying
1144         get_max_loop_iterations_int.
1145         (pass_ch::execute): Initialize SCEV and loops appropriately.
1146
1147 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
1148
1149         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
1150         Reduced Tiny.
1151         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
1152         * doc/extend.texi (AVR Variable Attributes): Improve documentation
1153         of io, io_low and address attributes.
1154         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
1155         * doc/avr-mmcu.texi: Rebuild.
1156
1157 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
1158
1159         PR target/113233
1160         * config/loongarch/genopts/loongarch.opt.in: Mark options with
1161         the "Save" property.
1162         * config/loongarch/loongarch.opt: Same.
1163         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
1164         according to la_target.
1165         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
1166         RESTORE} for the la_target structure; Rename option conditions
1167         to have the same "la_" prefix.
1168         * config/loongarch/loongarch.h: Same.
1169
1170 2024-01-11  Pan Li  <pan2.li@intel.com>
1171
1172         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
1173         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
1174
1175 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
1176
1177         PR target/113077
1178         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
1179         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
1180         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
1181         synthesize these if needed.  Update caller ...
1182         (ldp_bb_info::fuse_pair): ... here.
1183         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
1184         and either insn is frame-related.
1185         (find_trailing_add): Punt on frame-related insns.
1186         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
1187         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
1188
1189 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
1190
1191         * config/mips/mips.cc (mips_start_function_definition):
1192         Add ATTRIBUTE_UNUSED.
1193
1194 2024-01-11  Richard Biener  <rguenther@suse.de>
1195
1196         PR middle-end/112740
1197         * expr.cc (store_constructor): Check the integer vector
1198         mask has a single bit per element before using sign-extension
1199         to expand an uniform vector.
1200
1201 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1202
1203         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
1204         preempt VLS on unknown NITERS loop.
1205
1206 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
1207
1208         * doc/invoke.texi: Add -mevex512.
1209
1210 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
1211
1212         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
1213         (*nor<mode>3): Likewise.
1214         (nor<mode>3): Likewise.
1215         (*negsi2_extended): New template.
1216         (*<optab>si3_internal): Likewise.
1217         (*one_cmplsi2_internal): Likewise.
1218         (*norsi3_internal): Likewise.
1219         (*<optab>nsi_internal): Likewise.
1220         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
1221         modified bit operation to make the optimization work.
1222
1223 2024-01-11  liuhongt  <hongtao.liu@intel.com>
1224
1225         PR target/104401
1226         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
1227
1228 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1229
1230         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
1231         (get_vector_costs): Ditto.
1232         (riscv_builtin_vectorization_cost): Ditto.
1233
1234 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1235
1236         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
1237
1238 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
1239
1240         PR jit/111396
1241         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
1242         ipa_free_size_summary.
1243         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
1244         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
1245         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
1246         * ipa-prop.h (ipa_prop_cc_finalize): New function.
1247         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
1248         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
1249         ipa_sra_cc_finalize): New functions.
1250         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
1251         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
1252         ipa_sra_cc_finalize
1253         Include ipa-utils.h.
1254
1255 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
1256
1257         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
1258         (th_int_get_save_adjustment): Likewise.
1259         (th_int_adjust_cfi_prologue): Likewise.
1260         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
1261         (TH_INT_INTERRUPT): New macro.
1262         (riscv_expand_prologue): Add the processing of XTheadInt.
1263         (riscv_expand_epilogue): Likewise.
1264         * config/riscv/riscv.h (BITSET_P): Moved to here.
1265         * config/riscv/riscv.md: New unspec.
1266         * config/riscv/thead.cc (th_int_get_mask): New function.
1267         (th_int_get_save_adjustment): Likewise.
1268         (th_int_adjust_cfi_prologue): Likewise.
1269         * config/riscv/thead.md (th_int_push): New pattern.
1270         (th_int_pop): new pattern.
1271
1272 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
1273
1274         PR tree-optimization/112468
1275         * doc/sourcebuild.texi: Document ifn_copysign.
1276         * match.pd: Only apply transformation if target supports the IFN.
1277
1278 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
1279
1280         PR tree-optimization/112581
1281         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
1282         mark_ssa_maybe_undefs.
1283         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
1284         variables can not be reassociated.
1285         (init_range_entry): Check for uninitialized variables too.
1286         (init_reassoc): Call mark_ssa_maybe_undefs.
1287
1288 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
1289
1290         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
1291         Also handle sign extension.
1292
1293 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
1294
1295         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
1296         to 0.
1297         (-mlate-ldp-fusion): Likewise.
1298
1299 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
1300
1301         PR tree-optimization/113287
1302         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
1303         instead of using BRANCH_EDGE to determine true edge.
1304
1305 2024-01-10  Richard Biener  <rguenther@suse.de>
1306
1307         PR tree-optimization/113078
1308         * tree-vect-loop.cc (check_reduction_path): Canonicalize
1309         .COND_SUB to .COND_ADD.
1310
1311 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
1312
1313         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
1314         Handle prefix mappings before calling find_opt.
1315         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
1316         "-fno-"-prefixed command-line option.
1317         * opts-common.cc (get_option_prefix_remapping): New.
1318         * opts.h (get_option_prefix_remapping): New decl.
1319
1320 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
1321
1322         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
1323         m_urlifier to pp_output_formatted_text.
1324         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
1325         (obstack_append_string): New overload, taking a length.
1326         (urlify_quoted_string): Pass in an obstack ptr, rather than using
1327         that of the pp's buffer.  Generalize to handle trailing text in
1328         the buffer beyond the run of quoted text.
1329         (class quoting_info): New.
1330         (on_begin_quote): New.
1331         (on_end_quote): New.
1332         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
1333         it to calls to on_begin_quote and on_end_quote.
1334         (struct auto_obstack): New.
1335         (quoting_info::handle_phase_3): New.
1336         (pp_output_formatted_text): Add urlifier param.  Use it if there
1337         is deferred urlification.  Delete m_quotes.
1338         (selftest::pp_printf_with_urlifier): Pass urlifier to
1339         pp_output_formatted_text.
1340         (selftest::test_urlification): Update results for the existing
1341         case of quoted text stradding chunks; add more such test cases.
1342         * pretty-print.h (class quoting_info): New forward decl.
1343         (chunk_info::m_quotes): New field.
1344         (pp_output_formatted_text): Add optional urlifier param.
1345
1346 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
1347
1348         * pretty-print.cc (selftest::test_pp_format): Add selftest
1349         coverage for numbered args.
1350
1351 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
1352
1353         PR tree-optimization/113144
1354         PR tree-optimization/113145
1355         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1356         Update all BB that the original exits dominated.
1357
1358 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
1359
1360         * dwarf2out.cc (modified_type_die): Extend the support of reverse
1361         storage order to enumeration types if -gstrict-dwarf is not passed.
1362         (gen_enumeration_type_die): Add REVERSE parameter and generate the
1363         DIE immediately after the existing one if it is true.
1364         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
1365         call to gen_enumeration_type_die.
1366         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
1367         first recursive call as well as the call to gen_tagged_type_die.
1368         (gen_type_die): Add REVERSE parameter and pass it in the call to
1369         gen_type_die_with_usage.
1370
1371 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
1372
1373         PR tree-optimization/113120
1374         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
1375         with root->size TYPE_PRECISION don't build anything new.
1376         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
1377         rather than build_nonstandard_integer_type.
1378
1379 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
1380
1381         * config/i386/i386.opt: Adjust document.
1382         * doc/invoke.texi: Add description for
1383         -mapx-inline-asm-use-gpr32.
1384
1385 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1386
1387         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
1388         (avg<v_double_trunc>3_floor): New pattern.
1389         (<u>avg<v_double_trunc>3_ceil): Remove.
1390         (avg<v_double_trunc>3_ceil): New pattern.
1391         (uavg<mode>3_floor): Ditto.
1392         (uavg<mode>3_ceil): Ditto.
1393         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
1394         (enum insn_type): Ditto.
1395         * config/riscv/riscv-v.cc: Ditto.
1396         * config/riscv/vector-iterators.md (ashiftrt): Remove.
1397         (ASHIFTRT): Ditto.
1398         * config/riscv/vector.md: Add VLS modes.
1399
1400 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
1401
1402         PR target/111480
1403         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
1404         (vczlsbb_char): New int attribute.
1405         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
1406         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
1407         (*vctzlsbb_zext_<mode>): Rename to ...
1408         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
1409         cover vclzlsbb.
1410
1411 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
1412
1413         PR target/112606
1414         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
1415         of the last argument from altivec_register_operand to any_operand.  If
1416         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
1417         otherwise if it doesn't satisfy altivec_register_operand, force it to
1418         REG using copy_to_mode_reg.
1419
1420 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
1421
1422         PR middle-end/113100
1423         * builtins.cc (expand_builtin_stack_address): Guard stack point
1424         adjustment with SPARC_STACK_BOUNDARY_HACK.
1425
1426 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1427
1428         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
1429         argument string definitions.
1430         * config/loongarch/loongarch-str.h: Same.
1431         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
1432         as aliases to -mexplicit-relocs={always,none}
1433         * config/loongarch/loongarch.opt: Regenerate.
1434         * config/loongarch/loongarch.cc: Same.
1435
1436 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1437
1438         * config/loongarch/loongarch-def.h: Define constants with
1439         enums instead of Macros.
1440
1441 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1442
1443         * config/loongarch/genopts/loongarch-strings: Rename.
1444         * config/loongarch/genopts/loongarch.opt.in: Same.
1445         * config/loongarch/loongarch-cpu.cc: Same.
1446         * config/loongarch/loongarch-def.cc: Same.
1447         * config/loongarch/loongarch-def.h: Same.
1448         * config/loongarch/loongarch-opts.cc: Same.
1449         * config/loongarch/loongarch-opts.h: Same.
1450         * config/loongarch/loongarch-str.h: Same.
1451         * config/loongarch/loongarch.opt: Same.
1452
1453 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
1454
1455         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
1456         variable with the common la_ prefix.
1457         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
1458         flags as saved using TargetVariable.
1459         * config/loongarch/loongarch.opt: Same.
1460         * config/loongarch/loongarch-def.h: Define evolution_set to
1461         mark changes to the -march default.
1462         * config/loongarch/loongarch-driver.cc: Same.
1463         * config/loongarch/loongarch-opts.cc: Same.
1464         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
1465         conditions around the la_target structure.
1466         * config/loongarch/loongarch.cc: Same.
1467         * config/loongarch/loongarch.md: Same.
1468         * config/loongarch/loongarch-builtins.cc: Same.
1469         * config/loongarch/loongarch-c.cc: Same.
1470         * config/loongarch/lasx.md: Same.
1471         * config/loongarch/lsx.md: Same.
1472         * config/loongarch/sync.md: Same.
1473
1474 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
1475
1476         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
1477         no less.
1478
1479 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
1480
1481         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
1482
1483 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
1484
1485         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
1486         restart_loop.
1487         (vectorizable_live_operation): Likewise.
1488
1489 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
1490
1491         PR tree-optimization/113199
1492         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
1493         BIT_FIELD_REF.
1494
1495 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
1496
1497         PR target/113270
1498         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
1499         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
1500         GTY(()) declaration before the definition, drop GTY(()) drom the
1501         definition.
1502
1503 2024-01-09  Richard Biener  <rguenther@suse.de>
1504
1505         PR tree-optimization/113026
1506         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
1507         redundant and wrong niter bound setting.  Move niter
1508         bound adjustment down.
1509
1510 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
1511
1512         PR middle-end/113163
1513         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
1514         Reject non-linear inductions that aren't supported.
1515
1516 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
1517
1518         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
1519         left shift implementation strategies.
1520         (arc_shift_info): Type for each entry of the shift strategy table.
1521         (arc_shift_context_idx): Return a integer value for each code
1522         generation context, used as an index
1523         (arc_ashl_alg): Table indexed by context and shifted bit count.
1524         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
1525         left shift implementation.
1526         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
1527         provide accurate costs, when optimizing for speed or size.
1528
1529 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1530
1531         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
1532
1533 2024-01-09  Julian Brown  <julian@codesourcery.com>
1534
1535         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
1536         processed out before gimplification.
1537         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
1538         * tree.def (OMP_ARRAY_SECTION): New tree code.
1539
1540 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
1541
1542         PR tree-optimization/113210
1543         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
1544         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
1545         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
1546         minus 1.
1547
1548 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
1549
1550         PR rtl-optimization/113140
1551         * reorg.cc (fill_slots_from_thread): If we are to branch after the
1552         last instruction of the function, create an end label.
1553
1554 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
1555             Hongtao Liu  <hongtao.liu@intel.com>
1556
1557         PR target/112992
1558         * config/i386/i386-expand.cc
1559         (ix86_convert_const_wide_int_to_broadcast): Allow call to
1560         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
1561         (ix86_broadcast_from_constant): Revert recent change; Return a
1562         suitable MEMREF independently of mode/target combinations.
1563         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
1564         to decide whether expansion is possible/preferrable.  Only try
1565         forcing DImode constants to memory (and trying again) if calling
1566         ix86_expand_vector_init_duplicate fails with an DImode immediate
1567         constant.
1568         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
1569         V4SImode for suitable immediate constants.
1570         <case E_V4DImode>: Try using V8SImode for suitable constants.
1571         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
1572         <case E_V2HImode>: Likewise.
1573         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
1574         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
1575         <label widen>: Handle CONT_INTs via simplify_binary_operation.
1576         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
1577         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
1578         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
1579         (ix86_expand_vector_init): Move try using a broadcast for all_same
1580         with ix86_expand_vector_init_duplicate before using constant pool.
1581
1582 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
1583
1584         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
1585
1586 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
1587
1588         * config/arm/arm-cpus.in (cortex-m52): New cpu.
1589         * config/arm/arm-tables.opt: Regenerate.
1590         * config/arm/arm-tune.md: Regenerate.
1591
1592 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
1593
1594         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
1595         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
1596         (@vec_concatz<mode>): New insn pattern.
1597         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
1598         Handle VALS containing two vectors.
1599
1600 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1601
1602         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
1603         (vundefined): Ditto.
1604
1605 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
1606
1607         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
1608                                 Add new function_base for crypto vector.
1609         (class bitmanip): Ditto.
1610         (class b_reverse):Ditto.
1611         (class vwsll):   Ditto.
1612         (class clmul):   Ditto.
1613         (class vg_nhab):  Ditto.
1614         (class crypto_vv):Ditto.
1615         (class crypto_vi):Ditto.
1616         (class vaeskf2_vsm3c):Ditto.
1617         (class vsm3me): Ditto.
1618         (BASE): Add BASE declaration for crypto vector.
1619         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
1620         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
1621                                 Add crypto vector intrinsic definition.
1622         (vbrev): Ditto.
1623         (vclz): Ditto.
1624         (vctz): Ditto.
1625         (vwsll): Ditto.
1626         (vandn): Ditto.
1627         (vbrev8): Ditto.
1628         (vrev8): Ditto.
1629         (vrol): Ditto.
1630         (vror): Ditto.
1631         (vclmul): Ditto.
1632         (vclmulh): Ditto.
1633         (vghsh): Ditto.
1634         (vgmul): Ditto.
1635         (vaesef): Ditto.
1636         (vaesem): Ditto.
1637         (vaesdf): Ditto.
1638         (vaesdm): Ditto.
1639         (vaesz): Ditto.
1640         (vaeskf1): Ditto.
1641         (vaeskf2): Ditto.
1642         (vsha2ms): Ditto.
1643         (vsha2ch): Ditto.
1644         (vsha2cl): Ditto.
1645         (vsm4k): Ditto.
1646         (vsm4r): Ditto.
1647         (vsm3me): Ditto.
1648         (vsm3c): Ditto.
1649         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
1650                                 Add new function_shape for crypto vector.
1651         (struct crypto_vi_def): Ditto.
1652         (struct crypto_vv_no_op_type_def): Ditto.
1653         (SHAPE): Add SHAPE declaration of crypto vector.
1654         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
1655         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
1656                                 Add new data type for crypto vector.
1657         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1658         (vuint32mf2_t): Ditto.
1659         (vuint32m1_t): Ditto.
1660         (vuint32m2_t): Ditto.
1661         (vuint32m4_t): Ditto.
1662         (vuint32m8_t): Ditto.
1663         (vuint64m1_t): Ditto.
1664         (vuint64m2_t): Ditto.
1665         (vuint64m4_t): Ditto.
1666         (vuint64m8_t): Ditto.
1667         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
1668                                 Add new data struct for crypto vector.
1669         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1670         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
1671         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
1672
1673 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
1674
1675         PR sanitizer/113251
1676         * varasm.cc (assemble_function_label_raw): Do not call
1677         asan_function_start () without the current function.
1678
1679 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
1680
1681         PR target/113225
1682         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
1683         extern and kernel_helper attributed function decls.
1684
1685 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
1686
1687         * btfout.cc (output_btf_strs): Changed.
1688
1689 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1690
1691         * config/gcn/mkoffload.cc (main): Handle gfx1100
1692         when setting the default XNACK.
1693
1694 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
1695
1696         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
1697         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
1698         (ASM_SPEC): Handle gfx1100.
1699         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
1700         (enum gcn_isa): Add ISA_RDNA3.
1701         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
1702         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1703         * config/gcn/gcn.cc (gcn_option_override,
1704         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
1705         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
1706         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1707         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
1708         with gfx1100.
1709         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
1710         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
1711         __gfx1100__.
1712         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
1713         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
1714         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
1715         (isa_has_combined_avgprs, main): Handle gfx1100.
1716         * config/gcn/t-omp-device (isa): Add gfx1100.
1717
1718 2024-01-08  Richard Biener  <rguenther@suse.de>
1719
1720         * doc/invoke.texi (-mmovbe): Clarify.
1721
1722 2024-01-08  Richard Biener  <rguenther@suse.de>
1723
1724         PR tree-optimization/113026
1725         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
1726         Avoid an epilog in more cases.
1727         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
1728         epilogues niter upper bounds and estimates.
1729
1730 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1731
1732         PR tree-optimization/113228
1733         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
1734
1735 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1736
1737         PR tree-optimization/113120
1738         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
1739         large _BitInt zero INTEGER_CST PHI argument.
1740
1741 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
1742
1743         PR tree-optimization/113119
1744         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
1745         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
1746         is before REALPART_EXPR.
1747
1748 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
1749
1750         PR target/112952
1751         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
1752         range when diagnosing attribute "io" and "io_low" are out of range.
1753         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
1754         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
1755         in contexts other than static storage.
1756         (avr_asm_output_aligned_decl_common): Move output of decls with
1757         attribute "address", "io", and "io_low" to...
1758         (avr_output_addr_attrib): ...this new function.
1759         (avr_asm_asm_output_aligned_bss): Remove output for decls with
1760         attribute "address", "io", and "io_low".
1761         (avr_encode_section_info): Rectify handling of decls with attribute
1762         "address", "io", and "io_low".
1763
1764 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1765
1766         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
1767         (elf_flags): Remove XNACK from the default value.
1768         (main): Set a default XNACK according to the arch.
1769
1770 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
1771
1772         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
1773         (process_asm): Don't count avgprs.
1774
1775 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
1776
1777         * config/i386/i386.opt: Add supported sub-features.
1778         * doc/extend.texi: Add description for target attribute.
1779
1780 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
1781
1782         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
1783
1784 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
1785             Uros Bizjak  <ubizjak@gmail.com>
1786
1787         PR target/113231
1788         * config/i386/i386-features.cc (compute_convert_gain): Include
1789         the overhead of explicit load and store (movd) instructions when
1790         converting non-store scalar operations with memory destinations.
1791         Various indentation whitespace fixes.
1792
1793 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
1794
1795         * config/arm/neon.md (cbranch<mode>4): New.
1796
1797 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1798
1799         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
1800
1801 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
1802
1803         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
1804
1805 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1806
1807         PR target/113248
1808         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
1809         Update the MAX_SEW.
1810
1811 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1812
1813         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
1814         (variable_vectorized_p): Teach loop invariant.
1815         (has_unexpected_spills_p): Ditto.
1816
1817 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1818
1819         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
1820         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
1821         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
1822
1823 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
1824
1825         PR target/113104
1826         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
1827         (aarch64-vect-compare-costs): ...this.
1828         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
1829         Replace with...
1830         (-param=aarch64-vect-compare-costs=): ...this new param.
1831         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
1832         Don't disable it when vectorizing for Advanced SIMD only.
1833         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
1834         whenever aarch64_vect_compare_costs is true.
1835
1836 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
1837
1838         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
1839         Modify the method of determining the memory offset of [x]vld/[x]vst.
1840         (lasx_mxst_<lasxfmt_f>): Likewise.
1841         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
1842         (loongarch_address_insns): Likewise.
1843         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
1844         (lsx_st_<lsxfmt_f>): Likewise.
1845         * config/loongarch/predicates.md (aq10b_operand): Likewise.
1846         (aq10h_operand): Likewise.
1847         (aq10w_operand): Likewise.
1848         (aq10d_operand): Likewise.
1849
1850 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
1851
1852         PR target/113217
1853         * config/aarch64/aarch64-ldp-fusion.cc
1854         (ldp_bb_info::try_fuse_pair): If the second access can throw,
1855         narrow the move range to exactly that insn.
1856
1857 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
1858
1859         * asan.cc (asan_function_start): Drop switch_to_section ().
1860         (asan_emit_stack_protection): Set .LASANPC alignment.
1861         * config/i386/i386.cc: Use assemble_function_label_raw ()
1862         instead of ASM_OUTPUT_LABEL ().
1863         * config/s390/s390.cc (s390_asm_output_function_label):
1864         Likewise.
1865         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
1866         * final.cc (final_start_function_1): Drop
1867         asan_function_start ().
1868         * output.h (assemble_function_label_raw): New function.
1869         * varasm.cc (assemble_function_label_raw): Likewise.
1870
1871 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
1872
1873         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
1874         Use ASM_OUTPUT_FUNCTION_LABEL ().
1875         * config/alpha/alpha.cc (alpha_start_function): Likewise.
1876         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1877         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
1878         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1879         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1880         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
1881         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
1882         * config/ia64/ia64.cc (ia64_start_function): Likewise.
1883         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
1884         Likewise.
1885         * config/microblaze/microblaze.cc (microblaze_function_prologue):
1886         Likewise.
1887         * config/mips/mips.cc (mips_start_unique_function): Return the
1888         tree.
1889         (mips_start_function_definition): Use
1890         ASM_OUTPUT_FUNCTION_LABEL ().
1891         (mips_finish_stub): Pass the tree to
1892         mips_start_function_definition ().
1893         (mips16_build_function_stub): Likewise.
1894         (mips16_build_call_stub): Likewise.
1895         (mips_output_function_prologue): Likewise.
1896         * config/pa/pa.cc (pa_output_function_label): Use
1897         ASM_OUTPUT_FUNCTION_LABEL ().
1898         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
1899         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
1900         Likewise.
1901         (rs6000_xcoff_declare_function_name): Likewise.
1902
1903 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
1904
1905         PR tree-optimization/113201
1906         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
1907         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
1908
1909 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
1910
1911         PR tree-optimization/90693
1912         * tree-ssa-math-opts.cc (match_single_bit_test): If
1913         tree_expr_nonzero_p (arg), remember it in the second argument to
1914         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
1915         arg ^ (arg - 1) > arg - 1.
1916         * internal-fn.cc (expand_POPCOUNT): If second argument to
1917         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
1918         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
1919
1920 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
1921
1922         * config/riscv/riscv-v.cc (expand_load_store):
1923         Remove `value`.
1924         (expand_cond_len_op): Ditto.
1925         (expand_gather_scatter): Ditto.
1926         (expand_lanes_load_store): Ditto.
1927         (expand_fold_extract_last): Ditto.
1928
1929 2024-01-05  Pan Li  <pan2.li@intel.com>
1930
1931         Revert:
1932         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
1933
1934         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
1935                                 Add new function_base for crypto vector.
1936         (class bitmanip): Ditto.
1937         (class b_reverse):Ditto.
1938         (class vwsll):   Ditto.
1939         (class clmul):   Ditto.
1940         (class vg_nhab):  Ditto.
1941         (class crypto_vv):Ditto.
1942         (class crypto_vi):Ditto.
1943         (class vaeskf2_vsm3c):Ditto.
1944         (class vsm3me): Ditto.
1945         (BASE): Add BASE declaration for crypto vector.
1946         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
1947         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
1948                                 Add crypto vector intrinsic definition.
1949         (vbrev): Ditto.
1950         (vclz): Ditto.
1951         (vctz): Ditto.
1952         (vwsll): Ditto.
1953         (vandn): Ditto.
1954         (vbrev8): Ditto.
1955         (vrev8): Ditto.
1956         (vrol): Ditto.
1957         (vror): Ditto.
1958         (vclmul): Ditto.
1959         (vclmulh): Ditto.
1960         (vghsh): Ditto.
1961         (vgmul): Ditto.
1962         (vaesef): Ditto.
1963         (vaesem): Ditto.
1964         (vaesdf): Ditto.
1965         (vaesdm): Ditto.
1966         (vaesz): Ditto.
1967         (vaeskf1): Ditto.
1968         (vaeskf2): Ditto.
1969         (vsha2ms): Ditto.
1970         (vsha2ch): Ditto.
1971         (vsha2cl): Ditto.
1972         (vsm4k): Ditto.
1973         (vsm4r): Ditto.
1974         (vsm3me): Ditto.
1975         (vsm3c): Ditto.
1976         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
1977                                 Add new function_shape for crypto vector.
1978         (struct crypto_vi_def): Ditto.
1979         (struct crypto_vv_no_op_type_def): Ditto.
1980         (SHAPE): Add SHAPE declaration of crypto vector.
1981         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
1982         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
1983                                 Add new data type for crypto vector.
1984         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1985         (vuint32mf2_t): Ditto.
1986         (vuint32m1_t): Ditto.
1987         (vuint32m2_t): Ditto.
1988         (vuint32m4_t): Ditto.
1989         (vuint32m8_t): Ditto.
1990         (vuint64m1_t): Ditto.
1991         (vuint64m2_t): Ditto.
1992         (vuint64m4_t): Ditto.
1993         (vuint64m8_t): Ditto.
1994         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
1995                                 Add new data struct for crypto vector.
1996         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
1997         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
1998         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
1999
2000 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
2001
2002         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
2003                                 Add new function_base for crypto vector.
2004         (class bitmanip): Ditto.
2005         (class b_reverse):Ditto.
2006         (class vwsll):   Ditto.
2007         (class clmul):   Ditto.
2008         (class vg_nhab):  Ditto.
2009         (class crypto_vv):Ditto.
2010         (class crypto_vi):Ditto.
2011         (class vaeskf2_vsm3c):Ditto.
2012         (class vsm3me): Ditto.
2013         (BASE): Add BASE declaration for crypto vector.
2014         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
2015         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
2016                                 Add crypto vector intrinsic definition.
2017         (vbrev): Ditto.
2018         (vclz): Ditto.
2019         (vctz): Ditto.
2020         (vwsll): Ditto.
2021         (vandn): Ditto.
2022         (vbrev8): Ditto.
2023         (vrev8): Ditto.
2024         (vrol): Ditto.
2025         (vror): Ditto.
2026         (vclmul): Ditto.
2027         (vclmulh): Ditto.
2028         (vghsh): Ditto.
2029         (vgmul): Ditto.
2030         (vaesef): Ditto.
2031         (vaesem): Ditto.
2032         (vaesdf): Ditto.
2033         (vaesdm): Ditto.
2034         (vaesz): Ditto.
2035         (vaeskf1): Ditto.
2036         (vaeskf2): Ditto.
2037         (vsha2ms): Ditto.
2038         (vsha2ch): Ditto.
2039         (vsha2cl): Ditto.
2040         (vsm4k): Ditto.
2041         (vsm4r): Ditto.
2042         (vsm3me): Ditto.
2043         (vsm3c): Ditto.
2044         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
2045                                 Add new function_shape for crypto vector.
2046         (struct crypto_vi_def): Ditto.
2047         (struct crypto_vv_no_op_type_def): Ditto.
2048         (SHAPE): Add SHAPE declaration of crypto vector.
2049         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
2050         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
2051                                 Add new data type for crypto vector.
2052         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2053         (vuint32mf2_t): Ditto.
2054         (vuint32m1_t): Ditto.
2055         (vuint32m2_t): Ditto.
2056         (vuint32m4_t): Ditto.
2057         (vuint32m8_t): Ditto.
2058         (vuint64m1_t): Ditto.
2059         (vuint64m2_t): Ditto.
2060         (vuint64m4_t): Ditto.
2061         (vuint64m8_t): Ditto.
2062         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
2063                                 Add new data struct for crypto vector.
2064         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
2065         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
2066         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
2067
2068 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2069
2070         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2071
2072 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
2073
2074         PR tree-optimization/113186
2075         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
2076         Match `^` with the `==` for 1bit integral types.
2077         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
2078         integral types.
2079
2080 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2081
2082         * toplev.cc (general_init): Pass lang_mask to urlifier.
2083
2084 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2085
2086         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
2087         param.
2088         (diagnostic_context::make_option_url): Update for lang_mask param.
2089         * gcc-urlifier.cc: Include "opts.h" and "options.h".
2090         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
2091         (gcc_urlifier::m_lang_mask): New field.
2092         (doc_urls): Make static.
2093         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
2094         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
2095         Look for an option by name before trying a binary search in
2096         doc_urls.
2097         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
2098         (gcc_urlifier::get_url_suffix_for_option): New.
2099         (make_gcc_urlifier): Add lang_mask param.
2100         (selftest::gcc_urlifier_cc_tests): Update for above changes.
2101         Verify that a URL is found for "-fpack-struct".
2102         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
2103         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
2104         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
2105         to make_gcc_urlifier.
2106         * opts-diagnostic.h (get_option_url): Add lang_mask param.
2107         * opts.cc (get_option_html_page): Remove special-casing for
2108         analyzer and LTO.
2109         (get_option_url_suffix): New.
2110         (get_option_url): Reimplement.
2111         (selftest::test_get_option_html_page): Rename to...
2112         (selftest::test_get_option_url_suffix): ...this and update for
2113         above changes.
2114         (selftest::opts_cc_tests): Update for renaming.
2115         * opts.h: Include "rich-location.h".
2116         (get_option_url_suffix): New decl.
2117
2118 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2119
2120         * Makefile.in (ALL_OPT_URL_FILES): New.
2121         (GCC_OBJS): Add options-urls.o.
2122         (OBJS): Likewise.
2123         (OBJS-libcommon): Likewise.
2124         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
2125         inputs to opt-gather.awk.
2126         (options-urls.cc): New Makefile target.
2127         * opt-functions.awk (url_suffix): New function.
2128         (lang_url_suffix): New function.
2129         * options-urls-cc-gen.awk: New file.
2130         * opts.h (get_opt_url_suffix): New decl.
2131
2132 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2133
2134         * params.opt.urls: New file, autogenerated by
2135         regenerate-opt-urls.py.
2136
2137 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2138
2139         * common.opt.urls: New file, autogenerated by
2140         regenerate-opt-urls.py.
2141         * config/aarch64/aarch64.opt.urls: Likewise.
2142         * config/alpha/alpha.opt.urls: Likewise.
2143         * config/alpha/elf.opt.urls: Likewise.
2144         * config/arc/arc-tables.opt.urls: Likewise.
2145         * config/arc/arc.opt.urls: Likewise.
2146         * config/arm/arm-tables.opt.urls: Likewise.
2147         * config/arm/arm.opt.urls: Likewise.
2148         * config/arm/vxworks.opt.urls: Likewise.
2149         * config/avr/avr.opt.urls: Likewise.
2150         * config/bpf/bpf.opt.urls: Likewise.
2151         * config/c6x/c6x-tables.opt.urls: Likewise.
2152         * config/c6x/c6x.opt.urls: Likewise.
2153         * config/cris/cris.opt.urls: Likewise.
2154         * config/cris/elf.opt.urls: Likewise.
2155         * config/csky/csky.opt.urls: Likewise.
2156         * config/csky/csky_tables.opt.urls: Likewise.
2157         * config/darwin.opt.urls: Likewise.
2158         * config/dragonfly.opt.urls: Likewise.
2159         * config/epiphany/epiphany.opt.urls: Likewise.
2160         * config/fr30/fr30.opt.urls: Likewise.
2161         * config/freebsd.opt.urls: Likewise.
2162         * config/frv/frv.opt.urls: Likewise.
2163         * config/ft32/ft32.opt.urls: Likewise.
2164         * config/fused-madd.opt.urls: Likewise.
2165         * config/g.opt.urls: Likewise.
2166         * config/gcn/gcn.opt.urls: Likewise.
2167         * config/gnu-user.opt.urls: Likewise.
2168         * config/h8300/h8300.opt.urls: Likewise.
2169         * config/hpux11.opt.urls: Likewise.
2170         * config/i386/cygming.opt.urls: Likewise.
2171         * config/i386/cygwin.opt.urls: Likewise.
2172         * config/i386/djgpp.opt.urls: Likewise.
2173         * config/i386/i386.opt.urls: Likewise.
2174         * config/i386/mingw-w64.opt.urls: Likewise.
2175         * config/i386/mingw.opt.urls: Likewise.
2176         * config/i386/nto.opt.urls: Likewise.
2177         * config/ia64/ia64.opt.urls: Likewise.
2178         * config/ia64/ilp32.opt.urls: Likewise.
2179         * config/ia64/vms.opt.urls: Likewise.
2180         * config/iq2000/iq2000.opt.urls: Likewise.
2181         * config/linux-android.opt.urls: Likewise.
2182         * config/linux.opt.urls: Likewise.
2183         * config/lm32/lm32.opt.urls: Likewise.
2184         * config/loongarch/loongarch.opt.urls: Likewise.
2185         * config/lynx.opt.urls: Likewise.
2186         * config/m32c/m32c.opt.urls: Likewise.
2187         * config/m32r/m32r.opt.urls: Likewise.
2188         * config/m68k/ieee.opt.urls: Likewise.
2189         * config/m68k/m68k-tables.opt.urls: Likewise.
2190         * config/m68k/m68k.opt.urls: Likewise.
2191         * config/m68k/uclinux.opt.urls: Likewise.
2192         * config/mcore/mcore.opt.urls: Likewise.
2193         * config/microblaze/microblaze.opt.urls: Likewise.
2194         * config/mips/mips-tables.opt.urls: Likewise.
2195         * config/mips/mips.opt.urls: Likewise.
2196         * config/mips/sde.opt.urls: Likewise.
2197         * config/mmix/mmix.opt.urls: Likewise.
2198         * config/mn10300/mn10300.opt.urls: Likewise.
2199         * config/moxie/moxie.opt.urls: Likewise.
2200         * config/msp430/msp430.opt.urls: Likewise.
2201         * config/nds32/nds32-elf.opt.urls: Likewise.
2202         * config/nds32/nds32-linux.opt.urls: Likewise.
2203         * config/nds32/nds32.opt.urls: Likewise.
2204         * config/netbsd-elf.opt.urls: Likewise.
2205         * config/netbsd.opt.urls: Likewise.
2206         * config/nios2/elf.opt.urls: Likewise.
2207         * config/nios2/nios2.opt.urls: Likewise.
2208         * config/nvptx/nvptx-gen.opt.urls: Likewise.
2209         * config/nvptx/nvptx.opt.urls: Likewise.
2210         * config/openbsd.opt.urls: Likewise.
2211         * config/or1k/elf.opt.urls: Likewise.
2212         * config/or1k/or1k.opt.urls: Likewise.
2213         * config/pa/pa-hpux.opt.urls: Likewise.
2214         * config/pa/pa-hpux1010.opt.urls: Likewise.
2215         * config/pa/pa-hpux1111.opt.urls: Likewise.
2216         * config/pa/pa-hpux1131.opt.urls: Likewise.
2217         * config/pa/pa.opt.urls: Likewise.
2218         * config/pa/pa64-hpux.opt.urls: Likewise.
2219         * config/pdp11/pdp11.opt.urls: Likewise.
2220         * config/pru/pru.opt.urls: Likewise.
2221         * config/riscv/riscv.opt.urls: Likewise.
2222         * config/rl78/rl78.opt.urls: Likewise.
2223         * config/rpath.opt.urls: Likewise.
2224         * config/rs6000/476.opt.urls: Likewise.
2225         * config/rs6000/aix64.opt.urls: Likewise.
2226         * config/rs6000/darwin.opt.urls: Likewise.
2227         * config/rs6000/linux64.opt.urls: Likewise.
2228         * config/rs6000/rs6000-tables.opt.urls: Likewise.
2229         * config/rs6000/rs6000.opt.urls: Likewise.
2230         * config/rs6000/sysv4.opt.urls: Likewise.
2231         * config/rtems.opt.urls: Likewise.
2232         * config/rx/elf.opt.urls: Likewise.
2233         * config/rx/rx.opt.urls: Likewise.
2234         * config/s390/s390.opt.urls: Likewise.
2235         * config/s390/tpf.opt.urls: Likewise.
2236         * config/sh/sh.opt.urls: Likewise.
2237         * config/sh/superh.opt.urls: Likewise.
2238         * config/sol2.opt.urls: Likewise.
2239         * config/sparc/long-double-switch.opt.urls: Likewise.
2240         * config/sparc/sparc.opt.urls: Likewise.
2241         * config/stormy16/stormy16.opt.urls: Likewise.
2242         * config/v850/v850.opt.urls: Likewise.
2243         * config/vax/elf.opt.urls: Likewise.
2244         * config/vax/vax.opt.urls: Likewise.
2245         * config/visium/visium.opt.urls: Likewise.
2246         * config/vms/vms.opt.urls: Likewise.
2247         * config/vxworks-smp.opt.urls: Likewise.
2248         * config/vxworks.opt.urls: Likewise.
2249         * config/xtensa/elf.opt.urls: Likewise.
2250         * config/xtensa/uclinux.opt.urls: Likewise.
2251         * config/xtensa/xtensa.opt.urls: Likewise.
2252         * config/bfin/bfin.opt.urls: New file.
2253
2254 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2255
2256         * Makefile.in (OPT_URLS_HTML_DEPS): New.
2257         (regenerate-opt-urls): New target.
2258         (regenerate-opt-urls-unit-test): New target.
2259         * doc/options.texi (Option properties): Add UrlSuffix and
2260         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
2261         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
2262         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
2263         and Makefile.in's OPT_URLS_HTML_DEPS.
2264         (Anatomy of a Target Back End): Add
2265         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
2266         * regenerate-opt-urls.py: New file.
2267
2268 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
2269
2270         * diagnostic-format-sarif.cc
2271         (sarif_builder::make_logical_location_object): Convert to...
2272         (make_sarif_logical_location_object): ...this.
2273         (sarif_builder::set_any_logical_locs_arr): Update for above
2274         change.
2275         (sarif_builder::make_thread_flow_location_object): Call
2276         maybe_add_sarif_properties on each diagnostic_event.
2277         * diagnostic-format-sarif.h (class logical_location): New forward
2278         decl.
2279         (make_sarif_logical_location_object): New decl.
2280         * diagnostic-path.h (class sarif_object): New forward decl.
2281         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
2282
2283 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
2284             Patrick Lin  <patrick@andestech.com>
2285             Rufus Chen  <rufus@andestech.com>
2286             Monk Chiang  <monk.chiang@sifive.com>
2287
2288         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
2289         with Nan-boxing value.
2290         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
2291
2292 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
2293             Jeff Law  <jlaw@ventanamicro.com>
2294
2295         PR rtl-optimization/104914
2296         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
2297         a sign or zero extension is only required if the modified field
2298         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
2299         targets, don't refer to the temporarily incorrectly extended value
2300         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
2301
2302 2024-01-04  Pan Li  <pan2.li@intel.com>
2303
2304         Revert:
2305         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2306
2307         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2308
2309 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2310
2311         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
2312
2313 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
2314
2315         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
2316         offset of fcsr.
2317
2318 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2319
2320         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
2321         (compute_nregs_for_mode): Refine LMUL.
2322         (max_number_of_live_regs): Ditto.
2323         (compute_estimated_lmul): Ditto.
2324         (has_unexpected_spills_p): Ditto.
2325
2326 2024-01-04  Li Wei  <liwei@loongson.cn>
2327
2328         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
2329         Remove useless forward declaration.
2330         (loongarch_is_even_extraction): Remove useless forward declaration.
2331         (loongarch_try_expand_lsx_vshuf_const): Removed.
2332         (loongarch_expand_vec_perm_const_1): Merged.
2333         (loongarch_is_double_duplicate): Removed.
2334         (loongarch_is_center_extraction): Ditto.
2335         (loongarch_is_reversing_permutation): Ditto.
2336         (loongarch_is_di_misalign_extract): Ditto.
2337         (loongarch_is_si_misalign_extract): Ditto.
2338         (loongarch_is_lasx_lowpart_extract): Ditto.
2339         (loongarch_is_op_reverse_perm): Ditto.
2340         (loongarch_is_single_op_perm): Ditto.
2341         (loongarch_is_divisible_perm): Ditto.
2342         (loongarch_is_triple_stride_extract): Ditto.
2343         (loongarch_expand_vec_perm_const_2): Merged.
2344         (loongarch_expand_vec_perm_const): New.
2345         (loongarch_vectorize_vec_perm_const): Adjust.
2346
2347 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
2348
2349         * omp-general.cc: Fix comment typos and misplaced/confusing
2350         comments.  Delete redundant include of omp-general.h.
2351
2352 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
2353
2354         PR rtl-optimization/104914
2355         * config/mips/mips.md (insqisi_extended): New patterns.
2356         (inshisi_extended): Ditto.
2357
2358 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
2359
2360         * config/mips/mips.cc (mips_insn_cost): New function.
2361
2362 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
2363
2364         * config/mips/mips.md (perf_ratio): New attribute.
2365
2366 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2367
2368         PR target/113206
2369         PR target/113209
2370         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
2371         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
2372         blocks belong to infinite loop.
2373         (pre_vsetvl::emit_vsetvl): Remove fake edges.
2374         * config/riscv/t-riscv: Add a new include file.
2375
2376 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2377
2378         * config/riscv/vector.md: Fix indent.
2379
2380 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
2381
2382         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
2383         OMP_CLAUSE__SIMDUID_.
2384         * tree.cc (omp_clause_num_ops): Update position of entry for
2385         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
2386         (omp_clause_code_name): Likewise.
2387
2388 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
2389
2390         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
2391         printing of FUNC_MAP/IND_FUNC_MAP labels.
2392
2393 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
2394
2395         * gcc.cc (process_command): Update copyright notice dates.
2396         * gcov-dump.cc (print_version): Ditto.
2397         * gcov.cc (print_version): Ditto.
2398         * gcov-tool.cc (print_version): Ditto.
2399         * gengtype.cc (create_file): Ditto.
2400         * doc/cpp.texi: Bump @copying's copyright year.
2401         * doc/cppinternals.texi: Ditto.
2402         * doc/gcc.texi: Ditto.
2403         * doc/gccint.texi: Ditto.
2404         * doc/gcov.texi: Ditto.
2405         * doc/install.texi: Ditto.
2406         * doc/invoke.texi: Ditto.
2407
2408 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
2409
2410         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
2411         (fmin<mode>3): Likewise.
2412         (reduc_fmax_scal_<mode>3): New define_expand.
2413         (reduc_fmin_scal_<mode>3): Likewise.
2414
2415 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2416
2417         PR target/113112
2418         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
2419         (max_number_of_live_regs): Ditto.
2420         (has_unexpected_spills_p): Ditto.
2421
2422 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
2423             Jin Ma  <jinma@linux.alibaba.com>
2424             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
2425             Christoph Müllner  <christoph.muellner@vrull.eu>
2426
2427         * config/riscv/vector.md:
2428         Use vector_length_operand for vsetvl patterns.
2429
2430 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2431
2432         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
2433         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
2434
2435 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
2436
2437         * config/aarch64/aarch64-tuning-flags.def
2438         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
2439         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
2440         * config/aarch64/aarch64.cc
2441         (aarch64_override_options_internal): Set
2442         param_fully_pipelined_fma according to tuning option.
2443         * config/aarch64/tuning_models/ampere1.h: Add
2444         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
2445         * config/aarch64/tuning_models/ampere1a.h: Likewise.
2446         * config/aarch64/tuning_models/ampere1b.h: Likewise.
2447
2448 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
2449
2450         * config/riscv/vector-crypto.md: Modify copyright year.
2451
2452 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2453
2454         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
2455
2456 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
2457
2458         * config.in: Regenerate.
2459         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
2460         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
2461         Added TLS Le Relax support.
2462         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
2463         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
2464         * configure: Regenerate.
2465         * configure.ac: Check if binutils supports TLS le relax.
2466
2467 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
2468
2469         * config/riscv/iterators.md: Add rotate insn name.
2470         * config/riscv/riscv.md: Add new insns name for crypto vector.
2471         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
2472         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
2473         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
2474
2475 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2476
2477         PR target/113112
2478         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
2479         pointer type liveness count.
2480 \f
2481 Copyright (C) 2024 Free Software Foundation, Inc.
2482
2483 Copying and distribution of this file, with or without modification,
2484 are permitted in any medium without royalty provided the copyright
2485 notice and this notice are preserved.