gcc/ChangeLog

   1 2024-02-16  Edwin Lu  <ewlu@rivosinc.com>
   2
   3         * doc/sourcebuild.texi: add scan-assembler-bound
   4
   5 2024-02-16  Jason Merrill  <jason@redhat.com>
   6
   7         * gdbhooks.py: Fix regex syntax.
   8
   9 2024-02-16  Richard Biener  <rguenther@suse.de>
  10
  11         PR tree-optimization/113895
  12         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
  13         consistency checking when there are out-of-bound array
  14         accesses.  Allow -1 off when from an array reference with
  15         constant index.
  16
  17 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
  18
  19         PR target/106543
  20         * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
  21         pattern.
  22
  23 2024-02-16  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
  24
  25         * doc/sourcebuild.texi (Effective-Target Keywords, Other
  26         attribugs): Document linker_plugin.
  27         (Require Support): Document dg-require-linker-plugin.
  28
  29 2024-02-16  Kito Cheng  <kito.cheng@sifive.com>
  30
  31         PR target/109349
  32         * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
  33         * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
  34         (RISCV_MINOR_VERSION_BASE): Ditto.
  35         (RISCV_REVISION_VERSION_BASE): Ditto.
  36         * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
  37         rather than magic number.
  38         * config/riscv/riscv.h (riscv_arch_help): New.
  39         (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
  40         (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
  41         --print-supported-extensions.
  42         * config/riscv/riscv.opt (march=help): New.
  43         (print-supported-extensions): New.
  44         (-print-supported-extensions): New.
  45         * doc/invoke.texi (RISC-V Options): Document -march=help.
  46
  47 2024-02-16  Tejas Belagod  <tejas.belagod@arm.com>
  48
  49         PR target/113780
  50         * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
  51         for indirect calls with 4 or more arguments in pac-enabled functions.
  52
  53 2024-02-15  David Faust  <david.faust@oracle.com>
  54
  55         * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
  56         use ldxb instead of ldxh.
  57
  58 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
  59
  60         PR middle-end/113921
  61         * cfgrtl.h (prepend_insn_to_edge): New declaration.
  62         * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
  63         comment.
  64         (prepend_insn_to_edge): New function.
  65         * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
  66         insert_insn_on_edge.
  67
  68 2024-02-15  Richard Biener  <rguenther@suse.de>
  69
  70         PR tree-optimization/111156
  71         * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
  72         at the pattern stmt if any.
  73
  74 2024-02-15  Georg-Johann Lay  <avr@gjlay.de>
  75
  76         PR target/113927
  77         * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
  78         * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
  79         * config/avr/avr.cc (avr_adiw_reg_p): New function.
  80         (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
  81         Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
  82         * config/avr/avr.md: Same.
  83         (attr "isa") <tiny, no_tiny>: Remove.
  84         <adiw, no_adiw>: Add.
  85         (define_insn, define_insn_and_split): When an alternative has
  86         constraint "w", then set attribute "isa" to "adiw".
  87         * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
  88         Built-in define __AVR_HAVE_ADIW__.
  89         * doc/invoke.texi (AVR Options): Document it.
  90
  91 2024-02-15  Andrew Stubbs  <ams@baylibre.com>
  92
  93         * config/gcn/gcn-valu.md
  94         (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
  95         * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
  96         details are supported on RDNA devices.
  97
  98 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
  99
 100         PR middle-end/113508
 101         * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
 102         usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
 103         smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
 104         Add sentence about what the mode m is.
 105
 106 2024-02-15  Andrew Pinski  <quic_apinski@quicinc.com>
 107
 108         * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
 109         smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
 110         var.
 111
 112 2024-02-15  Richard Biener  <rguenther@suse.de>
 113
 114         * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
 115         stmts.
 116
 117 2024-02-15  Jakub Jelinek  <jakub@redhat.com>
 118
 119         PR tree-optimization/113567
 120         * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
 121         _BitInt multiplication, division or modulo with
 122         SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
 123         force the affected inputs into a new SSA_NAME.
 124
 125 2024-02-14  Uros Bizjak  <ubizjak@gmail.com>
 126
 127         PR target/113871
 128         * config/i386/mmx.md (V248FI): New mode iterator.
 129         (V24FI_32): DItto.
 130         (vec_shl_<V248FI:mode>): New expander.
 131         (vec_shl_<V24FI_32:mode>): Ditto.
 132         (vec_shr_<V248FI:mode>): Ditto.
 133         (vec_shr_<V24FI_32:mode>): Ditto.
 134         * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
 135         (vec_shr_<V248FI:mode>): Ditto.
 136
 137 2024-02-14  Jan Hubicka  <jh@suse.cz>
 138
 139         PR tree-optimization/111054
 140         * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
 141
 142 2024-02-14  Tamar Christina  <tamar.christina@arm.com>
 143
 144         * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
 145
 146 2024-02-14  Richard Biener  <rguenther@suse.de>
 147
 148         PR tree-optimization/113910
 149         * bitmap.cc (bitmap_hash): Mix the full element "hash" to
 150         the hashval_t hash.
 151
 152 2024-02-14  Jakub Jelinek  <jakub@redhat.com>
 153
 154         * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
 155         (pp_integer_with_precision): For unsigned ptrdiff_t printing
 156         with u, o or x print ptrdiff_t argument converted to
 157         unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
 158
 159 2024-02-14  Richard Biener  <rguenther@suse.de>
 160
 161         PR middle-end/113576
 162         * expr.cc (do_store_flag): For vector bool compares of vectors
 163         with padding zero that.
 164         * dojump.cc (do_compare_and_jump): Likewise.
 165
 166 2024-02-14  Gerald Pfeifer  <gerald@pfeifer.com>
 167
 168         * doc/install.texi (Prerequisites): Update gettext link.
 169
 170 2024-02-13  H.J. Lu  <hjl.tools@gmail.com>
 171
 172         PR target/113876
 173         * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
 174         Return false if the incoming stack isn't 16-byte aligned.
 175
 176 2024-02-13  Tobias Burnus  <tburnus@baylibre.com>
 177
 178         PR middle-end/113904
 179         * omp-general.cc (struct omp_ts_info): Update for splitting of
 180         OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
 181         * omp-selectors.h (enum omp_tp_type): Replace
 182         OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
 183
 184 2024-02-13  Monk Chiang  <monk.chiang@sifive.com>
 185
 186         PR target/113742
 187         * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
 188         recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
 189
 190 2024-02-13  Richard Biener  <rguenther@suse.de>
 191
 192         PR tree-optimization/113895
 193         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
 194         offset to discover constant array indices in bits, handle
 195         COMPONENT_REF to bitfields.
 196
 197 2024-02-13  Richard Biener  <rguenther@suse.de>
 198
 199         PR tree-optimization/113831
 200         * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
 201         typo in comment.
 202
 203 2024-02-13  Richard Biener  <rguenther@suse.de>
 204
 205         PR tree-optimization/113902
 206         * tree-vect-loop.cc (move_early_exit_stmts): Track
 207         last_seen_vuse for VUSE updating.
 208
 209 2024-02-13  Tamar Christina  <tamar.christina@arm.com>
 210
 211         PR tree-optimization/113734
 212         * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
 213         an early break loop as partial.
 214
 215 2024-02-13  Richard Biener  <rguenther@suse.de>
 216
 217         PR tree-optimization/113898
 218         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
 219         missing accumulated off adjustment.
 220
 221 2024-02-13  Jakub Jelinek  <jakub@redhat.com>
 222
 223         * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
 224         instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
 225         it against UINT_MAX and ULONG_MAX.
 226
 227 2024-02-13  David Malcolm  <dmalcolm@redhat.com>
 228
 229         * diagnostic-core.h (emit_diagnostic_valist): Rename overload
 230         to...
 231         (emit_diagnostic_valist_meta): ...this.
 232         * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
 233         (emit_diagnostic_valist_meta): ...this.
 234
 235 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
 236
 237         PR tree-optimization/113849
 238         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
 239         fast path for widening casts where !m_upwards_2limb and lhs_type
 240         has precision which is a multiple of limb_prec.
 241
 242 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
 243
 244         PR c++/113674
 245         * attribs.cc (extract_attribute_substring): Remove.
 246         (lookup_scoped_attribute_spec): Don't call it.
 247
 248 2024-02-12  Jakub Jelinek  <jakub@redhat.com>
 249
 250         * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
 251         and cast to fmt_size_t instead of %lu and cast to unsigned long.
 252
 253 2024-02-12  Christophe Lyon  <christophe.lyon@linaro.org>
 254
 255         * Makefile.in: Add no-info dependency.
 256         * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
 257         available.
 258         * configure: Regenerate.
 259
 260 2024-02-12  Iain Sandoe  <iain@sandoe.co.uk>
 261
 262         PR target/113855
 263         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
 264         available to all sub-targets.
 265         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
 266         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
 267
 268 2024-02-12  Richard Biener  <rguenther@suse.de>
 269
 270         PR tree-optimization/113831
 271         PR tree-optimization/108355
 272         * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
 273         we see variable array indices and get_ref_base_and_extent
 274         can resolve those to constants fix up the ops to constants
 275         as well.
 276         (ao_ref_init_from_vn_reference): Use 'off' member for
 277         ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
 278         (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
 279
 280 2024-02-12  Pan Li  <pan2.li@intel.com>
 281
 282         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
 283         Replace args to arguments for misspelled term.
 284
 285 2024-02-12  Georg-Johann Lay  <avr@gjlay.de>
 286
 287         PR target/112944
 288         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
 289         <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
 290         when not linked with -mrodata-in-ram.
 291
 292 2024-02-12  Richard Biener  <rguenther@suse.de>
 293
 294         PR tree-optimization/113863
 295         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
 296         Record crossed virtual PHIs.
 297         * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
 298         virtual PHIs.
 299
 300 2024-02-10  Marek Polacek  <polacek@redhat.com>
 301
 302         DR 2237
 303         PR c++/107126
 304         PR c++/97202
 305         * doc/invoke.texi: Document -Wtemplate-id-cdtor.
 306
 307 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
 308
 309         * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
 310         computation of idx for i == 4 of bitint_prec_huge.
 311
 312 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
 313
 314         PR middle-end/110754
 315         * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
 316         decls create PARM_DECL with pointer to original type, set
 317         TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
 318         DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
 319         (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
 320         wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
 321         (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
 322         of the var as argument.
 323
 324 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
 325
 326         * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
 327         size_t and precision 4 for ptrdiff_t.  Formatting fix.
 328         (pp_format): Document %{t,z}{d,i,u,o,x}.  Implement t and z modifiers.
 329         Formatting fixes.
 330         (test_pp_format): Test t and z modifiers.
 331         * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
 332
 333 2024-02-10  Jakub Jelinek  <jakub@redhat.com>
 334
 335         * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
 336         sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
 337         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
 338         * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
 339         and casts to fmt_size_t instead of "%ld" and casts to long.
 340         (print_value_expr_statistics, print_type_hash_statistics): Likewise.
 341         * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
 342         instead of "%lu" and casts to unsigned long.
 343         * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
 344         unsigned long.
 345         * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
 346         and casts to fmt_size_t instead of "%ld" and casts to long.
 347         * cfgexpand.cc (dump_stack_var_partition): Use
 348         HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
 349         and casts to unsigned long.
 350         * gengtype.cc (adjust_field_rtx_def): Likewise.
 351         * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
 352         and casts to fmt_size_t instead of "%ld" and casts to long.
 353         * postreload-gcse.cc (dump_hash_table): Likewise.
 354         * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
 355         and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
 356         (ggc_internal_alloc, ggc_free): Likewise.
 357         * genpreds.cc (write_lookup_constraint_1): Likewise.
 358         (write_insn_constraint_len): Likewise.
 359         * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
 360         and casts to fmt_size_t instead of "%ld" and casts to long.
 361         * varasm.cc (output_constant_pool_contents): Use
 362         HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
 363         * var-tracking.cc (dump_var): Likewise.
 364
 365 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
 366
 367         PR tree-optimization/113783
 368         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
 369         through VIEW_CONVERT_EXPR for final cast checks.  Handle
 370         VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
 371         INTEGER_TYPEs.
 372         (gimple_lower_bitint): Don't merge mergeable operations or other
 373         casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
 374         * expr.cc (expand_expr_real_1): Don't use convert_modes if either
 375         mode is BLKmode.
 376
 377 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
 378
 379         * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
 380         HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
 381         HOST_SIZE_T_PRINT_HEX_PURE): Define.
 382         * ira-conflicts.cc (build_conflict_bit_table): Use it.  Formatting
 383         fixes.
 384
 385 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
 386
 387         PR middle-end/113415
 388         * cfgexpand.cc (expand_asm_stmt): For asm goto, use
 389         duplicate_insn_chain to duplicate after_rtl_seq sequence instead
 390         of hand written loop with emit_insn of copy_insn and emit original
 391         after_rtl_seq on the last edge.
 392
 393 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
 394
 395         PR tree-optimization/113818
 396         * gimple-lower-bitint.cc (add_eh_edge): New function.
 397         (bitint_large_huge::handle_load,
 398         bitint_large_huge::lower_mergeable_stmt,
 399         bitint_large_huge::lower_muldiv_stmt): Use it.
 400
 401 2024-02-09  Jakub Jelinek  <jakub@redhat.com>
 402
 403         PR tree-optimization/113774
 404         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
 405         emit any comparison if m_first and low + 1 is equal to
 406         m_upwards_2limb, simplify condition for that.  If not
 407         single_comparison, not m_first and we can prove that the idx <= low
 408         comparison will be always true, emit instead of idx <= low
 409         comparison low <= low such that cfg cleanup will optimize it at
 410         the end of the pass.
 411
 412 2024-02-08  Aldy Hernandez  <aldyh@redhat.com>
 413
 414         PR tree-optimization/113735
 415         * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
 416         limit_check().
 417
 418 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
 419
 420         * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
 421         (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
 422
 423 2024-02-08  H.J. Lu  <hjl.tools@gmail.com>
 424
 425         PR target/113711
 426         PR target/113733
 427         * config/i386/constraints.md: List all constraints with j prefix.
 428         (j>): Change auto-dec to auto-inc in documentation.
 429         (je): Changed to a memory constraint with APX NDD TLS operand
 430         check.
 431         (jM): New memory constraint for APX NDD instructions.
 432         (jO): Likewise.
 433         * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
 434         * config/i386/i386.cc (x86_poff_operand_p): Likewise.
 435         * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
 436         (*add<mode>_1[SWI48]): Use je and jM.
 437         (addsi_1_zext): Use jM.
 438         (*addv<dwi>4_doubleword_1[DWI]): Likewise.
 439         (*sub<mode>_1[SWI]): Use jM.
 440         (@add<mode>3_cc_overflow_1[SWI]): Likewise.
 441         (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
 442         (*and<dwi>3_doubleword): Likewise.
 443         (*anddi_1): Use jM.
 444         (*andsi_1_zext): Likewise.
 445         (*and<mode>_1[SWI24]): Likewise.
 446         (*<code><dwi>3_doubleword[any_or]): Use rjO
 447         (*code<mode>_1[any_or SWI248]): Use jM.
 448         (*<code>si_1_zext[zero_extend + any_or]): Likewise.
 449         * config/i386/predicates.md (apx_ndd_memory_operand): New.
 450         (apx_ndd_add_memory_operand): Likewise.
 451
 452 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
 453
 454         PR target/113824
 455         * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
 456         * doc/avr-mmcu.texi: Rebuild.
 457
 458 2024-02-08  Tamar Christina  <tamar.christina@arm.com>
 459
 460         PR tree-optimization/113808
 461         * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
 462         value cross iterations.
 463
 464 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
 465
 466         * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
 467         defines __AVR_PM_BASE_ADDRESS__ if the core has it.
 468
 469 2024-02-08  Richard Biener  <rguenther@suse.de>
 470
 471         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
 472         Revert last change to dr_may_alias_p.
 473
 474 2024-02-08  Georg-Johann Lay  <avr@gjlay.de>
 475
 476         * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
 477         cc1_rodata_in_ram.  Rename spec link_misc to link_rodata_in_ram.
 478         Remove spec asm_misc.
 479         * config/avr/specs.h: Same.
 480
 481 2024-02-08  Pan Li  <pan2.li@intel.com>
 482
 483         PR target/113766
 484         * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
 485         sure the c.arg_num is >= 2 before checking.
 486         (struct build_frm_base): Ditto.
 487         (struct narrow_alu_def): Ditto.
 488
 489 2024-02-07  Richard Biener  <rguenther@suse.de>
 490
 491         PR tree-optimization/113796
 492         * tree-if-conv.cc (combine_blocks): Wipe range-info before
 493         replacing PHIs and inserting predicates.
 494
 495 2024-02-07  Roger Sayle  <roger@nextmovesoftware.com>
 496             Uros Bizjak  <ubizjak@gmail.com>
 497
 498         PR target/113690
 499         * config/i386/i386-features.cc (timode_convert_cst): New helper
 500         function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
 501         CONST_VECTOR.
 502         (timode_scalar_chain::convert_op): Use timode_convert_cst.
 503         (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
 504         Use timode_convert_cst.
 505
 506 2024-02-07  Victor Do Nascimento  <victor.donascimento@arm.com>
 507
 508         * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
 509         * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
 510         (AARCH64_FL_DEBUGv8p9): Likewise.
 511         (AARCH64_FL_FGT2): Likewise.Likewise.
 512         (AARCH64_FL_ITE): Likewise.
 513         (AARCH64_FL_PFAR): Likewise.
 514         (AARCH64_FL_PMUv3_ICNTR): Likewise.
 515         (AARCH64_FL_PMUv3_SS): Likewise.
 516         (AARCH64_FL_PMUv3p9): Likewise.
 517         (AARCH64_FL_RASv2): Likewise.
 518         (AARCH64_FL_S1PIE): Likewise.
 519         (AARCH64_FL_S1POE): Likewise.
 520         (AARCH64_FL_S2PIE): Likewise.
 521         (AARCH64_FL_S2POE): Likewise.
 522         (AARCH64_FL_SCTLR2): Likewise.
 523         (AARCH64_FL_SEBEP): Likewise.
 524         (AARCH64_FL_SPE_FDS): Likewise.
 525         (AARCH64_FL_TCR2): Likewise.
 526
 527 2024-02-07  Richard Biener  <rguenther@suse.de>
 528
 529         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
 530         Only check whether reads are in-bound in places that are not safe.
 531         Fix dependence check.  Add missing newline.  Clarify comments.
 532
 533 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
 534
 535         PR tree-optimization/113750
 536         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
 537         for single predecessor when doing early break vect.
 538         * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
 539         after labels.
 540
 541 2024-02-07  Tamar Christina  <tamar.christina@arm.com>
 542
 543         PR tree-optimization/113731
 544         * gimple-iterator.cc (gsi_move_before): Take new parameter for update
 545         method.
 546         * gimple-iterator.h (gsi_move_before): Default new param to
 547         GSI_SAME_STMT.
 548         * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
 549         GSI_NEW_STMT.
 550
 551 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
 552
 553         PR tree-optimization/113756
 554         * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
 555         use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
 556         of lh_bits value and mask.
 557
 558 2024-02-07  Jakub Jelinek  <jakub@redhat.com>
 559
 560         PR tree-optimization/113753
 561         * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
 562         UNSIGNED rather than SIGNED.  If high or needs_overflow and prec is
 563         not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
 564         so that they start with r[half_blocks_needed] lowest bit.  Fix up
 565         computation of top mask for SIGNED.
 566
 567 2024-02-07  Pan Li  <pan2.li@intel.com>
 568
 569         PR target/113766
 570         * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
 571         the signature of func.
 572         * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
 573         * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
 574         overloaded func with empty args error.
 575
 576 2024-02-06  H.J. Lu  <hjl.tools@gmail.com>
 577
 578         PR target/113689
 579         * config/i386/i386.cc (x86_64_select_profile_regnum): Return
 580         R10_REG after sorry.
 581
 582 2024-02-06  Andrew Carlotti  <andrew.carlotti@arm.com>
 583
 584         * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
 585         Move before new caller, and add ".default" suffix.
 586         (get_suffixed_assembler_name): New.
 587         (make_resolver_func): Use get_suffixed_assembler_name.
 588         (aarch64_generate_version_dispatcher_body): Redo name mangling.
 589
 590 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
 591
 592         PR target/113763
 593         * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
 594         element from std::pair<unsigned int, char> to an unnamed struct.
 595         Adjust uses of tile range variable.
 596
 597 2024-02-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 598
 599         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
 600         (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
 601
 602 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
 603
 604         PR sanitizer/110676
 605         * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
 606         reset maxlen to sizetype maximum.
 607
 608 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
 609
 610         PR tree-optimization/113736
 611         * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
 612         var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
 613
 614 2024-02-06  Jakub Jelinek  <jakub@redhat.com>
 615
 616         PR tree-optimization/113759
 617         * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
 618         or from_unsignedN differs from properties of typeN, update typeN
 619         to build_nonstandard_integer_type.  If TREE_TYPE (rhsN) is not
 620         uselessly convertible to typeN, convert it using fold_convert or
 621         build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
 622         (convert_plusminus_to_widen): Likewise.
 623
 624 2024-02-06  Tejas Belagod  <tejas.belagod@arm.com>
 625
 626         PR target/112577
 627         * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
 628         vector structure modes correctly.
 629
 630 2024-02-05  Christoph Müllner  <christoph.muellner@vrull.eu>
 631
 632         * config/riscv/thead.cc (th_print_operand_address): Fix compiler
 633         warning.
 634
 635 2024-02-05  H.J. Lu  <hjl.tools@gmail.com>
 636
 637         PR target/113689
 638         * config/i386/i386.cc (x86_64_select_profile_regnum): New.
 639         (x86_function_profiler): Call x86_64_select_profile_regnum to
 640         get a scratch register for large model profiling.
 641
 642 2024-02-05  Richard Ball  <richard.ball@arm.com>
 643
 644         * config/arm/arm.cc (arm_output_mi_thunk): Emit
 645         insn for bti_c when bti is enabled.
 646
 647 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
 648
 649         * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
 650         neg.
 651
 652 2024-02-05  Xi Ruoyao  <xry111@xry111.site>
 653
 654         * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
 655         (neg<mode>2): Change the mode iterator from MSA to IMSA because
 656         in FP arithmetic we cannot use (0 - x) for -x.
 657         (neg<mode>2): New define_insn to implement FP vector negation,
 658         using a bnegi instruction to negate the sign bit.
 659
 660 2024-02-05  Richard Biener  <rguenther@suse.de>
 661
 662         PR tree-optimization/113707
 663         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
 664         checking the avail set treat out-of-region defines as
 665         available.
 666
 667 2024-02-05  Richard Biener  <rguenther@suse.de>
 668
 669         * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
 670         the default mode when building a pointer.
 671
 672 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
 673
 674         PR tree-optimization/113737
 675         * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
 676         has just a single label, remove it and make single successor edge
 677         EDGE_FALLTHRU.
 678
 679 2024-02-05  Jakub Jelinek  <jakub@redhat.com>
 680
 681         PR target/113059
 682         * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
 683         Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
 684         df_analyze call.
 685
 686 2024-02-05  Richard Biener  <rguenther@suse.de>
 687
 688         PR target/113255
 689         * config/i386/i386-expand.cc
 690         (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
 691         Use a new pseudo for the skipped number of bytes.
 692
 693 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
 694
 695         * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
 696         * doc/invoke.texi (RISC-V Options): Add sifive-p450,
 697         sifive-p670.
 698
 699 2024-02-05  Monk Chiang  <monk.chiang@sifive.com>
 700
 701         * config/riscv/riscv.md: Include sifive-p400.md.
 702         * config/riscv/sifive-p400.md: New file.
 703         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
 704         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
 705         Add sifive_p400.
 706         * config/riscv/riscv.cc (sifive_p400_tune_info): New.
 707         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
 708         * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
 709
 710 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
 711
 712         * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
 713         Add missing ":SI" to the match_operator.
 714
 715 2024-02-04  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
 716
 717         * config/xtensa/xtensa.md (SHI): New mode iterator.
 718         (2 split patterns related to constsynth):
 719         Change to also accept HImode operands.
 720
 721 2024-02-04  Jeff Law  <jlaw@ventanamicro.com>
 722
 723         * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
 724         similarly.
 725
 726 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
 727
 728         * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
 729         incorrect expand.
 730         * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
 731         (elmsgnbit): Likewise.
 732         (neg<mode:FVEC>2): New define_insn.
 733         * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
 734         are now instantiated in simd.md.
 735
 736 2024-02-04  Xi Ruoyao  <xry111@xry111.site>
 737
 738         * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
 739         use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
 740         MAX_MACHINE_MODE.
 741
 742 2024-02-04  Li Wei  <liwei@loongson.cn>
 743
 744         * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
 745         (loongarch_expand_vselect_vconcat): Ditto.
 746         (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
 747         all 128-bit constant permutation situations.
 748         (loongarch_expand_lsx_shuffle): Adjust and rename function name.
 749         (loongarch_is_imm_set_shuffle): Renamed function name.
 750         (loongarch_expand_vec_perm_even_odd): Function forward declaration.
 751         (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
 752         extract-even and extract-odd permutations.
 753         (loongarch_is_odd_extraction): Delete.
 754         (loongarch_is_even_extraction): Ditto.
 755         (loongarch_expand_vec_perm_const): Adjust.
 756
 757 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
 758
 759         PR middle-end/113722
 760         * wide-int.cc (wi::bswap_large): Rename third argument from
 761         len to xlen and adjust use in safe_uhwi.  Add len variable, set
 762         it to BLOCKS_NEEDED (precision) and use it for clearing of val
 763         and as canonize argument.  Clear val using memset instead of
 764         a loop.
 765
 766 2024-02-03  Jakub Jelinek  <jakub@redhat.com>
 767
 768         * ggc-common.cc (gt_pch_save): Allow addr to be equal to
 769         mmi.preferred_base + mmi.size - sizeof (void *).
 770
 771 2024-02-03  Xi Ruoyao  <xry111@xry111.site>
 772
 773         * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
 774         * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
 775         the ODR-violating locale declaration.
 776
 777 2024-02-02  Tamar Christina  <tamar.christina@arm.com>
 778
 779         PR tree-optimization/113588
 780         PR tree-optimization/113467
 781         * tree-vect-data-refs.cc
 782         (vect_analyze_data_ref_dependence):  Choose correct dest and fix checks.
 783         (vect_analyze_early_break_dependences): Update comments.
 784
 785 2024-02-02  John David Anglin  <danglin@gcc.gnu.org>
 786
 787         PR target/59778
 788         * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
 789         and PA_BUILTIN_SET_FPSR builtins.
 790         * (pa_builtins_icode): Declare.
 791         * (def_builtin, pa_fpu_init_builtins): New.
 792         * (pa_init_builtins): Initialize FPU builtins.
 793         * (pa_builtin_decl, pa_expand_builtin_1): New.
 794         * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
 795         PA_BUILTIN_SET_FPSR builtins.
 796         * (pa_atomic_assign_expand_fenv): New.
 797         * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
 798         UNSPECV constants.
 799         (get_fpsr, put_fpsr): New expanders.
 800         (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
 801         insn patterns.
 802
 803 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 804
 805         PR target/113697
 806         * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
 807
 808 2024-02-02  Jonathan Wakely  <jwakely@redhat.com>
 809
 810         * doc/extend.texi (Common Type Attributes): Fix typo in
 811         description of hardbool.
 812
 813 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
 814
 815         PR tree-optimization/113692
 816         * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
 817         from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
 818         final_cast_p.
 819
 820 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
 821
 822         PR middle-end/113699
 823         * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
 824         uninitialized large/huge _BitInt SSA_NAME inputs.
 825
 826 2024-02-02  Jakub Jelinek  <jakub@redhat.com>
 827
 828         PR middle-end/113705
 829         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
 830         around wi::to_wide in order to compare value in prec precision.
 831
 832 2024-02-02  Lehua Ding  <lehua.ding@rivai.ai>
 833
 834         Revert:
 835         2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 836
 837         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
 838
 839 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 840
 841         * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
 842
 843 2024-02-02  Pan Li  <pan2.li@intel.com>
 844
 845         * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
 846         (riscv_pass_by_reference): Ditto.
 847         (riscv_fntype_abi): Ditto.
 848
 849 2024-02-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 850
 851         * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
 852         (pre_vsetvl::cleaup): Remove vsetvl_pre.
 853         (pre_vsetvl::remove_vsetvl_pre_insns): New function.
 854
 855 2024-02-02  Jiahao Xu  <xujiahao@loongson.cn>
 856
 857         * config/loongarch/larchintrin.h
 858         (__frecipe_s): Update function return type.
 859         (__frecipe_d): Ditto.
 860         (__frsqrte_s): Ditto.
 861         (__frsqrte_d): Ditto.
 862
 863 2024-02-02  Li Wei  <liwei@loongson.cn>
 864
 865         * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
 866         (loongarch_vector_costs::add_stmt_cost): Adjust.
 867
 868 2024-02-02  Xi Ruoyao  <xry111@xry111.site>
 869
 870         * config/loongarch/loongarch.md (unspec): Add
 871         UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
 872         (la_pcrel64_two_parts): New define_insn.
 873         * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
 874         typo in the comment.
 875         (loongarch_call_tls_get_addr): If -mcmodel=extreme
 876         -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
 877         addressing the TLS symbol and __tls_get_addr.  Emit an REG_EQUAL
 878         note to allow CSE addressing __tls_get_addr.
 879         (loongarch_legitimize_tls_address): If -mcmodel=extreme
 880         -mexplicit-relocs={always,auto}, address TLS IE symbols with
 881         la_pcrel64_two_parts.
 882         (loongarch_split_symbol): If -mcmodel=extreme
 883         -mexplicit-relocs={always,auto}, address symbols with
 884         la_pcrel64_two_parts.
 885         (loongarch_output_mi_thunk): Clean up unreachable code.  If
 886         -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
 887         thunks with la_pcrel64_two_parts.
 888
 889 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
 890
 891         * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
 892         Add support for call36.
 893
 894 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
 895
 896         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
 897         When the code model of the symbol is extreme and -mexplicit-relocs=auto,
 898         the macro instruction loading symbol address is not applicable.
 899         (loongarch_call_tls_get_addr): Adjust code.
 900         (loongarch_legitimize_tls_address): Likewise.
 901
 902 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
 903
 904         * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
 905         Add function declaration.
 906         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
 907         For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
 908         is not allowed
 909         (loongarch_load_tls): Added macro support in extreme mode.
 910         (loongarch_call_tls_get_addr): Likewise.
 911         (loongarch_legitimize_tls_address): Likewise.
 912         (loongarch_force_address): Likewise.
 913         (loongarch_legitimize_move): Likewise.
 914         (loongarch_output_mi_thunk): Likewise.
 915         (loongarch_option_override_internal): Remove the code that detects
 916         explicit relocs status.
 917         (loongarch_handle_model_attribute): Likewise.
 918         * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
 919         * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
 920         (symbolic_off64_or_reg_operand): Likewise.
 921
 922 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
 923
 924         * config/loongarch/loongarch.cc (loongarch_load_tls):
 925         Load all types of tls symbols through one function.
 926         (loongarch_got_load_tls_gd): Delete.
 927         (loongarch_got_load_tls_ld): Delete.
 928         (loongarch_got_load_tls_ie): Delete.
 929         (loongarch_got_load_tls_le): Delete.
 930         (loongarch_call_tls_get_addr): Modify the called function name.
 931         (loongarch_legitimize_tls_address): Likewise.
 932         * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
 933         (@load_tls<mode>): New template.
 934         (@got_load_tls_ld<mode>): Delete.
 935         (@got_load_tls_le<mode>): Delete.
 936         (@got_load_tls_ie<mode>): Delete.
 937
 938 2024-02-02  Lulu Cheng  <chenglulu@loongson.cn>
 939
 940         * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
 941         (loongarch_legitimize_address): Add logical transformation code.
 942
 943 2024-02-01  Marek Polacek  <polacek@redhat.com>
 944
 945         * doc/invoke.texi: Update -Wdangling-reference documentation.
 946
 947 2024-02-01  Uros Bizjak  <ubizjak@gmail.com>
 948
 949         PR target/113701
 950         * config/i386/i386.md (*cmp<dwi>_doubleword):
 951         Do not force SUBREG pieces to pseudos.
 952
 953 2024-02-01  John David Anglin  <danglin@gcc.gnu.org>
 954
 955         * config/pa/pa.md (atomic_storedi_1): Fix bug in
 956         alternative 1.
 957
 958 2024-02-01  Georg-Johann Lay  <avr@gjlay.de>
 959
 960         * config/avr/avr.cc: Tabify.
 961
 962 2024-02-01  Richard Ball  <richard.ball@arm.com>
 963
 964         PR tree-optimization/111268
 965         * tree-vect-slp.cc (vectorizable_slp_permutation_1):
 966         Add variable-length check for vector input arguments
 967         to a function.
 968
 969 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
 970
 971         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
 972         hard-code number of SGPR/VGPR/AVGPR registers.
 973         * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
 974         SGPR/VGPR/AVGPR registers.
 975
 976 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
 977
 978         * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
 979         attribute, and include sifive-p600.md.
 980         * config/riscv/generic-ooo.md: Update type attribute.
 981         * config/riscv/generic.md: Update type attribute.
 982         * config/riscv/sifive-7.md: Update type attribute.
 983         * config/riscv/sifive-p600.md: New file.
 984         * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
 985         * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
 986         Add sifive_p600.
 987         * config/riscv/riscv.cc (sifive_p600_tune_info): New.
 988         * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
 989         * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
 990
 991 2024-02-01  Monk Chiang  <monk.chiang@sifive.com>
 992
 993         * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
 994         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
 995         * config/riscv/riscv.opt: New macro for 7 new unprivileged
 996         extensions.
 997         * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
 998         Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
 999
1000 2024-02-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
1001
1002         * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
1003         -static-libasan.  Add missing whitespace.
1004
1005 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
1006
1007         * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
1008         (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
1009         Don't 'define_constants'.
1010
1011 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
1012
1013         * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
1014
1015 2024-02-01  Thomas Schwinge  <tschwinge@baylibre.com>
1016
1017         * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
1018         [TARGET_RDNA3]: Adjust.
1019
1020 2024-02-01  Richard Biener  <rguenther@suse.de>
1021
1022         PR tree-optimization/113693
1023         * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
1024         data when available.
1025
1026 2024-02-01  Jakub Jelinek  <jakub@redhat.com>
1027             Jason Merrill  <jason@redhat.com>
1028
1029         PR c++/113531
1030         * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
1031         on variables which were promoted to TREE_STATIC.
1032
1033 2024-02-01  Roger Sayle  <roger@nextmovesoftware.com>
1034             Richard Biener  <rguenther@suse.de>
1035
1036         PR target/113560
1037         * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
1038         information via tree_non_zero_bits to check if this operand
1039         is suitably extended for a widening (or highpart) multiplication.
1040         (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
1041         isn't already of the claimed type.
1042
1043 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
1044
1045         Revert:
1046         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
1047
1048         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1049         (generic_ooo_branch): ditto
1050         * config/riscv/generic.md (generic_sfb_alu): ditto
1051         (generic_fmul_half): ditto
1052         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1053         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
1054         (sifive_7_popcount): ditto
1055         * config/riscv/vector.md: change rdfrm to fmove
1056         * config/riscv/zc.md: change pushpop to load/store
1057
1058 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
1059
1060         Revert:
1061         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
1062                     Robin Dapp  <rdapp.gcc@gmail.com>
1063
1064         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1065         (generic_ooo_vec_load): ditto
1066         (generic_ooo_vec_store): ditto
1067         (generic_ooo_vec_loadstore_seg): ditto
1068         (generic_ooo_vec_alu): ditto
1069         (generic_ooo_vec_fcmp): ditto
1070         (generic_ooo_vec_imul): ditto
1071         (generic_ooo_vec_fadd): ditto
1072         (generic_ooo_vec_fmul): ditto
1073         (generic_ooo_crypto): ditto
1074         (generic_ooo_perm): ditto
1075         (generic_ooo_vec_reduction): ditto
1076         (generic_ooo_vec_ordered_reduction): ditto
1077         (generic_ooo_vec_idiv): ditto
1078         (generic_ooo_vec_float_divsqrt): ditto
1079         (generic_ooo_vec_mask): ditto
1080         (generic_ooo_vec_vesetvl): ditto
1081         (generic_ooo_vec_setrm): ditto
1082         (generic_ooo_vec_readlen): ditto
1083         * config/riscv/riscv.md: include generic-vector-ooo
1084         * config/riscv/generic-vector-ooo.md: New file. to here
1085
1086 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
1087
1088         Revert:
1089         2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
1090
1091         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
1092
1093 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
1094
1095         * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
1096
1097 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
1098             Robin Dapp  <rdapp.gcc@gmail.com>
1099
1100         * config/riscv/generic-ooo.md (generic_ooo): Move reservation
1101         (generic_ooo_vec_load): ditto
1102         (generic_ooo_vec_store): ditto
1103         (generic_ooo_vec_loadstore_seg): ditto
1104         (generic_ooo_vec_alu): ditto
1105         (generic_ooo_vec_fcmp): ditto
1106         (generic_ooo_vec_imul): ditto
1107         (generic_ooo_vec_fadd): ditto
1108         (generic_ooo_vec_fmul): ditto
1109         (generic_ooo_crypto): ditto
1110         (generic_ooo_perm): ditto
1111         (generic_ooo_vec_reduction): ditto
1112         (generic_ooo_vec_ordered_reduction): ditto
1113         (generic_ooo_vec_idiv): ditto
1114         (generic_ooo_vec_float_divsqrt): ditto
1115         (generic_ooo_vec_mask): ditto
1116         (generic_ooo_vec_vesetvl): ditto
1117         (generic_ooo_vec_setrm): ditto
1118         (generic_ooo_vec_readlen): ditto
1119         * config/riscv/riscv.md: include generic-vector-ooo
1120         * config/riscv/generic-vector-ooo.md: New file. to here
1121
1122 2024-02-01  Edwin Lu  <ewlu@rivosinc.com>
1123
1124         * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
1125         (generic_ooo_branch): ditto
1126         * config/riscv/generic.md (generic_sfb_alu): ditto
1127         (generic_fmul_half): ditto
1128         * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
1129         * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
1130         (sifive_7_popcount): ditto
1131         * config/riscv/vector.md: change rdfrm to fmove
1132         * config/riscv/zc.md: change pushpop to load/store
1133
1134 2024-02-01  Andrew Pinski  <quic_apinski@quicinc.com>
1135
1136         PR target/113657
1137         * config/aarch64/aarch64-simd.md (split for movv8di):
1138         For strict aligned mode, use DImode instead of TImode.
1139
1140 2024-01-31  Robin Dapp  <rdapp@ventanamicro.com>
1141
1142         PR middle-end/113607
1143         * match.pd: Make sure else values match when folding a
1144         vec_cond into a conditional operation.
1145
1146 2024-01-31  Marek Polacek  <polacek@redhat.com>
1147
1148         * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
1149
1150 2024-01-31  Tamar Christina  <tamar.christina@arm.com>
1151             Matthew Malcomson  <matthew.malcomson@arm.com>
1152
1153         PR sanitizer/112644
1154         * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
1155         memcmp.
1156         * builtins.cc (expand_builtin): Include HWASAN when checking for
1157         builtin inlining.
1158
1159 2024-01-31  Richard Biener  <rguenther@suse.de>
1160
1161         PR middle-end/110176
1162         * match.pd (zext (bool) <= (int) 4294967295u): Make sure
1163         to match INTEGER_CST only without outstanding conversion.
1164
1165 2024-01-31  Alex Coplan  <alex.coplan@arm.com>
1166
1167         PR target/111677
1168         * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
1169         V16QImode for the full 16-byte FPR saves in the vector PCS case.
1170
1171 2024-01-31  Richard Biener  <rguenther@suse.de>
1172
1173         PR tree-optimization/111444
1174         * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
1175         vn_reference_lookup_2 when optimistically skipping may-defs.
1176
1177 2024-01-31  Richard Biener  <rguenther@suse.de>
1178
1179         PR tree-optimization/113630
1180         * tree-ssa-pre.cc (compute_avail): Avoid registering a
1181         reference with a representation with not matching base
1182         access size.
1183
1184 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
1185
1186         PR rtl-optimization/113656
1187         * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
1188         <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
1189
1190 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
1191
1192         PR debug/113637
1193         * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
1194         with BLKmode are larger than DWARF2_ADDR_SIZE.
1195
1196 2024-01-31  Jakub Jelinek  <jakub@redhat.com>
1197
1198         PR tree-optimization/113639
1199         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
1200         For VIEW_CONVERT_EXPR set rhs1 to its operand.
1201
1202 2024-01-31  Richard Biener  <rguenther@suse.de>
1203
1204         PR tree-optimization/113670
1205         * tree-vect-data-refs.cc (vect_check_gather_scatter):
1206         Make sure we can take the address of the reference base.
1207
1208 2024-01-31  Georg-Johann Lay  <avr@gjlay.de>
1209
1210         * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
1211         ATA5835, ATtiny64AUTO, ATA5700M322.
1212         * doc/avr-mmcu.texi: Rebuild.
1213
1214 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
1215
1216         PR debug/113394
1217         * ipa-strub.cc (build_ref_type_for): Drop nonaliased.  Adjust
1218         caller.
1219
1220 2024-01-31  Alexandre Oliva  <oliva@adacore.com>
1221
1222         PR middle-end/112917
1223         PR middle-end/113100
1224         * builtins.cc (expand_builtin_stack_address): Use
1225         STACK_ADDRESS_OFFSET.
1226         * doc/extend.texi (__builtin_stack_address): Adjust.
1227         * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
1228         * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
1229         * doc/tm.texi: Rebuilt.
1230
1231 2024-01-31  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1232
1233         PR target/113495
1234         * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
1235         (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
1236         (pre_vsetvl::compute_transparent): New function.
1237         (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
1238
1239 2024-01-30  Fangrui Song  <maskray@google.com>
1240
1241         PR target/105576
1242         * config/i386/constraints.md: Define constraint "Ws".
1243         * doc/md.texi: Document it.
1244
1245 2024-01-30  Marek Polacek  <polacek@redhat.com>
1246
1247         PR c++/110358
1248         PR c++/109640
1249         * doc/invoke.texi: Update -Wdangling-reference description.
1250
1251 2024-01-30  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
1252
1253         * config/xtensa/constraints.md (R, T, U):
1254         Change define_constraint to define_memory_constraint.
1255         * config/xtensa/predicates.md (move_operand): Don't check that a
1256         constant pool operand size is a multiple of UNITS_PER_WORD.
1257         * config/xtensa/xtensa.cc
1258         (xtensa_lra_p, TARGET_LRA_P): Remove.
1259         (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
1260         clause as it can no longer be true.
1261         (fixup_subreg_mem): Drop function.
1262         (xtensa_output_integer_literal_parts): Consider 16-bit wide
1263         constants.
1264         (xtensa_legitimate_constant_p): Add short-circuit path for
1265         integer load instructions. Don't check that mode size is
1266         at least UNITS_PER_WORD.
1267         * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
1268         rather reload_in_progress and reload_completed.
1269         (doloop_end): Drop operand 2.
1270         (movhi_internal): Add alternative loading constant from a
1271         literal pool.
1272         (define_split for DI register_operand): Don't limit to
1273         !TARGET_AUTO_LITPOOLS.
1274         * config/xtensa/xtensa.opt (mlra): Change to no effect.
1275
1276 2024-01-30  Pan Li  <pan2.li@intel.com>
1277
1278         * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
1279         calculate the gpr count required by vls mode.
1280         (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
1281         (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
1282         for vls mode.
1283         (riscv_get_arg_info): Add vls mode handling.
1284         (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
1285
1286 2024-01-30  Richard Biener  <rguenther@suse.de>
1287
1288         PR tree-optimization/113659
1289         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1290         Handle main exit without virtual use.
1291
1292 2024-01-30  Christoph Müllner  <christoph.muellner@vrull.eu>
1293
1294         * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
1295
1296 2024-01-30  Iain Sandoe  <iain@sandoe.co.uk>
1297
1298         PR libgcc/113403
1299         * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
1300         (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
1301         * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
1302         * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
1303         * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
1304         * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
1305
1306 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
1307
1308         PR target/113623
1309         * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
1310         Mark all registers that occur in addresses as needing a GPR.
1311
1312 2024-01-30  Richard Sandiford  <richard.sandiford@arm.com>
1313
1314         PR target/113636
1315         * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
1316         the containing insn as an extra parameter.  Reset debug instructions
1317         if they reference a register that is no longer used by real insns.
1318         (early_ra::apply_allocation): Update calls accordingly.
1319
1320 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
1321
1322         PR tree-optimization/113603
1323         * tree-ssa-strlen.cc (strlen_pass::handle_store): After
1324         count_nonzero_bytes call refetch si using get_strinfo in case it
1325         has been unshared in the meantime.
1326
1327 2024-01-30  Jakub Jelinek  <jakub@redhat.com>
1328
1329         PR middle-end/101195
1330         * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
1331         fit into unsigned HOST_WIDE_INT, return constm1_rtx.
1332
1333 2024-01-30  Jin Ma  <jinma@linux.alibaba.com>
1334
1335         * config/riscv/thead.cc (th_print_operand_address): Change %ld
1336         to %lld.
1337
1338 2024-01-29  Manos Anagnostakis  <manos.anagnostakis@vrull.eu>
1339             Manolis Tsamis  <manolis.tsamis@vrull.eu>
1340             Philipp Tomsich  <philipp.tomsich@vrull.eu>
1341
1342         * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
1343         * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
1344         Likewise.
1345         * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
1346         Call on framework moved later.
1347
1348 2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>
1349
1350         * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
1351         instruction in naked function epilogues.
1352
1353 2024-01-29  YunQiang Su  <syq@gcc.gnu.org>
1354
1355         PR target/113655
1356         * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
1357         gcc_cv_as_mips_explicit_relocs.
1358         * configure: Regnerated.
1359
1360 2024-01-29  Matthieu Longo  <matthieu.longo@arm.com>
1361
1362         PR target/108933
1363         * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
1364         Correct generated RTL.
1365         (arm_rev16si2_alt1): Correctly handle conditional execution.
1366         (arm_rev16si2_alt2): Likewise.
1367
1368 2024-01-29  Richard Biener  <rguenther@suse.de>
1369
1370         PR middle-end/113622
1371         * expr.cc (expand_assignment): Spill hard registers if
1372         we index them with a variable offset.
1373
1374 2024-01-29  Richard Biener  <rguenther@suse.de>
1375
1376         PR middle-end/113622
1377         * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
1378         Also allow DECL_HARD_REGISTER variables.
1379
1380 2024-01-29  Alex Coplan  <alex.coplan@arm.com>
1381
1382         PR target/113616
1383         * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
1384         Use iterate_safely when iterating over debug uses.
1385         (fixup_debug_uses): Likewise.
1386         (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
1387         over nondebug insns instead of manually maintaining the next insn.
1388         * iterator-utils.h (class safe_iterator): New.
1389         (iterate_safely): New.
1390
1391 2024-01-29  H.J. Lu  <hjl.tools@gmail.com>
1392
1393         PR target/38534
1394         * config/i386/i386-options.cc (ix86_set_func_type): Save
1395         callee-saved registers in noreturn functions for -O0/-Og.
1396
1397 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
1398
1399         PR target/113615
1400         * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
1401         define for !TARGET_RDNA2_PLUS.
1402
1403 2024-01-29  Richard Sandiford  <richard.sandiford@arm.com>
1404
1405         PR target/113281
1406         * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
1407         workaround for right shifts.
1408         (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
1409         (vect_determine_precisions_from_range): Be more selective about
1410         which codes can be narrowed based on their input and output ranges.
1411         For shifts, require at least one more bit of precision than the
1412         maximum shift amount.
1413
1414 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
1415
1416         * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
1417
1418 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
1419
1420         * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
1421         but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
1422         LLVM 13.0.1+.
1423
1424 2024-01-29  Tobias Burnus  <tburnus@baylibre.com>
1425
1426         PR other/111966
1427         * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
1428         (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
1429         (SET_SRAM_ECC_UNSET): ... this.
1430         (copy_early_debug_info): Remove gfx900 special case, now handled as
1431         part of the generic handling.
1432         (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
1433
1434 2024-01-29  Jakub Jelinek  <jakub@redhat.com>
1435
1436         PR tree-optimization/110603
1437         * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
1438         setting of pdata->maxlen to vr.upper_bound (which is unconditionally
1439         overwritten anyway).  Avoid creating invalid range with minlen
1440         larger than maxlen.  Formatting fix.
1441
1442 2024-01-29  Richard Biener  <rguenther@suse.de>
1443
1444         PR debug/103047
1445         * tree-inline.cc (initialize_inlined_parameters): Reverse
1446         the decl chain of inlined parameters.
1447
1448 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
1449
1450         * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
1451         alignment of CFString constants by setting DECL_USER_ALIGN.
1452
1453 2024-01-28  Iain Sandoe  <iain@sandoe.co.uk>
1454             Jakub Jelinek   <jakub@redhat.com>
1455
1456         PR libgcc/113402
1457         * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
1458         and BUILT_IN_GCC_NESTED_PTR_DELETED.
1459         * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
1460         BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
1461         rename the library fallbacks to __gcc_nested_func_ptr_created and
1462         __gcc_nested_func_ptr_deleted.
1463         * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
1464         and __gcc_nested_func_ptr_deleted.
1465         * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
1466         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
1467         * tree.cc (build_common_builtin_nodes): Build the
1468         BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
1469         builtins only for non-explicit.
1470
1471 2024-01-28  YunQiang Su  <syq@gcc.gnu.org>
1472
1473         * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
1474
1475 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
1476
1477         PR target/38534
1478         * config/i386/i386-options.cc (ix86_set_func_type): Don't
1479         save and restore callee saved registers for a noreturn function
1480         with nothrow or compiled with -fno-exceptions.
1481
1482 2024-01-27  H.J. Lu  <hjl.tools@gmail.com>
1483
1484         PR target/103503
1485         PR target/113312
1486         * config/i386/i386-expand.cc (ix86_expand_call): Replace
1487         no_caller_saved_registers check with call_saved_registers check.
1488         Clobber all registers that are not used by the callee with
1489         no_callee_saved_registers attribute.
1490         * config/i386/i386-options.cc (ix86_set_func_type): Set
1491         call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
1492         noreturn function.  Disallow no_callee_saved_registers with
1493         interrupt or no_caller_saved_registers attributes together.
1494         (ix86_set_current_function): Replace no_caller_saved_registers
1495         check with call_saved_registers check.
1496         (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
1497         (ix86_handle_call_saved_registers_attribute): This.
1498         (ix86_gnu_attributes): Add
1499         ix86_handle_call_saved_registers_attribute.
1500         * config/i386/i386.cc (ix86_conditional_register_usage): Replace
1501         no_caller_saved_registers check with call_saved_registers check.
1502         (ix86_function_ok_for_sibcall): Don't allow callee with
1503         no_callee_saved_registers attribute when the calling function
1504         has callee-saved registers.
1505         (ix86_comp_type_attributes): Also check
1506         no_callee_saved_registers.
1507         (ix86_epilogue_uses): Replace no_caller_saved_registers check
1508         with call_saved_registers check.
1509         (ix86_hard_regno_scratch_ok): Likewise.
1510         (ix86_save_reg): Replace no_caller_saved_registers check with
1511         call_saved_registers check.  Don't save any registers for
1512         TYPE_NO_CALLEE_SAVED_REGISTERS.  Save all registers with
1513         TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
1514         no_callee_saved_registers attribute is called.
1515         (find_drap_reg): Replace no_caller_saved_registers check with
1516         call_saved_registers check.
1517         * config/i386/i386.h (call_saved_registers_type): New enum.
1518         (machine_function): Replace no_caller_saved_registers with
1519         call_saved_registers.
1520         * doc/extend.texi: Document no_callee_saved_registers attribute.
1521
1522 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
1523
1524         PR tree-optimization/113614
1525         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
1526         widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
1527         TRUNC_MOD_EXPR or FLOAT_EXPR uses.
1528
1529 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
1530
1531         PR tree-optimization/113568
1532         * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
1533         For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
1534         in the widening extension checks.
1535
1536 2024-01-27  Jakub Jelinek  <jakub@redhat.com>
1537
1538         * gimple-lower-bitint.cc (gimple_lower_bitint): For
1539         TDF_DETAILS dump mapping of SSA_NAMEs to decls.
1540
1541 2024-01-26  Hans-Peter Nilsson  <hp@axis.com>
1542
1543         * cgraphunit.cc (process_function_and_variable_attributes): Tweak
1544         the warning for an attribute-always_inline without inline declaration.
1545
1546 2024-01-26  Robin Dapp  <rdapp@ventanamicro.com>
1547
1548         PR other/113575
1549         * genopinit.cc (main): Split init_all_optabs into functions
1550         of 1000 patterns each.
1551
1552 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
1553
1554         * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
1555         TM_MULTILIB_CONFIG.
1556         * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
1557         * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
1558         -march/-mtune.
1559
1560 2024-01-26  Andrew Stubbs  <ams@baylibre.com>
1561
1562         * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
1563         * config/gcn/gcn-valu.md (all_convert): New iterator.
1564         (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
1565         define_expand, and rename the old one to ...
1566         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
1567         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
1568         (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
1569         (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
1570         * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
1571         (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
1572         * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
1573         (<u>mulqihi3_scalar): Likewise.
1574
1575 2024-01-26  Richard Biener  <rguenther@suse.de>
1576
1577         PR tree-optimization/113602
1578         * tree-data-ref.cc (dr_analyze_innermost): Fail when
1579         the base object isn't addressable.
1580
1581 2024-01-26  Tobias Burnus  <tburnus@baylibre.com>
1582
1583         * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
1584         "--amdhsa-code-object-version=" argument.
1585         (ASM_SPEC): Use it; replace previous version of it.
1586
1587 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1588
1589         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
1590         (pre_vsetvl::emit_vsetvl): Ditto.
1591
1592 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
1593
1594         * config/loongarch/lasx.md (vec_extract<mode>_0):
1595         New define_insn_and_split patten.
1596
1597 2024-01-26  Jiahao Xu  <xujiahao@loongson.cn>
1598
1599         * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
1600
1601 2024-01-26  Li Wei  <liwei@loongson.cn>
1602
1603         * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
1604
1605 2024-01-26  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1606
1607         PR target/113469
1608         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
1609
1610 2024-01-26  Andrew Pinski  <quic_apinski@quicinc.com>
1611
1612         PR target/100212
1613         * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
1614         undefined shift after the call to exact_log2.
1615
1616 2024-01-25  Andrew Pinski  <quic_apinski@quicinc.com>
1617
1618         PR target/100204
1619         * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
1620         before taking the negative of it.
1621
1622 2024-01-25  Vladimir N. Makarov  <vmakarov@redhat.com>
1623
1624         PR target/113526
1625         * lra-constraints.cc (curr_insn_transform): Change class even for
1626         spilled pseudo successfully matched with with NO_REGS.
1627
1628 2024-01-25  Georg-Johann Lay  <avr@gjlay.de>
1629
1630         PR target/113601
1631         * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
1632
1633 2024-01-25  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1634
1635         PR target/112987
1636         * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
1637         (aarch64_expand_epilogue): Use the new function.
1638         (aarch64_split_compare_and_swap): Likewise.
1639         (aarch64_split_atomic_op): Likewise.
1640
1641 2024-01-25  Robin Dapp  <rdapp.gcc@gmail.com>
1642
1643         PR middle-end/112971
1644         * fold-const.cc (simplify_const_binop): New function for binop
1645         simplification of two constant vectors when element-wise
1646         handling is not necessary.
1647         (const_binop): Call new function.
1648
1649 2024-01-25  Mary Bennett  <mary.bennett@embecosm.com>
1650
1651         * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
1652         * config/riscv/constraints.md: Likewise.
1653         * config/riscv/corev.def: Likewise.
1654         * config/riscv/corev.md: Likewise.
1655         * config/riscv/predicates.md: Likewise.
1656         * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
1657         * config/riscv/riscv-ftypes.def: Likewise.
1658         * config/riscv/riscv.opt: Likewise.
1659         * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
1660         * doc/extend.texi: Add XCVbitmanip builtin documentation.
1661         * doc/sourcebuild.texi: Likewise.
1662
1663 2024-01-25  Tobias Burnus  <tburnus@baylibre.com>
1664
1665         * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
1666
1667 2024-01-25  Yanzhang Wang  <yanzhang.wang@intel.com>
1668
1669         PR target/113538
1670         * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
1671         (riscv_fntype_abi): Ditto.
1672         * config/riscv/riscv.opt: Ditto.
1673
1674 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
1675
1676         PR middle-end/113574
1677         * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
1678         count against TYPE_PRECISION rather than TYPE_SIZE.
1679
1680 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
1681
1682         PR target/113572
1683         * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
1684         Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
1685
1686 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
1687
1688         PR target/113550
1689         * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
1690         whether each split instruction is a load that clobbers the source
1691         address.  Emit that instruction last if so.
1692
1693 2024-01-25  Richard Sandiford  <richard.sandiford@arm.com>
1694
1695         PR target/113485
1696         * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
1697         pattern.
1698         (<optab><Vnarrowq><mode>2): Use it instead of generating a
1699         paradoxical subreg for the input.
1700
1701 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1702
1703         * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
1704         (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
1705         predecessors dump information.
1706
1707 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1708
1709         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
1710         redundant full available computation.
1711         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
1712
1713 2024-01-25  Jakub Jelinek  <jakub@redhat.com>
1714
1715         * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
1716         * doc/rtl.texi (CONST_VECTOR): Likewise.
1717
1718 2024-01-25  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1719
1720         * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
1721         * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
1722         (pass_vsetvl::execute): Ditto.
1723         * config/riscv/riscv.opt: Ditto.
1724
1725 2024-01-25  Jiahao Xu  <xujiahao@loongson.cn>
1726
1727         * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
1728         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
1729
1730 2024-01-25  Richard Biener  <rguenther@suse.de>
1731
1732         PR tree-optimization/113576
1733         * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
1734         exits with may_be_zero niters when its the last one.
1735
1736 2024-01-25  Lulu Cheng  <chenglulu@loongson.cn>
1737
1738         * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
1739         For symbols of type tls, non-zero Offset is not generated.
1740
1741 2024-01-25  Haochen Gui  <guihaoc@gcc.gnu.org>
1742
1743         * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
1744         P9 with m32 and mpowerpc64.
1745
1746 2024-01-25  liuhongt  <hongtao.liu@intel.com>
1747
1748         * config/i386/i386-options.cc (ix86_option_override_internal):
1749         Enable -mlam=u57 by default when compiled with
1750         -fsanitize=hwaddress.
1751
1752 2024-01-25  Palmer Dabbelt  <palmer@rivosinc.com>
1753
1754         * common/config/riscv/riscv-common.cc (riscv_implied_info):
1755         Remove {"ztso", "a"}.
1756
1757 2024-01-24  Martin Jambor  <mjambor@suse.cz>
1758
1759         PR ipa/108007
1760         PR ipa/112616
1761         * cgraph.h (cgraph_edge): Add a parameter to
1762         redirect_call_stmt_to_callee.
1763         * ipa-param-manipulation.h (ipa_param_adjustments): Add a
1764         parameter to modify_call.
1765         (ipa_release_ssas_in_hash): Declare.
1766         * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
1767         parameter killed_ssas, pass it to padjs->modify_call.
1768         * ipa-param-manipulation.cc (purge_all_uses): New function.
1769         (ipa_param_adjustments::modify_call): New parameter killed_ssas.
1770         Instead of substituting uses, invoke purge_all_uses.  If
1771         hash of killed SSAs has not been provided, create a temporary one
1772         and release SSAs that have been added to it.
1773         (compare_ssa_versions): New function.
1774         (ipa_release_ssas_in_hash): Likewise.
1775         * tree-inline.cc (redirect_all_calls): Create
1776         id->killed_new_ssa_names earlier, pass it to edge redirection,
1777         adjust a comment.
1778         (copy_body): Release SSAs in id->killed_new_ssa_names.
1779
1780 2024-01-24  Andrew Pinski  <quic_apinski@quicinc.com>
1781
1782         PR target/113486
1783         * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
1784         TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
1785
1786 2024-01-24  Monk Chiang  <monk.chiang@sifive.com>
1787
1788         PR target/113095
1789         * config/riscv/sfb.md: New splitters to rewrite single bit
1790         sign extension as the condition to SFB instructions.
1791
1792 2024-01-24  Jan Hubicka  <jh@suse.cz>
1793
1794         PR middle-end/88345
1795         * common.opt: (flimit-function-alignment): Reorder alphabeticaly
1796         (fmin-function-alignment): New parameter.
1797         * doc/invoke.texi: (-fmin-function-alignment): Document.
1798         (-falign-functions,-falign-loops,-falign-labels): Mention that
1799         aglinments are ignored in cold code.
1800         * varasm.cc (assemble_start_function): Handle min-function-alignment.
1801
1802 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
1803
1804         PR target/109636
1805         * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
1806         mulv2di3): Remove.
1807         * config/aarch64/iterators.md (VQDIV): Remove.
1808         (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
1809         SVE_I_SIMD_DI): New.
1810         (VPRED, sve_lane_con): Add V4SI and V2DI.
1811         * config/aarch64/aarch64-sve.md (<optab><mode>3,
1812         @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
1813         (mul<mode>3): New, split from <optab><mode>3.
1814         (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
1815         * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
1816         *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
1817         SVE_FULL_HSDI_SIMD_DI.
1818
1819 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
1820
1821         PR tree-optimization/113552
1822         * config/aarch64/aarch64.cc
1823         (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
1824
1825 2024-01-24  Martin Jambor  <mjambor@suse.cz>
1826
1827         PR ipa/113490
1828         * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
1829         count is equal or greater than the limit.  Use the limit from the
1830         callee.
1831
1832 2024-01-24  YunQiang Su  <syq@gcc.gnu.org>
1833
1834         * configure.ac: Detect the explicit relocs support for
1835         mips, and define C macro MIPS_EXPLICIT_RELOCS.
1836         * config.in: Regenerated.
1837         * configure: Regenerated.
1838         * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
1839         * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
1840         * config/mips/mips.cc(mips_set_compression_mode): Sorry if
1841         !TARGET_EXPLICIT_RELOCS instead of just set it.
1842         * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
1843         TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
1844         * config/mips/mips.opt: Introduce -mexplicit-relocs= option
1845         and define -m(no-)explicit-relocs as aliases.
1846
1847 2024-01-24  Alex Coplan  <alex.coplan@arm.com>
1848
1849         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
1850         to 1.
1851         (-mlate-ldp-fusion): Likewise.
1852
1853 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
1854
1855         * tree-vect-loop.cc (vect_get_vect_def,
1856         vect_create_epilog_for_reduction): Rename main_exit_p to
1857         last_val_reduc_p.
1858
1859 2024-01-24  Tamar Christina  <tamar.christina@arm.com>
1860
1861         PR tree-optimization/113364
1862         * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
1863         early exits then we must reduce from the first offset for all of them.
1864
1865 2024-01-24  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
1866
1867         PR target/113495
1868         * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
1869         (get_regno): Ditto.
1870         (get_bb_index): Ditto.
1871         (pre_vsetvl::compute_avl_def_data): Ditto.
1872         (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
1873         (pre_vsetvl::pre_global_vsetvl_info): Ditto.
1874
1875 2024-01-23  Andrew Pinski  <quic_apinski@quicinc.com>
1876             Richard Sandiford  <richard.sandiford@arm.com>
1877
1878         PR target/100942
1879         * ccmp.cc (ccmp_candidate_p): Add outer argument.
1880         Allow if the outer is true and the lhs is used more
1881         than once.
1882         (expand_ccmp_expr): Update call to ccmp_candidate_p.
1883         * expr.h (expand_expr_real_gassign): Declare.
1884         * expr.cc (expand_expr_real_gassign): New function, split out from...
1885         (expand_expr_real_1): ...here.
1886         * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
1887
1888 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
1889
1890         PR target/113089
1891         * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
1892         (fixup_debug_use): New.
1893         (fixup_debug_uses_trailing_add): New.
1894         (fixup_debug_uses): New. Use it ...
1895         (ldp_bb_info::fuse_pair): ... here.
1896         (try_promote_writeback): Call fixup_debug_uses_trailing_add to
1897         fix up debug uses of the base register that are affected by
1898         folding in the trailing add insn.
1899
1900 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
1901
1902         PR target/113089
1903         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
1904         Update trailing nondebug uses of the base register in the case
1905         of cancelling writeback.
1906
1907 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
1908
1909         PR target/113089
1910         * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
1911         (debug_insn_use_iterator): New.
1912         (set_info::first_debug_insn_use): New.
1913         (set_info::debug_insn_uses): New.
1914         * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
1915         (set_info::first_debug_insn_use): New.
1916         (set_info::debug_insn_uses): New.
1917
1918 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
1919
1920         PR target/113356
1921         * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
1922         Don't record hazards against the opposite insn in the pair.
1923
1924 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
1925
1926         PR target/113070
1927         * config/aarch64/aarch64-ldp-fusion.cc
1928         (struct stp_change_builder): New.
1929         (decide_stp_strategy): Reanme to ...
1930         (try_repurpose_store): ... this.
1931         (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
1932         construct stp changes.  Fix up uses when inserting new stp insns.
1933
1934 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
1935
1936         PR target/113070
1937         * rtl-ssa.h: Include hash-set.h.
1938         * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
1939         new_sets parameter and use it to keep track of new user-created sets.
1940         (function_info::apply_changes_to_insn): Also call add_def on new sets.
1941         (function_info::change_insns): Add hash_set to keep track of new
1942         user-created defs.  Plumb it through.
1943         * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
1944         apply_changes_to_insn.
1945
1946 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
1947
1948         PR target/113070
1949         * rtl-ssa/accesses.cc (function_info::create_use): New.
1950         * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
1951         Ensure new uses end up referring to permanent defs.
1952         * rtl-ssa/functions.h (function_info::create_use): Declare.
1953
1954 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
1955
1956         PR target/113070
1957         * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
1958         to finalize_new_accesses from the backwards placement loop, run it
1959         forwards in a separate loop.
1960
1961 2024-01-23  Richard Biener  <rguenther@suse.de>
1962
1963         PR tree-optimization/113552
1964         * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
1965         floor_log2 instead of exact_log2 on the number of calls.
1966
1967 2024-01-23  Jeff Law  <jlaw@ventanamicro.com>
1968             Jakub Jelinek  <jakub@redhat.com>
1969
1970         * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
1971         decl.
1972
1973 2024-01-23  Richard Biener  <rguenther@suse.de>
1974
1975         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
1976         Separate single and multi-exit case when creating PHIs between
1977         the main and epilogue.
1978
1979 2024-01-23  Richard Sandiford  <richard.sandiford@arm.com>
1980
1981         PR target/112989
1982         * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
1983         MODE_single variants of functions that don't take tuple arguments.
1984
1985 2024-01-23  Alex Coplan  <alex.coplan@arm.com>
1986
1987         PR target/113114
1988         * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
1989         Don't assert recog success, just punt if the writeback pair
1990         isn't recognized.
1991
1992 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
1993
1994         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
1995         ATTRIBUTE_UNUSED to decl.
1996
1997 2024-01-23  Richard Biener  <rguenther@suse.de>
1998
1999         PR debug/107058
2000         * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
2001         handle unexpected but bogus DIE contexts when not checking
2002         enabled.
2003
2004 2024-01-23  Jakub Jelinek  <jakub@redhat.com>
2005
2006         PR tree-optimization/113462
2007         * fold-const.cc (native_interpret_int): Don't punt if total_bytes
2008         is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
2009         (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
2010         sizes between 129 and 8192 bytes.
2011
2012 2024-01-23  Xi Ruoyao  <xry111@xry111.site>
2013
2014         * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
2015         If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
2016         for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
2017         (loongarch_call_tls_get_addr): Do not split symbols of
2018         SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
2019         EXPLICIT_RELOCS_AUTO.
2020
2021 2024-01-23  Richard Biener  <rguenther@suse.de>
2022
2023         * alias.cc (known_base_value_p): Remove.
2024         (find_base_value): Remove PLUS/MINUS handling
2025         when both operands are not CONST_INT_P.
2026
2027 2024-01-23  Richard Biener  <rguenther@suse.de>
2028
2029         PR rtl-optimization/113255
2030         * alias.cc (find_base_term): Remove PLUS/MINUS handling
2031         when both operands are not CONST_INT_P.
2032
2033 2024-01-23  Richard Biener  <rguenther@suse.de>
2034
2035         PR debug/112718
2036         * dwarf2out.cc (dwarf2out_finish): Reset all type units
2037         for the fat part of an LTO compile.
2038
2039 2024-01-23  chenxiaolong  <chenxiaolong@loongson.cn>
2040
2041         * doc/sourcebuild.texi: Add attributes for keywords.
2042
2043 2024-01-23  Sandra Loosemore  <sandra@codesourcery.com>
2044
2045         PR c++/90463
2046         * doc/invoke.texi (Warning Options): Correct lists of options
2047         enabled by -Wall and -Wextra by checking against common.opt
2048         and c-family/c.opt.
2049
2050 2024-01-22  Andrew Pinski  <quic_apinski@quicinc.com>
2051
2052         PR target/113030
2053         * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
2054         instead of cpu_optaliases.
2055         (check_arch): Use arch_opt_alias instead of arch_optaliases.
2056
2057 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2058
2059         * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
2060         * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
2061         * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
2062
2063 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2064
2065         PR target/109092
2066         * config/riscv/riscv.md: Use reg instead of subreg.
2067
2068 2024-01-22  Tobias Burnus  <tburnus@baylibre.com>
2069
2070         PR other/111966
2071         * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
2072         to match the compiler default.
2073         (simple_object_copy_lto_debug_sections): Never unlink the outfile
2074         on error as the caller does so.
2075         (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
2076         (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
2077
2078 2024-01-22  Richard Biener  <rguenther@suse.de>
2079
2080         PR tree-optimization/113373
2081         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2082         Create LC PHIs in the exit blocks where necessary.
2083         * tree-vect-loop.cc (vectorizable_live_operation): Do not try
2084         to handle missing LC PHIs.
2085         (find_connected_edge): Remove.
2086         (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
2087
2088 2024-01-22  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2089
2090         * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
2091
2092 2024-01-22  xuli  <xuli1@eswincomputing.com>
2093
2094         PR target/113420
2095         * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
2096         (registered_function::overloaded_hash):refactor.
2097         (resolve_overloaded_builtin):avoid internal ICE.
2098
2099 2024-01-21  Mikael Pettersson  <mikpelinux@gmail.com>
2100
2101         PR target/82420
2102         PR target/111279
2103         * calls.cc (emit_library_call_value_1): Pass valid TYPE
2104         to emit_push_insn.
2105         * expr.cc (emit_push_insn): Likewise.
2106
2107 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
2108
2109         * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
2110         correcction version of last change.
2111
2112 2024-01-21  Jeff Law  <jlaw@ventanamicro.com>
2113
2114         * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
2115         fix bugs in signature.
2116
2117 2024-01-21  Roger Sayle  <roger@nextmovesoftware.com>
2118             Richard Biener  <rguenther@suse.de>
2119
2120         PR rtl-optimization/111267
2121         * fwprop.cc (fwprop_propagation::profitabe_p): Rename
2122         profitable_p method to likely_profitable_p.
2123         (try_fwprop_subst_node): Update call to likely_profitable_p.
2124         Only bail-out early when !prop.likely_profitable_p for instructions
2125         that are not single sets.  When comparing costs, bail-out if the
2126         cost is unchanged and !prop.likely_profitable_p.
2127
2128 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
2129
2130         PR c++/90464
2131         * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
2132         isn't enabled by -Wunused unless -Wextra is provided, and that
2133         -Wunused does enable -Wunused-const-variable=1 for C.  Clarify that
2134         -Wunused doesn't enable -Wunused-* options documented as behaving
2135         otherwise, and list them explicitly.
2136
2137 2024-01-21  Sandra Loosemore  <sandra@codesourcery.com>
2138
2139         PR c/109708
2140         * doc/invoke.texi (Warning Options): Fix broken example and
2141         clean up/reorganize the others.  Also describe what the short-form
2142         options mean.
2143
2144 2024-01-20  Sandra Loosemore  <sandra@codesourcery.com>
2145
2146         PR c/102998
2147         * doc/invoke.texi (Option Summary): Add -Warray-parameter.
2148         (Warning Options): Correct/edit discussion of -Warray-parameter
2149         to make the first example less confusing, and fill in missing info.
2150
2151 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
2152
2153         PR tree-optimization/113462
2154         * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
2155         Handle rhs1 INTEGER_CST like SSA_NAME.
2156
2157 2024-01-20  Jakub Jelinek  <jakub@redhat.com>
2158
2159         PR tree-optimization/113491
2160         * tree-switch-conversion.cc (switch_conversion::build_constructors):
2161         If elt.index has precision higher than sizetype, fold_convert it to
2162         sizetype.
2163         (switch_conversion::array_value_type): Return type if type is
2164         BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
2165         (switch_conversion::build_arrays): Use unsigned_type_for rather than
2166         lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
2167         above MAX_FIXED_MODE_SIZE or with BLKmode.  If utype has precision
2168         higher than sizetype, use sizetype as tidx type and fold_convert the
2169         subtraction to sizetype.
2170
2171 2024-01-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2172
2173         * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
2174         (riscv_vector_mode_supported_any_target_p): Ditto.
2175
2176 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
2177
2178         PR target/110934
2179         * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
2180         (TARGET_ZERO_CALL_USED_REGS): Define.
2181
2182 2024-01-19  Mikael Pettersson  <mikpelinux@gmail.com>
2183
2184         PR target/108640
2185         * config/m68k/m68k.cc (output_andsi3): Use QImode for
2186         address adjusted for 1-byte RMW access.
2187         (output_iorsi3): Likewise.
2188         (output_xorsi3): Likewise.
2189
2190 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
2191
2192         * doc/invoke.texi (RISC-V Options): Add list of supported
2193         extensions.
2194
2195 2024-01-19  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2196
2197         PR target/113495
2198         * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
2199         (RVV_VUNDEF): Ditto.
2200         * config/riscv/riscv-vsetvl.cc: Add timevar.
2201
2202 2024-01-19  Richard Biener  <rguenther@suse.de>
2203
2204         PR debug/113488
2205         * lto-streamer-in.cc (lto_read_tree_1): When there isn't
2206         an early DIE but there should be, do not pretend there is.
2207
2208 2024-01-19  Richard Biener  <rguenther@suse.de>
2209
2210         PR tree-optimization/113494
2211         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2212         Handle endless loop on exit.  Handle re-allocated PHI.
2213
2214 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
2215
2216         PR tree-optimization/113464
2217         * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
2218         optimize loads into GIMPLE_ASM stmts.
2219
2220 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
2221
2222         PR tree-optimization/113463
2223         * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
2224         Only look through NOP_EXPRs if rhs1 doesn't have wider type than
2225         lhs.
2226
2227 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
2228
2229         PR tree-optimization/113459
2230         * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
2231         TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
2232         of SCALAR_INT_TYPE_MODE if type has BLKmode.
2233         (vn_reference_lookup_3): Likewise.  Formatting fix.
2234
2235 2024-01-19  Jakub Jelinek  <jakub@redhat.com>
2236             Richard Biener  <rguenther@suse.de>
2237
2238         * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
2239         VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
2240         * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
2241         but adjust_address also for BLKmode mode and MEM op0.
2242
2243 2024-01-19  Palmer Dabbelt  <palmer@rivosinc.com>
2244
2245         * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
2246         extensions.
2247
2248 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
2249
2250         * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
2251
2252 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
2253
2254         * common/config/riscv/riscv-common.cc
2255         (riscv_subset_list::parse_std_ext): Remove.
2256         (riscv_subset_list::parse_multiletter_ext): Remove.
2257         * config/riscv/riscv-subset.h
2258         (riscv_subset_list::parse_std_ext): Remove.
2259         (riscv_subset_list::parse_multiletter_ext): Remove.
2260
2261 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
2262
2263         * common/config/riscv/riscv-common.cc
2264         (riscv_subset_list::parse_single_std_ext): New parameter.
2265         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
2266         (riscv_subset_list::parse_single_ext): Ditto.
2267         (riscv_subset_list::parse): Relax the order for the input of ISA
2268         string.
2269         * config/riscv/riscv-subset.h
2270         (riscv_subset_list::parse_single_std_ext): New parameter.
2271         (riscv_subset_list::parse_single_multiletter_ext): Ditto.
2272         (riscv_subset_list::parse_single_ext): Ditto.
2273
2274 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
2275
2276         * common/config/riscv/riscv-common.cc
2277         (riscv_subset_list::parse_base_ext): New.
2278         (riscv_subset_list::parse): Extract part of logic into
2279         riscv_subset_list::parse_base_ext.
2280         * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
2281         New.
2282
2283 2024-01-19  Kito Cheng  <kito.cheng@sifive.com>
2284
2285         * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
2286         sorry message.
2287
2288 2024-01-19  Kuan-Lin Chen  <rufus@andestech.com>
2289
2290         * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
2291         UNSPEC_CLMUL_VC.
2292
2293 2024-01-19  Sandra Loosemore  <sandra@codesourcery.com>
2294
2295         PR c/110029
2296         * doc/extend.texi (Common Variable Attributes): Explain what
2297         happens when multiple variables with cleanups are in the same scope.
2298
2299 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
2300
2301         PR ipa/108470
2302         * doc/extend.texi (Common Function Attributes): Document that
2303         noinline also disables some interprocedural optimizations and
2304         improve flow to the part about using inline asm instead to
2305         disable calls from being optimized away completely.  Remove the
2306         sentence that says noipa is mainly for internal compiler testing.
2307
2308 2024-01-18  John David Anglin  <danglin@gcc.gnu.org>
2309
2310         PR tree-optimization/69807
2311         * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
2312
2313 2024-01-18  Brian Inglis  <Brian.Inglis@Shaw.ca>
2314
2315         PR target/108521
2316         * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
2317         from x86 Windows Options.
2318
2319 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
2320
2321         PR c/107942
2322         * doc/extend.texi (C Extensions): Add new section to menu.
2323         (Function Attributes):  Move dangling index entries to....
2324         (Const and Volatile Functions): New section.
2325
2326 2024-01-18  David Malcolm  <dmalcolm@redhat.com>
2327
2328         PR middle-end/112684
2329         * toplev.cc (toplev::main): Don't ICE in
2330         -fdiagnostics-generate-patch when exiting after options,
2331         since no edit context will have been created.
2332
2333 2024-01-18  Richard Biener  <rguenther@suse.de>
2334
2335         * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
2336         operands vector.
2337
2338 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
2339
2340         * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
2341         when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
2342
2343 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
2344             Jin Ma  <jinma@linux.alibaba.com>
2345             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
2346             Christoph Müllner  <christoph.muellner@vrull.eu>
2347
2348         * config/riscv/thead.cc
2349         (th_asm_output_opcode): Rewrite some instructions.
2350
2351 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
2352             Jin Ma  <jinma@linux.alibaba.com>
2353             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
2354             Christoph Müllner  <christoph.muellner@vrull.eu>
2355
2356         * config/riscv/riscv.md (none,thv,rvv): New attribute.
2357         (no,yes): Add an attribute to disable alternative
2358         for xtheadvector or RVV1.0.
2359         * config/riscv/vector.md:
2360         Disable alternatives that destination register overlaps
2361         source register group for xtheadvector.
2362
2363 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
2364             Jin Ma  <jinma@linux.alibaba.com>
2365             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
2366             Christoph Müllner  <christoph.muellner@vrull.eu>
2367
2368         * config/riscv/riscv-vector-builtins-bases.cc
2369         (class th_loadstore_width): Define new builtin bases.
2370         (class th_extract): Define new builtin bases.
2371         (BASE): Define new builtin bases.
2372         * config/riscv/riscv-vector-builtins-bases.h:
2373         Define new builtin class.
2374         * config/riscv/riscv-vector-builtins-shapes.cc
2375         (struct th_loadstore_width_def): Define new builtin shapes.
2376         (struct th_indexed_loadstore_width_def):
2377         Define new builtin shapes.
2378         (struct th_extract_def): Define new builtin shapes.
2379         (SHAPE): Define new builtin shapes.
2380         * config/riscv/riscv-vector-builtins-shapes.h:
2381         Define new builtin shapes.
2382         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
2383         Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
2384         * config/riscv/riscv-vector-builtins.h
2385         (enum required_ext): Add new XTheadVector member.
2386         (struct function_group_info): Likewise.
2387         * config/riscv/t-riscv:
2388         Add thead-vector-builtins-functions.def
2389         * config/riscv/thead-vector.md
2390         (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
2391         (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
2392         (@pred_store_width<vlmem_op_attr><mode>): Likewise.
2393         (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
2394         (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
2395         (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
2396         (@pred_th_extract<mode>): Likewise.
2397         (*pred_th_extract<mode>): Likewise.
2398         * config/riscv/thead-vector-builtins-functions.def: New file.
2399
2400 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
2401             Jin Ma  <jinma@linux.alibaba.com>
2402             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
2403             Christoph Müllner  <christoph.muellner@vrull.eu>
2404
2405         * config.gcc:  Add files for XTheadVector intrinsics.
2406         * config/riscv/autovec.md: Guard XTheadVector.
2407         * config/riscv/predicates.md: Disable immediate vl
2408         for XTheadVector.
2409         * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
2410         Add pragma for XTheadVector.
2411         * config/riscv/riscv-string.cc (riscv_expand_block_move):
2412         Guard XTheadVector.
2413         * config/riscv/riscv-v.cc (vls_mode_valid_p):
2414         Avoid autovec.
2415         * config/riscv/riscv-vector-builtins-bases.cc:
2416         Do not normalize vsetvl instructions for XTheadVector.
2417         * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
2418         New check type function.
2419         (build_one): Adjust for XTheadVector.
2420         * config/riscv/riscv-vector-switch.def (ENTRY):
2421         Disable fractional mode for the XTheadVector extension.
2422         (TUPLE_ENTRY): Likewise.
2423         * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
2424         Guard XTheadVector.
2425         (riscv_preferred_simd_mode): Likewsie.
2426         (riscv_autovectorize_vector_modes): Likewise.
2427         (riscv_vector_mode_supported_any_target_p): Likewise.
2428         (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
2429         * config/riscv/thead.cc (th_asm_output_opcode):
2430         Rewrite vsetvl instructions.
2431         * config/riscv/vector.md:
2432         Include thead-vector.md and change fractional LMUL
2433         into 1 for vbool.
2434         * config/riscv/riscv_th_vector.h: New file.
2435         * config/riscv/thead-vector.md: New file.
2436
2437 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
2438             Jin Ma  <jinma@linux.alibaba.com>
2439             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
2440             Christoph Müllner  <christoph.muellner@vrull.eu>
2441
2442         * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
2443         Add new function to add assembler insn code prefix/suffix.
2444         (th_asm_output_opcode):
2445         Add Thead function to add assembler insn code prefix/suffix.
2446         * config/riscv/riscv.cc (riscv_asm_output_opcode):
2447         Implement function to add assembler insn code prefix/suffix.
2448         * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
2449         Add new function to add assembler insn code prefix/suffix.
2450         * config/riscv/thead.cc (th_asm_output_opcode):
2451         Implement Thead function to add assembler insn code
2452         prefix/suffix.
2453
2454 2024-01-18  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
2455             Jin Ma  <jinma@linux.alibaba.com>
2456             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
2457             Christoph Müllner  <christoph.muellner@vrull.eu>
2458
2459         * common/config/riscv/riscv-common.cc
2460         (riscv_subset_list::parse): Add new vendor extension.
2461         * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
2462         Add test marco.
2463         * config/riscv/riscv.opt:  Add new mask.
2464
2465 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
2466
2467         * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
2468         to be conditional on macosx-version-min.
2469
2470 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
2471
2472         * config/darwin.cc (darwin_objc1_section): Use the correct
2473         meta-data version for constant strings.
2474         (machopic_select_section): Assert if we fail to handle CFString
2475         sections as Obejctive-C meta-data or drectly.
2476
2477 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
2478
2479         * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
2480         OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
2481         OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
2482         versions when the object format is Mach-O.
2483
2484 2024-01-18  Iain Sandoe  <iain@sandoe.co.uk>
2485
2486         PR target/105522
2487         * config/darwin.cc (machopic_select_section): Handle C and C++
2488         CFStrings.
2489         (darwin_rename_builtins): Move this out of the CFString code.
2490         (darwin_libc_has_function): Likewise.
2491         (darwin_build_constant_cfstring): Create an anonymous var to
2492         hold each CFString.
2493         * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
2494         CFstrings.
2495
2496 2024-01-18  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
2497
2498         PR bootstrap/113445
2499         * haifa-sched.cc (dep_list_size): Make global.
2500         * sched-deps.cc (find_inc): Use instead of sd_lists_size().
2501         * sched-int.h (dep_list_size): Declare.
2502
2503 2024-01-18  Martin Jambor  <mjambor@suse.cz>
2504
2505         PR tree-optimization/110422
2506         * tree-sra.cc (scan_function): Disqualify bases of operands of asm
2507         gotos.
2508
2509 2024-01-18  Richard Biener  <rguenther@suse.de>
2510
2511         PR tree-optimization/113475
2512         * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
2513         * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
2514         (phi_analyzer::~phi_analyzer): Deallocate and free collected
2515         phi_grous.
2516         (phi_analyzer::process_phi): Record allocated phi_groups.
2517
2518 2024-01-18  Richard Biener  <rguenther@suse.de>
2519
2520         * tree-vect-stmts.cc (vectorizable_store): Do not allocate
2521         storage for gvec_oprnds elements.
2522
2523 2024-01-18  Richard Biener  <rguenther@suse.de>
2524
2525         * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
2526         prefer all later exits we can handle.
2527         (vect_analyze_loop_form): Free the allocated loop body.
2528         Adjust comments.
2529
2530 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
2531
2532         * config/avr/avr-log.cc: Tabify.
2533
2534 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2535
2536         * config/riscv/autovec.md: Support vi variant.
2537
2538 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
2539
2540         * config/avr/avr-devices.cc: Tabify.
2541
2542 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
2543
2544         * config/avr/avr-c.cc: Tabify.
2545
2546 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
2547
2548         * config/avr/driver-avr.cc: Tabify.
2549
2550 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
2551
2552         * config/avr/gen-avr-mmcu-texi.cc: Tabify.
2553
2554 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
2555
2556         * config/avr/gen-avr-mmcu-specs.cc: Tabify.
2557
2558 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
2559
2560         * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
2561         minline-strcmp, minline-strncmp, minline-strlen,
2562         -param=riscv-vector-abi): Remove Bool keywords.
2563
2564 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
2565
2566         PR target/113122
2567         * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
2568         support.  Add missing space after , in emitted assembly in some
2569         cases.  Formatting fixes.
2570
2571 2024-01-18  Xi Ruoyao  <xry111@xry111.site>
2572
2573         * config/loongarch/loongarch.md (movsi_internal): Remove
2574         constraint z.
2575
2576 2024-01-18  Georg-Johann Lay  <avr@gjlay.de>
2577
2578         * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
2579         in the diagnostic, and capitalize the device name.
2580         (print_mcu): Generate specs such that:
2581         <*check_rodata_in_ram>: New.
2582         <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
2583         <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
2584         <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
2585
2586 2024-01-18  Jakub Jelinek  <jakub@redhat.com>
2587
2588         PR other/113399
2589         * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
2590         Common and Optimization.
2591
2592 2024-01-18  Richard Biener  <rguenther@suse.de>
2593
2594         PR tree-optimization/113431
2595         * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
2596         When there is an invariant load we might not preserve
2597         scalar order.
2598
2599 2024-01-18  Richard Biener  <rguenther@suse.de>
2600
2601         PR tree-optimization/113374
2602         * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
2603         * tree-vect-loop.cc (move_early_exit_stmts): Update
2604         virtual LC PHIs.
2605         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2606         Refactor.  Preserve virtual LC PHIs on all exits.
2607
2608 2024-01-18  Lulu Cheng  <chenglulu@loongson.cn>
2609
2610         * config/loongarch/loongarch.cc (loongarch_split_symbol):
2611         Assign the '/u' attribute to the mem.
2612
2613 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
2614
2615         PR middle-end/110847
2616         * doc/invoke.texi (Option Summary): Document negative forms of
2617         -Wtsan and -Wxor-used-as-pow.
2618         (Warning Options): Likewise.
2619
2620 2024-01-18  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2621
2622         PR target/113429
2623         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
2624
2625 2024-01-18  Sandra Loosemore  <sandra@codesourcery.com>
2626
2627         * doc/extend.texi (Common Function Attributes): Re-alphabetize
2628         the table.
2629         (Common Variable Attributes): Likewise.
2630         (Common Type Attributes): Likewise.
2631
2632 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
2633
2634         PR middle-end/111659
2635         * doc/extend.texi (Common Variable Attributes): Fix long lines
2636         in documentation of strict_flex_array + other minor copy-editing.
2637         Add a cross-reference to -Wstrict-flex-arrays.
2638         * doc/invoke.texi (Option Summary): Fix whitespace in tables
2639         before -fstrict-flex-arrays and -Wstrict-flex-arrays.
2640         (C Dialect Options): Combine the docs for the two
2641         -fstrict-flex-arrays forms into a single entry.  Note this option
2642         is for C/C++ only.  Add a cross-reference to -Wstrict-flex-arrays.
2643         (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
2644         Minor copy-editing.  Add cross references to the strict_flex_array
2645         attribute and -fstrict-flex-arrays option.  Add note that this
2646         option depends on -ftree-vrp.
2647
2648 2024-01-17  Andrew Pinski  <quic_apinski@quicinc.com>
2649
2650         PR target/113221
2651         * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
2652         only allow REG operands instead of allowing all.
2653
2654 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
2655
2656         * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
2657         Remove redundant checks in else condition for readablity.
2658         (earliest_fuse_vsetvl_info) Print iteration count in debug
2659         prints.
2660         (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
2661         dump details in certain cases.
2662
2663 2024-01-17  Vineet Gupta  <vineetg@rivosinc.com>
2664
2665         * config/riscv/riscv.opt: New -param=vsetvl-strategy.
2666         * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
2667         * config/riscv/riscv-vsetvl.cc
2668         (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
2669         (pass_vsetvl::execute): Use vsetvl_strategy.
2670
2671 2024-01-17  Jan Hubicka  <jh@suse.cz>
2672
2673         * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
2674         accidental hack reseting offset.
2675
2676 2024-01-17  Jan Hubicka  <jh@suse.cz>
2677
2678         * config/i386/i386-options.cc (ix86_option_override_internal): Fix
2679         handling of X86_TUNE_AVOID_512FMA_CHAINS.
2680
2681 2024-01-17  Jan Hubicka  <jh@suse.cz>
2682             Jakub Jelinek  <jakub@redhat.com>
2683
2684         PR tree-optimization/110852
2685         * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
2686         binary operations
2687         (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
2688         PRED_COMBINED_VALUE_PREDICTIONS_PHI
2689         * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
2690         (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
2691
2692 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
2693
2694         PR tree-optimization/113421
2695         * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
2696         comment.
2697         (bitint_dom_walker::before_dom_children): Add g temporary to simplify
2698         formatting.  Start at vop rather than cvop even if stmt is a store
2699         and needs_operand_addr.
2700
2701 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
2702
2703         PR middle-end/113410
2704         * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
2705         If access_nelts is integral with larger precision than sizetype,
2706         fold_convert it to sizetype.
2707
2708 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
2709
2710         PR tree-optimization/113408
2711         * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
2712         VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
2713         to handle_cast.
2714
2715 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
2716
2717         PR middle-end/113406
2718         * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
2719         regardless of whether is_gimple_reg_type (restype) or not.
2720
2721 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
2722
2723         * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
2724         funcions -> functions, and use were instead of was.
2725         * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
2726         and guaranteee -> guarantee.
2727         * attribs.h (struct attr_access): Fix comment typo funcion -> function.
2728
2729 2024-01-17  Jakub Jelinek  <jakub@redhat.com>
2730
2731         PR middle-end/113409
2732         * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
2733         INTEGER_TYPE.
2734         (omp_extract_for_data): Use build_bitint_type rather than
2735         build_nonstandard_integer_type if either iter_type or loop->v type
2736         is BITINT_TYPE.
2737         * omp-expand.cc (expand_omp_for_generic,
2738         expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
2739         BITINT_TYPE like INTEGER_TYPE.
2740
2741 2024-01-17  Richard Biener  <rguenther@suse.de>
2742
2743         PR tree-optimization/113371
2744         * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
2745         Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
2746         * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
2747         not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
2748
2749 2024-01-17  Maxim Kuvyrkov  <maxim.kuvyrkov@linaro.org>
2750
2751         PR rtl-optimization/96388
2752         PR rtl-optimization/111554
2753         * sched-deps.cc (find_inc): Avoid exponential behavior.
2754
2755 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
2756
2757         PR c/111693
2758         * doc/invoke.texi (Option Summary): Move -Wuseless-cast
2759         from C++ Language Options to Warning Options.  Add entry for
2760         -Wuse-after-free.
2761         (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
2762         from here....
2763         (Warning Options): ...to here.  Minor copy-editing to fix typo
2764         and grammar.
2765
2766 2024-01-17  YunQiang Su  <syq@gcc.gnu.org>
2767
2768         * config/mips/mips.cc (mips_compute_frame_info): If another
2769         register is used as global_pointer, mark $GP live false.
2770
2771 2024-01-17  Sandra Loosemore  <sandra@codesourcery.com>
2772
2773         PR target/112973
2774         * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
2775         give the section a light copy-editing pass.
2776
2777 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
2778
2779         * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
2780         * config/aarch64/aarch64-tune.md: Regenerated.
2781         * doc/invoke.texi (-mcpu): Add cobalt-100 core.
2782
2783 2024-01-16  Wilco Dijkstra  <wilco.dijkstra@arm.com>
2784
2785         PR target/112573
2786         * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
2787         badly formed CONST expressions.
2788
2789 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
2790
2791         * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
2792
2793 2024-01-16  Daniel Cederman  <cederman@gaisler.com>
2794
2795         * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
2796         * config/sparc/sync.md (membar_storeload): Turn into named insn
2797         and add GR712RC errata workaround.
2798         (membar_v8): Add GR712RC errata workaround.
2799
2800 2024-01-16  Andreas Larsson  <andreas@gaisler.com>
2801
2802         * config/sparc/sync.md (*membar_storeload_leon3): Remove
2803         (*membar_storeload): Enable for LEON
2804
2805 2024-01-16  Jakub Jelinek  <jakub@redhat.com>
2806
2807         PR tree-optimization/113372
2808         PR middle-end/90348
2809         PR middle-end/110115
2810         PR middle-end/111422
2811         * cfgexpand.cc (add_scope_conflicts_2): New function.
2812         (add_scope_conflicts_1): Use it.
2813
2814 2024-01-16  Georg-Johann Lay  <avr@gjlay.de>
2815
2816         * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
2817         (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
2818         * doc/avr-mmcu.texi: Regenerate.
2819
2820 2024-01-16  Feng Xue  <fxue@os.amperecomputing.com>
2821
2822         PR tree-optimization/113091
2823         * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
2824         (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
2825         scalar use with new function.
2826         (vect_bb_slp_mark_live_stmts): New function as entry to existing
2827         overriden functions with same name.
2828         (vect_slp_analyze_operations): Call new entry function to mark
2829         live statements.
2830
2831 2024-01-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2832
2833         PR target/113404
2834         * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
2835         for RVV in big-endian mode.
2836
2837 2024-01-16  Yanzhang Wang  <yanzhang.wang@intel.com>
2838
2839         * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
2840         (riscv_pass_in_vector_p): Delete.
2841         (riscv_init_cumulative_args): Delete the checking.
2842         (riscv_get_arg_info): Delete the checking.
2843         (riscv_function_value): Delete the checking.
2844         * config/riscv/riscv.h: Delete the member for checking.
2845
2846 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
2847
2848         * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
2849
2850 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
2851
2852         * config.gcc: Include riscv_bitmanip.h.
2853         * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
2854         * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
2855         * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
2856         (RISCV_BUILTIN_NO_PREFIX): New helper macro.
2857         * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
2858         * config/riscv/riscv-ftypes.def (2): New ftypes.
2859         * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
2860         (RISCV_BUILTIN_NO_PREFIX): Likewise.
2861         * config/riscv/riscv_bitmanip.h: New file.
2862
2863 2024-01-15  Liao Shihua  <shihua@iscas.ac.cn>
2864
2865         * config.gcc: Include riscv_crypto.h.
2866         * config/riscv/riscv_crypto.h: New file.
2867
2868 2024-01-15  Vladimir N. Makarov  <vmakarov@redhat.com>
2869
2870         PR middle-end/113354
2871         * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
2872         in the insn if the corresponding operand does not require hard
2873         register anymore.
2874
2875 2024-01-15  Georg-Johann Lay  <avr@gjlay.de>
2876
2877         PR target/107201
2878         * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
2879         * config/avr/driver-avr.cc (avr_no_devlib): New function.
2880         (avr_devicespecs_file): Use it to remove -nodevicelib from the
2881         options for cores only.
2882         * config/avr/avr-arch.h (avr_get_parch): New prototype.
2883         * config/avr/avr-devices.cc (avr_get_parch): New function.
2884
2885 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2886
2887         PR target/113247
2888         * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
2889         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
2890         * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
2891
2892 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2893
2894         PR target/113281
2895         * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
2896         (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
2897         * config/riscv/riscv-vector-costs.h: New function.
2898
2899 2024-01-15  Richard Biener  <rguenther@suse.de>
2900
2901         PR tree-optimization/113385
2902         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2903         First redirect, then split the exit edge.
2904
2905 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2906
2907         * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
2908         Remove m_num_vector_iterations.
2909         * config/riscv/riscv-vector-costs.h: Ditto.
2910
2911 2024-01-15  Andrew Pinski  <quic_apinski@quicinc.com>
2912
2913         PR target/113156
2914         * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
2915         (-mbranch-cost): Set "Optimization" flag.
2916
2917 2024-01-15  Jakub Jelinek  <jakub@redhat.com>
2918
2919         PR tree-optimization/113370
2920         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
2921         set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
2922         set it to just prec % limb_prec.
2923
2924 2024-01-15  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
2925
2926         PR target/113393
2927         * config/riscv/vector.md: Fix ternary attributes.
2928
2929 2024-01-14  Georg-Johann Lay  <avr@gjlay.de>
2930
2931         PR target/112944
2932         * configure.ac [target=avr]: Check availability of emulations
2933         avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
2934         HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
2935         * configure: Regenerate.
2936         * config.in: Regenerate.
2937         * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
2938         __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
2939         * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
2940         * config/avr/avr-arch.h (enum avr_device_specific_features):
2941         Add AVR_ISA_FLMAP.
2942         * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
2943         AVR_ISA_FLMAP.
2944         * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
2945         (avr_set_core_architecture): Set avr_arch_index.
2946         (have_avrxmega2_flmap, have_avrxmega4_flmap)
2947         (have_avrxmega3_rodata_in_flash): Set new static const bool according
2948         to configure results.
2949         (avr_rodata_in_flash_p): New function using them.
2950         (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
2951         track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
2952         (avr_asm_named_section): Track avr_has_rodata_p.
2953         (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
2954         and not avr_rodata_in_flash_p ().
2955         * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
2956         (LINK_SPEC): Add %(link_rodata_in_ram).
2957         (LINK_ARCH_SPEC): Remove.
2958         * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
2959         (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
2960         const bool according to configure results.
2961         (diagnose_mrodata_in_ram): New function.
2962         (print_mcu): Generate specs with the following changes:
2963         <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
2964         need to extend avr/specs.h each time we add a new bell or whistle.
2965         <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
2966         -m[no-]rodata-in-ram.
2967         <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
2968         <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
2969         <*cpp>: Add %(cpp_rodata_in_ram).
2970         <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
2971         requested.
2972         <*self_spec>: Add -mflmap or %<mflmap as needed.
2973
2974 2024-01-14  Jeff Law  <jlaw@ventanamicro.com>
2975
2976         * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
2977         not the GPR iterator.  Adjust pattern name and mode attribute
2978         accordingly.
2979
2980 2024-01-13  Jakub Jelinek  <jakub@redhat.com>
2981
2982         PR tree-optimization/113361
2983         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
2984         Fix up determination of the type for > limb_prec constants.
2985
2986 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
2987
2988         * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
2989         Add web-link to the avr-gcc wiki.
2990
2991 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
2992
2993         * doc/extend.texi (AVR Variable Attributes) [address]: Remove
2994         documentation for a version without argument, which is not supported.
2995
2996 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
2997
2998         * config/arm/arm_neon.h
2999         (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
3000         (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
3001         (vld1_f16_x4, vld1_f32_x4): New.
3002         (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
3003         (vld1_bf16_x4): New.
3004         (vld1q_types_x4): Updated to use vld1q_x4
3005         from arm_neon_builtins.def
3006         * config/arm/arm_neon_builtins.def
3007         (vld1_x4): Updated entries.
3008         (vld1q_x4): New entries, but comes from the old vld1_x4
3009         * config/arm/neon.md
3010         (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
3011
3012 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3013
3014         * config/arm/arm_neon.h
3015         (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
3016         (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
3017         (vld1_f16_x3, vld1_f32_x3): New.
3018         (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
3019         (vld1_bf16_x3): New.
3020         (vld1q_types_x3): Updated to use vld1q_x3 from
3021         arm_neon_builtins.def
3022         * config/arm/arm_neon_builtins.def
3023         (vld1_x3): Updated entries.
3024         (vld1q_x3): New entries, but comes from the old vld1_x2
3025         * config/arm/neon.md
3026         (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
3027
3028 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3029
3030         * config/arm/arm_neon.h
3031         (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
3032         (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
3033         (vld1_f16_x2, vld1_f32_x2): New.
3034         (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
3035         (vld1_bf16_x2): New.
3036         (vld1q_types_x2): Updated to use vld1q_x2 from
3037         arm_neon_builtins.def
3038         * config/arm/arm_neon_builtins.def
3039         (vld1_x2): Updated entries.
3040         (vld1q_x2): New entries, but comes from the old vld1_x2
3041         * config/arm/neon.md
3042         (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
3043         neon_vld1_x2<mode>.
3044
3045 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3046
3047         * config/arm/arm_neon.h
3048         (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
3049         (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
3050         (vst1q_f16_x4, vst1q_f32_x4): New.
3051         (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
3052         (vst1q_bf16_x4): New.
3053         * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
3054         * config/arm/neon.md
3055         (neon_vst1q_x4<mode>): New.
3056         (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
3057         * config/arm/unspecs.md
3058         (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
3059
3060 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3061
3062         * config/arm/arm_neon.h
3063         (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
3064         (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
3065         (vst1q_f16_x3, vst1q_f32_x3): New.
3066         (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
3067         (vst1q_bf16_x3): New.
3068         * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
3069         * config/arm/neon.md
3070         (neon_vst1q_x3<mode>): New.
3071         (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
3072         * config/arm/unspecs.md
3073         (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
3074
3075 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3076
3077         * config/arm/arm_neon.h
3078         (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
3079         (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
3080         (vst1q_f16_x2, vst1q_f32_x2): New.
3081         (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
3082         (vst1q_bf16_x2): New.
3083         * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
3084         * config/arm/neon.md
3085         (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
3086         neon_vst1_x2<mode>.
3087         * config/arm/iterators.md
3088         (VMEMX2): New mode iterator.
3089         (VMEMX2_q): New mode attribute.
3090
3091 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3092
3093         * config/arm/arm_neon.h
3094         (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
3095         (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
3096         (vst1_f16_x4, vst1_f32_x4): New.
3097         (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
3098         (vst1_bf16_x4): New.
3099         * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
3100         * config/arm/neon.md (vst1_x4<mode>): New.
3101
3102 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3103
3104         * config/arm/arm_neon.h
3105         (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
3106         (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
3107         (vst1_f16_x3, vst1_f32_x3): New.
3108         (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
3109         (vst1_bf16_x3): New.
3110         * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
3111         * config/arm/neon.md (vst1_x3<mode>): New.
3112
3113 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3114
3115         * config/arm/arm_neon.h
3116         (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
3117         (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
3118         (vst1_f16_x2, vst1_f32_x2): New.
3119         (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
3120         (vst1_bf16_x2): New.
3121         * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
3122         * config/arm/neon.md (vst1_x2<mode>): New.
3123
3124 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3125
3126         * config/arm/arm_neon.h
3127         (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
3128         (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
3129         (vld1q_f16_x4, vld1q_f32_x4): New.
3130         (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
3131         (vld1q_bf16_x4): New.
3132         * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
3133         * config/arm/neon.md
3134         (neon_vld1_x4<mode>): New.
3135         (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
3136         * config/arm/unspecs.md
3137         (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
3138
3139 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3140
3141         * config/arm/arm_neon.h
3142         (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
3143         (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
3144         (vld1q_f16_x3, vld1q_f32_x3): New.
3145         (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
3146         (vld1q_bf16_x3): New.
3147         * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
3148         * config/arm/neon.md
3149         (neon_vld1_x3<mode>): New.
3150         (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
3151         * config/arm/unspecs.md
3152         (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
3153
3154 2024-01-12  Ezra Sitorus  <ezra.sitorus@arm.com>
3155
3156         * config/arm/arm_neon.h
3157         (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
3158         (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
3159         (vld1q_f16_x2, vld1q_f32_x2): New.
3160         (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
3161         (vld1q_bf16_x2): New.
3162         * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
3163         * config/arm/neon.md (vld1_x2<mode>): New.
3164
3165 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
3166
3167         PR tree-optimization/113287
3168         * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
3169
3170 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
3171
3172         * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
3173         * tree-vect-loop.cc (vect_transform_loop): Likewise.
3174
3175 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
3176
3177         PR tree-optimization/113178
3178         * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
3179         alternate exits.
3180
3181 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
3182
3183         PR tree-optimization/113237
3184         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
3185         existing LCSSA variable for exit when all exits are early break.
3186
3187 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
3188
3189         PR tree-optimization/113137
3190         PR tree-optimization/113136
3191         PR tree-optimization/113172
3192         PR tree-optimization/113178
3193         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3194         Maintain PHIs on inverted loops.
3195         (vect_do_peeling): Maintain virtual PHIs on inverted loops.
3196         * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
3197         latch.
3198         (vect_create_loop_vinfo): Record all conds instead of only alt ones.
3199
3200 2024-01-12  Tamar Christina  <tamar.christina@arm.com>
3201
3202         PR tree-optimization/113135
3203         * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
3204         dependency analysis.
3205
3206 2024-01-12  Iain Sandoe  <iain@sandoe.co.uk>
3207
3208         * config/rs6000/host-darwin.cc (segv_handler): Use the revised
3209         diagnostics class member name for abort of error.
3210
3211 2024-01-12  Georg-Johann Lay  <avr@gjlay.de>
3212
3213         * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
3214         format string to %s argument.
3215
3216 2024-01-12  John David Anglin  <danglin@gcc.gnu.org>
3217             Jakub Jelinek  <jakub@redhat.com>
3218
3219         PR middle-end/113182
3220         * varasm.cc (process_pending_assemble_externals,
3221         assemble_external_libcall): Use targetm.strip_name_encoding
3222         before calling get_identifier.
3223
3224 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
3225
3226         PR target/113196
3227         * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
3228         New member variable.
3229         * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
3230         Declare.
3231         * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
3232         * config/aarch64/aarch64-simd.md
3233         (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
3234         (vec_unpack<su>_hi_<mode>): ...this.  Move the generation of
3235         zip2 for zero-extends to...
3236         (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
3237         instruction.  Fix big-endian handling.
3238         (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
3239         (vec_unpack<su>_lo_<mode>): ...this.  Move the generation of
3240         zip1 for zero-extends to...
3241         (<optab><Vnarrowq><mode>2): ...a split of this instruction.
3242         Fix big-endian handling.
3243         (*aarch64_zip1_uxtl): New pattern.
3244         (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
3245         (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
3246         * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
3247         (aarch64_gen_shareable_zero): Use it.
3248         (aarch64_split_simd_shift_p): New function.
3249
3250 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
3251
3252         * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
3253         (function_beg_insn): New macro.
3254         * function.cc (expand_function_start): Initialize function_beg_insn.
3255
3256 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
3257
3258         PR target/112989
3259         * config/aarch64/aarch64-sve-builtins.h
3260         (function_builder::m_overload_names): Replace with...
3261         * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
3262         new global.
3263         (add_overloaded_function): Update accordingly, using get_identifier
3264         to get a GGC-friendly record of the name.
3265
3266 2024-01-12  Richard Sandiford  <richard.sandiford@arm.com>
3267
3268         PR target/112989
3269         * config/aarch64/aarch64-sve-builtins.def: Don't include
3270         aarch64-sve-builtins-sme.def.
3271         (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
3272         * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
3273         (DEF_SME_FUNCTION): New macro.  Use it and DEF_SME_FUNCTION_GS
3274         instead of DEF_SVE_*.  Add AARCH64_FL_SME to anything that
3275         requires AARCH64_FL_SME2.
3276         * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
3277         AARCH64_FL_SME adjustment here.
3278         * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
3279         include SME intrinsics.
3280         (sme_function_groups): New array.
3281         (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
3282         (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
3283
3284 2024-01-12  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3285
3286         PR target/113281
3287         * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
3288         (struct cpu_vector_cost): Add regmove struct.
3289         (get_vector_costs): Export as global.
3290         * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
3291         (costs::add_stmt_cost): Ditto.
3292         * config/riscv/riscv.cc (get_common_costs): Export global function.
3293
3294 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
3295
3296         PR tree-optimization/113334
3297         * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
3298         wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
3299         to determine if number should be extended by all ones rather than zero
3300         extended.
3301
3302 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
3303
3304         PR tree-optimization/113330
3305         * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
3306         too large size.
3307
3308 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
3309
3310         PR tree-optimization/113323
3311         * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
3312         check for lhs being large/huge _BitInt not in m_names.
3313
3314 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
3315
3316         PR tree-optimization/113316
3317         * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
3318         uninitialized large/huge _BitInt arguments to calls.
3319
3320 2024-01-12  Jakub Jelinek  <jakub@redhat.com>
3321
3322         * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
3323         TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
3324         CEIL (TYPE_PRECISION (t), limb_prec).
3325         (bitint_large_huge::handle_cast): Likewise.
3326
3327 2024-01-12  Ilya Leoshkevich  <iii@linux.ibm.com>
3328
3329         PR sanitizer/113284
3330         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
3331         Use assemble_function_label_final () for Power ELF V1 ABI.
3332         * output.h (assemble_function_label_final): New function.
3333         * varasm.cc (assemble_function_label_raw): Use
3334         assemble_function_label_final ().
3335         (assemble_function_label_final): New function.
3336
3337 2024-01-12  Richard Biener  <rguenther@suse.de>
3338
3339         PR middle-end/113344
3340         * match.pd ((double)float CMP (double)float -> float CMP float):
3341         Perform result type check only for vectors.
3342         * fold-const.cc (fold_binary_loc): Likewise.
3343
3344 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
3345
3346         * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
3347         (usdot_prod<mode>): Ditto.
3348         (sdot_prod<mode>): Ditto.
3349         (udot_prod<mode>): Ditto.
3350
3351 2024-01-12  Haochen Jiang  <haochen.jiang@intel.com>
3352
3353         PR target/113288
3354         * config/i386/i386-c.cc (ix86_target_macros_internal):
3355         Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
3356
3357 2024-01-12  Richard Biener  <rguenther@suse.de>
3358
3359         PR target/112280
3360         * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
3361         Do not generate code when d.testing_p.
3362
3363 2024-01-12  liuhongt  <hongtao.liu@intel.com>
3364
3365         PR target/113039
3366         * doc/invoke.texi (fcf-protection=): Update documents.
3367
3368 2024-01-12  Pan Li  <pan2.li@intel.com>
3369
3370         * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
3371         comments of predicate func riscv_v_ext_mode_p.
3372
3373 2024-01-12  Feng Wang  <wangfeng@eswincomputing.com>
3374
3375         * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
3376                         Modify ABI-name length of vfloat16m8_t
3377
3378 2024-01-12  Li Wei  <liwei@loongson.cn>
3379
3380         * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
3381         Adjust.
3382
3383 2024-01-12  Li Wei  <liwei@loongson.cn>
3384
3385         * config/loongarch/loongarch.md (add<mode>3): Removed.
3386         (*addsi3): New.
3387         (addsi3): Ditto.
3388         (adddi3): Ditto.
3389         (*addsi3_extended): Removed.
3390         (addsi3_extended): New.
3391
3392 2024-01-11  Jin Ma  <jinma@linux.alibaba.com>
3393
3394         * config/riscv/thead.md: Add limits for splits.
3395
3396 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
3397
3398         PR middle-end/113322
3399         * expr.cc (do_store_flag): Don't try single bit tests with
3400         comparison on vector types.
3401
3402 2024-01-11  Andrew Pinski  <quic_apinski@quicinc.com>
3403
3404         PR tree-optimization/113301
3405         * match.pd (`1/x`): Delay signed case until late.
3406
3407 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
3408
3409         * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
3410         and -msp8 to...
3411         (AVR Internal Options): ...this new @subsubsection.
3412
3413 2024-01-11  Vladimir N. Makarov  <vmakarov@redhat.com>
3414
3415         PR rtl-optimization/112918
3416         * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
3417         (in_class_p): Restrict condition for narrowing class in case of
3418         allow_all_reload_class_changes_p.
3419         (process_alt_operands): Try to match operand without and with
3420         narrowing reg class.  Discourage narrowing the class.  Finish insn
3421         matching only if there is no class narrowing.
3422         (curr_insn_transform): Pass true to in_class_p for reg operand win.
3423
3424 2024-01-11  Richard Biener  <rguenther@suse.de>
3425
3426         PR tree-optimization/112505
3427         * tree-vect-loop.cc (vectorizable_induction): Reject
3428         bit-precision induction.
3429
3430 2024-01-11  Richard Biener  <rguenther@suse.de>
3431
3432         PR tree-optimization/113126
3433         * match.pd ((double)float CMP (double)float -> float CMP float):
3434         Make sure the boolean type is the same.
3435         * fold-const.cc (fold_binary_loc): Likewise.
3436
3437 2024-01-11  Richard Biener  <rguenther@suse.de>
3438
3439         PR tree-optimization/112636
3440         * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
3441         estimate_numbers_of_iterations before querying
3442         get_max_loop_iterations_int.
3443         (pass_ch::execute): Initialize SCEV and loops appropriately.
3444
3445 2024-01-11  Georg-Johann Lay  <avr@gjlay.de>
3446
3447         * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
3448         Reduced Tiny.
3449         * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
3450         * doc/extend.texi (AVR Variable Attributes): Improve documentation
3451         of io, io_low and address attributes.
3452         * doc/invoke.texi (AVR Options): Add some anchors for external refs.
3453         * doc/avr-mmcu.texi: Rebuild.
3454
3455 2024-01-11  Yang Yujie  <yangyujie@loongson.cn>
3456
3457         PR target/113233
3458         * config/loongarch/genopts/loongarch.opt.in: Mark options with
3459         the "Save" property.
3460         * config/loongarch/loongarch.opt: Same.
3461         * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
3462         according to la_target.
3463         * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
3464         RESTORE} for the la_target structure; Rename option conditions
3465         to have the same "la_" prefix.
3466         * config/loongarch/loongarch.h: Same.
3467
3468 2024-01-11  Pan Li  <pan2.li@intel.com>
3469
3470         * loop-unroll.cc (insert_var_expansion_initialization): Leverage
3471         MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
3472
3473 2024-01-11  Alex Coplan  <alex.coplan@arm.com>
3474
3475         PR target/113077
3476         * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
3477         fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
3478         (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
3479         synthesize these if needed.  Update caller ...
3480         (ldp_bb_info::fuse_pair): ... here.
3481         (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
3482         and either insn is frame-related.
3483         (find_trailing_add): Punt on frame-related insns.
3484         * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
3485         REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
3486
3487 2024-01-11  YunQiang Su  <syq@gcc.gnu.org>
3488
3489         * config/mips/mips.cc (mips_start_function_definition):
3490         Add ATTRIBUTE_UNUSED.
3491
3492 2024-01-11  Richard Biener  <rguenther@suse.de>
3493
3494         PR middle-end/112740
3495         * expr.cc (store_constructor): Check the integer vector
3496         mask has a single bit per element before using sign-extension
3497         to expand an uniform vector.
3498
3499 2024-01-11  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3500
3501         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
3502         preempt VLS on unknown NITERS loop.
3503
3504 2024-01-11  Haochen Jiang  <haochen.jiang@intel.com>
3505
3506         * doc/invoke.texi: Add -mevex512.
3507
3508 2024-01-11  Lulu Cheng  <chenglulu@loongson.cn>
3509
3510         * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
3511         (*nor<mode>3): Likewise.
3512         (nor<mode>3): Likewise.
3513         (*negsi2_extended): New template.
3514         (*<optab>si3_internal): Likewise.
3515         (*one_cmplsi2_internal): Likewise.
3516         (*norsi3_internal): Likewise.
3517         (*<optab>nsi_internal): Likewise.
3518         (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
3519         modified bit operation to make the optimization work.
3520
3521 2024-01-11  liuhongt  <hongtao.liu@intel.com>
3522
3523         PR target/104401
3524         * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
3525
3526 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3527
3528         * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
3529         (get_vector_costs): Ditto.
3530         (riscv_builtin_vectorization_cost): Ditto.
3531
3532 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3533
3534         * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
3535
3536 2024-01-10  Antoni Boucher  <bouanto@zoho.com>
3537
3538         PR jit/111396
3539         * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
3540         ipa_free_size_summary.
3541         * ipa-icf.cc (ipa_icf_cc_finalize): New function.
3542         * ipa-profile.cc (ipa_profile_cc_finalize): New function.
3543         * ipa-prop.cc (ipa_prop_cc_finalize): New function.
3544         * ipa-prop.h (ipa_prop_cc_finalize): New function.
3545         * ipa-sra.cc (ipa_sra_cc_finalize): New function.
3546         * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
3547         ipa_sra_cc_finalize): New functions.
3548         * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
3549         ipa_prop_cc_finalize, ipa_profile_cc_finalize and
3550         ipa_sra_cc_finalize
3551         Include ipa-utils.h.
3552
3553 2024-01-10  Jin Ma  <jinma@linux.alibaba.com>
3554
3555         * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
3556         (th_int_get_save_adjustment): Likewise.
3557         (th_int_adjust_cfi_prologue): Likewise.
3558         * config/riscv/riscv.cc (BITSET_P): Moved away from here.
3559         (TH_INT_INTERRUPT): New macro.
3560         (riscv_expand_prologue): Add the processing of XTheadInt.
3561         (riscv_expand_epilogue): Likewise.
3562         * config/riscv/riscv.h (BITSET_P): Moved to here.
3563         * config/riscv/riscv.md: New unspec.
3564         * config/riscv/thead.cc (th_int_get_mask): New function.
3565         (th_int_get_save_adjustment): Likewise.
3566         (th_int_adjust_cfi_prologue): Likewise.
3567         * config/riscv/thead.md (th_int_push): New pattern.
3568         (th_int_pop): new pattern.
3569
3570 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
3571
3572         PR tree-optimization/112468
3573         * doc/sourcebuild.texi: Document ifn_copysign.
3574         * match.pd: Only apply transformation if target supports the IFN.
3575
3576 2024-01-10  Andrew Pinski  <quic_apinski@quicinc.com>
3577
3578         PR tree-optimization/112581
3579         * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
3580         mark_ssa_maybe_undefs.
3581         * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
3582         variables can not be reassociated.
3583         (init_range_entry): Check for uninitialized variables too.
3584         (init_reassoc): Call mark_ssa_maybe_undefs.
3585
3586 2024-01-10  Maciej W. Rozycki  <macro@embecosm.com>
3587
3588         * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
3589         Also handle sign extension.
3590
3591 2024-01-10  Alex Coplan  <alex.coplan@arm.com>
3592
3593         * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
3594         to 0.
3595         (-mlate-ldp-fusion): Likewise.
3596
3597 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
3598
3599         PR tree-optimization/113287
3600         * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
3601         instead of using BRANCH_EDGE to determine true edge.
3602
3603 2024-01-10  Richard Biener  <rguenther@suse.de>
3604
3605         PR tree-optimization/113078
3606         * tree-vect-loop.cc (check_reduction_path): Canonicalize
3607         .COND_SUB to .COND_ADD.
3608
3609 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
3610
3611         * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
3612         Handle prefix mappings before calling find_opt.
3613         (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
3614         "-fno-"-prefixed command-line option.
3615         * opts-common.cc (get_option_prefix_remapping): New.
3616         * opts.h (get_option_prefix_remapping): New decl.
3617
3618 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
3619
3620         * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
3621         m_urlifier to pp_output_formatted_text.
3622         * pretty-print.cc: Add #define of INCLUDE_VECTOR.
3623         (obstack_append_string): New overload, taking a length.
3624         (urlify_quoted_string): Pass in an obstack ptr, rather than using
3625         that of the pp's buffer.  Generalize to handle trailing text in
3626         the buffer beyond the run of quoted text.
3627         (class quoting_info): New.
3628         (on_begin_quote): New.
3629         (on_end_quote): New.
3630         (pp_format): Refactor phase 1 and phase 2 quoting support, moving
3631         it to calls to on_begin_quote and on_end_quote.
3632         (struct auto_obstack): New.
3633         (quoting_info::handle_phase_3): New.
3634         (pp_output_formatted_text): Add urlifier param.  Use it if there
3635         is deferred urlification.  Delete m_quotes.
3636         (selftest::pp_printf_with_urlifier): Pass urlifier to
3637         pp_output_formatted_text.
3638         (selftest::test_urlification): Update results for the existing
3639         case of quoted text stradding chunks; add more such test cases.
3640         * pretty-print.h (class quoting_info): New forward decl.
3641         (chunk_info::m_quotes): New field.
3642         (pp_output_formatted_text): Add optional urlifier param.
3643
3644 2024-01-10  David Malcolm  <dmalcolm@redhat.com>
3645
3646         * pretty-print.cc (selftest::test_pp_format): Add selftest
3647         coverage for numbered args.
3648
3649 2024-01-10  Tamar Christina  <tamar.christina@arm.com>
3650
3651         PR tree-optimization/113144
3652         PR tree-optimization/113145
3653         * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3654         Update all BB that the original exits dominated.
3655
3656 2024-01-10  Eric Botcazou  <ebotcazou@adacore.com>
3657
3658         * dwarf2out.cc (modified_type_die): Extend the support of reverse
3659         storage order to enumeration types if -gstrict-dwarf is not passed.
3660         (gen_enumeration_type_die): Add REVERSE parameter and generate the
3661         DIE immediately after the existing one if it is true.
3662         (gen_tagged_type_die): Add REVERSE parameter and pass it in the
3663         call to gen_enumeration_type_die.
3664         (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
3665         first recursive call as well as the call to gen_tagged_type_die.
3666         (gen_type_die): Add REVERSE parameter and pass it in the call to
3667         gen_type_die_with_usage.
3668
3669 2024-01-10  Jakub Jelinek  <jakub@redhat.com>
3670
3671         PR tree-optimization/113120
3672         * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
3673         with root->size TYPE_PRECISION don't build anything new.
3674         Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
3675         rather than build_nonstandard_integer_type.
3676
3677 2024-01-10  Hongyu Wang  <hongyu.wang@intel.com>
3678
3679         * config/i386/i386.opt: Adjust document.
3680         * doc/invoke.texi: Add description for
3681         -mapx-inline-asm-use-gpr32.
3682
3683 2024-01-10  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3684
3685         * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
3686         (avg<v_double_trunc>3_floor): New pattern.
3687         (<u>avg<v_double_trunc>3_ceil): Remove.
3688         (avg<v_double_trunc>3_ceil): New pattern.
3689         (uavg<mode>3_floor): Ditto.
3690         (uavg<mode>3_ceil): Ditto.
3691         * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
3692         (enum insn_type): Ditto.
3693         * config/riscv/riscv-v.cc: Ditto.
3694         * config/riscv/vector-iterators.md (ashiftrt): Remove.
3695         (ASHIFTRT): Ditto.
3696         * config/riscv/vector.md: Add VLS modes.
3697
3698 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
3699
3700         PR target/111480
3701         * config/rs6000/vsx.md (VCZLSBB): New int iterator.
3702         (vczlsbb_char): New int attribute.
3703         (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
3704         (vc<vczlsbb_char>zlsbb_<mode>): ... this.
3705         (*vctzlsbb_zext_<mode>): Rename to ...
3706         (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
3707         cover vclzlsbb.
3708
3709 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
3710
3711         PR target/112606
3712         * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
3713         of the last argument from altivec_register_operand to any_operand.  If
3714         operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
3715         otherwise if it doesn't satisfy altivec_register_operand, force it to
3716         REG using copy_to_mode_reg.
3717
3718 2024-01-10  Kewen Lin  <linkw@linux.ibm.com>
3719
3720         PR middle-end/113100
3721         * builtins.cc (expand_builtin_stack_address): Guard stack point
3722         adjustment with SPARC_STACK_BOUNDARY_HACK.
3723
3724 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
3725
3726         * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
3727         argument string definitions.
3728         * config/loongarch/loongarch-str.h: Same.
3729         * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
3730         as aliases to -mexplicit-relocs={always,none}
3731         * config/loongarch/loongarch.opt: Regenerate.
3732         * config/loongarch/loongarch.cc: Same.
3733
3734 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
3735
3736         * config/loongarch/loongarch-def.h: Define constants with
3737         enums instead of Macros.
3738
3739 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
3740
3741         * config/loongarch/genopts/loongarch-strings: Rename.
3742         * config/loongarch/genopts/loongarch.opt.in: Same.
3743         * config/loongarch/loongarch-cpu.cc: Same.
3744         * config/loongarch/loongarch-def.cc: Same.
3745         * config/loongarch/loongarch-def.h: Same.
3746         * config/loongarch/loongarch-opts.cc: Same.
3747         * config/loongarch/loongarch-opts.h: Same.
3748         * config/loongarch/loongarch-str.h: Same.
3749         * config/loongarch/loongarch.opt: Same.
3750
3751 2024-01-10  Yang Yujie  <yangyujie@loongson.cn>
3752
3753         * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
3754         variable with the common la_ prefix.
3755         * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
3756         flags as saved using TargetVariable.
3757         * config/loongarch/loongarch.opt: Same.
3758         * config/loongarch/loongarch-def.h: Define evolution_set to
3759         mark changes to the -march default.
3760         * config/loongarch/loongarch-driver.cc: Same.
3761         * config/loongarch/loongarch-opts.cc: Same.
3762         * config/loongarch/loongarch-opts.h: Define and use ISA evolution
3763         conditions around the la_target structure.
3764         * config/loongarch/loongarch.cc: Same.
3765         * config/loongarch/loongarch.md: Same.
3766         * config/loongarch/loongarch-builtins.cc: Same.
3767         * config/loongarch/loongarch-c.cc: Same.
3768         * config/loongarch/lasx.md: Same.
3769         * config/loongarch/lsx.md: Same.
3770         * config/loongarch/sync.md: Same.
3771
3772 2024-01-09  Jeff Law  <jlaw@ventanamicro.com>
3773
3774         * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
3775         no less.
3776
3777 2024-01-09  Richard Sandiford  <richard.sandiford@arm.com>
3778
3779         * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
3780
3781 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
3782
3783         * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
3784         restart_loop.
3785         (vectorizable_live_operation): Likewise.
3786
3787 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
3788
3789         PR tree-optimization/113199
3790         * tree-vect-loop.cc (vectorizable_live_operation_1): Use
3791         BIT_FIELD_REF.
3792
3793 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
3794
3795         PR target/113270
3796         * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
3797         * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
3798         GTY(()) declaration before the definition, drop GTY(()) drom the
3799         definition.
3800
3801 2024-01-09  Richard Biener  <rguenther@suse.de>
3802
3803         PR tree-optimization/113026
3804         * tree-vect-loop-manip.cc (vect_do_peeling): Remove
3805         redundant and wrong niter bound setting.  Move niter
3806         bound adjustment down.
3807
3808 2024-01-09  Tamar Christina  <tamar.christina@arm.com>
3809
3810         PR middle-end/113163
3811         * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
3812         Reject non-linear inductions that aren't supported.
3813
3814 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
3815
3816         * config/arc/arc.cc (arc_shift_alg): New enumerated type for
3817         left shift implementation strategies.
3818         (arc_shift_info): Type for each entry of the shift strategy table.
3819         (arc_shift_context_idx): Return a integer value for each code
3820         generation context, used as an index
3821         (arc_ashl_alg): Table indexed by context and shifted bit count.
3822         (arc_split_ashl): Use the arc_ashl_alg table to select SImode
3823         left shift implementation.
3824         (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
3825         provide accurate costs, when optimizing for speed or size.
3826
3827 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3828
3829         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
3830
3831 2024-01-09  Julian Brown  <julian@codesourcery.com>
3832
3833         * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
3834         processed out before gimplification.
3835         * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
3836         * tree.def (OMP_ARRAY_SECTION): New tree code.
3837
3838 2024-01-09  Jakub Jelinek  <jakub@redhat.com>
3839
3840         PR tree-optimization/113210
3841         * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
3842         value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
3843         INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
3844         minus 1.
3845
3846 2024-01-09  Eric Botcazou  <ebotcazou@adacore.com>
3847
3848         PR rtl-optimization/113140
3849         * reorg.cc (fill_slots_from_thread): If we are to branch after the
3850         last instruction of the function, create an end label.
3851
3852 2024-01-09  Roger Sayle  <roger@nextmovesoftware.com>
3853             Hongtao Liu  <hongtao.liu@intel.com>
3854
3855         PR target/112992
3856         * config/i386/i386-expand.cc
3857         (ix86_convert_const_wide_int_to_broadcast): Allow call to
3858         ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
3859         (ix86_broadcast_from_constant): Revert recent change; Return a
3860         suitable MEMREF independently of mode/target combinations.
3861         (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
3862         to decide whether expansion is possible/preferrable.  Only try
3863         forcing DImode constants to memory (and trying again) if calling
3864         ix86_expand_vector_init_duplicate fails with an DImode immediate
3865         constant.
3866         (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
3867         V4SImode for suitable immediate constants.
3868         <case E_V4DImode>: Try using V8SImode for suitable constants.
3869         <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
3870         <case E_V2HImode>: Likewise.
3871         <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
3872         <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
3873         <label widen>: Handle CONT_INTs via simplify_binary_operation.
3874         Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
3875         <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
3876         <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
3877         (ix86_expand_vector_init): Move try using a broadcast for all_same
3878         with ix86_expand_vector_init_duplicate before using constant pool.
3879
3880 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
3881
3882         * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
3883
3884 2024-01-09  Chung-Ju Wu  <jasonwucj@gmail.com>
3885
3886         * config/arm/arm-cpus.in (cortex-m52): New cpu.
3887         * config/arm/arm-tables.opt: Regenerate.
3888         * config/arm/arm-tune.md: Regenerate.
3889
3890 2024-01-09  Jiahao Xu  <xujiahao@loongson.cn>
3891
3892         * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
3893         (vec_init<mode><lasxhalf>): .. this, and extend to mode.
3894         (@vec_concatz<mode>): New insn pattern.
3895         * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
3896         Handle VALS containing two vectors.
3897
3898 2024-01-09  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
3899
3900         * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
3901         (vundefined): Ditto.
3902
3903 2024-01-09  Feng Wang  <wangfeng@eswincomputing.com>
3904
3905         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
3906                                 Add new function_base for crypto vector.
3907         (class bitmanip): Ditto.
3908         (class b_reverse):Ditto.
3909         (class vwsll):   Ditto.
3910         (class clmul):   Ditto.
3911         (class vg_nhab):  Ditto.
3912         (class crypto_vv):Ditto.
3913         (class crypto_vi):Ditto.
3914         (class vaeskf2_vsm3c):Ditto.
3915         (class vsm3me): Ditto.
3916         (BASE): Add BASE declaration for crypto vector.
3917         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
3918         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
3919                                 Add crypto vector intrinsic definition.
3920         (vbrev): Ditto.
3921         (vclz): Ditto.
3922         (vctz): Ditto.
3923         (vwsll): Ditto.
3924         (vandn): Ditto.
3925         (vbrev8): Ditto.
3926         (vrev8): Ditto.
3927         (vrol): Ditto.
3928         (vror): Ditto.
3929         (vclmul): Ditto.
3930         (vclmulh): Ditto.
3931         (vghsh): Ditto.
3932         (vgmul): Ditto.
3933         (vaesef): Ditto.
3934         (vaesem): Ditto.
3935         (vaesdf): Ditto.
3936         (vaesdm): Ditto.
3937         (vaesz): Ditto.
3938         (vaeskf1): Ditto.
3939         (vaeskf2): Ditto.
3940         (vsha2ms): Ditto.
3941         (vsha2ch): Ditto.
3942         (vsha2cl): Ditto.
3943         (vsm4k): Ditto.
3944         (vsm4r): Ditto.
3945         (vsm3me): Ditto.
3946         (vsm3c): Ditto.
3947         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
3948                                 Add new function_shape for crypto vector.
3949         (struct crypto_vi_def): Ditto.
3950         (struct crypto_vv_no_op_type_def): Ditto.
3951         (SHAPE): Add SHAPE declaration of crypto vector.
3952         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
3953         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
3954                                 Add new data type for crypto vector.
3955         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3956         (vuint32mf2_t): Ditto.
3957         (vuint32m1_t): Ditto.
3958         (vuint32m2_t): Ditto.
3959         (vuint32m4_t): Ditto.
3960         (vuint32m8_t): Ditto.
3961         (vuint64m1_t): Ditto.
3962         (vuint64m2_t): Ditto.
3963         (vuint64m4_t): Ditto.
3964         (vuint64m8_t): Ditto.
3965         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
3966                                 Add new data struct for crypto vector.
3967         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
3968         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
3969         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
3970
3971 2024-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>
3972
3973         PR sanitizer/113251
3974         * varasm.cc (assemble_function_label_raw): Do not call
3975         asan_function_start () without the current function.
3976
3977 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
3978
3979         PR target/113225
3980         * btfout.cc (btf_collect_datasec): Skip creating BTF info for
3981         extern and kernel_helper attributed function decls.
3982
3983 2024-01-08  Cupertino Miranda  <cupertino.miranda@oracle.com>
3984
3985         * btfout.cc (output_btf_strs): Changed.
3986
3987 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
3988
3989         * config/gcn/mkoffload.cc (main): Handle gfx1100
3990         when setting the default XNACK.
3991
3992 2024-01-08  Tobias Burnus  <tobias@codesourcery.com>
3993
3994         * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
3995         * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
3996         (ASM_SPEC): Handle gfx1100.
3997         * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
3998         (enum gcn_isa): Add ISA_RDNA3.
3999         (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
4000         * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4001         * config/gcn/gcn.cc (gcn_option_override,
4002         gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
4003         (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
4004         TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4005         (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
4006         with gfx1100.
4007         * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
4008         (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
4009         __gfx1100__.
4010         * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
4011         * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
4012         * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
4013         (isa_has_combined_avgprs, main): Handle gfx1100.
4014         * config/gcn/t-omp-device (isa): Add gfx1100.
4015
4016 2024-01-08  Richard Biener  <rguenther@suse.de>
4017
4018         * doc/invoke.texi (-mmovbe): Clarify.
4019
4020 2024-01-08  Richard Biener  <rguenther@suse.de>
4021
4022         PR tree-optimization/113026
4023         * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
4024         Avoid an epilog in more cases.
4025         * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
4026         epilogues niter upper bounds and estimates.
4027
4028 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
4029
4030         PR tree-optimization/113228
4031         * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
4032
4033 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
4034
4035         PR tree-optimization/113120
4036         * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
4037         large _BitInt zero INTEGER_CST PHI argument.
4038
4039 2024-01-08  Jakub Jelinek  <jakub@redhat.com>
4040
4041         PR tree-optimization/113119
4042         * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
4043         both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
4044         is before REALPART_EXPR.
4045
4046 2024-01-08  Georg-Johann Lay  <avr@gjlay.de>
4047
4048         PR target/112952
4049         * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
4050         range when diagnosing attribute "io" and "io_low" are out of range.
4051         (avr_eval_addr_attrib): Don't ICE on empty address at that place.
4052         (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
4053         in contexts other than static storage.
4054         (avr_asm_output_aligned_decl_common): Move output of decls with
4055         attribute "address", "io", and "io_low" to...
4056         (avr_output_addr_attrib): ...this new function.
4057         (avr_asm_asm_output_aligned_bss): Remove output for decls with
4058         attribute "address", "io", and "io_low".
4059         (avr_encode_section_info): Rectify handling of decls with attribute
4060         "address", "io", and "io_low".
4061
4062 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
4063
4064         * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
4065         (elf_flags): Remove XNACK from the default value.
4066         (main): Set a default XNACK according to the arch.
4067
4068 2024-01-08  Andrew Stubbs  <ams@codesourcery.com>
4069
4070         * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
4071         (process_asm): Don't count avgprs.
4072
4073 2024-01-08  Hongyu Wang  <hongyu.wang@intel.com>
4074
4075         * config/i386/i386.opt: Add supported sub-features.
4076         * doc/extend.texi: Add description for target attribute.
4077
4078 2024-01-08  Feng Wang  <wangfeng@eswincomputing.com>
4079
4080         * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
4081
4082 2024-01-07  Roger Sayle  <roger@nextmovesoftware.com>
4083             Uros Bizjak  <ubizjak@gmail.com>
4084
4085         PR target/113231
4086         * config/i386/i386-features.cc (compute_convert_gain): Include
4087         the overhead of explicit load and store (movd) instructions when
4088         converting non-store scalar operations with memory destinations.
4089         Various indentation whitespace fixes.
4090
4091 2024-01-07  Tamar Christina  <tamar.christina@arm.com>
4092
4093         * config/arm/neon.md (cbranch<mode>4): New.
4094
4095 2024-01-07  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4096
4097         * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
4098
4099 2024-01-06  Jiahao Xu  <xujiahao@loongson.cn>
4100
4101         * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
4102
4103 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4104
4105         PR target/113248
4106         * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
4107         Update the MAX_SEW.
4108
4109 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4110
4111         * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
4112         (variable_vectorized_p): Teach loop invariant.
4113         (has_unexpected_spills_p): Ditto.
4114
4115 2024-01-06  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4116
4117         * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
4118         * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
4119         * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
4120
4121 2024-01-05  Richard Sandiford  <richard.sandiford@arm.com>
4122
4123         PR target/113104
4124         * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
4125         (aarch64-vect-compare-costs): ...this.
4126         * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
4127         Replace with...
4128         (-param=aarch64-vect-compare-costs=): ...this new param.
4129         * config/aarch64/aarch64.cc (aarch64_override_options_internal):
4130         Don't disable it when vectorizing for Advanced SIMD only.
4131         (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
4132         whenever aarch64_vect_compare_costs is true.
4133
4134 2024-01-05  Lulu Cheng  <chenglulu@loongson.cn>
4135
4136         * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
4137         Modify the method of determining the memory offset of [x]vld/[x]vst.
4138         (lasx_mxst_<lasxfmt_f>): Likewise.
4139         * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
4140         (loongarch_address_insns): Likewise.
4141         * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
4142         (lsx_st_<lsxfmt_f>): Likewise.
4143         * config/loongarch/predicates.md (aq10b_operand): Likewise.
4144         (aq10h_operand): Likewise.
4145         (aq10w_operand): Likewise.
4146         (aq10d_operand): Likewise.
4147
4148 2024-01-05  Alex Coplan  <alex.coplan@arm.com>
4149
4150         PR target/113217
4151         * config/aarch64/aarch64-ldp-fusion.cc
4152         (ldp_bb_info::try_fuse_pair): If the second access can throw,
4153         narrow the move range to exactly that insn.
4154
4155 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
4156
4157         * asan.cc (asan_function_start): Drop switch_to_section ().
4158         (asan_emit_stack_protection): Set .LASANPC alignment.
4159         * config/i386/i386.cc: Use assemble_function_label_raw ()
4160         instead of ASM_OUTPUT_LABEL ().
4161         * config/s390/s390.cc (s390_asm_output_function_label):
4162         Likewise.
4163         * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
4164         * final.cc (final_start_function_1): Drop
4165         asan_function_start ().
4166         * output.h (assemble_function_label_raw): New function.
4167         * varasm.cc (assemble_function_label_raw): Likewise.
4168
4169 2024-01-05  Ilya Leoshkevich  <iii@linux.ibm.com>
4170
4171         * config/aarch64/aarch64.cc (aarch64_declare_function_name):
4172         Use ASM_OUTPUT_FUNCTION_LABEL ().
4173         * config/alpha/alpha.cc (alpha_start_function): Likewise.
4174         * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4175         * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
4176         * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4177         * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4178         * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
4179         * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
4180         * config/ia64/ia64.cc (ia64_start_function): Likewise.
4181         * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
4182         Likewise.
4183         * config/microblaze/microblaze.cc (microblaze_function_prologue):
4184         Likewise.
4185         * config/mips/mips.cc (mips_start_unique_function): Return the
4186         tree.
4187         (mips_start_function_definition): Use
4188         ASM_OUTPUT_FUNCTION_LABEL ().
4189         (mips_finish_stub): Pass the tree to
4190         mips_start_function_definition ().
4191         (mips16_build_function_stub): Likewise.
4192         (mips16_build_call_stub): Likewise.
4193         (mips_output_function_prologue): Likewise.
4194         * config/pa/pa.cc (pa_output_function_label): Use
4195         ASM_OUTPUT_FUNCTION_LABEL ().
4196         * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
4197         * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
4198         Likewise.
4199         (rs6000_xcoff_declare_function_name): Likewise.
4200
4201 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
4202
4203         PR tree-optimization/113201
4204         * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
4205         replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
4206
4207 2024-01-05  Jakub Jelinek  <jakub@redhat.com>
4208
4209         PR tree-optimization/90693
4210         * tree-ssa-math-opts.cc (match_single_bit_test): If
4211         tree_expr_nonzero_p (arg), remember it in the second argument to
4212         IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
4213         arg ^ (arg - 1) > arg - 1.
4214         * internal-fn.cc (expand_POPCOUNT): If second argument to
4215         IFN_POPCOUNT suggests arg is non-zero, try to expand it as
4216         arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
4217
4218 2024-01-05  Kito Cheng  <kito.cheng@sifive.com>
4219
4220         * config/riscv/riscv-v.cc (expand_load_store):
4221         Remove `value`.
4222         (expand_cond_len_op): Ditto.
4223         (expand_gather_scatter): Ditto.
4224         (expand_lanes_load_store): Ditto.
4225         (expand_fold_extract_last): Ditto.
4226
4227 2024-01-05  Pan Li  <pan2.li@intel.com>
4228
4229         Revert:
4230         2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
4231
4232         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
4233                                 Add new function_base for crypto vector.
4234         (class bitmanip): Ditto.
4235         (class b_reverse):Ditto.
4236         (class vwsll):   Ditto.
4237         (class clmul):   Ditto.
4238         (class vg_nhab):  Ditto.
4239         (class crypto_vv):Ditto.
4240         (class crypto_vi):Ditto.
4241         (class vaeskf2_vsm3c):Ditto.
4242         (class vsm3me): Ditto.
4243         (BASE): Add BASE declaration for crypto vector.
4244         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
4245         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
4246                                 Add crypto vector intrinsic definition.
4247         (vbrev): Ditto.
4248         (vclz): Ditto.
4249         (vctz): Ditto.
4250         (vwsll): Ditto.
4251         (vandn): Ditto.
4252         (vbrev8): Ditto.
4253         (vrev8): Ditto.
4254         (vrol): Ditto.
4255         (vror): Ditto.
4256         (vclmul): Ditto.
4257         (vclmulh): Ditto.
4258         (vghsh): Ditto.
4259         (vgmul): Ditto.
4260         (vaesef): Ditto.
4261         (vaesem): Ditto.
4262         (vaesdf): Ditto.
4263         (vaesdm): Ditto.
4264         (vaesz): Ditto.
4265         (vaeskf1): Ditto.
4266         (vaeskf2): Ditto.
4267         (vsha2ms): Ditto.
4268         (vsha2ch): Ditto.
4269         (vsha2cl): Ditto.
4270         (vsm4k): Ditto.
4271         (vsm4r): Ditto.
4272         (vsm3me): Ditto.
4273         (vsm3c): Ditto.
4274         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
4275                                 Add new function_shape for crypto vector.
4276         (struct crypto_vi_def): Ditto.
4277         (struct crypto_vv_no_op_type_def): Ditto.
4278         (SHAPE): Add SHAPE declaration of crypto vector.
4279         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
4280         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
4281                                 Add new data type for crypto vector.
4282         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4283         (vuint32mf2_t): Ditto.
4284         (vuint32m1_t): Ditto.
4285         (vuint32m2_t): Ditto.
4286         (vuint32m4_t): Ditto.
4287         (vuint32m8_t): Ditto.
4288         (vuint64m1_t): Ditto.
4289         (vuint64m2_t): Ditto.
4290         (vuint64m4_t): Ditto.
4291         (vuint64m8_t): Ditto.
4292         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
4293                                 Add new data struct for crypto vector.
4294         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4295         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
4296         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
4297
4298 2024-01-05  Feng Wang  <wangfeng@eswincomputing.com>
4299
4300         * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
4301                                 Add new function_base for crypto vector.
4302         (class bitmanip): Ditto.
4303         (class b_reverse):Ditto.
4304         (class vwsll):   Ditto.
4305         (class clmul):   Ditto.
4306         (class vg_nhab):  Ditto.
4307         (class crypto_vv):Ditto.
4308         (class crypto_vi):Ditto.
4309         (class vaeskf2_vsm3c):Ditto.
4310         (class vsm3me): Ditto.
4311         (BASE): Add BASE declaration for crypto vector.
4312         * config/riscv/riscv-vector-builtins-bases.h: Ditto.
4313         * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
4314                                 Add crypto vector intrinsic definition.
4315         (vbrev): Ditto.
4316         (vclz): Ditto.
4317         (vctz): Ditto.
4318         (vwsll): Ditto.
4319         (vandn): Ditto.
4320         (vbrev8): Ditto.
4321         (vrev8): Ditto.
4322         (vrol): Ditto.
4323         (vror): Ditto.
4324         (vclmul): Ditto.
4325         (vclmulh): Ditto.
4326         (vghsh): Ditto.
4327         (vgmul): Ditto.
4328         (vaesef): Ditto.
4329         (vaesem): Ditto.
4330         (vaesdf): Ditto.
4331         (vaesdm): Ditto.
4332         (vaesz): Ditto.
4333         (vaeskf1): Ditto.
4334         (vaeskf2): Ditto.
4335         (vsha2ms): Ditto.
4336         (vsha2ch): Ditto.
4337         (vsha2cl): Ditto.
4338         (vsm4k): Ditto.
4339         (vsm4r): Ditto.
4340         (vsm3me): Ditto.
4341         (vsm3c): Ditto.
4342         * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
4343                                 Add new function_shape for crypto vector.
4344         (struct crypto_vi_def): Ditto.
4345         (struct crypto_vv_no_op_type_def): Ditto.
4346         (SHAPE): Add SHAPE declaration of crypto vector.
4347         * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
4348         * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
4349                                 Add new data type for crypto vector.
4350         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4351         (vuint32mf2_t): Ditto.
4352         (vuint32m1_t): Ditto.
4353         (vuint32m2_t): Ditto.
4354         (vuint32m4_t): Ditto.
4355         (vuint32m8_t): Ditto.
4356         (vuint64m1_t): Ditto.
4357         (vuint64m2_t): Ditto.
4358         (vuint64m4_t): Ditto.
4359         (vuint64m8_t): Ditto.
4360         * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
4361                                 Add new data struct for crypto vector.
4362         (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
4363         (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
4364         * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
4365
4366 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4367
4368         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
4369
4370 2024-01-04  Andrew Pinski  <quic_apinski@quicinc.com>
4371
4372         PR tree-optimization/113186
4373         * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
4374         Match `^` with the `==` for 1bit integral types.
4375         * match.pd (maybe_cmp): Allow for bit_xor for 1bit
4376         integral types.
4377
4378 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
4379
4380         * toplev.cc (general_init): Pass lang_mask to urlifier.
4381
4382 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
4383
4384         * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
4385         param.
4386         (diagnostic_context::make_option_url): Update for lang_mask param.
4387         * gcc-urlifier.cc: Include "opts.h" and "options.h".
4388         (gcc_urlifier::gcc_urlifier): Add lang_mask param.
4389         (gcc_urlifier::m_lang_mask): New field.
4390         (doc_urls): Make static.
4391         (gcc_urlifier::get_url_for_quoted_text): Use label_text.
4392         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
4393         Look for an option by name before trying a binary search in
4394         doc_urls.
4395         (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
4396         (gcc_urlifier::get_url_suffix_for_option): New.
4397         (make_gcc_urlifier): Add lang_mask param.
4398         (selftest::gcc_urlifier_cc_tests): Update for above changes.
4399         Verify that a URL is found for "-fpack-struct".
4400         * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
4401         * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
4402         * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
4403         to make_gcc_urlifier.
4404         * opts-diagnostic.h (get_option_url): Add lang_mask param.
4405         * opts.cc (get_option_html_page): Remove special-casing for
4406         analyzer and LTO.
4407         (get_option_url_suffix): New.
4408         (get_option_url): Reimplement.
4409         (selftest::test_get_option_html_page): Rename to...
4410         (selftest::test_get_option_url_suffix): ...this and update for
4411         above changes.
4412         (selftest::opts_cc_tests): Update for renaming.
4413         * opts.h: Include "rich-location.h".
4414         (get_option_url_suffix): New decl.
4415
4416 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
4417
4418         * Makefile.in (ALL_OPT_URL_FILES): New.
4419         (GCC_OBJS): Add options-urls.o.
4420         (OBJS): Likewise.
4421         (OBJS-libcommon): Likewise.
4422         (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
4423         inputs to opt-gather.awk.
4424         (options-urls.cc): New Makefile target.
4425         * opt-functions.awk (url_suffix): New function.
4426         (lang_url_suffix): New function.
4427         * options-urls-cc-gen.awk: New file.
4428         * opts.h (get_opt_url_suffix): New decl.
4429
4430 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
4431
4432         * params.opt.urls: New file, autogenerated by
4433         regenerate-opt-urls.py.
4434
4435 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
4436
4437         * common.opt.urls: New file, autogenerated by
4438         regenerate-opt-urls.py.
4439         * config/aarch64/aarch64.opt.urls: Likewise.
4440         * config/alpha/alpha.opt.urls: Likewise.
4441         * config/alpha/elf.opt.urls: Likewise.
4442         * config/arc/arc-tables.opt.urls: Likewise.
4443         * config/arc/arc.opt.urls: Likewise.
4444         * config/arm/arm-tables.opt.urls: Likewise.
4445         * config/arm/arm.opt.urls: Likewise.
4446         * config/arm/vxworks.opt.urls: Likewise.
4447         * config/avr/avr.opt.urls: Likewise.
4448         * config/bpf/bpf.opt.urls: Likewise.
4449         * config/c6x/c6x-tables.opt.urls: Likewise.
4450         * config/c6x/c6x.opt.urls: Likewise.
4451         * config/cris/cris.opt.urls: Likewise.
4452         * config/cris/elf.opt.urls: Likewise.
4453         * config/csky/csky.opt.urls: Likewise.
4454         * config/csky/csky_tables.opt.urls: Likewise.
4455         * config/darwin.opt.urls: Likewise.
4456         * config/dragonfly.opt.urls: Likewise.
4457         * config/epiphany/epiphany.opt.urls: Likewise.
4458         * config/fr30/fr30.opt.urls: Likewise.
4459         * config/freebsd.opt.urls: Likewise.
4460         * config/frv/frv.opt.urls: Likewise.
4461         * config/ft32/ft32.opt.urls: Likewise.
4462         * config/fused-madd.opt.urls: Likewise.
4463         * config/g.opt.urls: Likewise.
4464         * config/gcn/gcn.opt.urls: Likewise.
4465         * config/gnu-user.opt.urls: Likewise.
4466         * config/h8300/h8300.opt.urls: Likewise.
4467         * config/hpux11.opt.urls: Likewise.
4468         * config/i386/cygming.opt.urls: Likewise.
4469         * config/i386/cygwin.opt.urls: Likewise.
4470         * config/i386/djgpp.opt.urls: Likewise.
4471         * config/i386/i386.opt.urls: Likewise.
4472         * config/i386/mingw-w64.opt.urls: Likewise.
4473         * config/i386/mingw.opt.urls: Likewise.
4474         * config/i386/nto.opt.urls: Likewise.
4475         * config/ia64/ia64.opt.urls: Likewise.
4476         * config/ia64/ilp32.opt.urls: Likewise.
4477         * config/ia64/vms.opt.urls: Likewise.
4478         * config/iq2000/iq2000.opt.urls: Likewise.
4479         * config/linux-android.opt.urls: Likewise.
4480         * config/linux.opt.urls: Likewise.
4481         * config/lm32/lm32.opt.urls: Likewise.
4482         * config/loongarch/loongarch.opt.urls: Likewise.
4483         * config/lynx.opt.urls: Likewise.
4484         * config/m32c/m32c.opt.urls: Likewise.
4485         * config/m32r/m32r.opt.urls: Likewise.
4486         * config/m68k/ieee.opt.urls: Likewise.
4487         * config/m68k/m68k-tables.opt.urls: Likewise.
4488         * config/m68k/m68k.opt.urls: Likewise.
4489         * config/m68k/uclinux.opt.urls: Likewise.
4490         * config/mcore/mcore.opt.urls: Likewise.
4491         * config/microblaze/microblaze.opt.urls: Likewise.
4492         * config/mips/mips-tables.opt.urls: Likewise.
4493         * config/mips/mips.opt.urls: Likewise.
4494         * config/mips/sde.opt.urls: Likewise.
4495         * config/mmix/mmix.opt.urls: Likewise.
4496         * config/mn10300/mn10300.opt.urls: Likewise.
4497         * config/moxie/moxie.opt.urls: Likewise.
4498         * config/msp430/msp430.opt.urls: Likewise.
4499         * config/nds32/nds32-elf.opt.urls: Likewise.
4500         * config/nds32/nds32-linux.opt.urls: Likewise.
4501         * config/nds32/nds32.opt.urls: Likewise.
4502         * config/netbsd-elf.opt.urls: Likewise.
4503         * config/netbsd.opt.urls: Likewise.
4504         * config/nios2/elf.opt.urls: Likewise.
4505         * config/nios2/nios2.opt.urls: Likewise.
4506         * config/nvptx/nvptx-gen.opt.urls: Likewise.
4507         * config/nvptx/nvptx.opt.urls: Likewise.
4508         * config/openbsd.opt.urls: Likewise.
4509         * config/or1k/elf.opt.urls: Likewise.
4510         * config/or1k/or1k.opt.urls: Likewise.
4511         * config/pa/pa-hpux.opt.urls: Likewise.
4512         * config/pa/pa-hpux1010.opt.urls: Likewise.
4513         * config/pa/pa-hpux1111.opt.urls: Likewise.
4514         * config/pa/pa-hpux1131.opt.urls: Likewise.
4515         * config/pa/pa.opt.urls: Likewise.
4516         * config/pa/pa64-hpux.opt.urls: Likewise.
4517         * config/pdp11/pdp11.opt.urls: Likewise.
4518         * config/pru/pru.opt.urls: Likewise.
4519         * config/riscv/riscv.opt.urls: Likewise.
4520         * config/rl78/rl78.opt.urls: Likewise.
4521         * config/rpath.opt.urls: Likewise.
4522         * config/rs6000/476.opt.urls: Likewise.
4523         * config/rs6000/aix64.opt.urls: Likewise.
4524         * config/rs6000/darwin.opt.urls: Likewise.
4525         * config/rs6000/linux64.opt.urls: Likewise.
4526         * config/rs6000/rs6000-tables.opt.urls: Likewise.
4527         * config/rs6000/rs6000.opt.urls: Likewise.
4528         * config/rs6000/sysv4.opt.urls: Likewise.
4529         * config/rtems.opt.urls: Likewise.
4530         * config/rx/elf.opt.urls: Likewise.
4531         * config/rx/rx.opt.urls: Likewise.
4532         * config/s390/s390.opt.urls: Likewise.
4533         * config/s390/tpf.opt.urls: Likewise.
4534         * config/sh/sh.opt.urls: Likewise.
4535         * config/sh/superh.opt.urls: Likewise.
4536         * config/sol2.opt.urls: Likewise.
4537         * config/sparc/long-double-switch.opt.urls: Likewise.
4538         * config/sparc/sparc.opt.urls: Likewise.
4539         * config/stormy16/stormy16.opt.urls: Likewise.
4540         * config/v850/v850.opt.urls: Likewise.
4541         * config/vax/elf.opt.urls: Likewise.
4542         * config/vax/vax.opt.urls: Likewise.
4543         * config/visium/visium.opt.urls: Likewise.
4544         * config/vms/vms.opt.urls: Likewise.
4545         * config/vxworks-smp.opt.urls: Likewise.
4546         * config/vxworks.opt.urls: Likewise.
4547         * config/xtensa/elf.opt.urls: Likewise.
4548         * config/xtensa/uclinux.opt.urls: Likewise.
4549         * config/xtensa/xtensa.opt.urls: Likewise.
4550         * config/bfin/bfin.opt.urls: New file.
4551
4552 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
4553
4554         * Makefile.in (OPT_URLS_HTML_DEPS): New.
4555         (regenerate-opt-urls): New target.
4556         (regenerate-opt-urls-unit-test): New target.
4557         * doc/options.texi (Option properties): Add UrlSuffix and
4558         description of regenerate-opt-urls.py.  Add LangUrlSuffix_*.
4559         * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
4560         reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
4561         and Makefile.in's OPT_URLS_HTML_DEPS.
4562         (Anatomy of a Target Back End): Add
4563         reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
4564         * regenerate-opt-urls.py: New file.
4565
4566 2024-01-04  David Malcolm  <dmalcolm@redhat.com>
4567
4568         * diagnostic-format-sarif.cc
4569         (sarif_builder::make_logical_location_object): Convert to...
4570         (make_sarif_logical_location_object): ...this.
4571         (sarif_builder::set_any_logical_locs_arr): Update for above
4572         change.
4573         (sarif_builder::make_thread_flow_location_object): Call
4574         maybe_add_sarif_properties on each diagnostic_event.
4575         * diagnostic-format-sarif.h (class logical_location): New forward
4576         decl.
4577         (make_sarif_logical_location_object): New decl.
4578         * diagnostic-path.h (class sarif_object): New forward decl.
4579         (diagnostic_event::maybe_add_sarif_properties): New vfunc.
4580
4581 2024-01-04  Kuan-Lin Chen  <rufus@andestech.com>
4582             Patrick Lin  <patrick@andestech.com>
4583             Rufus Chen  <rufus@andestech.com>
4584             Monk Chiang  <monk.chiang@sifive.com>
4585
4586         * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
4587         with Nan-boxing value.
4588         * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
4589
4590 2024-01-04  Roger Sayle  <roger@nextmovesoftware.com>
4591             Jeff Law  <jlaw@ventanamicro.com>
4592
4593         PR rtl-optimization/104914
4594         * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
4595         a sign or zero extension is only required if the modified field
4596         overlaps the SUBREG's most significant bit.  On MODE_REP_EXTENDED
4597         targets, don't refer to the temporarily incorrectly extended value
4598         using a SUBREG, but instead generate an explicit TRUNCATE rtx.
4599
4600 2024-01-04  Pan Li  <pan2.li@intel.com>
4601
4602         Revert:
4603         2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4604
4605         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
4606
4607 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4608
4609         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
4610
4611 2024-01-04  Kito Cheng  <kito.cheng@sifive.com>
4612
4613         * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
4614         offset of fcsr.
4615
4616 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4617
4618         * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
4619         (compute_nregs_for_mode): Refine LMUL.
4620         (max_number_of_live_regs): Ditto.
4621         (compute_estimated_lmul): Ditto.
4622         (has_unexpected_spills_p): Ditto.
4623
4624 2024-01-04  Li Wei  <liwei@loongson.cn>
4625
4626         * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
4627         Remove useless forward declaration.
4628         (loongarch_is_even_extraction): Remove useless forward declaration.
4629         (loongarch_try_expand_lsx_vshuf_const): Removed.
4630         (loongarch_expand_vec_perm_const_1): Merged.
4631         (loongarch_is_double_duplicate): Removed.
4632         (loongarch_is_center_extraction): Ditto.
4633         (loongarch_is_reversing_permutation): Ditto.
4634         (loongarch_is_di_misalign_extract): Ditto.
4635         (loongarch_is_si_misalign_extract): Ditto.
4636         (loongarch_is_lasx_lowpart_extract): Ditto.
4637         (loongarch_is_op_reverse_perm): Ditto.
4638         (loongarch_is_single_op_perm): Ditto.
4639         (loongarch_is_divisible_perm): Ditto.
4640         (loongarch_is_triple_stride_extract): Ditto.
4641         (loongarch_expand_vec_perm_const_2): Merged.
4642         (loongarch_expand_vec_perm_const): New.
4643         (loongarch_vectorize_vec_perm_const): Adjust.
4644
4645 2024-01-04  Sandra Loosemore  <sandra@codesourcery.com>
4646
4647         * omp-general.cc: Fix comment typos and misplaced/confusing
4648         comments.  Delete redundant include of omp-general.h.
4649
4650 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
4651
4652         PR rtl-optimization/104914
4653         * config/mips/mips.md (insqisi_extended): New patterns.
4654         (inshisi_extended): Ditto.
4655
4656 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
4657
4658         * config/mips/mips.cc (mips_insn_cost): New function.
4659
4660 2024-01-04  YunQiang Su  <syq@gcc.gnu.org>
4661
4662         * config/mips/mips.md (perf_ratio): New attribute.
4663
4664 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4665
4666         PR target/113206
4667         PR target/113209
4668         * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
4669         (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
4670         blocks belong to infinite loop.
4671         (pre_vsetvl::emit_vsetvl): Remove fake edges.
4672         * config/riscv/t-riscv: Add a new include file.
4673
4674 2024-01-04  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4675
4676         * config/riscv/vector.md: Fix indent.
4677
4678 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
4679
4680         * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
4681         OMP_CLAUSE__SIMDUID_.
4682         * tree.cc (omp_clause_num_ops): Update position of entry for
4683         OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
4684         (omp_clause_code_name): Likewise.
4685
4686 2024-01-03  Kwok Cheung Yeung  <kcy@codesourcery.com>
4687
4688         * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
4689         printing of FUNC_MAP/IND_FUNC_MAP labels.
4690
4691 2024-01-03  Jakub Jelinek  <jakub@redhat.com>
4692
4693         * gcc.cc (process_command): Update copyright notice dates.
4694         * gcov-dump.cc (print_version): Ditto.
4695         * gcov.cc (print_version): Ditto.
4696         * gcov-tool.cc (print_version): Ditto.
4697         * gengtype.cc (create_file): Ditto.
4698         * doc/cpp.texi: Bump @copying's copyright year.
4699         * doc/cppinternals.texi: Ditto.
4700         * doc/gcc.texi: Ditto.
4701         * doc/gccint.texi: Ditto.
4702         * doc/gcov.texi: Ditto.
4703         * doc/install.texi: Ditto.
4704         * doc/invoke.texi: Ditto.
4705
4706 2024-01-03  Xi Ruoyao  <xry111@xry111.site>
4707
4708         * config/loongarch/simd.md (fmax<mode>3): New define_insn.
4709         (fmin<mode>3): Likewise.
4710         (reduc_fmax_scal_<mode>3): New define_expand.
4711         (reduc_fmin_scal_<mode>3): Likewise.
4712
4713 2024-01-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4714
4715         PR target/113112
4716         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
4717         (max_number_of_live_regs): Ditto.
4718         (has_unexpected_spills_p): Ditto.
4719
4720 2024-01-02  Jun Sha (Joshua)  <cooper.joshua@linux.alibaba.com>
4721             Jin Ma  <jinma@linux.alibaba.com>
4722             Xianmiao Qu  <cooper.qu@linux.alibaba.com>
4723             Christoph Müllner  <christoph.muellner@vrull.eu>
4724
4725         * config/riscv/vector.md:
4726         Use vector_length_operand for vsetvl patterns.
4727
4728 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4729
4730         * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
4731         (expand_cond_len_op): Add simplification of dummy len and dummy mask.
4732
4733 2024-01-02  Di Zhao  <dizhao@os.amperecomputing.com>
4734
4735         * config/aarch64/aarch64-tuning-flags.def
4736         (AARCH64_EXTRA_TUNING_OPTION): New tuning option
4737         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
4738         * config/aarch64/aarch64.cc
4739         (aarch64_override_options_internal): Set
4740         param_fully_pipelined_fma according to tuning option.
4741         * config/aarch64/tuning_models/ampere1.h: Add
4742         AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
4743         * config/aarch64/tuning_models/ampere1a.h: Likewise.
4744         * config/aarch64/tuning_models/ampere1b.h: Likewise.
4745
4746 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
4747
4748         * config/riscv/vector-crypto.md: Modify copyright year.
4749
4750 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4751
4752         * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
4753
4754 2024-01-02  Lulu Cheng  <chenglulu@loongson.cn>
4755
4756         * config.in: Regenerate.
4757         * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
4758         * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
4759         Added TLS Le Relax support.
4760         (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
4761         * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
4762         * configure: Regenerate.
4763         * configure.ac: Check if binutils supports TLS le relax.
4764
4765 2024-01-02  Feng Wang  <wangfeng@eswincomputing.com>
4766
4767         * config/riscv/iterators.md: Add rotate insn name.
4768         * config/riscv/riscv.md: Add new insns name for crypto vector.
4769         * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
4770         * config/riscv/vector.md: Add the corresponding attr for crypto vector.
4771         * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
4772
4773 2024-01-02  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
4774
4775         PR target/113112
4776         * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
4777         pointer type liveness count.
4778 \f
4779 Copyright (C) 2024 Free Software Foundation, Inc.
4780
4781 Copying and distribution of this file, with or without modification,
4782 are permitted in any medium without royalty provided the copyright
4783 notice and this notice are preserved.