1 /* Perform branch target register load optimizations.
2 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
26 #include "hard-reg-set.h"
32 #include "insn-attr.h"
36 #include "diagnostic-core.h"
37 #include "tree-pass.h"
41 /* Target register optimizations - these are performed after reload. */
43 typedef struct btr_def_group_s
45 struct btr_def_group_s
*next
;
47 struct btr_def_s
*members
;
50 typedef struct btr_user_s
52 struct btr_user_s
*next
;
56 /* If INSN has a single use of a single branch register, then
57 USE points to it within INSN. If there is more than
58 one branch register use, or the use is in some way ambiguous,
62 int first_reaching_def
;
63 char other_use_this_block
;
66 /* btr_def structs appear on three lists:
67 1. A list of all btr_def structures (head is
68 ALL_BTR_DEFS, linked by the NEXT field).
69 2. A list of branch reg definitions per basic block (head is
70 BB_BTR_DEFS[i], linked by the NEXT_THIS_BB field).
71 3. A list of all branch reg definitions belonging to the same
72 group (head is in a BTR_DEF_GROUP struct, linked by
73 NEXT_THIS_GROUP field). */
75 typedef struct btr_def_s
77 struct btr_def_s
*next_this_bb
;
78 struct btr_def_s
*next_this_group
;
84 /* For a branch register setting insn that has a constant
85 source (i.e. a label), group links together all the
86 insns with the same source. For other branch register
87 setting insns, group is NULL. */
90 /* If this def has a reaching use which is not a simple use
91 in a branch instruction, then has_ambiguous_use will be true,
92 and we will not attempt to migrate this definition. */
93 char has_ambiguous_use
;
94 /* live_range is an approximation to the true live range for this
95 def/use web, because it records the set of blocks that contain
96 the live range. There could be other live ranges for the same
97 branch register in that set of blocks, either in the block
98 containing the def (before the def), or in a block containing
99 a use (after the use). If there are such other live ranges, then
100 other_btr_uses_before_def or other_btr_uses_after_use must be set true
102 char other_btr_uses_before_def
;
103 char other_btr_uses_after_use
;
104 /* We set own_end when we have moved a definition into a dominator.
105 Thus, when a later combination removes this definition again, we know
106 to clear out trs_live_at_end again. */
111 static int issue_rate
;
113 static int basic_block_freq (const_basic_block
);
114 static int insn_sets_btr_p (const_rtx
, int, int *);
115 static rtx
*find_btr_use (rtx
);
116 static int btr_referenced_p (rtx
, rtx
*);
117 static int find_btr_reference (rtx
*, void *);
118 static void find_btr_def_group (btr_def_group
*, btr_def
);
119 static btr_def
add_btr_def (fibheap_t
, basic_block
, int, rtx
,
120 unsigned int, int, btr_def_group
*);
121 static btr_user
new_btr_user (basic_block
, int, rtx
);
122 static void dump_hard_reg_set (HARD_REG_SET
);
123 static void dump_btrs_live (int);
124 static void note_other_use_this_block (unsigned int, btr_user
);
125 static void compute_defs_uses_and_gen (fibheap_t
, btr_def
*,btr_user
*,
126 sbitmap
*, sbitmap
*, HARD_REG_SET
*);
127 static void compute_kill (sbitmap
*, sbitmap
*, HARD_REG_SET
*);
128 static void compute_out (sbitmap
*bb_out
, sbitmap
*, sbitmap
*, int);
129 static void link_btr_uses (btr_def
*, btr_user
*, sbitmap
*, sbitmap
*, int);
130 static void build_btr_def_use_webs (fibheap_t
);
131 static int block_at_edge_of_live_range_p (int, btr_def
);
132 static void clear_btr_from_live_range (btr_def def
);
133 static void add_btr_to_live_range (btr_def
, int);
134 static void augment_live_range (bitmap
, HARD_REG_SET
*, basic_block
,
136 static int choose_btr (HARD_REG_SET
);
137 static void combine_btr_defs (btr_def
, HARD_REG_SET
*);
138 static void btr_def_live_range (btr_def
, HARD_REG_SET
*);
139 static void move_btr_def (basic_block
, int, btr_def
, bitmap
, HARD_REG_SET
*);
140 static int migrate_btr_def (btr_def
, int);
141 static void migrate_btr_defs (enum reg_class
, int);
142 static int can_move_up (const_basic_block
, const_rtx
, int);
143 static void note_btr_set (rtx
, const_rtx
, void *);
145 /* The following code performs code motion of target load instructions
146 (instructions that set branch target registers), to move them
147 forward away from the branch instructions and out of loops (or,
148 more generally, from a more frequently executed place to a less
149 frequently executed place).
150 Moving target load instructions further in front of the branch
151 instruction that uses the target register value means that the hardware
152 has a better chance of preloading the instructions at the branch
153 target by the time the branch is reached. This avoids bubbles
154 when a taken branch needs to flush out the pipeline.
155 Moving target load instructions out of loops means they are executed
158 /* An obstack to hold the def-use web data structures built up for
159 migrating branch target load instructions. */
160 static struct obstack migrate_btrl_obstack
;
162 /* Array indexed by basic block number, giving the set of registers
163 live in that block. */
164 static HARD_REG_SET
*btrs_live
;
166 /* Array indexed by basic block number, giving the set of registers live at
167 the end of that block, including any uses by a final jump insn, if any. */
168 static HARD_REG_SET
*btrs_live_at_end
;
170 /* Set of all target registers that we are willing to allocate. */
171 static HARD_REG_SET all_btrs
;
173 /* Provide lower and upper bounds for target register numbers, so that
174 we don't need to search through all the hard registers all the time. */
175 static int first_btr
, last_btr
;
179 /* Return an estimate of the frequency of execution of block bb. */
181 basic_block_freq (const_basic_block bb
)
183 return bb
->frequency
;
186 static rtx
*btr_reference_found
;
188 /* A subroutine of btr_referenced_p, called through for_each_rtx.
189 PREG is a pointer to an rtx that is to be excluded from the
190 traversal. If we find a reference to a target register anywhere
191 else, return 1, and put a pointer to it into btr_reference_found. */
193 find_btr_reference (rtx
*px
, void *preg
)
202 if (overlaps_hard_reg_set_p (all_btrs
, GET_MODE (x
), REGNO (x
)))
204 btr_reference_found
= px
;
210 /* Return nonzero if X references (sets or reads) any branch target register.
211 If EXCLUDEP is set, disregard any references within the rtx pointed to
212 by it. If returning nonzero, also set btr_reference_found as above. */
214 btr_referenced_p (rtx x
, rtx
*excludep
)
216 return for_each_rtx (&x
, find_btr_reference
, excludep
);
219 /* Return true if insn is an instruction that sets a target register.
220 if CHECK_CONST is true, only return true if the source is constant.
221 If such a set is found and REGNO is nonzero, assign the register number
222 of the destination register to *REGNO. */
224 insn_sets_btr_p (const_rtx insn
, int check_const
, int *regno
)
228 if (NONJUMP_INSN_P (insn
)
229 && (set
= single_set (insn
)))
231 rtx dest
= SET_DEST (set
);
232 rtx src
= SET_SRC (set
);
234 if (GET_CODE (dest
) == SUBREG
)
235 dest
= XEXP (dest
, 0);
238 && TEST_HARD_REG_BIT (all_btrs
, REGNO (dest
)))
240 gcc_assert (!btr_referenced_p (src
, NULL
));
242 if (!check_const
|| CONSTANT_P (src
))
245 *regno
= REGNO (dest
);
253 /* Find and return a use of a target register within an instruction INSN. */
255 find_btr_use (rtx insn
)
257 return btr_referenced_p (insn
, NULL
) ? btr_reference_found
: NULL
;
260 /* Find the group that the target register definition DEF belongs
261 to in the list starting with *ALL_BTR_DEF_GROUPS. If no such
262 group exists, create one. Add def to the group. */
264 find_btr_def_group (btr_def_group
*all_btr_def_groups
, btr_def def
)
266 if (insn_sets_btr_p (def
->insn
, 1, NULL
))
268 btr_def_group this_group
;
269 rtx def_src
= SET_SRC (single_set (def
->insn
));
271 /* ?? This linear search is an efficiency concern, particularly
272 as the search will almost always fail to find a match. */
273 for (this_group
= *all_btr_def_groups
;
275 this_group
= this_group
->next
)
276 if (rtx_equal_p (def_src
, this_group
->src
))
281 this_group
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_group_s
);
282 this_group
->src
= def_src
;
283 this_group
->members
= NULL
;
284 this_group
->next
= *all_btr_def_groups
;
285 *all_btr_def_groups
= this_group
;
287 def
->group
= this_group
;
288 def
->next_this_group
= this_group
->members
;
289 this_group
->members
= def
;
295 /* Create a new target register definition structure, for a definition in
296 block BB, instruction INSN, and insert it into ALL_BTR_DEFS. Return
297 the new definition. */
299 add_btr_def (fibheap_t all_btr_defs
, basic_block bb
, int insn_luid
, rtx insn
,
300 unsigned int dest_reg
, int other_btr_uses_before_def
,
301 btr_def_group
*all_btr_def_groups
)
303 btr_def this_def
= XOBNEW (&migrate_btrl_obstack
, struct btr_def_s
);
305 this_def
->luid
= insn_luid
;
306 this_def
->insn
= insn
;
307 this_def
->btr
= dest_reg
;
308 this_def
->cost
= basic_block_freq (bb
);
309 this_def
->has_ambiguous_use
= 0;
310 this_def
->other_btr_uses_before_def
= other_btr_uses_before_def
;
311 this_def
->other_btr_uses_after_use
= 0;
312 this_def
->next_this_bb
= NULL
;
313 this_def
->next_this_group
= NULL
;
314 this_def
->uses
= NULL
;
315 this_def
->live_range
= NULL
;
316 find_btr_def_group (all_btr_def_groups
, this_def
);
318 fibheap_insert (all_btr_defs
, -this_def
->cost
, this_def
);
322 "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n",
323 dest_reg
, bb
->index
, INSN_UID (insn
),
324 (this_def
->group
? "" : ":not const"), this_def
->cost
);
329 /* Create a new target register user structure, for a use in block BB,
330 instruction INSN. Return the new user. */
332 new_btr_user (basic_block bb
, int insn_luid
, rtx insn
)
334 /* This instruction reads target registers. We need
335 to decide whether we can replace all target register
338 rtx
*usep
= find_btr_use (PATTERN (insn
));
340 btr_user user
= NULL
;
344 int unambiguous_single_use
;
346 /* We want to ensure that USE is the only use of a target
347 register in INSN, so that we know that to rewrite INSN to use
348 a different target register, all we have to do is replace USE. */
349 unambiguous_single_use
= !btr_referenced_p (PATTERN (insn
), usep
);
350 if (!unambiguous_single_use
)
353 use
= usep
? *usep
: NULL_RTX
;
354 user
= XOBNEW (&migrate_btrl_obstack
, struct btr_user_s
);
356 user
->luid
= insn_luid
;
359 user
->other_use_this_block
= 0;
361 user
->n_reaching_defs
= 0;
362 user
->first_reaching_def
= -1;
366 fprintf (dump_file
, "Uses target reg: { bb %d, insn %d }",
367 bb
->index
, INSN_UID (insn
));
370 fprintf (dump_file
, ": unambiguous use of reg %d\n",
377 /* Write the contents of S to the dump file. */
379 dump_hard_reg_set (HARD_REG_SET s
)
382 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
383 if (TEST_HARD_REG_BIT (s
, reg
))
384 fprintf (dump_file
, " %d", reg
);
387 /* Write the set of target regs live in block BB to the dump file. */
389 dump_btrs_live (int bb
)
391 fprintf (dump_file
, "BB%d live:", bb
);
392 dump_hard_reg_set (btrs_live
[bb
]);
393 fprintf (dump_file
, "\n");
396 /* REGNO is the number of a branch target register that is being used or
397 set. USERS_THIS_BB is a list of preceding branch target register users;
398 If any of them use the same register, set their other_use_this_block
401 note_other_use_this_block (unsigned int regno
, btr_user users_this_bb
)
405 for (user
= users_this_bb
; user
!= NULL
; user
= user
->next
)
406 if (user
->use
&& REGNO (user
->use
) == regno
)
407 user
->other_use_this_block
= 1;
411 btr_user users_this_bb
;
412 HARD_REG_SET btrs_written_in_block
;
413 HARD_REG_SET btrs_live_in_block
;
418 /* Called via note_stores or directly to register stores into /
419 clobbers of a branch target register DEST that are not recognized as
420 straightforward definitions. DATA points to information about the
421 current basic block that needs updating. */
423 note_btr_set (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
, void *data
)
425 defs_uses_info
*info
= (defs_uses_info
*) data
;
426 int regno
, end_regno
;
430 regno
= REGNO (dest
);
431 end_regno
= END_HARD_REGNO (dest
);
432 for (; regno
< end_regno
; regno
++)
433 if (TEST_HARD_REG_BIT (all_btrs
, regno
))
435 note_other_use_this_block (regno
, info
->users_this_bb
);
436 SET_HARD_REG_BIT (info
->btrs_written_in_block
, regno
);
437 SET_HARD_REG_BIT (info
->btrs_live_in_block
, regno
);
438 sbitmap_difference (info
->bb_gen
, info
->bb_gen
,
439 info
->btr_defset
[regno
- first_btr
]);
444 compute_defs_uses_and_gen (fibheap_t all_btr_defs
, btr_def
*def_array
,
445 btr_user
*use_array
, sbitmap
*btr_defset
,
446 sbitmap
*bb_gen
, HARD_REG_SET
*btrs_written
)
448 /* Scan the code building up the set of all defs and all uses.
449 For each target register, build the set of defs of that register.
450 For each block, calculate the set of target registers
451 written in that block.
452 Also calculate the set of btrs ever live in that block.
456 btr_def_group all_btr_def_groups
= NULL
;
459 sbitmap_vector_zero (bb_gen
, last_basic_block
);
460 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
462 basic_block bb
= BASIC_BLOCK (i
);
464 btr_def defs_this_bb
= NULL
;
469 info
.users_this_bb
= NULL
;
470 info
.bb_gen
= bb_gen
[i
];
471 info
.btr_defset
= btr_defset
;
473 CLEAR_HARD_REG_SET (info
.btrs_live_in_block
);
474 CLEAR_HARD_REG_SET (info
.btrs_written_in_block
);
475 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
476 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
477 && REGNO_REG_SET_P (df_get_live_in (bb
), reg
))
478 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
480 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
482 insn
= NEXT_INSN (insn
), insn_luid
++)
487 int insn_uid
= INSN_UID (insn
);
489 if (insn_sets_btr_p (insn
, 0, ®no
))
491 btr_def def
= add_btr_def (
492 all_btr_defs
, bb
, insn_luid
, insn
, regno
,
493 TEST_HARD_REG_BIT (info
.btrs_live_in_block
, regno
),
494 &all_btr_def_groups
);
496 def_array
[insn_uid
] = def
;
497 SET_HARD_REG_BIT (info
.btrs_written_in_block
, regno
);
498 SET_HARD_REG_BIT (info
.btrs_live_in_block
, regno
);
499 sbitmap_difference (bb_gen
[i
], bb_gen
[i
],
500 btr_defset
[regno
- first_btr
]);
501 SET_BIT (bb_gen
[i
], insn_uid
);
502 def
->next_this_bb
= defs_this_bb
;
504 SET_BIT (btr_defset
[regno
- first_btr
], insn_uid
);
505 note_other_use_this_block (regno
, info
.users_this_bb
);
507 /* Check for the blockage emitted by expand_nl_goto_receiver. */
508 else if (cfun
->has_nonlocal_label
509 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
)
513 /* Do the equivalent of calling note_other_use_this_block
514 for every target register. */
515 for (user
= info
.users_this_bb
; user
!= NULL
;
518 user
->other_use_this_block
= 1;
519 IOR_HARD_REG_SET (info
.btrs_written_in_block
, all_btrs
);
520 IOR_HARD_REG_SET (info
.btrs_live_in_block
, all_btrs
);
521 sbitmap_zero (info
.bb_gen
);
525 if (btr_referenced_p (PATTERN (insn
), NULL
))
527 btr_user user
= new_btr_user (bb
, insn_luid
, insn
);
529 use_array
[insn_uid
] = user
;
531 SET_HARD_REG_BIT (info
.btrs_live_in_block
,
536 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
537 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
538 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
541 note_other_use_this_block (reg
,
543 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
545 note_stores (PATTERN (insn
), note_btr_set
, &info
);
547 user
->next
= info
.users_this_bb
;
548 info
.users_this_bb
= user
;
552 HARD_REG_SET
*clobbered
= &call_used_reg_set
;
553 HARD_REG_SET call_saved
;
554 rtx pat
= PATTERN (insn
);
557 /* Check for sibcall. */
558 if (GET_CODE (pat
) == PARALLEL
)
559 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
560 if (ANY_RETURN_P (XVECEXP (pat
, 0, i
)))
562 COMPL_HARD_REG_SET (call_saved
,
564 clobbered
= &call_saved
;
567 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
568 if (TEST_HARD_REG_BIT (*clobbered
, regno
))
569 note_btr_set (regno_reg_rtx
[regno
], NULL_RTX
, &info
);
575 COPY_HARD_REG_SET (btrs_live
[i
], info
.btrs_live_in_block
);
576 COPY_HARD_REG_SET (btrs_written
[i
], info
.btrs_written_in_block
);
578 REG_SET_TO_HARD_REG_SET (btrs_live_at_end
[i
], df_get_live_out (bb
));
579 /* If this block ends in a jump insn, add any uses or even clobbers
580 of branch target registers that it might have. */
581 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
) && ! INSN_P (insn
); )
582 insn
= PREV_INSN (insn
);
583 /* ??? for the fall-through edge, it would make sense to insert the
584 btr set on the edge, but that would require to split the block
585 early on so that we can distinguish between dominance from the fall
586 through edge - which can use the call-clobbered registers - from
587 dominance by the throw edge. */
588 if (can_throw_internal (insn
))
592 COPY_HARD_REG_SET (tmp
, call_used_reg_set
);
593 AND_HARD_REG_SET (tmp
, all_btrs
);
594 IOR_HARD_REG_SET (btrs_live_at_end
[i
], tmp
);
597 if (can_throw
|| JUMP_P (insn
))
601 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
602 if (refers_to_regno_p (regno
, regno
+1, insn
, NULL
))
603 SET_HARD_REG_BIT (btrs_live_at_end
[i
], regno
);
612 compute_kill (sbitmap
*bb_kill
, sbitmap
*btr_defset
,
613 HARD_REG_SET
*btrs_written
)
618 /* For each basic block, form the set BB_KILL - the set
619 of definitions that the block kills. */
620 sbitmap_vector_zero (bb_kill
, last_basic_block
);
621 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
623 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
624 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
625 && TEST_HARD_REG_BIT (btrs_written
[i
], regno
))
626 sbitmap_a_or_b (bb_kill
[i
], bb_kill
[i
],
627 btr_defset
[regno
- first_btr
]);
632 compute_out (sbitmap
*bb_out
, sbitmap
*bb_gen
, sbitmap
*bb_kill
, int max_uid
)
634 /* Perform iterative dataflow:
635 Initially, for all blocks, BB_OUT = BB_GEN.
637 BB_IN = union over predecessors of BB_OUT(pred)
638 BB_OUT = (BB_IN - BB_KILL) + BB_GEN
639 Iterate until the bb_out sets stop growing. */
642 sbitmap bb_in
= sbitmap_alloc (max_uid
);
644 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
645 sbitmap_copy (bb_out
[i
], bb_gen
[i
]);
651 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
653 sbitmap_union_of_preds (bb_in
, bb_out
, i
);
654 changed
|= sbitmap_union_of_diff_cg (bb_out
[i
], bb_gen
[i
],
658 sbitmap_free (bb_in
);
662 link_btr_uses (btr_def
*def_array
, btr_user
*use_array
, sbitmap
*bb_out
,
663 sbitmap
*btr_defset
, int max_uid
)
666 sbitmap reaching_defs
= sbitmap_alloc (max_uid
);
668 /* Link uses to the uses lists of all of their reaching defs.
669 Count up the number of reaching defs of each use. */
670 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
672 basic_block bb
= BASIC_BLOCK (i
);
676 sbitmap_union_of_preds (reaching_defs
, bb_out
, i
);
677 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
679 insn
= NEXT_INSN (insn
))
683 int insn_uid
= INSN_UID (insn
);
685 btr_def def
= def_array
[insn_uid
];
686 btr_user user
= use_array
[insn_uid
];
689 /* Remove all reaching defs of regno except
691 sbitmap_difference (reaching_defs
, reaching_defs
,
692 btr_defset
[def
->btr
- first_btr
]);
693 SET_BIT(reaching_defs
, insn_uid
);
698 /* Find all the reaching defs for this use. */
699 sbitmap reaching_defs_of_reg
= sbitmap_alloc(max_uid
);
700 unsigned int uid
= 0;
701 sbitmap_iterator sbi
;
705 reaching_defs_of_reg
,
707 btr_defset
[REGNO (user
->use
) - first_btr
]);
712 sbitmap_zero (reaching_defs_of_reg
);
713 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
714 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
715 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
717 sbitmap_a_or_b_and_c (reaching_defs_of_reg
,
718 reaching_defs_of_reg
,
720 btr_defset
[reg
- first_btr
]);
722 EXECUTE_IF_SET_IN_SBITMAP (reaching_defs_of_reg
, 0, uid
, sbi
)
724 btr_def def
= def_array
[uid
];
726 /* We now know that def reaches user. */
730 "Def in insn %d reaches use in insn %d\n",
733 user
->n_reaching_defs
++;
735 def
->has_ambiguous_use
= 1;
736 if (user
->first_reaching_def
!= -1)
737 { /* There is more than one reaching def. This is
738 a rare case, so just give up on this def/use
739 web when it occurs. */
740 def
->has_ambiguous_use
= 1;
741 def_array
[user
->first_reaching_def
]
742 ->has_ambiguous_use
= 1;
745 "(use %d has multiple reaching defs)\n",
749 user
->first_reaching_def
= uid
;
750 if (user
->other_use_this_block
)
751 def
->other_btr_uses_after_use
= 1;
752 user
->next
= def
->uses
;
755 sbitmap_free (reaching_defs_of_reg
);
762 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
763 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
764 && TEST_HARD_REG_BIT (call_used_reg_set
, regno
))
765 sbitmap_difference (reaching_defs
, reaching_defs
,
766 btr_defset
[regno
- first_btr
]);
771 sbitmap_free (reaching_defs
);
775 build_btr_def_use_webs (fibheap_t all_btr_defs
)
777 const int max_uid
= get_max_uid ();
778 btr_def
*def_array
= XCNEWVEC (btr_def
, max_uid
);
779 btr_user
*use_array
= XCNEWVEC (btr_user
, max_uid
);
780 sbitmap
*btr_defset
= sbitmap_vector_alloc (
781 (last_btr
- first_btr
) + 1, max_uid
);
782 sbitmap
*bb_gen
= sbitmap_vector_alloc (last_basic_block
, max_uid
);
783 HARD_REG_SET
*btrs_written
= XCNEWVEC (HARD_REG_SET
, last_basic_block
);
787 sbitmap_vector_zero (btr_defset
, (last_btr
- first_btr
) + 1);
789 compute_defs_uses_and_gen (all_btr_defs
, def_array
, use_array
, btr_defset
,
790 bb_gen
, btrs_written
);
792 bb_kill
= sbitmap_vector_alloc (last_basic_block
, max_uid
);
793 compute_kill (bb_kill
, btr_defset
, btrs_written
);
796 bb_out
= sbitmap_vector_alloc (last_basic_block
, max_uid
);
797 compute_out (bb_out
, bb_gen
, bb_kill
, max_uid
);
799 sbitmap_vector_free (bb_gen
);
800 sbitmap_vector_free (bb_kill
);
802 link_btr_uses (def_array
, use_array
, bb_out
, btr_defset
, max_uid
);
804 sbitmap_vector_free (bb_out
);
805 sbitmap_vector_free (btr_defset
);
810 /* Return true if basic block BB contains the start or end of the
811 live range of the definition DEF, AND there are other live
812 ranges of the same target register that include BB. */
814 block_at_edge_of_live_range_p (int bb
, btr_def def
)
816 if (def
->other_btr_uses_before_def
&& BASIC_BLOCK (bb
) == def
->bb
)
818 else if (def
->other_btr_uses_after_use
)
821 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
822 if (BASIC_BLOCK (bb
) == user
->bb
)
828 /* We are removing the def/use web DEF. The target register
829 used in this web is therefore no longer live in the live range
830 of this web, so remove it from the live set of all basic blocks
831 in the live range of the web.
832 Blocks at the boundary of the live range may contain other live
833 ranges for the same target register, so we have to be careful
834 to remove the target register from the live set of these blocks
835 only if they do not contain other live ranges for the same register. */
837 clear_btr_from_live_range (btr_def def
)
842 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
844 if ((!def
->other_btr_uses_before_def
845 && !def
->other_btr_uses_after_use
)
846 || !block_at_edge_of_live_range_p (bb
, def
))
848 CLEAR_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
849 CLEAR_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
855 CLEAR_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
859 /* We are adding the def/use web DEF. Add the target register used
860 in this web to the live set of all of the basic blocks that contain
861 the live range of the web.
862 If OWN_END is set, also show that the register is live from our
863 definitions at the end of the basic block where it is defined. */
865 add_btr_to_live_range (btr_def def
, int own_end
)
870 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
872 SET_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
873 SET_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
879 SET_HARD_REG_BIT (btrs_live_at_end
[def
->bb
->index
], def
->btr
);
884 /* Update a live range to contain the basic block NEW_BLOCK, and all
885 blocks on paths between the existing live range and NEW_BLOCK.
886 HEAD is a block contained in the existing live range that dominates
887 all other blocks in the existing live range.
888 Also add to the set BTRS_LIVE_IN_RANGE all target registers that
889 are live in the blocks that we add to the live range.
890 If FULL_RANGE is set, include the full live range of NEW_BB;
891 otherwise, if NEW_BB dominates HEAD_BB, only add registers that
892 are life at the end of NEW_BB for NEW_BB itself.
893 It is a precondition that either NEW_BLOCK dominates HEAD,or
894 HEAD dom NEW_BLOCK. This is used to speed up the
895 implementation of this function. */
897 augment_live_range (bitmap live_range
, HARD_REG_SET
*btrs_live_in_range
,
898 basic_block head_bb
, basic_block new_bb
, int full_range
)
900 basic_block
*worklist
, *tos
;
902 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks
+ 1);
904 if (dominated_by_p (CDI_DOMINATORS
, new_bb
, head_bb
))
906 if (new_bb
== head_bb
)
909 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_bb
->index
]);
919 int new_block
= new_bb
->index
;
921 gcc_assert (dominated_by_p (CDI_DOMINATORS
, head_bb
, new_bb
));
923 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[head_bb
->index
]);
924 bitmap_set_bit (live_range
, new_block
);
925 /* A previous btr migration could have caused a register to be
926 live just at the end of new_block which we need in full, so
927 use trs_live_at_end even if full_range is set. */
928 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live_at_end
[new_block
]);
930 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_block
]);
934 "Adding end of block %d and rest of %d to live range\n",
935 new_block
, head_bb
->index
);
936 fprintf (dump_file
,"Now live btrs are ");
937 dump_hard_reg_set (*btrs_live_in_range
);
938 fprintf (dump_file
, "\n");
940 FOR_EACH_EDGE (e
, ei
, head_bb
->preds
)
944 while (tos
!= worklist
)
946 basic_block bb
= *--tos
;
947 if (!bitmap_bit_p (live_range
, bb
->index
))
952 bitmap_set_bit (live_range
, bb
->index
);
953 IOR_HARD_REG_SET (*btrs_live_in_range
,
954 btrs_live
[bb
->index
]);
955 /* A previous btr migration could have caused a register to be
956 live just at the end of a block which we need in full. */
957 IOR_HARD_REG_SET (*btrs_live_in_range
,
958 btrs_live_at_end
[bb
->index
]);
962 "Adding block %d to live range\n", bb
->index
);
963 fprintf (dump_file
,"Now live btrs are ");
964 dump_hard_reg_set (*btrs_live_in_range
);
965 fprintf (dump_file
, "\n");
968 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
970 basic_block pred
= e
->src
;
971 if (!bitmap_bit_p (live_range
, pred
->index
))
980 /* Return the most desirable target register that is not in
981 the set USED_BTRS. */
983 choose_btr (HARD_REG_SET used_btrs
)
987 if (!hard_reg_set_subset_p (all_btrs
, used_btrs
))
988 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
990 #ifdef REG_ALLOC_ORDER
991 int regno
= reg_alloc_order
[i
];
995 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
996 && !TEST_HARD_REG_BIT (used_btrs
, regno
))
1002 /* Calculate the set of basic blocks that contain the live range of
1003 the def/use web DEF.
1004 Also calculate the set of target registers that are live at time
1005 in this live range, but ignore the live range represented by DEF
1006 when calculating this set. */
1008 btr_def_live_range (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1010 if (!def
->live_range
)
1014 def
->live_range
= BITMAP_ALLOC (NULL
);
1016 bitmap_set_bit (def
->live_range
, def
->bb
->index
);
1017 COPY_HARD_REG_SET (*btrs_live_in_range
,
1018 (flag_btr_bb_exclusive
1019 ? btrs_live
: btrs_live_at_end
)[def
->bb
->index
]);
1021 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1022 augment_live_range (def
->live_range
, btrs_live_in_range
,
1024 (flag_btr_bb_exclusive
1025 || user
->insn
!= BB_END (def
->bb
)
1026 || !JUMP_P (user
->insn
)));
1030 /* def->live_range is accurate, but we need to recompute
1031 the set of target registers live over it, because migration
1032 of other PT instructions may have affected it.
1035 unsigned def_bb
= flag_btr_bb_exclusive
? -1 : def
->bb
->index
;
1038 CLEAR_HARD_REG_SET (*btrs_live_in_range
);
1039 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
1041 IOR_HARD_REG_SET (*btrs_live_in_range
,
1043 ? btrs_live_at_end
: btrs_live
) [bb
]);
1046 if (!def
->other_btr_uses_before_def
&&
1047 !def
->other_btr_uses_after_use
)
1048 CLEAR_HARD_REG_BIT (*btrs_live_in_range
, def
->btr
);
1051 /* Merge into the def/use web DEF any other def/use webs in the same
1052 group that are dominated by DEF, provided that there is a target
1053 register available to allocate to the merged web. */
1055 combine_btr_defs (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1059 for (other_def
= def
->group
->members
;
1061 other_def
= other_def
->next_this_group
)
1063 if (other_def
!= def
1064 && other_def
->uses
!= NULL
1065 && ! other_def
->has_ambiguous_use
1066 && dominated_by_p (CDI_DOMINATORS
, other_def
->bb
, def
->bb
))
1068 /* def->bb dominates the other def, so def and other_def could
1070 /* Merge their live ranges, and get the set of
1071 target registers live over the merged range. */
1073 HARD_REG_SET combined_btrs_live
;
1074 bitmap combined_live_range
= BITMAP_ALLOC (NULL
);
1077 if (other_def
->live_range
== NULL
)
1079 HARD_REG_SET dummy_btrs_live_in_range
;
1080 btr_def_live_range (other_def
, &dummy_btrs_live_in_range
);
1082 COPY_HARD_REG_SET (combined_btrs_live
, *btrs_live_in_range
);
1083 bitmap_copy (combined_live_range
, def
->live_range
);
1085 for (user
= other_def
->uses
; user
!= NULL
; user
= user
->next
)
1086 augment_live_range (combined_live_range
, &combined_btrs_live
,
1088 (flag_btr_bb_exclusive
1089 || user
->insn
!= BB_END (def
->bb
)
1090 || !JUMP_P (user
->insn
)));
1092 btr
= choose_btr (combined_btrs_live
);
1095 /* We can combine them. */
1098 "Combining def in insn %d with def in insn %d\n",
1099 INSN_UID (other_def
->insn
), INSN_UID (def
->insn
));
1102 user
= other_def
->uses
;
1103 while (user
!= NULL
)
1105 btr_user next
= user
->next
;
1107 user
->next
= def
->uses
;
1111 /* Combining def/use webs can make target registers live
1112 after uses where they previously were not. This means
1113 some REG_DEAD notes may no longer be correct. We could
1114 be more precise about this if we looked at the combined
1115 live range, but here I just delete any REG_DEAD notes
1116 in case they are no longer correct. */
1117 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1118 remove_note (user
->insn
,
1119 find_regno_note (user
->insn
, REG_DEAD
,
1120 REGNO (user
->use
)));
1121 clear_btr_from_live_range (other_def
);
1122 other_def
->uses
= NULL
;
1123 bitmap_copy (def
->live_range
, combined_live_range
);
1124 if (other_def
->btr
== btr
&& other_def
->other_btr_uses_after_use
)
1125 def
->other_btr_uses_after_use
= 1;
1126 COPY_HARD_REG_SET (*btrs_live_in_range
, combined_btrs_live
);
1128 /* Delete the old target register initialization. */
1129 delete_insn (other_def
->insn
);
1132 BITMAP_FREE (combined_live_range
);
1137 /* Move the definition DEF from its current position to basic
1138 block NEW_DEF_BB, and modify it to use branch target register BTR.
1139 Delete the old defining insn, and insert a new one in NEW_DEF_BB.
1140 Update all reaching uses of DEF in the RTL to use BTR.
1141 If this new position means that other defs in the
1142 same group can be combined with DEF then combine them. */
1144 move_btr_def (basic_block new_def_bb
, int btr
, btr_def def
, bitmap live_range
,
1145 HARD_REG_SET
*btrs_live_in_range
)
1147 /* We can move the instruction.
1148 Set a target register in block NEW_DEF_BB to the value
1149 needed for this target register definition.
1150 Replace all uses of the old target register definition by
1151 uses of the new definition. Delete the old definition. */
1152 basic_block b
= new_def_bb
;
1153 rtx insp
= BB_HEAD (b
);
1154 rtx old_insn
= def
->insn
;
1158 enum machine_mode btr_mode
;
1163 fprintf(dump_file
, "migrating to basic block %d, using reg %d\n",
1164 new_def_bb
->index
, btr
);
1166 clear_btr_from_live_range (def
);
1168 def
->bb
= new_def_bb
;
1170 def
->cost
= basic_block_freq (new_def_bb
);
1171 bitmap_copy (def
->live_range
, live_range
);
1172 combine_btr_defs (def
, btrs_live_in_range
);
1174 def
->other_btr_uses_before_def
1175 = TEST_HARD_REG_BIT (btrs_live
[b
->index
], btr
) ? 1 : 0;
1176 add_btr_to_live_range (def
, 1);
1178 insp
= NEXT_INSN (insp
);
1179 /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some
1180 optimizations can result in insp being both first and last insn of
1182 /* ?? some assertions to check that insp is sensible? */
1184 if (def
->other_btr_uses_before_def
)
1187 for (insp
= BB_END (b
); ! INSN_P (insp
); insp
= PREV_INSN (insp
))
1188 gcc_assert (insp
!= BB_HEAD (b
));
1190 if (JUMP_P (insp
) || can_throw_internal (insp
))
1191 insp
= PREV_INSN (insp
);
1194 set
= single_set (old_insn
);
1195 src
= SET_SRC (set
);
1196 btr_mode
= GET_MODE (SET_DEST (set
));
1197 btr_rtx
= gen_rtx_REG (btr_mode
, btr
);
1199 new_insn
= gen_move_insn (btr_rtx
, src
);
1201 /* Insert target register initialization at head of basic block. */
1202 def
->insn
= emit_insn_after (new_insn
, insp
);
1204 df_set_regs_ever_live (btr
, true);
1207 fprintf (dump_file
, "New pt is insn %d, inserted after insn %d\n",
1208 INSN_UID (def
->insn
), INSN_UID (insp
));
1210 /* Delete the old target register initialization. */
1211 delete_insn (old_insn
);
1213 /* Replace each use of the old target register by a use of the new target
1215 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1217 /* Some extra work here to ensure consistent modes, because
1218 it seems that a target register REG rtx can be given a different
1219 mode depending on the context (surely that should not be
1221 rtx replacement_rtx
;
1222 if (GET_MODE (user
->use
) == GET_MODE (btr_rtx
)
1223 || GET_MODE (user
->use
) == VOIDmode
)
1224 replacement_rtx
= btr_rtx
;
1226 replacement_rtx
= gen_rtx_REG (GET_MODE (user
->use
), btr
);
1227 validate_replace_rtx (user
->use
, replacement_rtx
, user
->insn
);
1228 user
->use
= replacement_rtx
;
1232 /* We anticipate intra-block scheduling to be done. See if INSN could move
1233 up within BB by N_INSNS. */
1235 can_move_up (const_basic_block bb
, const_rtx insn
, int n_insns
)
1237 while (insn
!= BB_HEAD (bb
) && n_insns
> 0)
1239 insn
= PREV_INSN (insn
);
1240 /* ??? What if we have an anti-dependency that actually prevents the
1241 scheduler from doing the move? We'd like to re-allocate the register,
1242 but not necessarily put the load into another basic block. */
1246 return n_insns
<= 0;
1249 /* Attempt to migrate the target register definition DEF to an
1250 earlier point in the flowgraph.
1252 It is a precondition of this function that DEF is migratable:
1253 i.e. it has a constant source, and all uses are unambiguous.
1255 Only migrations that reduce the cost of DEF will be made.
1256 MIN_COST is the lower bound on the cost of the DEF after migration.
1257 If we migrate DEF so that its cost falls below MIN_COST,
1258 then we do not attempt to migrate further. The idea is that
1259 we migrate definitions in a priority order based on their cost,
1260 when the cost of this definition falls below MIN_COST, then
1261 there is another definition with cost == MIN_COST which now
1262 has a higher priority than this definition.
1264 Return nonzero if there may be benefit from attempting to
1265 migrate this DEF further (i.e. we have reduced the cost below
1266 MIN_COST, but we may be able to reduce it further).
1267 Return zero if no further migration is possible. */
1269 migrate_btr_def (btr_def def
, int min_cost
)
1272 HARD_REG_SET btrs_live_in_range
;
1273 int btr_used_near_def
= 0;
1274 int def_basic_block_freq
;
1275 basic_block attempt
;
1283 "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ",
1284 INSN_UID (def
->insn
), def
->cost
, min_cost
);
1286 if (!def
->group
|| def
->has_ambiguous_use
)
1287 /* These defs are not migratable. */
1290 fprintf (dump_file
, "it's not migratable\n");
1295 /* We have combined this def with another in the same group, so
1296 no need to consider it further.
1300 fprintf (dump_file
, "it's already combined with another pt\n");
1304 btr_def_live_range (def
, &btrs_live_in_range
);
1305 live_range
= BITMAP_ALLOC (NULL
);
1306 bitmap_copy (live_range
, def
->live_range
);
1308 #ifdef INSN_SCHEDULING
1309 def_latency
= insn_default_latency (def
->insn
) * issue_rate
;
1311 def_latency
= issue_rate
;
1314 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1316 if (user
->bb
== def
->bb
1317 && user
->luid
> def
->luid
1318 && (def
->luid
+ def_latency
) > user
->luid
1319 && ! can_move_up (def
->bb
, def
->insn
,
1320 (def
->luid
+ def_latency
) - user
->luid
))
1322 btr_used_near_def
= 1;
1327 def_basic_block_freq
= basic_block_freq (def
->bb
);
1329 for (attempt
= get_immediate_dominator (CDI_DOMINATORS
, def
->bb
);
1330 !give_up
&& attempt
&& attempt
!= ENTRY_BLOCK_PTR
&& def
->cost
>= min_cost
;
1331 attempt
= get_immediate_dominator (CDI_DOMINATORS
, attempt
))
1333 /* Try to move the instruction that sets the target register into
1334 basic block ATTEMPT. */
1335 int try_freq
= basic_block_freq (attempt
);
1339 /* If ATTEMPT has abnormal edges, skip it. */
1340 FOR_EACH_EDGE (e
, ei
, attempt
->succs
)
1341 if (e
->flags
& EDGE_COMPLEX
)
1347 fprintf (dump_file
, "trying block %d ...", attempt
->index
);
1349 if (try_freq
< def_basic_block_freq
1350 || (try_freq
== def_basic_block_freq
&& btr_used_near_def
))
1353 augment_live_range (live_range
, &btrs_live_in_range
, def
->bb
, attempt
,
1354 flag_btr_bb_exclusive
);
1357 fprintf (dump_file
, "Now btrs live in range are: ");
1358 dump_hard_reg_set (btrs_live_in_range
);
1359 fprintf (dump_file
, "\n");
1361 btr
= choose_btr (btrs_live_in_range
);
1364 move_btr_def (attempt
, btr
, def
, live_range
, &btrs_live_in_range
);
1365 bitmap_copy(live_range
, def
->live_range
);
1366 btr_used_near_def
= 0;
1368 def_basic_block_freq
= basic_block_freq (def
->bb
);
1372 /* There are no free target registers available to move
1373 this far forward, so give up */
1377 "giving up because there are no free target registers\n");
1386 fprintf (dump_file
, "failed to move\n");
1388 BITMAP_FREE (live_range
);
1392 /* Attempt to move instructions that set target registers earlier
1393 in the flowgraph, away from their corresponding uses. */
1395 migrate_btr_defs (enum reg_class btr_class
, int allow_callee_save
)
1397 fibheap_t all_btr_defs
= fibheap_new ();
1400 gcc_obstack_init (&migrate_btrl_obstack
);
1405 for (i
= NUM_FIXED_BLOCKS
; i
< last_basic_block
; i
++)
1407 basic_block bb
= BASIC_BLOCK (i
);
1409 "Basic block %d: count = " HOST_WIDEST_INT_PRINT_DEC
1410 " loop-depth = %d idom = %d\n",
1411 i
, (HOST_WIDEST_INT
) bb
->count
, bb
->loop_depth
,
1412 get_immediate_dominator (CDI_DOMINATORS
, bb
)->index
);
1416 CLEAR_HARD_REG_SET (all_btrs
);
1417 for (first_btr
= -1, reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
1418 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) btr_class
], reg
)
1419 && (allow_callee_save
|| call_used_regs
[reg
]
1420 || df_regs_ever_live_p (reg
)))
1422 SET_HARD_REG_BIT (all_btrs
, reg
);
1428 btrs_live
= XCNEWVEC (HARD_REG_SET
, last_basic_block
);
1429 btrs_live_at_end
= XCNEWVEC (HARD_REG_SET
, last_basic_block
);
1431 build_btr_def_use_webs (all_btr_defs
);
1433 while (!fibheap_empty (all_btr_defs
))
1435 btr_def def
= (btr_def
) fibheap_extract_min (all_btr_defs
);
1436 int min_cost
= -fibheap_min_key (all_btr_defs
);
1437 if (migrate_btr_def (def
, min_cost
))
1439 fibheap_insert (all_btr_defs
, -def
->cost
, (void *) def
);
1443 "Putting insn %d back on queue with priority %d\n",
1444 INSN_UID (def
->insn
), def
->cost
);
1448 BITMAP_FREE (def
->live_range
);
1452 free (btrs_live_at_end
);
1453 obstack_free (&migrate_btrl_obstack
, NULL
);
1454 fibheap_delete (all_btr_defs
);
1458 branch_target_load_optimize (bool after_prologue_epilogue_gen
)
1460 enum reg_class klass
1461 = (enum reg_class
) targetm
.branch_target_register_class ();
1462 if (klass
!= NO_REGS
)
1464 /* Initialize issue_rate. */
1465 if (targetm
.sched
.issue_rate
)
1466 issue_rate
= targetm
.sched
.issue_rate ();
1470 if (!after_prologue_epilogue_gen
)
1472 /* Build the CFG for migrate_btr_defs. */
1474 /* This may or may not be needed, depending on where we
1476 cleanup_cfg (optimize
? CLEANUP_EXPENSIVE
: 0);
1482 /* Dominator info is also needed for migrate_btr_def. */
1483 calculate_dominance_info (CDI_DOMINATORS
);
1484 migrate_btr_defs (klass
,
1485 (targetm
.branch_target_register_callee_saved
1486 (after_prologue_epilogue_gen
)));
1488 free_dominance_info (CDI_DOMINATORS
);
1493 gate_handle_branch_target_load_optimize1 (void)
1495 return flag_branch_target_load_optimize
;
1500 rest_of_handle_branch_target_load_optimize1 (void)
1502 branch_target_load_optimize (epilogue_completed
);
1506 struct rtl_opt_pass pass_branch_target_load_optimize1
=
1511 gate_handle_branch_target_load_optimize1
, /* gate */
1512 rest_of_handle_branch_target_load_optimize1
, /* execute */
1515 0, /* static_pass_number */
1516 TV_NONE
, /* tv_id */
1517 0, /* properties_required */
1518 0, /* properties_provided */
1519 0, /* properties_destroyed */
1520 0, /* todo_flags_start */
1521 TODO_verify_rtl_sharing
|
1522 TODO_ggc_collect
, /* todo_flags_finish */
1527 gate_handle_branch_target_load_optimize2 (void)
1529 return (optimize
> 0 && flag_branch_target_load_optimize2
);
1534 rest_of_handle_branch_target_load_optimize2 (void)
1536 static int warned
= 0;
1538 /* Leave this a warning for now so that it is possible to experiment
1539 with running this pass twice. In 3.6, we should either make this
1540 an error, or use separate dump files. */
1541 if (flag_branch_target_load_optimize
1542 && flag_branch_target_load_optimize2
1545 warning (0, "branch target register load optimization is not intended "
1551 branch_target_load_optimize (epilogue_completed
);
1555 struct rtl_opt_pass pass_branch_target_load_optimize2
=
1560 gate_handle_branch_target_load_optimize2
, /* gate */
1561 rest_of_handle_branch_target_load_optimize2
, /* execute */
1564 0, /* static_pass_number */
1565 TV_NONE
, /* tv_id */
1566 0, /* properties_required */
1567 0, /* properties_provided */
1568 0, /* properties_destroyed */
1569 0, /* todo_flags_start */
1570 TODO_ggc_collect
, /* todo_flags_finish */