1 /* Perform branch target register load optimizations.
2 Copyright (C) 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
37 #include "insn-attr.h"
42 /* Target register optimizations - these are performed after reload. */
44 typedef struct btr_def_group_s
46 struct btr_def_group_s
*next
;
48 struct btr_def_s
*members
;
51 typedef struct btr_user_s
53 struct btr_user_s
*next
;
57 /* If INSN has a single use of a single branch register, then
58 USE points to it within INSN. If there is more than
59 one branch register use, or the use is in some way ambiguous,
63 int first_reaching_def
;
64 char other_use_this_block
;
67 /* btr_def structs appear on three lists:
68 1. A list of all btr_def structures (head is
69 ALL_BTR_DEFS, linked by the NEXT field).
70 2. A list of branch reg definitions per basic block (head is
71 BB_BTR_DEFS[i], linked by the NEXT_THIS_BB field).
72 3. A list of all branch reg definitions belonging to the same
73 group (head is in a BTR_DEF_GROUP struct, linked by
74 NEXT_THIS_GROUP field). */
76 typedef struct btr_def_s
78 struct btr_def_s
*next_this_bb
;
79 struct btr_def_s
*next_this_group
;
85 /* For a branch register setting insn that has a constant
86 source (i.e. a label), group links together all the
87 insns with the same source. For other branch register
88 setting insns, group is NULL. */
91 /* If this def has a reaching use which is not a simple use
92 in a branch instruction, then has_ambiguous_use will be true,
93 and we will not attempt to migrate this definition. */
94 char has_ambiguous_use
;
95 /* live_range is an approximation to the true live range for this
96 def/use web, because it records the set of blocks that contain
97 the live range. There could be other live ranges for the same
98 branch register in that set of blocks, either in the block
99 containing the def (before the def), or in a block containing
100 a use (after the use). If there are such other live ranges, then
101 other_btr_uses_before_def or other_btr_uses_after_use must be set true
103 char other_btr_uses_before_def
;
104 char other_btr_uses_after_use
;
108 static int issue_rate
;
110 static int basic_block_freq (basic_block
);
111 static int insn_sets_btr_p (rtx
, int, int *);
112 static rtx
*find_btr_use (rtx
);
113 static int btr_referenced_p (rtx
, rtx
*);
114 static int find_btr_reference (rtx
*, void *);
115 static void find_btr_def_group (btr_def_group
*, btr_def
);
116 static btr_def
add_btr_def (fibheap_t
, basic_block
, int, rtx
,
117 unsigned int, int, btr_def_group
*);
118 static btr_user
new_btr_user (basic_block
, int, rtx
);
119 static void dump_hard_reg_set (HARD_REG_SET
);
120 static void dump_btrs_live (int);
121 static void note_other_use_this_block (unsigned int, btr_user
);
122 static void compute_defs_uses_and_gen (fibheap_t
, btr_def
*,btr_user
*,
123 sbitmap
*, sbitmap
*, HARD_REG_SET
*);
124 static void compute_kill (sbitmap
*, sbitmap
*, HARD_REG_SET
*);
125 static void compute_out (sbitmap
*bb_out
, sbitmap
*, sbitmap
*, int);
126 static void link_btr_uses (btr_def
*, btr_user
*, sbitmap
*, sbitmap
*, int);
127 static void build_btr_def_use_webs (fibheap_t
);
128 static int block_at_edge_of_live_range_p (int, btr_def
);
129 static void clear_btr_from_live_range (btr_def def
);
130 static void add_btr_to_live_range (btr_def
);
131 static void augment_live_range (bitmap
, HARD_REG_SET
*, basic_block
,
133 static int choose_btr (HARD_REG_SET
);
134 static void combine_btr_defs (btr_def
, HARD_REG_SET
*);
135 static void btr_def_live_range (btr_def
, HARD_REG_SET
*);
136 static void move_btr_def (basic_block
, int, btr_def
, bitmap
, HARD_REG_SET
*);
137 static int migrate_btr_def (btr_def
, int);
138 static void migrate_btr_defs (enum reg_class
, int);
139 static int can_move_up (basic_block
, rtx
, int);
140 static void note_btr_set (rtx
, rtx
, void *);
142 /* The following code performs code motion of target load instructions
143 (instructions that set branch target registers), to move them
144 forward away from the branch instructions and out of loops (or,
145 more generally, from a more frequently executed place to a less
146 frequently executed place).
147 Moving target load instructions further in front of the branch
148 instruction that uses the target register value means that the hardware
149 has a better chance of preloading the instructions at the branch
150 target by the time the branch is reached. This avoids bubbles
151 when a taken branch needs to flush out the pipeline.
152 Moving target load instructions out of loops means they are executed
155 /* An obstack to hold the def-use web data structures built up for
156 migrating branch target load instructions. */
157 static struct obstack migrate_btrl_obstack
;
159 /* Array indexed by basic block number, giving the set of registers
160 live in that block. */
161 static HARD_REG_SET
*btrs_live
;
163 /* Array indexed by basic block number, giving the set of registers live at
164 the end of that block, including any uses by a final jump insn, if any. */
165 static HARD_REG_SET
*btrs_live_at_end
;
167 /* Set of all target registers that we are willing to allocate. */
168 static HARD_REG_SET all_btrs
;
170 /* Provide lower and upper bounds for target register numbers, so that
171 we don't need to search through all the hard registers all the time. */
172 static int first_btr
, last_btr
;
176 /* Return an estimate of the frequency of execution of block bb. */
178 basic_block_freq (basic_block bb
)
180 return bb
->frequency
;
183 static rtx
*btr_reference_found
;
185 /* A subroutine of btr_referenced_p, called through for_each_rtx.
186 PREG is a pointer to an rtx that is to be excluded from the
187 traversal. If we find a reference to a target register anywhere
188 else, return 1, and put a pointer to it into btr_reference_found. */
190 find_btr_reference (rtx
*px
, void *preg
)
201 for (i
= hard_regno_nregs
[regno
][GET_MODE (x
)] - 1; i
>= 0; i
--)
202 if (TEST_HARD_REG_BIT (all_btrs
, regno
+i
))
204 btr_reference_found
= px
;
210 /* Return nonzero if X references (sets or reads) any branch target register.
211 If EXCLUDEP is set, disregard any references within the rtx pointed to
212 by it. If returning nonzero, also set btr_reference_found as above. */
214 btr_referenced_p (rtx x
, rtx
*excludep
)
216 return for_each_rtx (&x
, find_btr_reference
, excludep
);
219 /* Return true if insn is an instruction that sets a target register.
220 if CHECK_CONST is true, only return true if the source is constant.
221 If such a set is found and REGNO is nonzero, assign the register number
222 of the destination register to *REGNO. */
224 insn_sets_btr_p (rtx insn
, int check_const
, int *regno
)
228 if (NONJUMP_INSN_P (insn
)
229 && (set
= single_set (insn
)))
231 rtx dest
= SET_DEST (set
);
232 rtx src
= SET_SRC (set
);
234 if (GET_CODE (dest
) == SUBREG
)
235 dest
= XEXP (dest
, 0);
238 && TEST_HARD_REG_BIT (all_btrs
, REGNO (dest
)))
240 gcc_assert (!btr_referenced_p (src
, NULL
));
242 if (!check_const
|| CONSTANT_P (src
))
245 *regno
= REGNO (dest
);
253 /* Find and return a use of a target register within an instruction INSN. */
255 find_btr_use (rtx insn
)
257 return btr_referenced_p (insn
, NULL
) ? btr_reference_found
: NULL
;
260 /* Find the group that the target register definition DEF belongs
261 to in the list starting with *ALL_BTR_DEF_GROUPS. If no such
262 group exists, create one. Add def to the group. */
264 find_btr_def_group (btr_def_group
*all_btr_def_groups
, btr_def def
)
266 if (insn_sets_btr_p (def
->insn
, 1, NULL
))
268 btr_def_group this_group
;
269 rtx def_src
= SET_SRC (single_set (def
->insn
));
271 /* ?? This linear search is an efficiency concern, particularly
272 as the search will almost always fail to find a match. */
273 for (this_group
= *all_btr_def_groups
;
275 this_group
= this_group
->next
)
276 if (rtx_equal_p (def_src
, this_group
->src
))
281 this_group
= obstack_alloc (&migrate_btrl_obstack
,
282 sizeof (struct btr_def_group_s
));
283 this_group
->src
= def_src
;
284 this_group
->members
= NULL
;
285 this_group
->next
= *all_btr_def_groups
;
286 *all_btr_def_groups
= this_group
;
288 def
->group
= this_group
;
289 def
->next_this_group
= this_group
->members
;
290 this_group
->members
= def
;
296 /* Create a new target register definition structure, for a definition in
297 block BB, instruction INSN, and insert it into ALL_BTR_DEFS. Return
298 the new definition. */
300 add_btr_def (fibheap_t all_btr_defs
, basic_block bb
, int insn_luid
, rtx insn
,
301 unsigned int dest_reg
, int other_btr_uses_before_def
,
302 btr_def_group
*all_btr_def_groups
)
305 = obstack_alloc (&migrate_btrl_obstack
, sizeof (struct btr_def_s
));
307 this->luid
= insn_luid
;
309 this->btr
= dest_reg
;
310 this->cost
= basic_block_freq (bb
);
311 this->has_ambiguous_use
= 0;
312 this->other_btr_uses_before_def
= other_btr_uses_before_def
;
313 this->other_btr_uses_after_use
= 0;
314 this->next_this_bb
= NULL
;
315 this->next_this_group
= NULL
;
317 this->live_range
= NULL
;
318 find_btr_def_group (all_btr_def_groups
, this);
320 fibheap_insert (all_btr_defs
, -this->cost
, this);
324 "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n",
325 dest_reg
, bb
->index
, INSN_UID (insn
), (this->group
? "" : ":not const"),
331 /* Create a new target register user structure, for a use in block BB,
332 instruction INSN. Return the new user. */
334 new_btr_user (basic_block bb
, int insn_luid
, rtx insn
)
336 /* This instruction reads target registers. We need
337 to decide whether we can replace all target register
340 rtx
*usep
= find_btr_use (PATTERN (insn
));
342 btr_user user
= NULL
;
346 int unambiguous_single_use
;
348 /* We want to ensure that USE is the only use of a target
349 register in INSN, so that we know that to rewrite INSN to use
350 a different target register, all we have to do is replace USE. */
351 unambiguous_single_use
= !btr_referenced_p (PATTERN (insn
), usep
);
352 if (!unambiguous_single_use
)
355 use
= usep
? *usep
: NULL_RTX
;
356 user
= obstack_alloc (&migrate_btrl_obstack
, sizeof (struct btr_user_s
));
358 user
->luid
= insn_luid
;
361 user
->other_use_this_block
= 0;
363 user
->n_reaching_defs
= 0;
364 user
->first_reaching_def
= -1;
368 fprintf (dump_file
, "Uses target reg: { bb %d, insn %d }",
369 bb
->index
, INSN_UID (insn
));
372 fprintf (dump_file
, ": unambiguous use of reg %d\n",
379 /* Write the contents of S to the dump file. */
381 dump_hard_reg_set (HARD_REG_SET s
)
384 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
385 if (TEST_HARD_REG_BIT (s
, reg
))
386 fprintf (dump_file
, " %d", reg
);
389 /* Write the set of target regs live in block BB to the dump file. */
391 dump_btrs_live (int bb
)
393 fprintf (dump_file
, "BB%d live:", bb
);
394 dump_hard_reg_set (btrs_live
[bb
]);
395 fprintf (dump_file
, "\n");
398 /* REGNO is the number of a branch target register that is being used or
399 set. USERS_THIS_BB is a list of preceding branch target register users;
400 If any of them use the same register, set their other_use_this_block
403 note_other_use_this_block (unsigned int regno
, btr_user users_this_bb
)
407 for (user
= users_this_bb
; user
!= NULL
; user
= user
->next
)
408 if (user
->use
&& REGNO (user
->use
) == regno
)
409 user
->other_use_this_block
= 1;
413 btr_user users_this_bb
;
414 HARD_REG_SET btrs_written_in_block
;
415 HARD_REG_SET btrs_live_in_block
;
420 /* Called via note_stores or directly to register stores into /
421 clobbers of a branch target register DEST that are not recognized as
422 straightforward definitions. DATA points to information about the
423 current basic block that needs updating. */
425 note_btr_set (rtx dest
, rtx set ATTRIBUTE_UNUSED
, void *data
)
427 defs_uses_info
*info
= data
;
428 int regno
, end_regno
;
432 regno
= REGNO (dest
);
433 end_regno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (dest
)];
434 for (; regno
< end_regno
; regno
++)
435 if (TEST_HARD_REG_BIT (all_btrs
, regno
))
437 note_other_use_this_block (regno
, info
->users_this_bb
);
438 SET_HARD_REG_BIT (info
->btrs_written_in_block
, regno
);
439 SET_HARD_REG_BIT (info
->btrs_live_in_block
, regno
);
440 sbitmap_difference (info
->bb_gen
, info
->bb_gen
,
441 info
->btr_defset
[regno
- first_btr
]);
446 compute_defs_uses_and_gen (fibheap_t all_btr_defs
, btr_def
*def_array
,
447 btr_user
*use_array
, sbitmap
*btr_defset
,
448 sbitmap
*bb_gen
, HARD_REG_SET
*btrs_written
)
450 /* Scan the code building up the set of all defs and all uses.
451 For each target register, build the set of defs of that register.
452 For each block, calculate the set of target registers
453 written in that block.
454 Also calculate the set of btrs ever live in that block.
458 btr_def_group all_btr_def_groups
= NULL
;
461 sbitmap_vector_zero (bb_gen
, n_basic_blocks
);
462 for (i
= 0; i
< n_basic_blocks
; i
++)
464 basic_block bb
= BASIC_BLOCK (i
);
466 btr_def defs_this_bb
= NULL
;
471 info
.users_this_bb
= NULL
;
472 info
.bb_gen
= bb_gen
[i
];
473 info
.btr_defset
= btr_defset
;
475 CLEAR_HARD_REG_SET (info
.btrs_live_in_block
);
476 CLEAR_HARD_REG_SET (info
.btrs_written_in_block
);
477 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
478 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
479 && REGNO_REG_SET_P (bb
->global_live_at_start
, reg
))
480 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
482 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
484 insn
= NEXT_INSN (insn
), insn_luid
++)
489 int insn_uid
= INSN_UID (insn
);
491 if (insn_sets_btr_p (insn
, 0, ®no
))
493 btr_def def
= add_btr_def (
494 all_btr_defs
, bb
, insn_luid
, insn
, regno
,
495 TEST_HARD_REG_BIT (info
.btrs_live_in_block
, regno
),
496 &all_btr_def_groups
);
498 def_array
[insn_uid
] = def
;
499 SET_HARD_REG_BIT (info
.btrs_written_in_block
, regno
);
500 SET_HARD_REG_BIT (info
.btrs_live_in_block
, regno
);
501 sbitmap_difference (bb_gen
[i
], bb_gen
[i
],
502 btr_defset
[regno
- first_btr
]);
503 SET_BIT (bb_gen
[i
], insn_uid
);
504 def
->next_this_bb
= defs_this_bb
;
506 SET_BIT (btr_defset
[regno
- first_btr
], insn_uid
);
507 note_other_use_this_block (regno
, info
.users_this_bb
);
511 if (btr_referenced_p (PATTERN (insn
), NULL
))
513 btr_user user
= new_btr_user (bb
, insn_luid
, insn
);
515 use_array
[insn_uid
] = user
;
517 SET_HARD_REG_BIT (info
.btrs_live_in_block
,
522 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
523 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
524 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
527 note_other_use_this_block (reg
,
529 SET_HARD_REG_BIT (info
.btrs_live_in_block
, reg
);
531 note_stores (PATTERN (insn
), note_btr_set
, &info
);
533 user
->next
= info
.users_this_bb
;
534 info
.users_this_bb
= user
;
538 HARD_REG_SET
*clobbered
= &call_used_reg_set
;
539 HARD_REG_SET call_saved
;
540 rtx pat
= PATTERN (insn
);
543 /* Check for sibcall. */
544 if (GET_CODE (pat
) == PARALLEL
)
545 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
546 if (GET_CODE (XVECEXP (pat
, 0, i
)) == RETURN
)
548 COMPL_HARD_REG_SET (call_saved
,
550 clobbered
= &call_saved
;
553 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
554 if (TEST_HARD_REG_BIT (*clobbered
, regno
))
555 note_btr_set (regno_reg_rtx
[regno
], NULL_RTX
, &info
);
561 COPY_HARD_REG_SET (btrs_live
[i
], info
.btrs_live_in_block
);
562 COPY_HARD_REG_SET (btrs_written
[i
], info
.btrs_written_in_block
);
564 REG_SET_TO_HARD_REG_SET (btrs_live_at_end
[i
], bb
->global_live_at_end
);
565 /* If this block ends in a jump insn, add any uses or even clobbers
566 of branch target registers that it might have. */
567 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
) && ! INSN_P (insn
); )
568 insn
= PREV_INSN (insn
);
569 /* ??? for the fall-through edge, it would make sense to insert the
570 btr set on the edge, but that would require to split the block
571 early on so that we can distinguish between dominance from the fall
572 through edge - which can use the call-clobbered registers - from
573 dominance by the throw edge. */
574 if (can_throw_internal (insn
))
578 COPY_HARD_REG_SET (tmp
, call_used_reg_set
);
579 AND_HARD_REG_SET (tmp
, all_btrs
);
580 IOR_HARD_REG_SET (btrs_live_at_end
[i
], tmp
);
583 if (can_throw
|| JUMP_P (insn
))
587 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
588 if (refers_to_regno_p (regno
, regno
+1, insn
, NULL
))
589 SET_HARD_REG_BIT (btrs_live_at_end
[i
], regno
);
598 compute_kill (sbitmap
*bb_kill
, sbitmap
*btr_defset
,
599 HARD_REG_SET
*btrs_written
)
604 /* For each basic block, form the set BB_KILL - the set
605 of definitions that the block kills. */
606 sbitmap_vector_zero (bb_kill
, n_basic_blocks
);
607 for (i
= 0; i
< n_basic_blocks
; i
++)
609 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
610 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
611 && TEST_HARD_REG_BIT (btrs_written
[i
], regno
))
612 sbitmap_a_or_b (bb_kill
[i
], bb_kill
[i
],
613 btr_defset
[regno
- first_btr
]);
618 compute_out (sbitmap
*bb_out
, sbitmap
*bb_gen
, sbitmap
*bb_kill
, int max_uid
)
620 /* Perform iterative dataflow:
621 Initially, for all blocks, BB_OUT = BB_GEN.
623 BB_IN = union over predecessors of BB_OUT(pred)
624 BB_OUT = (BB_IN - BB_KILL) + BB_GEN
625 Iterate until the bb_out sets stop growing. */
628 sbitmap bb_in
= sbitmap_alloc (max_uid
);
630 for (i
= 0; i
< n_basic_blocks
; i
++)
631 sbitmap_copy (bb_out
[i
], bb_gen
[i
]);
637 for (i
= 0; i
< n_basic_blocks
; i
++)
639 sbitmap_union_of_preds (bb_in
, bb_out
, i
);
640 changed
|= sbitmap_union_of_diff_cg (bb_out
[i
], bb_gen
[i
],
644 sbitmap_free (bb_in
);
648 link_btr_uses (btr_def
*def_array
, btr_user
*use_array
, sbitmap
*bb_out
,
649 sbitmap
*btr_defset
, int max_uid
)
652 sbitmap reaching_defs
= sbitmap_alloc (max_uid
);
654 /* Link uses to the uses lists of all of their reaching defs.
655 Count up the number of reaching defs of each use. */
656 for (i
= 0; i
< n_basic_blocks
; i
++)
658 basic_block bb
= BASIC_BLOCK (i
);
662 sbitmap_union_of_preds (reaching_defs
, bb_out
, i
);
663 for (insn
= BB_HEAD (bb
), last
= NEXT_INSN (BB_END (bb
));
665 insn
= NEXT_INSN (insn
))
669 int insn_uid
= INSN_UID (insn
);
671 btr_def def
= def_array
[insn_uid
];
672 btr_user user
= use_array
[insn_uid
];
675 /* Remove all reaching defs of regno except
677 sbitmap_difference (reaching_defs
, reaching_defs
,
678 btr_defset
[def
->btr
- first_btr
]);
679 SET_BIT(reaching_defs
, insn_uid
);
684 /* Find all the reaching defs for this use. */
685 sbitmap reaching_defs_of_reg
= sbitmap_alloc(max_uid
);
690 reaching_defs_of_reg
,
692 btr_defset
[REGNO (user
->use
) - first_btr
]);
697 sbitmap_zero (reaching_defs_of_reg
);
698 for (reg
= first_btr
; reg
<= last_btr
; reg
++)
699 if (TEST_HARD_REG_BIT (all_btrs
, reg
)
700 && refers_to_regno_p (reg
, reg
+ 1, user
->insn
,
702 sbitmap_a_or_b_and_c (reaching_defs_of_reg
,
703 reaching_defs_of_reg
,
705 btr_defset
[reg
- first_btr
]);
707 EXECUTE_IF_SET_IN_SBITMAP (reaching_defs_of_reg
, 0, uid
,
709 btr_def def
= def_array
[uid
];
711 /* We now know that def reaches user. */
715 "Def in insn %d reaches use in insn %d\n",
718 user
->n_reaching_defs
++;
720 def
->has_ambiguous_use
= 1;
721 if (user
->first_reaching_def
!= -1)
722 { /* There is more than one reaching def. This is
723 a rare case, so just give up on this def/use
724 web when it occurs. */
725 def
->has_ambiguous_use
= 1;
726 def_array
[user
->first_reaching_def
]
727 ->has_ambiguous_use
= 1;
730 "(use %d has multiple reaching defs)\n",
734 user
->first_reaching_def
= uid
;
735 if (user
->other_use_this_block
)
736 def
->other_btr_uses_after_use
= 1;
737 user
->next
= def
->uses
;
740 sbitmap_free (reaching_defs_of_reg
);
747 for (regno
= first_btr
; regno
<= last_btr
; regno
++)
748 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
749 && TEST_HARD_REG_BIT (call_used_reg_set
, regno
))
750 sbitmap_difference (reaching_defs
, reaching_defs
,
751 btr_defset
[regno
- first_btr
]);
756 sbitmap_free (reaching_defs
);
760 build_btr_def_use_webs (fibheap_t all_btr_defs
)
762 const int max_uid
= get_max_uid ();
763 btr_def
*def_array
= xcalloc (max_uid
, sizeof (btr_def
));
764 btr_user
*use_array
= xcalloc (max_uid
, sizeof (btr_user
));
765 sbitmap
*btr_defset
= sbitmap_vector_alloc (
766 (last_btr
- first_btr
) + 1, max_uid
);
767 sbitmap
*bb_gen
= sbitmap_vector_alloc (n_basic_blocks
, max_uid
);
768 HARD_REG_SET
*btrs_written
= xcalloc (n_basic_blocks
, sizeof (HARD_REG_SET
));
772 sbitmap_vector_zero (btr_defset
, (last_btr
- first_btr
) + 1);
774 compute_defs_uses_and_gen (all_btr_defs
, def_array
, use_array
, btr_defset
,
775 bb_gen
, btrs_written
);
777 bb_kill
= sbitmap_vector_alloc (n_basic_blocks
, max_uid
);
778 compute_kill (bb_kill
, btr_defset
, btrs_written
);
781 bb_out
= sbitmap_vector_alloc (n_basic_blocks
, max_uid
);
782 compute_out (bb_out
, bb_gen
, bb_kill
, max_uid
);
784 sbitmap_vector_free (bb_gen
);
785 sbitmap_vector_free (bb_kill
);
787 link_btr_uses (def_array
, use_array
, bb_out
, btr_defset
, max_uid
);
789 sbitmap_vector_free (bb_out
);
790 sbitmap_vector_free (btr_defset
);
795 /* Return true if basic block BB contains the start or end of the
796 live range of the definition DEF, AND there are other live
797 ranges of the same target register that include BB. */
799 block_at_edge_of_live_range_p (int bb
, btr_def def
)
801 if (def
->other_btr_uses_before_def
&& BASIC_BLOCK (bb
) == def
->bb
)
803 else if (def
->other_btr_uses_after_use
)
806 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
807 if (BASIC_BLOCK (bb
) == user
->bb
)
813 /* We are removing the def/use web DEF. The target register
814 used in this web is therefore no longer live in the live range
815 of this web, so remove it from the live set of all basic blocks
816 in the live range of the web.
817 Blocks at the boundary of the live range may contain other live
818 ranges for the same target register, so we have to be careful
819 to remove the target register from the live set of these blocks
820 only if they do not contain other live ranges for the same register. */
822 clear_btr_from_live_range (btr_def def
)
827 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
829 if ((!def
->other_btr_uses_before_def
830 && !def
->other_btr_uses_after_use
)
831 || !block_at_edge_of_live_range_p (bb
, def
))
833 CLEAR_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
834 CLEAR_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
842 /* We are adding the def/use web DEF. Add the target register used
843 in this web to the live set of all of the basic blocks that contain
844 the live range of the web. */
846 add_btr_to_live_range (btr_def def
)
851 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
853 SET_HARD_REG_BIT (btrs_live
[bb
], def
->btr
);
854 SET_HARD_REG_BIT (btrs_live_at_end
[bb
], def
->btr
);
860 /* Update a live range to contain the basic block NEW_BLOCK, and all
861 blocks on paths between the existing live range and NEW_BLOCK.
862 HEAD is a block contained in the existing live range that dominates
863 all other blocks in the existing live range.
864 Also add to the set BTRS_LIVE_IN_RANGE all target registers that
865 are live in the blocks that we add to the live range.
866 It is a precondition that either NEW_BLOCK dominates HEAD,or
867 HEAD dom NEW_BLOCK. This is used to speed up the
868 implementation of this function. */
870 augment_live_range (bitmap live_range
, HARD_REG_SET
*btrs_live_in_range
,
871 basic_block head_bb
, basic_block new_bb
)
873 basic_block
*worklist
, *tos
;
875 tos
= worklist
= xmalloc (sizeof (basic_block
) * (n_basic_blocks
+ 1));
877 if (dominated_by_p (CDI_DOMINATORS
, new_bb
, head_bb
))
883 int new_block
= new_bb
->index
;
885 gcc_assert (dominated_by_p (CDI_DOMINATORS
, head_bb
, new_bb
));
887 bitmap_set_bit (live_range
, new_block
);
888 if (flag_btr_bb_exclusive
)
889 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[new_block
]);
892 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live_at_end
[new_block
]);
893 IOR_HARD_REG_SET (*btrs_live_in_range
, btrs_live
[head_bb
->index
]);
898 "Adding end of block %d and rest of %d to live range\n",
899 new_block
, head_bb
->index
);
900 fprintf (dump_file
,"Now live btrs are ");
901 dump_hard_reg_set (*btrs_live_in_range
);
902 fprintf (dump_file
, "\n");
904 FOR_EACH_EDGE (e
, ei
, head_bb
->preds
)
908 while (tos
!= worklist
)
910 basic_block bb
= *--tos
;
911 if (!bitmap_bit_p (live_range
, bb
->index
))
916 bitmap_set_bit (live_range
, bb
->index
);
917 IOR_HARD_REG_SET (*btrs_live_in_range
,
918 btrs_live
[bb
->index
]);
922 "Adding block %d to live range\n", bb
->index
);
923 fprintf (dump_file
,"Now live btrs are ");
924 dump_hard_reg_set (*btrs_live_in_range
);
925 fprintf (dump_file
, "\n");
928 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
930 basic_block pred
= e
->src
;
931 if (!bitmap_bit_p (live_range
, pred
->index
))
940 /* Return the most desirable target register that is not in
941 the set USED_BTRS. */
943 choose_btr (HARD_REG_SET used_btrs
)
946 GO_IF_HARD_REG_SUBSET (all_btrs
, used_btrs
, give_up
);
948 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
950 #ifdef REG_ALLOC_ORDER
951 int regno
= reg_alloc_order
[i
];
955 if (TEST_HARD_REG_BIT (all_btrs
, regno
)
956 && !TEST_HARD_REG_BIT (used_btrs
, regno
))
963 /* Calculate the set of basic blocks that contain the live range of
965 Also calculate the set of target registers that are live at time
966 in this live range, but ignore the live range represented by DEF
967 when calculating this set. */
969 btr_def_live_range (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
971 if (!def
->live_range
)
975 def
->live_range
= BITMAP_XMALLOC ();
977 bitmap_set_bit (def
->live_range
, def
->bb
->index
);
978 COPY_HARD_REG_SET (*btrs_live_in_range
,
979 (flag_btr_bb_exclusive
980 ? btrs_live
: btrs_live_at_end
)[def
->bb
->index
]);
982 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
983 augment_live_range (def
->live_range
, btrs_live_in_range
,
988 /* def->live_range is accurate, but we need to recompute
989 the set of target registers live over it, because migration
990 of other PT instructions may have affected it.
993 unsigned def_bb
= flag_btr_bb_exclusive
? -1 : def
->bb
->index
;
996 CLEAR_HARD_REG_SET (*btrs_live_in_range
);
997 EXECUTE_IF_SET_IN_BITMAP (def
->live_range
, 0, bb
, bi
)
999 IOR_HARD_REG_SET (*btrs_live_in_range
,
1001 ? btrs_live_at_end
: btrs_live
) [bb
]);
1004 if (!def
->other_btr_uses_before_def
&&
1005 !def
->other_btr_uses_after_use
)
1006 CLEAR_HARD_REG_BIT (*btrs_live_in_range
, def
->btr
);
1009 /* Merge into the def/use web DEF any other def/use webs in the same
1010 group that are dominated by DEF, provided that there is a target
1011 register available to allocate to the merged web. */
1013 combine_btr_defs (btr_def def
, HARD_REG_SET
*btrs_live_in_range
)
1017 for (other_def
= def
->group
->members
;
1019 other_def
= other_def
->next_this_group
)
1021 if (other_def
!= def
1022 && other_def
->uses
!= NULL
1023 && ! other_def
->has_ambiguous_use
1024 && dominated_by_p (CDI_DOMINATORS
, other_def
->bb
, def
->bb
))
1026 /* def->bb dominates the other def, so def and other_def could
1028 /* Merge their live ranges, and get the set of
1029 target registers live over the merged range. */
1031 HARD_REG_SET combined_btrs_live
;
1032 bitmap combined_live_range
= BITMAP_XMALLOC ();
1035 if (other_def
->live_range
== NULL
)
1037 HARD_REG_SET dummy_btrs_live_in_range
;
1038 btr_def_live_range (other_def
, &dummy_btrs_live_in_range
);
1040 COPY_HARD_REG_SET (combined_btrs_live
, *btrs_live_in_range
);
1041 bitmap_copy (combined_live_range
, def
->live_range
);
1043 for (user
= other_def
->uses
; user
!= NULL
; user
= user
->next
)
1044 augment_live_range (combined_live_range
, &combined_btrs_live
,
1047 btr
= choose_btr (combined_btrs_live
);
1050 /* We can combine them. */
1053 "Combining def in insn %d with def in insn %d\n",
1054 INSN_UID (other_def
->insn
), INSN_UID (def
->insn
));
1057 user
= other_def
->uses
;
1058 while (user
!= NULL
)
1060 btr_user next
= user
->next
;
1062 user
->next
= def
->uses
;
1066 /* Combining def/use webs can make target registers live
1067 after uses where they previously were not. This means
1068 some REG_DEAD notes may no longer be correct. We could
1069 be more precise about this if we looked at the combined
1070 live range, but here I just delete any REG_DEAD notes
1071 in case they are no longer correct. */
1072 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1073 remove_note (user
->insn
,
1074 find_regno_note (user
->insn
, REG_DEAD
,
1075 REGNO (user
->use
)));
1076 clear_btr_from_live_range (other_def
);
1077 other_def
->uses
= NULL
;
1078 bitmap_copy (def
->live_range
, combined_live_range
);
1079 if (other_def
->other_btr_uses_after_use
)
1080 def
->other_btr_uses_after_use
= 1;
1081 COPY_HARD_REG_SET (*btrs_live_in_range
, combined_btrs_live
);
1083 /* Delete the old target register initialization. */
1084 delete_insn (other_def
->insn
);
1087 BITMAP_XFREE (combined_live_range
);
1092 /* Move the definition DEF from its current position to basic
1093 block NEW_DEF_BB, and modify it to use branch target register BTR.
1094 Delete the old defining insn, and insert a new one in NEW_DEF_BB.
1095 Update all reaching uses of DEF in the RTL to use BTR.
1096 If this new position means that other defs in the
1097 same group can be combined with DEF then combine them. */
1099 move_btr_def (basic_block new_def_bb
, int btr
, btr_def def
, bitmap live_range
,
1100 HARD_REG_SET
*btrs_live_in_range
)
1102 /* We can move the instruction.
1103 Set a target register in block NEW_DEF_BB to the value
1104 needed for this target register definition.
1105 Replace all uses of the old target register definition by
1106 uses of the new definition. Delete the old definition. */
1107 basic_block b
= new_def_bb
;
1108 rtx insp
= BB_HEAD (b
);
1109 rtx old_insn
= def
->insn
;
1113 enum machine_mode btr_mode
;
1118 fprintf(dump_file
, "migrating to basic block %d, using reg %d\n",
1119 new_def_bb
->index
, btr
);
1121 clear_btr_from_live_range (def
);
1123 def
->bb
= new_def_bb
;
1125 def
->cost
= basic_block_freq (new_def_bb
);
1126 def
->other_btr_uses_before_def
1127 = TEST_HARD_REG_BIT (btrs_live
[b
->index
], btr
) ? 1 : 0;
1128 bitmap_copy (def
->live_range
, live_range
);
1129 combine_btr_defs (def
, btrs_live_in_range
);
1131 add_btr_to_live_range (def
);
1133 insp
= NEXT_INSN (insp
);
1134 /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some
1135 optimizations can result in insp being both first and last insn of
1137 /* ?? some assertions to check that insp is sensible? */
1139 if (def
->other_btr_uses_before_def
)
1142 for (insp
= BB_END (b
); ! INSN_P (insp
); insp
= PREV_INSN (insp
))
1143 gcc_assert (insp
!= BB_HEAD (b
));
1145 if (JUMP_P (insp
) || can_throw_internal (insp
))
1146 insp
= PREV_INSN (insp
);
1149 set
= single_set (old_insn
);
1150 src
= SET_SRC (set
);
1151 btr_mode
= GET_MODE (SET_DEST (set
));
1152 btr_rtx
= gen_rtx_REG (btr_mode
, btr
);
1154 new_insn
= gen_move_insn (btr_rtx
, src
);
1156 /* Insert target register initialization at head of basic block. */
1157 def
->insn
= emit_insn_after (new_insn
, insp
);
1159 regs_ever_live
[btr
] = 1;
1162 fprintf (dump_file
, "New pt is insn %d, inserted after insn %d\n",
1163 INSN_UID (def
->insn
), INSN_UID (insp
));
1165 /* Delete the old target register initialization. */
1166 delete_insn (old_insn
);
1168 /* Replace each use of the old target register by a use of the new target
1170 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1172 /* Some extra work here to ensure consistent modes, because
1173 it seems that a target register REG rtx can be given a different
1174 mode depending on the context (surely that should not be
1176 rtx replacement_rtx
;
1177 if (GET_MODE (user
->use
) == GET_MODE (btr_rtx
)
1178 || GET_MODE (user
->use
) == VOIDmode
)
1179 replacement_rtx
= btr_rtx
;
1181 replacement_rtx
= gen_rtx_REG (GET_MODE (user
->use
), btr
);
1182 replace_rtx (user
->insn
, user
->use
, replacement_rtx
);
1183 user
->use
= replacement_rtx
;
1187 /* We anticipate intra-block scheduling to be done. See if INSN could move
1188 up within BB by N_INSNS. */
1190 can_move_up (basic_block bb
, rtx insn
, int n_insns
)
1192 while (insn
!= BB_HEAD (bb
) && n_insns
> 0)
1194 insn
= PREV_INSN (insn
);
1195 /* ??? What if we have an anti-dependency that actually prevents the
1196 scheduler from doing the move? We'd like to re-allocate the register,
1197 but not necessarily put the load into another basic block. */
1201 return n_insns
<= 0;
1204 /* Attempt to migrate the target register definition DEF to an
1205 earlier point in the flowgraph.
1207 It is a precondition of this function that DEF is migratable:
1208 i.e. it has a constant source, and all uses are unambiguous.
1210 Only migrations that reduce the cost of DEF will be made.
1211 MIN_COST is the lower bound on the cost of the DEF after migration.
1212 If we migrate DEF so that its cost falls below MIN_COST,
1213 then we do not attempt to migrate further. The idea is that
1214 we migrate definitions in a priority order based on their cost,
1215 when the cost of this definition falls below MIN_COST, then
1216 there is another definition with cost == MIN_COST which now
1217 has a higher priority than this definition.
1219 Return nonzero if there may be benefit from attempting to
1220 migrate this DEF further (i.e. we have reduced the cost below
1221 MIN_COST, but we may be able to reduce it further).
1222 Return zero if no further migration is possible. */
1224 migrate_btr_def (btr_def def
, int min_cost
)
1227 HARD_REG_SET btrs_live_in_range
;
1228 int btr_used_near_def
= 0;
1229 int def_basic_block_freq
;
1238 "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ",
1239 INSN_UID (def
->insn
), def
->cost
, min_cost
);
1241 if (!def
->group
|| def
->has_ambiguous_use
)
1242 /* These defs are not migratable. */
1245 fprintf (dump_file
, "it's not migratable\n");
1250 /* We have combined this def with another in the same group, so
1251 no need to consider it further.
1255 fprintf (dump_file
, "it's already combined with another pt\n");
1259 btr_def_live_range (def
, &btrs_live_in_range
);
1260 live_range
= BITMAP_XMALLOC ();
1261 bitmap_copy (live_range
, def
->live_range
);
1263 #ifdef INSN_SCHEDULING
1264 def_latency
= insn_default_latency (def
->insn
) * issue_rate
;
1266 def_latency
= issue_rate
;
1269 for (user
= def
->uses
; user
!= NULL
; user
= user
->next
)
1271 if (user
->bb
== def
->bb
1272 && user
->luid
> def
->luid
1273 && (def
->luid
+ def_latency
) > user
->luid
1274 && ! can_move_up (def
->bb
, def
->insn
,
1275 (def
->luid
+ def_latency
) - user
->luid
))
1277 btr_used_near_def
= 1;
1282 def_basic_block_freq
= basic_block_freq (def
->bb
);
1284 for (try = get_immediate_dominator (CDI_DOMINATORS
, def
->bb
);
1285 !give_up
&& try && try != ENTRY_BLOCK_PTR
&& def
->cost
>= min_cost
;
1286 try = get_immediate_dominator (CDI_DOMINATORS
, try))
1288 /* Try to move the instruction that sets the target register into
1290 int try_freq
= basic_block_freq (try);
1293 fprintf (dump_file
, "trying block %d ...", try->index
);
1295 if (try_freq
< def_basic_block_freq
1296 || (try_freq
== def_basic_block_freq
&& btr_used_near_def
))
1299 augment_live_range (live_range
, &btrs_live_in_range
, def
->bb
, try);
1302 fprintf (dump_file
, "Now btrs live in range are: ");
1303 dump_hard_reg_set (btrs_live_in_range
);
1304 fprintf (dump_file
, "\n");
1306 btr
= choose_btr (btrs_live_in_range
);
1309 move_btr_def (try, btr
, def
, live_range
, &btrs_live_in_range
);
1310 bitmap_copy(live_range
, def
->live_range
);
1311 btr_used_near_def
= 0;
1313 def_basic_block_freq
= basic_block_freq (def
->bb
);
1317 /* There are no free target registers available to move
1318 this far forward, so give up */
1322 "giving up because there are no free target registers\n");
1331 fprintf (dump_file
, "failed to move\n");
1333 BITMAP_XFREE (live_range
);
1337 /* Attempt to move instructions that set target registers earlier
1338 in the flowgraph, away from their corresponding uses. */
1340 migrate_btr_defs (enum reg_class btr_class
, int allow_callee_save
)
1342 fibheap_t all_btr_defs
= fibheap_new ();
1345 gcc_obstack_init (&migrate_btrl_obstack
);
1350 for (i
= 0; i
< n_basic_blocks
; i
++)
1352 basic_block bb
= BASIC_BLOCK (i
);
1354 "Basic block %d: count = " HOST_WIDEST_INT_PRINT_DEC
1355 " loop-depth = %d idom = %d\n",
1356 i
, (HOST_WIDEST_INT
) bb
->count
, bb
->loop_depth
,
1357 get_immediate_dominator (CDI_DOMINATORS
, bb
)->index
);
1361 CLEAR_HARD_REG_SET (all_btrs
);
1362 for (first_btr
= -1, reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
1363 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) btr_class
], reg
)
1364 && (allow_callee_save
|| call_used_regs
[reg
] || regs_ever_live
[reg
]))
1366 SET_HARD_REG_BIT (all_btrs
, reg
);
1372 btrs_live
= xcalloc (n_basic_blocks
, sizeof (HARD_REG_SET
));
1373 btrs_live_at_end
= xcalloc (n_basic_blocks
, sizeof (HARD_REG_SET
));
1375 build_btr_def_use_webs (all_btr_defs
);
1377 while (!fibheap_empty (all_btr_defs
))
1379 btr_def def
= fibheap_extract_min (all_btr_defs
);
1380 int min_cost
= -fibheap_min_key (all_btr_defs
);
1381 if (migrate_btr_def (def
, min_cost
))
1383 fibheap_insert (all_btr_defs
, -def
->cost
, (void *) def
);
1387 "Putting insn %d back on queue with priority %d\n",
1388 INSN_UID (def
->insn
), def
->cost
);
1393 if (def
->live_range
)
1394 BITMAP_XFREE (def
->live_range
);
1399 free (btrs_live_at_end
);
1400 obstack_free (&migrate_btrl_obstack
, NULL
);
1401 fibheap_delete (all_btr_defs
);
1405 branch_target_load_optimize (bool after_prologue_epilogue_gen
)
1407 enum reg_class
class = targetm
.branch_target_register_class ();
1408 if (class != NO_REGS
)
1410 /* Initialize issue_rate. */
1411 if (targetm
.sched
.issue_rate
)
1412 issue_rate
= targetm
.sched
.issue_rate ();
1416 /* Build the CFG for migrate_btr_defs. */
1418 /* This may or may not be needed, depending on where we
1420 cleanup_cfg (optimize
? CLEANUP_EXPENSIVE
: 0);
1423 life_analysis (NULL
, 0);
1425 /* Dominator info is also needed for migrate_btr_def. */
1426 calculate_dominance_info (CDI_DOMINATORS
);
1427 migrate_btr_defs (class,
1428 (targetm
.branch_target_register_callee_saved
1429 (after_prologue_epilogue_gen
)));
1431 free_dominance_info (CDI_DOMINATORS
);
1433 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
1434 PROP_DEATH_NOTES
| PROP_REG_INFO
);