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Add a function for getting the ABI of a call insn target
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1 /* Save and restore call-clobbered registers which are live across a call.
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
10
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "backend.h"
24 #include "rtl.h"
25 #include "tree.h"
26 #include "predict.h"
27 #include "df.h"
28 #include "memmodel.h"
29 #include "tm_p.h"
30 #include "insn-config.h"
31 #include "regs.h"
32 #include "emit-rtl.h"
33 #include "recog.h"
34 #include "reload.h"
35 #include "alias.h"
36 #include "addresses.h"
37 #include "dumpfile.h"
38 #include "rtl-iter.h"
39 #include "target.h"
40 #include "function-abi.h"
41
42 #define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD)
43
44 #define regno_save_mode \
45 (this_target_reload->x_regno_save_mode)
46 #define cached_reg_save_code \
47 (this_target_reload->x_cached_reg_save_code)
48 #define cached_reg_restore_code \
49 (this_target_reload->x_cached_reg_restore_code)
50
51 /* For each hard register, a place on the stack where it can be saved,
52 if needed. */
53
54 static rtx
55 regno_save_mem[FIRST_PSEUDO_REGISTER][MAX_MOVE_MAX / MIN_UNITS_PER_WORD + 1];
56
57 /* The number of elements in the subsequent array. */
58 static int save_slots_num;
59
60 /* Allocated slots so far. */
61 static rtx save_slots[FIRST_PSEUDO_REGISTER];
62
63 /* Set of hard regs currently residing in save area (during insn scan). */
64
65 static HARD_REG_SET hard_regs_saved;
66
67 /* Number of registers currently in hard_regs_saved. */
68
69 static int n_regs_saved;
70
71 /* Computed by mark_referenced_regs, all regs referenced in a given
72 insn. */
73 static HARD_REG_SET referenced_regs;
74
75
76 typedef void refmarker_fn (rtx *loc, machine_mode mode, int hardregno,
77 void *mark_arg);
78
79 static int reg_save_code (int, machine_mode);
80 static int reg_restore_code (int, machine_mode);
81
82 struct saved_hard_reg;
83 static void initiate_saved_hard_regs (void);
84 static void new_saved_hard_reg (int, int);
85 static void finish_saved_hard_regs (void);
86 static int saved_hard_reg_compare_func (const void *, const void *);
87
88 static void mark_set_regs (rtx, const_rtx, void *);
89 static void mark_referenced_regs (rtx *, refmarker_fn *mark, void *mark_arg);
90 static refmarker_fn mark_reg_as_referenced;
91 static refmarker_fn replace_reg_with_saved_mem;
92 static int insert_save (class insn_chain *, int, HARD_REG_SET *,
93 machine_mode *);
94 static int insert_restore (class insn_chain *, int, int, int,
95 machine_mode *);
96 static class insn_chain *insert_one_insn (class insn_chain *, int, int,
97 rtx);
98 static void add_stored_regs (rtx, const_rtx, void *);
99
100 \f
101
102 static GTY(()) rtx savepat;
103 static GTY(()) rtx restpat;
104 static GTY(()) rtx test_reg;
105 static GTY(()) rtx test_mem;
106 static GTY(()) rtx_insn *saveinsn;
107 static GTY(()) rtx_insn *restinsn;
108
109 /* Return the INSN_CODE used to save register REG in mode MODE. */
110 static int
111 reg_save_code (int reg, machine_mode mode)
112 {
113 bool ok;
114 if (cached_reg_save_code[reg][mode])
115 return cached_reg_save_code[reg][mode];
116 if (!targetm.hard_regno_mode_ok (reg, mode))
117 {
118 /* Depending on how targetm.hard_regno_mode_ok is defined, range
119 propagation might deduce here that reg >= FIRST_PSEUDO_REGISTER.
120 So the assert below silences a warning. */
121 gcc_assert (reg < FIRST_PSEUDO_REGISTER);
122 cached_reg_save_code[reg][mode] = -1;
123 cached_reg_restore_code[reg][mode] = -1;
124 return -1;
125 }
126
127 /* Update the register number and modes of the register
128 and memory operand. */
129 set_mode_and_regno (test_reg, mode, reg);
130 PUT_MODE (test_mem, mode);
131
132 /* Force re-recognition of the modified insns. */
133 INSN_CODE (saveinsn) = -1;
134 INSN_CODE (restinsn) = -1;
135
136 cached_reg_save_code[reg][mode] = recog_memoized (saveinsn);
137 cached_reg_restore_code[reg][mode] = recog_memoized (restinsn);
138
139 /* Now extract both insns and see if we can meet their
140 constraints. We don't know here whether the save and restore will
141 be in size- or speed-tuned code, so just use the set of enabled
142 alternatives. */
143 ok = (cached_reg_save_code[reg][mode] != -1
144 && cached_reg_restore_code[reg][mode] != -1);
145 if (ok)
146 {
147 extract_insn (saveinsn);
148 ok = constrain_operands (1, get_enabled_alternatives (saveinsn));
149 extract_insn (restinsn);
150 ok &= constrain_operands (1, get_enabled_alternatives (restinsn));
151 }
152
153 if (! ok)
154 {
155 cached_reg_save_code[reg][mode] = -1;
156 cached_reg_restore_code[reg][mode] = -1;
157 }
158 gcc_assert (cached_reg_save_code[reg][mode]);
159 return cached_reg_save_code[reg][mode];
160 }
161
162 /* Return the INSN_CODE used to restore register REG in mode MODE. */
163 static int
164 reg_restore_code (int reg, machine_mode mode)
165 {
166 if (cached_reg_restore_code[reg][mode])
167 return cached_reg_restore_code[reg][mode];
168 /* Populate our cache. */
169 reg_save_code (reg, mode);
170 return cached_reg_restore_code[reg][mode];
171 }
172 \f
173 /* Initialize for caller-save.
174
175 Look at all the hard registers that are used by a call and for which
176 reginfo.c has not already excluded from being used across a call.
177
178 Ensure that we can find a mode to save the register and that there is a
179 simple insn to save and restore the register. This latter check avoids
180 problems that would occur if we tried to save the MQ register of some
181 machines directly into memory. */
182
183 void
184 init_caller_save (void)
185 {
186 rtx addr_reg;
187 int offset;
188 rtx address;
189 int i, j;
190
191 if (caller_save_initialized_p)
192 return;
193
194 caller_save_initialized_p = true;
195
196 /* First find all the registers that we need to deal with and all
197 the modes that they can have. If we can't find a mode to use,
198 we can't have the register live over calls. */
199
200 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
201 for (j = 1; j <= MOVE_MAX_WORDS; j++)
202 {
203 regno_save_mode[i][j] = HARD_REGNO_CALLER_SAVE_MODE (i, j, VOIDmode);
204 if (regno_save_mode[i][j] == VOIDmode && j == 1)
205 CLEAR_HARD_REG_BIT (savable_regs, i);
206 }
207
208 /* The following code tries to approximate the conditions under which
209 we can easily save and restore a register without scratch registers or
210 other complexities. It will usually work, except under conditions where
211 the validity of an insn operand is dependent on the address offset.
212 No such cases are currently known.
213
214 We first find a typical offset from some BASE_REG_CLASS register.
215 This address is chosen by finding the first register in the class
216 and by finding the smallest power of two that is a valid offset from
217 that register in every mode we will use to save registers. */
218
219 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
220 if (TEST_HARD_REG_BIT
221 (reg_class_contents
222 [(int) base_reg_class (regno_save_mode[i][1], ADDR_SPACE_GENERIC,
223 PLUS, CONST_INT)], i))
224 break;
225
226 gcc_assert (i < FIRST_PSEUDO_REGISTER);
227
228 addr_reg = gen_rtx_REG (Pmode, i);
229
230 for (offset = 1 << (HOST_BITS_PER_INT / 2); offset; offset >>= 1)
231 {
232 address = gen_rtx_PLUS (Pmode, addr_reg, gen_int_mode (offset, Pmode));
233
234 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
235 if (regno_save_mode[i][1] != VOIDmode
236 && ! strict_memory_address_p (regno_save_mode[i][1], address))
237 break;
238
239 if (i == FIRST_PSEUDO_REGISTER)
240 break;
241 }
242
243 /* If we didn't find a valid address, we must use register indirect. */
244 if (offset == 0)
245 address = addr_reg;
246
247 /* Next we try to form an insn to save and restore the register. We
248 see if such an insn is recognized and meets its constraints.
249
250 To avoid lots of unnecessary RTL allocation, we construct all the RTL
251 once, then modify the memory and register operands in-place. */
252
253 test_reg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1);
254 test_mem = gen_rtx_MEM (word_mode, address);
255 savepat = gen_rtx_SET (test_mem, test_reg);
256 restpat = gen_rtx_SET (test_reg, test_mem);
257
258 saveinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, savepat, 0, -1, 0);
259 restinsn = gen_rtx_INSN (VOIDmode, 0, 0, 0, restpat, 0, -1, 0);
260
261 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
262 for (j = 1; j <= MOVE_MAX_WORDS; j++)
263 if (reg_save_code (i,regno_save_mode[i][j]) == -1)
264 {
265 regno_save_mode[i][j] = VOIDmode;
266 if (j == 1)
267 CLEAR_HARD_REG_BIT (savable_regs, i);
268 }
269 }
270
271 \f
272
273 /* Initialize save areas by showing that we haven't allocated any yet. */
274
275 void
276 init_save_areas (void)
277 {
278 int i, j;
279
280 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
281 for (j = 1; j <= MOVE_MAX_WORDS; j++)
282 regno_save_mem[i][j] = 0;
283 save_slots_num = 0;
284
285 }
286
287 /* The structure represents a hard register which should be saved
288 through the call. It is used when the integrated register
289 allocator (IRA) is used and sharing save slots is on. */
290 struct saved_hard_reg
291 {
292 /* Order number starting with 0. */
293 int num;
294 /* The hard regno. */
295 int hard_regno;
296 /* Execution frequency of all calls through which given hard
297 register should be saved. */
298 int call_freq;
299 /* Stack slot reserved to save the hard register through calls. */
300 rtx slot;
301 /* True if it is first hard register in the chain of hard registers
302 sharing the same stack slot. */
303 int first_p;
304 /* Order number of the next hard register structure with the same
305 slot in the chain. -1 represents end of the chain. */
306 int next;
307 };
308
309 /* Map: hard register number to the corresponding structure. */
310 static struct saved_hard_reg *hard_reg_map[FIRST_PSEUDO_REGISTER];
311
312 /* The number of all structures representing hard registers should be
313 saved, in order words, the number of used elements in the following
314 array. */
315 static int saved_regs_num;
316
317 /* Pointers to all the structures. Index is the order number of the
318 corresponding structure. */
319 static struct saved_hard_reg *all_saved_regs[FIRST_PSEUDO_REGISTER];
320
321 /* First called function for work with saved hard registers. */
322 static void
323 initiate_saved_hard_regs (void)
324 {
325 int i;
326
327 saved_regs_num = 0;
328 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
329 hard_reg_map[i] = NULL;
330 }
331
332 /* Allocate and return new saved hard register with given REGNO and
333 CALL_FREQ. */
334 static void
335 new_saved_hard_reg (int regno, int call_freq)
336 {
337 struct saved_hard_reg *saved_reg;
338
339 saved_reg
340 = (struct saved_hard_reg *) xmalloc (sizeof (struct saved_hard_reg));
341 hard_reg_map[regno] = all_saved_regs[saved_regs_num] = saved_reg;
342 saved_reg->num = saved_regs_num++;
343 saved_reg->hard_regno = regno;
344 saved_reg->call_freq = call_freq;
345 saved_reg->first_p = FALSE;
346 saved_reg->next = -1;
347 }
348
349 /* Free memory allocated for the saved hard registers. */
350 static void
351 finish_saved_hard_regs (void)
352 {
353 int i;
354
355 for (i = 0; i < saved_regs_num; i++)
356 free (all_saved_regs[i]);
357 }
358
359 /* The function is used to sort the saved hard register structures
360 according their frequency. */
361 static int
362 saved_hard_reg_compare_func (const void *v1p, const void *v2p)
363 {
364 const struct saved_hard_reg *p1 = *(struct saved_hard_reg * const *) v1p;
365 const struct saved_hard_reg *p2 = *(struct saved_hard_reg * const *) v2p;
366
367 if (flag_omit_frame_pointer)
368 {
369 if (p1->call_freq - p2->call_freq != 0)
370 return p1->call_freq - p2->call_freq;
371 }
372 else if (p2->call_freq - p1->call_freq != 0)
373 return p2->call_freq - p1->call_freq;
374
375 return p1->num - p2->num;
376 }
377
378 /* Allocate save areas for any hard registers that might need saving.
379 We take a conservative approach here and look for call-clobbered hard
380 registers that are assigned to pseudos that cross calls. This may
381 overestimate slightly (especially if some of these registers are later
382 used as spill registers), but it should not be significant.
383
384 For IRA we use priority coloring to decrease stack slots needed for
385 saving hard registers through calls. We build conflicts for them
386 to do coloring.
387
388 Future work:
389
390 In the fallback case we should iterate backwards across all possible
391 modes for the save, choosing the largest available one instead of
392 falling back to the smallest mode immediately. (eg TF -> DF -> SF).
393
394 We do not try to use "move multiple" instructions that exist
395 on some machines (such as the 68k moveml). It could be a win to try
396 and use them when possible. The hard part is doing it in a way that is
397 machine independent since they might be saving non-consecutive
398 registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */
399
400 void
401 setup_save_areas (void)
402 {
403 int i, j, k, freq;
404 HARD_REG_SET hard_regs_used;
405 struct saved_hard_reg *saved_reg;
406 rtx_insn *insn;
407 class insn_chain *chain, *next;
408 unsigned int regno;
409 HARD_REG_SET hard_regs_to_save, used_regs, this_insn_sets;
410 reg_set_iterator rsi;
411
412 CLEAR_HARD_REG_SET (hard_regs_used);
413
414 /* Find every CALL_INSN and record which hard regs are live across the
415 call into HARD_REG_MAP and HARD_REGS_USED. */
416 initiate_saved_hard_regs ();
417 /* Create hard reg saved regs. */
418 for (chain = reload_insn_chain; chain != 0; chain = next)
419 {
420 rtx cheap;
421
422 insn = chain->insn;
423 next = chain->next;
424 if (!CALL_P (insn)
425 || find_reg_note (insn, REG_NORETURN, NULL))
426 continue;
427 freq = REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn));
428 REG_SET_TO_HARD_REG_SET (hard_regs_to_save,
429 &chain->live_throughout);
430 used_regs = insn_callee_abi (insn).full_reg_clobbers ();
431 /* ??? This preserves traditional behavior; it might not be needed. */
432 used_regs |= fixed_reg_set;
433
434 /* Record all registers set in this call insn. These don't
435 need to be saved. N.B. the call insn might set a subreg
436 of a multi-hard-reg pseudo; then the pseudo is considered
437 live during the call, but the subreg that is set
438 isn't. */
439 CLEAR_HARD_REG_SET (this_insn_sets);
440 note_stores (insn, mark_set_regs, &this_insn_sets);
441 /* Sibcalls are considered to set the return value. */
442 if (SIBLING_CALL_P (insn) && crtl->return_rtx)
443 mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets);
444
445 used_regs &= ~(fixed_reg_set | this_insn_sets);
446 hard_regs_to_save &= used_regs & savable_regs;
447 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
448 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
449 {
450 if (hard_reg_map[regno] != NULL)
451 hard_reg_map[regno]->call_freq += freq;
452 else
453 new_saved_hard_reg (regno, freq);
454 SET_HARD_REG_BIT (hard_regs_used, regno);
455 }
456 cheap = find_reg_note (insn, REG_RETURNED, NULL);
457 if (cheap)
458 cheap = XEXP (cheap, 0);
459 /* Look through all live pseudos, mark their hard registers. */
460 EXECUTE_IF_SET_IN_REG_SET
461 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi)
462 {
463 int r = reg_renumber[regno];
464 int bound;
465
466 if (r < 0 || regno_reg_rtx[regno] == cheap)
467 continue;
468
469 bound = r + hard_regno_nregs (r, PSEUDO_REGNO_MODE (regno));
470 for (; r < bound; r++)
471 if (TEST_HARD_REG_BIT (used_regs, r))
472 {
473 if (hard_reg_map[r] != NULL)
474 hard_reg_map[r]->call_freq += freq;
475 else
476 new_saved_hard_reg (r, freq);
477 SET_HARD_REG_BIT (hard_regs_to_save, r);
478 SET_HARD_REG_BIT (hard_regs_used, r);
479 }
480 }
481 }
482
483 /* If requested, figure out which hard regs can share save slots. */
484 if (optimize && flag_ira_share_save_slots)
485 {
486 rtx slot;
487 char *saved_reg_conflicts;
488 int next_k;
489 struct saved_hard_reg *saved_reg2, *saved_reg3;
490 int call_saved_regs_num;
491 struct saved_hard_reg *call_saved_regs[FIRST_PSEUDO_REGISTER];
492 int best_slot_num;
493 int prev_save_slots_num;
494 rtx prev_save_slots[FIRST_PSEUDO_REGISTER];
495
496 /* Find saved hard register conflicts. */
497 saved_reg_conflicts = (char *) xmalloc (saved_regs_num * saved_regs_num);
498 memset (saved_reg_conflicts, 0, saved_regs_num * saved_regs_num);
499 for (chain = reload_insn_chain; chain != 0; chain = next)
500 {
501 rtx cheap;
502 call_saved_regs_num = 0;
503 insn = chain->insn;
504 next = chain->next;
505 if (!CALL_P (insn)
506 || find_reg_note (insn, REG_NORETURN, NULL))
507 continue;
508
509 cheap = find_reg_note (insn, REG_RETURNED, NULL);
510 if (cheap)
511 cheap = XEXP (cheap, 0);
512
513 REG_SET_TO_HARD_REG_SET (hard_regs_to_save,
514 &chain->live_throughout);
515 used_regs = insn_callee_abi (insn).full_reg_clobbers ();
516 /* ??? This preserves traditional behavior; it might not
517 be needed. */
518 used_regs |= fixed_reg_set;
519
520 /* Record all registers set in this call insn. These don't
521 need to be saved. N.B. the call insn might set a subreg
522 of a multi-hard-reg pseudo; then the pseudo is considered
523 live during the call, but the subreg that is set
524 isn't. */
525 CLEAR_HARD_REG_SET (this_insn_sets);
526 note_stores (insn, mark_set_regs, &this_insn_sets);
527 /* Sibcalls are considered to set the return value,
528 compare df-scan.c:df_get_call_refs. */
529 if (SIBLING_CALL_P (insn) && crtl->return_rtx)
530 mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets);
531
532 used_regs &= ~(fixed_reg_set | this_insn_sets);
533 hard_regs_to_save &= used_regs & savable_regs;
534 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
535 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
536 {
537 gcc_assert (hard_reg_map[regno] != NULL);
538 call_saved_regs[call_saved_regs_num++] = hard_reg_map[regno];
539 }
540 /* Look through all live pseudos, mark their hard registers. */
541 EXECUTE_IF_SET_IN_REG_SET
542 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi)
543 {
544 int r = reg_renumber[regno];
545 int bound;
546
547 if (r < 0 || regno_reg_rtx[regno] == cheap)
548 continue;
549
550 bound = r + hard_regno_nregs (r, PSEUDO_REGNO_MODE (regno));
551 for (; r < bound; r++)
552 if (TEST_HARD_REG_BIT (used_regs, r))
553 call_saved_regs[call_saved_regs_num++] = hard_reg_map[r];
554 }
555 for (i = 0; i < call_saved_regs_num; i++)
556 {
557 saved_reg = call_saved_regs[i];
558 for (j = 0; j < call_saved_regs_num; j++)
559 if (i != j)
560 {
561 saved_reg2 = call_saved_regs[j];
562 saved_reg_conflicts[saved_reg->num * saved_regs_num
563 + saved_reg2->num]
564 = saved_reg_conflicts[saved_reg2->num * saved_regs_num
565 + saved_reg->num]
566 = TRUE;
567 }
568 }
569 }
570 /* Sort saved hard regs. */
571 qsort (all_saved_regs, saved_regs_num, sizeof (struct saved_hard_reg *),
572 saved_hard_reg_compare_func);
573 /* Initiate slots available from the previous reload
574 iteration. */
575 prev_save_slots_num = save_slots_num;
576 memcpy (prev_save_slots, save_slots, save_slots_num * sizeof (rtx));
577 save_slots_num = 0;
578 /* Allocate stack slots for the saved hard registers. */
579 for (i = 0; i < saved_regs_num; i++)
580 {
581 saved_reg = all_saved_regs[i];
582 regno = saved_reg->hard_regno;
583 for (j = 0; j < i; j++)
584 {
585 saved_reg2 = all_saved_regs[j];
586 if (! saved_reg2->first_p)
587 continue;
588 slot = saved_reg2->slot;
589 for (k = j; k >= 0; k = next_k)
590 {
591 saved_reg3 = all_saved_regs[k];
592 next_k = saved_reg3->next;
593 if (saved_reg_conflicts[saved_reg->num * saved_regs_num
594 + saved_reg3->num])
595 break;
596 }
597 if (k < 0
598 && known_le (GET_MODE_SIZE (regno_save_mode[regno][1]),
599 GET_MODE_SIZE (regno_save_mode
600 [saved_reg2->hard_regno][1])))
601 {
602 saved_reg->slot
603 = adjust_address_nv
604 (slot, regno_save_mode[saved_reg->hard_regno][1], 0);
605 regno_save_mem[regno][1] = saved_reg->slot;
606 saved_reg->next = saved_reg2->next;
607 saved_reg2->next = i;
608 if (dump_file != NULL)
609 fprintf (dump_file, "%d uses slot of %d\n",
610 regno, saved_reg2->hard_regno);
611 break;
612 }
613 }
614 if (j == i)
615 {
616 saved_reg->first_p = TRUE;
617 for (best_slot_num = -1, j = 0; j < prev_save_slots_num; j++)
618 {
619 slot = prev_save_slots[j];
620 if (slot == NULL_RTX)
621 continue;
622 if (known_le (GET_MODE_SIZE (regno_save_mode[regno][1]),
623 GET_MODE_SIZE (GET_MODE (slot)))
624 && best_slot_num < 0)
625 best_slot_num = j;
626 if (GET_MODE (slot) == regno_save_mode[regno][1])
627 break;
628 }
629 if (best_slot_num >= 0)
630 {
631 saved_reg->slot = prev_save_slots[best_slot_num];
632 saved_reg->slot
633 = adjust_address_nv
634 (saved_reg->slot,
635 regno_save_mode[saved_reg->hard_regno][1], 0);
636 if (dump_file != NULL)
637 fprintf (dump_file,
638 "%d uses a slot from prev iteration\n", regno);
639 prev_save_slots[best_slot_num] = NULL_RTX;
640 if (best_slot_num + 1 == prev_save_slots_num)
641 prev_save_slots_num--;
642 }
643 else
644 {
645 saved_reg->slot
646 = assign_stack_local_1
647 (regno_save_mode[regno][1],
648 GET_MODE_SIZE (regno_save_mode[regno][1]), 0,
649 ASLK_REDUCE_ALIGN);
650 if (dump_file != NULL)
651 fprintf (dump_file, "%d uses a new slot\n", regno);
652 }
653 regno_save_mem[regno][1] = saved_reg->slot;
654 save_slots[save_slots_num++] = saved_reg->slot;
655 }
656 }
657 free (saved_reg_conflicts);
658 finish_saved_hard_regs ();
659 }
660 else
661 {
662 /* We are not sharing slots.
663
664 Run through all the call-used hard-registers and allocate
665 space for each in the caller-save area. Try to allocate space
666 in a manner which allows multi-register saves/restores to be done. */
667
668 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
669 for (j = MOVE_MAX_WORDS; j > 0; j--)
670 {
671 int do_save = 1;
672
673 /* If no mode exists for this size, try another. Also break out
674 if we have already saved this hard register. */
675 if (regno_save_mode[i][j] == VOIDmode || regno_save_mem[i][1] != 0)
676 continue;
677
678 /* See if any register in this group has been saved. */
679 for (k = 0; k < j; k++)
680 if (regno_save_mem[i + k][1])
681 {
682 do_save = 0;
683 break;
684 }
685 if (! do_save)
686 continue;
687
688 for (k = 0; k < j; k++)
689 if (! TEST_HARD_REG_BIT (hard_regs_used, i + k))
690 {
691 do_save = 0;
692 break;
693 }
694 if (! do_save)
695 continue;
696
697 /* We have found an acceptable mode to store in. Since
698 hard register is always saved in the widest mode
699 available, the mode may be wider than necessary, it is
700 OK to reduce the alignment of spill space. We will
701 verify that it is equal to or greater than required
702 when we restore and save the hard register in
703 insert_restore and insert_save. */
704 regno_save_mem[i][j]
705 = assign_stack_local_1 (regno_save_mode[i][j],
706 GET_MODE_SIZE (regno_save_mode[i][j]),
707 0, ASLK_REDUCE_ALIGN);
708
709 /* Setup single word save area just in case... */
710 for (k = 0; k < j; k++)
711 /* This should not depend on WORDS_BIG_ENDIAN.
712 The order of words in regs is the same as in memory. */
713 regno_save_mem[i + k][1]
714 = adjust_address_nv (regno_save_mem[i][j],
715 regno_save_mode[i + k][1],
716 k * UNITS_PER_WORD);
717 }
718 }
719
720 /* Now loop again and set the alias set of any save areas we made to
721 the alias set used to represent frame objects. */
722 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
723 for (j = MOVE_MAX_WORDS; j > 0; j--)
724 if (regno_save_mem[i][j] != 0)
725 set_mem_alias_set (regno_save_mem[i][j], get_frame_alias_set ());
726 }
727
728 \f
729
730 /* Find the places where hard regs are live across calls and save them. */
731
732 void
733 save_call_clobbered_regs (void)
734 {
735 class insn_chain *chain, *next, *last = NULL;
736 machine_mode save_mode [FIRST_PSEUDO_REGISTER];
737
738 /* Computed in mark_set_regs, holds all registers set by the current
739 instruction. */
740 HARD_REG_SET this_insn_sets;
741
742 CLEAR_HARD_REG_SET (hard_regs_saved);
743 n_regs_saved = 0;
744
745 for (chain = reload_insn_chain; chain != 0; chain = next)
746 {
747 rtx_insn *insn = chain->insn;
748 enum rtx_code code = GET_CODE (insn);
749
750 next = chain->next;
751
752 gcc_assert (!chain->is_caller_save_insn);
753
754 if (NONDEBUG_INSN_P (insn))
755 {
756 /* If some registers have been saved, see if INSN references
757 any of them. We must restore them before the insn if so. */
758
759 if (n_regs_saved)
760 {
761 int regno;
762 HARD_REG_SET this_insn_sets;
763
764 if (code == JUMP_INSN)
765 /* Restore all registers if this is a JUMP_INSN. */
766 referenced_regs = hard_regs_saved;
767 else
768 {
769 CLEAR_HARD_REG_SET (referenced_regs);
770 mark_referenced_regs (&PATTERN (insn),
771 mark_reg_as_referenced, NULL);
772 referenced_regs &= hard_regs_saved;
773 }
774
775 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
776 if (TEST_HARD_REG_BIT (referenced_regs, regno))
777 regno += insert_restore (chain, 1, regno, MOVE_MAX_WORDS,
778 save_mode);
779 /* If a saved register is set after the call, this means we no
780 longer should restore it. This can happen when parts of a
781 multi-word pseudo do not conflict with other pseudos, so
782 IRA may allocate the same hard register for both. One may
783 be live across the call, while the other is set
784 afterwards. */
785 CLEAR_HARD_REG_SET (this_insn_sets);
786 note_stores (insn, mark_set_regs, &this_insn_sets);
787 hard_regs_saved &= ~this_insn_sets;
788 }
789
790 if (code == CALL_INSN
791 && ! SIBLING_CALL_P (insn)
792 && ! find_reg_note (insn, REG_NORETURN, NULL))
793 {
794 unsigned regno;
795 HARD_REG_SET hard_regs_to_save;
796 HARD_REG_SET call_def_reg_set;
797 reg_set_iterator rsi;
798 rtx cheap;
799
800 cheap = find_reg_note (insn, REG_RETURNED, NULL);
801 if (cheap)
802 cheap = XEXP (cheap, 0);
803
804 /* Use the register life information in CHAIN to compute which
805 regs are live during the call. */
806 REG_SET_TO_HARD_REG_SET (hard_regs_to_save,
807 &chain->live_throughout);
808 /* Save hard registers always in the widest mode available. */
809 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
810 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
811 save_mode [regno] = regno_save_mode [regno][1];
812 else
813 save_mode [regno] = VOIDmode;
814
815 /* Look through all live pseudos, mark their hard registers
816 and choose proper mode for saving. */
817 EXECUTE_IF_SET_IN_REG_SET
818 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, regno, rsi)
819 {
820 int r = reg_renumber[regno];
821 int nregs;
822 machine_mode mode;
823
824 if (r < 0 || regno_reg_rtx[regno] == cheap)
825 continue;
826 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (regno));
827 mode = HARD_REGNO_CALLER_SAVE_MODE
828 (r, nregs, PSEUDO_REGNO_MODE (regno));
829 if (partial_subreg_p (save_mode[r], mode))
830 save_mode[r] = mode;
831 while (nregs-- > 0)
832 SET_HARD_REG_BIT (hard_regs_to_save, r + nregs);
833 }
834
835 /* Record all registers set in this call insn. These don't need
836 to be saved. N.B. the call insn might set a subreg of a
837 multi-hard-reg pseudo; then the pseudo is considered live
838 during the call, but the subreg that is set isn't. */
839 CLEAR_HARD_REG_SET (this_insn_sets);
840 note_stores (insn, mark_set_regs, &this_insn_sets);
841
842 /* Compute which hard regs must be saved before this call. */
843 hard_regs_to_save &= ~(fixed_reg_set
844 | this_insn_sets
845 | hard_regs_saved);
846 hard_regs_to_save &= savable_regs;
847 call_def_reg_set = insn_callee_abi (insn).full_reg_clobbers ();
848 /* ??? This preserves traditional behavior; it might not
849 be needed. */
850 call_def_reg_set |= fixed_reg_set;
851 hard_regs_to_save &= call_def_reg_set;
852
853 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
854 if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
855 regno += insert_save (chain, regno,
856 &hard_regs_to_save, save_mode);
857
858 /* Must recompute n_regs_saved. */
859 n_regs_saved = 0;
860 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
861 if (TEST_HARD_REG_BIT (hard_regs_saved, regno))
862 n_regs_saved++;
863
864 if (cheap
865 && HARD_REGISTER_P (cheap)
866 && TEST_HARD_REG_BIT (call_used_or_fixed_regs,
867 REGNO (cheap)))
868 {
869 rtx dest, newpat;
870 rtx pat = PATTERN (insn);
871 if (GET_CODE (pat) == PARALLEL)
872 pat = XVECEXP (pat, 0, 0);
873 dest = SET_DEST (pat);
874 /* For multiple return values dest is PARALLEL.
875 Currently we handle only single return value case. */
876 if (REG_P (dest))
877 {
878 newpat = gen_rtx_SET (cheap, copy_rtx (dest));
879 chain = insert_one_insn (chain, 0, -1, newpat);
880 }
881 }
882 }
883 last = chain;
884 }
885 else if (DEBUG_INSN_P (insn) && n_regs_saved)
886 mark_referenced_regs (&PATTERN (insn),
887 replace_reg_with_saved_mem,
888 save_mode);
889
890 if (chain->next == 0 || chain->next->block != chain->block)
891 {
892 int regno;
893 /* At the end of the basic block, we must restore any registers that
894 remain saved. If the last insn in the block is a JUMP_INSN, put
895 the restore before the insn, otherwise, put it after the insn. */
896
897 if (n_regs_saved
898 && DEBUG_INSN_P (insn)
899 && last
900 && last->block == chain->block)
901 {
902 rtx_insn *ins, *prev;
903 basic_block bb = BLOCK_FOR_INSN (insn);
904
905 /* When adding hard reg restores after a DEBUG_INSN, move
906 all notes between last real insn and this DEBUG_INSN after
907 the DEBUG_INSN, otherwise we could get code
908 -g/-g0 differences. */
909 for (ins = PREV_INSN (insn); ins != last->insn; ins = prev)
910 {
911 prev = PREV_INSN (ins);
912 if (NOTE_P (ins))
913 {
914 SET_NEXT_INSN (prev) = NEXT_INSN (ins);
915 SET_PREV_INSN (NEXT_INSN (ins)) = prev;
916 SET_PREV_INSN (ins) = insn;
917 SET_NEXT_INSN (ins) = NEXT_INSN (insn);
918 SET_NEXT_INSN (insn) = ins;
919 if (NEXT_INSN (ins))
920 SET_PREV_INSN (NEXT_INSN (ins)) = ins;
921 if (BB_END (bb) == insn)
922 BB_END (bb) = ins;
923 }
924 else
925 gcc_assert (DEBUG_INSN_P (ins));
926 }
927 }
928 last = NULL;
929
930 if (n_regs_saved)
931 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
932 if (TEST_HARD_REG_BIT (hard_regs_saved, regno))
933 regno += insert_restore (chain, JUMP_P (insn),
934 regno, MOVE_MAX_WORDS, save_mode);
935 }
936 }
937 }
938
939 /* Here from note_stores, or directly from save_call_clobbered_regs, when
940 an insn stores a value in a register.
941 Set the proper bit or bits in this_insn_sets. All pseudos that have
942 been assigned hard regs have had their register number changed already,
943 so we can ignore pseudos. */
944 static void
945 mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data)
946 {
947 int regno, endregno, i;
948 HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data;
949
950 if (GET_CODE (reg) == SUBREG)
951 {
952 rtx inner = SUBREG_REG (reg);
953 if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER)
954 return;
955 regno = subreg_regno (reg);
956 endregno = regno + subreg_nregs (reg);
957 }
958 else if (REG_P (reg)
959 && REGNO (reg) < FIRST_PSEUDO_REGISTER)
960 {
961 regno = REGNO (reg);
962 endregno = END_REGNO (reg);
963 }
964 else
965 return;
966
967 for (i = regno; i < endregno; i++)
968 SET_HARD_REG_BIT (*this_insn_sets, i);
969 }
970
971 /* Here from note_stores when an insn stores a value in a register.
972 Set the proper bit or bits in the passed regset. All pseudos that have
973 been assigned hard regs have had their register number changed already,
974 so we can ignore pseudos. */
975 static void
976 add_stored_regs (rtx reg, const_rtx setter, void *data)
977 {
978 int regno, endregno, i;
979 machine_mode mode = GET_MODE (reg);
980 int offset = 0;
981
982 if (GET_CODE (setter) == CLOBBER)
983 return;
984
985 if (GET_CODE (reg) == SUBREG
986 && REG_P (SUBREG_REG (reg))
987 && REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER)
988 {
989 offset = subreg_regno_offset (REGNO (SUBREG_REG (reg)),
990 GET_MODE (SUBREG_REG (reg)),
991 SUBREG_BYTE (reg),
992 GET_MODE (reg));
993 regno = REGNO (SUBREG_REG (reg)) + offset;
994 endregno = regno + subreg_nregs (reg);
995 }
996 else
997 {
998 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
999 return;
1000
1001 regno = REGNO (reg) + offset;
1002 endregno = end_hard_regno (mode, regno);
1003 }
1004
1005 for (i = regno; i < endregno; i++)
1006 SET_REGNO_REG_SET ((regset) data, i);
1007 }
1008
1009 /* Walk X and record all referenced registers in REFERENCED_REGS. */
1010 static void
1011 mark_referenced_regs (rtx *loc, refmarker_fn *mark, void *arg)
1012 {
1013 enum rtx_code code = GET_CODE (*loc);
1014 const char *fmt;
1015 int i, j;
1016
1017 if (code == SET)
1018 mark_referenced_regs (&SET_SRC (*loc), mark, arg);
1019 if (code == SET || code == CLOBBER)
1020 {
1021 loc = &SET_DEST (*loc);
1022 code = GET_CODE (*loc);
1023 if ((code == REG && REGNO (*loc) < FIRST_PSEUDO_REGISTER)
1024 || code == PC || code == CC0
1025 || (code == SUBREG && REG_P (SUBREG_REG (*loc))
1026 && REGNO (SUBREG_REG (*loc)) < FIRST_PSEUDO_REGISTER
1027 /* If we're setting only part of a multi-word register,
1028 we shall mark it as referenced, because the words
1029 that are not being set should be restored. */
1030 && !read_modify_subreg_p (*loc)))
1031 return;
1032 }
1033 if (code == MEM || code == SUBREG)
1034 {
1035 loc = &XEXP (*loc, 0);
1036 code = GET_CODE (*loc);
1037 }
1038
1039 if (code == REG)
1040 {
1041 int regno = REGNO (*loc);
1042 int hardregno = (regno < FIRST_PSEUDO_REGISTER ? regno
1043 : reg_renumber[regno]);
1044
1045 if (hardregno >= 0)
1046 mark (loc, GET_MODE (*loc), hardregno, arg);
1047 else if (arg)
1048 /* ??? Will we ever end up with an equiv expression in a debug
1049 insn, that would have required restoring a reg, or will
1050 reload take care of it for us? */
1051 return;
1052 /* If this is a pseudo that did not get a hard register, scan its
1053 memory location, since it might involve the use of another
1054 register, which might be saved. */
1055 else if (reg_equiv_mem (regno) != 0)
1056 mark_referenced_regs (&XEXP (reg_equiv_mem (regno), 0), mark, arg);
1057 else if (reg_equiv_address (regno) != 0)
1058 mark_referenced_regs (&reg_equiv_address (regno), mark, arg);
1059 return;
1060 }
1061
1062 fmt = GET_RTX_FORMAT (code);
1063 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1064 {
1065 if (fmt[i] == 'e')
1066 mark_referenced_regs (&XEXP (*loc, i), mark, arg);
1067 else if (fmt[i] == 'E')
1068 for (j = XVECLEN (*loc, i) - 1; j >= 0; j--)
1069 mark_referenced_regs (&XVECEXP (*loc, i, j), mark, arg);
1070 }
1071 }
1072
1073 /* Parameter function for mark_referenced_regs() that adds registers
1074 present in the insn and in equivalent mems and addresses to
1075 referenced_regs. */
1076
1077 static void
1078 mark_reg_as_referenced (rtx *loc ATTRIBUTE_UNUSED,
1079 machine_mode mode,
1080 int hardregno,
1081 void *arg ATTRIBUTE_UNUSED)
1082 {
1083 add_to_hard_reg_set (&referenced_regs, mode, hardregno);
1084 }
1085
1086 /* Parameter function for mark_referenced_regs() that replaces
1087 registers referenced in a debug_insn that would have been restored,
1088 should it be a non-debug_insn, with their save locations. */
1089
1090 static void
1091 replace_reg_with_saved_mem (rtx *loc,
1092 machine_mode mode,
1093 int regno,
1094 void *arg)
1095 {
1096 unsigned int i, nregs = hard_regno_nregs (regno, mode);
1097 rtx mem;
1098 machine_mode *save_mode = (machine_mode *)arg;
1099
1100 for (i = 0; i < nregs; i++)
1101 if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i))
1102 break;
1103
1104 /* If none of the registers in the range would need restoring, we're
1105 all set. */
1106 if (i == nregs)
1107 return;
1108
1109 while (++i < nregs)
1110 if (!TEST_HARD_REG_BIT (hard_regs_saved, regno + i))
1111 break;
1112
1113 if (i == nregs
1114 && regno_save_mem[regno][nregs])
1115 {
1116 mem = copy_rtx (regno_save_mem[regno][nregs]);
1117
1118 if (nregs == hard_regno_nregs (regno, save_mode[regno]))
1119 mem = adjust_address_nv (mem, save_mode[regno], 0);
1120
1121 if (GET_MODE (mem) != mode)
1122 {
1123 /* This is gen_lowpart_if_possible(), but without validating
1124 the newly-formed address. */
1125 poly_int64 offset = byte_lowpart_offset (mode, GET_MODE (mem));
1126 mem = adjust_address_nv (mem, mode, offset);
1127 }
1128 }
1129 else
1130 {
1131 mem = gen_rtx_CONCATN (mode, rtvec_alloc (nregs));
1132 for (i = 0; i < nregs; i++)
1133 if (TEST_HARD_REG_BIT (hard_regs_saved, regno + i))
1134 {
1135 gcc_assert (regno_save_mem[regno + i][1]);
1136 XVECEXP (mem, 0, i) = copy_rtx (regno_save_mem[regno + i][1]);
1137 }
1138 else
1139 {
1140 machine_mode smode = save_mode[regno];
1141 gcc_assert (smode != VOIDmode);
1142 if (hard_regno_nregs (regno, smode) > 1)
1143 smode = mode_for_size (exact_div (GET_MODE_BITSIZE (mode),
1144 nregs),
1145 GET_MODE_CLASS (mode), 0).require ();
1146 XVECEXP (mem, 0, i) = gen_rtx_REG (smode, regno + i);
1147 }
1148 }
1149
1150 gcc_assert (GET_MODE (mem) == mode);
1151 *loc = mem;
1152 }
1153
1154 \f
1155 /* Insert a sequence of insns to restore. Place these insns in front of
1156 CHAIN if BEFORE_P is nonzero, behind the insn otherwise. MAXRESTORE is
1157 the maximum number of registers which should be restored during this call.
1158 It should never be less than 1 since we only work with entire registers.
1159
1160 Note that we have verified in init_caller_save that we can do this
1161 with a simple SET, so use it. Set INSN_CODE to what we save there
1162 since the address might not be valid so the insn might not be recognized.
1163 These insns will be reloaded and have register elimination done by
1164 find_reload, so we need not worry about that here.
1165
1166 Return the extra number of registers saved. */
1167
1168 static int
1169 insert_restore (class insn_chain *chain, int before_p, int regno,
1170 int maxrestore, machine_mode *save_mode)
1171 {
1172 int i, k;
1173 rtx pat = NULL_RTX;
1174 int code;
1175 unsigned int numregs = 0;
1176 class insn_chain *new_chain;
1177 rtx mem;
1178
1179 /* A common failure mode if register status is not correct in the
1180 RTL is for this routine to be called with a REGNO we didn't
1181 expect to save. That will cause us to write an insn with a (nil)
1182 SET_DEST or SET_SRC. Instead of doing so and causing a crash
1183 later, check for this common case here instead. This will remove
1184 one step in debugging such problems. */
1185 gcc_assert (regno_save_mem[regno][1]);
1186
1187 /* Get the pattern to emit and update our status.
1188
1189 See if we can restore `maxrestore' registers at once. Work
1190 backwards to the single register case. */
1191 for (i = maxrestore; i > 0; i--)
1192 {
1193 int j;
1194 int ok = 1;
1195
1196 if (regno_save_mem[regno][i] == 0)
1197 continue;
1198
1199 for (j = 0; j < i; j++)
1200 if (! TEST_HARD_REG_BIT (hard_regs_saved, regno + j))
1201 {
1202 ok = 0;
1203 break;
1204 }
1205 /* Must do this one restore at a time. */
1206 if (! ok)
1207 continue;
1208
1209 numregs = i;
1210 break;
1211 }
1212
1213 mem = regno_save_mem [regno][numregs];
1214 if (save_mode [regno] != VOIDmode
1215 && save_mode [regno] != GET_MODE (mem)
1216 && numregs == hard_regno_nregs (regno, save_mode [regno])
1217 /* Check that insn to restore REGNO in save_mode[regno] is
1218 correct. */
1219 && reg_save_code (regno, save_mode[regno]) >= 0)
1220 mem = adjust_address_nv (mem, save_mode[regno], 0);
1221 else
1222 mem = copy_rtx (mem);
1223
1224 /* Verify that the alignment of spill space is equal to or greater
1225 than required. */
1226 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT,
1227 GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem));
1228
1229 pat = gen_rtx_SET (gen_rtx_REG (GET_MODE (mem), regno), mem);
1230 code = reg_restore_code (regno, GET_MODE (mem));
1231 new_chain = insert_one_insn (chain, before_p, code, pat);
1232
1233 /* Clear status for all registers we restored. */
1234 for (k = 0; k < i; k++)
1235 {
1236 CLEAR_HARD_REG_BIT (hard_regs_saved, regno + k);
1237 SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k);
1238 n_regs_saved--;
1239 }
1240
1241 /* Tell our callers how many extra registers we saved/restored. */
1242 return numregs - 1;
1243 }
1244
1245 /* Like insert_restore above, but save registers instead. */
1246
1247 static int
1248 insert_save (class insn_chain *chain, int regno,
1249 HARD_REG_SET *to_save, machine_mode *save_mode)
1250 {
1251 int i;
1252 unsigned int k;
1253 rtx pat = NULL_RTX;
1254 int code;
1255 unsigned int numregs = 0;
1256 class insn_chain *new_chain;
1257 rtx mem;
1258
1259 /* A common failure mode if register status is not correct in the
1260 RTL is for this routine to be called with a REGNO we didn't
1261 expect to save. That will cause us to write an insn with a (nil)
1262 SET_DEST or SET_SRC. Instead of doing so and causing a crash
1263 later, check for this common case here. This will remove one
1264 step in debugging such problems. */
1265 gcc_assert (regno_save_mem[regno][1]);
1266
1267 /* Get the pattern to emit and update our status.
1268
1269 See if we can save several registers with a single instruction.
1270 Work backwards to the single register case. */
1271 for (i = MOVE_MAX_WORDS; i > 0; i--)
1272 {
1273 int j;
1274 int ok = 1;
1275 if (regno_save_mem[regno][i] == 0)
1276 continue;
1277
1278 for (j = 0; j < i; j++)
1279 if (! TEST_HARD_REG_BIT (*to_save, regno + j))
1280 {
1281 ok = 0;
1282 break;
1283 }
1284 /* Must do this one save at a time. */
1285 if (! ok)
1286 continue;
1287
1288 numregs = i;
1289 break;
1290 }
1291
1292 mem = regno_save_mem [regno][numregs];
1293 if (save_mode [regno] != VOIDmode
1294 && save_mode [regno] != GET_MODE (mem)
1295 && numregs == hard_regno_nregs (regno, save_mode [regno])
1296 /* Check that insn to save REGNO in save_mode[regno] is
1297 correct. */
1298 && reg_save_code (regno, save_mode[regno]) >= 0)
1299 mem = adjust_address_nv (mem, save_mode[regno], 0);
1300 else
1301 mem = copy_rtx (mem);
1302
1303 /* Verify that the alignment of spill space is equal to or greater
1304 than required. */
1305 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT,
1306 GET_MODE_ALIGNMENT (GET_MODE (mem))) <= MEM_ALIGN (mem));
1307
1308 pat = gen_rtx_SET (mem, gen_rtx_REG (GET_MODE (mem), regno));
1309 code = reg_save_code (regno, GET_MODE (mem));
1310 new_chain = insert_one_insn (chain, 1, code, pat);
1311
1312 /* Set hard_regs_saved and dead_or_set for all the registers we saved. */
1313 for (k = 0; k < numregs; k++)
1314 {
1315 SET_HARD_REG_BIT (hard_regs_saved, regno + k);
1316 SET_REGNO_REG_SET (&new_chain->dead_or_set, regno + k);
1317 n_regs_saved++;
1318 }
1319
1320 /* Tell our callers how many extra registers we saved/restored. */
1321 return numregs - 1;
1322 }
1323
1324 /* A note_uses callback used by insert_one_insn. Add the hard-register
1325 equivalent of each REG to regset DATA. */
1326
1327 static void
1328 add_used_regs (rtx *loc, void *data)
1329 {
1330 subrtx_iterator::array_type array;
1331 FOR_EACH_SUBRTX (iter, array, *loc, NONCONST)
1332 {
1333 const_rtx x = *iter;
1334 if (REG_P (x))
1335 {
1336 unsigned int regno = REGNO (x);
1337 if (HARD_REGISTER_NUM_P (regno))
1338 bitmap_set_range ((regset) data, regno, REG_NREGS (x));
1339 else
1340 gcc_checking_assert (reg_renumber[regno] < 0);
1341 }
1342 }
1343 }
1344
1345 /* Emit a new caller-save insn and set the code. */
1346 static class insn_chain *
1347 insert_one_insn (class insn_chain *chain, int before_p, int code, rtx pat)
1348 {
1349 rtx_insn *insn = chain->insn;
1350 class insn_chain *new_chain;
1351
1352 /* If INSN references CC0, put our insns in front of the insn that sets
1353 CC0. This is always safe, since the only way we could be passed an
1354 insn that references CC0 is for a restore, and doing a restore earlier
1355 isn't a problem. We do, however, assume here that CALL_INSNs don't
1356 reference CC0. Guard against non-INSN's like CODE_LABEL. */
1357
1358 if (HAVE_cc0 && (NONJUMP_INSN_P (insn) || JUMP_P (insn))
1359 && before_p
1360 && reg_referenced_p (cc0_rtx, PATTERN (insn)))
1361 chain = chain->prev, insn = chain->insn;
1362
1363 new_chain = new_insn_chain ();
1364 if (before_p)
1365 {
1366 rtx link;
1367
1368 new_chain->prev = chain->prev;
1369 if (new_chain->prev != 0)
1370 new_chain->prev->next = new_chain;
1371 else
1372 reload_insn_chain = new_chain;
1373
1374 chain->prev = new_chain;
1375 new_chain->next = chain;
1376 new_chain->insn = emit_insn_before (pat, insn);
1377 /* ??? It would be nice if we could exclude the already / still saved
1378 registers from the live sets. */
1379 COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout);
1380 note_uses (&PATTERN (chain->insn), add_used_regs,
1381 &new_chain->live_throughout);
1382 /* If CHAIN->INSN is a call, then the registers which contain
1383 the arguments to the function are live in the new insn. */
1384 if (CALL_P (chain->insn))
1385 for (link = CALL_INSN_FUNCTION_USAGE (chain->insn);
1386 link != NULL_RTX;
1387 link = XEXP (link, 1))
1388 note_uses (&XEXP (link, 0), add_used_regs,
1389 &new_chain->live_throughout);
1390
1391 CLEAR_REG_SET (&new_chain->dead_or_set);
1392 if (chain->insn == BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block)))
1393 BB_HEAD (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn;
1394 }
1395 else
1396 {
1397 new_chain->next = chain->next;
1398 if (new_chain->next != 0)
1399 new_chain->next->prev = new_chain;
1400 chain->next = new_chain;
1401 new_chain->prev = chain;
1402 new_chain->insn = emit_insn_after (pat, insn);
1403 /* ??? It would be nice if we could exclude the already / still saved
1404 registers from the live sets, and observe REG_UNUSED notes. */
1405 COPY_REG_SET (&new_chain->live_throughout, &chain->live_throughout);
1406 /* Registers that are set in CHAIN->INSN live in the new insn.
1407 (Unless there is a REG_UNUSED note for them, but we don't
1408 look for them here.) */
1409 note_stores (chain->insn, add_stored_regs, &new_chain->live_throughout);
1410 CLEAR_REG_SET (&new_chain->dead_or_set);
1411 if (chain->insn == BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block)))
1412 BB_END (BASIC_BLOCK_FOR_FN (cfun, chain->block)) = new_chain->insn;
1413 }
1414 new_chain->block = chain->block;
1415 new_chain->is_caller_save_insn = 1;
1416
1417 INSN_CODE (new_chain->insn) = code;
1418 return new_chain;
1419 }
1420 #include "gt-caller-save.h"