1 /* Save and restore call-clobbered registers which are live across a call.
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
30 #include "insn-config.h"
36 #include "addresses.h"
41 #define MOVE_MAX_WORDS (MOVE_MAX / UNITS_PER_WORD)
43 #define regno_save_mode \
44 (this_target_reload->x_regno_save_mode)
45 #define cached_reg_save_code \
46 (this_target_reload->x_cached_reg_save_code)
47 #define cached_reg_restore_code \
48 (this_target_reload->x_cached_reg_restore_code)
50 /* For each hard register, a place on the stack where it can be saved,
54 regno_save_mem
[FIRST_PSEUDO_REGISTER
][MAX_MOVE_MAX
/ MIN_UNITS_PER_WORD
+ 1];
56 /* The number of elements in the subsequent array. */
57 static int save_slots_num
;
59 /* Allocated slots so far. */
60 static rtx save_slots
[FIRST_PSEUDO_REGISTER
];
62 /* Set of hard regs currently residing in save area (during insn scan). */
64 static HARD_REG_SET hard_regs_saved
;
66 /* Number of registers currently in hard_regs_saved. */
68 static int n_regs_saved
;
70 /* Computed by mark_referenced_regs, all regs referenced in a given
72 static HARD_REG_SET referenced_regs
;
75 typedef void refmarker_fn (rtx
*loc
, machine_mode mode
, int hardregno
,
78 static int reg_save_code (int, machine_mode
);
79 static int reg_restore_code (int, machine_mode
);
81 struct saved_hard_reg
;
82 static void initiate_saved_hard_regs (void);
83 static void new_saved_hard_reg (int, int);
84 static void finish_saved_hard_regs (void);
85 static int saved_hard_reg_compare_func (const void *, const void *);
87 static void mark_set_regs (rtx
, const_rtx
, void *);
88 static void mark_referenced_regs (rtx
*, refmarker_fn
*mark
, void *mark_arg
);
89 static refmarker_fn mark_reg_as_referenced
;
90 static refmarker_fn replace_reg_with_saved_mem
;
91 static int insert_save (class insn_chain
*, int, HARD_REG_SET
*,
93 static int insert_restore (class insn_chain
*, int, int, int,
95 static class insn_chain
*insert_one_insn (class insn_chain
*, int, int,
97 static void add_stored_regs (rtx
, const_rtx
, void *);
101 static GTY(()) rtx savepat
;
102 static GTY(()) rtx restpat
;
103 static GTY(()) rtx test_reg
;
104 static GTY(()) rtx test_mem
;
105 static GTY(()) rtx_insn
*saveinsn
;
106 static GTY(()) rtx_insn
*restinsn
;
108 /* Return the INSN_CODE used to save register REG in mode MODE. */
110 reg_save_code (int reg
, machine_mode mode
)
113 if (cached_reg_save_code
[reg
][mode
])
114 return cached_reg_save_code
[reg
][mode
];
115 if (!targetm
.hard_regno_mode_ok (reg
, mode
))
117 /* Depending on how targetm.hard_regno_mode_ok is defined, range
118 propagation might deduce here that reg >= FIRST_PSEUDO_REGISTER.
119 So the assert below silences a warning. */
120 gcc_assert (reg
< FIRST_PSEUDO_REGISTER
);
121 cached_reg_save_code
[reg
][mode
] = -1;
122 cached_reg_restore_code
[reg
][mode
] = -1;
126 /* Update the register number and modes of the register
127 and memory operand. */
128 set_mode_and_regno (test_reg
, mode
, reg
);
129 PUT_MODE (test_mem
, mode
);
131 /* Force re-recognition of the modified insns. */
132 INSN_CODE (saveinsn
) = -1;
133 INSN_CODE (restinsn
) = -1;
135 cached_reg_save_code
[reg
][mode
] = recog_memoized (saveinsn
);
136 cached_reg_restore_code
[reg
][mode
] = recog_memoized (restinsn
);
138 /* Now extract both insns and see if we can meet their
139 constraints. We don't know here whether the save and restore will
140 be in size- or speed-tuned code, so just use the set of enabled
142 ok
= (cached_reg_save_code
[reg
][mode
] != -1
143 && cached_reg_restore_code
[reg
][mode
] != -1);
146 extract_insn (saveinsn
);
147 ok
= constrain_operands (1, get_enabled_alternatives (saveinsn
));
148 extract_insn (restinsn
);
149 ok
&= constrain_operands (1, get_enabled_alternatives (restinsn
));
154 cached_reg_save_code
[reg
][mode
] = -1;
155 cached_reg_restore_code
[reg
][mode
] = -1;
157 gcc_assert (cached_reg_save_code
[reg
][mode
]);
158 return cached_reg_save_code
[reg
][mode
];
161 /* Return the INSN_CODE used to restore register REG in mode MODE. */
163 reg_restore_code (int reg
, machine_mode mode
)
165 if (cached_reg_restore_code
[reg
][mode
])
166 return cached_reg_restore_code
[reg
][mode
];
167 /* Populate our cache. */
168 reg_save_code (reg
, mode
);
169 return cached_reg_restore_code
[reg
][mode
];
172 /* Initialize for caller-save.
174 Look at all the hard registers that are used by a call and for which
175 reginfo.c has not already excluded from being used across a call.
177 Ensure that we can find a mode to save the register and that there is a
178 simple insn to save and restore the register. This latter check avoids
179 problems that would occur if we tried to save the MQ register of some
180 machines directly into memory. */
183 init_caller_save (void)
190 if (caller_save_initialized_p
)
193 caller_save_initialized_p
= true;
195 /* First find all the registers that we need to deal with and all
196 the modes that they can have. If we can't find a mode to use,
197 we can't have the register live over calls. */
199 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
200 for (j
= 1; j
<= MOVE_MAX_WORDS
; j
++)
202 regno_save_mode
[i
][j
] = HARD_REGNO_CALLER_SAVE_MODE (i
, j
, VOIDmode
);
203 if (regno_save_mode
[i
][j
] == VOIDmode
&& j
== 1)
204 CLEAR_HARD_REG_BIT (savable_regs
, i
);
207 /* The following code tries to approximate the conditions under which
208 we can easily save and restore a register without scratch registers or
209 other complexities. It will usually work, except under conditions where
210 the validity of an insn operand is dependent on the address offset.
211 No such cases are currently known.
213 We first find a typical offset from some BASE_REG_CLASS register.
214 This address is chosen by finding the first register in the class
215 and by finding the smallest power of two that is a valid offset from
216 that register in every mode we will use to save registers. */
218 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
219 if (TEST_HARD_REG_BIT
221 [(int) base_reg_class (regno_save_mode
[i
][1], ADDR_SPACE_GENERIC
,
222 PLUS
, CONST_INT
)], i
))
225 gcc_assert (i
< FIRST_PSEUDO_REGISTER
);
227 addr_reg
= gen_rtx_REG (Pmode
, i
);
229 for (offset
= 1 << (HOST_BITS_PER_INT
/ 2); offset
; offset
>>= 1)
231 address
= gen_rtx_PLUS (Pmode
, addr_reg
, gen_int_mode (offset
, Pmode
));
233 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
234 if (regno_save_mode
[i
][1] != VOIDmode
235 && ! strict_memory_address_p (regno_save_mode
[i
][1], address
))
238 if (i
== FIRST_PSEUDO_REGISTER
)
242 /* If we didn't find a valid address, we must use register indirect. */
246 /* Next we try to form an insn to save and restore the register. We
247 see if such an insn is recognized and meets its constraints.
249 To avoid lots of unnecessary RTL allocation, we construct all the RTL
250 once, then modify the memory and register operands in-place. */
252 test_reg
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
253 test_mem
= gen_rtx_MEM (word_mode
, address
);
254 savepat
= gen_rtx_SET (test_mem
, test_reg
);
255 restpat
= gen_rtx_SET (test_reg
, test_mem
);
257 saveinsn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, savepat
, 0, -1, 0);
258 restinsn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, restpat
, 0, -1, 0);
260 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
261 for (j
= 1; j
<= MOVE_MAX_WORDS
; j
++)
262 if (reg_save_code (i
,regno_save_mode
[i
][j
]) == -1)
264 regno_save_mode
[i
][j
] = VOIDmode
;
266 CLEAR_HARD_REG_BIT (savable_regs
, i
);
272 /* Initialize save areas by showing that we haven't allocated any yet. */
275 init_save_areas (void)
279 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
280 for (j
= 1; j
<= MOVE_MAX_WORDS
; j
++)
281 regno_save_mem
[i
][j
] = 0;
286 /* The structure represents a hard register which should be saved
287 through the call. It is used when the integrated register
288 allocator (IRA) is used and sharing save slots is on. */
289 struct saved_hard_reg
291 /* Order number starting with 0. */
293 /* The hard regno. */
295 /* Execution frequency of all calls through which given hard
296 register should be saved. */
298 /* Stack slot reserved to save the hard register through calls. */
300 /* True if it is first hard register in the chain of hard registers
301 sharing the same stack slot. */
303 /* Order number of the next hard register structure with the same
304 slot in the chain. -1 represents end of the chain. */
308 /* Map: hard register number to the corresponding structure. */
309 static struct saved_hard_reg
*hard_reg_map
[FIRST_PSEUDO_REGISTER
];
311 /* The number of all structures representing hard registers should be
312 saved, in order words, the number of used elements in the following
314 static int saved_regs_num
;
316 /* Pointers to all the structures. Index is the order number of the
317 corresponding structure. */
318 static struct saved_hard_reg
*all_saved_regs
[FIRST_PSEUDO_REGISTER
];
320 /* First called function for work with saved hard registers. */
322 initiate_saved_hard_regs (void)
327 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
328 hard_reg_map
[i
] = NULL
;
331 /* Allocate and return new saved hard register with given REGNO and
334 new_saved_hard_reg (int regno
, int call_freq
)
336 struct saved_hard_reg
*saved_reg
;
339 = (struct saved_hard_reg
*) xmalloc (sizeof (struct saved_hard_reg
));
340 hard_reg_map
[regno
] = all_saved_regs
[saved_regs_num
] = saved_reg
;
341 saved_reg
->num
= saved_regs_num
++;
342 saved_reg
->hard_regno
= regno
;
343 saved_reg
->call_freq
= call_freq
;
344 saved_reg
->first_p
= FALSE
;
345 saved_reg
->next
= -1;
348 /* Free memory allocated for the saved hard registers. */
350 finish_saved_hard_regs (void)
354 for (i
= 0; i
< saved_regs_num
; i
++)
355 free (all_saved_regs
[i
]);
358 /* The function is used to sort the saved hard register structures
359 according their frequency. */
361 saved_hard_reg_compare_func (const void *v1p
, const void *v2p
)
363 const struct saved_hard_reg
*p1
= *(struct saved_hard_reg
* const *) v1p
;
364 const struct saved_hard_reg
*p2
= *(struct saved_hard_reg
* const *) v2p
;
366 if (flag_omit_frame_pointer
)
368 if (p1
->call_freq
- p2
->call_freq
!= 0)
369 return p1
->call_freq
- p2
->call_freq
;
371 else if (p2
->call_freq
- p1
->call_freq
!= 0)
372 return p2
->call_freq
- p1
->call_freq
;
374 return p1
->num
- p2
->num
;
377 /* Allocate save areas for any hard registers that might need saving.
378 We take a conservative approach here and look for call-clobbered hard
379 registers that are assigned to pseudos that cross calls. This may
380 overestimate slightly (especially if some of these registers are later
381 used as spill registers), but it should not be significant.
383 For IRA we use priority coloring to decrease stack slots needed for
384 saving hard registers through calls. We build conflicts for them
389 In the fallback case we should iterate backwards across all possible
390 modes for the save, choosing the largest available one instead of
391 falling back to the smallest mode immediately. (eg TF -> DF -> SF).
393 We do not try to use "move multiple" instructions that exist
394 on some machines (such as the 68k moveml). It could be a win to try
395 and use them when possible. The hard part is doing it in a way that is
396 machine independent since they might be saving non-consecutive
397 registers. (imagine caller-saving d0,d1,a0,a1 on the 68k) */
400 setup_save_areas (void)
403 HARD_REG_SET hard_regs_used
;
404 struct saved_hard_reg
*saved_reg
;
406 class insn_chain
*chain
, *next
;
408 HARD_REG_SET hard_regs_to_save
, used_regs
, this_insn_sets
;
409 reg_set_iterator rsi
;
411 CLEAR_HARD_REG_SET (hard_regs_used
);
413 /* Find every CALL_INSN and record which hard regs are live across the
414 call into HARD_REG_MAP and HARD_REGS_USED. */
415 initiate_saved_hard_regs ();
416 /* Create hard reg saved regs. */
417 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
424 || find_reg_note (insn
, REG_NORETURN
, NULL
))
426 freq
= REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn
));
427 REG_SET_TO_HARD_REG_SET (hard_regs_to_save
,
428 &chain
->live_throughout
);
429 get_call_reg_set_usage (insn
, &used_regs
, call_used_or_fixed_regs
);
431 /* Record all registers set in this call insn. These don't
432 need to be saved. N.B. the call insn might set a subreg
433 of a multi-hard-reg pseudo; then the pseudo is considered
434 live during the call, but the subreg that is set
436 CLEAR_HARD_REG_SET (this_insn_sets
);
437 note_stores (insn
, mark_set_regs
, &this_insn_sets
);
438 /* Sibcalls are considered to set the return value. */
439 if (SIBLING_CALL_P (insn
) && crtl
->return_rtx
)
440 mark_set_regs (crtl
->return_rtx
, NULL_RTX
, &this_insn_sets
);
442 used_regs
&= ~(fixed_reg_set
| this_insn_sets
);
443 hard_regs_to_save
&= used_regs
& savable_regs
;
444 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
445 if (TEST_HARD_REG_BIT (hard_regs_to_save
, regno
))
447 if (hard_reg_map
[regno
] != NULL
)
448 hard_reg_map
[regno
]->call_freq
+= freq
;
450 new_saved_hard_reg (regno
, freq
);
451 SET_HARD_REG_BIT (hard_regs_used
, regno
);
453 cheap
= find_reg_note (insn
, REG_RETURNED
, NULL
);
455 cheap
= XEXP (cheap
, 0);
456 /* Look through all live pseudos, mark their hard registers. */
457 EXECUTE_IF_SET_IN_REG_SET
458 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
460 int r
= reg_renumber
[regno
];
463 if (r
< 0 || regno_reg_rtx
[regno
] == cheap
)
466 bound
= r
+ hard_regno_nregs (r
, PSEUDO_REGNO_MODE (regno
));
467 for (; r
< bound
; r
++)
468 if (TEST_HARD_REG_BIT (used_regs
, r
))
470 if (hard_reg_map
[r
] != NULL
)
471 hard_reg_map
[r
]->call_freq
+= freq
;
473 new_saved_hard_reg (r
, freq
);
474 SET_HARD_REG_BIT (hard_regs_to_save
, r
);
475 SET_HARD_REG_BIT (hard_regs_used
, r
);
480 /* If requested, figure out which hard regs can share save slots. */
481 if (optimize
&& flag_ira_share_save_slots
)
484 char *saved_reg_conflicts
;
486 struct saved_hard_reg
*saved_reg2
, *saved_reg3
;
487 int call_saved_regs_num
;
488 struct saved_hard_reg
*call_saved_regs
[FIRST_PSEUDO_REGISTER
];
490 int prev_save_slots_num
;
491 rtx prev_save_slots
[FIRST_PSEUDO_REGISTER
];
493 /* Find saved hard register conflicts. */
494 saved_reg_conflicts
= (char *) xmalloc (saved_regs_num
* saved_regs_num
);
495 memset (saved_reg_conflicts
, 0, saved_regs_num
* saved_regs_num
);
496 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
499 call_saved_regs_num
= 0;
503 || find_reg_note (insn
, REG_NORETURN
, NULL
))
506 cheap
= find_reg_note (insn
, REG_RETURNED
, NULL
);
508 cheap
= XEXP (cheap
, 0);
510 REG_SET_TO_HARD_REG_SET (hard_regs_to_save
,
511 &chain
->live_throughout
);
512 get_call_reg_set_usage (insn
, &used_regs
, call_used_or_fixed_regs
);
514 /* Record all registers set in this call insn. These don't
515 need to be saved. N.B. the call insn might set a subreg
516 of a multi-hard-reg pseudo; then the pseudo is considered
517 live during the call, but the subreg that is set
519 CLEAR_HARD_REG_SET (this_insn_sets
);
520 note_stores (insn
, mark_set_regs
, &this_insn_sets
);
521 /* Sibcalls are considered to set the return value,
522 compare df-scan.c:df_get_call_refs. */
523 if (SIBLING_CALL_P (insn
) && crtl
->return_rtx
)
524 mark_set_regs (crtl
->return_rtx
, NULL_RTX
, &this_insn_sets
);
526 used_regs
&= ~(fixed_reg_set
| this_insn_sets
);
527 hard_regs_to_save
&= used_regs
& savable_regs
;
528 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
529 if (TEST_HARD_REG_BIT (hard_regs_to_save
, regno
))
531 gcc_assert (hard_reg_map
[regno
] != NULL
);
532 call_saved_regs
[call_saved_regs_num
++] = hard_reg_map
[regno
];
534 /* Look through all live pseudos, mark their hard registers. */
535 EXECUTE_IF_SET_IN_REG_SET
536 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
538 int r
= reg_renumber
[regno
];
541 if (r
< 0 || regno_reg_rtx
[regno
] == cheap
)
544 bound
= r
+ hard_regno_nregs (r
, PSEUDO_REGNO_MODE (regno
));
545 for (; r
< bound
; r
++)
546 if (TEST_HARD_REG_BIT (used_regs
, r
))
547 call_saved_regs
[call_saved_regs_num
++] = hard_reg_map
[r
];
549 for (i
= 0; i
< call_saved_regs_num
; i
++)
551 saved_reg
= call_saved_regs
[i
];
552 for (j
= 0; j
< call_saved_regs_num
; j
++)
555 saved_reg2
= call_saved_regs
[j
];
556 saved_reg_conflicts
[saved_reg
->num
* saved_regs_num
558 = saved_reg_conflicts
[saved_reg2
->num
* saved_regs_num
564 /* Sort saved hard regs. */
565 qsort (all_saved_regs
, saved_regs_num
, sizeof (struct saved_hard_reg
*),
566 saved_hard_reg_compare_func
);
567 /* Initiate slots available from the previous reload
569 prev_save_slots_num
= save_slots_num
;
570 memcpy (prev_save_slots
, save_slots
, save_slots_num
* sizeof (rtx
));
572 /* Allocate stack slots for the saved hard registers. */
573 for (i
= 0; i
< saved_regs_num
; i
++)
575 saved_reg
= all_saved_regs
[i
];
576 regno
= saved_reg
->hard_regno
;
577 for (j
= 0; j
< i
; j
++)
579 saved_reg2
= all_saved_regs
[j
];
580 if (! saved_reg2
->first_p
)
582 slot
= saved_reg2
->slot
;
583 for (k
= j
; k
>= 0; k
= next_k
)
585 saved_reg3
= all_saved_regs
[k
];
586 next_k
= saved_reg3
->next
;
587 if (saved_reg_conflicts
[saved_reg
->num
* saved_regs_num
592 && known_le (GET_MODE_SIZE (regno_save_mode
[regno
][1]),
593 GET_MODE_SIZE (regno_save_mode
594 [saved_reg2
->hard_regno
][1])))
598 (slot
, regno_save_mode
[saved_reg
->hard_regno
][1], 0);
599 regno_save_mem
[regno
][1] = saved_reg
->slot
;
600 saved_reg
->next
= saved_reg2
->next
;
601 saved_reg2
->next
= i
;
602 if (dump_file
!= NULL
)
603 fprintf (dump_file
, "%d uses slot of %d\n",
604 regno
, saved_reg2
->hard_regno
);
610 saved_reg
->first_p
= TRUE
;
611 for (best_slot_num
= -1, j
= 0; j
< prev_save_slots_num
; j
++)
613 slot
= prev_save_slots
[j
];
614 if (slot
== NULL_RTX
)
616 if (known_le (GET_MODE_SIZE (regno_save_mode
[regno
][1]),
617 GET_MODE_SIZE (GET_MODE (slot
)))
618 && best_slot_num
< 0)
620 if (GET_MODE (slot
) == regno_save_mode
[regno
][1])
623 if (best_slot_num
>= 0)
625 saved_reg
->slot
= prev_save_slots
[best_slot_num
];
629 regno_save_mode
[saved_reg
->hard_regno
][1], 0);
630 if (dump_file
!= NULL
)
632 "%d uses a slot from prev iteration\n", regno
);
633 prev_save_slots
[best_slot_num
] = NULL_RTX
;
634 if (best_slot_num
+ 1 == prev_save_slots_num
)
635 prev_save_slots_num
--;
640 = assign_stack_local_1
641 (regno_save_mode
[regno
][1],
642 GET_MODE_SIZE (regno_save_mode
[regno
][1]), 0,
644 if (dump_file
!= NULL
)
645 fprintf (dump_file
, "%d uses a new slot\n", regno
);
647 regno_save_mem
[regno
][1] = saved_reg
->slot
;
648 save_slots
[save_slots_num
++] = saved_reg
->slot
;
651 free (saved_reg_conflicts
);
652 finish_saved_hard_regs ();
656 /* We are not sharing slots.
658 Run through all the call-used hard-registers and allocate
659 space for each in the caller-save area. Try to allocate space
660 in a manner which allows multi-register saves/restores to be done. */
662 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
663 for (j
= MOVE_MAX_WORDS
; j
> 0; j
--)
667 /* If no mode exists for this size, try another. Also break out
668 if we have already saved this hard register. */
669 if (regno_save_mode
[i
][j
] == VOIDmode
|| regno_save_mem
[i
][1] != 0)
672 /* See if any register in this group has been saved. */
673 for (k
= 0; k
< j
; k
++)
674 if (regno_save_mem
[i
+ k
][1])
682 for (k
= 0; k
< j
; k
++)
683 if (! TEST_HARD_REG_BIT (hard_regs_used
, i
+ k
))
691 /* We have found an acceptable mode to store in. Since
692 hard register is always saved in the widest mode
693 available, the mode may be wider than necessary, it is
694 OK to reduce the alignment of spill space. We will
695 verify that it is equal to or greater than required
696 when we restore and save the hard register in
697 insert_restore and insert_save. */
699 = assign_stack_local_1 (regno_save_mode
[i
][j
],
700 GET_MODE_SIZE (regno_save_mode
[i
][j
]),
701 0, ASLK_REDUCE_ALIGN
);
703 /* Setup single word save area just in case... */
704 for (k
= 0; k
< j
; k
++)
705 /* This should not depend on WORDS_BIG_ENDIAN.
706 The order of words in regs is the same as in memory. */
707 regno_save_mem
[i
+ k
][1]
708 = adjust_address_nv (regno_save_mem
[i
][j
],
709 regno_save_mode
[i
+ k
][1],
714 /* Now loop again and set the alias set of any save areas we made to
715 the alias set used to represent frame objects. */
716 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
717 for (j
= MOVE_MAX_WORDS
; j
> 0; j
--)
718 if (regno_save_mem
[i
][j
] != 0)
719 set_mem_alias_set (regno_save_mem
[i
][j
], get_frame_alias_set ());
724 /* Find the places where hard regs are live across calls and save them. */
727 save_call_clobbered_regs (void)
729 class insn_chain
*chain
, *next
, *last
= NULL
;
730 machine_mode save_mode
[FIRST_PSEUDO_REGISTER
];
732 /* Computed in mark_set_regs, holds all registers set by the current
734 HARD_REG_SET this_insn_sets
;
736 CLEAR_HARD_REG_SET (hard_regs_saved
);
739 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
741 rtx_insn
*insn
= chain
->insn
;
742 enum rtx_code code
= GET_CODE (insn
);
746 gcc_assert (!chain
->is_caller_save_insn
);
748 if (NONDEBUG_INSN_P (insn
))
750 /* If some registers have been saved, see if INSN references
751 any of them. We must restore them before the insn if so. */
756 HARD_REG_SET this_insn_sets
;
758 if (code
== JUMP_INSN
)
759 /* Restore all registers if this is a JUMP_INSN. */
760 referenced_regs
= hard_regs_saved
;
763 CLEAR_HARD_REG_SET (referenced_regs
);
764 mark_referenced_regs (&PATTERN (insn
),
765 mark_reg_as_referenced
, NULL
);
766 referenced_regs
&= hard_regs_saved
;
769 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
770 if (TEST_HARD_REG_BIT (referenced_regs
, regno
))
771 regno
+= insert_restore (chain
, 1, regno
, MOVE_MAX_WORDS
,
773 /* If a saved register is set after the call, this means we no
774 longer should restore it. This can happen when parts of a
775 multi-word pseudo do not conflict with other pseudos, so
776 IRA may allocate the same hard register for both. One may
777 be live across the call, while the other is set
779 CLEAR_HARD_REG_SET (this_insn_sets
);
780 note_stores (insn
, mark_set_regs
, &this_insn_sets
);
781 hard_regs_saved
&= ~this_insn_sets
;
784 if (code
== CALL_INSN
785 && ! SIBLING_CALL_P (insn
)
786 && ! find_reg_note (insn
, REG_NORETURN
, NULL
))
789 HARD_REG_SET hard_regs_to_save
;
790 HARD_REG_SET call_def_reg_set
;
791 reg_set_iterator rsi
;
794 cheap
= find_reg_note (insn
, REG_RETURNED
, NULL
);
796 cheap
= XEXP (cheap
, 0);
798 /* Use the register life information in CHAIN to compute which
799 regs are live during the call. */
800 REG_SET_TO_HARD_REG_SET (hard_regs_to_save
,
801 &chain
->live_throughout
);
802 /* Save hard registers always in the widest mode available. */
803 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
804 if (TEST_HARD_REG_BIT (hard_regs_to_save
, regno
))
805 save_mode
[regno
] = regno_save_mode
[regno
][1];
807 save_mode
[regno
] = VOIDmode
;
809 /* Look through all live pseudos, mark their hard registers
810 and choose proper mode for saving. */
811 EXECUTE_IF_SET_IN_REG_SET
812 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
814 int r
= reg_renumber
[regno
];
818 if (r
< 0 || regno_reg_rtx
[regno
] == cheap
)
820 nregs
= hard_regno_nregs (r
, PSEUDO_REGNO_MODE (regno
));
821 mode
= HARD_REGNO_CALLER_SAVE_MODE
822 (r
, nregs
, PSEUDO_REGNO_MODE (regno
));
823 if (partial_subreg_p (save_mode
[r
], mode
))
826 SET_HARD_REG_BIT (hard_regs_to_save
, r
+ nregs
);
829 /* Record all registers set in this call insn. These don't need
830 to be saved. N.B. the call insn might set a subreg of a
831 multi-hard-reg pseudo; then the pseudo is considered live
832 during the call, but the subreg that is set isn't. */
833 CLEAR_HARD_REG_SET (this_insn_sets
);
834 note_stores (insn
, mark_set_regs
, &this_insn_sets
);
836 /* Compute which hard regs must be saved before this call. */
837 hard_regs_to_save
&= ~(fixed_reg_set
840 hard_regs_to_save
&= savable_regs
;
841 get_call_reg_set_usage (insn
, &call_def_reg_set
,
842 call_used_or_fixed_regs
);
843 hard_regs_to_save
&= call_def_reg_set
;
845 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
846 if (TEST_HARD_REG_BIT (hard_regs_to_save
, regno
))
847 regno
+= insert_save (chain
, regno
,
848 &hard_regs_to_save
, save_mode
);
850 /* Must recompute n_regs_saved. */
852 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
853 if (TEST_HARD_REG_BIT (hard_regs_saved
, regno
))
857 && HARD_REGISTER_P (cheap
)
858 && TEST_HARD_REG_BIT (call_used_or_fixed_regs
,
862 rtx pat
= PATTERN (insn
);
863 if (GET_CODE (pat
) == PARALLEL
)
864 pat
= XVECEXP (pat
, 0, 0);
865 dest
= SET_DEST (pat
);
866 /* For multiple return values dest is PARALLEL.
867 Currently we handle only single return value case. */
870 newpat
= gen_rtx_SET (cheap
, copy_rtx (dest
));
871 chain
= insert_one_insn (chain
, 0, -1, newpat
);
877 else if (DEBUG_INSN_P (insn
) && n_regs_saved
)
878 mark_referenced_regs (&PATTERN (insn
),
879 replace_reg_with_saved_mem
,
882 if (chain
->next
== 0 || chain
->next
->block
!= chain
->block
)
885 /* At the end of the basic block, we must restore any registers that
886 remain saved. If the last insn in the block is a JUMP_INSN, put
887 the restore before the insn, otherwise, put it after the insn. */
890 && DEBUG_INSN_P (insn
)
892 && last
->block
== chain
->block
)
894 rtx_insn
*ins
, *prev
;
895 basic_block bb
= BLOCK_FOR_INSN (insn
);
897 /* When adding hard reg restores after a DEBUG_INSN, move
898 all notes between last real insn and this DEBUG_INSN after
899 the DEBUG_INSN, otherwise we could get code
900 -g/-g0 differences. */
901 for (ins
= PREV_INSN (insn
); ins
!= last
->insn
; ins
= prev
)
903 prev
= PREV_INSN (ins
);
906 SET_NEXT_INSN (prev
) = NEXT_INSN (ins
);
907 SET_PREV_INSN (NEXT_INSN (ins
)) = prev
;
908 SET_PREV_INSN (ins
) = insn
;
909 SET_NEXT_INSN (ins
) = NEXT_INSN (insn
);
910 SET_NEXT_INSN (insn
) = ins
;
912 SET_PREV_INSN (NEXT_INSN (ins
)) = ins
;
913 if (BB_END (bb
) == insn
)
917 gcc_assert (DEBUG_INSN_P (ins
));
923 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
924 if (TEST_HARD_REG_BIT (hard_regs_saved
, regno
))
925 regno
+= insert_restore (chain
, JUMP_P (insn
),
926 regno
, MOVE_MAX_WORDS
, save_mode
);
931 /* Here from note_stores, or directly from save_call_clobbered_regs, when
932 an insn stores a value in a register.
933 Set the proper bit or bits in this_insn_sets. All pseudos that have
934 been assigned hard regs have had their register number changed already,
935 so we can ignore pseudos. */
937 mark_set_regs (rtx reg
, const_rtx setter ATTRIBUTE_UNUSED
, void *data
)
939 int regno
, endregno
, i
;
940 HARD_REG_SET
*this_insn_sets
= (HARD_REG_SET
*) data
;
942 if (GET_CODE (reg
) == SUBREG
)
944 rtx inner
= SUBREG_REG (reg
);
945 if (!REG_P (inner
) || REGNO (inner
) >= FIRST_PSEUDO_REGISTER
)
947 regno
= subreg_regno (reg
);
948 endregno
= regno
+ subreg_nregs (reg
);
951 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
954 endregno
= END_REGNO (reg
);
959 for (i
= regno
; i
< endregno
; i
++)
960 SET_HARD_REG_BIT (*this_insn_sets
, i
);
963 /* Here from note_stores when an insn stores a value in a register.
964 Set the proper bit or bits in the passed regset. All pseudos that have
965 been assigned hard regs have had their register number changed already,
966 so we can ignore pseudos. */
968 add_stored_regs (rtx reg
, const_rtx setter
, void *data
)
970 int regno
, endregno
, i
;
971 machine_mode mode
= GET_MODE (reg
);
974 if (GET_CODE (setter
) == CLOBBER
)
977 if (GET_CODE (reg
) == SUBREG
978 && REG_P (SUBREG_REG (reg
))
979 && REGNO (SUBREG_REG (reg
)) < FIRST_PSEUDO_REGISTER
)
981 offset
= subreg_regno_offset (REGNO (SUBREG_REG (reg
)),
982 GET_MODE (SUBREG_REG (reg
)),
985 regno
= REGNO (SUBREG_REG (reg
)) + offset
;
986 endregno
= regno
+ subreg_nregs (reg
);
990 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
993 regno
= REGNO (reg
) + offset
;
994 endregno
= end_hard_regno (mode
, regno
);
997 for (i
= regno
; i
< endregno
; i
++)
998 SET_REGNO_REG_SET ((regset
) data
, i
);
1001 /* Walk X and record all referenced registers in REFERENCED_REGS. */
1003 mark_referenced_regs (rtx
*loc
, refmarker_fn
*mark
, void *arg
)
1005 enum rtx_code code
= GET_CODE (*loc
);
1010 mark_referenced_regs (&SET_SRC (*loc
), mark
, arg
);
1011 if (code
== SET
|| code
== CLOBBER
)
1013 loc
= &SET_DEST (*loc
);
1014 code
= GET_CODE (*loc
);
1015 if ((code
== REG
&& REGNO (*loc
) < FIRST_PSEUDO_REGISTER
)
1016 || code
== PC
|| code
== CC0
1017 || (code
== SUBREG
&& REG_P (SUBREG_REG (*loc
))
1018 && REGNO (SUBREG_REG (*loc
)) < FIRST_PSEUDO_REGISTER
1019 /* If we're setting only part of a multi-word register,
1020 we shall mark it as referenced, because the words
1021 that are not being set should be restored. */
1022 && !read_modify_subreg_p (*loc
)))
1025 if (code
== MEM
|| code
== SUBREG
)
1027 loc
= &XEXP (*loc
, 0);
1028 code
= GET_CODE (*loc
);
1033 int regno
= REGNO (*loc
);
1034 int hardregno
= (regno
< FIRST_PSEUDO_REGISTER
? regno
1035 : reg_renumber
[regno
]);
1038 mark (loc
, GET_MODE (*loc
), hardregno
, arg
);
1040 /* ??? Will we ever end up with an equiv expression in a debug
1041 insn, that would have required restoring a reg, or will
1042 reload take care of it for us? */
1044 /* If this is a pseudo that did not get a hard register, scan its
1045 memory location, since it might involve the use of another
1046 register, which might be saved. */
1047 else if (reg_equiv_mem (regno
) != 0)
1048 mark_referenced_regs (&XEXP (reg_equiv_mem (regno
), 0), mark
, arg
);
1049 else if (reg_equiv_address (regno
) != 0)
1050 mark_referenced_regs (®_equiv_address (regno
), mark
, arg
);
1054 fmt
= GET_RTX_FORMAT (code
);
1055 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1058 mark_referenced_regs (&XEXP (*loc
, i
), mark
, arg
);
1059 else if (fmt
[i
] == 'E')
1060 for (j
= XVECLEN (*loc
, i
) - 1; j
>= 0; j
--)
1061 mark_referenced_regs (&XVECEXP (*loc
, i
, j
), mark
, arg
);
1065 /* Parameter function for mark_referenced_regs() that adds registers
1066 present in the insn and in equivalent mems and addresses to
1070 mark_reg_as_referenced (rtx
*loc ATTRIBUTE_UNUSED
,
1073 void *arg ATTRIBUTE_UNUSED
)
1075 add_to_hard_reg_set (&referenced_regs
, mode
, hardregno
);
1078 /* Parameter function for mark_referenced_regs() that replaces
1079 registers referenced in a debug_insn that would have been restored,
1080 should it be a non-debug_insn, with their save locations. */
1083 replace_reg_with_saved_mem (rtx
*loc
,
1088 unsigned int i
, nregs
= hard_regno_nregs (regno
, mode
);
1090 machine_mode
*save_mode
= (machine_mode
*)arg
;
1092 for (i
= 0; i
< nregs
; i
++)
1093 if (TEST_HARD_REG_BIT (hard_regs_saved
, regno
+ i
))
1096 /* If none of the registers in the range would need restoring, we're
1102 if (!TEST_HARD_REG_BIT (hard_regs_saved
, regno
+ i
))
1106 && regno_save_mem
[regno
][nregs
])
1108 mem
= copy_rtx (regno_save_mem
[regno
][nregs
]);
1110 if (nregs
== hard_regno_nregs (regno
, save_mode
[regno
]))
1111 mem
= adjust_address_nv (mem
, save_mode
[regno
], 0);
1113 if (GET_MODE (mem
) != mode
)
1115 /* This is gen_lowpart_if_possible(), but without validating
1116 the newly-formed address. */
1117 poly_int64 offset
= byte_lowpart_offset (mode
, GET_MODE (mem
));
1118 mem
= adjust_address_nv (mem
, mode
, offset
);
1123 mem
= gen_rtx_CONCATN (mode
, rtvec_alloc (nregs
));
1124 for (i
= 0; i
< nregs
; i
++)
1125 if (TEST_HARD_REG_BIT (hard_regs_saved
, regno
+ i
))
1127 gcc_assert (regno_save_mem
[regno
+ i
][1]);
1128 XVECEXP (mem
, 0, i
) = copy_rtx (regno_save_mem
[regno
+ i
][1]);
1132 machine_mode smode
= save_mode
[regno
];
1133 gcc_assert (smode
!= VOIDmode
);
1134 if (hard_regno_nregs (regno
, smode
) > 1)
1135 smode
= mode_for_size (exact_div (GET_MODE_BITSIZE (mode
),
1137 GET_MODE_CLASS (mode
), 0).require ();
1138 XVECEXP (mem
, 0, i
) = gen_rtx_REG (smode
, regno
+ i
);
1142 gcc_assert (GET_MODE (mem
) == mode
);
1147 /* Insert a sequence of insns to restore. Place these insns in front of
1148 CHAIN if BEFORE_P is nonzero, behind the insn otherwise. MAXRESTORE is
1149 the maximum number of registers which should be restored during this call.
1150 It should never be less than 1 since we only work with entire registers.
1152 Note that we have verified in init_caller_save that we can do this
1153 with a simple SET, so use it. Set INSN_CODE to what we save there
1154 since the address might not be valid so the insn might not be recognized.
1155 These insns will be reloaded and have register elimination done by
1156 find_reload, so we need not worry about that here.
1158 Return the extra number of registers saved. */
1161 insert_restore (class insn_chain
*chain
, int before_p
, int regno
,
1162 int maxrestore
, machine_mode
*save_mode
)
1167 unsigned int numregs
= 0;
1168 class insn_chain
*new_chain
;
1171 /* A common failure mode if register status is not correct in the
1172 RTL is for this routine to be called with a REGNO we didn't
1173 expect to save. That will cause us to write an insn with a (nil)
1174 SET_DEST or SET_SRC. Instead of doing so and causing a crash
1175 later, check for this common case here instead. This will remove
1176 one step in debugging such problems. */
1177 gcc_assert (regno_save_mem
[regno
][1]);
1179 /* Get the pattern to emit and update our status.
1181 See if we can restore `maxrestore' registers at once. Work
1182 backwards to the single register case. */
1183 for (i
= maxrestore
; i
> 0; i
--)
1188 if (regno_save_mem
[regno
][i
] == 0)
1191 for (j
= 0; j
< i
; j
++)
1192 if (! TEST_HARD_REG_BIT (hard_regs_saved
, regno
+ j
))
1197 /* Must do this one restore at a time. */
1205 mem
= regno_save_mem
[regno
][numregs
];
1206 if (save_mode
[regno
] != VOIDmode
1207 && save_mode
[regno
] != GET_MODE (mem
)
1208 && numregs
== hard_regno_nregs (regno
, save_mode
[regno
])
1209 /* Check that insn to restore REGNO in save_mode[regno] is
1211 && reg_save_code (regno
, save_mode
[regno
]) >= 0)
1212 mem
= adjust_address_nv (mem
, save_mode
[regno
], 0);
1214 mem
= copy_rtx (mem
);
1216 /* Verify that the alignment of spill space is equal to or greater
1218 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT
,
1219 GET_MODE_ALIGNMENT (GET_MODE (mem
))) <= MEM_ALIGN (mem
));
1221 pat
= gen_rtx_SET (gen_rtx_REG (GET_MODE (mem
), regno
), mem
);
1222 code
= reg_restore_code (regno
, GET_MODE (mem
));
1223 new_chain
= insert_one_insn (chain
, before_p
, code
, pat
);
1225 /* Clear status for all registers we restored. */
1226 for (k
= 0; k
< i
; k
++)
1228 CLEAR_HARD_REG_BIT (hard_regs_saved
, regno
+ k
);
1229 SET_REGNO_REG_SET (&new_chain
->dead_or_set
, regno
+ k
);
1233 /* Tell our callers how many extra registers we saved/restored. */
1237 /* Like insert_restore above, but save registers instead. */
1240 insert_save (class insn_chain
*chain
, int regno
,
1241 HARD_REG_SET
*to_save
, machine_mode
*save_mode
)
1247 unsigned int numregs
= 0;
1248 class insn_chain
*new_chain
;
1251 /* A common failure mode if register status is not correct in the
1252 RTL is for this routine to be called with a REGNO we didn't
1253 expect to save. That will cause us to write an insn with a (nil)
1254 SET_DEST or SET_SRC. Instead of doing so and causing a crash
1255 later, check for this common case here. This will remove one
1256 step in debugging such problems. */
1257 gcc_assert (regno_save_mem
[regno
][1]);
1259 /* Get the pattern to emit and update our status.
1261 See if we can save several registers with a single instruction.
1262 Work backwards to the single register case. */
1263 for (i
= MOVE_MAX_WORDS
; i
> 0; i
--)
1267 if (regno_save_mem
[regno
][i
] == 0)
1270 for (j
= 0; j
< i
; j
++)
1271 if (! TEST_HARD_REG_BIT (*to_save
, regno
+ j
))
1276 /* Must do this one save at a time. */
1284 mem
= regno_save_mem
[regno
][numregs
];
1285 if (save_mode
[regno
] != VOIDmode
1286 && save_mode
[regno
] != GET_MODE (mem
)
1287 && numregs
== hard_regno_nregs (regno
, save_mode
[regno
])
1288 /* Check that insn to save REGNO in save_mode[regno] is
1290 && reg_save_code (regno
, save_mode
[regno
]) >= 0)
1291 mem
= adjust_address_nv (mem
, save_mode
[regno
], 0);
1293 mem
= copy_rtx (mem
);
1295 /* Verify that the alignment of spill space is equal to or greater
1297 gcc_assert (MIN (MAX_SUPPORTED_STACK_ALIGNMENT
,
1298 GET_MODE_ALIGNMENT (GET_MODE (mem
))) <= MEM_ALIGN (mem
));
1300 pat
= gen_rtx_SET (mem
, gen_rtx_REG (GET_MODE (mem
), regno
));
1301 code
= reg_save_code (regno
, GET_MODE (mem
));
1302 new_chain
= insert_one_insn (chain
, 1, code
, pat
);
1304 /* Set hard_regs_saved and dead_or_set for all the registers we saved. */
1305 for (k
= 0; k
< numregs
; k
++)
1307 SET_HARD_REG_BIT (hard_regs_saved
, regno
+ k
);
1308 SET_REGNO_REG_SET (&new_chain
->dead_or_set
, regno
+ k
);
1312 /* Tell our callers how many extra registers we saved/restored. */
1316 /* A note_uses callback used by insert_one_insn. Add the hard-register
1317 equivalent of each REG to regset DATA. */
1320 add_used_regs (rtx
*loc
, void *data
)
1322 subrtx_iterator::array_type array
;
1323 FOR_EACH_SUBRTX (iter
, array
, *loc
, NONCONST
)
1325 const_rtx x
= *iter
;
1328 unsigned int regno
= REGNO (x
);
1329 if (HARD_REGISTER_NUM_P (regno
))
1330 bitmap_set_range ((regset
) data
, regno
, REG_NREGS (x
));
1332 gcc_checking_assert (reg_renumber
[regno
] < 0);
1337 /* Emit a new caller-save insn and set the code. */
1338 static class insn_chain
*
1339 insert_one_insn (class insn_chain
*chain
, int before_p
, int code
, rtx pat
)
1341 rtx_insn
*insn
= chain
->insn
;
1342 class insn_chain
*new_chain
;
1344 /* If INSN references CC0, put our insns in front of the insn that sets
1345 CC0. This is always safe, since the only way we could be passed an
1346 insn that references CC0 is for a restore, and doing a restore earlier
1347 isn't a problem. We do, however, assume here that CALL_INSNs don't
1348 reference CC0. Guard against non-INSN's like CODE_LABEL. */
1350 if (HAVE_cc0
&& (NONJUMP_INSN_P (insn
) || JUMP_P (insn
))
1352 && reg_referenced_p (cc0_rtx
, PATTERN (insn
)))
1353 chain
= chain
->prev
, insn
= chain
->insn
;
1355 new_chain
= new_insn_chain ();
1360 new_chain
->prev
= chain
->prev
;
1361 if (new_chain
->prev
!= 0)
1362 new_chain
->prev
->next
= new_chain
;
1364 reload_insn_chain
= new_chain
;
1366 chain
->prev
= new_chain
;
1367 new_chain
->next
= chain
;
1368 new_chain
->insn
= emit_insn_before (pat
, insn
);
1369 /* ??? It would be nice if we could exclude the already / still saved
1370 registers from the live sets. */
1371 COPY_REG_SET (&new_chain
->live_throughout
, &chain
->live_throughout
);
1372 note_uses (&PATTERN (chain
->insn
), add_used_regs
,
1373 &new_chain
->live_throughout
);
1374 /* If CHAIN->INSN is a call, then the registers which contain
1375 the arguments to the function are live in the new insn. */
1376 if (CALL_P (chain
->insn
))
1377 for (link
= CALL_INSN_FUNCTION_USAGE (chain
->insn
);
1379 link
= XEXP (link
, 1))
1380 note_uses (&XEXP (link
, 0), add_used_regs
,
1381 &new_chain
->live_throughout
);
1383 CLEAR_REG_SET (&new_chain
->dead_or_set
);
1384 if (chain
->insn
== BB_HEAD (BASIC_BLOCK_FOR_FN (cfun
, chain
->block
)))
1385 BB_HEAD (BASIC_BLOCK_FOR_FN (cfun
, chain
->block
)) = new_chain
->insn
;
1389 new_chain
->next
= chain
->next
;
1390 if (new_chain
->next
!= 0)
1391 new_chain
->next
->prev
= new_chain
;
1392 chain
->next
= new_chain
;
1393 new_chain
->prev
= chain
;
1394 new_chain
->insn
= emit_insn_after (pat
, insn
);
1395 /* ??? It would be nice if we could exclude the already / still saved
1396 registers from the live sets, and observe REG_UNUSED notes. */
1397 COPY_REG_SET (&new_chain
->live_throughout
, &chain
->live_throughout
);
1398 /* Registers that are set in CHAIN->INSN live in the new insn.
1399 (Unless there is a REG_UNUSED note for them, but we don't
1400 look for them here.) */
1401 note_stores (chain
->insn
, add_stored_regs
, &new_chain
->live_throughout
);
1402 CLEAR_REG_SET (&new_chain
->dead_or_set
);
1403 if (chain
->insn
== BB_END (BASIC_BLOCK_FOR_FN (cfun
, chain
->block
)))
1404 BB_END (BASIC_BLOCK_FOR_FN (cfun
, chain
->block
)) = new_chain
->insn
;
1406 new_chain
->block
= chain
->block
;
1407 new_chain
->is_caller_save_insn
= 1;
1409 INSN_CODE (new_chain
->insn
) = code
;
1412 #include "gt-caller-save.h"