1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
84 #include "stor-layout.h"
88 #include "hard-reg-set.h"
89 #include "basic-block.h"
90 #include "insn-config.h"
92 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
94 #include "insn-attr.h"
96 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
102 #include "tree-pass.h"
104 #include "valtrack.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts
;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges
;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras
;
120 /* Number of instructions combined in this function. */
122 static int combine_successes
;
124 /* Totals over entire compilation. */
126 static int total_attempts
, total_merges
, total_extras
, total_successes
;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs
;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs
;
145 typedef struct reg_stat_struct
{
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick
;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
215 char last_set_sign_bit_copies
;
216 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid
;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies
;
238 unsigned HOST_WIDE_INT nonzero_bits
;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label
;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
255 static vec
<reg_stat_type
> reg_stat
;
257 /* Record the luid of the last insn that invalidated memory
258 (anything that writes memory, and subroutine calls, but not pushes). */
260 static int mem_last_set
;
262 /* Record the luid of the last CALL_INSN
263 so we can tell whether a potential combination crosses any calls. */
265 static int last_call_luid
;
267 /* When `subst' is called, this is the insn that is being modified
268 (by combining in a previous insn). The PATTERN of this insn
269 is still the old pattern partially modified and it should not be
270 looked at, but this may be used to examine the successors of the insn
271 to judge whether a simplification is valid. */
273 static rtx subst_insn
;
275 /* This is the lowest LUID that `subst' is currently dealing with.
276 get_last_value will not return a value if the register was set at or
277 after this LUID. If not for this mechanism, we could get confused if
278 I2 or I1 in try_combine were an insn that used the old value of a register
279 to obtain a new value. In that case, we might erroneously get the
280 new value of the register when we wanted the old one. */
282 static int subst_low_luid
;
284 /* This contains any hard registers that are used in newpat; reg_dead_at_p
285 must consider all these registers to be always live. */
287 static HARD_REG_SET newpat_used_regs
;
289 /* This is an insn to which a LOG_LINKS entry has been added. If this
290 insn is the earlier than I2 or I3, combine should rescan starting at
293 static rtx added_links_insn
;
295 /* Basic block in which we are performing combines. */
296 static basic_block this_basic_block
;
297 static bool optimize_this_for_speed_p
;
300 /* Length of the currently allocated uid_insn_cost array. */
302 static int max_uid_known
;
304 /* The following array records the insn_rtx_cost for every insn
305 in the instruction stream. */
307 static int *uid_insn_cost
;
309 /* The following array records the LOG_LINKS for every insn in the
310 instruction stream as struct insn_link pointers. */
314 struct insn_link
*next
;
317 static struct insn_link
**uid_log_links
;
319 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
320 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
322 #define FOR_EACH_LOG_LINK(L, INSN) \
323 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
325 /* Links for LOG_LINKS are allocated from this obstack. */
327 static struct obstack insn_link_obstack
;
329 /* Allocate a link. */
331 static inline struct insn_link
*
332 alloc_insn_link (rtx insn
, struct insn_link
*next
)
335 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
336 sizeof (struct insn_link
));
342 /* Incremented for each basic block. */
344 static int label_tick
;
346 /* Reset to label_tick for each extended basic block in scanning order. */
348 static int label_tick_ebb_start
;
350 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
351 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
353 static enum machine_mode nonzero_bits_mode
;
355 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
356 be safely used. It is zero while computing them and after combine has
357 completed. This former test prevents propagating values based on
358 previously set values, which can be incorrect if a variable is modified
361 static int nonzero_sign_valid
;
364 /* Record one modification to rtl structure
365 to be undone by storing old_contents into *where. */
367 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
373 union { rtx r
; int i
; enum machine_mode m
; struct insn_link
*l
; } old_contents
;
374 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
377 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
378 num_undo says how many are currently recorded.
380 other_insn is nonzero if we have modified some other insn in the process
381 of working on subst_insn. It must be verified too. */
390 static struct undobuf undobuf
;
392 /* Number of times the pseudo being substituted for
393 was found and replaced. */
395 static int n_occurrences
;
397 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
399 unsigned HOST_WIDE_INT
,
400 unsigned HOST_WIDE_INT
*);
401 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
403 unsigned int, unsigned int *);
404 static void do_SUBST (rtx
*, rtx
);
405 static void do_SUBST_INT (int *, int);
406 static void init_reg_last (void);
407 static void setup_incoming_promotions (rtx
);
408 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
409 static int cant_combine_insn_p (rtx
);
410 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
411 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
412 static int contains_muldiv (rtx
);
413 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *, rtx
);
414 static void undo_all (void);
415 static void undo_commit (void);
416 static rtx
*find_split_point (rtx
*, rtx
, bool);
417 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
418 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
419 static rtx
simplify_if_then_else (rtx
);
420 static rtx
simplify_set (rtx
);
421 static rtx
simplify_logical (rtx
);
422 static rtx
expand_compound_operation (rtx
);
423 static const_rtx
expand_field_assignment (const_rtx
);
424 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
425 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
426 static rtx
extract_left_shift (rtx
, int);
427 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
428 unsigned HOST_WIDE_INT
*);
429 static rtx
canon_reg_for_combine (rtx
, rtx
);
430 static rtx
force_to_mode (rtx
, enum machine_mode
,
431 unsigned HOST_WIDE_INT
, int);
432 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
433 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
434 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
435 static rtx
make_field_assignment (rtx
);
436 static rtx
apply_distributive_law (rtx
);
437 static rtx
distribute_and_simplify_rtx (rtx
, int);
438 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
439 unsigned HOST_WIDE_INT
);
440 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
441 unsigned HOST_WIDE_INT
);
442 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
443 HOST_WIDE_INT
, enum machine_mode
, int *);
444 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
445 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
447 static int recog_for_combine (rtx
*, rtx
, rtx
*);
448 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
449 static enum rtx_code
simplify_compare_const (enum rtx_code
, rtx
, rtx
*);
450 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
451 static void update_table_tick (rtx
);
452 static void record_value_for_reg (rtx
, rtx
, rtx
);
453 static void check_promoted_subreg (rtx
, rtx
);
454 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
455 static void record_dead_and_set_regs (rtx
);
456 static int get_last_value_validate (rtx
*, rtx
, int, int);
457 static rtx
get_last_value (const_rtx
);
458 static int use_crosses_set_p (const_rtx
, int);
459 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
460 static int reg_dead_at_p (rtx
, rtx
);
461 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
462 static int reg_bitfield_target_p (rtx
, rtx
);
463 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
464 static void distribute_links (struct insn_link
*);
465 static void mark_used_regs_combine (rtx
);
466 static void record_promoted_value (rtx
, rtx
);
467 static int unmentioned_reg_p_1 (rtx
*, void *);
468 static bool unmentioned_reg_p (rtx
, rtx
);
469 static int record_truncated_value (rtx
*, void *);
470 static void record_truncated_values (rtx
*, void *);
471 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
472 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
475 /* It is not safe to use ordinary gen_lowpart in combine.
476 See comments in gen_lowpart_for_combine. */
477 #undef RTL_HOOKS_GEN_LOWPART
478 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
480 /* Our implementation of gen_lowpart never emits a new pseudo. */
481 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
482 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
484 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
485 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
487 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
488 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
490 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
491 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
493 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
496 /* Convenience wrapper for the canonicalize_comparison target hook.
497 Target hooks cannot use enum rtx_code. */
499 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
500 bool op0_preserve_value
)
502 int code_int
= (int)*code
;
503 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
504 *code
= (enum rtx_code
)code_int
;
507 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
508 PATTERN can not be split. Otherwise, it returns an insn sequence.
509 This is a wrapper around split_insns which ensures that the
510 reg_stat vector is made larger if the splitter creates a new
514 combine_split_insns (rtx pattern
, rtx insn
)
519 ret
= split_insns (pattern
, insn
);
520 nregs
= max_reg_num ();
521 if (nregs
> reg_stat
.length ())
522 reg_stat
.safe_grow_cleared (nregs
);
526 /* This is used by find_single_use to locate an rtx in LOC that
527 contains exactly one use of DEST, which is typically either a REG
528 or CC0. It returns a pointer to the innermost rtx expression
529 containing DEST. Appearances of DEST that are being used to
530 totally replace it are not counted. */
533 find_single_use_1 (rtx dest
, rtx
*loc
)
536 enum rtx_code code
= GET_CODE (x
);
552 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
553 of a REG that occupies all of the REG, the insn uses DEST if
554 it is mentioned in the destination or the source. Otherwise, we
555 need just check the source. */
556 if (GET_CODE (SET_DEST (x
)) != CC0
557 && GET_CODE (SET_DEST (x
)) != PC
558 && !REG_P (SET_DEST (x
))
559 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
560 && REG_P (SUBREG_REG (SET_DEST (x
)))
561 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
562 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
563 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
564 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
567 return find_single_use_1 (dest
, &SET_SRC (x
));
571 return find_single_use_1 (dest
, &XEXP (x
, 0));
577 /* If it wasn't one of the common cases above, check each expression and
578 vector of this code. Look for a unique usage of DEST. */
580 fmt
= GET_RTX_FORMAT (code
);
581 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
585 if (dest
== XEXP (x
, i
)
586 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
587 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
590 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
593 result
= this_result
;
594 else if (this_result
)
595 /* Duplicate usage. */
598 else if (fmt
[i
] == 'E')
602 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
604 if (XVECEXP (x
, i
, j
) == dest
606 && REG_P (XVECEXP (x
, i
, j
))
607 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
610 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
613 result
= this_result
;
614 else if (this_result
)
624 /* See if DEST, produced in INSN, is used only a single time in the
625 sequel. If so, return a pointer to the innermost rtx expression in which
628 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
630 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
631 care about REG_DEAD notes or LOG_LINKS.
633 Otherwise, we find the single use by finding an insn that has a
634 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
635 only referenced once in that insn, we know that it must be the first
636 and last insn referencing DEST. */
639 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
644 struct insn_link
*link
;
649 next
= NEXT_INSN (insn
);
651 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
654 result
= find_single_use_1 (dest
, &PATTERN (next
));
664 bb
= BLOCK_FOR_INSN (insn
);
665 for (next
= NEXT_INSN (insn
);
666 next
&& BLOCK_FOR_INSN (next
) == bb
;
667 next
= NEXT_INSN (next
))
668 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
670 FOR_EACH_LOG_LINK (link
, next
)
671 if (link
->insn
== insn
)
676 result
= find_single_use_1 (dest
, &PATTERN (next
));
686 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
687 insn. The substitution can be undone by undo_all. If INTO is already
688 set to NEWVAL, do not record this change. Because computing NEWVAL might
689 also call SUBST, we have to compute it before we put anything into
693 do_SUBST (rtx
*into
, rtx newval
)
698 if (oldval
== newval
)
701 /* We'd like to catch as many invalid transformations here as
702 possible. Unfortunately, there are way too many mode changes
703 that are perfectly valid, so we'd waste too much effort for
704 little gain doing the checks here. Focus on catching invalid
705 transformations involving integer constants. */
706 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
707 && CONST_INT_P (newval
))
709 /* Sanity check that we're replacing oldval with a CONST_INT
710 that is a valid sign-extension for the original mode. */
711 gcc_assert (INTVAL (newval
)
712 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
714 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
715 CONST_INT is not valid, because after the replacement, the
716 original mode would be gone. Unfortunately, we can't tell
717 when do_SUBST is called to replace the operand thereof, so we
718 perform this test on oldval instead, checking whether an
719 invalid replacement took place before we got here. */
720 gcc_assert (!(GET_CODE (oldval
) == SUBREG
721 && CONST_INT_P (SUBREG_REG (oldval
))));
722 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
723 && CONST_INT_P (XEXP (oldval
, 0))));
727 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
729 buf
= XNEW (struct undo
);
731 buf
->kind
= UNDO_RTX
;
733 buf
->old_contents
.r
= oldval
;
736 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
739 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
741 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
742 for the value of a HOST_WIDE_INT value (including CONST_INT) is
746 do_SUBST_INT (int *into
, int newval
)
751 if (oldval
== newval
)
755 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
757 buf
= XNEW (struct undo
);
759 buf
->kind
= UNDO_INT
;
761 buf
->old_contents
.i
= oldval
;
764 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
767 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
769 /* Similar to SUBST, but just substitute the mode. This is used when
770 changing the mode of a pseudo-register, so that any other
771 references to the entry in the regno_reg_rtx array will change as
775 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
778 enum machine_mode oldval
= GET_MODE (*into
);
780 if (oldval
== newval
)
784 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
786 buf
= XNEW (struct undo
);
788 buf
->kind
= UNDO_MODE
;
790 buf
->old_contents
.m
= oldval
;
791 adjust_reg_mode (*into
, newval
);
793 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
796 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
799 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
802 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
805 struct insn_link
* oldval
= *into
;
807 if (oldval
== newval
)
811 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
813 buf
= XNEW (struct undo
);
815 buf
->kind
= UNDO_LINKS
;
817 buf
->old_contents
.l
= oldval
;
820 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
823 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
826 /* Subroutine of try_combine. Determine whether the replacement patterns
827 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
828 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
829 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
830 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
831 of all the instructions can be estimated and the replacements are more
832 expensive than the original sequence. */
835 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
836 rtx newi2pat
, rtx newotherpat
)
838 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
839 int new_i2_cost
, new_i3_cost
;
840 int old_cost
, new_cost
;
842 /* Lookup the original insn_rtx_costs. */
843 i2_cost
= INSN_COST (i2
);
844 i3_cost
= INSN_COST (i3
);
848 i1_cost
= INSN_COST (i1
);
851 i0_cost
= INSN_COST (i0
);
852 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
853 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
857 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
858 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
864 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
865 i1_cost
= i0_cost
= 0;
868 /* Calculate the replacement insn_rtx_costs. */
869 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
872 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
873 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
874 ? new_i2_cost
+ new_i3_cost
: 0;
878 new_cost
= new_i3_cost
;
882 if (undobuf
.other_insn
)
884 int old_other_cost
, new_other_cost
;
886 old_other_cost
= INSN_COST (undobuf
.other_insn
);
887 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
888 if (old_other_cost
> 0 && new_other_cost
> 0)
890 old_cost
+= old_other_cost
;
891 new_cost
+= new_other_cost
;
897 /* Disallow this combination if both new_cost and old_cost are greater than
898 zero, and new_cost is greater than old cost. */
899 if (old_cost
> 0 && new_cost
> old_cost
)
906 "rejecting combination of insns %d, %d, %d and %d\n",
907 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
909 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
910 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
915 "rejecting combination of insns %d, %d and %d\n",
916 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
917 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
918 i1_cost
, i2_cost
, i3_cost
, old_cost
);
923 "rejecting combination of insns %d and %d\n",
924 INSN_UID (i2
), INSN_UID (i3
));
925 fprintf (dump_file
, "original costs %d + %d = %d\n",
926 i2_cost
, i3_cost
, old_cost
);
931 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
932 new_i2_cost
, new_i3_cost
, new_cost
);
935 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
941 /* Update the uid_insn_cost array with the replacement costs. */
942 INSN_COST (i2
) = new_i2_cost
;
943 INSN_COST (i3
) = new_i3_cost
;
955 /* Delete any insns that copy a register to itself. */
958 delete_noop_moves (void)
965 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
967 next
= NEXT_INSN (insn
);
968 if (INSN_P (insn
) && noop_move_p (insn
))
971 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
973 delete_insn_and_edges (insn
);
980 /* Fill in log links field for all insns. */
983 create_log_links (void)
987 df_ref
*def_vec
, *use_vec
;
989 next_use
= XCNEWVEC (rtx
, max_reg_num ());
991 /* Pass through each block from the end, recording the uses of each
992 register and establishing log links when def is encountered.
993 Note that we do not clear next_use array in order to save time,
994 so we have to test whether the use is in the same basic block as def.
996 There are a few cases below when we do not consider the definition or
997 usage -- these are taken from original flow.c did. Don't ask me why it is
998 done this way; I don't know and if it works, I don't want to know. */
1002 FOR_BB_INSNS_REVERSE (bb
, insn
)
1004 if (!NONDEBUG_INSN_P (insn
))
1007 /* Log links are created only once. */
1008 gcc_assert (!LOG_LINKS (insn
));
1010 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
1012 df_ref def
= *def_vec
;
1013 int regno
= DF_REF_REGNO (def
);
1016 if (!next_use
[regno
])
1019 /* Do not consider if it is pre/post modification in MEM. */
1020 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1023 /* Do not make the log link for frame pointer. */
1024 if ((regno
== FRAME_POINTER_REGNUM
1025 && (! reload_completed
|| frame_pointer_needed
))
1026 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1027 || (regno
== HARD_FRAME_POINTER_REGNUM
1028 && (! reload_completed
|| frame_pointer_needed
))
1030 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1031 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1036 use_insn
= next_use
[regno
];
1037 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1041 We don't build a LOG_LINK for hard registers contained
1042 in ASM_OPERANDs. If these registers get replaced,
1043 we might wind up changing the semantics of the insn,
1044 even if reload can make what appear to be valid
1045 assignments later. */
1046 if (regno
>= FIRST_PSEUDO_REGISTER
1047 || asm_noperands (PATTERN (use_insn
)) < 0)
1049 /* Don't add duplicate links between instructions. */
1050 struct insn_link
*links
;
1051 FOR_EACH_LOG_LINK (links
, use_insn
)
1052 if (insn
== links
->insn
)
1056 LOG_LINKS (use_insn
)
1057 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1060 next_use
[regno
] = NULL_RTX
;
1063 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1065 df_ref use
= *use_vec
;
1066 int regno
= DF_REF_REGNO (use
);
1068 /* Do not consider the usage of the stack pointer
1069 by function call. */
1070 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1073 next_use
[regno
] = insn
;
1081 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1082 true if we found a LOG_LINK that proves that A feeds B. This only works
1083 if there are no instructions between A and B which could have a link
1084 depending on A, since in that case we would not record a link for B.
1085 We also check the implicit dependency created by a cc0 setter/user
1089 insn_a_feeds_b (rtx a
, rtx b
)
1091 struct insn_link
*links
;
1092 FOR_EACH_LOG_LINK (links
, b
)
1093 if (links
->insn
== a
)
1102 /* Main entry point for combiner. F is the first insn of the function.
1103 NREGS is the first unused pseudo-reg number.
1105 Return nonzero if the combiner has turned an indirect jump
1106 instruction into a direct jump. */
1108 combine_instructions (rtx f
, unsigned int nregs
)
1114 struct insn_link
*links
, *nextlinks
;
1116 basic_block last_bb
;
1118 int new_direct_jump_p
= 0;
1120 for (first
= f
; first
&& !INSN_P (first
); )
1121 first
= NEXT_INSN (first
);
1125 combine_attempts
= 0;
1128 combine_successes
= 0;
1130 rtl_hooks
= combine_rtl_hooks
;
1132 reg_stat
.safe_grow_cleared (nregs
);
1134 init_recog_no_volatile ();
1136 /* Allocate array for insn info. */
1137 max_uid_known
= get_max_uid ();
1138 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1139 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1140 gcc_obstack_init (&insn_link_obstack
);
1142 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1144 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1145 problems when, for example, we have j <<= 1 in a loop. */
1147 nonzero_sign_valid
= 0;
1148 label_tick
= label_tick_ebb_start
= 1;
1150 /* Scan all SETs and see if we can deduce anything about what
1151 bits are known to be zero for some registers and how many copies
1152 of the sign bit are known to exist for those registers.
1154 Also set any known values so that we can use it while searching
1155 for what bits are known to be set. */
1157 setup_incoming_promotions (first
);
1158 /* Allow the entry block and the first block to fall into the same EBB.
1159 Conceptually the incoming promotions are assigned to the entry block. */
1160 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1162 create_log_links ();
1163 FOR_EACH_BB (this_basic_block
)
1165 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1170 if (!single_pred_p (this_basic_block
)
1171 || single_pred (this_basic_block
) != last_bb
)
1172 label_tick_ebb_start
= label_tick
;
1173 last_bb
= this_basic_block
;
1175 FOR_BB_INSNS (this_basic_block
, insn
)
1176 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1182 subst_low_luid
= DF_INSN_LUID (insn
);
1185 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1187 record_dead_and_set_regs (insn
);
1190 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1191 if (REG_NOTE_KIND (links
) == REG_INC
)
1192 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1196 /* Record the current insn_rtx_cost of this instruction. */
1197 if (NONJUMP_INSN_P (insn
))
1198 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1199 optimize_this_for_speed_p
);
1201 fprintf (dump_file
, "insn_cost %d: %d\n",
1202 INSN_UID (insn
), INSN_COST (insn
));
1206 nonzero_sign_valid
= 1;
1208 /* Now scan all the insns in forward order. */
1209 label_tick
= label_tick_ebb_start
= 1;
1211 setup_incoming_promotions (first
);
1212 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1214 FOR_EACH_BB (this_basic_block
)
1216 rtx last_combined_insn
= NULL_RTX
;
1217 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1222 if (!single_pred_p (this_basic_block
)
1223 || single_pred (this_basic_block
) != last_bb
)
1224 label_tick_ebb_start
= label_tick
;
1225 last_bb
= this_basic_block
;
1227 rtl_profile_for_bb (this_basic_block
);
1228 for (insn
= BB_HEAD (this_basic_block
);
1229 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1230 insn
= next
? next
: NEXT_INSN (insn
))
1233 if (NONDEBUG_INSN_P (insn
))
1235 while (last_combined_insn
1236 && INSN_DELETED_P (last_combined_insn
))
1237 last_combined_insn
= PREV_INSN (last_combined_insn
);
1238 if (last_combined_insn
== NULL_RTX
1239 || BARRIER_P (last_combined_insn
)
1240 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1241 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1242 last_combined_insn
= insn
;
1244 /* See if we know about function return values before this
1245 insn based upon SUBREG flags. */
1246 check_promoted_subreg (insn
, PATTERN (insn
));
1248 /* See if we can find hardregs and subreg of pseudos in
1249 narrower modes. This could help turning TRUNCATEs
1251 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1253 /* Try this insn with each insn it links back to. */
1255 FOR_EACH_LOG_LINK (links
, insn
)
1256 if ((next
= try_combine (insn
, links
->insn
, NULL_RTX
,
1257 NULL_RTX
, &new_direct_jump_p
,
1258 last_combined_insn
)) != 0)
1261 /* Try each sequence of three linked insns ending with this one. */
1263 FOR_EACH_LOG_LINK (links
, insn
)
1265 rtx link
= links
->insn
;
1267 /* If the linked insn has been replaced by a note, then there
1268 is no point in pursuing this chain any further. */
1272 FOR_EACH_LOG_LINK (nextlinks
, link
)
1273 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1274 NULL_RTX
, &new_direct_jump_p
,
1275 last_combined_insn
)) != 0)
1280 /* Try to combine a jump insn that uses CC0
1281 with a preceding insn that sets CC0, and maybe with its
1282 logical predecessor as well.
1283 This is how we make decrement-and-branch insns.
1284 We need this special code because data flow connections
1285 via CC0 do not get entered in LOG_LINKS. */
1288 && (prev
= prev_nonnote_insn (insn
)) != 0
1289 && NONJUMP_INSN_P (prev
)
1290 && sets_cc0_p (PATTERN (prev
)))
1292 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1294 last_combined_insn
)) != 0)
1297 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1298 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1299 NULL_RTX
, &new_direct_jump_p
,
1300 last_combined_insn
)) != 0)
1304 /* Do the same for an insn that explicitly references CC0. */
1305 if (NONJUMP_INSN_P (insn
)
1306 && (prev
= prev_nonnote_insn (insn
)) != 0
1307 && NONJUMP_INSN_P (prev
)
1308 && sets_cc0_p (PATTERN (prev
))
1309 && GET_CODE (PATTERN (insn
)) == SET
1310 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1312 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1314 last_combined_insn
)) != 0)
1317 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1318 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1319 NULL_RTX
, &new_direct_jump_p
,
1320 last_combined_insn
)) != 0)
1324 /* Finally, see if any of the insns that this insn links to
1325 explicitly references CC0. If so, try this insn, that insn,
1326 and its predecessor if it sets CC0. */
1327 FOR_EACH_LOG_LINK (links
, insn
)
1328 if (NONJUMP_INSN_P (links
->insn
)
1329 && GET_CODE (PATTERN (links
->insn
)) == SET
1330 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1331 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1332 && NONJUMP_INSN_P (prev
)
1333 && sets_cc0_p (PATTERN (prev
))
1334 && (next
= try_combine (insn
, links
->insn
,
1335 prev
, NULL_RTX
, &new_direct_jump_p
,
1336 last_combined_insn
)) != 0)
1340 /* Try combining an insn with two different insns whose results it
1342 FOR_EACH_LOG_LINK (links
, insn
)
1343 for (nextlinks
= links
->next
; nextlinks
;
1344 nextlinks
= nextlinks
->next
)
1345 if ((next
= try_combine (insn
, links
->insn
,
1346 nextlinks
->insn
, NULL_RTX
,
1348 last_combined_insn
)) != 0)
1351 /* Try four-instruction combinations. */
1352 FOR_EACH_LOG_LINK (links
, insn
)
1354 struct insn_link
*next1
;
1355 rtx link
= links
->insn
;
1357 /* If the linked insn has been replaced by a note, then there
1358 is no point in pursuing this chain any further. */
1362 FOR_EACH_LOG_LINK (next1
, link
)
1364 rtx link1
= next1
->insn
;
1367 /* I0 -> I1 -> I2 -> I3. */
1368 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1369 if ((next
= try_combine (insn
, link
, link1
,
1372 last_combined_insn
)) != 0)
1374 /* I0, I1 -> I2, I2 -> I3. */
1375 for (nextlinks
= next1
->next
; nextlinks
;
1376 nextlinks
= nextlinks
->next
)
1377 if ((next
= try_combine (insn
, link
, link1
,
1380 last_combined_insn
)) != 0)
1384 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1386 rtx link1
= next1
->insn
;
1389 /* I0 -> I2; I1, I2 -> I3. */
1390 FOR_EACH_LOG_LINK (nextlinks
, link
)
1391 if ((next
= try_combine (insn
, link
, link1
,
1394 last_combined_insn
)) != 0)
1396 /* I0 -> I1; I1, I2 -> I3. */
1397 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1398 if ((next
= try_combine (insn
, link
, link1
,
1401 last_combined_insn
)) != 0)
1406 /* Try this insn with each REG_EQUAL note it links back to. */
1407 FOR_EACH_LOG_LINK (links
, insn
)
1410 rtx temp
= links
->insn
;
1411 if ((set
= single_set (temp
)) != 0
1412 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1413 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1414 /* Avoid using a register that may already been marked
1415 dead by an earlier instruction. */
1416 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1417 && (GET_MODE (note
) == VOIDmode
1418 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1419 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1421 /* Temporarily replace the set's source with the
1422 contents of the REG_EQUAL note. The insn will
1423 be deleted or recognized by try_combine. */
1424 rtx orig
= SET_SRC (set
);
1425 SET_SRC (set
) = note
;
1427 i2mod_old_rhs
= copy_rtx (orig
);
1428 i2mod_new_rhs
= copy_rtx (note
);
1429 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1431 last_combined_insn
);
1435 SET_SRC (set
) = orig
;
1440 record_dead_and_set_regs (insn
);
1448 default_rtl_profile ();
1450 new_direct_jump_p
|= purge_all_dead_edges ();
1451 delete_noop_moves ();
1454 obstack_free (&insn_link_obstack
, NULL
);
1455 free (uid_log_links
);
1456 free (uid_insn_cost
);
1457 reg_stat
.release ();
1460 struct undo
*undo
, *next
;
1461 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1469 total_attempts
+= combine_attempts
;
1470 total_merges
+= combine_merges
;
1471 total_extras
+= combine_extras
;
1472 total_successes
+= combine_successes
;
1474 nonzero_sign_valid
= 0;
1475 rtl_hooks
= general_rtl_hooks
;
1477 /* Make recognizer allow volatile MEMs again. */
1480 return new_direct_jump_p
;
1483 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1486 init_reg_last (void)
1491 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1492 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1495 /* Set up any promoted values for incoming argument registers. */
1498 setup_incoming_promotions (rtx first
)
1501 bool strictly_local
= false;
1503 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1504 arg
= DECL_CHAIN (arg
))
1506 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1508 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1510 /* Only continue if the incoming argument is in a register. */
1514 /* Determine, if possible, whether all call sites of the current
1515 function lie within the current compilation unit. (This does
1516 take into account the exporting of a function via taking its
1517 address, and so forth.) */
1518 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1520 /* The mode and signedness of the argument before any promotions happen
1521 (equal to the mode of the pseudo holding it at that stage). */
1522 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1523 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1525 /* The mode and signedness of the argument after any source language and
1526 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1527 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1528 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1530 /* The mode and signedness of the argument as it is actually passed,
1531 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1532 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1533 TREE_TYPE (cfun
->decl
), 0);
1535 /* The mode of the register in which the argument is being passed. */
1536 mode4
= GET_MODE (reg
);
1538 /* Eliminate sign extensions in the callee when:
1539 (a) A mode promotion has occurred; */
1542 /* (b) The mode of the register is the same as the mode of
1543 the argument as it is passed; */
1546 /* (c) There's no language level extension; */
1549 /* (c.1) All callers are from the current compilation unit. If that's
1550 the case we don't have to rely on an ABI, we only have to know
1551 what we're generating right now, and we know that we will do the
1552 mode1 to mode2 promotion with the given sign. */
1553 else if (!strictly_local
)
1555 /* (c.2) The combination of the two promotions is useful. This is
1556 true when the signs match, or if the first promotion is unsigned.
1557 In the later case, (sign_extend (zero_extend x)) is the same as
1558 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1564 /* Record that the value was promoted from mode1 to mode3,
1565 so that any sign extension at the head of the current
1566 function may be eliminated. */
1567 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1568 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1569 record_value_for_reg (reg
, first
, x
);
1573 /* Called via note_stores. If X is a pseudo that is narrower than
1574 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1576 If we are setting only a portion of X and we can't figure out what
1577 portion, assume all bits will be used since we don't know what will
1580 Similarly, set how many bits of X are known to be copies of the sign bit
1581 at all locations in the function. This is the smallest number implied
1585 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1587 rtx insn
= (rtx
) data
;
1591 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1592 /* If this register is undefined at the start of the file, we can't
1593 say what its contents were. */
1594 && ! REGNO_REG_SET_P
1595 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1596 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1598 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1600 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1602 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1603 rsp
->sign_bit_copies
= 1;
1607 /* If this register is being initialized using itself, and the
1608 register is uninitialized in this basic block, and there are
1609 no LOG_LINKS which set the register, then part of the
1610 register is uninitialized. In that case we can't assume
1611 anything about the number of nonzero bits.
1613 ??? We could do better if we checked this in
1614 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1615 could avoid making assumptions about the insn which initially
1616 sets the register, while still using the information in other
1617 insns. We would have to be careful to check every insn
1618 involved in the combination. */
1621 && reg_referenced_p (x
, PATTERN (insn
))
1622 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1625 struct insn_link
*link
;
1627 FOR_EACH_LOG_LINK (link
, insn
)
1628 if (dead_or_set_p (link
->insn
, x
))
1632 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1633 rsp
->sign_bit_copies
= 1;
1638 /* If this is a complex assignment, see if we can convert it into a
1639 simple assignment. */
1640 set
= expand_field_assignment (set
);
1642 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1643 set what we know about X. */
1645 if (SET_DEST (set
) == x
1646 || (paradoxical_subreg_p (SET_DEST (set
))
1647 && SUBREG_REG (SET_DEST (set
)) == x
))
1649 rtx src
= SET_SRC (set
);
1651 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1652 /* If X is narrower than a word and SRC is a non-negative
1653 constant that would appear negative in the mode of X,
1654 sign-extend it for use in reg_stat[].nonzero_bits because some
1655 machines (maybe most) will actually do the sign-extension
1656 and this is the conservative approach.
1658 ??? For 2.5, try to tighten up the MD files in this regard
1659 instead of this kludge. */
1661 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1662 && CONST_INT_P (src
)
1664 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1665 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1668 /* Don't call nonzero_bits if it cannot change anything. */
1669 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1670 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1671 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1672 if (rsp
->sign_bit_copies
== 0
1673 || rsp
->sign_bit_copies
> num
)
1674 rsp
->sign_bit_copies
= num
;
1678 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1679 rsp
->sign_bit_copies
= 1;
1684 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1685 optionally insns that were previously combined into I3 or that will be
1686 combined into the merger of INSN and I3. The order is PRED, PRED2,
1687 INSN, SUCC, SUCC2, I3.
1689 Return 0 if the combination is not allowed for any reason.
1691 If the combination is allowed, *PDEST will be set to the single
1692 destination of INSN and *PSRC to the single source, and this function
1696 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1697 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1698 rtx
*pdest
, rtx
*psrc
)
1707 bool all_adjacent
= true;
1708 int (*is_volatile_p
) (const_rtx
);
1714 if (next_active_insn (succ2
) != i3
)
1715 all_adjacent
= false;
1716 if (next_active_insn (succ
) != succ2
)
1717 all_adjacent
= false;
1719 else if (next_active_insn (succ
) != i3
)
1720 all_adjacent
= false;
1721 if (next_active_insn (insn
) != succ
)
1722 all_adjacent
= false;
1724 else if (next_active_insn (insn
) != i3
)
1725 all_adjacent
= false;
1727 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1728 or a PARALLEL consisting of such a SET and CLOBBERs.
1730 If INSN has CLOBBER parallel parts, ignore them for our processing.
1731 By definition, these happen during the execution of the insn. When it
1732 is merged with another insn, all bets are off. If they are, in fact,
1733 needed and aren't also supplied in I3, they may be added by
1734 recog_for_combine. Otherwise, it won't match.
1736 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1739 Get the source and destination of INSN. If more than one, can't
1742 if (GET_CODE (PATTERN (insn
)) == SET
)
1743 set
= PATTERN (insn
);
1744 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1745 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1747 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1749 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1751 switch (GET_CODE (elt
))
1753 /* This is important to combine floating point insns
1754 for the SH4 port. */
1756 /* Combining an isolated USE doesn't make sense.
1757 We depend here on combinable_i3pat to reject them. */
1758 /* The code below this loop only verifies that the inputs of
1759 the SET in INSN do not change. We call reg_set_between_p
1760 to verify that the REG in the USE does not change between
1762 If the USE in INSN was for a pseudo register, the matching
1763 insn pattern will likely match any register; combining this
1764 with any other USE would only be safe if we knew that the
1765 used registers have identical values, or if there was
1766 something to tell them apart, e.g. different modes. For
1767 now, we forgo such complicated tests and simply disallow
1768 combining of USES of pseudo registers with any other USE. */
1769 if (REG_P (XEXP (elt
, 0))
1770 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1772 rtx i3pat
= PATTERN (i3
);
1773 int i
= XVECLEN (i3pat
, 0) - 1;
1774 unsigned int regno
= REGNO (XEXP (elt
, 0));
1778 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1780 if (GET_CODE (i3elt
) == USE
1781 && REG_P (XEXP (i3elt
, 0))
1782 && (REGNO (XEXP (i3elt
, 0)) == regno
1783 ? reg_set_between_p (XEXP (elt
, 0),
1784 PREV_INSN (insn
), i3
)
1785 : regno
>= FIRST_PSEUDO_REGISTER
))
1792 /* We can ignore CLOBBERs. */
1797 /* Ignore SETs whose result isn't used but not those that
1798 have side-effects. */
1799 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1800 && insn_nothrow_p (insn
)
1801 && !side_effects_p (elt
))
1804 /* If we have already found a SET, this is a second one and
1805 so we cannot combine with this insn. */
1813 /* Anything else means we can't combine. */
1819 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1820 so don't do anything with it. */
1821 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1830 /* The simplification in expand_field_assignment may call back to
1831 get_last_value, so set safe guard here. */
1832 subst_low_luid
= DF_INSN_LUID (insn
);
1834 set
= expand_field_assignment (set
);
1835 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1837 /* Don't eliminate a store in the stack pointer. */
1838 if (dest
== stack_pointer_rtx
1839 /* Don't combine with an insn that sets a register to itself if it has
1840 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1841 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1842 /* Can't merge an ASM_OPERANDS. */
1843 || GET_CODE (src
) == ASM_OPERANDS
1844 /* Can't merge a function call. */
1845 || GET_CODE (src
) == CALL
1846 /* Don't eliminate a function call argument. */
1848 && (find_reg_fusage (i3
, USE
, dest
)
1850 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1851 && global_regs
[REGNO (dest
)])))
1852 /* Don't substitute into an incremented register. */
1853 || FIND_REG_INC_NOTE (i3
, dest
)
1854 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1855 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1856 /* Don't substitute into a non-local goto, this confuses CFG. */
1857 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1858 /* Make sure that DEST is not used after SUCC but before I3. */
1861 && (reg_used_between_p (dest
, succ2
, i3
)
1862 || reg_used_between_p (dest
, succ
, succ2
)))
1863 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1864 /* Make sure that the value that is to be substituted for the register
1865 does not use any registers whose values alter in between. However,
1866 If the insns are adjacent, a use can't cross a set even though we
1867 think it might (this can happen for a sequence of insns each setting
1868 the same destination; last_set of that register might point to
1869 a NOTE). If INSN has a REG_EQUIV note, the register is always
1870 equivalent to the memory so the substitution is valid even if there
1871 are intervening stores. Also, don't move a volatile asm or
1872 UNSPEC_VOLATILE across any other insns. */
1875 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1876 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1877 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1878 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1879 /* Don't combine across a CALL_INSN, because that would possibly
1880 change whether the life span of some REGs crosses calls or not,
1881 and it is a pain to update that information.
1882 Exception: if source is a constant, moving it later can't hurt.
1883 Accept that as a special case. */
1884 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1887 /* DEST must either be a REG or CC0. */
1890 /* If register alignment is being enforced for multi-word items in all
1891 cases except for parameters, it is possible to have a register copy
1892 insn referencing a hard register that is not allowed to contain the
1893 mode being copied and which would not be valid as an operand of most
1894 insns. Eliminate this problem by not combining with such an insn.
1896 Also, on some machines we don't want to extend the life of a hard
1900 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1901 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1902 /* Don't extend the life of a hard register unless it is
1903 user variable (if we have few registers) or it can't
1904 fit into the desired register (meaning something special
1906 Also avoid substituting a return register into I3, because
1907 reload can't handle a conflict with constraints of other
1909 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1910 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1913 else if (GET_CODE (dest
) != CC0
)
1917 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1918 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1919 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1921 /* Don't substitute for a register intended as a clobberable
1923 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1924 if (rtx_equal_p (reg
, dest
))
1927 /* If the clobber represents an earlyclobber operand, we must not
1928 substitute an expression containing the clobbered register.
1929 As we do not analyze the constraint strings here, we have to
1930 make the conservative assumption. However, if the register is
1931 a fixed hard reg, the clobber cannot represent any operand;
1932 we leave it up to the machine description to either accept or
1933 reject use-and-clobber patterns. */
1935 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1936 || !fixed_regs
[REGNO (reg
)])
1937 if (reg_overlap_mentioned_p (reg
, src
))
1941 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1942 or not), reject, unless nothing volatile comes between it and I3 */
1944 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1946 /* Make sure neither succ nor succ2 contains a volatile reference. */
1947 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1949 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1951 /* We'll check insns between INSN and I3 below. */
1954 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1955 to be an explicit register variable, and was chosen for a reason. */
1957 if (GET_CODE (src
) == ASM_OPERANDS
1958 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1961 /* If INSN contains volatile references (specifically volatile MEMs),
1962 we cannot combine across any other volatile references.
1963 Even if INSN doesn't contain volatile references, any intervening
1964 volatile insn might affect machine state. */
1966 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
1970 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1971 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
1974 /* If INSN contains an autoincrement or autodecrement, make sure that
1975 register is not used between there and I3, and not already used in
1976 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1977 Also insist that I3 not be a jump; if it were one
1978 and the incremented register were spilled, we would lose. */
1981 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1982 if (REG_NOTE_KIND (link
) == REG_INC
1984 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1985 || (pred
!= NULL_RTX
1986 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1987 || (pred2
!= NULL_RTX
1988 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1989 || (succ
!= NULL_RTX
1990 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1991 || (succ2
!= NULL_RTX
1992 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1993 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1998 /* Don't combine an insn that follows a CC0-setting insn.
1999 An insn that uses CC0 must not be separated from the one that sets it.
2000 We do, however, allow I2 to follow a CC0-setting insn if that insn
2001 is passed as I1; in that case it will be deleted also.
2002 We also allow combining in this case if all the insns are adjacent
2003 because that would leave the two CC0 insns adjacent as well.
2004 It would be more logical to test whether CC0 occurs inside I1 or I2,
2005 but that would be much slower, and this ought to be equivalent. */
2007 p
= prev_nonnote_insn (insn
);
2008 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2013 /* If we get here, we have passed all the tests and the combination is
2022 /* LOC is the location within I3 that contains its pattern or the component
2023 of a PARALLEL of the pattern. We validate that it is valid for combining.
2025 One problem is if I3 modifies its output, as opposed to replacing it
2026 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2027 doing so would produce an insn that is not equivalent to the original insns.
2031 (set (reg:DI 101) (reg:DI 100))
2032 (set (subreg:SI (reg:DI 101) 0) <foo>)
2034 This is NOT equivalent to:
2036 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2037 (set (reg:DI 101) (reg:DI 100))])
2039 Not only does this modify 100 (in which case it might still be valid
2040 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2042 We can also run into a problem if I2 sets a register that I1
2043 uses and I1 gets directly substituted into I3 (not via I2). In that
2044 case, we would be getting the wrong value of I2DEST into I3, so we
2045 must reject the combination. This case occurs when I2 and I1 both
2046 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2047 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2048 of a SET must prevent combination from occurring. The same situation
2049 can occur for I0, in which case I0_NOT_IN_SRC is set.
2051 Before doing the above check, we first try to expand a field assignment
2052 into a set of logical operations.
2054 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2055 we place a register that is both set and used within I3. If more than one
2056 such register is detected, we fail.
2058 Return 1 if the combination is valid, zero otherwise. */
2061 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2062 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2066 if (GET_CODE (x
) == SET
)
2069 rtx dest
= SET_DEST (set
);
2070 rtx src
= SET_SRC (set
);
2071 rtx inner_dest
= dest
;
2074 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2075 || GET_CODE (inner_dest
) == SUBREG
2076 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2077 inner_dest
= XEXP (inner_dest
, 0);
2079 /* Check for the case where I3 modifies its output, as discussed
2080 above. We don't want to prevent pseudos from being combined
2081 into the address of a MEM, so only prevent the combination if
2082 i1 or i2 set the same MEM. */
2083 if ((inner_dest
!= dest
&&
2084 (!MEM_P (inner_dest
)
2085 || rtx_equal_p (i2dest
, inner_dest
)
2086 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2087 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2088 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2089 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2090 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2092 /* This is the same test done in can_combine_p except we can't test
2093 all_adjacent; we don't have to, since this instruction will stay
2094 in place, thus we are not considering increasing the lifetime of
2097 Also, if this insn sets a function argument, combining it with
2098 something that might need a spill could clobber a previous
2099 function argument; the all_adjacent test in can_combine_p also
2100 checks this; here, we do a more specific test for this case. */
2102 || (REG_P (inner_dest
)
2103 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2104 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2105 GET_MODE (inner_dest
))))
2106 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2107 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2110 /* If DEST is used in I3, it is being killed in this insn, so
2111 record that for later. We have to consider paradoxical
2112 subregs here, since they kill the whole register, but we
2113 ignore partial subregs, STRICT_LOW_PART, etc.
2114 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2115 STACK_POINTER_REGNUM, since these are always considered to be
2116 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2118 if (GET_CODE (subdest
) == SUBREG
2119 && (GET_MODE_SIZE (GET_MODE (subdest
))
2120 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2121 subdest
= SUBREG_REG (subdest
);
2124 && reg_referenced_p (subdest
, PATTERN (i3
))
2125 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2126 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2127 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2129 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2130 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2131 || ! fixed_regs
[REGNO (subdest
)])
2133 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2135 if (*pi3dest_killed
)
2138 *pi3dest_killed
= subdest
;
2142 else if (GET_CODE (x
) == PARALLEL
)
2146 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2147 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2148 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2155 /* Return 1 if X is an arithmetic expression that contains a multiplication
2156 and division. We don't count multiplications by powers of two here. */
2159 contains_muldiv (rtx x
)
2161 switch (GET_CODE (x
))
2163 case MOD
: case DIV
: case UMOD
: case UDIV
:
2167 return ! (CONST_INT_P (XEXP (x
, 1))
2168 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2171 return contains_muldiv (XEXP (x
, 0))
2172 || contains_muldiv (XEXP (x
, 1));
2175 return contains_muldiv (XEXP (x
, 0));
2181 /* Determine whether INSN can be used in a combination. Return nonzero if
2182 not. This is used in try_combine to detect early some cases where we
2183 can't perform combinations. */
2186 cant_combine_insn_p (rtx insn
)
2191 /* If this isn't really an insn, we can't do anything.
2192 This can occur when flow deletes an insn that it has merged into an
2193 auto-increment address. */
2194 if (! INSN_P (insn
))
2197 /* Never combine loads and stores involving hard regs that are likely
2198 to be spilled. The register allocator can usually handle such
2199 reg-reg moves by tying. If we allow the combiner to make
2200 substitutions of likely-spilled regs, reload might die.
2201 As an exception, we allow combinations involving fixed regs; these are
2202 not available to the register allocator so there's no risk involved. */
2204 set
= single_set (insn
);
2207 src
= SET_SRC (set
);
2208 dest
= SET_DEST (set
);
2209 if (GET_CODE (src
) == SUBREG
)
2210 src
= SUBREG_REG (src
);
2211 if (GET_CODE (dest
) == SUBREG
)
2212 dest
= SUBREG_REG (dest
);
2213 if (REG_P (src
) && REG_P (dest
)
2214 && ((HARD_REGISTER_P (src
)
2215 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2216 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2217 || (HARD_REGISTER_P (dest
)
2218 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2219 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2225 struct likely_spilled_retval_info
2227 unsigned regno
, nregs
;
2231 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2232 hard registers that are known to be written to / clobbered in full. */
2234 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2236 struct likely_spilled_retval_info
*const info
=
2237 (struct likely_spilled_retval_info
*) data
;
2238 unsigned regno
, nregs
;
2241 if (!REG_P (XEXP (set
, 0)))
2244 if (regno
>= info
->regno
+ info
->nregs
)
2246 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2247 if (regno
+ nregs
<= info
->regno
)
2249 new_mask
= (2U << (nregs
- 1)) - 1;
2250 if (regno
< info
->regno
)
2251 new_mask
>>= info
->regno
- regno
;
2253 new_mask
<<= regno
- info
->regno
;
2254 info
->mask
&= ~new_mask
;
2257 /* Return nonzero iff part of the return value is live during INSN, and
2258 it is likely spilled. This can happen when more than one insn is needed
2259 to copy the return value, e.g. when we consider to combine into the
2260 second copy insn for a complex value. */
2263 likely_spilled_retval_p (rtx insn
)
2265 rtx use
= BB_END (this_basic_block
);
2267 unsigned regno
, nregs
;
2268 /* We assume here that no machine mode needs more than
2269 32 hard registers when the value overlaps with a register
2270 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2272 struct likely_spilled_retval_info info
;
2274 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2276 reg
= XEXP (PATTERN (use
), 0);
2277 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2279 regno
= REGNO (reg
);
2280 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2283 mask
= (2U << (nregs
- 1)) - 1;
2285 /* Disregard parts of the return value that are set later. */
2289 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2291 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2294 /* Check if any of the (probably) live return value registers is
2299 if ((mask
& 1 << nregs
)
2300 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2306 /* Adjust INSN after we made a change to its destination.
2308 Changing the destination can invalidate notes that say something about
2309 the results of the insn and a LOG_LINK pointing to the insn. */
2312 adjust_for_new_dest (rtx insn
)
2314 /* For notes, be conservative and simply remove them. */
2315 remove_reg_equal_equiv_notes (insn
);
2317 /* The new insn will have a destination that was previously the destination
2318 of an insn just above it. Call distribute_links to make a LOG_LINK from
2319 the next use of that destination. */
2320 distribute_links (alloc_insn_link (insn
, NULL
));
2322 df_insn_rescan (insn
);
2325 /* Return TRUE if combine can reuse reg X in mode MODE.
2326 ADDED_SETS is nonzero if the original set is still required. */
2328 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2336 /* Allow hard registers if the new mode is legal, and occupies no more
2337 registers than the old mode. */
2338 if (regno
< FIRST_PSEUDO_REGISTER
)
2339 return (HARD_REGNO_MODE_OK (regno
, mode
)
2340 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2341 >= hard_regno_nregs
[regno
][mode
]));
2343 /* Or a pseudo that is only used once. */
2344 return (REG_N_SETS (regno
) == 1 && !added_sets
2345 && !REG_USERVAR_P (x
));
2349 /* Check whether X, the destination of a set, refers to part of
2350 the register specified by REG. */
2353 reg_subword_p (rtx x
, rtx reg
)
2355 /* Check that reg is an integer mode register. */
2356 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2359 if (GET_CODE (x
) == STRICT_LOW_PART
2360 || GET_CODE (x
) == ZERO_EXTRACT
)
2363 return GET_CODE (x
) == SUBREG
2364 && SUBREG_REG (x
) == reg
2365 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2368 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2369 Note that the INSN should be deleted *after* removing dead edges, so
2370 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2371 but not for a (set (pc) (label_ref FOO)). */
2374 update_cfg_for_uncondjump (rtx insn
)
2376 basic_block bb
= BLOCK_FOR_INSN (insn
);
2377 gcc_assert (BB_END (bb
) == insn
);
2379 purge_dead_edges (bb
);
2382 if (EDGE_COUNT (bb
->succs
) == 1)
2386 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2388 /* Remove barriers from the footer if there are any. */
2389 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2390 if (BARRIER_P (insn
))
2392 if (PREV_INSN (insn
))
2393 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2395 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2396 if (NEXT_INSN (insn
))
2397 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2399 else if (LABEL_P (insn
))
2404 /* Try to combine the insns I0, I1 and I2 into I3.
2405 Here I0, I1 and I2 appear earlier than I3.
2406 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2409 If we are combining more than two insns and the resulting insn is not
2410 recognized, try splitting it into two insns. If that happens, I2 and I3
2411 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2412 Otherwise, I0, I1 and I2 are pseudo-deleted.
2414 Return 0 if the combination does not work. Then nothing is changed.
2415 If we did the combination, return the insn at which combine should
2418 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2419 new direct jump instruction.
2421 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2422 been I3 passed to an earlier try_combine within the same basic
2426 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
,
2427 rtx last_combined_insn
)
2429 /* New patterns for I3 and I2, respectively. */
2430 rtx newpat
, newi2pat
= 0;
2431 rtvec newpat_vec_with_clobbers
= 0;
2432 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2433 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2435 int added_sets_0
, added_sets_1
, added_sets_2
;
2436 /* Total number of SETs to put into I3. */
2438 /* Nonzero if I2's or I1's body now appears in I3. */
2439 int i2_is_used
= 0, i1_is_used
= 0;
2440 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2441 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2442 /* Contains I3 if the destination of I3 is used in its source, which means
2443 that the old life of I3 is being killed. If that usage is placed into
2444 I2 and not in I3, a REG_DEAD note must be made. */
2445 rtx i3dest_killed
= 0;
2446 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2447 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2448 /* Copy of SET_SRC of I1 and I0, if needed. */
2449 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2450 /* Set if I2DEST was reused as a scratch register. */
2451 bool i2scratch
= false;
2452 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2453 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2454 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2455 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2456 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2457 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2458 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2459 /* Notes that must be added to REG_NOTES in I3 and I2. */
2460 rtx new_i3_notes
, new_i2_notes
;
2461 /* Notes that we substituted I3 into I2 instead of the normal case. */
2462 int i3_subst_into_i2
= 0;
2463 /* Notes that I1, I2 or I3 is a MULT operation. */
2466 int changed_i3_dest
= 0;
2470 struct insn_link
*link
;
2472 rtx new_other_notes
;
2475 /* Only try four-insn combinations when there's high likelihood of
2476 success. Look for simple insns, such as loads of constants or
2477 binary operations involving a constant. */
2484 if (!flag_expensive_optimizations
)
2487 for (i
= 0; i
< 4; i
++)
2489 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2490 rtx set
= single_set (insn
);
2494 src
= SET_SRC (set
);
2495 if (CONSTANT_P (src
))
2500 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2502 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2503 || GET_CODE (src
) == LSHIFTRT
)
2506 if (ngood
< 2 && nshift
< 2)
2510 /* Exit early if one of the insns involved can't be used for
2512 if (cant_combine_insn_p (i3
)
2513 || cant_combine_insn_p (i2
)
2514 || (i1
&& cant_combine_insn_p (i1
))
2515 || (i0
&& cant_combine_insn_p (i0
))
2516 || likely_spilled_retval_p (i3
))
2520 undobuf
.other_insn
= 0;
2522 /* Reset the hard register usage information. */
2523 CLEAR_HARD_REG_SET (newpat_used_regs
);
2525 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2528 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2529 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2531 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2532 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2534 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2535 INSN_UID (i2
), INSN_UID (i3
));
2538 /* If multiple insns feed into one of I2 or I3, they can be in any
2539 order. To simplify the code below, reorder them in sequence. */
2540 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2541 temp
= i2
, i2
= i0
, i0
= temp
;
2542 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2543 temp
= i1
, i1
= i0
, i0
= temp
;
2544 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2545 temp
= i1
, i1
= i2
, i2
= temp
;
2547 added_links_insn
= 0;
2549 /* First check for one important special case that the code below will
2550 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2551 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2552 we may be able to replace that destination with the destination of I3.
2553 This occurs in the common code where we compute both a quotient and
2554 remainder into a structure, in which case we want to do the computation
2555 directly into the structure to avoid register-register copies.
2557 Note that this case handles both multiple sets in I2 and also cases
2558 where I2 has a number of CLOBBERs inside the PARALLEL.
2560 We make very conservative checks below and only try to handle the
2561 most common cases of this. For example, we only handle the case
2562 where I2 and I3 are adjacent to avoid making difficult register
2565 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2566 && REG_P (SET_SRC (PATTERN (i3
)))
2567 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2568 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2569 && GET_CODE (PATTERN (i2
)) == PARALLEL
2570 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2571 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2572 below would need to check what is inside (and reg_overlap_mentioned_p
2573 doesn't support those codes anyway). Don't allow those destinations;
2574 the resulting insn isn't likely to be recognized anyway. */
2575 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2576 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2577 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2578 SET_DEST (PATTERN (i3
)))
2579 && next_active_insn (i2
) == i3
)
2581 rtx p2
= PATTERN (i2
);
2583 /* Make sure that the destination of I3,
2584 which we are going to substitute into one output of I2,
2585 is not used within another output of I2. We must avoid making this:
2586 (parallel [(set (mem (reg 69)) ...)
2587 (set (reg 69) ...)])
2588 which is not well-defined as to order of actions.
2589 (Besides, reload can't handle output reloads for this.)
2591 The problem can also happen if the dest of I3 is a memory ref,
2592 if another dest in I2 is an indirect memory ref. */
2593 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2594 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2595 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2596 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2597 SET_DEST (XVECEXP (p2
, 0, i
))))
2600 if (i
== XVECLEN (p2
, 0))
2601 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2602 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2603 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2608 subst_low_luid
= DF_INSN_LUID (i2
);
2610 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2611 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2612 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2613 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2615 /* Replace the dest in I2 with our dest and make the resulting
2616 insn the new pattern for I3. Then skip to where we validate
2617 the pattern. Everything was set up above. */
2618 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2620 i3_subst_into_i2
= 1;
2621 goto validate_replacement
;
2625 /* If I2 is setting a pseudo to a constant and I3 is setting some
2626 sub-part of it to another constant, merge them by making a new
2629 && (temp
= single_set (i2
)) != 0
2630 && CONST_SCALAR_INT_P (SET_SRC (temp
))
2631 && GET_CODE (PATTERN (i3
)) == SET
2632 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2633 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2635 rtx dest
= SET_DEST (PATTERN (i3
));
2639 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2641 if (CONST_INT_P (XEXP (dest
, 1))
2642 && CONST_INT_P (XEXP (dest
, 2)))
2644 width
= INTVAL (XEXP (dest
, 1));
2645 offset
= INTVAL (XEXP (dest
, 2));
2646 dest
= XEXP (dest
, 0);
2647 if (BITS_BIG_ENDIAN
)
2648 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2653 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2654 dest
= XEXP (dest
, 0);
2655 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2661 /* If this is the low part, we're done. */
2662 if (subreg_lowpart_p (dest
))
2664 /* Handle the case where inner is twice the size of outer. */
2665 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2666 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2667 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2668 /* Otherwise give up for now. */
2675 rtx inner
= SET_SRC (PATTERN (i3
));
2676 rtx outer
= SET_SRC (temp
);
2679 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp
))),
2680 std::make_pair (inner
, GET_MODE (dest
)),
2685 subst_low_luid
= DF_INSN_LUID (i2
);
2686 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2687 i2dest
= SET_DEST (temp
);
2688 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2690 /* Replace the source in I2 with the new constant and make the
2691 resulting insn the new pattern for I3. Then skip to where we
2692 validate the pattern. Everything was set up above. */
2693 SUBST (SET_SRC (temp
),
2694 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp
))));
2696 newpat
= PATTERN (i2
);
2698 /* The dest of I3 has been replaced with the dest of I2. */
2699 changed_i3_dest
= 1;
2700 goto validate_replacement
;
2705 /* If we have no I1 and I2 looks like:
2706 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2708 make up a dummy I1 that is
2711 (set (reg:CC X) (compare:CC Y (const_int 0)))
2713 (We can ignore any trailing CLOBBERs.)
2715 This undoes a previous combination and allows us to match a branch-and-
2718 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2719 && XVECLEN (PATTERN (i2
), 0) >= 2
2720 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2721 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2723 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2724 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2725 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2726 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2727 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2728 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2730 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2731 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2736 /* We make I1 with the same INSN_UID as I2. This gives it
2737 the same DF_INSN_LUID for value tracking. Our fake I1 will
2738 never appear in the insn stream so giving it the same INSN_UID
2739 as I2 will not cause a problem. */
2741 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2742 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2743 INSN_LOCATION (i2
), -1, NULL_RTX
);
2745 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2746 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2747 SET_DEST (PATTERN (i1
)));
2748 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2753 /* Verify that I2 and I1 are valid for combining. */
2754 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2755 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2757 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2764 /* Record whether I2DEST is used in I2SRC and similarly for the other
2765 cases. Knowing this will help in register status updating below. */
2766 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2767 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2768 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2769 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2770 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2771 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2772 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2773 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2774 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2776 /* For the earlier insns, determine which of the subsequent ones they
2778 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2779 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2780 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2781 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2782 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2784 /* Ensure that I3's pattern can be the destination of combines. */
2785 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2786 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2787 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2788 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2795 /* See if any of the insns is a MULT operation. Unless one is, we will
2796 reject a combination that is, since it must be slower. Be conservative
2798 if (GET_CODE (i2src
) == MULT
2799 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2800 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2801 || (GET_CODE (PATTERN (i3
)) == SET
2802 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2805 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2806 We used to do this EXCEPT in one case: I3 has a post-inc in an
2807 output operand. However, that exception can give rise to insns like
2809 which is a famous insn on the PDP-11 where the value of r3 used as the
2810 source was model-dependent. Avoid this sort of thing. */
2813 if (!(GET_CODE (PATTERN (i3
)) == SET
2814 && REG_P (SET_SRC (PATTERN (i3
)))
2815 && MEM_P (SET_DEST (PATTERN (i3
)))
2816 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2817 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2818 /* It's not the exception. */
2823 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2824 if (REG_NOTE_KIND (link
) == REG_INC
2825 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2827 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2835 /* See if the SETs in I1 or I2 need to be kept around in the merged
2836 instruction: whenever the value set there is still needed past I3.
2837 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2839 For the SET in I1, we have two cases: if I1 and I2 independently feed
2840 into I3, the set in I1 needs to be kept around unless I1DEST dies
2841 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2842 in I1 needs to be kept around unless I1DEST dies or is set in either
2843 I2 or I3. The same considerations apply to I0. */
2845 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2848 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2849 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2854 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2855 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
2856 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
2857 && dead_or_set_p (i2
, i0dest
)));
2861 /* We are about to copy insns for the case where they need to be kept
2862 around. Check that they can be copied in the merged instruction. */
2864 if (targetm
.cannot_copy_insn_p
2865 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2866 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2867 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2873 /* If the set in I2 needs to be kept around, we must make a copy of
2874 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2875 PATTERN (I2), we are only substituting for the original I1DEST, not into
2876 an already-substituted copy. This also prevents making self-referential
2877 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2882 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2883 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2885 i2pat
= copy_rtx (PATTERN (i2
));
2890 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2891 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2893 i1pat
= copy_rtx (PATTERN (i1
));
2898 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2899 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2901 i0pat
= copy_rtx (PATTERN (i0
));
2906 /* Substitute in the latest insn for the regs set by the earlier ones. */
2908 maxreg
= max_reg_num ();
2913 /* Many machines that don't use CC0 have insns that can both perform an
2914 arithmetic operation and set the condition code. These operations will
2915 be represented as a PARALLEL with the first element of the vector
2916 being a COMPARE of an arithmetic operation with the constant zero.
2917 The second element of the vector will set some pseudo to the result
2918 of the same arithmetic operation. If we simplify the COMPARE, we won't
2919 match such a pattern and so will generate an extra insn. Here we test
2920 for this case, where both the comparison and the operation result are
2921 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2922 I2SRC. Later we will make the PARALLEL that contains I2. */
2924 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2925 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2926 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
2927 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2930 rtx
*cc_use_loc
= NULL
, cc_use_insn
= NULL_RTX
;
2931 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
2932 enum machine_mode compare_mode
, orig_compare_mode
;
2933 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
2935 newpat
= PATTERN (i3
);
2936 newpat_dest
= SET_DEST (newpat
);
2937 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
2939 if (undobuf
.other_insn
== 0
2940 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
2943 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
2944 compare_code
= simplify_compare_const (compare_code
,
2946 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
2949 /* Do the rest only if op1 is const0_rtx, which may be the
2950 result of simplification. */
2951 if (op1
== const0_rtx
)
2953 /* If a single use of the CC is found, prepare to modify it
2954 when SELECT_CC_MODE returns a new CC-class mode, or when
2955 the above simplify_compare_const() returned a new comparison
2956 operator. undobuf.other_insn is assigned the CC use insn
2957 when modifying it. */
2960 #ifdef SELECT_CC_MODE
2961 enum machine_mode new_mode
2962 = SELECT_CC_MODE (compare_code
, op0
, op1
);
2963 if (new_mode
!= orig_compare_mode
2964 && can_change_dest_mode (SET_DEST (newpat
),
2965 added_sets_2
, new_mode
))
2967 unsigned int regno
= REGNO (newpat_dest
);
2968 compare_mode
= new_mode
;
2969 if (regno
< FIRST_PSEUDO_REGISTER
)
2970 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
2973 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2974 newpat_dest
= regno_reg_rtx
[regno
];
2978 /* Cases for modifying the CC-using comparison. */
2979 if (compare_code
!= orig_compare_code
2980 /* ??? Do we need to verify the zero rtx? */
2981 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
2983 /* Replace cc_use_loc with entire new RTX. */
2985 gen_rtx_fmt_ee (compare_code
, compare_mode
,
2986 newpat_dest
, const0_rtx
));
2987 undobuf
.other_insn
= cc_use_insn
;
2989 else if (compare_mode
!= orig_compare_mode
)
2991 /* Just replace the CC reg with a new mode. */
2992 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
2993 undobuf
.other_insn
= cc_use_insn
;
2997 /* Now we modify the current newpat:
2998 First, SET_DEST(newpat) is updated if the CC mode has been
2999 altered. For targets without SELECT_CC_MODE, this should be
3001 if (compare_mode
!= orig_compare_mode
)
3002 SUBST (SET_DEST (newpat
), newpat_dest
);
3003 /* This is always done to propagate i2src into newpat. */
3004 SUBST (SET_SRC (newpat
),
3005 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3006 /* Create new version of i2pat if needed; the below PARALLEL
3007 creation needs this to work correctly. */
3008 if (! rtx_equal_p (i2src
, op0
))
3009 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3015 if (i2_is_used
== 0)
3017 /* It is possible that the source of I2 or I1 may be performing
3018 an unneeded operation, such as a ZERO_EXTEND of something
3019 that is known to have the high part zero. Handle that case
3020 by letting subst look at the inner insns.
3022 Another way to do this would be to have a function that tries
3023 to simplify a single insn instead of merging two or more
3024 insns. We don't do this because of the potential of infinite
3025 loops and because of the potential extra memory required.
3026 However, doing it the way we are is a bit of a kludge and
3027 doesn't catch all cases.
3029 But only do this if -fexpensive-optimizations since it slows
3030 things down and doesn't usually win.
3032 This is not done in the COMPARE case above because the
3033 unmodified I2PAT is used in the PARALLEL and so a pattern
3034 with a modified I2SRC would not match. */
3036 if (flag_expensive_optimizations
)
3038 /* Pass pc_rtx so no substitutions are done, just
3042 subst_low_luid
= DF_INSN_LUID (i1
);
3043 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3046 subst_low_luid
= DF_INSN_LUID (i2
);
3047 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3050 n_occurrences
= 0; /* `subst' counts here */
3051 subst_low_luid
= DF_INSN_LUID (i2
);
3053 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3054 copy of I2SRC each time we substitute it, in order to avoid creating
3055 self-referential RTL when we will be substituting I1SRC for I1DEST
3056 later. Likewise if I0 feeds into I2, either directly or indirectly
3057 through I1, and I0DEST is in I0SRC. */
3058 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3059 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3060 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3061 && i0dest_in_i0src
));
3064 /* Record whether I2's body now appears within I3's body. */
3065 i2_is_used
= n_occurrences
;
3068 /* If we already got a failure, don't try to do more. Otherwise, try to
3069 substitute I1 if we have it. */
3071 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3073 /* Check that an autoincrement side-effect on I1 has not been lost.
3074 This happens if I1DEST is mentioned in I2 and dies there, and
3075 has disappeared from the new pattern. */
3076 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3078 && dead_or_set_p (i2
, i1dest
)
3079 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3080 /* Before we can do this substitution, we must redo the test done
3081 above (see detailed comments there) that ensures I1DEST isn't
3082 mentioned in any SETs in NEWPAT that are field assignments. */
3083 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3091 subst_low_luid
= DF_INSN_LUID (i1
);
3093 /* If the following substitution will modify I1SRC, make a copy of it
3094 for the case where it is substituted for I1DEST in I2PAT later. */
3095 if (added_sets_2
&& i1_feeds_i2_n
)
3096 i1src_copy
= copy_rtx (i1src
);
3098 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3099 copy of I1SRC each time we substitute it, in order to avoid creating
3100 self-referential RTL when we will be substituting I0SRC for I0DEST
3102 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3103 i0_feeds_i1_n
&& i0dest_in_i0src
);
3106 /* Record whether I1's body now appears within I3's body. */
3107 i1_is_used
= n_occurrences
;
3110 /* Likewise for I0 if we have it. */
3112 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3114 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3115 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3116 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3117 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3118 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3125 /* If the following substitution will modify I0SRC, make a copy of it
3126 for the case where it is substituted for I0DEST in I1PAT later. */
3127 if (added_sets_1
&& i0_feeds_i1_n
)
3128 i0src_copy
= copy_rtx (i0src
);
3129 /* And a copy for I0DEST in I2PAT substitution. */
3130 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3131 || (i0_feeds_i2_n
)))
3132 i0src_copy2
= copy_rtx (i0src
);
3135 subst_low_luid
= DF_INSN_LUID (i0
);
3136 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3140 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3141 to count all the ways that I2SRC and I1SRC can be used. */
3142 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3143 && i2_is_used
+ added_sets_2
> 1)
3144 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3145 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3147 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3148 && (n_occurrences
+ added_sets_0
3149 + (added_sets_1
&& i0_feeds_i1_n
)
3150 + (added_sets_2
&& i0_feeds_i2_n
)
3152 /* Fail if we tried to make a new register. */
3153 || max_reg_num () != maxreg
3154 /* Fail if we couldn't do something and have a CLOBBER. */
3155 || GET_CODE (newpat
) == CLOBBER
3156 /* Fail if this new pattern is a MULT and we didn't have one before
3157 at the outer level. */
3158 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3165 /* If the actions of the earlier insns must be kept
3166 in addition to substituting them into the latest one,
3167 we must make a new PARALLEL for the latest insn
3168 to hold additional the SETs. */
3170 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3172 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3175 if (GET_CODE (newpat
) == PARALLEL
)
3177 rtvec old
= XVEC (newpat
, 0);
3178 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3179 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3180 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3181 sizeof (old
->elem
[0]) * old
->num_elem
);
3186 total_sets
= 1 + extra_sets
;
3187 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3188 XVECEXP (newpat
, 0, 0) = old
;
3192 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3198 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3200 XVECEXP (newpat
, 0, --total_sets
) = t
;
3206 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3207 i0_feeds_i1_n
&& i0dest_in_i0src
);
3208 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3209 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3211 XVECEXP (newpat
, 0, --total_sets
) = t
;
3215 validate_replacement
:
3217 /* Note which hard regs this insn has as inputs. */
3218 mark_used_regs_combine (newpat
);
3220 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3221 consider splitting this pattern, we might need these clobbers. */
3222 if (i1
&& GET_CODE (newpat
) == PARALLEL
3223 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3225 int len
= XVECLEN (newpat
, 0);
3227 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3228 for (i
= 0; i
< len
; i
++)
3229 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3232 /* Is the result of combination a valid instruction? */
3233 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3235 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3236 the second SET's destination is a register that is unused and isn't
3237 marked as an instruction that might trap in an EH region. In that case,
3238 we just need the first SET. This can occur when simplifying a divmod
3239 insn. We *must* test for this case here because the code below that
3240 splits two independent SETs doesn't handle this case correctly when it
3241 updates the register status.
3243 It's pointless doing this if we originally had two sets, one from
3244 i3, and one from i2. Combining then splitting the parallel results
3245 in the original i2 again plus an invalid insn (which we delete).
3246 The net effect is only to move instructions around, which makes
3247 debug info less accurate.
3249 Also check the case where the first SET's destination is unused.
3250 That would not cause incorrect code, but does cause an unneeded
3253 if (insn_code_number
< 0
3254 && !(added_sets_2
&& i1
== 0)
3255 && GET_CODE (newpat
) == PARALLEL
3256 && XVECLEN (newpat
, 0) == 2
3257 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3258 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3259 && asm_noperands (newpat
) < 0)
3261 rtx set0
= XVECEXP (newpat
, 0, 0);
3262 rtx set1
= XVECEXP (newpat
, 0, 1);
3264 if (((REG_P (SET_DEST (set1
))
3265 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3266 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3267 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3268 && insn_nothrow_p (i3
)
3269 && !side_effects_p (SET_SRC (set1
)))
3272 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3275 else if (((REG_P (SET_DEST (set0
))
3276 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3277 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3278 && find_reg_note (i3
, REG_UNUSED
,
3279 SUBREG_REG (SET_DEST (set0
)))))
3280 && insn_nothrow_p (i3
)
3281 && !side_effects_p (SET_SRC (set0
)))
3284 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3286 if (insn_code_number
>= 0)
3287 changed_i3_dest
= 1;
3291 /* If we were combining three insns and the result is a simple SET
3292 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3293 insns. There are two ways to do this. It can be split using a
3294 machine-specific method (like when you have an addition of a large
3295 constant) or by combine in the function find_split_point. */
3297 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3298 && asm_noperands (newpat
) < 0)
3300 rtx parallel
, m_split
, *split
;
3302 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3303 use I2DEST as a scratch register will help. In the latter case,
3304 convert I2DEST to the mode of the source of NEWPAT if we can. */
3306 m_split
= combine_split_insns (newpat
, i3
);
3308 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3309 inputs of NEWPAT. */
3311 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3312 possible to try that as a scratch reg. This would require adding
3313 more code to make it work though. */
3315 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3317 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3319 /* First try to split using the original register as a
3320 scratch register. */
3321 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3322 gen_rtvec (2, newpat
,
3323 gen_rtx_CLOBBER (VOIDmode
,
3325 m_split
= combine_split_insns (parallel
, i3
);
3327 /* If that didn't work, try changing the mode of I2DEST if
3330 && new_mode
!= GET_MODE (i2dest
)
3331 && new_mode
!= VOIDmode
3332 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3334 enum machine_mode old_mode
= GET_MODE (i2dest
);
3337 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3338 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3341 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3342 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3345 parallel
= (gen_rtx_PARALLEL
3347 gen_rtvec (2, newpat
,
3348 gen_rtx_CLOBBER (VOIDmode
,
3350 m_split
= combine_split_insns (parallel
, i3
);
3353 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3357 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3358 buf
= undobuf
.undos
;
3359 undobuf
.undos
= buf
->next
;
3360 buf
->next
= undobuf
.frees
;
3361 undobuf
.frees
= buf
;
3365 i2scratch
= m_split
!= 0;
3368 /* If recog_for_combine has discarded clobbers, try to use them
3369 again for the split. */
3370 if (m_split
== 0 && newpat_vec_with_clobbers
)
3372 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3373 m_split
= combine_split_insns (parallel
, i3
);
3376 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3378 m_split
= PATTERN (m_split
);
3379 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3380 if (insn_code_number
>= 0)
3383 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3384 && (next_nonnote_nondebug_insn (i2
) == i3
3385 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3388 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3389 newi2pat
= PATTERN (m_split
);
3391 i3set
= single_set (NEXT_INSN (m_split
));
3392 i2set
= single_set (m_split
);
3394 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3396 /* If I2 or I3 has multiple SETs, we won't know how to track
3397 register status, so don't use these insns. If I2's destination
3398 is used between I2 and I3, we also can't use these insns. */
3400 if (i2_code_number
>= 0 && i2set
&& i3set
3401 && (next_nonnote_nondebug_insn (i2
) == i3
3402 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3403 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3405 if (insn_code_number
>= 0)
3408 /* It is possible that both insns now set the destination of I3.
3409 If so, we must show an extra use of it. */
3411 if (insn_code_number
>= 0)
3413 rtx new_i3_dest
= SET_DEST (i3set
);
3414 rtx new_i2_dest
= SET_DEST (i2set
);
3416 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3417 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3418 || GET_CODE (new_i3_dest
) == SUBREG
)
3419 new_i3_dest
= XEXP (new_i3_dest
, 0);
3421 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3422 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3423 || GET_CODE (new_i2_dest
) == SUBREG
)
3424 new_i2_dest
= XEXP (new_i2_dest
, 0);
3426 if (REG_P (new_i3_dest
)
3427 && REG_P (new_i2_dest
)
3428 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3429 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3433 /* If we can split it and use I2DEST, go ahead and see if that
3434 helps things be recognized. Verify that none of the registers
3435 are set between I2 and I3. */
3436 if (insn_code_number
< 0
3437 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3441 /* We need I2DEST in the proper mode. If it is a hard register
3442 or the only use of a pseudo, we can change its mode.
3443 Make sure we don't change a hard register to have a mode that
3444 isn't valid for it, or change the number of registers. */
3445 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3446 || GET_MODE (*split
) == VOIDmode
3447 || can_change_dest_mode (i2dest
, added_sets_2
,
3449 && (next_nonnote_nondebug_insn (i2
) == i3
3450 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3451 /* We can't overwrite I2DEST if its value is still used by
3453 && ! reg_referenced_p (i2dest
, newpat
))
3455 rtx newdest
= i2dest
;
3456 enum rtx_code split_code
= GET_CODE (*split
);
3457 enum machine_mode split_mode
= GET_MODE (*split
);
3458 bool subst_done
= false;
3459 newi2pat
= NULL_RTX
;
3463 /* *SPLIT may be part of I2SRC, so make sure we have the
3464 original expression around for later debug processing.
3465 We should not need I2SRC any more in other cases. */
3466 if (MAY_HAVE_DEBUG_INSNS
)
3467 i2src
= copy_rtx (i2src
);
3471 /* Get NEWDEST as a register in the proper mode. We have already
3472 validated that we can do this. */
3473 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3475 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3476 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3479 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3480 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3484 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3485 an ASHIFT. This can occur if it was inside a PLUS and hence
3486 appeared to be a memory address. This is a kludge. */
3487 if (split_code
== MULT
3488 && CONST_INT_P (XEXP (*split
, 1))
3489 && INTVAL (XEXP (*split
, 1)) > 0
3490 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3492 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3493 XEXP (*split
, 0), GEN_INT (i
)));
3494 /* Update split_code because we may not have a multiply
3496 split_code
= GET_CODE (*split
);
3499 #ifdef INSN_SCHEDULING
3500 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3501 be written as a ZERO_EXTEND. */
3502 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3504 #ifdef LOAD_EXTEND_OP
3505 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3506 what it really is. */
3507 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3509 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3510 SUBREG_REG (*split
)));
3513 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3514 SUBREG_REG (*split
)));
3518 /* Attempt to split binary operators using arithmetic identities. */
3519 if (BINARY_P (SET_SRC (newpat
))
3520 && split_mode
== GET_MODE (SET_SRC (newpat
))
3521 && ! side_effects_p (SET_SRC (newpat
)))
3523 rtx setsrc
= SET_SRC (newpat
);
3524 enum machine_mode mode
= GET_MODE (setsrc
);
3525 enum rtx_code code
= GET_CODE (setsrc
);
3526 rtx src_op0
= XEXP (setsrc
, 0);
3527 rtx src_op1
= XEXP (setsrc
, 1);
3529 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3530 if (rtx_equal_p (src_op0
, src_op1
))
3532 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3533 SUBST (XEXP (setsrc
, 0), newdest
);
3534 SUBST (XEXP (setsrc
, 1), newdest
);
3537 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3538 else if ((code
== PLUS
|| code
== MULT
)
3539 && GET_CODE (src_op0
) == code
3540 && GET_CODE (XEXP (src_op0
, 0)) == code
3541 && (INTEGRAL_MODE_P (mode
)
3542 || (FLOAT_MODE_P (mode
)
3543 && flag_unsafe_math_optimizations
)))
3545 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3546 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3547 rtx r
= XEXP (src_op0
, 1);
3550 /* Split both "((X op Y) op X) op Y" and
3551 "((X op Y) op Y) op X" as "T op T" where T is
3553 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3554 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3556 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3558 SUBST (XEXP (setsrc
, 0), newdest
);
3559 SUBST (XEXP (setsrc
, 1), newdest
);
3562 /* Split "((X op X) op Y) op Y)" as "T op T" where
3564 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3566 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3567 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3568 SUBST (XEXP (setsrc
, 0), newdest
);
3569 SUBST (XEXP (setsrc
, 1), newdest
);
3577 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3578 SUBST (*split
, newdest
);
3581 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3583 /* recog_for_combine might have added CLOBBERs to newi2pat.
3584 Make sure NEWPAT does not depend on the clobbered regs. */
3585 if (GET_CODE (newi2pat
) == PARALLEL
)
3586 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3587 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3589 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3590 if (reg_overlap_mentioned_p (reg
, newpat
))
3597 /* If the split point was a MULT and we didn't have one before,
3598 don't use one now. */
3599 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3600 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3604 /* Check for a case where we loaded from memory in a narrow mode and
3605 then sign extended it, but we need both registers. In that case,
3606 we have a PARALLEL with both loads from the same memory location.
3607 We can split this into a load from memory followed by a register-register
3608 copy. This saves at least one insn, more if register allocation can
3611 We cannot do this if the destination of the first assignment is a
3612 condition code register or cc0. We eliminate this case by making sure
3613 the SET_DEST and SET_SRC have the same mode.
3615 We cannot do this if the destination of the second assignment is
3616 a register that we have already assumed is zero-extended. Similarly
3617 for a SUBREG of such a register. */
3619 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3620 && GET_CODE (newpat
) == PARALLEL
3621 && XVECLEN (newpat
, 0) == 2
3622 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3623 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3624 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3625 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3626 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3627 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3628 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3629 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3631 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3632 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3633 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3635 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3636 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3637 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3638 && (reg_stat
[REGNO (temp
)].nonzero_bits
3639 != GET_MODE_MASK (word_mode
))))
3640 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3641 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3643 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3644 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3645 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3646 && (reg_stat
[REGNO (temp
)].nonzero_bits
3647 != GET_MODE_MASK (word_mode
)))))
3648 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3649 SET_SRC (XVECEXP (newpat
, 0, 1)))
3650 && ! find_reg_note (i3
, REG_UNUSED
,
3651 SET_DEST (XVECEXP (newpat
, 0, 0))))
3655 newi2pat
= XVECEXP (newpat
, 0, 0);
3656 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3657 newpat
= XVECEXP (newpat
, 0, 1);
3658 SUBST (SET_SRC (newpat
),
3659 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3660 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3662 if (i2_code_number
>= 0)
3663 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3665 if (insn_code_number
>= 0)
3669 /* Similarly, check for a case where we have a PARALLEL of two independent
3670 SETs but we started with three insns. In this case, we can do the sets
3671 as two separate insns. This case occurs when some SET allows two
3672 other insns to combine, but the destination of that SET is still live. */
3674 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3675 && GET_CODE (newpat
) == PARALLEL
3676 && XVECLEN (newpat
, 0) == 2
3677 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3678 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3679 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3680 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3681 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3682 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3683 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3684 XVECEXP (newpat
, 0, 0))
3685 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3686 XVECEXP (newpat
, 0, 1))
3687 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3688 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3690 rtx set0
= XVECEXP (newpat
, 0, 0);
3691 rtx set1
= XVECEXP (newpat
, 0, 1);
3693 /* Normally, it doesn't matter which of the two is done first,
3694 but the one that references cc0 can't be the second, and
3695 one which uses any regs/memory set in between i2 and i3 can't
3696 be first. The PARALLEL might also have been pre-existing in i3,
3697 so we need to make sure that we won't wrongly hoist a SET to i2
3698 that would conflict with a death note present in there. */
3699 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3700 && !(REG_P (SET_DEST (set1
))
3701 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3702 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3703 && find_reg_note (i2
, REG_DEAD
,
3704 SUBREG_REG (SET_DEST (set1
))))
3706 && !reg_referenced_p (cc0_rtx
, set0
)
3713 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3714 && !(REG_P (SET_DEST (set0
))
3715 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3716 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3717 && find_reg_note (i2
, REG_DEAD
,
3718 SUBREG_REG (SET_DEST (set0
))))
3720 && !reg_referenced_p (cc0_rtx
, set1
)
3733 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3735 if (i2_code_number
>= 0)
3737 /* recog_for_combine might have added CLOBBERs to newi2pat.
3738 Make sure NEWPAT does not depend on the clobbered regs. */
3739 if (GET_CODE (newi2pat
) == PARALLEL
)
3741 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3742 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3744 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3745 if (reg_overlap_mentioned_p (reg
, newpat
))
3753 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3757 /* If it still isn't recognized, fail and change things back the way they
3759 if ((insn_code_number
< 0
3760 /* Is the result a reasonable ASM_OPERANDS? */
3761 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3767 /* If we had to change another insn, make sure it is valid also. */
3768 if (undobuf
.other_insn
)
3770 CLEAR_HARD_REG_SET (newpat_used_regs
);
3772 other_pat
= PATTERN (undobuf
.other_insn
);
3773 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3776 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3784 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3785 they are adjacent to each other or not. */
3787 rtx p
= prev_nonnote_insn (i3
);
3788 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3789 && sets_cc0_p (newi2pat
))
3797 /* Only allow this combination if insn_rtx_costs reports that the
3798 replacement instructions are cheaper than the originals. */
3799 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3805 if (MAY_HAVE_DEBUG_INSNS
)
3809 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3810 if (undo
->kind
== UNDO_MODE
)
3812 rtx reg
= *undo
->where
.r
;
3813 enum machine_mode new_mode
= GET_MODE (reg
);
3814 enum machine_mode old_mode
= undo
->old_contents
.m
;
3816 /* Temporarily revert mode back. */
3817 adjust_reg_mode (reg
, old_mode
);
3819 if (reg
== i2dest
&& i2scratch
)
3821 /* If we used i2dest as a scratch register with a
3822 different mode, substitute it for the original
3823 i2src while its original mode is temporarily
3824 restored, and then clear i2scratch so that we don't
3825 do it again later. */
3826 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3829 /* Put back the new mode. */
3830 adjust_reg_mode (reg
, new_mode
);
3834 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3840 last
= last_combined_insn
;
3845 last
= undobuf
.other_insn
;
3847 if (DF_INSN_LUID (last
)
3848 < DF_INSN_LUID (last_combined_insn
))
3849 last
= last_combined_insn
;
3852 /* We're dealing with a reg that changed mode but not
3853 meaning, so we want to turn it into a subreg for
3854 the new mode. However, because of REG sharing and
3855 because its mode had already changed, we have to do
3856 it in two steps. First, replace any debug uses of
3857 reg, with its original mode temporarily restored,
3858 with this copy we have created; then, replace the
3859 copy with the SUBREG of the original shared reg,
3860 once again changed to the new mode. */
3861 propagate_for_debug (first
, last
, reg
, tempreg
,
3863 adjust_reg_mode (reg
, new_mode
);
3864 propagate_for_debug (first
, last
, tempreg
,
3865 lowpart_subreg (old_mode
, reg
, new_mode
),
3871 /* If we will be able to accept this, we have made a
3872 change to the destination of I3. This requires us to
3873 do a few adjustments. */
3875 if (changed_i3_dest
)
3877 PATTERN (i3
) = newpat
;
3878 adjust_for_new_dest (i3
);
3881 /* We now know that we can do this combination. Merge the insns and
3882 update the status of registers and LOG_LINKS. */
3884 if (undobuf
.other_insn
)
3888 PATTERN (undobuf
.other_insn
) = other_pat
;
3890 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3891 are still valid. Then add any non-duplicate notes added by
3892 recog_for_combine. */
3893 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3895 next
= XEXP (note
, 1);
3897 if (REG_NOTE_KIND (note
) == REG_UNUSED
3898 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3899 remove_note (undobuf
.other_insn
, note
);
3902 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3903 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3910 struct insn_link
*link
;
3913 /* I3 now uses what used to be its destination and which is now
3914 I2's destination. This requires us to do a few adjustments. */
3915 PATTERN (i3
) = newpat
;
3916 adjust_for_new_dest (i3
);
3918 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3921 However, some later insn might be using I2's dest and have
3922 a LOG_LINK pointing at I3. We must remove this link.
3923 The simplest way to remove the link is to point it at I1,
3924 which we know will be a NOTE. */
3926 /* newi2pat is usually a SET here; however, recog_for_combine might
3927 have added some clobbers. */
3928 if (GET_CODE (newi2pat
) == PARALLEL
)
3929 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3931 ni2dest
= SET_DEST (newi2pat
);
3933 for (insn
= NEXT_INSN (i3
);
3934 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
3935 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3936 insn
= NEXT_INSN (insn
))
3938 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3940 FOR_EACH_LOG_LINK (link
, insn
)
3941 if (link
->insn
== i3
)
3950 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3951 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
3954 /* Compute which registers we expect to eliminate. newi2pat may be setting
3955 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3956 same as i3dest, in which case newi2pat may be setting i1dest. */
3957 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3958 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3961 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3962 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3965 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3966 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3970 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3972 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3973 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3975 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3977 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
3979 /* Ensure that we do not have something that should not be shared but
3980 occurs multiple times in the new insns. Check this by first
3981 resetting all the `used' flags and then copying anything is shared. */
3983 reset_used_flags (i3notes
);
3984 reset_used_flags (i2notes
);
3985 reset_used_flags (i1notes
);
3986 reset_used_flags (i0notes
);
3987 reset_used_flags (newpat
);
3988 reset_used_flags (newi2pat
);
3989 if (undobuf
.other_insn
)
3990 reset_used_flags (PATTERN (undobuf
.other_insn
));
3992 i3notes
= copy_rtx_if_shared (i3notes
);
3993 i2notes
= copy_rtx_if_shared (i2notes
);
3994 i1notes
= copy_rtx_if_shared (i1notes
);
3995 i0notes
= copy_rtx_if_shared (i0notes
);
3996 newpat
= copy_rtx_if_shared (newpat
);
3997 newi2pat
= copy_rtx_if_shared (newi2pat
);
3998 if (undobuf
.other_insn
)
3999 reset_used_flags (PATTERN (undobuf
.other_insn
));
4001 INSN_CODE (i3
) = insn_code_number
;
4002 PATTERN (i3
) = newpat
;
4004 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4006 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4008 reset_used_flags (call_usage
);
4009 call_usage
= copy_rtx (call_usage
);
4013 /* I2SRC must still be meaningful at this point. Some splitting
4014 operations can invalidate I2SRC, but those operations do not
4017 replace_rtx (call_usage
, i2dest
, i2src
);
4021 replace_rtx (call_usage
, i1dest
, i1src
);
4023 replace_rtx (call_usage
, i0dest
, i0src
);
4025 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4028 if (undobuf
.other_insn
)
4029 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4031 /* We had one special case above where I2 had more than one set and
4032 we replaced a destination of one of those sets with the destination
4033 of I3. In that case, we have to update LOG_LINKS of insns later
4034 in this basic block. Note that this (expensive) case is rare.
4036 Also, in this case, we must pretend that all REG_NOTEs for I2
4037 actually came from I3, so that REG_UNUSED notes from I2 will be
4038 properly handled. */
4040 if (i3_subst_into_i2
)
4042 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4043 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4044 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4045 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4046 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4047 && ! find_reg_note (i2
, REG_UNUSED
,
4048 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4049 for (temp
= NEXT_INSN (i2
);
4051 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4052 || BB_HEAD (this_basic_block
) != temp
);
4053 temp
= NEXT_INSN (temp
))
4054 if (temp
!= i3
&& INSN_P (temp
))
4055 FOR_EACH_LOG_LINK (link
, temp
)
4056 if (link
->insn
== i2
)
4062 while (XEXP (link
, 1))
4063 link
= XEXP (link
, 1);
4064 XEXP (link
, 1) = i2notes
;
4071 LOG_LINKS (i3
) = NULL
;
4073 LOG_LINKS (i2
) = NULL
;
4078 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4079 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4081 INSN_CODE (i2
) = i2_code_number
;
4082 PATTERN (i2
) = newi2pat
;
4086 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4087 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4089 SET_INSN_DELETED (i2
);
4094 LOG_LINKS (i1
) = NULL
;
4096 if (MAY_HAVE_DEBUG_INSNS
)
4097 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4099 SET_INSN_DELETED (i1
);
4104 LOG_LINKS (i0
) = NULL
;
4106 if (MAY_HAVE_DEBUG_INSNS
)
4107 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4109 SET_INSN_DELETED (i0
);
4112 /* Get death notes for everything that is now used in either I3 or
4113 I2 and used to die in a previous insn. If we built two new
4114 patterns, move from I1 to I2 then I2 to I3 so that we get the
4115 proper movement on registers that I2 modifies. */
4118 from_luid
= DF_INSN_LUID (i0
);
4120 from_luid
= DF_INSN_LUID (i1
);
4122 from_luid
= DF_INSN_LUID (i2
);
4124 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4125 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4127 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4129 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4130 elim_i2
, elim_i1
, elim_i0
);
4132 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4133 elim_i2
, elim_i1
, elim_i0
);
4135 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4136 elim_i2
, elim_i1
, elim_i0
);
4138 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4139 elim_i2
, elim_i1
, elim_i0
);
4141 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4142 elim_i2
, elim_i1
, elim_i0
);
4144 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4145 know these are REG_UNUSED and want them to go to the desired insn,
4146 so we always pass it as i3. */
4148 if (newi2pat
&& new_i2_notes
)
4149 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4153 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4156 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4157 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4158 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4159 in that case, it might delete I2. Similarly for I2 and I1.
4160 Show an additional death due to the REG_DEAD note we make here. If
4161 we discard it in distribute_notes, we will decrement it again. */
4165 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4166 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4167 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, elim_i2
,
4170 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4171 elim_i2
, elim_i1
, elim_i0
);
4174 if (i2dest_in_i2src
)
4176 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4177 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4178 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4179 NULL_RTX
, NULL_RTX
);
4181 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4182 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4185 if (i1dest_in_i1src
)
4187 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4188 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4189 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4190 NULL_RTX
, NULL_RTX
);
4192 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4193 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4196 if (i0dest_in_i0src
)
4198 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4199 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4200 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4201 NULL_RTX
, NULL_RTX
);
4203 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4204 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4207 distribute_links (i3links
);
4208 distribute_links (i2links
);
4209 distribute_links (i1links
);
4210 distribute_links (i0links
);
4214 struct insn_link
*link
;
4215 rtx i2_insn
= 0, i2_val
= 0, set
;
4217 /* The insn that used to set this register doesn't exist, and
4218 this life of the register may not exist either. See if one of
4219 I3's links points to an insn that sets I2DEST. If it does,
4220 that is now the last known value for I2DEST. If we don't update
4221 this and I2 set the register to a value that depended on its old
4222 contents, we will get confused. If this insn is used, thing
4223 will be set correctly in combine_instructions. */
4224 FOR_EACH_LOG_LINK (link
, i3
)
4225 if ((set
= single_set (link
->insn
)) != 0
4226 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4227 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4229 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4231 /* If the reg formerly set in I2 died only once and that was in I3,
4232 zero its use count so it won't make `reload' do any work. */
4234 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4235 && ! i2dest_in_i2src
)
4236 INC_REG_N_SETS (REGNO (i2dest
), -1);
4239 if (i1
&& REG_P (i1dest
))
4241 struct insn_link
*link
;
4242 rtx i1_insn
= 0, i1_val
= 0, set
;
4244 FOR_EACH_LOG_LINK (link
, i3
)
4245 if ((set
= single_set (link
->insn
)) != 0
4246 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4247 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4249 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4251 if (! added_sets_1
&& ! i1dest_in_i1src
)
4252 INC_REG_N_SETS (REGNO (i1dest
), -1);
4255 if (i0
&& REG_P (i0dest
))
4257 struct insn_link
*link
;
4258 rtx i0_insn
= 0, i0_val
= 0, set
;
4260 FOR_EACH_LOG_LINK (link
, i3
)
4261 if ((set
= single_set (link
->insn
)) != 0
4262 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4263 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4265 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4267 if (! added_sets_0
&& ! i0dest_in_i0src
)
4268 INC_REG_N_SETS (REGNO (i0dest
), -1);
4271 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4272 been made to this insn. The order is important, because newi2pat
4273 can affect nonzero_bits of newpat. */
4275 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4276 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4279 if (undobuf
.other_insn
!= NULL_RTX
)
4283 fprintf (dump_file
, "modifying other_insn ");
4284 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4286 df_insn_rescan (undobuf
.other_insn
);
4289 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4293 fprintf (dump_file
, "modifying insn i0 ");
4294 dump_insn_slim (dump_file
, i0
);
4296 df_insn_rescan (i0
);
4299 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4303 fprintf (dump_file
, "modifying insn i1 ");
4304 dump_insn_slim (dump_file
, i1
);
4306 df_insn_rescan (i1
);
4309 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4313 fprintf (dump_file
, "modifying insn i2 ");
4314 dump_insn_slim (dump_file
, i2
);
4316 df_insn_rescan (i2
);
4319 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4323 fprintf (dump_file
, "modifying insn i3 ");
4324 dump_insn_slim (dump_file
, i3
);
4326 df_insn_rescan (i3
);
4329 /* Set new_direct_jump_p if a new return or simple jump instruction
4330 has been created. Adjust the CFG accordingly. */
4331 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4333 *new_direct_jump_p
= 1;
4334 mark_jump_label (PATTERN (i3
), i3
, 0);
4335 update_cfg_for_uncondjump (i3
);
4338 if (undobuf
.other_insn
!= NULL_RTX
4339 && (returnjump_p (undobuf
.other_insn
)
4340 || any_uncondjump_p (undobuf
.other_insn
)))
4342 *new_direct_jump_p
= 1;
4343 update_cfg_for_uncondjump (undobuf
.other_insn
);
4346 /* A noop might also need cleaning up of CFG, if it comes from the
4347 simplification of a jump. */
4349 && GET_CODE (newpat
) == SET
4350 && SET_SRC (newpat
) == pc_rtx
4351 && SET_DEST (newpat
) == pc_rtx
)
4353 *new_direct_jump_p
= 1;
4354 update_cfg_for_uncondjump (i3
);
4357 if (undobuf
.other_insn
!= NULL_RTX
4358 && JUMP_P (undobuf
.other_insn
)
4359 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4360 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4361 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4363 *new_direct_jump_p
= 1;
4364 update_cfg_for_uncondjump (undobuf
.other_insn
);
4367 combine_successes
++;
4370 if (added_links_insn
4371 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4372 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4373 return added_links_insn
;
4375 return newi2pat
? i2
: i3
;
4378 /* Undo all the modifications recorded in undobuf. */
4383 struct undo
*undo
, *next
;
4385 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4391 *undo
->where
.r
= undo
->old_contents
.r
;
4394 *undo
->where
.i
= undo
->old_contents
.i
;
4397 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4400 *undo
->where
.l
= undo
->old_contents
.l
;
4406 undo
->next
= undobuf
.frees
;
4407 undobuf
.frees
= undo
;
4413 /* We've committed to accepting the changes we made. Move all
4414 of the undos to the free list. */
4419 struct undo
*undo
, *next
;
4421 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4424 undo
->next
= undobuf
.frees
;
4425 undobuf
.frees
= undo
;
4430 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4431 where we have an arithmetic expression and return that point. LOC will
4434 try_combine will call this function to see if an insn can be split into
4438 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4441 enum rtx_code code
= GET_CODE (x
);
4443 unsigned HOST_WIDE_INT len
= 0;
4444 HOST_WIDE_INT pos
= 0;
4446 rtx inner
= NULL_RTX
;
4448 /* First special-case some codes. */
4452 #ifdef INSN_SCHEDULING
4453 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4455 if (MEM_P (SUBREG_REG (x
)))
4458 return find_split_point (&SUBREG_REG (x
), insn
, false);
4462 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4463 using LO_SUM and HIGH. */
4464 if (GET_CODE (XEXP (x
, 0)) == CONST
4465 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4467 enum machine_mode address_mode
= get_address_mode (x
);
4470 gen_rtx_LO_SUM (address_mode
,
4471 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4473 return &XEXP (XEXP (x
, 0), 0);
4477 /* If we have a PLUS whose second operand is a constant and the
4478 address is not valid, perhaps will can split it up using
4479 the machine-specific way to split large constants. We use
4480 the first pseudo-reg (one of the virtual regs) as a placeholder;
4481 it will not remain in the result. */
4482 if (GET_CODE (XEXP (x
, 0)) == PLUS
4483 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4484 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4485 MEM_ADDR_SPACE (x
)))
4487 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4488 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4492 /* This should have produced two insns, each of which sets our
4493 placeholder. If the source of the second is a valid address,
4494 we can make put both sources together and make a split point
4498 && NEXT_INSN (seq
) != NULL_RTX
4499 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4500 && NONJUMP_INSN_P (seq
)
4501 && GET_CODE (PATTERN (seq
)) == SET
4502 && SET_DEST (PATTERN (seq
)) == reg
4503 && ! reg_mentioned_p (reg
,
4504 SET_SRC (PATTERN (seq
)))
4505 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4506 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4507 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4508 && memory_address_addr_space_p
4509 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4510 MEM_ADDR_SPACE (x
)))
4512 rtx src1
= SET_SRC (PATTERN (seq
));
4513 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4515 /* Replace the placeholder in SRC2 with SRC1. If we can
4516 find where in SRC2 it was placed, that can become our
4517 split point and we can replace this address with SRC2.
4518 Just try two obvious places. */
4520 src2
= replace_rtx (src2
, reg
, src1
);
4522 if (XEXP (src2
, 0) == src1
)
4523 split
= &XEXP (src2
, 0);
4524 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4525 && XEXP (XEXP (src2
, 0), 0) == src1
)
4526 split
= &XEXP (XEXP (src2
, 0), 0);
4530 SUBST (XEXP (x
, 0), src2
);
4535 /* If that didn't work, perhaps the first operand is complex and
4536 needs to be computed separately, so make a split point there.
4537 This will occur on machines that just support REG + CONST
4538 and have a constant moved through some previous computation. */
4540 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4541 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4542 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4543 return &XEXP (XEXP (x
, 0), 0);
4546 /* If we have a PLUS whose first operand is complex, try computing it
4547 separately by making a split there. */
4548 if (GET_CODE (XEXP (x
, 0)) == PLUS
4549 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4551 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4552 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4553 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4554 return &XEXP (XEXP (x
, 0), 0);
4559 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4560 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4561 we need to put the operand into a register. So split at that
4564 if (SET_DEST (x
) == cc0_rtx
4565 && GET_CODE (SET_SRC (x
)) != COMPARE
4566 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4567 && !OBJECT_P (SET_SRC (x
))
4568 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4569 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4570 return &SET_SRC (x
);
4573 /* See if we can split SET_SRC as it stands. */
4574 split
= find_split_point (&SET_SRC (x
), insn
, true);
4575 if (split
&& split
!= &SET_SRC (x
))
4578 /* See if we can split SET_DEST as it stands. */
4579 split
= find_split_point (&SET_DEST (x
), insn
, false);
4580 if (split
&& split
!= &SET_DEST (x
))
4583 /* See if this is a bitfield assignment with everything constant. If
4584 so, this is an IOR of an AND, so split it into that. */
4585 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4586 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4587 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4588 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4589 && CONST_INT_P (SET_SRC (x
))
4590 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4591 + INTVAL (XEXP (SET_DEST (x
), 2)))
4592 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4593 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4595 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4596 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4597 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4598 rtx dest
= XEXP (SET_DEST (x
), 0);
4599 enum machine_mode mode
= GET_MODE (dest
);
4600 unsigned HOST_WIDE_INT mask
4601 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4604 if (BITS_BIG_ENDIAN
)
4605 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4607 or_mask
= gen_int_mode (src
<< pos
, mode
);
4610 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4613 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4615 simplify_gen_binary (IOR
, mode
,
4616 simplify_gen_binary (AND
, mode
,
4621 SUBST (SET_DEST (x
), dest
);
4623 split
= find_split_point (&SET_SRC (x
), insn
, true);
4624 if (split
&& split
!= &SET_SRC (x
))
4628 /* Otherwise, see if this is an operation that we can split into two.
4629 If so, try to split that. */
4630 code
= GET_CODE (SET_SRC (x
));
4635 /* If we are AND'ing with a large constant that is only a single
4636 bit and the result is only being used in a context where we
4637 need to know if it is zero or nonzero, replace it with a bit
4638 extraction. This will avoid the large constant, which might
4639 have taken more than one insn to make. If the constant were
4640 not a valid argument to the AND but took only one insn to make,
4641 this is no worse, but if it took more than one insn, it will
4644 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4645 && REG_P (XEXP (SET_SRC (x
), 0))
4646 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4647 && REG_P (SET_DEST (x
))
4648 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4649 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4650 && XEXP (*split
, 0) == SET_DEST (x
)
4651 && XEXP (*split
, 1) == const0_rtx
)
4653 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4654 XEXP (SET_SRC (x
), 0),
4655 pos
, NULL_RTX
, 1, 1, 0, 0);
4656 if (extraction
!= 0)
4658 SUBST (SET_SRC (x
), extraction
);
4659 return find_split_point (loc
, insn
, false);
4665 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4666 is known to be on, this can be converted into a NEG of a shift. */
4667 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4668 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4669 && 1 <= (pos
= exact_log2
4670 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4671 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4673 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4677 gen_rtx_LSHIFTRT (mode
,
4678 XEXP (SET_SRC (x
), 0),
4681 split
= find_split_point (&SET_SRC (x
), insn
, true);
4682 if (split
&& split
!= &SET_SRC (x
))
4688 inner
= XEXP (SET_SRC (x
), 0);
4690 /* We can't optimize if either mode is a partial integer
4691 mode as we don't know how many bits are significant
4693 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4694 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4698 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4704 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4705 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4707 inner
= XEXP (SET_SRC (x
), 0);
4708 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4709 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4711 if (BITS_BIG_ENDIAN
)
4712 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4713 unsignedp
= (code
== ZERO_EXTRACT
);
4722 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4724 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4726 /* For unsigned, we have a choice of a shift followed by an
4727 AND or two shifts. Use two shifts for field sizes where the
4728 constant might be too large. We assume here that we can
4729 always at least get 8-bit constants in an AND insn, which is
4730 true for every current RISC. */
4732 if (unsignedp
&& len
<= 8)
4734 unsigned HOST_WIDE_INT mask
4735 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4739 (mode
, gen_lowpart (mode
, inner
),
4741 gen_int_mode (mask
, mode
)));
4743 split
= find_split_point (&SET_SRC (x
), insn
, true);
4744 if (split
&& split
!= &SET_SRC (x
))
4751 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4752 gen_rtx_ASHIFT (mode
,
4753 gen_lowpart (mode
, inner
),
4754 GEN_INT (GET_MODE_PRECISION (mode
)
4756 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4758 split
= find_split_point (&SET_SRC (x
), insn
, true);
4759 if (split
&& split
!= &SET_SRC (x
))
4764 /* See if this is a simple operation with a constant as the second
4765 operand. It might be that this constant is out of range and hence
4766 could be used as a split point. */
4767 if (BINARY_P (SET_SRC (x
))
4768 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4769 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4770 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4771 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4772 return &XEXP (SET_SRC (x
), 1);
4774 /* Finally, see if this is a simple operation with its first operand
4775 not in a register. The operation might require this operand in a
4776 register, so return it as a split point. We can always do this
4777 because if the first operand were another operation, we would have
4778 already found it as a split point. */
4779 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4780 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4781 return &XEXP (SET_SRC (x
), 0);
4787 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4788 it is better to write this as (not (ior A B)) so we can split it.
4789 Similarly for IOR. */
4790 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4793 gen_rtx_NOT (GET_MODE (x
),
4794 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4796 XEXP (XEXP (x
, 0), 0),
4797 XEXP (XEXP (x
, 1), 0))));
4798 return find_split_point (loc
, insn
, set_src
);
4801 /* Many RISC machines have a large set of logical insns. If the
4802 second operand is a NOT, put it first so we will try to split the
4803 other operand first. */
4804 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4806 rtx tem
= XEXP (x
, 0);
4807 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4808 SUBST (XEXP (x
, 1), tem
);
4814 /* Canonicalization can produce (minus A (mult B C)), where C is a
4815 constant. It may be better to try splitting (plus (mult B -C) A)
4816 instead if this isn't a multiply by a power of two. */
4817 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4818 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4819 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4821 enum machine_mode mode
= GET_MODE (x
);
4822 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4823 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4824 SUBST (*loc
, gen_rtx_PLUS (mode
,
4826 XEXP (XEXP (x
, 1), 0),
4827 gen_int_mode (other_int
,
4830 return find_split_point (loc
, insn
, set_src
);
4833 /* Split at a multiply-accumulate instruction. However if this is
4834 the SET_SRC, we likely do not have such an instruction and it's
4835 worthless to try this split. */
4836 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4843 /* Otherwise, select our actions depending on our rtx class. */
4844 switch (GET_RTX_CLASS (code
))
4846 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4848 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4851 /* ... fall through ... */
4853 case RTX_COMM_ARITH
:
4855 case RTX_COMM_COMPARE
:
4856 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4859 /* ... fall through ... */
4861 /* Some machines have (and (shift ...) ...) insns. If X is not
4862 an AND, but XEXP (X, 0) is, use it as our split point. */
4863 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4864 return &XEXP (x
, 0);
4866 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4872 /* Otherwise, we don't have a split point. */
4877 /* Throughout X, replace FROM with TO, and return the result.
4878 The result is TO if X is FROM;
4879 otherwise the result is X, but its contents may have been modified.
4880 If they were modified, a record was made in undobuf so that
4881 undo_all will (among other things) return X to its original state.
4883 If the number of changes necessary is too much to record to undo,
4884 the excess changes are not made, so the result is invalid.
4885 The changes already made can still be undone.
4886 undobuf.num_undo is incremented for such changes, so by testing that
4887 the caller can tell whether the result is valid.
4889 `n_occurrences' is incremented each time FROM is replaced.
4891 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4893 IN_COND is nonzero if we are at the top level of a condition.
4895 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4896 by copying if `n_occurrences' is nonzero. */
4899 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4901 enum rtx_code code
= GET_CODE (x
);
4902 enum machine_mode op0_mode
= VOIDmode
;
4907 /* Two expressions are equal if they are identical copies of a shared
4908 RTX or if they are both registers with the same register number
4911 #define COMBINE_RTX_EQUAL_P(X,Y) \
4913 || (REG_P (X) && REG_P (Y) \
4914 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4916 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4919 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4922 /* If X and FROM are the same register but different modes, they
4923 will not have been seen as equal above. However, the log links code
4924 will make a LOG_LINKS entry for that case. If we do nothing, we
4925 will try to rerecognize our original insn and, when it succeeds,
4926 we will delete the feeding insn, which is incorrect.
4928 So force this insn not to match in this (rare) case. */
4929 if (! in_dest
&& code
== REG
&& REG_P (from
)
4930 && reg_overlap_mentioned_p (x
, from
))
4931 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4933 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4934 of which may contain things that can be combined. */
4935 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4938 /* It is possible to have a subexpression appear twice in the insn.
4939 Suppose that FROM is a register that appears within TO.
4940 Then, after that subexpression has been scanned once by `subst',
4941 the second time it is scanned, TO may be found. If we were
4942 to scan TO here, we would find FROM within it and create a
4943 self-referent rtl structure which is completely wrong. */
4944 if (COMBINE_RTX_EQUAL_P (x
, to
))
4947 /* Parallel asm_operands need special attention because all of the
4948 inputs are shared across the arms. Furthermore, unsharing the
4949 rtl results in recognition failures. Failure to handle this case
4950 specially can result in circular rtl.
4952 Solve this by doing a normal pass across the first entry of the
4953 parallel, and only processing the SET_DESTs of the subsequent
4956 if (code
== PARALLEL
4957 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4958 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4960 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
4962 /* If this substitution failed, this whole thing fails. */
4963 if (GET_CODE (new_rtx
) == CLOBBER
4964 && XEXP (new_rtx
, 0) == const0_rtx
)
4967 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4969 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4971 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4974 && GET_CODE (dest
) != CC0
4975 && GET_CODE (dest
) != PC
)
4977 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
4979 /* If this substitution failed, this whole thing fails. */
4980 if (GET_CODE (new_rtx
) == CLOBBER
4981 && XEXP (new_rtx
, 0) == const0_rtx
)
4984 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4990 len
= GET_RTX_LENGTH (code
);
4991 fmt
= GET_RTX_FORMAT (code
);
4993 /* We don't need to process a SET_DEST that is a register, CC0,
4994 or PC, so set up to skip this common case. All other cases
4995 where we want to suppress replacing something inside a
4996 SET_SRC are handled via the IN_DEST operand. */
4998 && (REG_P (SET_DEST (x
))
4999 || GET_CODE (SET_DEST (x
)) == CC0
5000 || GET_CODE (SET_DEST (x
)) == PC
))
5003 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5006 op0_mode
= GET_MODE (XEXP (x
, 0));
5008 for (i
= 0; i
< len
; i
++)
5013 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5015 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5017 new_rtx
= (unique_copy
&& n_occurrences
5018 ? copy_rtx (to
) : to
);
5023 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5026 /* If this substitution failed, this whole thing
5028 if (GET_CODE (new_rtx
) == CLOBBER
5029 && XEXP (new_rtx
, 0) == const0_rtx
)
5033 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5036 else if (fmt
[i
] == 'e')
5038 /* If this is a register being set, ignore it. */
5039 new_rtx
= XEXP (x
, i
);
5042 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5044 || code
== STRICT_LOW_PART
))
5047 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5049 /* In general, don't install a subreg involving two
5050 modes not tieable. It can worsen register
5051 allocation, and can even make invalid reload
5052 insns, since the reg inside may need to be copied
5053 from in the outside mode, and that may be invalid
5054 if it is an fp reg copied in integer mode.
5056 We allow two exceptions to this: It is valid if
5057 it is inside another SUBREG and the mode of that
5058 SUBREG and the mode of the inside of TO is
5059 tieable and it is valid if X is a SET that copies
5062 if (GET_CODE (to
) == SUBREG
5063 && ! MODES_TIEABLE_P (GET_MODE (to
),
5064 GET_MODE (SUBREG_REG (to
)))
5065 && ! (code
== SUBREG
5066 && MODES_TIEABLE_P (GET_MODE (x
),
5067 GET_MODE (SUBREG_REG (to
))))
5069 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5072 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5074 #ifdef CANNOT_CHANGE_MODE_CLASS
5077 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5078 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5081 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5084 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5088 /* If we are in a SET_DEST, suppress most cases unless we
5089 have gone inside a MEM, in which case we want to
5090 simplify the address. We assume here that things that
5091 are actually part of the destination have their inner
5092 parts in the first expression. This is true for SUBREG,
5093 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5094 things aside from REG and MEM that should appear in a
5096 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5098 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5099 || code
== ZERO_EXTRACT
))
5102 code
== IF_THEN_ELSE
&& i
== 0,
5105 /* If we found that we will have to reject this combination,
5106 indicate that by returning the CLOBBER ourselves, rather than
5107 an expression containing it. This will speed things up as
5108 well as prevent accidents where two CLOBBERs are considered
5109 to be equal, thus producing an incorrect simplification. */
5111 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5114 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5116 enum machine_mode mode
= GET_MODE (x
);
5118 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5119 GET_MODE (SUBREG_REG (x
)),
5122 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5124 else if (CONST_SCALAR_INT_P (new_rtx
)
5125 && GET_CODE (x
) == ZERO_EXTEND
)
5127 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5128 new_rtx
, GET_MODE (XEXP (x
, 0)));
5132 SUBST (XEXP (x
, i
), new_rtx
);
5137 /* Check if we are loading something from the constant pool via float
5138 extension; in this case we would undo compress_float_constant
5139 optimization and degenerate constant load to an immediate value. */
5140 if (GET_CODE (x
) == FLOAT_EXTEND
5141 && MEM_P (XEXP (x
, 0))
5142 && MEM_READONLY_P (XEXP (x
, 0)))
5144 rtx tmp
= avoid_constant_pool_reference (x
);
5149 /* Try to simplify X. If the simplification changed the code, it is likely
5150 that further simplification will help, so loop, but limit the number
5151 of repetitions that will be performed. */
5153 for (i
= 0; i
< 4; i
++)
5155 /* If X is sufficiently simple, don't bother trying to do anything
5157 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5158 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5160 if (GET_CODE (x
) == code
)
5163 code
= GET_CODE (x
);
5165 /* We no longer know the original mode of operand 0 since we
5166 have changed the form of X) */
5167 op0_mode
= VOIDmode
;
5173 /* Simplify X, a piece of RTL. We just operate on the expression at the
5174 outer level; call `subst' to simplify recursively. Return the new
5177 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5178 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5182 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5185 enum rtx_code code
= GET_CODE (x
);
5186 enum machine_mode mode
= GET_MODE (x
);
5190 /* If this is a commutative operation, put a constant last and a complex
5191 expression first. We don't need to do this for comparisons here. */
5192 if (COMMUTATIVE_ARITH_P (x
)
5193 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5196 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5197 SUBST (XEXP (x
, 1), temp
);
5200 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5201 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5202 things. Check for cases where both arms are testing the same
5205 Don't do anything if all operands are very simple. */
5208 && ((!OBJECT_P (XEXP (x
, 0))
5209 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5210 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5211 || (!OBJECT_P (XEXP (x
, 1))
5212 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5213 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5215 && (!OBJECT_P (XEXP (x
, 0))
5216 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5217 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5219 rtx cond
, true_rtx
, false_rtx
;
5221 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5223 /* If everything is a comparison, what we have is highly unlikely
5224 to be simpler, so don't use it. */
5225 && ! (COMPARISON_P (x
)
5226 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5228 rtx cop1
= const0_rtx
;
5229 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5231 if (cond_code
== NE
&& COMPARISON_P (cond
))
5234 /* Simplify the alternative arms; this may collapse the true and
5235 false arms to store-flag values. Be careful to use copy_rtx
5236 here since true_rtx or false_rtx might share RTL with x as a
5237 result of the if_then_else_cond call above. */
5238 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5239 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5241 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5242 is unlikely to be simpler. */
5243 if (general_operand (true_rtx
, VOIDmode
)
5244 && general_operand (false_rtx
, VOIDmode
))
5246 enum rtx_code reversed
;
5248 /* Restarting if we generate a store-flag expression will cause
5249 us to loop. Just drop through in this case. */
5251 /* If the result values are STORE_FLAG_VALUE and zero, we can
5252 just make the comparison operation. */
5253 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5254 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5256 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5257 && ((reversed
= reversed_comparison_code_parts
5258 (cond_code
, cond
, cop1
, NULL
))
5260 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5263 /* Likewise, we can make the negate of a comparison operation
5264 if the result values are - STORE_FLAG_VALUE and zero. */
5265 else if (CONST_INT_P (true_rtx
)
5266 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5267 && false_rtx
== const0_rtx
)
5268 x
= simplify_gen_unary (NEG
, mode
,
5269 simplify_gen_relational (cond_code
,
5273 else if (CONST_INT_P (false_rtx
)
5274 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5275 && true_rtx
== const0_rtx
5276 && ((reversed
= reversed_comparison_code_parts
5277 (cond_code
, cond
, cop1
, NULL
))
5279 x
= simplify_gen_unary (NEG
, mode
,
5280 simplify_gen_relational (reversed
,
5285 return gen_rtx_IF_THEN_ELSE (mode
,
5286 simplify_gen_relational (cond_code
,
5291 true_rtx
, false_rtx
);
5293 code
= GET_CODE (x
);
5294 op0_mode
= VOIDmode
;
5299 /* Try to fold this expression in case we have constants that weren't
5302 switch (GET_RTX_CLASS (code
))
5305 if (op0_mode
== VOIDmode
)
5306 op0_mode
= GET_MODE (XEXP (x
, 0));
5307 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5310 case RTX_COMM_COMPARE
:
5312 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5313 if (cmp_mode
== VOIDmode
)
5315 cmp_mode
= GET_MODE (XEXP (x
, 1));
5316 if (cmp_mode
== VOIDmode
)
5317 cmp_mode
= op0_mode
;
5319 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5320 XEXP (x
, 0), XEXP (x
, 1));
5323 case RTX_COMM_ARITH
:
5325 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5327 case RTX_BITFIELD_OPS
:
5329 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5330 XEXP (x
, 1), XEXP (x
, 2));
5339 code
= GET_CODE (temp
);
5340 op0_mode
= VOIDmode
;
5341 mode
= GET_MODE (temp
);
5344 /* First see if we can apply the inverse distributive law. */
5345 if (code
== PLUS
|| code
== MINUS
5346 || code
== AND
|| code
== IOR
|| code
== XOR
)
5348 x
= apply_distributive_law (x
);
5349 code
= GET_CODE (x
);
5350 op0_mode
= VOIDmode
;
5353 /* If CODE is an associative operation not otherwise handled, see if we
5354 can associate some operands. This can win if they are constants or
5355 if they are logically related (i.e. (a & b) & a). */
5356 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5357 || code
== AND
|| code
== IOR
|| code
== XOR
5358 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5359 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5360 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5362 if (GET_CODE (XEXP (x
, 0)) == code
)
5364 rtx other
= XEXP (XEXP (x
, 0), 0);
5365 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5366 rtx inner_op1
= XEXP (x
, 1);
5369 /* Make sure we pass the constant operand if any as the second
5370 one if this is a commutative operation. */
5371 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5373 rtx tem
= inner_op0
;
5374 inner_op0
= inner_op1
;
5377 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5378 : code
== DIV
? MULT
5380 mode
, inner_op0
, inner_op1
);
5382 /* For commutative operations, try the other pair if that one
5384 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5386 other
= XEXP (XEXP (x
, 0), 1);
5387 inner
= simplify_binary_operation (code
, mode
,
5388 XEXP (XEXP (x
, 0), 0),
5393 return simplify_gen_binary (code
, mode
, other
, inner
);
5397 /* A little bit of algebraic simplification here. */
5401 /* Ensure that our address has any ASHIFTs converted to MULT in case
5402 address-recognizing predicates are called later. */
5403 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5404 SUBST (XEXP (x
, 0), temp
);
5408 if (op0_mode
== VOIDmode
)
5409 op0_mode
= GET_MODE (SUBREG_REG (x
));
5411 /* See if this can be moved to simplify_subreg. */
5412 if (CONSTANT_P (SUBREG_REG (x
))
5413 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5414 /* Don't call gen_lowpart if the inner mode
5415 is VOIDmode and we cannot simplify it, as SUBREG without
5416 inner mode is invalid. */
5417 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5418 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5419 return gen_lowpart (mode
, SUBREG_REG (x
));
5421 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5425 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5430 /* If op is known to have all lower bits zero, the result is zero. */
5432 && SCALAR_INT_MODE_P (mode
)
5433 && SCALAR_INT_MODE_P (op0_mode
)
5434 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5435 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5436 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5437 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5438 & GET_MODE_MASK (mode
)) == 0)
5439 return CONST0_RTX (mode
);
5442 /* Don't change the mode of the MEM if that would change the meaning
5444 if (MEM_P (SUBREG_REG (x
))
5445 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5446 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5447 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5448 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5450 /* Note that we cannot do any narrowing for non-constants since
5451 we might have been counting on using the fact that some bits were
5452 zero. We now do this in the SET. */
5457 temp
= expand_compound_operation (XEXP (x
, 0));
5459 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5460 replaced by (lshiftrt X C). This will convert
5461 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5463 if (GET_CODE (temp
) == ASHIFTRT
5464 && CONST_INT_P (XEXP (temp
, 1))
5465 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5466 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5467 INTVAL (XEXP (temp
, 1)));
5469 /* If X has only a single bit that might be nonzero, say, bit I, convert
5470 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5471 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5472 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5473 or a SUBREG of one since we'd be making the expression more
5474 complex if it was just a register. */
5477 && ! (GET_CODE (temp
) == SUBREG
5478 && REG_P (SUBREG_REG (temp
)))
5479 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5481 rtx temp1
= simplify_shift_const
5482 (NULL_RTX
, ASHIFTRT
, mode
,
5483 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5484 GET_MODE_PRECISION (mode
) - 1 - i
),
5485 GET_MODE_PRECISION (mode
) - 1 - i
);
5487 /* If all we did was surround TEMP with the two shifts, we
5488 haven't improved anything, so don't use it. Otherwise,
5489 we are better off with TEMP1. */
5490 if (GET_CODE (temp1
) != ASHIFTRT
5491 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5492 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5498 /* We can't handle truncation to a partial integer mode here
5499 because we don't know the real bitsize of the partial
5501 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5504 if (HWI_COMPUTABLE_MODE_P (mode
))
5506 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5507 GET_MODE_MASK (mode
), 0));
5509 /* We can truncate a constant value and return it. */
5510 if (CONST_INT_P (XEXP (x
, 0)))
5511 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5513 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5514 whose value is a comparison can be replaced with a subreg if
5515 STORE_FLAG_VALUE permits. */
5516 if (HWI_COMPUTABLE_MODE_P (mode
)
5517 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5518 && (temp
= get_last_value (XEXP (x
, 0)))
5519 && COMPARISON_P (temp
))
5520 return gen_lowpart (mode
, XEXP (x
, 0));
5524 /* (const (const X)) can become (const X). Do it this way rather than
5525 returning the inner CONST since CONST can be shared with a
5527 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5528 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5533 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5534 can add in an offset. find_split_point will split this address up
5535 again if it doesn't match. */
5536 if (GET_CODE (XEXP (x
, 0)) == HIGH
5537 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5543 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5544 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5545 bit-field and can be replaced by either a sign_extend or a
5546 sign_extract. The `and' may be a zero_extend and the two
5547 <c>, -<c> constants may be reversed. */
5548 if (GET_CODE (XEXP (x
, 0)) == XOR
5549 && CONST_INT_P (XEXP (x
, 1))
5550 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5551 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5552 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5553 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5554 && HWI_COMPUTABLE_MODE_P (mode
)
5555 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5556 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5557 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5558 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5559 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5560 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5561 == (unsigned int) i
+ 1))))
5562 return simplify_shift_const
5563 (NULL_RTX
, ASHIFTRT
, mode
,
5564 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5565 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5566 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5567 GET_MODE_PRECISION (mode
) - (i
+ 1));
5569 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5570 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5571 the bitsize of the mode - 1. This allows simplification of
5572 "a = (b & 8) == 0;" */
5573 if (XEXP (x
, 1) == constm1_rtx
5574 && !REG_P (XEXP (x
, 0))
5575 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5576 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5577 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5578 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5579 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5580 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5581 GET_MODE_PRECISION (mode
) - 1),
5582 GET_MODE_PRECISION (mode
) - 1);
5584 /* If we are adding two things that have no bits in common, convert
5585 the addition into an IOR. This will often be further simplified,
5586 for example in cases like ((a & 1) + (a & 2)), which can
5589 if (HWI_COMPUTABLE_MODE_P (mode
)
5590 && (nonzero_bits (XEXP (x
, 0), mode
)
5591 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5593 /* Try to simplify the expression further. */
5594 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5595 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5597 /* If we could, great. If not, do not go ahead with the IOR
5598 replacement, since PLUS appears in many special purpose
5599 address arithmetic instructions. */
5600 if (GET_CODE (temp
) != CLOBBER
5601 && (GET_CODE (temp
) != IOR
5602 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5603 || XEXP (temp
, 1) != XEXP (x
, 1))
5604 && (XEXP (temp
, 0) != XEXP (x
, 1)
5605 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5611 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5612 (and <foo> (const_int pow2-1)) */
5613 if (GET_CODE (XEXP (x
, 1)) == AND
5614 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5615 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5616 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5617 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5618 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5622 /* If we have (mult (plus A B) C), apply the distributive law and then
5623 the inverse distributive law to see if things simplify. This
5624 occurs mostly in addresses, often when unrolling loops. */
5626 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5628 rtx result
= distribute_and_simplify_rtx (x
, 0);
5633 /* Try simplify a*(b/c) as (a*b)/c. */
5634 if (FLOAT_MODE_P (mode
) && flag_associative_math
5635 && GET_CODE (XEXP (x
, 0)) == DIV
)
5637 rtx tem
= simplify_binary_operation (MULT
, mode
,
5638 XEXP (XEXP (x
, 0), 0),
5641 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5646 /* If this is a divide by a power of two, treat it as a shift if
5647 its first operand is a shift. */
5648 if (CONST_INT_P (XEXP (x
, 1))
5649 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5650 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5651 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5652 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5653 || GET_CODE (XEXP (x
, 0)) == ROTATE
5654 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5655 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5659 case GT
: case GTU
: case GE
: case GEU
:
5660 case LT
: case LTU
: case LE
: case LEU
:
5661 case UNEQ
: case LTGT
:
5662 case UNGT
: case UNGE
:
5663 case UNLT
: case UNLE
:
5664 case UNORDERED
: case ORDERED
:
5665 /* If the first operand is a condition code, we can't do anything
5667 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5668 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5669 && ! CC0_P (XEXP (x
, 0))))
5671 rtx op0
= XEXP (x
, 0);
5672 rtx op1
= XEXP (x
, 1);
5673 enum rtx_code new_code
;
5675 if (GET_CODE (op0
) == COMPARE
)
5676 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5678 /* Simplify our comparison, if possible. */
5679 new_code
= simplify_comparison (code
, &op0
, &op1
);
5681 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5682 if only the low-order bit is possibly nonzero in X (such as when
5683 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5684 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5685 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5688 Remove any ZERO_EXTRACT we made when thinking this was a
5689 comparison. It may now be simpler to use, e.g., an AND. If a
5690 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5691 the call to make_compound_operation in the SET case.
5693 Don't apply these optimizations if the caller would
5694 prefer a comparison rather than a value.
5695 E.g., for the condition in an IF_THEN_ELSE most targets need
5696 an explicit comparison. */
5701 else if (STORE_FLAG_VALUE
== 1
5702 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5703 && op1
== const0_rtx
5704 && mode
== GET_MODE (op0
)
5705 && nonzero_bits (op0
, mode
) == 1)
5706 return gen_lowpart (mode
,
5707 expand_compound_operation (op0
));
5709 else if (STORE_FLAG_VALUE
== 1
5710 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5711 && op1
== const0_rtx
5712 && mode
== GET_MODE (op0
)
5713 && (num_sign_bit_copies (op0
, mode
)
5714 == GET_MODE_PRECISION (mode
)))
5716 op0
= expand_compound_operation (op0
);
5717 return simplify_gen_unary (NEG
, mode
,
5718 gen_lowpart (mode
, op0
),
5722 else if (STORE_FLAG_VALUE
== 1
5723 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5724 && op1
== const0_rtx
5725 && mode
== GET_MODE (op0
)
5726 && nonzero_bits (op0
, mode
) == 1)
5728 op0
= expand_compound_operation (op0
);
5729 return simplify_gen_binary (XOR
, mode
,
5730 gen_lowpart (mode
, op0
),
5734 else if (STORE_FLAG_VALUE
== 1
5735 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5736 && op1
== const0_rtx
5737 && mode
== GET_MODE (op0
)
5738 && (num_sign_bit_copies (op0
, mode
)
5739 == GET_MODE_PRECISION (mode
)))
5741 op0
= expand_compound_operation (op0
);
5742 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5745 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5750 else if (STORE_FLAG_VALUE
== -1
5751 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5752 && op1
== const0_rtx
5753 && (num_sign_bit_copies (op0
, mode
)
5754 == GET_MODE_PRECISION (mode
)))
5755 return gen_lowpart (mode
,
5756 expand_compound_operation (op0
));
5758 else if (STORE_FLAG_VALUE
== -1
5759 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5760 && op1
== const0_rtx
5761 && mode
== GET_MODE (op0
)
5762 && nonzero_bits (op0
, mode
) == 1)
5764 op0
= expand_compound_operation (op0
);
5765 return simplify_gen_unary (NEG
, mode
,
5766 gen_lowpart (mode
, op0
),
5770 else if (STORE_FLAG_VALUE
== -1
5771 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5772 && op1
== const0_rtx
5773 && mode
== GET_MODE (op0
)
5774 && (num_sign_bit_copies (op0
, mode
)
5775 == GET_MODE_PRECISION (mode
)))
5777 op0
= expand_compound_operation (op0
);
5778 return simplify_gen_unary (NOT
, mode
,
5779 gen_lowpart (mode
, op0
),
5783 /* If X is 0/1, (eq X 0) is X-1. */
5784 else if (STORE_FLAG_VALUE
== -1
5785 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5786 && op1
== const0_rtx
5787 && mode
== GET_MODE (op0
)
5788 && nonzero_bits (op0
, mode
) == 1)
5790 op0
= expand_compound_operation (op0
);
5791 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5794 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5795 one bit that might be nonzero, we can convert (ne x 0) to
5796 (ashift x c) where C puts the bit in the sign bit. Remove any
5797 AND with STORE_FLAG_VALUE when we are done, since we are only
5798 going to test the sign bit. */
5799 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5800 && HWI_COMPUTABLE_MODE_P (mode
)
5801 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5802 && op1
== const0_rtx
5803 && mode
== GET_MODE (op0
)
5804 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5806 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5807 expand_compound_operation (op0
),
5808 GET_MODE_PRECISION (mode
) - 1 - i
);
5809 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5815 /* If the code changed, return a whole new comparison.
5816 We also need to avoid using SUBST in cases where
5817 simplify_comparison has widened a comparison with a CONST_INT,
5818 since in that case the wider CONST_INT may fail the sanity
5819 checks in do_SUBST. */
5820 if (new_code
!= code
5821 || (CONST_INT_P (op1
)
5822 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
5823 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
5824 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5826 /* Otherwise, keep this operation, but maybe change its operands.
5827 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5828 SUBST (XEXP (x
, 0), op0
);
5829 SUBST (XEXP (x
, 1), op1
);
5834 return simplify_if_then_else (x
);
5840 /* If we are processing SET_DEST, we are done. */
5844 return expand_compound_operation (x
);
5847 return simplify_set (x
);
5851 return simplify_logical (x
);
5858 /* If this is a shift by a constant amount, simplify it. */
5859 if (CONST_INT_P (XEXP (x
, 1)))
5860 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5861 INTVAL (XEXP (x
, 1)));
5863 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5865 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5866 ((unsigned HOST_WIDE_INT
) 1
5867 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5879 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5882 simplify_if_then_else (rtx x
)
5884 enum machine_mode mode
= GET_MODE (x
);
5885 rtx cond
= XEXP (x
, 0);
5886 rtx true_rtx
= XEXP (x
, 1);
5887 rtx false_rtx
= XEXP (x
, 2);
5888 enum rtx_code true_code
= GET_CODE (cond
);
5889 int comparison_p
= COMPARISON_P (cond
);
5892 enum rtx_code false_code
;
5895 /* Simplify storing of the truth value. */
5896 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5897 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5898 XEXP (cond
, 0), XEXP (cond
, 1));
5900 /* Also when the truth value has to be reversed. */
5902 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5903 && (reversed
= reversed_comparison (cond
, mode
)))
5906 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5907 in it is being compared against certain values. Get the true and false
5908 comparisons and see if that says anything about the value of each arm. */
5911 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5913 && REG_P (XEXP (cond
, 0)))
5916 rtx from
= XEXP (cond
, 0);
5917 rtx true_val
= XEXP (cond
, 1);
5918 rtx false_val
= true_val
;
5921 /* If FALSE_CODE is EQ, swap the codes and arms. */
5923 if (false_code
== EQ
)
5925 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5926 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5929 /* If we are comparing against zero and the expression being tested has
5930 only a single bit that might be nonzero, that is its value when it is
5931 not equal to zero. Similarly if it is known to be -1 or 0. */
5933 if (true_code
== EQ
&& true_val
== const0_rtx
5934 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5937 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
5939 else if (true_code
== EQ
&& true_val
== const0_rtx
5940 && (num_sign_bit_copies (from
, GET_MODE (from
))
5941 == GET_MODE_PRECISION (GET_MODE (from
))))
5944 false_val
= constm1_rtx
;
5947 /* Now simplify an arm if we know the value of the register in the
5948 branch and it is used in the arm. Be careful due to the potential
5949 of locally-shared RTL. */
5951 if (reg_mentioned_p (from
, true_rtx
))
5952 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5954 pc_rtx
, pc_rtx
, 0, 0, 0);
5955 if (reg_mentioned_p (from
, false_rtx
))
5956 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5958 pc_rtx
, pc_rtx
, 0, 0, 0);
5960 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5961 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5963 true_rtx
= XEXP (x
, 1);
5964 false_rtx
= XEXP (x
, 2);
5965 true_code
= GET_CODE (cond
);
5968 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5969 reversed, do so to avoid needing two sets of patterns for
5970 subtract-and-branch insns. Similarly if we have a constant in the true
5971 arm, the false arm is the same as the first operand of the comparison, or
5972 the false arm is more complicated than the true arm. */
5975 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5976 && (true_rtx
== pc_rtx
5977 || (CONSTANT_P (true_rtx
)
5978 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5979 || true_rtx
== const0_rtx
5980 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5981 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5982 && !OBJECT_P (false_rtx
))
5983 || reg_mentioned_p (true_rtx
, false_rtx
)
5984 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5986 true_code
= reversed_comparison_code (cond
, NULL
);
5987 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5988 SUBST (XEXP (x
, 1), false_rtx
);
5989 SUBST (XEXP (x
, 2), true_rtx
);
5991 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5994 /* It is possible that the conditional has been simplified out. */
5995 true_code
= GET_CODE (cond
);
5996 comparison_p
= COMPARISON_P (cond
);
5999 /* If the two arms are identical, we don't need the comparison. */
6001 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6004 /* Convert a == b ? b : a to "a". */
6005 if (true_code
== EQ
&& ! side_effects_p (cond
)
6006 && !HONOR_NANS (mode
)
6007 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6008 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6010 else if (true_code
== NE
&& ! side_effects_p (cond
)
6011 && !HONOR_NANS (mode
)
6012 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6013 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6016 /* Look for cases where we have (abs x) or (neg (abs X)). */
6018 if (GET_MODE_CLASS (mode
) == MODE_INT
6020 && XEXP (cond
, 1) == const0_rtx
6021 && GET_CODE (false_rtx
) == NEG
6022 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6023 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6024 && ! side_effects_p (true_rtx
))
6029 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6033 simplify_gen_unary (NEG
, mode
,
6034 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6040 /* Look for MIN or MAX. */
6042 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6044 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6045 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6046 && ! side_effects_p (cond
))
6051 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6054 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6057 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6060 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6065 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6066 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6067 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6068 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6069 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6070 neither 1 or -1, but it isn't worth checking for. */
6072 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6074 && GET_MODE_CLASS (mode
) == MODE_INT
6075 && ! side_effects_p (x
))
6077 rtx t
= make_compound_operation (true_rtx
, SET
);
6078 rtx f
= make_compound_operation (false_rtx
, SET
);
6079 rtx cond_op0
= XEXP (cond
, 0);
6080 rtx cond_op1
= XEXP (cond
, 1);
6081 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6082 enum machine_mode m
= mode
;
6083 rtx z
= 0, c1
= NULL_RTX
;
6085 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6086 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6087 || GET_CODE (t
) == ASHIFT
6088 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6089 && rtx_equal_p (XEXP (t
, 0), f
))
6090 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6092 /* If an identity-zero op is commutative, check whether there
6093 would be a match if we swapped the operands. */
6094 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6095 || GET_CODE (t
) == XOR
)
6096 && rtx_equal_p (XEXP (t
, 1), f
))
6097 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6098 else if (GET_CODE (t
) == SIGN_EXTEND
6099 && (GET_CODE (XEXP (t
, 0)) == PLUS
6100 || GET_CODE (XEXP (t
, 0)) == MINUS
6101 || GET_CODE (XEXP (t
, 0)) == IOR
6102 || GET_CODE (XEXP (t
, 0)) == XOR
6103 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6104 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6105 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6106 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6107 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6108 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6109 && (num_sign_bit_copies (f
, GET_MODE (f
))
6111 (GET_MODE_PRECISION (mode
)
6112 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6114 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6115 extend_op
= SIGN_EXTEND
;
6116 m
= GET_MODE (XEXP (t
, 0));
6118 else if (GET_CODE (t
) == SIGN_EXTEND
6119 && (GET_CODE (XEXP (t
, 0)) == PLUS
6120 || GET_CODE (XEXP (t
, 0)) == IOR
6121 || GET_CODE (XEXP (t
, 0)) == XOR
)
6122 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6123 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6124 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6125 && (num_sign_bit_copies (f
, GET_MODE (f
))
6127 (GET_MODE_PRECISION (mode
)
6128 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6130 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6131 extend_op
= SIGN_EXTEND
;
6132 m
= GET_MODE (XEXP (t
, 0));
6134 else if (GET_CODE (t
) == ZERO_EXTEND
6135 && (GET_CODE (XEXP (t
, 0)) == PLUS
6136 || GET_CODE (XEXP (t
, 0)) == MINUS
6137 || GET_CODE (XEXP (t
, 0)) == IOR
6138 || GET_CODE (XEXP (t
, 0)) == XOR
6139 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6140 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6141 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6142 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6143 && HWI_COMPUTABLE_MODE_P (mode
)
6144 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6145 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6146 && ((nonzero_bits (f
, GET_MODE (f
))
6147 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6150 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6151 extend_op
= ZERO_EXTEND
;
6152 m
= GET_MODE (XEXP (t
, 0));
6154 else if (GET_CODE (t
) == ZERO_EXTEND
6155 && (GET_CODE (XEXP (t
, 0)) == PLUS
6156 || GET_CODE (XEXP (t
, 0)) == IOR
6157 || GET_CODE (XEXP (t
, 0)) == XOR
)
6158 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6159 && HWI_COMPUTABLE_MODE_P (mode
)
6160 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6161 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6162 && ((nonzero_bits (f
, GET_MODE (f
))
6163 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6166 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6167 extend_op
= ZERO_EXTEND
;
6168 m
= GET_MODE (XEXP (t
, 0));
6173 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6174 cond_op0
, cond_op1
),
6175 pc_rtx
, pc_rtx
, 0, 0, 0);
6176 temp
= simplify_gen_binary (MULT
, m
, temp
,
6177 simplify_gen_binary (MULT
, m
, c1
,
6179 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6180 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6182 if (extend_op
!= UNKNOWN
)
6183 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6189 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6190 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6191 negation of a single bit, we can convert this operation to a shift. We
6192 can actually do this more generally, but it doesn't seem worth it. */
6194 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6195 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6196 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6197 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6198 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6199 == GET_MODE_PRECISION (mode
))
6200 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6202 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6203 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6205 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6206 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6207 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6208 && GET_MODE (XEXP (cond
, 0)) == mode
6209 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6210 == nonzero_bits (XEXP (cond
, 0), mode
)
6211 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6212 return XEXP (cond
, 0);
6217 /* Simplify X, a SET expression. Return the new expression. */
6220 simplify_set (rtx x
)
6222 rtx src
= SET_SRC (x
);
6223 rtx dest
= SET_DEST (x
);
6224 enum machine_mode mode
6225 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6229 /* (set (pc) (return)) gets written as (return). */
6230 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6233 /* Now that we know for sure which bits of SRC we are using, see if we can
6234 simplify the expression for the object knowing that we only need the
6237 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6239 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6240 SUBST (SET_SRC (x
), src
);
6243 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6244 the comparison result and try to simplify it unless we already have used
6245 undobuf.other_insn. */
6246 if ((GET_MODE_CLASS (mode
) == MODE_CC
6247 || GET_CODE (src
) == COMPARE
6249 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6250 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6251 && COMPARISON_P (*cc_use
)
6252 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6254 enum rtx_code old_code
= GET_CODE (*cc_use
);
6255 enum rtx_code new_code
;
6257 int other_changed
= 0;
6258 rtx inner_compare
= NULL_RTX
;
6259 enum machine_mode compare_mode
= GET_MODE (dest
);
6261 if (GET_CODE (src
) == COMPARE
)
6263 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6264 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6266 inner_compare
= op0
;
6267 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6271 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6273 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6276 new_code
= old_code
;
6277 else if (!CONSTANT_P (tmp
))
6279 new_code
= GET_CODE (tmp
);
6280 op0
= XEXP (tmp
, 0);
6281 op1
= XEXP (tmp
, 1);
6285 rtx pat
= PATTERN (other_insn
);
6286 undobuf
.other_insn
= other_insn
;
6287 SUBST (*cc_use
, tmp
);
6289 /* Attempt to simplify CC user. */
6290 if (GET_CODE (pat
) == SET
)
6292 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6293 if (new_rtx
!= NULL_RTX
)
6294 SUBST (SET_SRC (pat
), new_rtx
);
6297 /* Convert X into a no-op move. */
6298 SUBST (SET_DEST (x
), pc_rtx
);
6299 SUBST (SET_SRC (x
), pc_rtx
);
6303 /* Simplify our comparison, if possible. */
6304 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6306 #ifdef SELECT_CC_MODE
6307 /* If this machine has CC modes other than CCmode, check to see if we
6308 need to use a different CC mode here. */
6309 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6310 compare_mode
= GET_MODE (op0
);
6311 else if (inner_compare
6312 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6313 && new_code
== old_code
6314 && op0
== XEXP (inner_compare
, 0)
6315 && op1
== XEXP (inner_compare
, 1))
6316 compare_mode
= GET_MODE (inner_compare
);
6318 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6321 /* If the mode changed, we have to change SET_DEST, the mode in the
6322 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6323 a hard register, just build new versions with the proper mode. If it
6324 is a pseudo, we lose unless it is only time we set the pseudo, in
6325 which case we can safely change its mode. */
6326 if (compare_mode
!= GET_MODE (dest
))
6328 if (can_change_dest_mode (dest
, 0, compare_mode
))
6330 unsigned int regno
= REGNO (dest
);
6333 if (regno
< FIRST_PSEUDO_REGISTER
)
6334 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6337 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6338 new_dest
= regno_reg_rtx
[regno
];
6341 SUBST (SET_DEST (x
), new_dest
);
6342 SUBST (XEXP (*cc_use
, 0), new_dest
);
6349 #endif /* SELECT_CC_MODE */
6351 /* If the code changed, we have to build a new comparison in
6352 undobuf.other_insn. */
6353 if (new_code
!= old_code
)
6355 int other_changed_previously
= other_changed
;
6356 unsigned HOST_WIDE_INT mask
;
6357 rtx old_cc_use
= *cc_use
;
6359 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6363 /* If the only change we made was to change an EQ into an NE or
6364 vice versa, OP0 has only one bit that might be nonzero, and OP1
6365 is zero, check if changing the user of the condition code will
6366 produce a valid insn. If it won't, we can keep the original code
6367 in that insn by surrounding our operation with an XOR. */
6369 if (((old_code
== NE
&& new_code
== EQ
)
6370 || (old_code
== EQ
&& new_code
== NE
))
6371 && ! other_changed_previously
&& op1
== const0_rtx
6372 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6373 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6375 rtx pat
= PATTERN (other_insn
), note
= 0;
6377 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6378 && ! check_asm_operands (pat
)))
6380 *cc_use
= old_cc_use
;
6383 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6391 undobuf
.other_insn
= other_insn
;
6393 /* Otherwise, if we didn't previously have a COMPARE in the
6394 correct mode, we need one. */
6395 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6397 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6400 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6402 SUBST (SET_SRC (x
), op0
);
6405 /* Otherwise, update the COMPARE if needed. */
6406 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6408 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6414 /* Get SET_SRC in a form where we have placed back any
6415 compound expressions. Then do the checks below. */
6416 src
= make_compound_operation (src
, SET
);
6417 SUBST (SET_SRC (x
), src
);
6420 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6421 and X being a REG or (subreg (reg)), we may be able to convert this to
6422 (set (subreg:m2 x) (op)).
6424 We can always do this if M1 is narrower than M2 because that means that
6425 we only care about the low bits of the result.
6427 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6428 perform a narrower operation than requested since the high-order bits will
6429 be undefined. On machine where it is defined, this transformation is safe
6430 as long as M1 and M2 have the same number of words. */
6432 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6433 && !OBJECT_P (SUBREG_REG (src
))
6434 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6436 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6437 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6438 #ifndef WORD_REGISTER_OPERATIONS
6439 && (GET_MODE_SIZE (GET_MODE (src
))
6440 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6442 #ifdef CANNOT_CHANGE_MODE_CLASS
6443 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6444 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6445 GET_MODE (SUBREG_REG (src
)),
6449 || (GET_CODE (dest
) == SUBREG
6450 && REG_P (SUBREG_REG (dest
)))))
6452 SUBST (SET_DEST (x
),
6453 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6455 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6457 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6461 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6464 && GET_CODE (src
) == SUBREG
6465 && subreg_lowpart_p (src
)
6466 && (GET_MODE_PRECISION (GET_MODE (src
))
6467 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6469 rtx inner
= SUBREG_REG (src
);
6470 enum machine_mode inner_mode
= GET_MODE (inner
);
6472 /* Here we make sure that we don't have a sign bit on. */
6473 if (val_signbit_known_clear_p (GET_MODE (src
),
6474 nonzero_bits (inner
, inner_mode
)))
6476 SUBST (SET_SRC (x
), inner
);
6482 #ifdef LOAD_EXTEND_OP
6483 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6484 would require a paradoxical subreg. Replace the subreg with a
6485 zero_extend to avoid the reload that would otherwise be required. */
6487 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6488 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6489 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6490 && SUBREG_BYTE (src
) == 0
6491 && paradoxical_subreg_p (src
)
6492 && MEM_P (SUBREG_REG (src
)))
6495 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6496 GET_MODE (src
), SUBREG_REG (src
)));
6502 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6503 are comparing an item known to be 0 or -1 against 0, use a logical
6504 operation instead. Check for one of the arms being an IOR of the other
6505 arm with some value. We compute three terms to be IOR'ed together. In
6506 practice, at most two will be nonzero. Then we do the IOR's. */
6508 if (GET_CODE (dest
) != PC
6509 && GET_CODE (src
) == IF_THEN_ELSE
6510 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6511 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6512 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6513 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6514 #ifdef HAVE_conditional_move
6515 && ! can_conditionally_move_p (GET_MODE (src
))
6517 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6518 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6519 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6520 && ! side_effects_p (src
))
6522 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6523 ? XEXP (src
, 1) : XEXP (src
, 2));
6524 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6525 ? XEXP (src
, 2) : XEXP (src
, 1));
6526 rtx term1
= const0_rtx
, term2
, term3
;
6528 if (GET_CODE (true_rtx
) == IOR
6529 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6530 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6531 else if (GET_CODE (true_rtx
) == IOR
6532 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6533 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6534 else if (GET_CODE (false_rtx
) == IOR
6535 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6536 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6537 else if (GET_CODE (false_rtx
) == IOR
6538 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6539 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6541 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6542 XEXP (XEXP (src
, 0), 0), true_rtx
);
6543 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6544 simplify_gen_unary (NOT
, GET_MODE (src
),
6545 XEXP (XEXP (src
, 0), 0),
6550 simplify_gen_binary (IOR
, GET_MODE (src
),
6551 simplify_gen_binary (IOR
, GET_MODE (src
),
6558 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6559 whole thing fail. */
6560 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6562 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6565 /* Convert this into a field assignment operation, if possible. */
6566 return make_field_assignment (x
);
6569 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6573 simplify_logical (rtx x
)
6575 enum machine_mode mode
= GET_MODE (x
);
6576 rtx op0
= XEXP (x
, 0);
6577 rtx op1
= XEXP (x
, 1);
6579 switch (GET_CODE (x
))
6582 /* We can call simplify_and_const_int only if we don't lose
6583 any (sign) bits when converting INTVAL (op1) to
6584 "unsigned HOST_WIDE_INT". */
6585 if (CONST_INT_P (op1
)
6586 && (HWI_COMPUTABLE_MODE_P (mode
)
6587 || INTVAL (op1
) > 0))
6589 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6590 if (GET_CODE (x
) != AND
)
6597 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6598 apply the distributive law and then the inverse distributive
6599 law to see if things simplify. */
6600 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6602 rtx result
= distribute_and_simplify_rtx (x
, 0);
6606 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6608 rtx result
= distribute_and_simplify_rtx (x
, 1);
6615 /* If we have (ior (and A B) C), apply the distributive law and then
6616 the inverse distributive law to see if things simplify. */
6618 if (GET_CODE (op0
) == AND
)
6620 rtx result
= distribute_and_simplify_rtx (x
, 0);
6625 if (GET_CODE (op1
) == AND
)
6627 rtx result
= distribute_and_simplify_rtx (x
, 1);
6640 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6641 operations" because they can be replaced with two more basic operations.
6642 ZERO_EXTEND is also considered "compound" because it can be replaced with
6643 an AND operation, which is simpler, though only one operation.
6645 The function expand_compound_operation is called with an rtx expression
6646 and will convert it to the appropriate shifts and AND operations,
6647 simplifying at each stage.
6649 The function make_compound_operation is called to convert an expression
6650 consisting of shifts and ANDs into the equivalent compound expression.
6651 It is the inverse of this function, loosely speaking. */
6654 expand_compound_operation (rtx x
)
6656 unsigned HOST_WIDE_INT pos
= 0, len
;
6658 unsigned int modewidth
;
6661 switch (GET_CODE (x
))
6666 /* We can't necessarily use a const_int for a multiword mode;
6667 it depends on implicitly extending the value.
6668 Since we don't know the right way to extend it,
6669 we can't tell whether the implicit way is right.
6671 Even for a mode that is no wider than a const_int,
6672 we can't win, because we need to sign extend one of its bits through
6673 the rest of it, and we don't know which bit. */
6674 if (CONST_INT_P (XEXP (x
, 0)))
6677 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6678 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6679 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6680 reloaded. If not for that, MEM's would very rarely be safe.
6682 Reject MODEs bigger than a word, because we might not be able
6683 to reference a two-register group starting with an arbitrary register
6684 (and currently gen_lowpart might crash for a SUBREG). */
6686 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6689 /* Reject MODEs that aren't scalar integers because turning vector
6690 or complex modes into shifts causes problems. */
6692 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6695 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6696 /* If the inner object has VOIDmode (the only way this can happen
6697 is if it is an ASM_OPERANDS), we can't do anything since we don't
6698 know how much masking to do. */
6707 /* ... fall through ... */
6710 /* If the operand is a CLOBBER, just return it. */
6711 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6714 if (!CONST_INT_P (XEXP (x
, 1))
6715 || !CONST_INT_P (XEXP (x
, 2))
6716 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6719 /* Reject MODEs that aren't scalar integers because turning vector
6720 or complex modes into shifts causes problems. */
6722 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6725 len
= INTVAL (XEXP (x
, 1));
6726 pos
= INTVAL (XEXP (x
, 2));
6728 /* This should stay within the object being extracted, fail otherwise. */
6729 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6732 if (BITS_BIG_ENDIAN
)
6733 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6740 /* Convert sign extension to zero extension, if we know that the high
6741 bit is not set, as this is easier to optimize. It will be converted
6742 back to cheaper alternative in make_extraction. */
6743 if (GET_CODE (x
) == SIGN_EXTEND
6744 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6745 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6746 & ~(((unsigned HOST_WIDE_INT
)
6747 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6751 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6752 rtx temp2
= expand_compound_operation (temp
);
6754 /* Make sure this is a profitable operation. */
6755 if (set_src_cost (x
, optimize_this_for_speed_p
)
6756 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6758 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6759 > set_src_cost (temp
, optimize_this_for_speed_p
))
6765 /* We can optimize some special cases of ZERO_EXTEND. */
6766 if (GET_CODE (x
) == ZERO_EXTEND
)
6768 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6769 know that the last value didn't have any inappropriate bits
6771 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6772 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6773 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6774 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6775 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6776 return XEXP (XEXP (x
, 0), 0);
6778 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6779 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6780 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6781 && subreg_lowpart_p (XEXP (x
, 0))
6782 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6783 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6784 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6785 return SUBREG_REG (XEXP (x
, 0));
6787 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6788 is a comparison and STORE_FLAG_VALUE permits. This is like
6789 the first case, but it works even when GET_MODE (x) is larger
6790 than HOST_WIDE_INT. */
6791 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6792 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6793 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6794 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6795 <= HOST_BITS_PER_WIDE_INT
)
6796 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6797 return XEXP (XEXP (x
, 0), 0);
6799 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6800 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6801 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6802 && subreg_lowpart_p (XEXP (x
, 0))
6803 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6804 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6805 <= HOST_BITS_PER_WIDE_INT
)
6806 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6807 return SUBREG_REG (XEXP (x
, 0));
6811 /* If we reach here, we want to return a pair of shifts. The inner
6812 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6813 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6814 logical depending on the value of UNSIGNEDP.
6816 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6817 converted into an AND of a shift.
6819 We must check for the case where the left shift would have a negative
6820 count. This can happen in a case like (x >> 31) & 255 on machines
6821 that can't shift by a constant. On those machines, we would first
6822 combine the shift with the AND to produce a variable-position
6823 extraction. Then the constant of 31 would be substituted in
6824 to produce such a position. */
6826 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6827 if (modewidth
>= pos
+ len
)
6829 enum machine_mode mode
= GET_MODE (x
);
6830 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6831 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6833 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6834 tem
, modewidth
- pos
- len
);
6835 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6836 mode
, tem
, modewidth
- len
);
6838 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6839 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6840 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6843 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6845 /* Any other cases we can't handle. */
6848 /* If we couldn't do this for some reason, return the original
6850 if (GET_CODE (tem
) == CLOBBER
)
6856 /* X is a SET which contains an assignment of one object into
6857 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6858 or certain SUBREGS). If possible, convert it into a series of
6861 We half-heartedly support variable positions, but do not at all
6862 support variable lengths. */
6865 expand_field_assignment (const_rtx x
)
6868 rtx pos
; /* Always counts from low bit. */
6870 rtx mask
, cleared
, masked
;
6871 enum machine_mode compute_mode
;
6873 /* Loop until we find something we can't simplify. */
6876 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6877 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6879 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6880 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6881 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6883 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6884 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6886 inner
= XEXP (SET_DEST (x
), 0);
6887 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6888 pos
= XEXP (SET_DEST (x
), 2);
6890 /* A constant position should stay within the width of INNER. */
6891 if (CONST_INT_P (pos
)
6892 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6895 if (BITS_BIG_ENDIAN
)
6897 if (CONST_INT_P (pos
))
6898 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6900 else if (GET_CODE (pos
) == MINUS
6901 && CONST_INT_P (XEXP (pos
, 1))
6902 && (INTVAL (XEXP (pos
, 1))
6903 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6904 /* If position is ADJUST - X, new position is X. */
6905 pos
= XEXP (pos
, 0);
6908 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
6909 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6910 gen_int_mode (prec
- len
,
6917 /* A SUBREG between two modes that occupy the same numbers of words
6918 can be done by moving the SUBREG to the source. */
6919 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6920 /* We need SUBREGs to compute nonzero_bits properly. */
6921 && nonzero_sign_valid
6922 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6923 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6924 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6925 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6927 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6929 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6936 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6937 inner
= SUBREG_REG (inner
);
6939 compute_mode
= GET_MODE (inner
);
6941 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6942 if (! SCALAR_INT_MODE_P (compute_mode
))
6944 enum machine_mode imode
;
6946 /* Don't do anything for vector or complex integral types. */
6947 if (! FLOAT_MODE_P (compute_mode
))
6950 /* Try to find an integral mode to pun with. */
6951 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6952 if (imode
== BLKmode
)
6955 compute_mode
= imode
;
6956 inner
= gen_lowpart (imode
, inner
);
6959 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6960 if (len
>= HOST_BITS_PER_WIDE_INT
)
6963 /* Now compute the equivalent expression. Make a copy of INNER
6964 for the SET_DEST in case it is a MEM into which we will substitute;
6965 we don't want shared RTL in that case. */
6966 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6968 cleared
= simplify_gen_binary (AND
, compute_mode
,
6969 simplify_gen_unary (NOT
, compute_mode
,
6970 simplify_gen_binary (ASHIFT
,
6975 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6976 simplify_gen_binary (
6978 gen_lowpart (compute_mode
, SET_SRC (x
)),
6982 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6983 simplify_gen_binary (IOR
, compute_mode
,
6990 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6991 it is an RTX that represents the (variable) starting position; otherwise,
6992 POS is the (constant) starting bit position. Both are counted from the LSB.
6994 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6996 IN_DEST is nonzero if this is a reference in the destination of a SET.
6997 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6998 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7001 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7002 ZERO_EXTRACT should be built even for bits starting at bit 0.
7004 MODE is the desired mode of the result (if IN_DEST == 0).
7006 The result is an RTX for the extraction or NULL_RTX if the target
7010 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7011 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7012 int in_dest
, int in_compare
)
7014 /* This mode describes the size of the storage area
7015 to fetch the overall value from. Within that, we
7016 ignore the POS lowest bits, etc. */
7017 enum machine_mode is_mode
= GET_MODE (inner
);
7018 enum machine_mode inner_mode
;
7019 enum machine_mode wanted_inner_mode
;
7020 enum machine_mode wanted_inner_reg_mode
= word_mode
;
7021 enum machine_mode pos_mode
= word_mode
;
7022 enum machine_mode extraction_mode
= word_mode
;
7023 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7025 rtx orig_pos_rtx
= pos_rtx
;
7026 HOST_WIDE_INT orig_pos
;
7028 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7029 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7031 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7033 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7034 consider just the QI as the memory to extract from.
7035 The subreg adds or removes high bits; its mode is
7036 irrelevant to the meaning of this extraction,
7037 since POS and LEN count from the lsb. */
7038 if (MEM_P (SUBREG_REG (inner
)))
7039 is_mode
= GET_MODE (SUBREG_REG (inner
));
7040 inner
= SUBREG_REG (inner
);
7042 else if (GET_CODE (inner
) == ASHIFT
7043 && CONST_INT_P (XEXP (inner
, 1))
7044 && pos_rtx
== 0 && pos
== 0
7045 && len
> UINTVAL (XEXP (inner
, 1)))
7047 /* We're extracting the least significant bits of an rtx
7048 (ashift X (const_int C)), where LEN > C. Extract the
7049 least significant (LEN - C) bits of X, giving an rtx
7050 whose mode is MODE, then shift it left C times. */
7051 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7052 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7053 unsignedp
, in_dest
, in_compare
);
7055 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7057 else if (GET_CODE (inner
) == TRUNCATE
)
7058 inner
= XEXP (inner
, 0);
7060 inner_mode
= GET_MODE (inner
);
7062 /* See if this can be done without an extraction. We never can if the
7063 width of the field is not the same as that of some integer mode. For
7064 registers, we can only avoid the extraction if the position is at the
7065 low-order bit and this is either not in the destination or we have the
7066 appropriate STRICT_LOW_PART operation available.
7068 For MEM, we can avoid an extract if the field starts on an appropriate
7069 boundary and we can change the mode of the memory reference. */
7071 if (tmode
!= BLKmode
7072 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7074 && (inner_mode
== tmode
7076 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7077 || reg_truncated_to_mode (tmode
, inner
))
7080 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7081 || (MEM_P (inner
) && pos_rtx
== 0
7083 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7084 : BITS_PER_UNIT
)) == 0
7085 /* We can't do this if we are widening INNER_MODE (it
7086 may not be aligned, for one thing). */
7087 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7088 && (inner_mode
== tmode
7089 || (! mode_dependent_address_p (XEXP (inner
, 0),
7090 MEM_ADDR_SPACE (inner
))
7091 && ! MEM_VOLATILE_P (inner
))))))
7093 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7094 field. If the original and current mode are the same, we need not
7095 adjust the offset. Otherwise, we do if bytes big endian.
7097 If INNER is not a MEM, get a piece consisting of just the field
7098 of interest (in this case POS % BITS_PER_WORD must be 0). */
7102 HOST_WIDE_INT offset
;
7104 /* POS counts from lsb, but make OFFSET count in memory order. */
7105 if (BYTES_BIG_ENDIAN
)
7106 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7108 offset
= pos
/ BITS_PER_UNIT
;
7110 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7112 else if (REG_P (inner
))
7114 if (tmode
!= inner_mode
)
7116 /* We can't call gen_lowpart in a DEST since we
7117 always want a SUBREG (see below) and it would sometimes
7118 return a new hard register. */
7121 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7123 if (WORDS_BIG_ENDIAN
7124 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7125 final_word
= ((GET_MODE_SIZE (inner_mode
)
7126 - GET_MODE_SIZE (tmode
))
7127 / UNITS_PER_WORD
) - final_word
;
7129 final_word
*= UNITS_PER_WORD
;
7130 if (BYTES_BIG_ENDIAN
&&
7131 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7132 final_word
+= (GET_MODE_SIZE (inner_mode
)
7133 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7135 /* Avoid creating invalid subregs, for example when
7136 simplifying (x>>32)&255. */
7137 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7140 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7143 new_rtx
= gen_lowpart (tmode
, inner
);
7149 new_rtx
= force_to_mode (inner
, tmode
,
7150 len
>= HOST_BITS_PER_WIDE_INT
7151 ? ~(unsigned HOST_WIDE_INT
) 0
7152 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7155 /* If this extraction is going into the destination of a SET,
7156 make a STRICT_LOW_PART unless we made a MEM. */
7159 return (MEM_P (new_rtx
) ? new_rtx
7160 : (GET_CODE (new_rtx
) != SUBREG
7161 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7162 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7167 if (CONST_SCALAR_INT_P (new_rtx
))
7168 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7169 mode
, new_rtx
, tmode
);
7171 /* If we know that no extraneous bits are set, and that the high
7172 bit is not set, convert the extraction to the cheaper of
7173 sign and zero extension, that are equivalent in these cases. */
7174 if (flag_expensive_optimizations
7175 && (HWI_COMPUTABLE_MODE_P (tmode
)
7176 && ((nonzero_bits (new_rtx
, tmode
)
7177 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7180 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7181 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7183 /* Prefer ZERO_EXTENSION, since it gives more information to
7185 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7186 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7191 /* Otherwise, sign- or zero-extend unless we already are in the
7194 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7198 /* Unless this is a COMPARE or we have a funny memory reference,
7199 don't do anything with zero-extending field extracts starting at
7200 the low-order bit since they are simple AND operations. */
7201 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7202 && ! in_compare
&& unsignedp
)
7205 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7206 if the position is not a constant and the length is not 1. In all
7207 other cases, we would only be going outside our object in cases when
7208 an original shift would have been undefined. */
7210 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7211 || (pos_rtx
!= 0 && len
!= 1)))
7214 enum extraction_pattern pattern
= (in_dest
? EP_insv
7215 : unsignedp
? EP_extzv
: EP_extv
);
7217 /* If INNER is not from memory, we want it to have the mode of a register
7218 extraction pattern's structure operand, or word_mode if there is no
7219 such pattern. The same applies to extraction_mode and pos_mode
7220 and their respective operands.
7222 For memory, assume that the desired extraction_mode and pos_mode
7223 are the same as for a register operation, since at present we don't
7224 have named patterns for aligned memory structures. */
7225 struct extraction_insn insn
;
7226 if (get_best_reg_extraction_insn (&insn
, pattern
,
7227 GET_MODE_BITSIZE (inner_mode
), mode
))
7229 wanted_inner_reg_mode
= insn
.struct_mode
;
7230 pos_mode
= insn
.pos_mode
;
7231 extraction_mode
= insn
.field_mode
;
7234 /* Never narrow an object, since that might not be safe. */
7236 if (mode
!= VOIDmode
7237 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7238 extraction_mode
= mode
;
7241 wanted_inner_mode
= wanted_inner_reg_mode
;
7244 /* Be careful not to go beyond the extracted object and maintain the
7245 natural alignment of the memory. */
7246 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7247 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7248 > GET_MODE_BITSIZE (wanted_inner_mode
))
7250 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7251 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7257 if (BITS_BIG_ENDIAN
)
7259 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7260 BITS_BIG_ENDIAN style. If position is constant, compute new
7261 position. Otherwise, build subtraction.
7262 Note that POS is relative to the mode of the original argument.
7263 If it's a MEM we need to recompute POS relative to that.
7264 However, if we're extracting from (or inserting into) a register,
7265 we want to recompute POS relative to wanted_inner_mode. */
7266 int width
= (MEM_P (inner
)
7267 ? GET_MODE_BITSIZE (is_mode
)
7268 : GET_MODE_BITSIZE (wanted_inner_mode
));
7271 pos
= width
- len
- pos
;
7274 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7275 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7277 /* POS may be less than 0 now, but we check for that below.
7278 Note that it can only be less than 0 if !MEM_P (inner). */
7281 /* If INNER has a wider mode, and this is a constant extraction, try to
7282 make it smaller and adjust the byte to point to the byte containing
7284 if (wanted_inner_mode
!= VOIDmode
7285 && inner_mode
!= wanted_inner_mode
7287 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7289 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7290 && ! MEM_VOLATILE_P (inner
))
7294 /* The computations below will be correct if the machine is big
7295 endian in both bits and bytes or little endian in bits and bytes.
7296 If it is mixed, we must adjust. */
7298 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7299 adjust OFFSET to compensate. */
7300 if (BYTES_BIG_ENDIAN
7301 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7302 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7304 /* We can now move to the desired byte. */
7305 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7306 * GET_MODE_SIZE (wanted_inner_mode
);
7307 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7309 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7310 && is_mode
!= wanted_inner_mode
)
7311 offset
= (GET_MODE_SIZE (is_mode
)
7312 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7314 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7317 /* If INNER is not memory, get it into the proper mode. If we are changing
7318 its mode, POS must be a constant and smaller than the size of the new
7320 else if (!MEM_P (inner
))
7322 /* On the LHS, don't create paradoxical subregs implicitely truncating
7323 the register unless TRULY_NOOP_TRUNCATION. */
7325 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7329 if (GET_MODE (inner
) != wanted_inner_mode
7331 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7337 inner
= force_to_mode (inner
, wanted_inner_mode
,
7339 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7340 ? ~(unsigned HOST_WIDE_INT
) 0
7341 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7346 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7347 have to zero extend. Otherwise, we can just use a SUBREG. */
7349 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7351 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7352 GET_MODE (pos_rtx
));
7354 /* If we know that no extraneous bits are set, and that the high
7355 bit is not set, convert extraction to cheaper one - either
7356 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7358 if (flag_expensive_optimizations
7359 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7360 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7361 & ~(((unsigned HOST_WIDE_INT
)
7362 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7366 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7367 GET_MODE (pos_rtx
));
7369 /* Prefer ZERO_EXTENSION, since it gives more information to
7371 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7372 < set_src_cost (temp
, optimize_this_for_speed_p
))
7378 /* Make POS_RTX unless we already have it and it is correct. If we don't
7379 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7381 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7382 pos_rtx
= orig_pos_rtx
;
7384 else if (pos_rtx
== 0)
7385 pos_rtx
= GEN_INT (pos
);
7387 /* Make the required operation. See if we can use existing rtx. */
7388 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7389 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7391 new_rtx
= gen_lowpart (mode
, new_rtx
);
7396 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7397 with any other operations in X. Return X without that shift if so. */
7400 extract_left_shift (rtx x
, int count
)
7402 enum rtx_code code
= GET_CODE (x
);
7403 enum machine_mode mode
= GET_MODE (x
);
7409 /* This is the shift itself. If it is wide enough, we will return
7410 either the value being shifted if the shift count is equal to
7411 COUNT or a shift for the difference. */
7412 if (CONST_INT_P (XEXP (x
, 1))
7413 && INTVAL (XEXP (x
, 1)) >= count
)
7414 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7415 INTVAL (XEXP (x
, 1)) - count
);
7419 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7420 return simplify_gen_unary (code
, mode
, tem
, mode
);
7424 case PLUS
: case IOR
: case XOR
: case AND
:
7425 /* If we can safely shift this constant and we find the inner shift,
7426 make a new operation. */
7427 if (CONST_INT_P (XEXP (x
, 1))
7428 && (UINTVAL (XEXP (x
, 1))
7429 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7430 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7432 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7433 return simplify_gen_binary (code
, mode
, tem
,
7434 gen_int_mode (val
, mode
));
7445 /* Look at the expression rooted at X. Look for expressions
7446 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7447 Form these expressions.
7449 Return the new rtx, usually just X.
7451 Also, for machines like the VAX that don't have logical shift insns,
7452 try to convert logical to arithmetic shift operations in cases where
7453 they are equivalent. This undoes the canonicalizations to logical
7454 shifts done elsewhere.
7456 We try, as much as possible, to re-use rtl expressions to save memory.
7458 IN_CODE says what kind of expression we are processing. Normally, it is
7459 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7460 being kludges), it is MEM. When processing the arguments of a comparison
7461 or a COMPARE against zero, it is COMPARE. */
7464 make_compound_operation (rtx x
, enum rtx_code in_code
)
7466 enum rtx_code code
= GET_CODE (x
);
7467 enum machine_mode mode
= GET_MODE (x
);
7468 int mode_width
= GET_MODE_PRECISION (mode
);
7470 enum rtx_code next_code
;
7476 /* Select the code to be used in recursive calls. Once we are inside an
7477 address, we stay there. If we have a comparison, set to COMPARE,
7478 but once inside, go back to our default of SET. */
7480 next_code
= (code
== MEM
? MEM
7481 : ((code
== PLUS
|| code
== MINUS
)
7482 && SCALAR_INT_MODE_P (mode
)) ? MEM
7483 : ((code
== COMPARE
|| COMPARISON_P (x
))
7484 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7485 : in_code
== COMPARE
? SET
: in_code
);
7487 /* Process depending on the code of this operation. If NEW is set
7488 nonzero, it will be returned. */
7493 /* Convert shifts by constants into multiplications if inside
7495 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7496 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7497 && INTVAL (XEXP (x
, 1)) >= 0
7498 && SCALAR_INT_MODE_P (mode
))
7500 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7501 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7503 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7504 if (GET_CODE (new_rtx
) == NEG
)
7506 new_rtx
= XEXP (new_rtx
, 0);
7509 multval
= trunc_int_for_mode (multval
, mode
);
7510 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7517 lhs
= make_compound_operation (lhs
, next_code
);
7518 rhs
= make_compound_operation (rhs
, next_code
);
7519 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7520 && SCALAR_INT_MODE_P (mode
))
7522 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7524 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7526 else if (GET_CODE (lhs
) == MULT
7527 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7529 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7530 simplify_gen_unary (NEG
, mode
,
7533 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7537 SUBST (XEXP (x
, 0), lhs
);
7538 SUBST (XEXP (x
, 1), rhs
);
7541 x
= gen_lowpart (mode
, new_rtx
);
7547 lhs
= make_compound_operation (lhs
, next_code
);
7548 rhs
= make_compound_operation (rhs
, next_code
);
7549 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7550 && SCALAR_INT_MODE_P (mode
))
7552 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7554 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7556 else if (GET_CODE (rhs
) == MULT
7557 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7559 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7560 simplify_gen_unary (NEG
, mode
,
7563 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7567 SUBST (XEXP (x
, 0), lhs
);
7568 SUBST (XEXP (x
, 1), rhs
);
7571 return gen_lowpart (mode
, new_rtx
);
7574 /* If the second operand is not a constant, we can't do anything
7576 if (!CONST_INT_P (XEXP (x
, 1)))
7579 /* If the constant is a power of two minus one and the first operand
7580 is a logical right shift, make an extraction. */
7581 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7582 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7584 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7585 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7586 0, in_code
== COMPARE
);
7589 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7590 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7591 && subreg_lowpart_p (XEXP (x
, 0))
7592 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7593 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7595 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7597 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7598 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7599 0, in_code
== COMPARE
);
7601 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7602 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7603 || GET_CODE (XEXP (x
, 0)) == IOR
)
7604 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7605 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7606 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7608 /* Apply the distributive law, and then try to make extractions. */
7609 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7610 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7612 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7614 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7617 /* If we are have (and (rotate X C) M) and C is larger than the number
7618 of bits in M, this is an extraction. */
7620 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7621 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7622 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7623 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7625 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7626 new_rtx
= make_extraction (mode
, new_rtx
,
7627 (GET_MODE_PRECISION (mode
)
7628 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7629 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7632 /* On machines without logical shifts, if the operand of the AND is
7633 a logical shift and our mask turns off all the propagated sign
7634 bits, we can replace the logical shift with an arithmetic shift. */
7635 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7636 && !have_insn_for (LSHIFTRT
, mode
)
7637 && have_insn_for (ASHIFTRT
, mode
)
7638 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7639 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7640 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7641 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7643 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7645 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7646 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7648 gen_rtx_ASHIFTRT (mode
,
7649 make_compound_operation
7650 (XEXP (XEXP (x
, 0), 0), next_code
),
7651 XEXP (XEXP (x
, 0), 1)));
7654 /* If the constant is one less than a power of two, this might be
7655 representable by an extraction even if no shift is present.
7656 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7657 we are in a COMPARE. */
7658 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7659 new_rtx
= make_extraction (mode
,
7660 make_compound_operation (XEXP (x
, 0),
7662 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7664 /* If we are in a comparison and this is an AND with a power of two,
7665 convert this into the appropriate bit extract. */
7666 else if (in_code
== COMPARE
7667 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7668 new_rtx
= make_extraction (mode
,
7669 make_compound_operation (XEXP (x
, 0),
7671 i
, NULL_RTX
, 1, 1, 0, 1);
7676 /* If the sign bit is known to be zero, replace this with an
7677 arithmetic shift. */
7678 if (have_insn_for (ASHIFTRT
, mode
)
7679 && ! have_insn_for (LSHIFTRT
, mode
)
7680 && mode_width
<= HOST_BITS_PER_WIDE_INT
7681 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7683 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7684 make_compound_operation (XEXP (x
, 0),
7690 /* ... fall through ... */
7696 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7697 this is a SIGN_EXTRACT. */
7698 if (CONST_INT_P (rhs
)
7699 && GET_CODE (lhs
) == ASHIFT
7700 && CONST_INT_P (XEXP (lhs
, 1))
7701 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7702 && INTVAL (XEXP (lhs
, 1)) >= 0
7703 && INTVAL (rhs
) < mode_width
)
7705 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7706 new_rtx
= make_extraction (mode
, new_rtx
,
7707 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7708 NULL_RTX
, mode_width
- INTVAL (rhs
),
7709 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7713 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7714 If so, try to merge the shifts into a SIGN_EXTEND. We could
7715 also do this for some cases of SIGN_EXTRACT, but it doesn't
7716 seem worth the effort; the case checked for occurs on Alpha. */
7719 && ! (GET_CODE (lhs
) == SUBREG
7720 && (OBJECT_P (SUBREG_REG (lhs
))))
7721 && CONST_INT_P (rhs
)
7722 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7723 && INTVAL (rhs
) < mode_width
7724 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7725 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7726 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7727 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7732 /* Call ourselves recursively on the inner expression. If we are
7733 narrowing the object and it has a different RTL code from
7734 what it originally did, do this SUBREG as a force_to_mode. */
7736 rtx inner
= SUBREG_REG (x
), simplified
;
7737 enum rtx_code subreg_code
= in_code
;
7739 /* If in_code is COMPARE, it isn't always safe to pass it through
7740 to the recursive make_compound_operation call. */
7741 if (subreg_code
== COMPARE
7742 && (!subreg_lowpart_p (x
)
7743 || GET_CODE (inner
) == SUBREG
7744 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7745 is (const_int 0), rather than
7746 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7747 || (GET_CODE (inner
) == AND
7748 && CONST_INT_P (XEXP (inner
, 1))
7749 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7750 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
7751 >= GET_MODE_BITSIZE (mode
))))
7754 tem
= make_compound_operation (inner
, subreg_code
);
7757 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7761 if (GET_CODE (tem
) != GET_CODE (inner
)
7762 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7763 && subreg_lowpart_p (x
))
7766 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7768 /* If we have something other than a SUBREG, we might have
7769 done an expansion, so rerun ourselves. */
7770 if (GET_CODE (newer
) != SUBREG
)
7771 newer
= make_compound_operation (newer
, in_code
);
7773 /* force_to_mode can expand compounds. If it just re-expanded the
7774 compound, use gen_lowpart to convert to the desired mode. */
7775 if (rtx_equal_p (newer
, x
)
7776 /* Likewise if it re-expanded the compound only partially.
7777 This happens for SUBREG of ZERO_EXTRACT if they extract
7778 the same number of bits. */
7779 || (GET_CODE (newer
) == SUBREG
7780 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7781 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7782 && GET_CODE (inner
) == AND
7783 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7784 return gen_lowpart (GET_MODE (x
), tem
);
7800 x
= gen_lowpart (mode
, new_rtx
);
7801 code
= GET_CODE (x
);
7804 /* Now recursively process each operand of this operation. We need to
7805 handle ZERO_EXTEND specially so that we don't lose track of the
7807 if (GET_CODE (x
) == ZERO_EXTEND
)
7809 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7810 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7811 new_rtx
, GET_MODE (XEXP (x
, 0)));
7814 SUBST (XEXP (x
, 0), new_rtx
);
7818 fmt
= GET_RTX_FORMAT (code
);
7819 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7822 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7823 SUBST (XEXP (x
, i
), new_rtx
);
7825 else if (fmt
[i
] == 'E')
7826 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7828 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7829 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7833 /* If this is a commutative operation, the changes to the operands
7834 may have made it noncanonical. */
7835 if (COMMUTATIVE_ARITH_P (x
)
7836 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7839 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7840 SUBST (XEXP (x
, 1), tem
);
7846 /* Given M see if it is a value that would select a field of bits
7847 within an item, but not the entire word. Return -1 if not.
7848 Otherwise, return the starting position of the field, where 0 is the
7851 *PLEN is set to the length of the field. */
7854 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7856 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7857 int pos
= m
? ctz_hwi (m
) : -1;
7861 /* Now shift off the low-order zero bits and see if we have a
7862 power of two minus 1. */
7863 len
= exact_log2 ((m
>> pos
) + 1);
7872 /* If X refers to a register that equals REG in value, replace these
7873 references with REG. */
7875 canon_reg_for_combine (rtx x
, rtx reg
)
7882 enum rtx_code code
= GET_CODE (x
);
7883 switch (GET_RTX_CLASS (code
))
7886 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7887 if (op0
!= XEXP (x
, 0))
7888 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7893 case RTX_COMM_ARITH
:
7894 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7895 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7896 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7897 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7901 case RTX_COMM_COMPARE
:
7902 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7903 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7904 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7905 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7906 GET_MODE (op0
), op0
, op1
);
7910 case RTX_BITFIELD_OPS
:
7911 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7912 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7913 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7914 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7915 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7916 GET_MODE (op0
), op0
, op1
, op2
);
7921 if (rtx_equal_p (get_last_value (reg
), x
)
7922 || rtx_equal_p (reg
, get_last_value (x
)))
7931 fmt
= GET_RTX_FORMAT (code
);
7933 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7936 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7937 if (op
!= XEXP (x
, i
))
7947 else if (fmt
[i
] == 'E')
7950 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7952 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7953 if (op
!= XVECEXP (x
, i
, j
))
7960 XVECEXP (x
, i
, j
) = op
;
7971 /* Return X converted to MODE. If the value is already truncated to
7972 MODE we can just return a subreg even though in the general case we
7973 would need an explicit truncation. */
7976 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7978 if (!CONST_INT_P (x
)
7979 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7980 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
7981 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7983 /* Bit-cast X into an integer mode. */
7984 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7985 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7986 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7990 return gen_lowpart (mode
, x
);
7993 /* See if X can be simplified knowing that we will only refer to it in
7994 MODE and will only refer to those bits that are nonzero in MASK.
7995 If other bits are being computed or if masking operations are done
7996 that select a superset of the bits in MASK, they can sometimes be
7999 Return a possibly simplified expression, but always convert X to
8000 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8002 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8003 are all off in X. This is used when X will be complemented, by either
8004 NOT, NEG, or XOR. */
8007 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8010 enum rtx_code code
= GET_CODE (x
);
8011 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8012 enum machine_mode op_mode
;
8013 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8016 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8017 code below will do the wrong thing since the mode of such an
8018 expression is VOIDmode.
8020 Also do nothing if X is a CLOBBER; this can happen if X was
8021 the return value from a call to gen_lowpart. */
8022 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8025 /* We want to perform the operation is its present mode unless we know
8026 that the operation is valid in MODE, in which case we do the operation
8028 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8029 && have_insn_for (code
, mode
))
8030 ? mode
: GET_MODE (x
));
8032 /* It is not valid to do a right-shift in a narrower mode
8033 than the one it came in with. */
8034 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8035 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8036 op_mode
= GET_MODE (x
);
8038 /* Truncate MASK to fit OP_MODE. */
8040 mask
&= GET_MODE_MASK (op_mode
);
8042 /* When we have an arithmetic operation, or a shift whose count we
8043 do not know, we need to assume that all bits up to the highest-order
8044 bit in MASK will be needed. This is how we form such a mask. */
8045 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8046 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8048 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8051 /* Determine what bits of X are guaranteed to be (non)zero. */
8052 nonzero
= nonzero_bits (x
, mode
);
8054 /* If none of the bits in X are needed, return a zero. */
8055 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8058 /* If X is a CONST_INT, return a new one. Do this here since the
8059 test below will fail. */
8060 if (CONST_INT_P (x
))
8062 if (SCALAR_INT_MODE_P (mode
))
8063 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8066 x
= GEN_INT (INTVAL (x
) & mask
);
8067 return gen_lowpart_common (mode
, x
);
8071 /* If X is narrower than MODE and we want all the bits in X's mode, just
8072 get X in the proper mode. */
8073 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8074 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8075 return gen_lowpart (mode
, x
);
8077 /* We can ignore the effect of a SUBREG if it narrows the mode or
8078 if the constant masks to zero all the bits the mode doesn't have. */
8079 if (GET_CODE (x
) == SUBREG
8080 && subreg_lowpart_p (x
)
8081 && ((GET_MODE_SIZE (GET_MODE (x
))
8082 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8084 & GET_MODE_MASK (GET_MODE (x
))
8085 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8086 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8088 /* The arithmetic simplifications here only work for scalar integer modes. */
8089 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8090 return gen_lowpart_or_truncate (mode
, x
);
8095 /* If X is a (clobber (const_int)), return it since we know we are
8096 generating something that won't match. */
8103 x
= expand_compound_operation (x
);
8104 if (GET_CODE (x
) != code
)
8105 return force_to_mode (x
, mode
, mask
, next_select
);
8109 /* Similarly for a truncate. */
8110 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8113 /* If this is an AND with a constant, convert it into an AND
8114 whose constant is the AND of that constant with MASK. If it
8115 remains an AND of MASK, delete it since it is redundant. */
8117 if (CONST_INT_P (XEXP (x
, 1)))
8119 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8120 mask
& INTVAL (XEXP (x
, 1)));
8122 /* If X is still an AND, see if it is an AND with a mask that
8123 is just some low-order bits. If so, and it is MASK, we don't
8126 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8127 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8131 /* If it remains an AND, try making another AND with the bits
8132 in the mode mask that aren't in MASK turned on. If the
8133 constant in the AND is wide enough, this might make a
8134 cheaper constant. */
8136 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8137 && GET_MODE_MASK (GET_MODE (x
)) != mask
8138 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8140 unsigned HOST_WIDE_INT cval
8141 = UINTVAL (XEXP (x
, 1))
8142 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8145 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8146 gen_int_mode (cval
, GET_MODE (x
)));
8147 if (set_src_cost (y
, optimize_this_for_speed_p
)
8148 < set_src_cost (x
, optimize_this_for_speed_p
))
8158 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8159 low-order bits (as in an alignment operation) and FOO is already
8160 aligned to that boundary, mask C1 to that boundary as well.
8161 This may eliminate that PLUS and, later, the AND. */
8164 unsigned int width
= GET_MODE_PRECISION (mode
);
8165 unsigned HOST_WIDE_INT smask
= mask
;
8167 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8168 number, sign extend it. */
8170 if (width
< HOST_BITS_PER_WIDE_INT
8171 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8172 smask
|= HOST_WIDE_INT_M1U
<< width
;
8174 if (CONST_INT_P (XEXP (x
, 1))
8175 && exact_log2 (- smask
) >= 0
8176 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8177 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8178 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8179 (INTVAL (XEXP (x
, 1)) & smask
)),
8180 mode
, smask
, next_select
);
8183 /* ... fall through ... */
8186 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8187 most significant bit in MASK since carries from those bits will
8188 affect the bits we are interested in. */
8193 /* If X is (minus C Y) where C's least set bit is larger than any bit
8194 in the mask, then we may replace with (neg Y). */
8195 if (CONST_INT_P (XEXP (x
, 0))
8196 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8197 & -INTVAL (XEXP (x
, 0))))
8200 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8202 return force_to_mode (x
, mode
, mask
, next_select
);
8205 /* Similarly, if C contains every bit in the fuller_mask, then we may
8206 replace with (not Y). */
8207 if (CONST_INT_P (XEXP (x
, 0))
8208 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8210 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8211 XEXP (x
, 1), GET_MODE (x
));
8212 return force_to_mode (x
, mode
, mask
, next_select
);
8220 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8221 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8222 operation which may be a bitfield extraction. Ensure that the
8223 constant we form is not wider than the mode of X. */
8225 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8226 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8227 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8228 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8229 && CONST_INT_P (XEXP (x
, 1))
8230 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8231 + floor_log2 (INTVAL (XEXP (x
, 1))))
8232 < GET_MODE_PRECISION (GET_MODE (x
)))
8233 && (UINTVAL (XEXP (x
, 1))
8234 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8236 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8237 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8239 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8240 XEXP (XEXP (x
, 0), 0), temp
);
8241 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8242 XEXP (XEXP (x
, 0), 1));
8243 return force_to_mode (x
, mode
, mask
, next_select
);
8247 /* For most binary operations, just propagate into the operation and
8248 change the mode if we have an operation of that mode. */
8250 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8251 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8253 /* If we ended up truncating both operands, truncate the result of the
8254 operation instead. */
8255 if (GET_CODE (op0
) == TRUNCATE
8256 && GET_CODE (op1
) == TRUNCATE
)
8258 op0
= XEXP (op0
, 0);
8259 op1
= XEXP (op1
, 0);
8262 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8263 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8265 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8266 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8270 /* For left shifts, do the same, but just for the first operand.
8271 However, we cannot do anything with shifts where we cannot
8272 guarantee that the counts are smaller than the size of the mode
8273 because such a count will have a different meaning in a
8276 if (! (CONST_INT_P (XEXP (x
, 1))
8277 && INTVAL (XEXP (x
, 1)) >= 0
8278 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8279 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8280 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8281 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8284 /* If the shift count is a constant and we can do arithmetic in
8285 the mode of the shift, refine which bits we need. Otherwise, use the
8286 conservative form of the mask. */
8287 if (CONST_INT_P (XEXP (x
, 1))
8288 && INTVAL (XEXP (x
, 1)) >= 0
8289 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8290 && HWI_COMPUTABLE_MODE_P (op_mode
))
8291 mask
>>= INTVAL (XEXP (x
, 1));
8295 op0
= gen_lowpart_or_truncate (op_mode
,
8296 force_to_mode (XEXP (x
, 0), op_mode
,
8297 mask
, next_select
));
8299 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8300 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8304 /* Here we can only do something if the shift count is a constant,
8305 this shift constant is valid for the host, and we can do arithmetic
8308 if (CONST_INT_P (XEXP (x
, 1))
8309 && INTVAL (XEXP (x
, 1)) >= 0
8310 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8311 && HWI_COMPUTABLE_MODE_P (op_mode
))
8313 rtx inner
= XEXP (x
, 0);
8314 unsigned HOST_WIDE_INT inner_mask
;
8316 /* Select the mask of the bits we need for the shift operand. */
8317 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8319 /* We can only change the mode of the shift if we can do arithmetic
8320 in the mode of the shift and INNER_MASK is no wider than the
8321 width of X's mode. */
8322 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8323 op_mode
= GET_MODE (x
);
8325 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8327 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8328 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8331 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8332 shift and AND produces only copies of the sign bit (C2 is one less
8333 than a power of two), we can do this with just a shift. */
8335 if (GET_CODE (x
) == LSHIFTRT
8336 && CONST_INT_P (XEXP (x
, 1))
8337 /* The shift puts one of the sign bit copies in the least significant
8339 && ((INTVAL (XEXP (x
, 1))
8340 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8341 >= GET_MODE_PRECISION (GET_MODE (x
)))
8342 && exact_log2 (mask
+ 1) >= 0
8343 /* Number of bits left after the shift must be more than the mask
8345 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8346 <= GET_MODE_PRECISION (GET_MODE (x
)))
8347 /* Must be more sign bit copies than the mask needs. */
8348 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8349 >= exact_log2 (mask
+ 1)))
8350 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8351 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8352 - exact_log2 (mask
+ 1)));
8357 /* If we are just looking for the sign bit, we don't need this shift at
8358 all, even if it has a variable count. */
8359 if (val_signbit_p (GET_MODE (x
), mask
))
8360 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8362 /* If this is a shift by a constant, get a mask that contains those bits
8363 that are not copies of the sign bit. We then have two cases: If
8364 MASK only includes those bits, this can be a logical shift, which may
8365 allow simplifications. If MASK is a single-bit field not within
8366 those bits, we are requesting a copy of the sign bit and hence can
8367 shift the sign bit to the appropriate location. */
8369 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8370 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8374 /* If the considered data is wider than HOST_WIDE_INT, we can't
8375 represent a mask for all its bits in a single scalar.
8376 But we only care about the lower bits, so calculate these. */
8378 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8380 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8382 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8383 is the number of bits a full-width mask would have set.
8384 We need only shift if these are fewer than nonzero can
8385 hold. If not, we must keep all bits set in nonzero. */
8387 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8388 < HOST_BITS_PER_WIDE_INT
)
8389 nonzero
>>= INTVAL (XEXP (x
, 1))
8390 + HOST_BITS_PER_WIDE_INT
8391 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8395 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8396 nonzero
>>= INTVAL (XEXP (x
, 1));
8399 if ((mask
& ~nonzero
) == 0)
8401 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8402 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8403 if (GET_CODE (x
) != ASHIFTRT
)
8404 return force_to_mode (x
, mode
, mask
, next_select
);
8407 else if ((i
= exact_log2 (mask
)) >= 0)
8409 x
= simplify_shift_const
8410 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8411 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8413 if (GET_CODE (x
) != ASHIFTRT
)
8414 return force_to_mode (x
, mode
, mask
, next_select
);
8418 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8419 even if the shift count isn't a constant. */
8421 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8422 XEXP (x
, 0), XEXP (x
, 1));
8426 /* If this is a zero- or sign-extension operation that just affects bits
8427 we don't care about, remove it. Be sure the call above returned
8428 something that is still a shift. */
8430 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8431 && CONST_INT_P (XEXP (x
, 1))
8432 && INTVAL (XEXP (x
, 1)) >= 0
8433 && (INTVAL (XEXP (x
, 1))
8434 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8435 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8436 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8437 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8444 /* If the shift count is constant and we can do computations
8445 in the mode of X, compute where the bits we care about are.
8446 Otherwise, we can't do anything. Don't change the mode of
8447 the shift or propagate MODE into the shift, though. */
8448 if (CONST_INT_P (XEXP (x
, 1))
8449 && INTVAL (XEXP (x
, 1)) >= 0)
8451 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8453 gen_int_mode (mask
, GET_MODE (x
)),
8455 if (temp
&& CONST_INT_P (temp
))
8457 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8458 INTVAL (temp
), next_select
));
8463 /* If we just want the low-order bit, the NEG isn't needed since it
8464 won't change the low-order bit. */
8466 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8468 /* We need any bits less significant than the most significant bit in
8469 MASK since carries from those bits will affect the bits we are
8475 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8476 same as the XOR case above. Ensure that the constant we form is not
8477 wider than the mode of X. */
8479 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8480 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8481 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8482 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8483 < GET_MODE_PRECISION (GET_MODE (x
)))
8484 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8486 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8488 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8489 XEXP (XEXP (x
, 0), 0), temp
);
8490 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8491 temp
, XEXP (XEXP (x
, 0), 1));
8493 return force_to_mode (x
, mode
, mask
, next_select
);
8496 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8497 use the full mask inside the NOT. */
8501 op0
= gen_lowpart_or_truncate (op_mode
,
8502 force_to_mode (XEXP (x
, 0), mode
, mask
,
8504 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8505 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8509 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8510 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8511 which is equal to STORE_FLAG_VALUE. */
8512 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8513 && XEXP (x
, 1) == const0_rtx
8514 && GET_MODE (XEXP (x
, 0)) == mode
8515 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8516 && (nonzero_bits (XEXP (x
, 0), mode
)
8517 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8518 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8523 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8524 written in a narrower mode. We play it safe and do not do so. */
8527 gen_lowpart_or_truncate (GET_MODE (x
),
8528 force_to_mode (XEXP (x
, 1), mode
,
8529 mask
, next_select
)));
8531 gen_lowpart_or_truncate (GET_MODE (x
),
8532 force_to_mode (XEXP (x
, 2), mode
,
8533 mask
, next_select
)));
8540 /* Ensure we return a value of the proper mode. */
8541 return gen_lowpart_or_truncate (mode
, x
);
8544 /* Return nonzero if X is an expression that has one of two values depending on
8545 whether some other value is zero or nonzero. In that case, we return the
8546 value that is being tested, *PTRUE is set to the value if the rtx being
8547 returned has a nonzero value, and *PFALSE is set to the other alternative.
8549 If we return zero, we set *PTRUE and *PFALSE to X. */
8552 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8554 enum machine_mode mode
= GET_MODE (x
);
8555 enum rtx_code code
= GET_CODE (x
);
8556 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8557 unsigned HOST_WIDE_INT nz
;
8559 /* If we are comparing a value against zero, we are done. */
8560 if ((code
== NE
|| code
== EQ
)
8561 && XEXP (x
, 1) == const0_rtx
)
8563 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8564 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8568 /* If this is a unary operation whose operand has one of two values, apply
8569 our opcode to compute those values. */
8570 else if (UNARY_P (x
)
8571 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8573 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8574 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8575 GET_MODE (XEXP (x
, 0)));
8579 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8580 make can't possibly match and would suppress other optimizations. */
8581 else if (code
== COMPARE
)
8584 /* If this is a binary operation, see if either side has only one of two
8585 values. If either one does or if both do and they are conditional on
8586 the same value, compute the new true and false values. */
8587 else if (BINARY_P (x
))
8589 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8590 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8592 if ((cond0
!= 0 || cond1
!= 0)
8593 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8595 /* If if_then_else_cond returned zero, then true/false are the
8596 same rtl. We must copy one of them to prevent invalid rtl
8599 true0
= copy_rtx (true0
);
8600 else if (cond1
== 0)
8601 true1
= copy_rtx (true1
);
8603 if (COMPARISON_P (x
))
8605 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8607 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8612 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8613 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8616 return cond0
? cond0
: cond1
;
8619 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8620 operands is zero when the other is nonzero, and vice-versa,
8621 and STORE_FLAG_VALUE is 1 or -1. */
8623 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8624 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8626 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8628 rtx op0
= XEXP (XEXP (x
, 0), 1);
8629 rtx op1
= XEXP (XEXP (x
, 1), 1);
8631 cond0
= XEXP (XEXP (x
, 0), 0);
8632 cond1
= XEXP (XEXP (x
, 1), 0);
8634 if (COMPARISON_P (cond0
)
8635 && COMPARISON_P (cond1
)
8636 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8637 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8638 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8639 || ((swap_condition (GET_CODE (cond0
))
8640 == reversed_comparison_code (cond1
, NULL
))
8641 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8642 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8643 && ! side_effects_p (x
))
8645 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8646 *pfalse
= simplify_gen_binary (MULT
, mode
,
8648 ? simplify_gen_unary (NEG
, mode
,
8656 /* Similarly for MULT, AND and UMIN, except that for these the result
8658 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8659 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8660 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8662 cond0
= XEXP (XEXP (x
, 0), 0);
8663 cond1
= XEXP (XEXP (x
, 1), 0);
8665 if (COMPARISON_P (cond0
)
8666 && COMPARISON_P (cond1
)
8667 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8668 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8669 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8670 || ((swap_condition (GET_CODE (cond0
))
8671 == reversed_comparison_code (cond1
, NULL
))
8672 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8673 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8674 && ! side_effects_p (x
))
8676 *ptrue
= *pfalse
= const0_rtx
;
8682 else if (code
== IF_THEN_ELSE
)
8684 /* If we have IF_THEN_ELSE already, extract the condition and
8685 canonicalize it if it is NE or EQ. */
8686 cond0
= XEXP (x
, 0);
8687 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8688 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8689 return XEXP (cond0
, 0);
8690 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8692 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8693 return XEXP (cond0
, 0);
8699 /* If X is a SUBREG, we can narrow both the true and false values
8700 if the inner expression, if there is a condition. */
8701 else if (code
== SUBREG
8702 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8705 true0
= simplify_gen_subreg (mode
, true0
,
8706 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8707 false0
= simplify_gen_subreg (mode
, false0
,
8708 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8709 if (true0
&& false0
)
8717 /* If X is a constant, this isn't special and will cause confusions
8718 if we treat it as such. Likewise if it is equivalent to a constant. */
8719 else if (CONSTANT_P (x
)
8720 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8723 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8724 will be least confusing to the rest of the compiler. */
8725 else if (mode
== BImode
)
8727 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8731 /* If X is known to be either 0 or -1, those are the true and
8732 false values when testing X. */
8733 else if (x
== constm1_rtx
|| x
== const0_rtx
8734 || (mode
!= VOIDmode
8735 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8737 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8741 /* Likewise for 0 or a single bit. */
8742 else if (HWI_COMPUTABLE_MODE_P (mode
)
8743 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8745 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8749 /* Otherwise fail; show no condition with true and false values the same. */
8750 *ptrue
= *pfalse
= x
;
8754 /* Return the value of expression X given the fact that condition COND
8755 is known to be true when applied to REG as its first operand and VAL
8756 as its second. X is known to not be shared and so can be modified in
8759 We only handle the simplest cases, and specifically those cases that
8760 arise with IF_THEN_ELSE expressions. */
8763 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8765 enum rtx_code code
= GET_CODE (x
);
8770 if (side_effects_p (x
))
8773 /* If either operand of the condition is a floating point value,
8774 then we have to avoid collapsing an EQ comparison. */
8776 && rtx_equal_p (x
, reg
)
8777 && ! FLOAT_MODE_P (GET_MODE (x
))
8778 && ! FLOAT_MODE_P (GET_MODE (val
)))
8781 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8784 /* If X is (abs REG) and we know something about REG's relationship
8785 with zero, we may be able to simplify this. */
8787 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8790 case GE
: case GT
: case EQ
:
8793 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8795 GET_MODE (XEXP (x
, 0)));
8800 /* The only other cases we handle are MIN, MAX, and comparisons if the
8801 operands are the same as REG and VAL. */
8803 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8805 if (rtx_equal_p (XEXP (x
, 0), val
))
8806 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8808 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8810 if (COMPARISON_P (x
))
8812 if (comparison_dominates_p (cond
, code
))
8813 return const_true_rtx
;
8815 code
= reversed_comparison_code (x
, NULL
);
8817 && comparison_dominates_p (cond
, code
))
8822 else if (code
== SMAX
|| code
== SMIN
8823 || code
== UMIN
|| code
== UMAX
)
8825 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8827 /* Do not reverse the condition when it is NE or EQ.
8828 This is because we cannot conclude anything about
8829 the value of 'SMAX (x, y)' when x is not equal to y,
8830 but we can when x equals y. */
8831 if ((code
== SMAX
|| code
== UMAX
)
8832 && ! (cond
== EQ
|| cond
== NE
))
8833 cond
= reverse_condition (cond
);
8838 return unsignedp
? x
: XEXP (x
, 1);
8840 return unsignedp
? x
: XEXP (x
, 0);
8842 return unsignedp
? XEXP (x
, 1) : x
;
8844 return unsignedp
? XEXP (x
, 0) : x
;
8851 else if (code
== SUBREG
)
8853 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8854 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8856 if (SUBREG_REG (x
) != r
)
8858 /* We must simplify subreg here, before we lose track of the
8859 original inner_mode. */
8860 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8861 inner_mode
, SUBREG_BYTE (x
));
8865 SUBST (SUBREG_REG (x
), r
);
8870 /* We don't have to handle SIGN_EXTEND here, because even in the
8871 case of replacing something with a modeless CONST_INT, a
8872 CONST_INT is already (supposed to be) a valid sign extension for
8873 its narrower mode, which implies it's already properly
8874 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8875 story is different. */
8876 else if (code
== ZERO_EXTEND
)
8878 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8879 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8881 if (XEXP (x
, 0) != r
)
8883 /* We must simplify the zero_extend here, before we lose
8884 track of the original inner_mode. */
8885 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8890 SUBST (XEXP (x
, 0), r
);
8896 fmt
= GET_RTX_FORMAT (code
);
8897 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8900 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8901 else if (fmt
[i
] == 'E')
8902 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8903 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8910 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8911 assignment as a field assignment. */
8914 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8916 if (x
== y
|| rtx_equal_p (x
, y
))
8919 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8922 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8923 Note that all SUBREGs of MEM are paradoxical; otherwise they
8924 would have been rewritten. */
8925 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8926 && MEM_P (SUBREG_REG (y
))
8927 && rtx_equal_p (SUBREG_REG (y
),
8928 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8931 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8932 && MEM_P (SUBREG_REG (x
))
8933 && rtx_equal_p (SUBREG_REG (x
),
8934 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8937 /* We used to see if get_last_value of X and Y were the same but that's
8938 not correct. In one direction, we'll cause the assignment to have
8939 the wrong destination and in the case, we'll import a register into this
8940 insn that might have already have been dead. So fail if none of the
8941 above cases are true. */
8945 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8946 Return that assignment if so.
8948 We only handle the most common cases. */
8951 make_field_assignment (rtx x
)
8953 rtx dest
= SET_DEST (x
);
8954 rtx src
= SET_SRC (x
);
8959 unsigned HOST_WIDE_INT len
;
8961 enum machine_mode mode
;
8963 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8964 a clear of a one-bit field. We will have changed it to
8965 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8968 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8969 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8970 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8971 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8973 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8976 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8980 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8981 && subreg_lowpart_p (XEXP (src
, 0))
8982 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8983 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8984 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8985 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8986 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8987 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8989 assign
= make_extraction (VOIDmode
, dest
, 0,
8990 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8993 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8997 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8999 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9000 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9001 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9003 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9006 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
9010 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9011 SRC is an AND with all bits of that field set, then we can discard
9013 if (GET_CODE (dest
) == ZERO_EXTRACT
9014 && CONST_INT_P (XEXP (dest
, 1))
9015 && GET_CODE (src
) == AND
9016 && CONST_INT_P (XEXP (src
, 1)))
9018 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9019 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9020 unsigned HOST_WIDE_INT ze_mask
;
9022 if (width
>= HOST_BITS_PER_WIDE_INT
)
9025 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9027 /* Complete overlap. We can remove the source AND. */
9028 if ((and_mask
& ze_mask
) == ze_mask
)
9029 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
9031 /* Partial overlap. We can reduce the source AND. */
9032 if ((and_mask
& ze_mask
) != and_mask
)
9034 mode
= GET_MODE (src
);
9035 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9036 gen_int_mode (and_mask
& ze_mask
, mode
));
9037 return gen_rtx_SET (VOIDmode
, dest
, src
);
9041 /* The other case we handle is assignments into a constant-position
9042 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9043 a mask that has all one bits except for a group of zero bits and
9044 OTHER is known to have zeros where C1 has ones, this is such an
9045 assignment. Compute the position and length from C1. Shift OTHER
9046 to the appropriate position, force it to the required mode, and
9047 make the extraction. Check for the AND in both operands. */
9049 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9052 rhs
= expand_compound_operation (XEXP (src
, 0));
9053 lhs
= expand_compound_operation (XEXP (src
, 1));
9055 if (GET_CODE (rhs
) == AND
9056 && CONST_INT_P (XEXP (rhs
, 1))
9057 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9058 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9059 else if (GET_CODE (lhs
) == AND
9060 && CONST_INT_P (XEXP (lhs
, 1))
9061 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9062 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9066 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9067 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9068 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9069 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9072 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9076 /* The mode to use for the source is the mode of the assignment, or of
9077 what is inside a possible STRICT_LOW_PART. */
9078 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9079 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9081 /* Shift OTHER right POS places and make it the source, restricting it
9082 to the proper length and mode. */
9084 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9088 src
= force_to_mode (src
, mode
,
9089 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9090 ? ~(unsigned HOST_WIDE_INT
) 0
9091 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9094 /* If SRC is masked by an AND that does not make a difference in
9095 the value being stored, strip it. */
9096 if (GET_CODE (assign
) == ZERO_EXTRACT
9097 && CONST_INT_P (XEXP (assign
, 1))
9098 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9099 && GET_CODE (src
) == AND
9100 && CONST_INT_P (XEXP (src
, 1))
9101 && UINTVAL (XEXP (src
, 1))
9102 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9103 src
= XEXP (src
, 0);
9105 return gen_rtx_SET (VOIDmode
, assign
, src
);
9108 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9112 apply_distributive_law (rtx x
)
9114 enum rtx_code code
= GET_CODE (x
);
9115 enum rtx_code inner_code
;
9116 rtx lhs
, rhs
, other
;
9119 /* Distributivity is not true for floating point as it can change the
9120 value. So we don't do it unless -funsafe-math-optimizations. */
9121 if (FLOAT_MODE_P (GET_MODE (x
))
9122 && ! flag_unsafe_math_optimizations
)
9125 /* The outer operation can only be one of the following: */
9126 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9127 && code
!= PLUS
&& code
!= MINUS
)
9133 /* If either operand is a primitive we can't do anything, so get out
9135 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9138 lhs
= expand_compound_operation (lhs
);
9139 rhs
= expand_compound_operation (rhs
);
9140 inner_code
= GET_CODE (lhs
);
9141 if (inner_code
!= GET_CODE (rhs
))
9144 /* See if the inner and outer operations distribute. */
9151 /* These all distribute except over PLUS. */
9152 if (code
== PLUS
|| code
== MINUS
)
9157 if (code
!= PLUS
&& code
!= MINUS
)
9162 /* This is also a multiply, so it distributes over everything. */
9165 /* This used to handle SUBREG, but this turned out to be counter-
9166 productive, since (subreg (op ...)) usually is not handled by
9167 insn patterns, and this "optimization" therefore transformed
9168 recognizable patterns into unrecognizable ones. Therefore the
9169 SUBREG case was removed from here.
9171 It is possible that distributing SUBREG over arithmetic operations
9172 leads to an intermediate result than can then be optimized further,
9173 e.g. by moving the outer SUBREG to the other side of a SET as done
9174 in simplify_set. This seems to have been the original intent of
9175 handling SUBREGs here.
9177 However, with current GCC this does not appear to actually happen,
9178 at least on major platforms. If some case is found where removing
9179 the SUBREG case here prevents follow-on optimizations, distributing
9180 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9186 /* Set LHS and RHS to the inner operands (A and B in the example
9187 above) and set OTHER to the common operand (C in the example).
9188 There is only one way to do this unless the inner operation is
9190 if (COMMUTATIVE_ARITH_P (lhs
)
9191 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9192 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9193 else if (COMMUTATIVE_ARITH_P (lhs
)
9194 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9195 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9196 else if (COMMUTATIVE_ARITH_P (lhs
)
9197 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9198 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9199 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9200 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9204 /* Form the new inner operation, seeing if it simplifies first. */
9205 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9207 /* There is one exception to the general way of distributing:
9208 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9209 if (code
== XOR
&& inner_code
== IOR
)
9212 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9215 /* We may be able to continuing distributing the result, so call
9216 ourselves recursively on the inner operation before forming the
9217 outer operation, which we return. */
9218 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9219 apply_distributive_law (tem
), other
);
9222 /* See if X is of the form (* (+ A B) C), and if so convert to
9223 (+ (* A C) (* B C)) and try to simplify.
9225 Most of the time, this results in no change. However, if some of
9226 the operands are the same or inverses of each other, simplifications
9229 For example, (and (ior A B) (not B)) can occur as the result of
9230 expanding a bit field assignment. When we apply the distributive
9231 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9232 which then simplifies to (and (A (not B))).
9234 Note that no checks happen on the validity of applying the inverse
9235 distributive law. This is pointless since we can do it in the
9236 few places where this routine is called.
9238 N is the index of the term that is decomposed (the arithmetic operation,
9239 i.e. (+ A B) in the first example above). !N is the index of the term that
9240 is distributed, i.e. of C in the first example above. */
9242 distribute_and_simplify_rtx (rtx x
, int n
)
9244 enum machine_mode mode
;
9245 enum rtx_code outer_code
, inner_code
;
9246 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9248 /* Distributivity is not true for floating point as it can change the
9249 value. So we don't do it unless -funsafe-math-optimizations. */
9250 if (FLOAT_MODE_P (GET_MODE (x
))
9251 && ! flag_unsafe_math_optimizations
)
9254 decomposed
= XEXP (x
, n
);
9255 if (!ARITHMETIC_P (decomposed
))
9258 mode
= GET_MODE (x
);
9259 outer_code
= GET_CODE (x
);
9260 distributed
= XEXP (x
, !n
);
9262 inner_code
= GET_CODE (decomposed
);
9263 inner_op0
= XEXP (decomposed
, 0);
9264 inner_op1
= XEXP (decomposed
, 1);
9266 /* Special case (and (xor B C) (not A)), which is equivalent to
9267 (xor (ior A B) (ior A C)) */
9268 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9270 distributed
= XEXP (distributed
, 0);
9276 /* Distribute the second term. */
9277 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9278 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9282 /* Distribute the first term. */
9283 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9284 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9287 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9289 if (GET_CODE (tmp
) != outer_code
9290 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9291 < set_src_cost (x
, optimize_this_for_speed_p
)))
9297 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9298 in MODE. Return an equivalent form, if different from (and VAROP
9299 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9302 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9303 unsigned HOST_WIDE_INT constop
)
9305 unsigned HOST_WIDE_INT nonzero
;
9306 unsigned HOST_WIDE_INT orig_constop
;
9311 orig_constop
= constop
;
9312 if (GET_CODE (varop
) == CLOBBER
)
9315 /* Simplify VAROP knowing that we will be only looking at some of the
9318 Note by passing in CONSTOP, we guarantee that the bits not set in
9319 CONSTOP are not significant and will never be examined. We must
9320 ensure that is the case by explicitly masking out those bits
9321 before returning. */
9322 varop
= force_to_mode (varop
, mode
, constop
, 0);
9324 /* If VAROP is a CLOBBER, we will fail so return it. */
9325 if (GET_CODE (varop
) == CLOBBER
)
9328 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9329 to VAROP and return the new constant. */
9330 if (CONST_INT_P (varop
))
9331 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9333 /* See what bits may be nonzero in VAROP. Unlike the general case of
9334 a call to nonzero_bits, here we don't care about bits outside
9337 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9339 /* Turn off all bits in the constant that are known to already be zero.
9340 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9341 which is tested below. */
9345 /* If we don't have any bits left, return zero. */
9349 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9350 a power of two, we can replace this with an ASHIFT. */
9351 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9352 && (i
= exact_log2 (constop
)) >= 0)
9353 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9355 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9356 or XOR, then try to apply the distributive law. This may eliminate
9357 operations if either branch can be simplified because of the AND.
9358 It may also make some cases more complex, but those cases probably
9359 won't match a pattern either with or without this. */
9361 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9365 apply_distributive_law
9366 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9367 simplify_and_const_int (NULL_RTX
,
9371 simplify_and_const_int (NULL_RTX
,
9376 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9377 the AND and see if one of the operands simplifies to zero. If so, we
9378 may eliminate it. */
9380 if (GET_CODE (varop
) == PLUS
9381 && exact_log2 (constop
+ 1) >= 0)
9385 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9386 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9387 if (o0
== const0_rtx
)
9389 if (o1
== const0_rtx
)
9393 /* Make a SUBREG if necessary. If we can't make it, fail. */
9394 varop
= gen_lowpart (mode
, varop
);
9395 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9398 /* If we are only masking insignificant bits, return VAROP. */
9399 if (constop
== nonzero
)
9402 if (varop
== orig_varop
&& constop
== orig_constop
)
9405 /* Otherwise, return an AND. */
9406 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9410 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9413 Return an equivalent form, if different from X. Otherwise, return X. If
9414 X is zero, we are to always construct the equivalent form. */
9417 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9418 unsigned HOST_WIDE_INT constop
)
9420 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9425 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9426 gen_int_mode (constop
, mode
));
9427 if (GET_MODE (x
) != mode
)
9428 x
= gen_lowpart (mode
, x
);
9432 /* Given a REG, X, compute which bits in X can be nonzero.
9433 We don't care about bits outside of those defined in MODE.
9435 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9436 a shift, AND, or zero_extract, we can do better. */
9439 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9440 const_rtx known_x ATTRIBUTE_UNUSED
,
9441 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9442 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9443 unsigned HOST_WIDE_INT
*nonzero
)
9448 /* If X is a register whose nonzero bits value is current, use it.
9449 Otherwise, if X is a register whose value we can find, use that
9450 value. Otherwise, use the previously-computed global nonzero bits
9451 for this register. */
9453 rsp
= ®_stat
[REGNO (x
)];
9454 if (rsp
->last_set_value
!= 0
9455 && (rsp
->last_set_mode
== mode
9456 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9457 && GET_MODE_CLASS (mode
) == MODE_INT
))
9458 && ((rsp
->last_set_label
>= label_tick_ebb_start
9459 && rsp
->last_set_label
< label_tick
)
9460 || (rsp
->last_set_label
== label_tick
9461 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9462 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9463 && REG_N_SETS (REGNO (x
)) == 1
9465 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9468 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9470 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9471 /* We don't know anything about the upper bits. */
9472 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9478 tem
= get_last_value (x
);
9482 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9483 /* If X is narrower than MODE and TEM is a non-negative
9484 constant that would appear negative in the mode of X,
9485 sign-extend it for use in reg_nonzero_bits because some
9486 machines (maybe most) will actually do the sign-extension
9487 and this is the conservative approach.
9489 ??? For 2.5, try to tighten up the MD files in this regard
9490 instead of this kludge. */
9492 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9493 && CONST_INT_P (tem
)
9495 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9496 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9500 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9502 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9504 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9505 /* We don't know anything about the upper bits. */
9506 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9514 /* Return the number of bits at the high-order end of X that are known to
9515 be equal to the sign bit. X will be used in mode MODE; if MODE is
9516 VOIDmode, X will be used in its own mode. The returned value will always
9517 be between 1 and the number of bits in MODE. */
9520 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9521 const_rtx known_x ATTRIBUTE_UNUSED
,
9522 enum machine_mode known_mode
9524 unsigned int known_ret ATTRIBUTE_UNUSED
,
9525 unsigned int *result
)
9530 rsp
= ®_stat
[REGNO (x
)];
9531 if (rsp
->last_set_value
!= 0
9532 && rsp
->last_set_mode
== mode
9533 && ((rsp
->last_set_label
>= label_tick_ebb_start
9534 && rsp
->last_set_label
< label_tick
)
9535 || (rsp
->last_set_label
== label_tick
9536 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9537 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9538 && REG_N_SETS (REGNO (x
)) == 1
9540 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9543 *result
= rsp
->last_set_sign_bit_copies
;
9547 tem
= get_last_value (x
);
9551 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9552 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9553 *result
= rsp
->sign_bit_copies
;
9558 /* Return the number of "extended" bits there are in X, when interpreted
9559 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9560 unsigned quantities, this is the number of high-order zero bits.
9561 For signed quantities, this is the number of copies of the sign bit
9562 minus 1. In both case, this function returns the number of "spare"
9563 bits. For example, if two quantities for which this function returns
9564 at least 1 are added, the addition is known not to overflow.
9566 This function will always return 0 unless called during combine, which
9567 implies that it must be called from a define_split. */
9570 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9572 if (nonzero_sign_valid
== 0)
9576 ? (HWI_COMPUTABLE_MODE_P (mode
)
9577 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9578 - floor_log2 (nonzero_bits (x
, mode
)))
9580 : num_sign_bit_copies (x
, mode
) - 1);
9583 /* This function is called from `simplify_shift_const' to merge two
9584 outer operations. Specifically, we have already found that we need
9585 to perform operation *POP0 with constant *PCONST0 at the outermost
9586 position. We would now like to also perform OP1 with constant CONST1
9587 (with *POP0 being done last).
9589 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9590 the resulting operation. *PCOMP_P is set to 1 if we would need to
9591 complement the innermost operand, otherwise it is unchanged.
9593 MODE is the mode in which the operation will be done. No bits outside
9594 the width of this mode matter. It is assumed that the width of this mode
9595 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9597 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9598 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9599 result is simply *PCONST0.
9601 If the resulting operation cannot be expressed as one operation, we
9602 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9605 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9607 enum rtx_code op0
= *pop0
;
9608 HOST_WIDE_INT const0
= *pconst0
;
9610 const0
&= GET_MODE_MASK (mode
);
9611 const1
&= GET_MODE_MASK (mode
);
9613 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9617 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9620 if (op1
== UNKNOWN
|| op0
== SET
)
9623 else if (op0
== UNKNOWN
)
9624 op0
= op1
, const0
= const1
;
9626 else if (op0
== op1
)
9650 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9651 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9654 /* If the two constants aren't the same, we can't do anything. The
9655 remaining six cases can all be done. */
9656 else if (const0
!= const1
)
9664 /* (a & b) | b == b */
9666 else /* op1 == XOR */
9667 /* (a ^ b) | b == a | b */
9673 /* (a & b) ^ b == (~a) & b */
9674 op0
= AND
, *pcomp_p
= 1;
9675 else /* op1 == IOR */
9676 /* (a | b) ^ b == a & ~b */
9677 op0
= AND
, const0
= ~const0
;
9682 /* (a | b) & b == b */
9684 else /* op1 == XOR */
9685 /* (a ^ b) & b) == (~a) & b */
9692 /* Check for NO-OP cases. */
9693 const0
&= GET_MODE_MASK (mode
);
9695 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9697 else if (const0
== 0 && op0
== AND
)
9699 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9705 /* ??? Slightly redundant with the above mask, but not entirely.
9706 Moving this above means we'd have to sign-extend the mode mask
9707 for the final test. */
9708 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9709 *pconst0
= trunc_int_for_mode (const0
, mode
);
9714 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9715 the shift in. The original shift operation CODE is performed on OP in
9716 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9717 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9718 result of the shift is subject to operation OUTER_CODE with operand
9721 static enum machine_mode
9722 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9723 enum machine_mode orig_mode
, enum machine_mode mode
,
9724 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9726 if (orig_mode
== mode
)
9728 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9730 /* In general we can't perform in wider mode for right shift and rotate. */
9734 /* We can still widen if the bits brought in from the left are identical
9735 to the sign bit of ORIG_MODE. */
9736 if (num_sign_bit_copies (op
, mode
)
9737 > (unsigned) (GET_MODE_PRECISION (mode
)
9738 - GET_MODE_PRECISION (orig_mode
)))
9743 /* Similarly here but with zero bits. */
9744 if (HWI_COMPUTABLE_MODE_P (mode
)
9745 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9748 /* We can also widen if the bits brought in will be masked off. This
9749 operation is performed in ORIG_MODE. */
9750 if (outer_code
== AND
)
9752 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9755 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9771 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9772 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9773 if we cannot simplify it. Otherwise, return a simplified value.
9775 The shift is normally computed in the widest mode we find in VAROP, as
9776 long as it isn't a different number of words than RESULT_MODE. Exceptions
9777 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9780 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9781 rtx varop
, int orig_count
)
9783 enum rtx_code orig_code
= code
;
9784 rtx orig_varop
= varop
;
9786 enum machine_mode mode
= result_mode
;
9787 enum machine_mode shift_mode
, tmode
;
9788 unsigned int mode_words
9789 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9790 /* We form (outer_op (code varop count) (outer_const)). */
9791 enum rtx_code outer_op
= UNKNOWN
;
9792 HOST_WIDE_INT outer_const
= 0;
9793 int complement_p
= 0;
9796 /* Make sure and truncate the "natural" shift on the way in. We don't
9797 want to do this inside the loop as it makes it more difficult to
9799 if (SHIFT_COUNT_TRUNCATED
)
9800 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9802 /* If we were given an invalid count, don't do anything except exactly
9803 what was requested. */
9805 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9810 /* Unless one of the branches of the `if' in this loop does a `continue',
9811 we will `break' the loop after the `if'. */
9815 /* If we have an operand of (clobber (const_int 0)), fail. */
9816 if (GET_CODE (varop
) == CLOBBER
)
9819 /* Convert ROTATERT to ROTATE. */
9820 if (code
== ROTATERT
)
9822 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9824 if (VECTOR_MODE_P (result_mode
))
9825 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9827 count
= bitsize
- count
;
9830 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9831 mode
, outer_op
, outer_const
);
9833 /* Handle cases where the count is greater than the size of the mode
9834 minus 1. For ASHIFT, use the size minus one as the count (this can
9835 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9836 take the count modulo the size. For other shifts, the result is
9839 Since these shifts are being produced by the compiler by combining
9840 multiple operations, each of which are defined, we know what the
9841 result is supposed to be. */
9843 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9845 if (code
== ASHIFTRT
)
9846 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9847 else if (code
== ROTATE
|| code
== ROTATERT
)
9848 count
%= GET_MODE_PRECISION (shift_mode
);
9851 /* We can't simply return zero because there may be an
9859 /* If we discovered we had to complement VAROP, leave. Making a NOT
9860 here would cause an infinite loop. */
9864 /* An arithmetic right shift of a quantity known to be -1 or 0
9866 if (code
== ASHIFTRT
9867 && (num_sign_bit_copies (varop
, shift_mode
)
9868 == GET_MODE_PRECISION (shift_mode
)))
9874 /* If we are doing an arithmetic right shift and discarding all but
9875 the sign bit copies, this is equivalent to doing a shift by the
9876 bitsize minus one. Convert it into that shift because it will often
9877 allow other simplifications. */
9879 if (code
== ASHIFTRT
9880 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9881 >= GET_MODE_PRECISION (shift_mode
)))
9882 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9884 /* We simplify the tests below and elsewhere by converting
9885 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9886 `make_compound_operation' will convert it to an ASHIFTRT for
9887 those machines (such as VAX) that don't have an LSHIFTRT. */
9888 if (code
== ASHIFTRT
9889 && val_signbit_known_clear_p (shift_mode
,
9890 nonzero_bits (varop
, shift_mode
)))
9893 if (((code
== LSHIFTRT
9894 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9895 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9897 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9898 && !((nonzero_bits (varop
, shift_mode
) << count
)
9899 & GET_MODE_MASK (shift_mode
))))
9900 && !side_effects_p (varop
))
9903 switch (GET_CODE (varop
))
9909 new_rtx
= expand_compound_operation (varop
);
9910 if (new_rtx
!= varop
)
9918 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9919 minus the width of a smaller mode, we can do this with a
9920 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9921 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9922 && ! mode_dependent_address_p (XEXP (varop
, 0),
9923 MEM_ADDR_SPACE (varop
))
9924 && ! MEM_VOLATILE_P (varop
)
9925 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9926 MODE_INT
, 1)) != BLKmode
)
9928 new_rtx
= adjust_address_nv (varop
, tmode
,
9929 BYTES_BIG_ENDIAN
? 0
9930 : count
/ BITS_PER_UNIT
);
9932 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9933 : ZERO_EXTEND
, mode
, new_rtx
);
9940 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9941 the same number of words as what we've seen so far. Then store
9942 the widest mode in MODE. */
9943 if (subreg_lowpart_p (varop
)
9944 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9945 > GET_MODE_SIZE (GET_MODE (varop
)))
9946 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9947 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9949 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9950 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9952 varop
= SUBREG_REG (varop
);
9953 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9954 mode
= GET_MODE (varop
);
9960 /* Some machines use MULT instead of ASHIFT because MULT
9961 is cheaper. But it is still better on those machines to
9962 merge two shifts into one. */
9963 if (CONST_INT_P (XEXP (varop
, 1))
9964 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9967 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9969 GEN_INT (exact_log2 (
9970 UINTVAL (XEXP (varop
, 1)))));
9976 /* Similar, for when divides are cheaper. */
9977 if (CONST_INT_P (XEXP (varop
, 1))
9978 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9981 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9983 GEN_INT (exact_log2 (
9984 UINTVAL (XEXP (varop
, 1)))));
9990 /* If we are extracting just the sign bit of an arithmetic
9991 right shift, that shift is not needed. However, the sign
9992 bit of a wider mode may be different from what would be
9993 interpreted as the sign bit in a narrower mode, so, if
9994 the result is narrower, don't discard the shift. */
9995 if (code
== LSHIFTRT
9996 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9997 && (GET_MODE_BITSIZE (result_mode
)
9998 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10000 varop
= XEXP (varop
, 0);
10004 /* ... fall through ... */
10009 /* Here we have two nested shifts. The result is usually the
10010 AND of a new shift with a mask. We compute the result below. */
10011 if (CONST_INT_P (XEXP (varop
, 1))
10012 && INTVAL (XEXP (varop
, 1)) >= 0
10013 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10014 && HWI_COMPUTABLE_MODE_P (result_mode
)
10015 && HWI_COMPUTABLE_MODE_P (mode
)
10016 && !VECTOR_MODE_P (result_mode
))
10018 enum rtx_code first_code
= GET_CODE (varop
);
10019 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10020 unsigned HOST_WIDE_INT mask
;
10023 /* We have one common special case. We can't do any merging if
10024 the inner code is an ASHIFTRT of a smaller mode. However, if
10025 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10026 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10027 we can convert it to
10028 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10029 This simplifies certain SIGN_EXTEND operations. */
10030 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10031 && count
== (GET_MODE_PRECISION (result_mode
)
10032 - GET_MODE_PRECISION (GET_MODE (varop
))))
10034 /* C3 has the low-order C1 bits zero. */
10036 mask
= GET_MODE_MASK (mode
)
10037 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10039 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10040 XEXP (varop
, 0), mask
);
10041 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10043 count
= first_count
;
10048 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10049 than C1 high-order bits equal to the sign bit, we can convert
10050 this to either an ASHIFT or an ASHIFTRT depending on the
10053 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10055 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10056 && GET_MODE (varop
) == shift_mode
10057 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10060 varop
= XEXP (varop
, 0);
10061 count
-= first_count
;
10071 /* There are some cases we can't do. If CODE is ASHIFTRT,
10072 we can only do this if FIRST_CODE is also ASHIFTRT.
10074 We can't do the case when CODE is ROTATE and FIRST_CODE is
10077 If the mode of this shift is not the mode of the outer shift,
10078 we can't do this if either shift is a right shift or ROTATE.
10080 Finally, we can't do any of these if the mode is too wide
10081 unless the codes are the same.
10083 Handle the case where the shift codes are the same
10086 if (code
== first_code
)
10088 if (GET_MODE (varop
) != result_mode
10089 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10090 || code
== ROTATE
))
10093 count
+= first_count
;
10094 varop
= XEXP (varop
, 0);
10098 if (code
== ASHIFTRT
10099 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10100 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10101 || (GET_MODE (varop
) != result_mode
10102 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10103 || first_code
== ROTATE
10104 || code
== ROTATE
)))
10107 /* To compute the mask to apply after the shift, shift the
10108 nonzero bits of the inner shift the same way the
10109 outer shift will. */
10111 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10115 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10118 /* Give up if we can't compute an outer operation to use. */
10120 || !CONST_INT_P (mask_rtx
)
10121 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10123 result_mode
, &complement_p
))
10126 /* If the shifts are in the same direction, we add the
10127 counts. Otherwise, we subtract them. */
10128 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10129 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10130 count
+= first_count
;
10132 count
-= first_count
;
10134 /* If COUNT is positive, the new shift is usually CODE,
10135 except for the two exceptions below, in which case it is
10136 FIRST_CODE. If the count is negative, FIRST_CODE should
10139 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10140 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10142 else if (count
< 0)
10143 code
= first_code
, count
= -count
;
10145 varop
= XEXP (varop
, 0);
10149 /* If we have (A << B << C) for any shift, we can convert this to
10150 (A << C << B). This wins if A is a constant. Only try this if
10151 B is not a constant. */
10153 else if (GET_CODE (varop
) == code
10154 && CONST_INT_P (XEXP (varop
, 0))
10155 && !CONST_INT_P (XEXP (varop
, 1)))
10157 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10160 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10167 if (VECTOR_MODE_P (mode
))
10170 /* Make this fit the case below. */
10171 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10177 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10178 with C the size of VAROP - 1 and the shift is logical if
10179 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10180 we have an (le X 0) operation. If we have an arithmetic shift
10181 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10182 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10184 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10185 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10186 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10187 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10188 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10189 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10192 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10195 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10196 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10201 /* If we have (shift (logical)), move the logical to the outside
10202 to allow it to possibly combine with another logical and the
10203 shift to combine with another shift. This also canonicalizes to
10204 what a ZERO_EXTRACT looks like. Also, some machines have
10205 (and (shift)) insns. */
10207 if (CONST_INT_P (XEXP (varop
, 1))
10208 /* We can't do this if we have (ashiftrt (xor)) and the
10209 constant has its sign bit set in shift_mode. */
10210 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10211 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10213 && (new_rtx
= simplify_const_binary_operation
10214 (code
, result_mode
,
10215 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10216 GEN_INT (count
))) != 0
10217 && CONST_INT_P (new_rtx
)
10218 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10219 INTVAL (new_rtx
), result_mode
, &complement_p
))
10221 varop
= XEXP (varop
, 0);
10225 /* If we can't do that, try to simplify the shift in each arm of the
10226 logical expression, make a new logical expression, and apply
10227 the inverse distributive law. This also can't be done
10228 for some (ashiftrt (xor)). */
10229 if (CONST_INT_P (XEXP (varop
, 1))
10230 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10231 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10234 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10235 XEXP (varop
, 0), count
);
10236 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10237 XEXP (varop
, 1), count
);
10239 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10241 varop
= apply_distributive_law (varop
);
10249 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10250 says that the sign bit can be tested, FOO has mode MODE, C is
10251 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10252 that may be nonzero. */
10253 if (code
== LSHIFTRT
10254 && XEXP (varop
, 1) == const0_rtx
10255 && GET_MODE (XEXP (varop
, 0)) == result_mode
10256 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10257 && HWI_COMPUTABLE_MODE_P (result_mode
)
10258 && STORE_FLAG_VALUE
== -1
10259 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10260 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10263 varop
= XEXP (varop
, 0);
10270 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10271 than the number of bits in the mode is equivalent to A. */
10272 if (code
== LSHIFTRT
10273 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10274 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10276 varop
= XEXP (varop
, 0);
10281 /* NEG commutes with ASHIFT since it is multiplication. Move the
10282 NEG outside to allow shifts to combine. */
10284 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10287 varop
= XEXP (varop
, 0);
10293 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10294 is one less than the number of bits in the mode is
10295 equivalent to (xor A 1). */
10296 if (code
== LSHIFTRT
10297 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10298 && XEXP (varop
, 1) == constm1_rtx
10299 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10300 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10304 varop
= XEXP (varop
, 0);
10308 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10309 that might be nonzero in BAR are those being shifted out and those
10310 bits are known zero in FOO, we can replace the PLUS with FOO.
10311 Similarly in the other operand order. This code occurs when
10312 we are computing the size of a variable-size array. */
10314 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10315 && count
< HOST_BITS_PER_WIDE_INT
10316 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10317 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10318 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10320 varop
= XEXP (varop
, 0);
10323 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10324 && count
< HOST_BITS_PER_WIDE_INT
10325 && HWI_COMPUTABLE_MODE_P (result_mode
)
10326 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10328 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10329 & nonzero_bits (XEXP (varop
, 1),
10332 varop
= XEXP (varop
, 1);
10336 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10338 && CONST_INT_P (XEXP (varop
, 1))
10339 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10341 GEN_INT (count
))) != 0
10342 && CONST_INT_P (new_rtx
)
10343 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10344 INTVAL (new_rtx
), result_mode
, &complement_p
))
10346 varop
= XEXP (varop
, 0);
10350 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10351 signbit', and attempt to change the PLUS to an XOR and move it to
10352 the outer operation as is done above in the AND/IOR/XOR case
10353 leg for shift(logical). See details in logical handling above
10354 for reasoning in doing so. */
10355 if (code
== LSHIFTRT
10356 && CONST_INT_P (XEXP (varop
, 1))
10357 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10358 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10360 GEN_INT (count
))) != 0
10361 && CONST_INT_P (new_rtx
)
10362 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10363 INTVAL (new_rtx
), result_mode
, &complement_p
))
10365 varop
= XEXP (varop
, 0);
10372 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10373 with C the size of VAROP - 1 and the shift is logical if
10374 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10375 we have a (gt X 0) operation. If the shift is arithmetic with
10376 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10377 we have a (neg (gt X 0)) operation. */
10379 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10380 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10381 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10382 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10383 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10384 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10385 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10388 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10391 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10392 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10399 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10400 if the truncate does not affect the value. */
10401 if (code
== LSHIFTRT
10402 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10403 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10404 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10405 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10406 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10408 rtx varop_inner
= XEXP (varop
, 0);
10411 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10412 XEXP (varop_inner
, 0),
10414 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10415 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10428 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10429 outer_op
, outer_const
);
10431 /* We have now finished analyzing the shift. The result should be
10432 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10433 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10434 to the result of the shift. OUTER_CONST is the relevant constant,
10435 but we must turn off all bits turned off in the shift. */
10437 if (outer_op
== UNKNOWN
10438 && orig_code
== code
&& orig_count
== count
10439 && varop
== orig_varop
10440 && shift_mode
== GET_MODE (varop
))
10443 /* Make a SUBREG if necessary. If we can't make it, fail. */
10444 varop
= gen_lowpart (shift_mode
, varop
);
10445 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10448 /* If we have an outer operation and we just made a shift, it is
10449 possible that we could have simplified the shift were it not
10450 for the outer operation. So try to do the simplification
10453 if (outer_op
!= UNKNOWN
)
10454 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10459 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10461 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10462 turn off all the bits that the shift would have turned off. */
10463 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10464 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10465 GET_MODE_MASK (result_mode
) >> orig_count
);
10467 /* Do the remainder of the processing in RESULT_MODE. */
10468 x
= gen_lowpart_or_truncate (result_mode
, x
);
10470 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10473 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10475 if (outer_op
!= UNKNOWN
)
10477 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10478 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10479 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10481 if (outer_op
== AND
)
10482 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10483 else if (outer_op
== SET
)
10485 /* This means that we have determined that the result is
10486 equivalent to a constant. This should be rare. */
10487 if (!side_effects_p (x
))
10488 x
= GEN_INT (outer_const
);
10490 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10491 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10493 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10494 GEN_INT (outer_const
));
10500 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10501 The result of the shift is RESULT_MODE. If we cannot simplify it,
10502 return X or, if it is NULL, synthesize the expression with
10503 simplify_gen_binary. Otherwise, return a simplified value.
10505 The shift is normally computed in the widest mode we find in VAROP, as
10506 long as it isn't a different number of words than RESULT_MODE. Exceptions
10507 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10510 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10511 rtx varop
, int count
)
10513 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10518 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10519 if (GET_MODE (x
) != result_mode
)
10520 x
= gen_lowpart (result_mode
, x
);
10525 /* Like recog, but we receive the address of a pointer to a new pattern.
10526 We try to match the rtx that the pointer points to.
10527 If that fails, we may try to modify or replace the pattern,
10528 storing the replacement into the same pointer object.
10530 Modifications include deletion or addition of CLOBBERs.
10532 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10533 the CLOBBERs are placed.
10535 The value is the final insn code from the pattern ultimately matched,
10539 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10541 rtx pat
= *pnewpat
;
10542 rtx pat_without_clobbers
;
10543 int insn_code_number
;
10544 int num_clobbers_to_add
= 0;
10546 rtx notes
= NULL_RTX
;
10547 rtx old_notes
, old_pat
;
10550 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10551 we use to indicate that something didn't match. If we find such a
10552 thing, force rejection. */
10553 if (GET_CODE (pat
) == PARALLEL
)
10554 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10555 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10556 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10559 old_pat
= PATTERN (insn
);
10560 old_notes
= REG_NOTES (insn
);
10561 PATTERN (insn
) = pat
;
10562 REG_NOTES (insn
) = NULL_RTX
;
10564 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10565 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10567 if (insn_code_number
< 0)
10568 fputs ("Failed to match this instruction:\n", dump_file
);
10570 fputs ("Successfully matched this instruction:\n", dump_file
);
10571 print_rtl_single (dump_file
, pat
);
10574 /* If it isn't, there is the possibility that we previously had an insn
10575 that clobbered some register as a side effect, but the combined
10576 insn doesn't need to do that. So try once more without the clobbers
10577 unless this represents an ASM insn. */
10579 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10580 && GET_CODE (pat
) == PARALLEL
)
10584 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10585 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10588 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10592 SUBST_INT (XVECLEN (pat
, 0), pos
);
10595 pat
= XVECEXP (pat
, 0, 0);
10597 PATTERN (insn
) = pat
;
10598 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10599 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10601 if (insn_code_number
< 0)
10602 fputs ("Failed to match this instruction:\n", dump_file
);
10604 fputs ("Successfully matched this instruction:\n", dump_file
);
10605 print_rtl_single (dump_file
, pat
);
10609 pat_without_clobbers
= pat
;
10611 PATTERN (insn
) = old_pat
;
10612 REG_NOTES (insn
) = old_notes
;
10614 /* Recognize all noop sets, these will be killed by followup pass. */
10615 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10616 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10618 /* If we had any clobbers to add, make a new pattern than contains
10619 them. Then check to make sure that all of them are dead. */
10620 if (num_clobbers_to_add
)
10622 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10623 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10624 ? (XVECLEN (pat
, 0)
10625 + num_clobbers_to_add
)
10626 : num_clobbers_to_add
+ 1));
10628 if (GET_CODE (pat
) == PARALLEL
)
10629 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10630 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10632 XVECEXP (newpat
, 0, 0) = pat
;
10634 add_clobbers (newpat
, insn_code_number
);
10636 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10637 i
< XVECLEN (newpat
, 0); i
++)
10639 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10640 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10642 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10644 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10645 notes
= alloc_reg_note (REG_UNUSED
,
10646 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10652 if (insn_code_number
>= 0
10653 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10655 old_pat
= PATTERN (insn
);
10656 old_notes
= REG_NOTES (insn
);
10657 old_icode
= INSN_CODE (insn
);
10658 PATTERN (insn
) = pat
;
10659 REG_NOTES (insn
) = notes
;
10661 /* Allow targets to reject combined insn. */
10662 if (!targetm
.legitimate_combined_insn (insn
))
10664 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10665 fputs ("Instruction not appropriate for target.",
10668 /* Callers expect recog_for_combine to strip
10669 clobbers from the pattern on failure. */
10670 pat
= pat_without_clobbers
;
10673 insn_code_number
= -1;
10676 PATTERN (insn
) = old_pat
;
10677 REG_NOTES (insn
) = old_notes
;
10678 INSN_CODE (insn
) = old_icode
;
10684 return insn_code_number
;
10687 /* Like gen_lowpart_general but for use by combine. In combine it
10688 is not possible to create any new pseudoregs. However, it is
10689 safe to create invalid memory addresses, because combine will
10690 try to recognize them and all they will do is make the combine
10693 If for some reason this cannot do its job, an rtx
10694 (clobber (const_int 0)) is returned.
10695 An insn containing that will not be recognized. */
10698 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10700 enum machine_mode imode
= GET_MODE (x
);
10701 unsigned int osize
= GET_MODE_SIZE (omode
);
10702 unsigned int isize
= GET_MODE_SIZE (imode
);
10705 if (omode
== imode
)
10708 /* We can only support MODE being wider than a word if X is a
10709 constant integer or has a mode the same size. */
10710 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10711 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10714 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10715 won't know what to do. So we will strip off the SUBREG here and
10716 process normally. */
10717 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10719 x
= SUBREG_REG (x
);
10721 /* For use in case we fall down into the address adjustments
10722 further below, we need to adjust the known mode and size of
10723 x; imode and isize, since we just adjusted x. */
10724 imode
= GET_MODE (x
);
10726 if (imode
== omode
)
10729 isize
= GET_MODE_SIZE (imode
);
10732 result
= gen_lowpart_common (omode
, x
);
10741 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10743 if (MEM_VOLATILE_P (x
)
10744 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10747 /* If we want to refer to something bigger than the original memref,
10748 generate a paradoxical subreg instead. That will force a reload
10749 of the original memref X. */
10751 return gen_rtx_SUBREG (omode
, x
, 0);
10753 if (WORDS_BIG_ENDIAN
)
10754 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10756 /* Adjust the address so that the address-after-the-data is
10758 if (BYTES_BIG_ENDIAN
)
10759 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10761 return adjust_address_nv (x
, omode
, offset
);
10764 /* If X is a comparison operator, rewrite it in a new mode. This
10765 probably won't match, but may allow further simplifications. */
10766 else if (COMPARISON_P (x
))
10767 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10769 /* If we couldn't simplify X any other way, just enclose it in a
10770 SUBREG. Normally, this SUBREG won't match, but some patterns may
10771 include an explicit SUBREG or we may simplify it further in combine. */
10777 offset
= subreg_lowpart_offset (omode
, imode
);
10778 if (imode
== VOIDmode
)
10780 imode
= int_mode_for_mode (omode
);
10781 x
= gen_lowpart_common (imode
, x
);
10785 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10791 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10794 /* Try to simplify a comparison between OP0 and a constant OP1,
10795 where CODE is the comparison code that will be tested, into a
10796 (CODE OP0 const0_rtx) form.
10798 The result is a possibly different comparison code to use.
10799 *POP1 may be updated. */
10801 static enum rtx_code
10802 simplify_compare_const (enum rtx_code code
, rtx op0
, rtx
*pop1
)
10804 enum machine_mode mode
= GET_MODE (op0
);
10805 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10806 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10808 /* Get the constant we are comparing against and turn off all bits
10809 not on in our mode. */
10810 if (mode
!= VOIDmode
)
10811 const_op
= trunc_int_for_mode (const_op
, mode
);
10813 /* If we are comparing against a constant power of two and the value
10814 being compared can only have that single bit nonzero (e.g., it was
10815 `and'ed with that bit), we can replace this with a comparison
10818 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10819 || code
== LT
|| code
== LTU
)
10820 && mode_width
<= HOST_BITS_PER_WIDE_INT
10821 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
10822 && (nonzero_bits (op0
, mode
)
10823 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
10825 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10829 /* Similarly, if we are comparing a value known to be either -1 or
10830 0 with -1, change it to the opposite comparison against zero. */
10832 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10833 || code
== GEU
|| code
== LTU
)
10834 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10836 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10840 /* Do some canonicalizations based on the comparison code. We prefer
10841 comparisons against zero and then prefer equality comparisons.
10842 If we can reduce the size of a constant, we will do that too. */
10846 /* < C is equivalent to <= (C - 1) */
10851 /* ... fall through to LE case below. */
10857 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10864 /* If we are doing a <= 0 comparison on a value known to have
10865 a zero sign bit, we can replace this with == 0. */
10866 else if (const_op
== 0
10867 && mode_width
<= HOST_BITS_PER_WIDE_INT
10868 && (nonzero_bits (op0
, mode
)
10869 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10875 /* >= C is equivalent to > (C - 1). */
10880 /* ... fall through to GT below. */
10886 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10893 /* If we are doing a > 0 comparison on a value known to have
10894 a zero sign bit, we can replace this with != 0. */
10895 else if (const_op
== 0
10896 && mode_width
<= HOST_BITS_PER_WIDE_INT
10897 && (nonzero_bits (op0
, mode
)
10898 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10904 /* < C is equivalent to <= (C - 1). */
10909 /* ... fall through ... */
10911 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10912 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10913 && (unsigned HOST_WIDE_INT
) const_op
10914 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10924 /* unsigned <= 0 is equivalent to == 0 */
10927 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10928 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10929 && (unsigned HOST_WIDE_INT
) const_op
10930 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10938 /* >= C is equivalent to > (C - 1). */
10943 /* ... fall through ... */
10946 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10947 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10948 && (unsigned HOST_WIDE_INT
) const_op
10949 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10959 /* unsigned > 0 is equivalent to != 0 */
10962 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10963 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10964 && (unsigned HOST_WIDE_INT
) const_op
10965 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10976 *pop1
= GEN_INT (const_op
);
10980 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10981 comparison code that will be tested.
10983 The result is a possibly different comparison code to use. *POP0 and
10984 *POP1 may be updated.
10986 It is possible that we might detect that a comparison is either always
10987 true or always false. However, we do not perform general constant
10988 folding in combine, so this knowledge isn't useful. Such tautologies
10989 should have been detected earlier. Hence we ignore all such cases. */
10991 static enum rtx_code
10992 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10998 enum machine_mode mode
, tmode
;
11000 /* Try a few ways of applying the same transformation to both operands. */
11003 #ifndef WORD_REGISTER_OPERATIONS
11004 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11005 so check specially. */
11006 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11007 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11008 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11009 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11010 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11011 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11012 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11013 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11014 && CONST_INT_P (XEXP (op0
, 1))
11015 && XEXP (op0
, 1) == XEXP (op1
, 1)
11016 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11017 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11018 && (INTVAL (XEXP (op0
, 1))
11019 == (GET_MODE_PRECISION (GET_MODE (op0
))
11020 - (GET_MODE_PRECISION
11021 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11023 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11024 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11028 /* If both operands are the same constant shift, see if we can ignore the
11029 shift. We can if the shift is a rotate or if the bits shifted out of
11030 this shift are known to be zero for both inputs and if the type of
11031 comparison is compatible with the shift. */
11032 if (GET_CODE (op0
) == GET_CODE (op1
)
11033 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11034 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11035 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11036 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11037 || (GET_CODE (op0
) == ASHIFTRT
11038 && (code
!= GTU
&& code
!= LTU
11039 && code
!= GEU
&& code
!= LEU
)))
11040 && CONST_INT_P (XEXP (op0
, 1))
11041 && INTVAL (XEXP (op0
, 1)) >= 0
11042 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11043 && XEXP (op0
, 1) == XEXP (op1
, 1))
11045 enum machine_mode mode
= GET_MODE (op0
);
11046 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11047 int shift_count
= INTVAL (XEXP (op0
, 1));
11049 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11050 mask
&= (mask
>> shift_count
) << shift_count
;
11051 else if (GET_CODE (op0
) == ASHIFT
)
11052 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11054 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11055 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11056 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11061 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11062 SUBREGs are of the same mode, and, in both cases, the AND would
11063 be redundant if the comparison was done in the narrower mode,
11064 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11065 and the operand's possibly nonzero bits are 0xffffff01; in that case
11066 if we only care about QImode, we don't need the AND). This case
11067 occurs if the output mode of an scc insn is not SImode and
11068 STORE_FLAG_VALUE == 1 (e.g., the 386).
11070 Similarly, check for a case where the AND's are ZERO_EXTEND
11071 operations from some narrower mode even though a SUBREG is not
11074 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11075 && CONST_INT_P (XEXP (op0
, 1))
11076 && CONST_INT_P (XEXP (op1
, 1)))
11078 rtx inner_op0
= XEXP (op0
, 0);
11079 rtx inner_op1
= XEXP (op1
, 0);
11080 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11081 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11084 if (paradoxical_subreg_p (inner_op0
)
11085 && GET_CODE (inner_op1
) == SUBREG
11086 && (GET_MODE (SUBREG_REG (inner_op0
))
11087 == GET_MODE (SUBREG_REG (inner_op1
)))
11088 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11089 <= HOST_BITS_PER_WIDE_INT
)
11090 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11091 GET_MODE (SUBREG_REG (inner_op0
)))))
11092 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11093 GET_MODE (SUBREG_REG (inner_op1
))))))
11095 op0
= SUBREG_REG (inner_op0
);
11096 op1
= SUBREG_REG (inner_op1
);
11098 /* The resulting comparison is always unsigned since we masked
11099 off the original sign bit. */
11100 code
= unsigned_condition (code
);
11106 for (tmode
= GET_CLASS_NARROWEST_MODE
11107 (GET_MODE_CLASS (GET_MODE (op0
)));
11108 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11109 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11111 op0
= gen_lowpart (tmode
, inner_op0
);
11112 op1
= gen_lowpart (tmode
, inner_op1
);
11113 code
= unsigned_condition (code
);
11122 /* If both operands are NOT, we can strip off the outer operation
11123 and adjust the comparison code for swapped operands; similarly for
11124 NEG, except that this must be an equality comparison. */
11125 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11126 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11127 && (code
== EQ
|| code
== NE
)))
11128 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11134 /* If the first operand is a constant, swap the operands and adjust the
11135 comparison code appropriately, but don't do this if the second operand
11136 is already a constant integer. */
11137 if (swap_commutative_operands_p (op0
, op1
))
11139 tem
= op0
, op0
= op1
, op1
= tem
;
11140 code
= swap_condition (code
);
11143 /* We now enter a loop during which we will try to simplify the comparison.
11144 For the most part, we only are concerned with comparisons with zero,
11145 but some things may really be comparisons with zero but not start
11146 out looking that way. */
11148 while (CONST_INT_P (op1
))
11150 enum machine_mode mode
= GET_MODE (op0
);
11151 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11152 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11153 int equality_comparison_p
;
11154 int sign_bit_comparison_p
;
11155 int unsigned_comparison_p
;
11156 HOST_WIDE_INT const_op
;
11158 /* We only want to handle integral modes. This catches VOIDmode,
11159 CCmode, and the floating-point modes. An exception is that we
11160 can handle VOIDmode if OP0 is a COMPARE or a comparison
11163 if (GET_MODE_CLASS (mode
) != MODE_INT
11164 && ! (mode
== VOIDmode
11165 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11168 /* Try to simplify the compare to constant, possibly changing the
11169 comparison op, and/or changing op1 to zero. */
11170 code
= simplify_compare_const (code
, op0
, &op1
);
11171 const_op
= INTVAL (op1
);
11173 /* Compute some predicates to simplify code below. */
11175 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11176 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11177 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11180 /* If this is a sign bit comparison and we can do arithmetic in
11181 MODE, say that we will only be needing the sign bit of OP0. */
11182 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11183 op0
= force_to_mode (op0
, mode
,
11184 (unsigned HOST_WIDE_INT
) 1
11185 << (GET_MODE_PRECISION (mode
) - 1),
11188 /* Now try cases based on the opcode of OP0. If none of the cases
11189 does a "continue", we exit this loop immediately after the
11192 switch (GET_CODE (op0
))
11195 /* If we are extracting a single bit from a variable position in
11196 a constant that has only a single bit set and are comparing it
11197 with zero, we can convert this into an equality comparison
11198 between the position and the location of the single bit. */
11199 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11200 have already reduced the shift count modulo the word size. */
11201 if (!SHIFT_COUNT_TRUNCATED
11202 && CONST_INT_P (XEXP (op0
, 0))
11203 && XEXP (op0
, 1) == const1_rtx
11204 && equality_comparison_p
&& const_op
== 0
11205 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11207 if (BITS_BIG_ENDIAN
)
11208 i
= BITS_PER_WORD
- 1 - i
;
11210 op0
= XEXP (op0
, 2);
11214 /* Result is nonzero iff shift count is equal to I. */
11215 code
= reverse_condition (code
);
11219 /* ... fall through ... */
11222 tem
= expand_compound_operation (op0
);
11231 /* If testing for equality, we can take the NOT of the constant. */
11232 if (equality_comparison_p
11233 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11235 op0
= XEXP (op0
, 0);
11240 /* If just looking at the sign bit, reverse the sense of the
11242 if (sign_bit_comparison_p
)
11244 op0
= XEXP (op0
, 0);
11245 code
= (code
== GE
? LT
: GE
);
11251 /* If testing for equality, we can take the NEG of the constant. */
11252 if (equality_comparison_p
11253 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11255 op0
= XEXP (op0
, 0);
11260 /* The remaining cases only apply to comparisons with zero. */
11264 /* When X is ABS or is known positive,
11265 (neg X) is < 0 if and only if X != 0. */
11267 if (sign_bit_comparison_p
11268 && (GET_CODE (XEXP (op0
, 0)) == ABS
11269 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11270 && (nonzero_bits (XEXP (op0
, 0), mode
)
11271 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11274 op0
= XEXP (op0
, 0);
11275 code
= (code
== LT
? NE
: EQ
);
11279 /* If we have NEG of something whose two high-order bits are the
11280 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11281 if (num_sign_bit_copies (op0
, mode
) >= 2)
11283 op0
= XEXP (op0
, 0);
11284 code
= swap_condition (code
);
11290 /* If we are testing equality and our count is a constant, we
11291 can perform the inverse operation on our RHS. */
11292 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11293 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11294 op1
, XEXP (op0
, 1))) != 0)
11296 op0
= XEXP (op0
, 0);
11301 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11302 a particular bit. Convert it to an AND of a constant of that
11303 bit. This will be converted into a ZERO_EXTRACT. */
11304 if (const_op
== 0 && sign_bit_comparison_p
11305 && CONST_INT_P (XEXP (op0
, 1))
11306 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11308 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11309 ((unsigned HOST_WIDE_INT
) 1
11311 - INTVAL (XEXP (op0
, 1)))));
11312 code
= (code
== LT
? NE
: EQ
);
11316 /* Fall through. */
11319 /* ABS is ignorable inside an equality comparison with zero. */
11320 if (const_op
== 0 && equality_comparison_p
)
11322 op0
= XEXP (op0
, 0);
11328 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11329 (compare FOO CONST) if CONST fits in FOO's mode and we
11330 are either testing inequality or have an unsigned
11331 comparison with ZERO_EXTEND or a signed comparison with
11332 SIGN_EXTEND. But don't do it if we don't have a compare
11333 insn of the given mode, since we'd have to revert it
11334 later on, and then we wouldn't know whether to sign- or
11336 mode
= GET_MODE (XEXP (op0
, 0));
11337 if (GET_MODE_CLASS (mode
) == MODE_INT
11338 && ! unsigned_comparison_p
11339 && HWI_COMPUTABLE_MODE_P (mode
)
11340 && trunc_int_for_mode (const_op
, mode
) == const_op
11341 && have_insn_for (COMPARE
, mode
))
11343 op0
= XEXP (op0
, 0);
11349 /* Check for the case where we are comparing A - C1 with C2, that is
11351 (subreg:MODE (plus (A) (-C1))) op (C2)
11353 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11354 comparison in the wider mode. One of the following two conditions
11355 must be true in order for this to be valid:
11357 1. The mode extension results in the same bit pattern being added
11358 on both sides and the comparison is equality or unsigned. As
11359 C2 has been truncated to fit in MODE, the pattern can only be
11362 2. The mode extension results in the sign bit being copied on
11365 The difficulty here is that we have predicates for A but not for
11366 (A - C1) so we need to check that C1 is within proper bounds so
11367 as to perturbate A as little as possible. */
11369 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11370 && subreg_lowpart_p (op0
)
11371 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11372 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11373 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11375 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11376 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11377 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11380 && (unsigned HOST_WIDE_INT
) c1
11381 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11382 && (equality_comparison_p
|| unsigned_comparison_p
)
11383 /* (A - C1) zero-extends if it is positive and sign-extends
11384 if it is negative, C2 both zero- and sign-extends. */
11385 && ((0 == (nonzero_bits (a
, inner_mode
)
11386 & ~GET_MODE_MASK (mode
))
11388 /* (A - C1) sign-extends if it is positive and 1-extends
11389 if it is negative, C2 both sign- and 1-extends. */
11390 || (num_sign_bit_copies (a
, inner_mode
)
11391 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11394 || ((unsigned HOST_WIDE_INT
) c1
11395 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11396 /* (A - C1) always sign-extends, like C2. */
11397 && num_sign_bit_copies (a
, inner_mode
)
11398 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11399 - (mode_width
- 1))))
11401 op0
= SUBREG_REG (op0
);
11406 /* If the inner mode is narrower and we are extracting the low part,
11407 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11408 if (subreg_lowpart_p (op0
)
11409 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11410 /* Fall through */ ;
11414 /* ... fall through ... */
11417 mode
= GET_MODE (XEXP (op0
, 0));
11418 if (GET_MODE_CLASS (mode
) == MODE_INT
11419 && (unsigned_comparison_p
|| equality_comparison_p
)
11420 && HWI_COMPUTABLE_MODE_P (mode
)
11421 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11423 && have_insn_for (COMPARE
, mode
))
11425 op0
= XEXP (op0
, 0);
11431 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11432 this for equality comparisons due to pathological cases involving
11434 if (equality_comparison_p
11435 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11436 op1
, XEXP (op0
, 1))))
11438 op0
= XEXP (op0
, 0);
11443 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11444 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11445 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11447 op0
= XEXP (XEXP (op0
, 0), 0);
11448 code
= (code
== LT
? EQ
: NE
);
11454 /* We used to optimize signed comparisons against zero, but that
11455 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11456 arrive here as equality comparisons, or (GEU, LTU) are
11457 optimized away. No need to special-case them. */
11459 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11460 (eq B (minus A C)), whichever simplifies. We can only do
11461 this for equality comparisons due to pathological cases involving
11463 if (equality_comparison_p
11464 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11465 XEXP (op0
, 1), op1
)))
11467 op0
= XEXP (op0
, 0);
11472 if (equality_comparison_p
11473 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11474 XEXP (op0
, 0), op1
)))
11476 op0
= XEXP (op0
, 1);
11481 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11482 of bits in X minus 1, is one iff X > 0. */
11483 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11484 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11485 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11486 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11488 op0
= XEXP (op0
, 1);
11489 code
= (code
== GE
? LE
: GT
);
11495 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11496 if C is zero or B is a constant. */
11497 if (equality_comparison_p
11498 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11499 XEXP (op0
, 1), op1
)))
11501 op0
= XEXP (op0
, 0);
11508 case UNEQ
: case LTGT
:
11509 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11510 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11511 case UNORDERED
: case ORDERED
:
11512 /* We can't do anything if OP0 is a condition code value, rather
11513 than an actual data value. */
11515 || CC0_P (XEXP (op0
, 0))
11516 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11519 /* Get the two operands being compared. */
11520 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11521 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11523 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11525 /* Check for the cases where we simply want the result of the
11526 earlier test or the opposite of that result. */
11527 if (code
== NE
|| code
== EQ
11528 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11529 && (code
== LT
|| code
== GE
)))
11531 enum rtx_code new_code
;
11532 if (code
== LT
|| code
== NE
)
11533 new_code
= GET_CODE (op0
);
11535 new_code
= reversed_comparison_code (op0
, NULL
);
11537 if (new_code
!= UNKNOWN
)
11548 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11550 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11551 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11552 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11554 op0
= XEXP (op0
, 1);
11555 code
= (code
== GE
? GT
: LE
);
11561 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11562 will be converted to a ZERO_EXTRACT later. */
11563 if (const_op
== 0 && equality_comparison_p
11564 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11565 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11567 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11568 XEXP (XEXP (op0
, 0), 1));
11569 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11573 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11574 zero and X is a comparison and C1 and C2 describe only bits set
11575 in STORE_FLAG_VALUE, we can compare with X. */
11576 if (const_op
== 0 && equality_comparison_p
11577 && mode_width
<= HOST_BITS_PER_WIDE_INT
11578 && CONST_INT_P (XEXP (op0
, 1))
11579 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11580 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11581 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11582 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11584 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11585 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11586 if ((~STORE_FLAG_VALUE
& mask
) == 0
11587 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11588 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11589 && COMPARISON_P (tem
))))
11591 op0
= XEXP (XEXP (op0
, 0), 0);
11596 /* If we are doing an equality comparison of an AND of a bit equal
11597 to the sign bit, replace this with a LT or GE comparison of
11598 the underlying value. */
11599 if (equality_comparison_p
11601 && CONST_INT_P (XEXP (op0
, 1))
11602 && mode_width
<= HOST_BITS_PER_WIDE_INT
11603 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11604 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11606 op0
= XEXP (op0
, 0);
11607 code
= (code
== EQ
? GE
: LT
);
11611 /* If this AND operation is really a ZERO_EXTEND from a narrower
11612 mode, the constant fits within that mode, and this is either an
11613 equality or unsigned comparison, try to do this comparison in
11618 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11619 -> (ne:DI (reg:SI 4) (const_int 0))
11621 unless TRULY_NOOP_TRUNCATION allows it or the register is
11622 known to hold a value of the required mode the
11623 transformation is invalid. */
11624 if ((equality_comparison_p
|| unsigned_comparison_p
)
11625 && CONST_INT_P (XEXP (op0
, 1))
11626 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11627 & GET_MODE_MASK (mode
))
11629 && const_op
>> i
== 0
11630 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11631 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11632 || (REG_P (XEXP (op0
, 0))
11633 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11635 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11639 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11640 fits in both M1 and M2 and the SUBREG is either paradoxical
11641 or represents the low part, permute the SUBREG and the AND
11643 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11645 unsigned HOST_WIDE_INT c1
;
11646 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11647 /* Require an integral mode, to avoid creating something like
11649 if (SCALAR_INT_MODE_P (tmode
)
11650 /* It is unsafe to commute the AND into the SUBREG if the
11651 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11652 not defined. As originally written the upper bits
11653 have a defined value due to the AND operation.
11654 However, if we commute the AND inside the SUBREG then
11655 they no longer have defined values and the meaning of
11656 the code has been changed. */
11658 #ifdef WORD_REGISTER_OPERATIONS
11659 || (mode_width
> GET_MODE_PRECISION (tmode
)
11660 && mode_width
<= BITS_PER_WORD
)
11662 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11663 && subreg_lowpart_p (XEXP (op0
, 0))))
11664 && CONST_INT_P (XEXP (op0
, 1))
11665 && mode_width
<= HOST_BITS_PER_WIDE_INT
11666 && HWI_COMPUTABLE_MODE_P (tmode
)
11667 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11668 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11670 && c1
!= GET_MODE_MASK (tmode
))
11672 op0
= simplify_gen_binary (AND
, tmode
,
11673 SUBREG_REG (XEXP (op0
, 0)),
11674 gen_int_mode (c1
, tmode
));
11675 op0
= gen_lowpart (mode
, op0
);
11680 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11681 if (const_op
== 0 && equality_comparison_p
11682 && XEXP (op0
, 1) == const1_rtx
11683 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11685 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11686 XEXP (XEXP (op0
, 0), 0), 1);
11687 code
= (code
== NE
? EQ
: NE
);
11691 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11692 (eq (and (lshiftrt X) 1) 0).
11693 Also handle the case where (not X) is expressed using xor. */
11694 if (const_op
== 0 && equality_comparison_p
11695 && XEXP (op0
, 1) == const1_rtx
11696 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11698 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11699 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11701 if (GET_CODE (shift_op
) == NOT
11702 || (GET_CODE (shift_op
) == XOR
11703 && CONST_INT_P (XEXP (shift_op
, 1))
11704 && CONST_INT_P (shift_count
)
11705 && HWI_COMPUTABLE_MODE_P (mode
)
11706 && (UINTVAL (XEXP (shift_op
, 1))
11707 == (unsigned HOST_WIDE_INT
) 1
11708 << INTVAL (shift_count
))))
11711 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11712 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11713 code
= (code
== NE
? EQ
: NE
);
11720 /* If we have (compare (ashift FOO N) (const_int C)) and
11721 the high order N bits of FOO (N+1 if an inequality comparison)
11722 are known to be zero, we can do this by comparing FOO with C
11723 shifted right N bits so long as the low-order N bits of C are
11725 if (CONST_INT_P (XEXP (op0
, 1))
11726 && INTVAL (XEXP (op0
, 1)) >= 0
11727 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11728 < HOST_BITS_PER_WIDE_INT
)
11729 && (((unsigned HOST_WIDE_INT
) const_op
11730 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11732 && mode_width
<= HOST_BITS_PER_WIDE_INT
11733 && (nonzero_bits (XEXP (op0
, 0), mode
)
11734 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11735 + ! equality_comparison_p
))) == 0)
11737 /* We must perform a logical shift, not an arithmetic one,
11738 as we want the top N bits of C to be zero. */
11739 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11741 temp
>>= INTVAL (XEXP (op0
, 1));
11742 op1
= gen_int_mode (temp
, mode
);
11743 op0
= XEXP (op0
, 0);
11747 /* If we are doing a sign bit comparison, it means we are testing
11748 a particular bit. Convert it to the appropriate AND. */
11749 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11750 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11752 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11753 ((unsigned HOST_WIDE_INT
) 1
11755 - INTVAL (XEXP (op0
, 1)))));
11756 code
= (code
== LT
? NE
: EQ
);
11760 /* If this an equality comparison with zero and we are shifting
11761 the low bit to the sign bit, we can convert this to an AND of the
11763 if (const_op
== 0 && equality_comparison_p
11764 && CONST_INT_P (XEXP (op0
, 1))
11765 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11767 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11773 /* If this is an equality comparison with zero, we can do this
11774 as a logical shift, which might be much simpler. */
11775 if (equality_comparison_p
&& const_op
== 0
11776 && CONST_INT_P (XEXP (op0
, 1)))
11778 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11780 INTVAL (XEXP (op0
, 1)));
11784 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11785 do the comparison in a narrower mode. */
11786 if (! unsigned_comparison_p
11787 && CONST_INT_P (XEXP (op0
, 1))
11788 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11789 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11790 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11791 MODE_INT
, 1)) != BLKmode
11792 && (((unsigned HOST_WIDE_INT
) const_op
11793 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11794 <= GET_MODE_MASK (tmode
)))
11796 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11800 /* Likewise if OP0 is a PLUS of a sign extension with a
11801 constant, which is usually represented with the PLUS
11802 between the shifts. */
11803 if (! unsigned_comparison_p
11804 && CONST_INT_P (XEXP (op0
, 1))
11805 && GET_CODE (XEXP (op0
, 0)) == PLUS
11806 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11807 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11808 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11809 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11810 MODE_INT
, 1)) != BLKmode
11811 && (((unsigned HOST_WIDE_INT
) const_op
11812 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11813 <= GET_MODE_MASK (tmode
)))
11815 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11816 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11817 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11818 add_const
, XEXP (op0
, 1));
11820 op0
= simplify_gen_binary (PLUS
, tmode
,
11821 gen_lowpart (tmode
, inner
),
11826 /* ... fall through ... */
11828 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11829 the low order N bits of FOO are known to be zero, we can do this
11830 by comparing FOO with C shifted left N bits so long as no
11831 overflow occurs. Even if the low order N bits of FOO aren't known
11832 to be zero, if the comparison is >= or < we can use the same
11833 optimization and for > or <= by setting all the low
11834 order N bits in the comparison constant. */
11835 if (CONST_INT_P (XEXP (op0
, 1))
11836 && INTVAL (XEXP (op0
, 1)) > 0
11837 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11838 && mode_width
<= HOST_BITS_PER_WIDE_INT
11839 && (((unsigned HOST_WIDE_INT
) const_op
11840 + (GET_CODE (op0
) != LSHIFTRT
11841 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11844 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11846 unsigned HOST_WIDE_INT low_bits
11847 = (nonzero_bits (XEXP (op0
, 0), mode
)
11848 & (((unsigned HOST_WIDE_INT
) 1
11849 << INTVAL (XEXP (op0
, 1))) - 1));
11850 if (low_bits
== 0 || !equality_comparison_p
)
11852 /* If the shift was logical, then we must make the condition
11854 if (GET_CODE (op0
) == LSHIFTRT
)
11855 code
= unsigned_condition (code
);
11857 const_op
<<= INTVAL (XEXP (op0
, 1));
11859 && (code
== GT
|| code
== GTU
11860 || code
== LE
|| code
== LEU
))
11862 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11863 op1
= GEN_INT (const_op
);
11864 op0
= XEXP (op0
, 0);
11869 /* If we are using this shift to extract just the sign bit, we
11870 can replace this with an LT or GE comparison. */
11872 && (equality_comparison_p
|| sign_bit_comparison_p
)
11873 && CONST_INT_P (XEXP (op0
, 1))
11874 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11876 op0
= XEXP (op0
, 0);
11877 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11889 /* Now make any compound operations involved in this comparison. Then,
11890 check for an outmost SUBREG on OP0 that is not doing anything or is
11891 paradoxical. The latter transformation must only be performed when
11892 it is known that the "extra" bits will be the same in op0 and op1 or
11893 that they don't matter. There are three cases to consider:
11895 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11896 care bits and we can assume they have any convenient value. So
11897 making the transformation is safe.
11899 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11900 In this case the upper bits of op0 are undefined. We should not make
11901 the simplification in that case as we do not know the contents of
11904 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11905 UNKNOWN. In that case we know those bits are zeros or ones. We must
11906 also be sure that they are the same as the upper bits of op1.
11908 We can never remove a SUBREG for a non-equality comparison because
11909 the sign bit is in a different place in the underlying object. */
11911 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11912 op1
= make_compound_operation (op1
, SET
);
11914 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11915 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11916 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11917 && (code
== NE
|| code
== EQ
))
11919 if (paradoxical_subreg_p (op0
))
11921 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11923 if (REG_P (SUBREG_REG (op0
)))
11925 op0
= SUBREG_REG (op0
);
11926 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11929 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
11930 <= HOST_BITS_PER_WIDE_INT
)
11931 && (nonzero_bits (SUBREG_REG (op0
),
11932 GET_MODE (SUBREG_REG (op0
)))
11933 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11935 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11937 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11938 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11939 op0
= SUBREG_REG (op0
), op1
= tem
;
11943 /* We now do the opposite procedure: Some machines don't have compare
11944 insns in all modes. If OP0's mode is an integer mode smaller than a
11945 word and we can't do a compare in that mode, see if there is a larger
11946 mode for which we can do the compare. There are a number of cases in
11947 which we can use the wider mode. */
11949 mode
= GET_MODE (op0
);
11950 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11951 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11952 && ! have_insn_for (COMPARE
, mode
))
11953 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11954 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
11955 tmode
= GET_MODE_WIDER_MODE (tmode
))
11956 if (have_insn_for (COMPARE
, tmode
))
11960 /* If this is a test for negative, we can make an explicit
11961 test of the sign bit. Test this first so we can use
11962 a paradoxical subreg to extend OP0. */
11964 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11965 && HWI_COMPUTABLE_MODE_P (mode
))
11967 unsigned HOST_WIDE_INT sign
11968 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
11969 op0
= simplify_gen_binary (AND
, tmode
,
11970 gen_lowpart (tmode
, op0
),
11971 gen_int_mode (sign
, mode
));
11972 code
= (code
== LT
) ? NE
: EQ
;
11976 /* If the only nonzero bits in OP0 and OP1 are those in the
11977 narrower mode and this is an equality or unsigned comparison,
11978 we can use the wider mode. Similarly for sign-extended
11979 values, in which case it is true for all comparisons. */
11980 zero_extended
= ((code
== EQ
|| code
== NE
11981 || code
== GEU
|| code
== GTU
11982 || code
== LEU
|| code
== LTU
)
11983 && (nonzero_bits (op0
, tmode
)
11984 & ~GET_MODE_MASK (mode
)) == 0
11985 && ((CONST_INT_P (op1
)
11986 || (nonzero_bits (op1
, tmode
)
11987 & ~GET_MODE_MASK (mode
)) == 0)));
11990 || ((num_sign_bit_copies (op0
, tmode
)
11991 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11992 - GET_MODE_PRECISION (mode
)))
11993 && (num_sign_bit_copies (op1
, tmode
)
11994 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11995 - GET_MODE_PRECISION (mode
)))))
11997 /* If OP0 is an AND and we don't have an AND in MODE either,
11998 make a new AND in the proper mode. */
11999 if (GET_CODE (op0
) == AND
12000 && !have_insn_for (AND
, mode
))
12001 op0
= simplify_gen_binary (AND
, tmode
,
12002 gen_lowpart (tmode
,
12004 gen_lowpart (tmode
,
12010 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12011 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12015 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12016 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12023 /* We may have changed the comparison operands. Re-canonicalize. */
12024 if (swap_commutative_operands_p (op0
, op1
))
12026 tem
= op0
, op0
= op1
, op1
= tem
;
12027 code
= swap_condition (code
);
12030 /* If this machine only supports a subset of valid comparisons, see if we
12031 can convert an unsupported one into a supported one. */
12032 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12040 /* Utility function for record_value_for_reg. Count number of
12045 enum rtx_code code
= GET_CODE (x
);
12049 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12050 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12052 rtx x0
= XEXP (x
, 0);
12053 rtx x1
= XEXP (x
, 1);
12056 return 1 + 2 * count_rtxs (x0
);
12058 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12059 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12060 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12061 return 2 + 2 * count_rtxs (x0
)
12062 + count_rtxs (x
== XEXP (x1
, 0)
12063 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12065 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12066 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12067 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12068 return 2 + 2 * count_rtxs (x1
)
12069 + count_rtxs (x
== XEXP (x0
, 0)
12070 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12073 fmt
= GET_RTX_FORMAT (code
);
12074 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12076 ret
+= count_rtxs (XEXP (x
, i
));
12077 else if (fmt
[i
] == 'E')
12078 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12079 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12084 /* Utility function for following routine. Called when X is part of a value
12085 being stored into last_set_value. Sets last_set_table_tick
12086 for each register mentioned. Similar to mention_regs in cse.c */
12089 update_table_tick (rtx x
)
12091 enum rtx_code code
= GET_CODE (x
);
12092 const char *fmt
= GET_RTX_FORMAT (code
);
12097 unsigned int regno
= REGNO (x
);
12098 unsigned int endregno
= END_REGNO (x
);
12101 for (r
= regno
; r
< endregno
; r
++)
12103 reg_stat_type
*rsp
= ®_stat
[r
];
12104 rsp
->last_set_table_tick
= label_tick
;
12110 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12113 /* Check for identical subexpressions. If x contains
12114 identical subexpression we only have to traverse one of
12116 if (i
== 0 && ARITHMETIC_P (x
))
12118 /* Note that at this point x1 has already been
12120 rtx x0
= XEXP (x
, 0);
12121 rtx x1
= XEXP (x
, 1);
12123 /* If x0 and x1 are identical then there is no need to
12128 /* If x0 is identical to a subexpression of x1 then while
12129 processing x1, x0 has already been processed. Thus we
12130 are done with x. */
12131 if (ARITHMETIC_P (x1
)
12132 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12135 /* If x1 is identical to a subexpression of x0 then we
12136 still have to process the rest of x0. */
12137 if (ARITHMETIC_P (x0
)
12138 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12140 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12145 update_table_tick (XEXP (x
, i
));
12147 else if (fmt
[i
] == 'E')
12148 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12149 update_table_tick (XVECEXP (x
, i
, j
));
12152 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12153 are saying that the register is clobbered and we no longer know its
12154 value. If INSN is zero, don't update reg_stat[].last_set; this is
12155 only permitted with VALUE also zero and is used to invalidate the
12159 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12161 unsigned int regno
= REGNO (reg
);
12162 unsigned int endregno
= END_REGNO (reg
);
12164 reg_stat_type
*rsp
;
12166 /* If VALUE contains REG and we have a previous value for REG, substitute
12167 the previous value. */
12168 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12172 /* Set things up so get_last_value is allowed to see anything set up to
12174 subst_low_luid
= DF_INSN_LUID (insn
);
12175 tem
= get_last_value (reg
);
12177 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12178 it isn't going to be useful and will take a lot of time to process,
12179 so just use the CLOBBER. */
12183 if (ARITHMETIC_P (tem
)
12184 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12185 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12186 tem
= XEXP (tem
, 0);
12187 else if (count_occurrences (value
, reg
, 1) >= 2)
12189 /* If there are two or more occurrences of REG in VALUE,
12190 prevent the value from growing too much. */
12191 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12192 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12195 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12199 /* For each register modified, show we don't know its value, that
12200 we don't know about its bitwise content, that its value has been
12201 updated, and that we don't know the location of the death of the
12203 for (i
= regno
; i
< endregno
; i
++)
12205 rsp
= ®_stat
[i
];
12208 rsp
->last_set
= insn
;
12210 rsp
->last_set_value
= 0;
12211 rsp
->last_set_mode
= VOIDmode
;
12212 rsp
->last_set_nonzero_bits
= 0;
12213 rsp
->last_set_sign_bit_copies
= 0;
12214 rsp
->last_death
= 0;
12215 rsp
->truncated_to_mode
= VOIDmode
;
12218 /* Mark registers that are being referenced in this value. */
12220 update_table_tick (value
);
12222 /* Now update the status of each register being set.
12223 If someone is using this register in this block, set this register
12224 to invalid since we will get confused between the two lives in this
12225 basic block. This makes using this register always invalid. In cse, we
12226 scan the table to invalidate all entries using this register, but this
12227 is too much work for us. */
12229 for (i
= regno
; i
< endregno
; i
++)
12231 rsp
= ®_stat
[i
];
12232 rsp
->last_set_label
= label_tick
;
12234 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12235 rsp
->last_set_invalid
= 1;
12237 rsp
->last_set_invalid
= 0;
12240 /* The value being assigned might refer to X (like in "x++;"). In that
12241 case, we must replace it with (clobber (const_int 0)) to prevent
12243 rsp
= ®_stat
[regno
];
12244 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12246 value
= copy_rtx (value
);
12247 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12251 /* For the main register being modified, update the value, the mode, the
12252 nonzero bits, and the number of sign bit copies. */
12254 rsp
->last_set_value
= value
;
12258 enum machine_mode mode
= GET_MODE (reg
);
12259 subst_low_luid
= DF_INSN_LUID (insn
);
12260 rsp
->last_set_mode
= mode
;
12261 if (GET_MODE_CLASS (mode
) == MODE_INT
12262 && HWI_COMPUTABLE_MODE_P (mode
))
12263 mode
= nonzero_bits_mode
;
12264 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12265 rsp
->last_set_sign_bit_copies
12266 = num_sign_bit_copies (value
, GET_MODE (reg
));
12270 /* Called via note_stores from record_dead_and_set_regs to handle one
12271 SET or CLOBBER in an insn. DATA is the instruction in which the
12272 set is occurring. */
12275 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12277 rtx record_dead_insn
= (rtx
) data
;
12279 if (GET_CODE (dest
) == SUBREG
)
12280 dest
= SUBREG_REG (dest
);
12282 if (!record_dead_insn
)
12285 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12291 /* If we are setting the whole register, we know its value. Otherwise
12292 show that we don't know the value. We can handle SUBREG in
12294 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12295 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12296 else if (GET_CODE (setter
) == SET
12297 && GET_CODE (SET_DEST (setter
)) == SUBREG
12298 && SUBREG_REG (SET_DEST (setter
)) == dest
12299 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12300 && subreg_lowpart_p (SET_DEST (setter
)))
12301 record_value_for_reg (dest
, record_dead_insn
,
12302 gen_lowpart (GET_MODE (dest
),
12303 SET_SRC (setter
)));
12305 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12307 else if (MEM_P (dest
)
12308 /* Ignore pushes, they clobber nothing. */
12309 && ! push_operand (dest
, GET_MODE (dest
)))
12310 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12313 /* Update the records of when each REG was most recently set or killed
12314 for the things done by INSN. This is the last thing done in processing
12315 INSN in the combiner loop.
12317 We update reg_stat[], in particular fields last_set, last_set_value,
12318 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12319 last_death, and also the similar information mem_last_set (which insn
12320 most recently modified memory) and last_call_luid (which insn was the
12321 most recent subroutine call). */
12324 record_dead_and_set_regs (rtx insn
)
12329 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12331 if (REG_NOTE_KIND (link
) == REG_DEAD
12332 && REG_P (XEXP (link
, 0)))
12334 unsigned int regno
= REGNO (XEXP (link
, 0));
12335 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12337 for (i
= regno
; i
< endregno
; i
++)
12339 reg_stat_type
*rsp
;
12341 rsp
= ®_stat
[i
];
12342 rsp
->last_death
= insn
;
12345 else if (REG_NOTE_KIND (link
) == REG_INC
)
12346 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12351 hard_reg_set_iterator hrsi
;
12352 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12354 reg_stat_type
*rsp
;
12356 rsp
= ®_stat
[i
];
12357 rsp
->last_set_invalid
= 1;
12358 rsp
->last_set
= insn
;
12359 rsp
->last_set_value
= 0;
12360 rsp
->last_set_mode
= VOIDmode
;
12361 rsp
->last_set_nonzero_bits
= 0;
12362 rsp
->last_set_sign_bit_copies
= 0;
12363 rsp
->last_death
= 0;
12364 rsp
->truncated_to_mode
= VOIDmode
;
12367 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12369 /* We can't combine into a call pattern. Remember, though, that
12370 the return value register is set at this LUID. We could
12371 still replace a register with the return value from the
12372 wrong subroutine call! */
12373 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12376 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12379 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12380 register present in the SUBREG, so for each such SUBREG go back and
12381 adjust nonzero and sign bit information of the registers that are
12382 known to have some zero/sign bits set.
12384 This is needed because when combine blows the SUBREGs away, the
12385 information on zero/sign bits is lost and further combines can be
12386 missed because of that. */
12389 record_promoted_value (rtx insn
, rtx subreg
)
12391 struct insn_link
*links
;
12393 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12394 enum machine_mode mode
= GET_MODE (subreg
);
12396 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12399 for (links
= LOG_LINKS (insn
); links
;)
12401 reg_stat_type
*rsp
;
12403 insn
= links
->insn
;
12404 set
= single_set (insn
);
12406 if (! set
|| !REG_P (SET_DEST (set
))
12407 || REGNO (SET_DEST (set
)) != regno
12408 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12410 links
= links
->next
;
12414 rsp
= ®_stat
[regno
];
12415 if (rsp
->last_set
== insn
)
12417 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12418 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12421 if (REG_P (SET_SRC (set
)))
12423 regno
= REGNO (SET_SRC (set
));
12424 links
= LOG_LINKS (insn
);
12431 /* Check if X, a register, is known to contain a value already
12432 truncated to MODE. In this case we can use a subreg to refer to
12433 the truncated value even though in the generic case we would need
12434 an explicit truncation. */
12437 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12439 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12440 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12443 || rsp
->truncation_label
< label_tick_ebb_start
)
12445 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12447 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12452 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12453 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12454 might be able to turn a truncate into a subreg using this information.
12455 Return -1 if traversing *P is complete or 0 otherwise. */
12458 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12461 enum machine_mode truncated_mode
;
12462 reg_stat_type
*rsp
;
12464 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12466 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12467 truncated_mode
= GET_MODE (x
);
12469 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12472 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12475 x
= SUBREG_REG (x
);
12477 /* ??? For hard-regs we now record everything. We might be able to
12478 optimize this using last_set_mode. */
12479 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12480 truncated_mode
= GET_MODE (x
);
12484 rsp
= ®_stat
[REGNO (x
)];
12485 if (rsp
->truncated_to_mode
== 0
12486 || rsp
->truncation_label
< label_tick_ebb_start
12487 || (GET_MODE_SIZE (truncated_mode
)
12488 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12490 rsp
->truncated_to_mode
= truncated_mode
;
12491 rsp
->truncation_label
= label_tick
;
12497 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12498 the modes they are used in. This can help truning TRUNCATEs into
12502 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12504 for_each_rtx (x
, record_truncated_value
, NULL
);
12507 /* Scan X for promoted SUBREGs. For each one found,
12508 note what it implies to the registers used in it. */
12511 check_promoted_subreg (rtx insn
, rtx x
)
12513 if (GET_CODE (x
) == SUBREG
12514 && SUBREG_PROMOTED_VAR_P (x
)
12515 && REG_P (SUBREG_REG (x
)))
12516 record_promoted_value (insn
, x
);
12519 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12522 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12526 check_promoted_subreg (insn
, XEXP (x
, i
));
12530 if (XVEC (x
, i
) != 0)
12531 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12532 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12538 /* Verify that all the registers and memory references mentioned in *LOC are
12539 still valid. *LOC was part of a value set in INSN when label_tick was
12540 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12541 the invalid references with (clobber (const_int 0)) and return 1. This
12542 replacement is useful because we often can get useful information about
12543 the form of a value (e.g., if it was produced by a shift that always
12544 produces -1 or 0) even though we don't know exactly what registers it
12545 was produced from. */
12548 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12551 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12552 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12557 unsigned int regno
= REGNO (x
);
12558 unsigned int endregno
= END_REGNO (x
);
12561 for (j
= regno
; j
< endregno
; j
++)
12563 reg_stat_type
*rsp
= ®_stat
[j
];
12564 if (rsp
->last_set_invalid
12565 /* If this is a pseudo-register that was only set once and not
12566 live at the beginning of the function, it is always valid. */
12567 || (! (regno
>= FIRST_PSEUDO_REGISTER
12568 && REG_N_SETS (regno
) == 1
12569 && (!REGNO_REG_SET_P
12570 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
12572 && rsp
->last_set_label
> tick
))
12575 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12582 /* If this is a memory reference, make sure that there were no stores after
12583 it that might have clobbered the value. We don't have alias info, so we
12584 assume any store invalidates it. Moreover, we only have local UIDs, so
12585 we also assume that there were stores in the intervening basic blocks. */
12586 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12587 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12590 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12594 for (i
= 0; i
< len
; i
++)
12598 /* Check for identical subexpressions. If x contains
12599 identical subexpression we only have to traverse one of
12601 if (i
== 1 && ARITHMETIC_P (x
))
12603 /* Note that at this point x0 has already been checked
12604 and found valid. */
12605 rtx x0
= XEXP (x
, 0);
12606 rtx x1
= XEXP (x
, 1);
12608 /* If x0 and x1 are identical then x is also valid. */
12612 /* If x1 is identical to a subexpression of x0 then
12613 while checking x0, x1 has already been checked. Thus
12614 it is valid and so as x. */
12615 if (ARITHMETIC_P (x0
)
12616 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12619 /* If x0 is identical to a subexpression of x1 then x is
12620 valid iff the rest of x1 is valid. */
12621 if (ARITHMETIC_P (x1
)
12622 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12624 get_last_value_validate (&XEXP (x1
,
12625 x0
== XEXP (x1
, 0) ? 1 : 0),
12626 insn
, tick
, replace
);
12629 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12633 else if (fmt
[i
] == 'E')
12634 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12635 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12636 insn
, tick
, replace
) == 0)
12640 /* If we haven't found a reason for it to be invalid, it is valid. */
12644 /* Get the last value assigned to X, if known. Some registers
12645 in the value may be replaced with (clobber (const_int 0)) if their value
12646 is known longer known reliably. */
12649 get_last_value (const_rtx x
)
12651 unsigned int regno
;
12653 reg_stat_type
*rsp
;
12655 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12656 then convert it to the desired mode. If this is a paradoxical SUBREG,
12657 we cannot predict what values the "extra" bits might have. */
12658 if (GET_CODE (x
) == SUBREG
12659 && subreg_lowpart_p (x
)
12660 && !paradoxical_subreg_p (x
)
12661 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12662 return gen_lowpart (GET_MODE (x
), value
);
12668 rsp
= ®_stat
[regno
];
12669 value
= rsp
->last_set_value
;
12671 /* If we don't have a value, or if it isn't for this basic block and
12672 it's either a hard register, set more than once, or it's a live
12673 at the beginning of the function, return 0.
12675 Because if it's not live at the beginning of the function then the reg
12676 is always set before being used (is never used without being set).
12677 And, if it's set only once, and it's always set before use, then all
12678 uses must have the same last value, even if it's not from this basic
12682 || (rsp
->last_set_label
< label_tick_ebb_start
12683 && (regno
< FIRST_PSEUDO_REGISTER
12684 || REG_N_SETS (regno
) != 1
12686 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
12689 /* If the value was set in a later insn than the ones we are processing,
12690 we can't use it even if the register was only set once. */
12691 if (rsp
->last_set_label
== label_tick
12692 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12695 /* If the value has all its registers valid, return it. */
12696 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12699 /* Otherwise, make a copy and replace any invalid register with
12700 (clobber (const_int 0)). If that fails for some reason, return 0. */
12702 value
= copy_rtx (value
);
12703 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12709 /* Return nonzero if expression X refers to a REG or to memory
12710 that is set in an instruction more recent than FROM_LUID. */
12713 use_crosses_set_p (const_rtx x
, int from_luid
)
12717 enum rtx_code code
= GET_CODE (x
);
12721 unsigned int regno
= REGNO (x
);
12722 unsigned endreg
= END_REGNO (x
);
12724 #ifdef PUSH_ROUNDING
12725 /* Don't allow uses of the stack pointer to be moved,
12726 because we don't know whether the move crosses a push insn. */
12727 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12730 for (; regno
< endreg
; regno
++)
12732 reg_stat_type
*rsp
= ®_stat
[regno
];
12734 && rsp
->last_set_label
== label_tick
12735 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12741 if (code
== MEM
&& mem_last_set
> from_luid
)
12744 fmt
= GET_RTX_FORMAT (code
);
12746 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12751 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12752 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12755 else if (fmt
[i
] == 'e'
12756 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12762 /* Define three variables used for communication between the following
12765 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12766 static int reg_dead_flag
;
12768 /* Function called via note_stores from reg_dead_at_p.
12770 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12771 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12774 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12776 unsigned int regno
, endregno
;
12781 regno
= REGNO (dest
);
12782 endregno
= END_REGNO (dest
);
12783 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12784 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12787 /* Return nonzero if REG is known to be dead at INSN.
12789 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12790 referencing REG, it is dead. If we hit a SET referencing REG, it is
12791 live. Otherwise, see if it is live or dead at the start of the basic
12792 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12793 must be assumed to be always live. */
12796 reg_dead_at_p (rtx reg
, rtx insn
)
12801 /* Set variables for reg_dead_at_p_1. */
12802 reg_dead_regno
= REGNO (reg
);
12803 reg_dead_endregno
= END_REGNO (reg
);
12807 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12808 we allow the machine description to decide whether use-and-clobber
12809 patterns are OK. */
12810 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12812 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12813 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12817 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12818 beginning of basic block. */
12819 block
= BLOCK_FOR_INSN (insn
);
12824 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12826 return reg_dead_flag
== 1 ? 1 : 0;
12828 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12832 if (insn
== BB_HEAD (block
))
12835 insn
= PREV_INSN (insn
);
12838 /* Look at live-in sets for the basic block that we were in. */
12839 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12840 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12846 /* Note hard registers in X that are used. */
12849 mark_used_regs_combine (rtx x
)
12851 RTX_CODE code
= GET_CODE (x
);
12852 unsigned int regno
;
12863 case ADDR_DIFF_VEC
:
12866 /* CC0 must die in the insn after it is set, so we don't need to take
12867 special note of it here. */
12873 /* If we are clobbering a MEM, mark any hard registers inside the
12874 address as used. */
12875 if (MEM_P (XEXP (x
, 0)))
12876 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12881 /* A hard reg in a wide mode may really be multiple registers.
12882 If so, mark all of them just like the first. */
12883 if (regno
< FIRST_PSEUDO_REGISTER
)
12885 /* None of this applies to the stack, frame or arg pointers. */
12886 if (regno
== STACK_POINTER_REGNUM
12887 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12888 || regno
== HARD_FRAME_POINTER_REGNUM
12890 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12891 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12893 || regno
== FRAME_POINTER_REGNUM
)
12896 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12902 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12904 rtx testreg
= SET_DEST (x
);
12906 while (GET_CODE (testreg
) == SUBREG
12907 || GET_CODE (testreg
) == ZERO_EXTRACT
12908 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12909 testreg
= XEXP (testreg
, 0);
12911 if (MEM_P (testreg
))
12912 mark_used_regs_combine (XEXP (testreg
, 0));
12914 mark_used_regs_combine (SET_SRC (x
));
12922 /* Recursively scan the operands of this expression. */
12925 const char *fmt
= GET_RTX_FORMAT (code
);
12927 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12930 mark_used_regs_combine (XEXP (x
, i
));
12931 else if (fmt
[i
] == 'E')
12935 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12936 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12942 /* Remove register number REGNO from the dead registers list of INSN.
12944 Return the note used to record the death, if there was one. */
12947 remove_death (unsigned int regno
, rtx insn
)
12949 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12952 remove_note (insn
, note
);
12957 /* For each register (hardware or pseudo) used within expression X, if its
12958 death is in an instruction with luid between FROM_LUID (inclusive) and
12959 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12960 list headed by PNOTES.
12962 That said, don't move registers killed by maybe_kill_insn.
12964 This is done when X is being merged by combination into TO_INSN. These
12965 notes will then be distributed as needed. */
12968 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12973 enum rtx_code code
= GET_CODE (x
);
12977 unsigned int regno
= REGNO (x
);
12978 rtx where_dead
= reg_stat
[regno
].last_death
;
12980 /* Don't move the register if it gets killed in between from and to. */
12981 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12982 && ! reg_referenced_p (x
, maybe_kill_insn
))
12986 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12987 && DF_INSN_LUID (where_dead
) >= from_luid
12988 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12990 rtx note
= remove_death (regno
, where_dead
);
12992 /* It is possible for the call above to return 0. This can occur
12993 when last_death points to I2 or I1 that we combined with.
12994 In that case make a new note.
12996 We must also check for the case where X is a hard register
12997 and NOTE is a death note for a range of hard registers
12998 including X. In that case, we must put REG_DEAD notes for
12999 the remaining registers in place of NOTE. */
13001 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13002 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13003 > GET_MODE_SIZE (GET_MODE (x
))))
13005 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13006 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
13007 unsigned int ourend
= END_HARD_REGNO (x
);
13010 for (i
= deadregno
; i
< deadend
; i
++)
13011 if (i
< regno
|| i
>= ourend
)
13012 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13015 /* If we didn't find any note, or if we found a REG_DEAD note that
13016 covers only part of the given reg, and we have a multi-reg hard
13017 register, then to be safe we must check for REG_DEAD notes
13018 for each register other than the first. They could have
13019 their own REG_DEAD notes lying around. */
13020 else if ((note
== 0
13022 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13023 < GET_MODE_SIZE (GET_MODE (x
)))))
13024 && regno
< FIRST_PSEUDO_REGISTER
13025 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
13027 unsigned int ourend
= END_HARD_REGNO (x
);
13028 unsigned int i
, offset
;
13032 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13036 for (i
= regno
+ offset
; i
< ourend
; i
++)
13037 move_deaths (regno_reg_rtx
[i
],
13038 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13041 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13043 XEXP (note
, 1) = *pnotes
;
13047 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13053 else if (GET_CODE (x
) == SET
)
13055 rtx dest
= SET_DEST (x
);
13057 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13059 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13060 that accesses one word of a multi-word item, some
13061 piece of everything register in the expression is used by
13062 this insn, so remove any old death. */
13063 /* ??? So why do we test for equality of the sizes? */
13065 if (GET_CODE (dest
) == ZERO_EXTRACT
13066 || GET_CODE (dest
) == STRICT_LOW_PART
13067 || (GET_CODE (dest
) == SUBREG
13068 && (((GET_MODE_SIZE (GET_MODE (dest
))
13069 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13070 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13071 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13073 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13077 /* If this is some other SUBREG, we know it replaces the entire
13078 value, so use that as the destination. */
13079 if (GET_CODE (dest
) == SUBREG
)
13080 dest
= SUBREG_REG (dest
);
13082 /* If this is a MEM, adjust deaths of anything used in the address.
13083 For a REG (the only other possibility), the entire value is
13084 being replaced so the old value is not used in this insn. */
13087 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13092 else if (GET_CODE (x
) == CLOBBER
)
13095 len
= GET_RTX_LENGTH (code
);
13096 fmt
= GET_RTX_FORMAT (code
);
13098 for (i
= 0; i
< len
; i
++)
13103 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13104 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13107 else if (fmt
[i
] == 'e')
13108 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13112 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13113 pattern of an insn. X must be a REG. */
13116 reg_bitfield_target_p (rtx x
, rtx body
)
13120 if (GET_CODE (body
) == SET
)
13122 rtx dest
= SET_DEST (body
);
13124 unsigned int regno
, tregno
, endregno
, endtregno
;
13126 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13127 target
= XEXP (dest
, 0);
13128 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13129 target
= SUBREG_REG (XEXP (dest
, 0));
13133 if (GET_CODE (target
) == SUBREG
)
13134 target
= SUBREG_REG (target
);
13136 if (!REG_P (target
))
13139 tregno
= REGNO (target
), regno
= REGNO (x
);
13140 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13141 return target
== x
;
13143 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13144 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13146 return endregno
> tregno
&& regno
< endtregno
;
13149 else if (GET_CODE (body
) == PARALLEL
)
13150 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13151 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13157 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13158 as appropriate. I3 and I2 are the insns resulting from the combination
13159 insns including FROM (I2 may be zero).
13161 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13162 not need REG_DEAD notes because they are being substituted for. This
13163 saves searching in the most common cases.
13165 Each note in the list is either ignored or placed on some insns, depending
13166 on the type of note. */
13169 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13170 rtx elim_i1
, rtx elim_i0
)
13172 rtx note
, next_note
;
13175 for (note
= notes
; note
; note
= next_note
)
13177 rtx place
= 0, place2
= 0;
13179 next_note
= XEXP (note
, 1);
13180 switch (REG_NOTE_KIND (note
))
13184 /* Doesn't matter much where we put this, as long as it's somewhere.
13185 It is preferable to keep these notes on branches, which is most
13186 likely to be i3. */
13190 case REG_NON_LOCAL_GOTO
:
13195 gcc_assert (i2
&& JUMP_P (i2
));
13200 case REG_EH_REGION
:
13201 /* These notes must remain with the call or trapping instruction. */
13204 else if (i2
&& CALL_P (i2
))
13208 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13209 if (may_trap_p (i3
))
13211 else if (i2
&& may_trap_p (i2
))
13213 /* ??? Otherwise assume we've combined things such that we
13214 can now prove that the instructions can't trap. Drop the
13215 note in this case. */
13219 case REG_ARGS_SIZE
:
13220 /* ??? How to distribute between i3-i1. Assume i3 contains the
13221 entire adjustment. Assert i3 contains at least some adjust. */
13222 if (!noop_move_p (i3
))
13224 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13225 /* fixup_args_size_notes looks at REG_NORETURN note,
13226 so ensure the note is placed there first. */
13230 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13231 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13235 XEXP (n
, 1) = REG_NOTES (i3
);
13236 REG_NOTES (i3
) = n
;
13240 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13241 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13242 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13243 gcc_assert (old_size
!= args_size
13245 && !ACCUMULATE_OUTGOING_ARGS
13246 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13253 /* These notes must remain with the call. It should not be
13254 possible for both I2 and I3 to be a call. */
13259 gcc_assert (i2
&& CALL_P (i2
));
13265 /* Any clobbers for i3 may still exist, and so we must process
13266 REG_UNUSED notes from that insn.
13268 Any clobbers from i2 or i1 can only exist if they were added by
13269 recog_for_combine. In that case, recog_for_combine created the
13270 necessary REG_UNUSED notes. Trying to keep any original
13271 REG_UNUSED notes from these insns can cause incorrect output
13272 if it is for the same register as the original i3 dest.
13273 In that case, we will notice that the register is set in i3,
13274 and then add a REG_UNUSED note for the destination of i3, which
13275 is wrong. However, it is possible to have REG_UNUSED notes from
13276 i2 or i1 for register which were both used and clobbered, so
13277 we keep notes from i2 or i1 if they will turn into REG_DEAD
13280 /* If this register is set or clobbered in I3, put the note there
13281 unless there is one already. */
13282 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13284 if (from_insn
!= i3
)
13287 if (! (REG_P (XEXP (note
, 0))
13288 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13289 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13292 /* Otherwise, if this register is used by I3, then this register
13293 now dies here, so we must put a REG_DEAD note here unless there
13295 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13296 && ! (REG_P (XEXP (note
, 0))
13297 ? find_regno_note (i3
, REG_DEAD
,
13298 REGNO (XEXP (note
, 0)))
13299 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13301 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13309 /* These notes say something about results of an insn. We can
13310 only support them if they used to be on I3 in which case they
13311 remain on I3. Otherwise they are ignored.
13313 If the note refers to an expression that is not a constant, we
13314 must also ignore the note since we cannot tell whether the
13315 equivalence is still true. It might be possible to do
13316 slightly better than this (we only have a problem if I2DEST
13317 or I1DEST is present in the expression), but it doesn't
13318 seem worth the trouble. */
13320 if (from_insn
== i3
13321 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13326 /* These notes say something about how a register is used. They must
13327 be present on any use of the register in I2 or I3. */
13328 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13331 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13340 case REG_LABEL_TARGET
:
13341 case REG_LABEL_OPERAND
:
13342 /* This can show up in several ways -- either directly in the
13343 pattern, or hidden off in the constant pool with (or without?)
13344 a REG_EQUAL note. */
13345 /* ??? Ignore the without-reg_equal-note problem for now. */
13346 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13347 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13348 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13349 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13353 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13354 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13355 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13356 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13364 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13365 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13367 if (place
&& JUMP_P (place
)
13368 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13369 && (JUMP_LABEL (place
) == NULL
13370 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13372 rtx label
= JUMP_LABEL (place
);
13375 JUMP_LABEL (place
) = XEXP (note
, 0);
13376 else if (LABEL_P (label
))
13377 LABEL_NUSES (label
)--;
13380 if (place2
&& JUMP_P (place2
)
13381 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13382 && (JUMP_LABEL (place2
) == NULL
13383 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13385 rtx label
= JUMP_LABEL (place2
);
13388 JUMP_LABEL (place2
) = XEXP (note
, 0);
13389 else if (LABEL_P (label
))
13390 LABEL_NUSES (label
)--;
13396 /* This note says something about the value of a register prior
13397 to the execution of an insn. It is too much trouble to see
13398 if the note is still correct in all situations. It is better
13399 to simply delete it. */
13403 /* If we replaced the right hand side of FROM_INSN with a
13404 REG_EQUAL note, the original use of the dying register
13405 will not have been combined into I3 and I2. In such cases,
13406 FROM_INSN is guaranteed to be the first of the combined
13407 instructions, so we simply need to search back before
13408 FROM_INSN for the previous use or set of this register,
13409 then alter the notes there appropriately.
13411 If the register is used as an input in I3, it dies there.
13412 Similarly for I2, if it is nonzero and adjacent to I3.
13414 If the register is not used as an input in either I3 or I2
13415 and it is not one of the registers we were supposed to eliminate,
13416 there are two possibilities. We might have a non-adjacent I2
13417 or we might have somehow eliminated an additional register
13418 from a computation. For example, we might have had A & B where
13419 we discover that B will always be zero. In this case we will
13420 eliminate the reference to A.
13422 In both cases, we must search to see if we can find a previous
13423 use of A and put the death note there. */
13426 && from_insn
== i2mod
13427 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13432 && CALL_P (from_insn
)
13433 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13435 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13437 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13438 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13440 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13442 && reg_overlap_mentioned_p (XEXP (note
, 0),
13444 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13445 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13452 basic_block bb
= this_basic_block
;
13454 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13456 if (!NONDEBUG_INSN_P (tem
))
13458 if (tem
== BB_HEAD (bb
))
13463 /* If the register is being set at TEM, see if that is all
13464 TEM is doing. If so, delete TEM. Otherwise, make this
13465 into a REG_UNUSED note instead. Don't delete sets to
13466 global register vars. */
13467 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13468 || !global_regs
[REGNO (XEXP (note
, 0))])
13469 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13471 rtx set
= single_set (tem
);
13472 rtx inner_dest
= 0;
13474 rtx cc0_setter
= NULL_RTX
;
13478 for (inner_dest
= SET_DEST (set
);
13479 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13480 || GET_CODE (inner_dest
) == SUBREG
13481 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13482 inner_dest
= XEXP (inner_dest
, 0))
13485 /* Verify that it was the set, and not a clobber that
13486 modified the register.
13488 CC0 targets must be careful to maintain setter/user
13489 pairs. If we cannot delete the setter due to side
13490 effects, mark the user with an UNUSED note instead
13493 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13494 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13496 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13497 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13498 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13502 /* Move the notes and links of TEM elsewhere.
13503 This might delete other dead insns recursively.
13504 First set the pattern to something that won't use
13506 rtx old_notes
= REG_NOTES (tem
);
13508 PATTERN (tem
) = pc_rtx
;
13509 REG_NOTES (tem
) = NULL
;
13511 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13512 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13513 distribute_links (LOG_LINKS (tem
));
13515 SET_INSN_DELETED (tem
);
13520 /* Delete the setter too. */
13523 PATTERN (cc0_setter
) = pc_rtx
;
13524 old_notes
= REG_NOTES (cc0_setter
);
13525 REG_NOTES (cc0_setter
) = NULL
;
13527 distribute_notes (old_notes
, cc0_setter
,
13528 cc0_setter
, NULL_RTX
,
13529 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13530 distribute_links (LOG_LINKS (cc0_setter
));
13532 SET_INSN_DELETED (cc0_setter
);
13533 if (cc0_setter
== i2
)
13540 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13542 /* If there isn't already a REG_UNUSED note, put one
13543 here. Do not place a REG_DEAD note, even if
13544 the register is also used here; that would not
13545 match the algorithm used in lifetime analysis
13546 and can cause the consistency check in the
13547 scheduler to fail. */
13548 if (! find_regno_note (tem
, REG_UNUSED
,
13549 REGNO (XEXP (note
, 0))))
13554 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13556 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13560 /* If we are doing a 3->2 combination, and we have a
13561 register which formerly died in i3 and was not used
13562 by i2, which now no longer dies in i3 and is used in
13563 i2 but does not die in i2, and place is between i2
13564 and i3, then we may need to move a link from place to
13566 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13568 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13569 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13571 struct insn_link
*links
= LOG_LINKS (place
);
13572 LOG_LINKS (place
) = NULL
;
13573 distribute_links (links
);
13578 if (tem
== BB_HEAD (bb
))
13584 /* If the register is set or already dead at PLACE, we needn't do
13585 anything with this note if it is still a REG_DEAD note.
13586 We check here if it is set at all, not if is it totally replaced,
13587 which is what `dead_or_set_p' checks, so also check for it being
13590 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13592 unsigned int regno
= REGNO (XEXP (note
, 0));
13593 reg_stat_type
*rsp
= ®_stat
[regno
];
13595 if (dead_or_set_p (place
, XEXP (note
, 0))
13596 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13598 /* Unless the register previously died in PLACE, clear
13599 last_death. [I no longer understand why this is
13601 if (rsp
->last_death
!= place
)
13602 rsp
->last_death
= 0;
13606 rsp
->last_death
= place
;
13608 /* If this is a death note for a hard reg that is occupying
13609 multiple registers, ensure that we are still using all
13610 parts of the object. If we find a piece of the object
13611 that is unused, we must arrange for an appropriate REG_DEAD
13612 note to be added for it. However, we can't just emit a USE
13613 and tag the note to it, since the register might actually
13614 be dead; so we recourse, and the recursive call then finds
13615 the previous insn that used this register. */
13617 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13618 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13620 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13621 bool all_used
= true;
13624 for (i
= regno
; i
< endregno
; i
++)
13625 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13626 && ! find_regno_fusage (place
, USE
, i
))
13627 || dead_or_set_regno_p (place
, i
))
13635 /* Put only REG_DEAD notes for pieces that are
13636 not already dead or set. */
13638 for (i
= regno
; i
< endregno
;
13639 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13641 rtx piece
= regno_reg_rtx
[i
];
13642 basic_block bb
= this_basic_block
;
13644 if (! dead_or_set_p (place
, piece
)
13645 && ! reg_bitfield_target_p (piece
,
13648 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13651 distribute_notes (new_note
, place
, place
,
13652 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13655 else if (! refers_to_regno_p (i
, i
+ 1,
13656 PATTERN (place
), 0)
13657 && ! find_regno_fusage (place
, USE
, i
))
13658 for (tem
= PREV_INSN (place
); ;
13659 tem
= PREV_INSN (tem
))
13661 if (!NONDEBUG_INSN_P (tem
))
13663 if (tem
== BB_HEAD (bb
))
13667 if (dead_or_set_p (tem
, piece
)
13668 || reg_bitfield_target_p (piece
,
13671 add_reg_note (tem
, REG_UNUSED
, piece
);
13684 /* Any other notes should not be present at this point in the
13686 gcc_unreachable ();
13691 XEXP (note
, 1) = REG_NOTES (place
);
13692 REG_NOTES (place
) = note
;
13696 add_shallow_copy_of_reg_note (place2
, note
);
13700 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13701 I3, I2, and I1 to new locations. This is also called to add a link
13702 pointing at I3 when I3's destination is changed. */
13705 distribute_links (struct insn_link
*links
)
13707 struct insn_link
*link
, *next_link
;
13709 for (link
= links
; link
; link
= next_link
)
13715 next_link
= link
->next
;
13717 /* If the insn that this link points to is a NOTE or isn't a single
13718 set, ignore it. In the latter case, it isn't clear what we
13719 can do other than ignore the link, since we can't tell which
13720 register it was for. Such links wouldn't be used by combine
13723 It is not possible for the destination of the target of the link to
13724 have been changed by combine. The only potential of this is if we
13725 replace I3, I2, and I1 by I3 and I2. But in that case the
13726 destination of I2 also remains unchanged. */
13728 if (NOTE_P (link
->insn
)
13729 || (set
= single_set (link
->insn
)) == 0)
13732 reg
= SET_DEST (set
);
13733 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13734 || GET_CODE (reg
) == STRICT_LOW_PART
)
13735 reg
= XEXP (reg
, 0);
13737 /* A LOG_LINK is defined as being placed on the first insn that uses
13738 a register and points to the insn that sets the register. Start
13739 searching at the next insn after the target of the link and stop
13740 when we reach a set of the register or the end of the basic block.
13742 Note that this correctly handles the link that used to point from
13743 I3 to I2. Also note that not much searching is typically done here
13744 since most links don't point very far away. */
13746 for (insn
= NEXT_INSN (link
->insn
);
13747 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
13748 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13749 insn
= NEXT_INSN (insn
))
13750 if (DEBUG_INSN_P (insn
))
13752 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13754 if (reg_referenced_p (reg
, PATTERN (insn
)))
13758 else if (CALL_P (insn
)
13759 && find_reg_fusage (insn
, USE
, reg
))
13764 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13767 /* If we found a place to put the link, place it there unless there
13768 is already a link to the same insn as LINK at that point. */
13772 struct insn_link
*link2
;
13774 FOR_EACH_LOG_LINK (link2
, place
)
13775 if (link2
->insn
== link
->insn
)
13780 link
->next
= LOG_LINKS (place
);
13781 LOG_LINKS (place
) = link
;
13783 /* Set added_links_insn to the earliest insn we added a
13785 if (added_links_insn
== 0
13786 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13787 added_links_insn
= place
;
13793 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13794 Check whether the expression pointer to by LOC is a register or
13795 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13796 Otherwise return zero. */
13799 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13804 && (REG_P (x
) || MEM_P (x
))
13805 && ! reg_mentioned_p (x
, (rtx
) expr
))
13810 /* Check for any register or memory mentioned in EQUIV that is not
13811 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13812 of EXPR where some registers may have been replaced by constants. */
13815 unmentioned_reg_p (rtx equiv
, rtx expr
)
13817 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13820 DEBUG_FUNCTION
void
13821 dump_combine_stats (FILE *file
)
13825 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13826 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13830 dump_combine_total_stats (FILE *file
)
13834 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13835 total_attempts
, total_merges
, total_extras
, total_successes
);
13839 gate_handle_combine (void)
13841 return (optimize
> 0);
13844 /* Try combining insns through substitution. */
13845 static unsigned int
13846 rest_of_handle_combine (void)
13848 int rebuild_jump_labels_after_combine
;
13850 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13851 df_note_add_problem ();
13854 regstat_init_n_sets_and_refs ();
13856 rebuild_jump_labels_after_combine
13857 = combine_instructions (get_insns (), max_reg_num ());
13859 /* Combining insns may have turned an indirect jump into a
13860 direct jump. Rebuild the JUMP_LABEL fields of jumping
13862 if (rebuild_jump_labels_after_combine
)
13864 timevar_push (TV_JUMP
);
13865 rebuild_jump_labels (get_insns ());
13867 timevar_pop (TV_JUMP
);
13870 regstat_free_n_sets_and_refs ();
13876 const pass_data pass_data_combine
=
13878 RTL_PASS
, /* type */
13879 "combine", /* name */
13880 OPTGROUP_NONE
, /* optinfo_flags */
13881 true, /* has_gate */
13882 true, /* has_execute */
13883 TV_COMBINE
, /* tv_id */
13884 PROP_cfglayout
, /* properties_required */
13885 0, /* properties_provided */
13886 0, /* properties_destroyed */
13887 0, /* todo_flags_start */
13888 ( TODO_df_finish
| TODO_verify_rtl_sharing
), /* todo_flags_finish */
13891 class pass_combine
: public rtl_opt_pass
13894 pass_combine (gcc::context
*ctxt
)
13895 : rtl_opt_pass (pass_data_combine
, ctxt
)
13898 /* opt_pass methods: */
13899 bool gate () { return gate_handle_combine (); }
13900 unsigned int execute () { return rest_of_handle_combine (); }
13902 }; // class pass_combine
13904 } // anon namespace
13907 make_pass_combine (gcc::context
*ctxt
)
13909 return new pass_combine (ctxt
);