1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
94 #include "diagnostic-core.h"
96 #include "stor-layout.h"
99 #include "cfgcleanup.h"
100 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
107 #include "insn-attr.h"
108 #include "rtlhooks-def.h"
110 #include "tree-pass.h"
111 #include "valtrack.h"
112 #include "rtl-iter.h"
113 #include "print-rtl.h"
115 #ifndef LOAD_EXTEND_OP
116 #define LOAD_EXTEND_OP(M) UNKNOWN
119 /* Number of attempts to combine instructions in this function. */
121 static int combine_attempts
;
123 /* Number of attempts that got as far as substitution in this function. */
125 static int combine_merges
;
127 /* Number of instructions combined with added SETs in this function. */
129 static int combine_extras
;
131 /* Number of instructions combined in this function. */
133 static int combine_successes
;
135 /* Totals over entire compilation. */
137 static int total_attempts
, total_merges
, total_extras
, total_successes
;
139 /* combine_instructions may try to replace the right hand side of the
140 second instruction with the value of an associated REG_EQUAL note
141 before throwing it at try_combine. That is problematic when there
142 is a REG_DEAD note for a register used in the old right hand side
143 and can cause distribute_notes to do wrong things. This is the
144 second instruction if it has been so modified, null otherwise. */
146 static rtx_insn
*i2mod
;
148 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
150 static rtx i2mod_old_rhs
;
152 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
154 static rtx i2mod_new_rhs
;
156 struct reg_stat_type
{
157 /* Record last point of death of (hard or pseudo) register n. */
158 rtx_insn
*last_death
;
160 /* Record last point of modification of (hard or pseudo) register n. */
163 /* The next group of fields allows the recording of the last value assigned
164 to (hard or pseudo) register n. We use this information to see if an
165 operation being processed is redundant given a prior operation performed
166 on the register. For example, an `and' with a constant is redundant if
167 all the zero bits are already known to be turned off.
169 We use an approach similar to that used by cse, but change it in the
172 (1) We do not want to reinitialize at each label.
173 (2) It is useful, but not critical, to know the actual value assigned
174 to a register. Often just its form is helpful.
176 Therefore, we maintain the following fields:
178 last_set_value the last value assigned
179 last_set_label records the value of label_tick when the
180 register was assigned
181 last_set_table_tick records the value of label_tick when a
182 value using the register is assigned
183 last_set_invalid set to nonzero when it is not valid
184 to use the value of this register in some
187 To understand the usage of these tables, it is important to understand
188 the distinction between the value in last_set_value being valid and
189 the register being validly contained in some other expression in the
192 (The next two parameters are out of date).
194 reg_stat[i].last_set_value is valid if it is nonzero, and either
195 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
197 Register I may validly appear in any expression returned for the value
198 of another register if reg_n_sets[i] is 1. It may also appear in the
199 value for register J if reg_stat[j].last_set_invalid is zero, or
200 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
202 If an expression is found in the table containing a register which may
203 not validly appear in an expression, the register is replaced by
204 something that won't match, (clobber (const_int 0)). */
206 /* Record last value assigned to (hard or pseudo) register n. */
210 /* Record the value of label_tick when an expression involving register n
211 is placed in last_set_value. */
213 int last_set_table_tick
;
215 /* Record the value of label_tick when the value for register n is placed in
220 /* These fields are maintained in parallel with last_set_value and are
221 used to store the mode in which the register was last set, the bits
222 that were known to be zero when it was last set, and the number of
223 sign bits copies it was known to have when it was last set. */
225 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
226 char last_set_sign_bit_copies
;
227 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
229 /* Set nonzero if references to register n in expressions should not be
230 used. last_set_invalid is set nonzero when this register is being
231 assigned to and last_set_table_tick == label_tick. */
233 char last_set_invalid
;
235 /* Some registers that are set more than once and used in more than one
236 basic block are nevertheless always set in similar ways. For example,
237 a QImode register may be loaded from memory in two places on a machine
238 where byte loads zero extend.
240 We record in the following fields if a register has some leading bits
241 that are always equal to the sign bit, and what we know about the
242 nonzero bits of a register, specifically which bits are known to be
245 If an entry is zero, it means that we don't know anything special. */
247 unsigned char sign_bit_copies
;
249 unsigned HOST_WIDE_INT nonzero_bits
;
251 /* Record the value of the label_tick when the last truncation
252 happened. The field truncated_to_mode is only valid if
253 truncation_label == label_tick. */
255 int truncation_label
;
257 /* Record the last truncation seen for this register. If truncation
258 is not a nop to this mode we might be able to save an explicit
259 truncation if we know that value already contains a truncated
262 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
266 static vec
<reg_stat_type
> reg_stat
;
268 /* One plus the highest pseudo for which we track REG_N_SETS.
269 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
270 but during combine_split_insns new pseudos can be created. As we don't have
271 updated DF information in that case, it is hard to initialize the array
272 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
273 so instead of growing the arrays, just assume all newly created pseudos
274 during combine might be set multiple times. */
276 static unsigned int reg_n_sets_max
;
278 /* Record the luid of the last insn that invalidated memory
279 (anything that writes memory, and subroutine calls, but not pushes). */
281 static int mem_last_set
;
283 /* Record the luid of the last CALL_INSN
284 so we can tell whether a potential combination crosses any calls. */
286 static int last_call_luid
;
288 /* When `subst' is called, this is the insn that is being modified
289 (by combining in a previous insn). The PATTERN of this insn
290 is still the old pattern partially modified and it should not be
291 looked at, but this may be used to examine the successors of the insn
292 to judge whether a simplification is valid. */
294 static rtx_insn
*subst_insn
;
296 /* This is the lowest LUID that `subst' is currently dealing with.
297 get_last_value will not return a value if the register was set at or
298 after this LUID. If not for this mechanism, we could get confused if
299 I2 or I1 in try_combine were an insn that used the old value of a register
300 to obtain a new value. In that case, we might erroneously get the
301 new value of the register when we wanted the old one. */
303 static int subst_low_luid
;
305 /* This contains any hard registers that are used in newpat; reg_dead_at_p
306 must consider all these registers to be always live. */
308 static HARD_REG_SET newpat_used_regs
;
310 /* This is an insn to which a LOG_LINKS entry has been added. If this
311 insn is the earlier than I2 or I3, combine should rescan starting at
314 static rtx_insn
*added_links_insn
;
316 /* Basic block in which we are performing combines. */
317 static basic_block this_basic_block
;
318 static bool optimize_this_for_speed_p
;
321 /* Length of the currently allocated uid_insn_cost array. */
323 static int max_uid_known
;
325 /* The following array records the insn_rtx_cost for every insn
326 in the instruction stream. */
328 static int *uid_insn_cost
;
330 /* The following array records the LOG_LINKS for every insn in the
331 instruction stream as struct insn_link pointers. */
336 struct insn_link
*next
;
339 static struct insn_link
**uid_log_links
;
341 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
342 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
344 #define FOR_EACH_LOG_LINK(L, INSN) \
345 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
347 /* Links for LOG_LINKS are allocated from this obstack. */
349 static struct obstack insn_link_obstack
;
351 /* Allocate a link. */
353 static inline struct insn_link
*
354 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
357 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
358 sizeof (struct insn_link
));
365 /* Incremented for each basic block. */
367 static int label_tick
;
369 /* Reset to label_tick for each extended basic block in scanning order. */
371 static int label_tick_ebb_start
;
373 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
374 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
376 static machine_mode nonzero_bits_mode
;
378 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
379 be safely used. It is zero while computing them and after combine has
380 completed. This former test prevents propagating values based on
381 previously set values, which can be incorrect if a variable is modified
384 static int nonzero_sign_valid
;
387 /* Record one modification to rtl structure
388 to be undone by storing old_contents into *where. */
390 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
396 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
397 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
400 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
401 num_undo says how many are currently recorded.
403 other_insn is nonzero if we have modified some other insn in the process
404 of working on subst_insn. It must be verified too. */
410 rtx_insn
*other_insn
;
413 static struct undobuf undobuf
;
415 /* Number of times the pseudo being substituted for
416 was found and replaced. */
418 static int n_occurrences
;
420 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
422 unsigned HOST_WIDE_INT
,
423 unsigned HOST_WIDE_INT
*);
424 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
426 unsigned int, unsigned int *);
427 static void do_SUBST (rtx
*, rtx
);
428 static void do_SUBST_INT (int *, int);
429 static void init_reg_last (void);
430 static void setup_incoming_promotions (rtx_insn
*);
431 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
432 static int cant_combine_insn_p (rtx_insn
*);
433 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
434 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
435 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
436 static int contains_muldiv (rtx
);
437 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
439 static void undo_all (void);
440 static void undo_commit (void);
441 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
442 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
443 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
444 static rtx
simplify_if_then_else (rtx
);
445 static rtx
simplify_set (rtx
);
446 static rtx
simplify_logical (rtx
);
447 static rtx
expand_compound_operation (rtx
);
448 static const_rtx
expand_field_assignment (const_rtx
);
449 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
450 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
451 static rtx
extract_left_shift (rtx
, int);
452 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
453 unsigned HOST_WIDE_INT
*);
454 static rtx
canon_reg_for_combine (rtx
, rtx
);
455 static rtx
force_to_mode (rtx
, machine_mode
,
456 unsigned HOST_WIDE_INT
, int);
457 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
458 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
459 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
460 static rtx
make_field_assignment (rtx
);
461 static rtx
apply_distributive_law (rtx
);
462 static rtx
distribute_and_simplify_rtx (rtx
, int);
463 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
464 unsigned HOST_WIDE_INT
);
465 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
466 unsigned HOST_WIDE_INT
);
467 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
468 HOST_WIDE_INT
, machine_mode
, int *);
469 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
470 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
472 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
473 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
474 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
476 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
477 static void update_table_tick (rtx
);
478 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
479 static void check_promoted_subreg (rtx_insn
*, rtx
);
480 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
481 static void record_dead_and_set_regs (rtx_insn
*);
482 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
483 static rtx
get_last_value (const_rtx
);
484 static int use_crosses_set_p (const_rtx
, int);
485 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
486 static int reg_dead_at_p (rtx
, rtx_insn
*);
487 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
488 static int reg_bitfield_target_p (rtx
, rtx
);
489 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
490 static void distribute_links (struct insn_link
*);
491 static void mark_used_regs_combine (rtx
);
492 static void record_promoted_value (rtx_insn
*, rtx
);
493 static bool unmentioned_reg_p (rtx
, rtx
);
494 static void record_truncated_values (rtx
*, void *);
495 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
496 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
499 /* It is not safe to use ordinary gen_lowpart in combine.
500 See comments in gen_lowpart_for_combine. */
501 #undef RTL_HOOKS_GEN_LOWPART
502 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
504 /* Our implementation of gen_lowpart never emits a new pseudo. */
505 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
506 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
508 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
509 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
511 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
512 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
514 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
515 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
517 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
520 /* Convenience wrapper for the canonicalize_comparison target hook.
521 Target hooks cannot use enum rtx_code. */
523 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
524 bool op0_preserve_value
)
526 int code_int
= (int)*code
;
527 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
528 *code
= (enum rtx_code
)code_int
;
531 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
532 PATTERN can not be split. Otherwise, it returns an insn sequence.
533 This is a wrapper around split_insns which ensures that the
534 reg_stat vector is made larger if the splitter creates a new
538 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
543 ret
= split_insns (pattern
, insn
);
544 nregs
= max_reg_num ();
545 if (nregs
> reg_stat
.length ())
546 reg_stat
.safe_grow_cleared (nregs
);
550 /* This is used by find_single_use to locate an rtx in LOC that
551 contains exactly one use of DEST, which is typically either a REG
552 or CC0. It returns a pointer to the innermost rtx expression
553 containing DEST. Appearances of DEST that are being used to
554 totally replace it are not counted. */
557 find_single_use_1 (rtx dest
, rtx
*loc
)
560 enum rtx_code code
= GET_CODE (x
);
576 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
577 of a REG that occupies all of the REG, the insn uses DEST if
578 it is mentioned in the destination or the source. Otherwise, we
579 need just check the source. */
580 if (GET_CODE (SET_DEST (x
)) != CC0
581 && GET_CODE (SET_DEST (x
)) != PC
582 && !REG_P (SET_DEST (x
))
583 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
584 && REG_P (SUBREG_REG (SET_DEST (x
)))
585 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
586 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
587 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
588 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
591 return find_single_use_1 (dest
, &SET_SRC (x
));
595 return find_single_use_1 (dest
, &XEXP (x
, 0));
601 /* If it wasn't one of the common cases above, check each expression and
602 vector of this code. Look for a unique usage of DEST. */
604 fmt
= GET_RTX_FORMAT (code
);
605 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
609 if (dest
== XEXP (x
, i
)
610 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
611 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
614 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
617 result
= this_result
;
618 else if (this_result
)
619 /* Duplicate usage. */
622 else if (fmt
[i
] == 'E')
626 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
628 if (XVECEXP (x
, i
, j
) == dest
630 && REG_P (XVECEXP (x
, i
, j
))
631 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
634 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
637 result
= this_result
;
638 else if (this_result
)
648 /* See if DEST, produced in INSN, is used only a single time in the
649 sequel. If so, return a pointer to the innermost rtx expression in which
652 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
654 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
655 care about REG_DEAD notes or LOG_LINKS.
657 Otherwise, we find the single use by finding an insn that has a
658 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
659 only referenced once in that insn, we know that it must be the first
660 and last insn referencing DEST. */
663 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
668 struct insn_link
*link
;
672 next
= NEXT_INSN (insn
);
674 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
677 result
= find_single_use_1 (dest
, &PATTERN (next
));
686 bb
= BLOCK_FOR_INSN (insn
);
687 for (next
= NEXT_INSN (insn
);
688 next
&& BLOCK_FOR_INSN (next
) == bb
;
689 next
= NEXT_INSN (next
))
690 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
692 FOR_EACH_LOG_LINK (link
, next
)
693 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
698 result
= find_single_use_1 (dest
, &PATTERN (next
));
708 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
709 insn. The substitution can be undone by undo_all. If INTO is already
710 set to NEWVAL, do not record this change. Because computing NEWVAL might
711 also call SUBST, we have to compute it before we put anything into
715 do_SUBST (rtx
*into
, rtx newval
)
720 if (oldval
== newval
)
723 /* We'd like to catch as many invalid transformations here as
724 possible. Unfortunately, there are way too many mode changes
725 that are perfectly valid, so we'd waste too much effort for
726 little gain doing the checks here. Focus on catching invalid
727 transformations involving integer constants. */
728 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
729 && CONST_INT_P (newval
))
731 /* Sanity check that we're replacing oldval with a CONST_INT
732 that is a valid sign-extension for the original mode. */
733 gcc_assert (INTVAL (newval
)
734 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
736 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
737 CONST_INT is not valid, because after the replacement, the
738 original mode would be gone. Unfortunately, we can't tell
739 when do_SUBST is called to replace the operand thereof, so we
740 perform this test on oldval instead, checking whether an
741 invalid replacement took place before we got here. */
742 gcc_assert (!(GET_CODE (oldval
) == SUBREG
743 && CONST_INT_P (SUBREG_REG (oldval
))));
744 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
745 && CONST_INT_P (XEXP (oldval
, 0))));
749 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
751 buf
= XNEW (struct undo
);
753 buf
->kind
= UNDO_RTX
;
755 buf
->old_contents
.r
= oldval
;
758 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
761 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
763 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
764 for the value of a HOST_WIDE_INT value (including CONST_INT) is
768 do_SUBST_INT (int *into
, int newval
)
773 if (oldval
== newval
)
777 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
779 buf
= XNEW (struct undo
);
781 buf
->kind
= UNDO_INT
;
783 buf
->old_contents
.i
= oldval
;
786 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
789 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
791 /* Similar to SUBST, but just substitute the mode. This is used when
792 changing the mode of a pseudo-register, so that any other
793 references to the entry in the regno_reg_rtx array will change as
797 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
800 machine_mode oldval
= GET_MODE (*into
);
802 if (oldval
== newval
)
806 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
808 buf
= XNEW (struct undo
);
810 buf
->kind
= UNDO_MODE
;
812 buf
->old_contents
.m
= oldval
;
813 adjust_reg_mode (*into
, newval
);
815 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
818 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
820 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
823 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
826 struct insn_link
* oldval
= *into
;
828 if (oldval
== newval
)
832 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
834 buf
= XNEW (struct undo
);
836 buf
->kind
= UNDO_LINKS
;
838 buf
->old_contents
.l
= oldval
;
841 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
844 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
846 /* Subroutine of try_combine. Determine whether the replacement patterns
847 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
848 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
849 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
850 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
851 of all the instructions can be estimated and the replacements are more
852 expensive than the original sequence. */
855 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
856 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
858 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
859 int new_i2_cost
, new_i3_cost
;
860 int old_cost
, new_cost
;
862 /* Lookup the original insn_rtx_costs. */
863 i2_cost
= INSN_COST (i2
);
864 i3_cost
= INSN_COST (i3
);
868 i1_cost
= INSN_COST (i1
);
871 i0_cost
= INSN_COST (i0
);
872 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
873 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
877 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
878 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
884 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
885 i1_cost
= i0_cost
= 0;
888 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
890 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
894 /* Calculate the replacement insn_rtx_costs. */
895 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
898 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
899 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
900 ? new_i2_cost
+ new_i3_cost
: 0;
904 new_cost
= new_i3_cost
;
908 if (undobuf
.other_insn
)
910 int old_other_cost
, new_other_cost
;
912 old_other_cost
= INSN_COST (undobuf
.other_insn
);
913 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
914 if (old_other_cost
> 0 && new_other_cost
> 0)
916 old_cost
+= old_other_cost
;
917 new_cost
+= new_other_cost
;
923 /* Disallow this combination if both new_cost and old_cost are greater than
924 zero, and new_cost is greater than old cost. */
925 int reject
= old_cost
> 0 && new_cost
> old_cost
;
929 fprintf (dump_file
, "%s combination of insns ",
930 reject
? "rejecting" : "allowing");
932 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
933 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
934 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
935 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
937 fprintf (dump_file
, "original costs ");
939 fprintf (dump_file
, "%d + ", i0_cost
);
940 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
941 fprintf (dump_file
, "%d + ", i1_cost
);
942 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
945 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
946 new_i2_cost
, new_i3_cost
, new_cost
);
948 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
954 /* Update the uid_insn_cost array with the replacement costs. */
955 INSN_COST (i2
) = new_i2_cost
;
956 INSN_COST (i3
) = new_i3_cost
;
968 /* Delete any insns that copy a register to itself. */
971 delete_noop_moves (void)
973 rtx_insn
*insn
, *next
;
976 FOR_EACH_BB_FN (bb
, cfun
)
978 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
980 next
= NEXT_INSN (insn
);
981 if (INSN_P (insn
) && noop_move_p (insn
))
984 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
986 delete_insn_and_edges (insn
);
993 /* Return false if we do not want to (or cannot) combine DEF. */
995 can_combine_def_p (df_ref def
)
997 /* Do not consider if it is pre/post modification in MEM. */
998 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1001 unsigned int regno
= DF_REF_REGNO (def
);
1003 /* Do not combine frame pointer adjustments. */
1004 if ((regno
== FRAME_POINTER_REGNUM
1005 && (!reload_completed
|| frame_pointer_needed
))
1006 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1007 && regno
== HARD_FRAME_POINTER_REGNUM
1008 && (!reload_completed
|| frame_pointer_needed
))
1009 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1010 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1016 /* Return false if we do not want to (or cannot) combine USE. */
1018 can_combine_use_p (df_ref use
)
1020 /* Do not consider the usage of the stack pointer by function call. */
1021 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1027 /* Fill in log links field for all insns. */
1030 create_log_links (void)
1033 rtx_insn
**next_use
;
1037 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1039 /* Pass through each block from the end, recording the uses of each
1040 register and establishing log links when def is encountered.
1041 Note that we do not clear next_use array in order to save time,
1042 so we have to test whether the use is in the same basic block as def.
1044 There are a few cases below when we do not consider the definition or
1045 usage -- these are taken from original flow.c did. Don't ask me why it is
1046 done this way; I don't know and if it works, I don't want to know. */
1048 FOR_EACH_BB_FN (bb
, cfun
)
1050 FOR_BB_INSNS_REVERSE (bb
, insn
)
1052 if (!NONDEBUG_INSN_P (insn
))
1055 /* Log links are created only once. */
1056 gcc_assert (!LOG_LINKS (insn
));
1058 FOR_EACH_INSN_DEF (def
, insn
)
1060 unsigned int regno
= DF_REF_REGNO (def
);
1063 if (!next_use
[regno
])
1066 if (!can_combine_def_p (def
))
1069 use_insn
= next_use
[regno
];
1070 next_use
[regno
] = NULL
;
1072 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1077 We don't build a LOG_LINK for hard registers contained
1078 in ASM_OPERANDs. If these registers get replaced,
1079 we might wind up changing the semantics of the insn,
1080 even if reload can make what appear to be valid
1081 assignments later. */
1082 if (regno
< FIRST_PSEUDO_REGISTER
1083 && asm_noperands (PATTERN (use_insn
)) >= 0)
1086 /* Don't add duplicate links between instructions. */
1087 struct insn_link
*links
;
1088 FOR_EACH_LOG_LINK (links
, use_insn
)
1089 if (insn
== links
->insn
&& regno
== links
->regno
)
1093 LOG_LINKS (use_insn
)
1094 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1097 FOR_EACH_INSN_USE (use
, insn
)
1098 if (can_combine_use_p (use
))
1099 next_use
[DF_REF_REGNO (use
)] = insn
;
1106 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1107 true if we found a LOG_LINK that proves that A feeds B. This only works
1108 if there are no instructions between A and B which could have a link
1109 depending on A, since in that case we would not record a link for B.
1110 We also check the implicit dependency created by a cc0 setter/user
1114 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1116 struct insn_link
*links
;
1117 FOR_EACH_LOG_LINK (links
, b
)
1118 if (links
->insn
== a
)
1120 if (HAVE_cc0
&& sets_cc0_p (a
))
1125 /* Main entry point for combiner. F is the first insn of the function.
1126 NREGS is the first unused pseudo-reg number.
1128 Return nonzero if the combiner has turned an indirect jump
1129 instruction into a direct jump. */
1131 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1133 rtx_insn
*insn
, *next
;
1135 struct insn_link
*links
, *nextlinks
;
1137 basic_block last_bb
;
1139 int new_direct_jump_p
= 0;
1141 for (first
= f
; first
&& !INSN_P (first
); )
1142 first
= NEXT_INSN (first
);
1146 combine_attempts
= 0;
1149 combine_successes
= 0;
1151 rtl_hooks
= combine_rtl_hooks
;
1153 reg_stat
.safe_grow_cleared (nregs
);
1155 init_recog_no_volatile ();
1157 /* Allocate array for insn info. */
1158 max_uid_known
= get_max_uid ();
1159 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1160 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1161 gcc_obstack_init (&insn_link_obstack
);
1163 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1165 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1166 problems when, for example, we have j <<= 1 in a loop. */
1168 nonzero_sign_valid
= 0;
1169 label_tick
= label_tick_ebb_start
= 1;
1171 /* Scan all SETs and see if we can deduce anything about what
1172 bits are known to be zero for some registers and how many copies
1173 of the sign bit are known to exist for those registers.
1175 Also set any known values so that we can use it while searching
1176 for what bits are known to be set. */
1178 setup_incoming_promotions (first
);
1179 /* Allow the entry block and the first block to fall into the same EBB.
1180 Conceptually the incoming promotions are assigned to the entry block. */
1181 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1183 create_log_links ();
1184 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1186 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1191 if (!single_pred_p (this_basic_block
)
1192 || single_pred (this_basic_block
) != last_bb
)
1193 label_tick_ebb_start
= label_tick
;
1194 last_bb
= this_basic_block
;
1196 FOR_BB_INSNS (this_basic_block
, insn
)
1197 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1201 subst_low_luid
= DF_INSN_LUID (insn
);
1204 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1206 record_dead_and_set_regs (insn
);
1209 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1210 if (REG_NOTE_KIND (links
) == REG_INC
)
1211 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1214 /* Record the current insn_rtx_cost of this instruction. */
1215 if (NONJUMP_INSN_P (insn
))
1216 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1217 optimize_this_for_speed_p
);
1219 fprintf (dump_file
, "insn_cost %d: %d\n",
1220 INSN_UID (insn
), INSN_COST (insn
));
1224 nonzero_sign_valid
= 1;
1226 /* Now scan all the insns in forward order. */
1227 label_tick
= label_tick_ebb_start
= 1;
1229 setup_incoming_promotions (first
);
1230 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1231 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1233 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1235 rtx_insn
*last_combined_insn
= NULL
;
1236 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1241 if (!single_pred_p (this_basic_block
)
1242 || single_pred (this_basic_block
) != last_bb
)
1243 label_tick_ebb_start
= label_tick
;
1244 last_bb
= this_basic_block
;
1246 rtl_profile_for_bb (this_basic_block
);
1247 for (insn
= BB_HEAD (this_basic_block
);
1248 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1249 insn
= next
? next
: NEXT_INSN (insn
))
1252 if (!NONDEBUG_INSN_P (insn
))
1255 while (last_combined_insn
1256 && last_combined_insn
->deleted ())
1257 last_combined_insn
= PREV_INSN (last_combined_insn
);
1258 if (last_combined_insn
== NULL_RTX
1259 || BARRIER_P (last_combined_insn
)
1260 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1261 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1262 last_combined_insn
= insn
;
1264 /* See if we know about function return values before this
1265 insn based upon SUBREG flags. */
1266 check_promoted_subreg (insn
, PATTERN (insn
));
1268 /* See if we can find hardregs and subreg of pseudos in
1269 narrower modes. This could help turning TRUNCATEs
1271 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1273 /* Try this insn with each insn it links back to. */
1275 FOR_EACH_LOG_LINK (links
, insn
)
1276 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1277 NULL
, &new_direct_jump_p
,
1278 last_combined_insn
)) != 0)
1280 statistics_counter_event (cfun
, "two-insn combine", 1);
1284 /* Try each sequence of three linked insns ending with this one. */
1286 if (max_combine
>= 3)
1287 FOR_EACH_LOG_LINK (links
, insn
)
1289 rtx_insn
*link
= links
->insn
;
1291 /* If the linked insn has been replaced by a note, then there
1292 is no point in pursuing this chain any further. */
1296 FOR_EACH_LOG_LINK (nextlinks
, link
)
1297 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1298 NULL
, &new_direct_jump_p
,
1299 last_combined_insn
)) != 0)
1301 statistics_counter_event (cfun
, "three-insn combine", 1);
1306 /* Try to combine a jump insn that uses CC0
1307 with a preceding insn that sets CC0, and maybe with its
1308 logical predecessor as well.
1309 This is how we make decrement-and-branch insns.
1310 We need this special code because data flow connections
1311 via CC0 do not get entered in LOG_LINKS. */
1315 && (prev
= prev_nonnote_insn (insn
)) != 0
1316 && NONJUMP_INSN_P (prev
)
1317 && sets_cc0_p (PATTERN (prev
)))
1319 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1321 last_combined_insn
)) != 0)
1324 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1325 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1326 NULL
, &new_direct_jump_p
,
1327 last_combined_insn
)) != 0)
1331 /* Do the same for an insn that explicitly references CC0. */
1332 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1333 && (prev
= prev_nonnote_insn (insn
)) != 0
1334 && NONJUMP_INSN_P (prev
)
1335 && sets_cc0_p (PATTERN (prev
))
1336 && GET_CODE (PATTERN (insn
)) == SET
1337 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1339 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1341 last_combined_insn
)) != 0)
1344 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1345 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1346 NULL
, &new_direct_jump_p
,
1347 last_combined_insn
)) != 0)
1351 /* Finally, see if any of the insns that this insn links to
1352 explicitly references CC0. If so, try this insn, that insn,
1353 and its predecessor if it sets CC0. */
1356 FOR_EACH_LOG_LINK (links
, insn
)
1357 if (NONJUMP_INSN_P (links
->insn
)
1358 && GET_CODE (PATTERN (links
->insn
)) == SET
1359 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1360 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1361 && NONJUMP_INSN_P (prev
)
1362 && sets_cc0_p (PATTERN (prev
))
1363 && (next
= try_combine (insn
, links
->insn
,
1364 prev
, NULL
, &new_direct_jump_p
,
1365 last_combined_insn
)) != 0)
1369 /* Try combining an insn with two different insns whose results it
1371 if (max_combine
>= 3)
1372 FOR_EACH_LOG_LINK (links
, insn
)
1373 for (nextlinks
= links
->next
; nextlinks
;
1374 nextlinks
= nextlinks
->next
)
1375 if ((next
= try_combine (insn
, links
->insn
,
1376 nextlinks
->insn
, NULL
,
1378 last_combined_insn
)) != 0)
1381 statistics_counter_event (cfun
, "three-insn combine", 1);
1385 /* Try four-instruction combinations. */
1386 if (max_combine
>= 4)
1387 FOR_EACH_LOG_LINK (links
, insn
)
1389 struct insn_link
*next1
;
1390 rtx_insn
*link
= links
->insn
;
1392 /* If the linked insn has been replaced by a note, then there
1393 is no point in pursuing this chain any further. */
1397 FOR_EACH_LOG_LINK (next1
, link
)
1399 rtx_insn
*link1
= next1
->insn
;
1402 /* I0 -> I1 -> I2 -> I3. */
1403 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1404 if ((next
= try_combine (insn
, link
, link1
,
1407 last_combined_insn
)) != 0)
1409 statistics_counter_event (cfun
, "four-insn combine", 1);
1412 /* I0, I1 -> I2, I2 -> I3. */
1413 for (nextlinks
= next1
->next
; nextlinks
;
1414 nextlinks
= nextlinks
->next
)
1415 if ((next
= try_combine (insn
, link
, link1
,
1418 last_combined_insn
)) != 0)
1420 statistics_counter_event (cfun
, "four-insn combine", 1);
1425 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1427 rtx_insn
*link1
= next1
->insn
;
1430 /* I0 -> I2; I1, I2 -> I3. */
1431 FOR_EACH_LOG_LINK (nextlinks
, link
)
1432 if ((next
= try_combine (insn
, link
, link1
,
1435 last_combined_insn
)) != 0)
1437 statistics_counter_event (cfun
, "four-insn combine", 1);
1440 /* I0 -> I1; I1, I2 -> I3. */
1441 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1442 if ((next
= try_combine (insn
, link
, link1
,
1445 last_combined_insn
)) != 0)
1447 statistics_counter_event (cfun
, "four-insn combine", 1);
1453 /* Try this insn with each REG_EQUAL note it links back to. */
1454 FOR_EACH_LOG_LINK (links
, insn
)
1457 rtx_insn
*temp
= links
->insn
;
1458 if ((set
= single_set (temp
)) != 0
1459 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1460 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1461 /* Avoid using a register that may already been marked
1462 dead by an earlier instruction. */
1463 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1464 && (GET_MODE (note
) == VOIDmode
1465 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1466 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1468 /* Temporarily replace the set's source with the
1469 contents of the REG_EQUAL note. The insn will
1470 be deleted or recognized by try_combine. */
1471 rtx orig
= SET_SRC (set
);
1472 SET_SRC (set
) = note
;
1474 i2mod_old_rhs
= copy_rtx (orig
);
1475 i2mod_new_rhs
= copy_rtx (note
);
1476 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1478 last_combined_insn
);
1482 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1485 SET_SRC (set
) = orig
;
1490 record_dead_and_set_regs (insn
);
1497 default_rtl_profile ();
1499 new_direct_jump_p
|= purge_all_dead_edges ();
1500 delete_noop_moves ();
1503 obstack_free (&insn_link_obstack
, NULL
);
1504 free (uid_log_links
);
1505 free (uid_insn_cost
);
1506 reg_stat
.release ();
1509 struct undo
*undo
, *next
;
1510 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1518 total_attempts
+= combine_attempts
;
1519 total_merges
+= combine_merges
;
1520 total_extras
+= combine_extras
;
1521 total_successes
+= combine_successes
;
1523 nonzero_sign_valid
= 0;
1524 rtl_hooks
= general_rtl_hooks
;
1526 /* Make recognizer allow volatile MEMs again. */
1529 return new_direct_jump_p
;
1532 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1535 init_reg_last (void)
1540 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1541 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1544 /* Set up any promoted values for incoming argument registers. */
1547 setup_incoming_promotions (rtx_insn
*first
)
1550 bool strictly_local
= false;
1552 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1553 arg
= DECL_CHAIN (arg
))
1555 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1557 machine_mode mode1
, mode2
, mode3
, mode4
;
1559 /* Only continue if the incoming argument is in a register. */
1563 /* Determine, if possible, whether all call sites of the current
1564 function lie within the current compilation unit. (This does
1565 take into account the exporting of a function via taking its
1566 address, and so forth.) */
1567 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1569 /* The mode and signedness of the argument before any promotions happen
1570 (equal to the mode of the pseudo holding it at that stage). */
1571 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1572 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1574 /* The mode and signedness of the argument after any source language and
1575 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1576 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1577 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1579 /* The mode and signedness of the argument as it is actually passed,
1580 see assign_parm_setup_reg in function.c. */
1581 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1582 TREE_TYPE (cfun
->decl
), 0);
1584 /* The mode of the register in which the argument is being passed. */
1585 mode4
= GET_MODE (reg
);
1587 /* Eliminate sign extensions in the callee when:
1588 (a) A mode promotion has occurred; */
1591 /* (b) The mode of the register is the same as the mode of
1592 the argument as it is passed; */
1595 /* (c) There's no language level extension; */
1598 /* (c.1) All callers are from the current compilation unit. If that's
1599 the case we don't have to rely on an ABI, we only have to know
1600 what we're generating right now, and we know that we will do the
1601 mode1 to mode2 promotion with the given sign. */
1602 else if (!strictly_local
)
1604 /* (c.2) The combination of the two promotions is useful. This is
1605 true when the signs match, or if the first promotion is unsigned.
1606 In the later case, (sign_extend (zero_extend x)) is the same as
1607 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1613 /* Record that the value was promoted from mode1 to mode3,
1614 so that any sign extension at the head of the current
1615 function may be eliminated. */
1616 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1617 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1618 record_value_for_reg (reg
, first
, x
);
1622 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1623 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1624 because some machines (maybe most) will actually do the sign-extension and
1625 this is the conservative approach.
1627 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1631 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1633 if (GET_MODE_PRECISION (mode
) < prec
1634 && CONST_INT_P (src
)
1636 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1637 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1642 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1646 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1649 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1650 unsigned HOST_WIDE_INT bits
= 0;
1651 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1652 unsigned int num
= 0;
1655 reg_equal
= XEXP (reg_equal_note
, 0);
1657 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1659 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1661 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1664 /* Don't call nonzero_bits if it cannot change anything. */
1665 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1667 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1668 if (reg_equal
&& bits
)
1669 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1670 rsp
->nonzero_bits
|= bits
;
1673 /* Don't call num_sign_bit_copies if it cannot change anything. */
1674 if (rsp
->sign_bit_copies
!= 1)
1676 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1677 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1679 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1680 if (num
== 0 || numeq
> num
)
1683 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1684 rsp
->sign_bit_copies
= num
;
1688 /* Called via note_stores. If X is a pseudo that is narrower than
1689 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1691 If we are setting only a portion of X and we can't figure out what
1692 portion, assume all bits will be used since we don't know what will
1695 Similarly, set how many bits of X are known to be copies of the sign bit
1696 at all locations in the function. This is the smallest number implied
1700 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1702 rtx_insn
*insn
= (rtx_insn
*) data
;
1705 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1706 /* If this register is undefined at the start of the file, we can't
1707 say what its contents were. */
1708 && ! REGNO_REG_SET_P
1709 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1710 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1712 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1714 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1716 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1717 rsp
->sign_bit_copies
= 1;
1721 /* If this register is being initialized using itself, and the
1722 register is uninitialized in this basic block, and there are
1723 no LOG_LINKS which set the register, then part of the
1724 register is uninitialized. In that case we can't assume
1725 anything about the number of nonzero bits.
1727 ??? We could do better if we checked this in
1728 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1729 could avoid making assumptions about the insn which initially
1730 sets the register, while still using the information in other
1731 insns. We would have to be careful to check every insn
1732 involved in the combination. */
1735 && reg_referenced_p (x
, PATTERN (insn
))
1736 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1739 struct insn_link
*link
;
1741 FOR_EACH_LOG_LINK (link
, insn
)
1742 if (dead_or_set_p (link
->insn
, x
))
1746 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1747 rsp
->sign_bit_copies
= 1;
1752 /* If this is a complex assignment, see if we can convert it into a
1753 simple assignment. */
1754 set
= expand_field_assignment (set
);
1756 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1757 set what we know about X. */
1759 if (SET_DEST (set
) == x
1760 || (paradoxical_subreg_p (SET_DEST (set
))
1761 && SUBREG_REG (SET_DEST (set
)) == x
))
1762 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1765 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1766 rsp
->sign_bit_copies
= 1;
1771 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1772 optionally insns that were previously combined into I3 or that will be
1773 combined into the merger of INSN and I3. The order is PRED, PRED2,
1774 INSN, SUCC, SUCC2, I3.
1776 Return 0 if the combination is not allowed for any reason.
1778 If the combination is allowed, *PDEST will be set to the single
1779 destination of INSN and *PSRC to the single source, and this function
1783 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1784 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1785 rtx
*pdest
, rtx
*psrc
)
1792 bool all_adjacent
= true;
1793 int (*is_volatile_p
) (const_rtx
);
1799 if (next_active_insn (succ2
) != i3
)
1800 all_adjacent
= false;
1801 if (next_active_insn (succ
) != succ2
)
1802 all_adjacent
= false;
1804 else if (next_active_insn (succ
) != i3
)
1805 all_adjacent
= false;
1806 if (next_active_insn (insn
) != succ
)
1807 all_adjacent
= false;
1809 else if (next_active_insn (insn
) != i3
)
1810 all_adjacent
= false;
1812 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1813 or a PARALLEL consisting of such a SET and CLOBBERs.
1815 If INSN has CLOBBER parallel parts, ignore them for our processing.
1816 By definition, these happen during the execution of the insn. When it
1817 is merged with another insn, all bets are off. If they are, in fact,
1818 needed and aren't also supplied in I3, they may be added by
1819 recog_for_combine. Otherwise, it won't match.
1821 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1824 Get the source and destination of INSN. If more than one, can't
1827 if (GET_CODE (PATTERN (insn
)) == SET
)
1828 set
= PATTERN (insn
);
1829 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1830 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1832 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1834 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1836 switch (GET_CODE (elt
))
1838 /* This is important to combine floating point insns
1839 for the SH4 port. */
1841 /* Combining an isolated USE doesn't make sense.
1842 We depend here on combinable_i3pat to reject them. */
1843 /* The code below this loop only verifies that the inputs of
1844 the SET in INSN do not change. We call reg_set_between_p
1845 to verify that the REG in the USE does not change between
1847 If the USE in INSN was for a pseudo register, the matching
1848 insn pattern will likely match any register; combining this
1849 with any other USE would only be safe if we knew that the
1850 used registers have identical values, or if there was
1851 something to tell them apart, e.g. different modes. For
1852 now, we forgo such complicated tests and simply disallow
1853 combining of USES of pseudo registers with any other USE. */
1854 if (REG_P (XEXP (elt
, 0))
1855 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1857 rtx i3pat
= PATTERN (i3
);
1858 int i
= XVECLEN (i3pat
, 0) - 1;
1859 unsigned int regno
= REGNO (XEXP (elt
, 0));
1863 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1865 if (GET_CODE (i3elt
) == USE
1866 && REG_P (XEXP (i3elt
, 0))
1867 && (REGNO (XEXP (i3elt
, 0)) == regno
1868 ? reg_set_between_p (XEXP (elt
, 0),
1869 PREV_INSN (insn
), i3
)
1870 : regno
>= FIRST_PSEUDO_REGISTER
))
1877 /* We can ignore CLOBBERs. */
1882 /* Ignore SETs whose result isn't used but not those that
1883 have side-effects. */
1884 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1885 && insn_nothrow_p (insn
)
1886 && !side_effects_p (elt
))
1889 /* If we have already found a SET, this is a second one and
1890 so we cannot combine with this insn. */
1898 /* Anything else means we can't combine. */
1904 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1905 so don't do anything with it. */
1906 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1915 /* The simplification in expand_field_assignment may call back to
1916 get_last_value, so set safe guard here. */
1917 subst_low_luid
= DF_INSN_LUID (insn
);
1919 set
= expand_field_assignment (set
);
1920 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1922 /* Do not eliminate user-specified register if it is in an
1923 asm input because we may break the register asm usage defined
1924 in GCC manual if allow to do so.
1925 Be aware that this may cover more cases than we expect but this
1926 should be harmless. */
1927 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1928 && extract_asm_operands (PATTERN (i3
)))
1931 /* Don't eliminate a store in the stack pointer. */
1932 if (dest
== stack_pointer_rtx
1933 /* Don't combine with an insn that sets a register to itself if it has
1934 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1935 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1936 /* Can't merge an ASM_OPERANDS. */
1937 || GET_CODE (src
) == ASM_OPERANDS
1938 /* Can't merge a function call. */
1939 || GET_CODE (src
) == CALL
1940 /* Don't eliminate a function call argument. */
1942 && (find_reg_fusage (i3
, USE
, dest
)
1944 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1945 && global_regs
[REGNO (dest
)])))
1946 /* Don't substitute into an incremented register. */
1947 || FIND_REG_INC_NOTE (i3
, dest
)
1948 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1949 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1950 /* Don't substitute into a non-local goto, this confuses CFG. */
1951 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1952 /* Make sure that DEST is not used after SUCC but before I3. */
1955 && (reg_used_between_p (dest
, succ2
, i3
)
1956 || reg_used_between_p (dest
, succ
, succ2
)))
1957 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1958 /* Make sure that the value that is to be substituted for the register
1959 does not use any registers whose values alter in between. However,
1960 If the insns are adjacent, a use can't cross a set even though we
1961 think it might (this can happen for a sequence of insns each setting
1962 the same destination; last_set of that register might point to
1963 a NOTE). If INSN has a REG_EQUIV note, the register is always
1964 equivalent to the memory so the substitution is valid even if there
1965 are intervening stores. Also, don't move a volatile asm or
1966 UNSPEC_VOLATILE across any other insns. */
1969 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1970 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1971 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1972 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1973 /* Don't combine across a CALL_INSN, because that would possibly
1974 change whether the life span of some REGs crosses calls or not,
1975 and it is a pain to update that information.
1976 Exception: if source is a constant, moving it later can't hurt.
1977 Accept that as a special case. */
1978 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1981 /* DEST must either be a REG or CC0. */
1984 /* If register alignment is being enforced for multi-word items in all
1985 cases except for parameters, it is possible to have a register copy
1986 insn referencing a hard register that is not allowed to contain the
1987 mode being copied and which would not be valid as an operand of most
1988 insns. Eliminate this problem by not combining with such an insn.
1990 Also, on some machines we don't want to extend the life of a hard
1994 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1995 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1996 /* Don't extend the life of a hard register unless it is
1997 user variable (if we have few registers) or it can't
1998 fit into the desired register (meaning something special
2000 Also avoid substituting a return register into I3, because
2001 reload can't handle a conflict with constraints of other
2003 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2004 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2007 else if (GET_CODE (dest
) != CC0
)
2011 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2012 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2013 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2015 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2017 /* If the clobber represents an earlyclobber operand, we must not
2018 substitute an expression containing the clobbered register.
2019 As we do not analyze the constraint strings here, we have to
2020 make the conservative assumption. However, if the register is
2021 a fixed hard reg, the clobber cannot represent any operand;
2022 we leave it up to the machine description to either accept or
2023 reject use-and-clobber patterns. */
2025 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2026 || !fixed_regs
[REGNO (reg
)])
2027 if (reg_overlap_mentioned_p (reg
, src
))
2031 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2032 or not), reject, unless nothing volatile comes between it and I3 */
2034 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2036 /* Make sure neither succ nor succ2 contains a volatile reference. */
2037 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2039 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2041 /* We'll check insns between INSN and I3 below. */
2044 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2045 to be an explicit register variable, and was chosen for a reason. */
2047 if (GET_CODE (src
) == ASM_OPERANDS
2048 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2051 /* If INSN contains volatile references (specifically volatile MEMs),
2052 we cannot combine across any other volatile references.
2053 Even if INSN doesn't contain volatile references, any intervening
2054 volatile insn might affect machine state. */
2056 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2060 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2061 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2064 /* If INSN contains an autoincrement or autodecrement, make sure that
2065 register is not used between there and I3, and not already used in
2066 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2067 Also insist that I3 not be a jump; if it were one
2068 and the incremented register were spilled, we would lose. */
2071 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2072 if (REG_NOTE_KIND (link
) == REG_INC
2074 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2075 || (pred
!= NULL_RTX
2076 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2077 || (pred2
!= NULL_RTX
2078 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2079 || (succ
!= NULL_RTX
2080 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2081 || (succ2
!= NULL_RTX
2082 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2083 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2086 /* Don't combine an insn that follows a CC0-setting insn.
2087 An insn that uses CC0 must not be separated from the one that sets it.
2088 We do, however, allow I2 to follow a CC0-setting insn if that insn
2089 is passed as I1; in that case it will be deleted also.
2090 We also allow combining in this case if all the insns are adjacent
2091 because that would leave the two CC0 insns adjacent as well.
2092 It would be more logical to test whether CC0 occurs inside I1 or I2,
2093 but that would be much slower, and this ought to be equivalent. */
2097 p
= prev_nonnote_insn (insn
);
2098 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2103 /* If we get here, we have passed all the tests and the combination is
2112 /* LOC is the location within I3 that contains its pattern or the component
2113 of a PARALLEL of the pattern. We validate that it is valid for combining.
2115 One problem is if I3 modifies its output, as opposed to replacing it
2116 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2117 doing so would produce an insn that is not equivalent to the original insns.
2121 (set (reg:DI 101) (reg:DI 100))
2122 (set (subreg:SI (reg:DI 101) 0) <foo>)
2124 This is NOT equivalent to:
2126 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2127 (set (reg:DI 101) (reg:DI 100))])
2129 Not only does this modify 100 (in which case it might still be valid
2130 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2132 We can also run into a problem if I2 sets a register that I1
2133 uses and I1 gets directly substituted into I3 (not via I2). In that
2134 case, we would be getting the wrong value of I2DEST into I3, so we
2135 must reject the combination. This case occurs when I2 and I1 both
2136 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2137 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2138 of a SET must prevent combination from occurring. The same situation
2139 can occur for I0, in which case I0_NOT_IN_SRC is set.
2141 Before doing the above check, we first try to expand a field assignment
2142 into a set of logical operations.
2144 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2145 we place a register that is both set and used within I3. If more than one
2146 such register is detected, we fail.
2148 Return 1 if the combination is valid, zero otherwise. */
2151 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2152 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2156 if (GET_CODE (x
) == SET
)
2159 rtx dest
= SET_DEST (set
);
2160 rtx src
= SET_SRC (set
);
2161 rtx inner_dest
= dest
;
2164 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2165 || GET_CODE (inner_dest
) == SUBREG
2166 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2167 inner_dest
= XEXP (inner_dest
, 0);
2169 /* Check for the case where I3 modifies its output, as discussed
2170 above. We don't want to prevent pseudos from being combined
2171 into the address of a MEM, so only prevent the combination if
2172 i1 or i2 set the same MEM. */
2173 if ((inner_dest
!= dest
&&
2174 (!MEM_P (inner_dest
)
2175 || rtx_equal_p (i2dest
, inner_dest
)
2176 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2177 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2178 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2179 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2180 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2182 /* This is the same test done in can_combine_p except we can't test
2183 all_adjacent; we don't have to, since this instruction will stay
2184 in place, thus we are not considering increasing the lifetime of
2187 Also, if this insn sets a function argument, combining it with
2188 something that might need a spill could clobber a previous
2189 function argument; the all_adjacent test in can_combine_p also
2190 checks this; here, we do a more specific test for this case. */
2192 || (REG_P (inner_dest
)
2193 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2194 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2195 GET_MODE (inner_dest
))))
2196 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2197 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2200 /* If DEST is used in I3, it is being killed in this insn, so
2201 record that for later. We have to consider paradoxical
2202 subregs here, since they kill the whole register, but we
2203 ignore partial subregs, STRICT_LOW_PART, etc.
2204 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2205 STACK_POINTER_REGNUM, since these are always considered to be
2206 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2208 if (GET_CODE (subdest
) == SUBREG
2209 && (GET_MODE_SIZE (GET_MODE (subdest
))
2210 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2211 subdest
= SUBREG_REG (subdest
);
2214 && reg_referenced_p (subdest
, PATTERN (i3
))
2215 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2216 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2217 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2218 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2219 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2220 || ! fixed_regs
[REGNO (subdest
)]))
2221 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2223 if (*pi3dest_killed
)
2226 *pi3dest_killed
= subdest
;
2230 else if (GET_CODE (x
) == PARALLEL
)
2234 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2235 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2236 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2243 /* Return 1 if X is an arithmetic expression that contains a multiplication
2244 and division. We don't count multiplications by powers of two here. */
2247 contains_muldiv (rtx x
)
2249 switch (GET_CODE (x
))
2251 case MOD
: case DIV
: case UMOD
: case UDIV
:
2255 return ! (CONST_INT_P (XEXP (x
, 1))
2256 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2259 return contains_muldiv (XEXP (x
, 0))
2260 || contains_muldiv (XEXP (x
, 1));
2263 return contains_muldiv (XEXP (x
, 0));
2269 /* Determine whether INSN can be used in a combination. Return nonzero if
2270 not. This is used in try_combine to detect early some cases where we
2271 can't perform combinations. */
2274 cant_combine_insn_p (rtx_insn
*insn
)
2279 /* If this isn't really an insn, we can't do anything.
2280 This can occur when flow deletes an insn that it has merged into an
2281 auto-increment address. */
2282 if (! INSN_P (insn
))
2285 /* Never combine loads and stores involving hard regs that are likely
2286 to be spilled. The register allocator can usually handle such
2287 reg-reg moves by tying. If we allow the combiner to make
2288 substitutions of likely-spilled regs, reload might die.
2289 As an exception, we allow combinations involving fixed regs; these are
2290 not available to the register allocator so there's no risk involved. */
2292 set
= single_set (insn
);
2295 src
= SET_SRC (set
);
2296 dest
= SET_DEST (set
);
2297 if (GET_CODE (src
) == SUBREG
)
2298 src
= SUBREG_REG (src
);
2299 if (GET_CODE (dest
) == SUBREG
)
2300 dest
= SUBREG_REG (dest
);
2301 if (REG_P (src
) && REG_P (dest
)
2302 && ((HARD_REGISTER_P (src
)
2303 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2304 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2305 || (HARD_REGISTER_P (dest
)
2306 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2307 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2313 struct likely_spilled_retval_info
2315 unsigned regno
, nregs
;
2319 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2320 hard registers that are known to be written to / clobbered in full. */
2322 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2324 struct likely_spilled_retval_info
*const info
=
2325 (struct likely_spilled_retval_info
*) data
;
2326 unsigned regno
, nregs
;
2329 if (!REG_P (XEXP (set
, 0)))
2332 if (regno
>= info
->regno
+ info
->nregs
)
2334 nregs
= REG_NREGS (x
);
2335 if (regno
+ nregs
<= info
->regno
)
2337 new_mask
= (2U << (nregs
- 1)) - 1;
2338 if (regno
< info
->regno
)
2339 new_mask
>>= info
->regno
- regno
;
2341 new_mask
<<= regno
- info
->regno
;
2342 info
->mask
&= ~new_mask
;
2345 /* Return nonzero iff part of the return value is live during INSN, and
2346 it is likely spilled. This can happen when more than one insn is needed
2347 to copy the return value, e.g. when we consider to combine into the
2348 second copy insn for a complex value. */
2351 likely_spilled_retval_p (rtx_insn
*insn
)
2353 rtx_insn
*use
= BB_END (this_basic_block
);
2356 unsigned regno
, nregs
;
2357 /* We assume here that no machine mode needs more than
2358 32 hard registers when the value overlaps with a register
2359 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2361 struct likely_spilled_retval_info info
;
2363 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2365 reg
= XEXP (PATTERN (use
), 0);
2366 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2368 regno
= REGNO (reg
);
2369 nregs
= REG_NREGS (reg
);
2372 mask
= (2U << (nregs
- 1)) - 1;
2374 /* Disregard parts of the return value that are set later. */
2378 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2380 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2383 /* Check if any of the (probably) live return value registers is
2388 if ((mask
& 1 << nregs
)
2389 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2395 /* Adjust INSN after we made a change to its destination.
2397 Changing the destination can invalidate notes that say something about
2398 the results of the insn and a LOG_LINK pointing to the insn. */
2401 adjust_for_new_dest (rtx_insn
*insn
)
2403 /* For notes, be conservative and simply remove them. */
2404 remove_reg_equal_equiv_notes (insn
);
2406 /* The new insn will have a destination that was previously the destination
2407 of an insn just above it. Call distribute_links to make a LOG_LINK from
2408 the next use of that destination. */
2410 rtx set
= single_set (insn
);
2413 rtx reg
= SET_DEST (set
);
2415 while (GET_CODE (reg
) == ZERO_EXTRACT
2416 || GET_CODE (reg
) == STRICT_LOW_PART
2417 || GET_CODE (reg
) == SUBREG
)
2418 reg
= XEXP (reg
, 0);
2419 gcc_assert (REG_P (reg
));
2421 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2423 df_insn_rescan (insn
);
2426 /* Return TRUE if combine can reuse reg X in mode MODE.
2427 ADDED_SETS is nonzero if the original set is still required. */
2429 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2437 /* Allow hard registers if the new mode is legal, and occupies no more
2438 registers than the old mode. */
2439 if (regno
< FIRST_PSEUDO_REGISTER
)
2440 return (HARD_REGNO_MODE_OK (regno
, mode
)
2441 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2443 /* Or a pseudo that is only used once. */
2444 return (regno
< reg_n_sets_max
2445 && REG_N_SETS (regno
) == 1
2447 && !REG_USERVAR_P (x
));
2451 /* Check whether X, the destination of a set, refers to part of
2452 the register specified by REG. */
2455 reg_subword_p (rtx x
, rtx reg
)
2457 /* Check that reg is an integer mode register. */
2458 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2461 if (GET_CODE (x
) == STRICT_LOW_PART
2462 || GET_CODE (x
) == ZERO_EXTRACT
)
2465 return GET_CODE (x
) == SUBREG
2466 && SUBREG_REG (x
) == reg
2467 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2470 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2471 Note that the INSN should be deleted *after* removing dead edges, so
2472 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2473 but not for a (set (pc) (label_ref FOO)). */
2476 update_cfg_for_uncondjump (rtx_insn
*insn
)
2478 basic_block bb
= BLOCK_FOR_INSN (insn
);
2479 gcc_assert (BB_END (bb
) == insn
);
2481 purge_dead_edges (bb
);
2484 if (EDGE_COUNT (bb
->succs
) == 1)
2488 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2490 /* Remove barriers from the footer if there are any. */
2491 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2492 if (BARRIER_P (insn
))
2494 if (PREV_INSN (insn
))
2495 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2497 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2498 if (NEXT_INSN (insn
))
2499 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2501 else if (LABEL_P (insn
))
2506 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2507 by an arbitrary number of CLOBBERs. */
2509 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2511 if (GET_CODE (pat
) != PARALLEL
)
2514 int len
= XVECLEN (pat
, 0);
2519 for (i
= 0; i
< n
; i
++)
2520 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2521 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2523 for ( ; i
< len
; i
++)
2524 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
2530 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2531 CLOBBERs), can be split into individual SETs in that order, without
2532 changing semantics. */
2534 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2536 if (!insn_nothrow_p (insn
))
2539 rtx pat
= PATTERN (insn
);
2542 for (i
= 0; i
< n
; i
++)
2544 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2547 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2549 for (j
= i
+ 1; j
< n
; j
++)
2550 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2557 /* Try to combine the insns I0, I1 and I2 into I3.
2558 Here I0, I1 and I2 appear earlier than I3.
2559 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2562 If we are combining more than two insns and the resulting insn is not
2563 recognized, try splitting it into two insns. If that happens, I2 and I3
2564 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2565 Otherwise, I0, I1 and I2 are pseudo-deleted.
2567 Return 0 if the combination does not work. Then nothing is changed.
2568 If we did the combination, return the insn at which combine should
2571 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2572 new direct jump instruction.
2574 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2575 been I3 passed to an earlier try_combine within the same basic
2579 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2580 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2582 /* New patterns for I3 and I2, respectively. */
2583 rtx newpat
, newi2pat
= 0;
2584 rtvec newpat_vec_with_clobbers
= 0;
2585 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2586 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2588 int added_sets_0
, added_sets_1
, added_sets_2
;
2589 /* Total number of SETs to put into I3. */
2591 /* Nonzero if I2's or I1's body now appears in I3. */
2592 int i2_is_used
= 0, i1_is_used
= 0;
2593 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2594 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2595 /* Contains I3 if the destination of I3 is used in its source, which means
2596 that the old life of I3 is being killed. If that usage is placed into
2597 I2 and not in I3, a REG_DEAD note must be made. */
2598 rtx i3dest_killed
= 0;
2599 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2600 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2601 /* Copy of SET_SRC of I1 and I0, if needed. */
2602 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2603 /* Set if I2DEST was reused as a scratch register. */
2604 bool i2scratch
= false;
2605 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2606 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2607 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2608 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2609 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2610 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2611 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2612 /* Notes that must be added to REG_NOTES in I3 and I2. */
2613 rtx new_i3_notes
, new_i2_notes
;
2614 /* Notes that we substituted I3 into I2 instead of the normal case. */
2615 int i3_subst_into_i2
= 0;
2616 /* Notes that I1, I2 or I3 is a MULT operation. */
2619 int changed_i3_dest
= 0;
2622 rtx_insn
*temp_insn
;
2624 struct insn_link
*link
;
2626 rtx new_other_notes
;
2629 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2631 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2634 /* Only try four-insn combinations when there's high likelihood of
2635 success. Look for simple insns, such as loads of constants or
2636 binary operations involving a constant. */
2644 if (!flag_expensive_optimizations
)
2647 for (i
= 0; i
< 4; i
++)
2649 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2650 rtx set
= single_set (insn
);
2654 src
= SET_SRC (set
);
2655 if (CONSTANT_P (src
))
2660 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2662 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2663 || GET_CODE (src
) == LSHIFTRT
)
2667 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2668 are likely manipulating its value. Ideally we'll be able to combine
2669 all four insns into a bitfield insertion of some kind.
2671 Note the source in I0 might be inside a sign/zero extension and the
2672 memory modes in I0 and I3 might be different. So extract the address
2673 from the destination of I3 and search for it in the source of I0.
2675 In the event that there's a match but the source/dest do not actually
2676 refer to the same memory, the worst that happens is we try some
2677 combinations that we wouldn't have otherwise. */
2678 if ((set0
= single_set (i0
))
2679 /* Ensure the source of SET0 is a MEM, possibly buried inside
2681 && (GET_CODE (SET_SRC (set0
)) == MEM
2682 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2683 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2684 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2685 && (set3
= single_set (i3
))
2686 /* Ensure the destination of SET3 is a MEM. */
2687 && GET_CODE (SET_DEST (set3
)) == MEM
2688 /* Would it be better to extract the base address for the MEM
2689 in SET3 and look for that? I don't have cases where it matters
2690 but I could envision such cases. */
2691 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2694 if (ngood
< 2 && nshift
< 2)
2698 /* Exit early if one of the insns involved can't be used for
2701 || (i1
&& CALL_P (i1
))
2702 || (i0
&& CALL_P (i0
))
2703 || cant_combine_insn_p (i3
)
2704 || cant_combine_insn_p (i2
)
2705 || (i1
&& cant_combine_insn_p (i1
))
2706 || (i0
&& cant_combine_insn_p (i0
))
2707 || likely_spilled_retval_p (i3
))
2711 undobuf
.other_insn
= 0;
2713 /* Reset the hard register usage information. */
2714 CLEAR_HARD_REG_SET (newpat_used_regs
);
2716 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2719 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2720 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2722 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2723 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2725 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2726 INSN_UID (i2
), INSN_UID (i3
));
2729 /* If multiple insns feed into one of I2 or I3, they can be in any
2730 order. To simplify the code below, reorder them in sequence. */
2731 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2733 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2735 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2738 added_links_insn
= 0;
2740 /* First check for one important special case that the code below will
2741 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2742 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2743 we may be able to replace that destination with the destination of I3.
2744 This occurs in the common code where we compute both a quotient and
2745 remainder into a structure, in which case we want to do the computation
2746 directly into the structure to avoid register-register copies.
2748 Note that this case handles both multiple sets in I2 and also cases
2749 where I2 has a number of CLOBBERs inside the PARALLEL.
2751 We make very conservative checks below and only try to handle the
2752 most common cases of this. For example, we only handle the case
2753 where I2 and I3 are adjacent to avoid making difficult register
2756 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2757 && REG_P (SET_SRC (PATTERN (i3
)))
2758 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2759 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2760 && GET_CODE (PATTERN (i2
)) == PARALLEL
2761 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2762 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2763 below would need to check what is inside (and reg_overlap_mentioned_p
2764 doesn't support those codes anyway). Don't allow those destinations;
2765 the resulting insn isn't likely to be recognized anyway. */
2766 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2767 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2768 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2769 SET_DEST (PATTERN (i3
)))
2770 && next_active_insn (i2
) == i3
)
2772 rtx p2
= PATTERN (i2
);
2774 /* Make sure that the destination of I3,
2775 which we are going to substitute into one output of I2,
2776 is not used within another output of I2. We must avoid making this:
2777 (parallel [(set (mem (reg 69)) ...)
2778 (set (reg 69) ...)])
2779 which is not well-defined as to order of actions.
2780 (Besides, reload can't handle output reloads for this.)
2782 The problem can also happen if the dest of I3 is a memory ref,
2783 if another dest in I2 is an indirect memory ref. */
2784 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2785 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2786 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2787 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2788 SET_DEST (XVECEXP (p2
, 0, i
))))
2791 /* Make sure this PARALLEL is not an asm. We do not allow combining
2792 that usually (see can_combine_p), so do not here either. */
2793 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2794 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2795 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2798 if (i
== XVECLEN (p2
, 0))
2799 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2800 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2801 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2806 subst_low_luid
= DF_INSN_LUID (i2
);
2808 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2809 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2810 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2811 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2813 /* Replace the dest in I2 with our dest and make the resulting
2814 insn the new pattern for I3. Then skip to where we validate
2815 the pattern. Everything was set up above. */
2816 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2818 i3_subst_into_i2
= 1;
2819 goto validate_replacement
;
2823 /* If I2 is setting a pseudo to a constant and I3 is setting some
2824 sub-part of it to another constant, merge them by making a new
2827 && (temp_expr
= single_set (i2
)) != 0
2828 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2829 && GET_CODE (PATTERN (i3
)) == SET
2830 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2831 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2833 rtx dest
= SET_DEST (PATTERN (i3
));
2837 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2839 if (CONST_INT_P (XEXP (dest
, 1))
2840 && CONST_INT_P (XEXP (dest
, 2)))
2842 width
= INTVAL (XEXP (dest
, 1));
2843 offset
= INTVAL (XEXP (dest
, 2));
2844 dest
= XEXP (dest
, 0);
2845 if (BITS_BIG_ENDIAN
)
2846 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2851 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2852 dest
= XEXP (dest
, 0);
2853 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2859 /* If this is the low part, we're done. */
2860 if (subreg_lowpart_p (dest
))
2862 /* Handle the case where inner is twice the size of outer. */
2863 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2864 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2865 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2866 /* Otherwise give up for now. */
2873 rtx inner
= SET_SRC (PATTERN (i3
));
2874 rtx outer
= SET_SRC (temp_expr
);
2877 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2878 std::make_pair (inner
, GET_MODE (dest
)),
2883 subst_low_luid
= DF_INSN_LUID (i2
);
2884 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2885 i2dest
= SET_DEST (temp_expr
);
2886 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2888 /* Replace the source in I2 with the new constant and make the
2889 resulting insn the new pattern for I3. Then skip to where we
2890 validate the pattern. Everything was set up above. */
2891 SUBST (SET_SRC (temp_expr
),
2892 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2894 newpat
= PATTERN (i2
);
2896 /* The dest of I3 has been replaced with the dest of I2. */
2897 changed_i3_dest
= 1;
2898 goto validate_replacement
;
2902 /* If we have no I1 and I2 looks like:
2903 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2905 make up a dummy I1 that is
2908 (set (reg:CC X) (compare:CC Y (const_int 0)))
2910 (We can ignore any trailing CLOBBERs.)
2912 This undoes a previous combination and allows us to match a branch-and-
2915 if (!HAVE_cc0
&& i1
== 0
2916 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2917 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2919 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2920 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2921 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2922 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2923 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2924 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2926 /* We make I1 with the same INSN_UID as I2. This gives it
2927 the same DF_INSN_LUID for value tracking. Our fake I1 will
2928 never appear in the insn stream so giving it the same INSN_UID
2929 as I2 will not cause a problem. */
2931 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2932 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2934 INSN_UID (i1
) = INSN_UID (i2
);
2936 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2937 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2938 SET_DEST (PATTERN (i1
)));
2939 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2940 SUBST_LINK (LOG_LINKS (i2
),
2941 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2944 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2945 make those two SETs separate I1 and I2 insns, and make an I0 that is
2947 if (!HAVE_cc0
&& i0
== 0
2948 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2949 && can_split_parallel_of_n_reg_sets (i2
, 2)
2950 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2951 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2953 /* If there is no I1, there is no I0 either. */
2956 /* We make I1 with the same INSN_UID as I2. This gives it
2957 the same DF_INSN_LUID for value tracking. Our fake I1 will
2958 never appear in the insn stream so giving it the same INSN_UID
2959 as I2 will not cause a problem. */
2961 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2962 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2964 INSN_UID (i1
) = INSN_UID (i2
);
2966 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2969 /* Verify that I2 and I1 are valid for combining. */
2970 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2971 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2973 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2980 /* Record whether I2DEST is used in I2SRC and similarly for the other
2981 cases. Knowing this will help in register status updating below. */
2982 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2983 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2984 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2985 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2986 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2987 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2988 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2989 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2990 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2992 /* For the earlier insns, determine which of the subsequent ones they
2994 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2995 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2996 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2997 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2998 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3000 /* Ensure that I3's pattern can be the destination of combines. */
3001 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3002 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3003 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3004 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3011 /* See if any of the insns is a MULT operation. Unless one is, we will
3012 reject a combination that is, since it must be slower. Be conservative
3014 if (GET_CODE (i2src
) == MULT
3015 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3016 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3017 || (GET_CODE (PATTERN (i3
)) == SET
3018 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3021 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3022 We used to do this EXCEPT in one case: I3 has a post-inc in an
3023 output operand. However, that exception can give rise to insns like
3025 which is a famous insn on the PDP-11 where the value of r3 used as the
3026 source was model-dependent. Avoid this sort of thing. */
3029 if (!(GET_CODE (PATTERN (i3
)) == SET
3030 && REG_P (SET_SRC (PATTERN (i3
)))
3031 && MEM_P (SET_DEST (PATTERN (i3
)))
3032 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3033 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3034 /* It's not the exception. */
3039 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3040 if (REG_NOTE_KIND (link
) == REG_INC
3041 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3043 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3050 /* See if the SETs in I1 or I2 need to be kept around in the merged
3051 instruction: whenever the value set there is still needed past I3.
3052 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3054 For the SET in I1, we have two cases: if I1 and I2 independently feed
3055 into I3, the set in I1 needs to be kept around unless I1DEST dies
3056 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3057 in I1 needs to be kept around unless I1DEST dies or is set in either
3058 I2 or I3. The same considerations apply to I0. */
3060 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3063 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3064 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3069 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3070 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3071 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3072 && dead_or_set_p (i2
, i0dest
)));
3076 /* We are about to copy insns for the case where they need to be kept
3077 around. Check that they can be copied in the merged instruction. */
3079 if (targetm
.cannot_copy_insn_p
3080 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3081 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3082 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3088 /* If the set in I2 needs to be kept around, we must make a copy of
3089 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3090 PATTERN (I2), we are only substituting for the original I1DEST, not into
3091 an already-substituted copy. This also prevents making self-referential
3092 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3097 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3098 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3100 i2pat
= copy_rtx (PATTERN (i2
));
3105 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3106 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3108 i1pat
= copy_rtx (PATTERN (i1
));
3113 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3114 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3116 i0pat
= copy_rtx (PATTERN (i0
));
3121 /* Substitute in the latest insn for the regs set by the earlier ones. */
3123 maxreg
= max_reg_num ();
3127 /* Many machines that don't use CC0 have insns that can both perform an
3128 arithmetic operation and set the condition code. These operations will
3129 be represented as a PARALLEL with the first element of the vector
3130 being a COMPARE of an arithmetic operation with the constant zero.
3131 The second element of the vector will set some pseudo to the result
3132 of the same arithmetic operation. If we simplify the COMPARE, we won't
3133 match such a pattern and so will generate an extra insn. Here we test
3134 for this case, where both the comparison and the operation result are
3135 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3136 I2SRC. Later we will make the PARALLEL that contains I2. */
3138 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3139 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3140 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3141 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3144 rtx
*cc_use_loc
= NULL
;
3145 rtx_insn
*cc_use_insn
= NULL
;
3146 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3147 machine_mode compare_mode
, orig_compare_mode
;
3148 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3150 newpat
= PATTERN (i3
);
3151 newpat_dest
= SET_DEST (newpat
);
3152 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3154 if (undobuf
.other_insn
== 0
3155 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3158 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3159 compare_code
= simplify_compare_const (compare_code
,
3160 GET_MODE (i2dest
), op0
, &op1
);
3161 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3164 /* Do the rest only if op1 is const0_rtx, which may be the
3165 result of simplification. */
3166 if (op1
== const0_rtx
)
3168 /* If a single use of the CC is found, prepare to modify it
3169 when SELECT_CC_MODE returns a new CC-class mode, or when
3170 the above simplify_compare_const() returned a new comparison
3171 operator. undobuf.other_insn is assigned the CC use insn
3172 when modifying it. */
3175 #ifdef SELECT_CC_MODE
3176 machine_mode new_mode
3177 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3178 if (new_mode
!= orig_compare_mode
3179 && can_change_dest_mode (SET_DEST (newpat
),
3180 added_sets_2
, new_mode
))
3182 unsigned int regno
= REGNO (newpat_dest
);
3183 compare_mode
= new_mode
;
3184 if (regno
< FIRST_PSEUDO_REGISTER
)
3185 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3188 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3189 newpat_dest
= regno_reg_rtx
[regno
];
3193 /* Cases for modifying the CC-using comparison. */
3194 if (compare_code
!= orig_compare_code
3195 /* ??? Do we need to verify the zero rtx? */
3196 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3198 /* Replace cc_use_loc with entire new RTX. */
3200 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3201 newpat_dest
, const0_rtx
));
3202 undobuf
.other_insn
= cc_use_insn
;
3204 else if (compare_mode
!= orig_compare_mode
)
3206 /* Just replace the CC reg with a new mode. */
3207 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3208 undobuf
.other_insn
= cc_use_insn
;
3212 /* Now we modify the current newpat:
3213 First, SET_DEST(newpat) is updated if the CC mode has been
3214 altered. For targets without SELECT_CC_MODE, this should be
3216 if (compare_mode
!= orig_compare_mode
)
3217 SUBST (SET_DEST (newpat
), newpat_dest
);
3218 /* This is always done to propagate i2src into newpat. */
3219 SUBST (SET_SRC (newpat
),
3220 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3221 /* Create new version of i2pat if needed; the below PARALLEL
3222 creation needs this to work correctly. */
3223 if (! rtx_equal_p (i2src
, op0
))
3224 i2pat
= gen_rtx_SET (i2dest
, op0
);
3229 if (i2_is_used
== 0)
3231 /* It is possible that the source of I2 or I1 may be performing
3232 an unneeded operation, such as a ZERO_EXTEND of something
3233 that is known to have the high part zero. Handle that case
3234 by letting subst look at the inner insns.
3236 Another way to do this would be to have a function that tries
3237 to simplify a single insn instead of merging two or more
3238 insns. We don't do this because of the potential of infinite
3239 loops and because of the potential extra memory required.
3240 However, doing it the way we are is a bit of a kludge and
3241 doesn't catch all cases.
3243 But only do this if -fexpensive-optimizations since it slows
3244 things down and doesn't usually win.
3246 This is not done in the COMPARE case above because the
3247 unmodified I2PAT is used in the PARALLEL and so a pattern
3248 with a modified I2SRC would not match. */
3250 if (flag_expensive_optimizations
)
3252 /* Pass pc_rtx so no substitutions are done, just
3256 subst_low_luid
= DF_INSN_LUID (i1
);
3257 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3260 subst_low_luid
= DF_INSN_LUID (i2
);
3261 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3264 n_occurrences
= 0; /* `subst' counts here */
3265 subst_low_luid
= DF_INSN_LUID (i2
);
3267 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3268 copy of I2SRC each time we substitute it, in order to avoid creating
3269 self-referential RTL when we will be substituting I1SRC for I1DEST
3270 later. Likewise if I0 feeds into I2, either directly or indirectly
3271 through I1, and I0DEST is in I0SRC. */
3272 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3273 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3274 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3275 && i0dest_in_i0src
));
3278 /* Record whether I2's body now appears within I3's body. */
3279 i2_is_used
= n_occurrences
;
3282 /* If we already got a failure, don't try to do more. Otherwise, try to
3283 substitute I1 if we have it. */
3285 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3287 /* Check that an autoincrement side-effect on I1 has not been lost.
3288 This happens if I1DEST is mentioned in I2 and dies there, and
3289 has disappeared from the new pattern. */
3290 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3292 && dead_or_set_p (i2
, i1dest
)
3293 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3294 /* Before we can do this substitution, we must redo the test done
3295 above (see detailed comments there) that ensures I1DEST isn't
3296 mentioned in any SETs in NEWPAT that are field assignments. */
3297 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3305 subst_low_luid
= DF_INSN_LUID (i1
);
3307 /* If the following substitution will modify I1SRC, make a copy of it
3308 for the case where it is substituted for I1DEST in I2PAT later. */
3309 if (added_sets_2
&& i1_feeds_i2_n
)
3310 i1src_copy
= copy_rtx (i1src
);
3312 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3313 copy of I1SRC each time we substitute it, in order to avoid creating
3314 self-referential RTL when we will be substituting I0SRC for I0DEST
3316 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3317 i0_feeds_i1_n
&& i0dest_in_i0src
);
3320 /* Record whether I1's body now appears within I3's body. */
3321 i1_is_used
= n_occurrences
;
3324 /* Likewise for I0 if we have it. */
3326 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3328 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3329 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3330 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3331 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3332 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3339 /* If the following substitution will modify I0SRC, make a copy of it
3340 for the case where it is substituted for I0DEST in I1PAT later. */
3341 if (added_sets_1
&& i0_feeds_i1_n
)
3342 i0src_copy
= copy_rtx (i0src
);
3343 /* And a copy for I0DEST in I2PAT substitution. */
3344 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3345 || (i0_feeds_i2_n
)))
3346 i0src_copy2
= copy_rtx (i0src
);
3349 subst_low_luid
= DF_INSN_LUID (i0
);
3350 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3354 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3355 to count all the ways that I2SRC and I1SRC can be used. */
3356 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3357 && i2_is_used
+ added_sets_2
> 1)
3358 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3359 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3361 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3362 && (n_occurrences
+ added_sets_0
3363 + (added_sets_1
&& i0_feeds_i1_n
)
3364 + (added_sets_2
&& i0_feeds_i2_n
)
3366 /* Fail if we tried to make a new register. */
3367 || max_reg_num () != maxreg
3368 /* Fail if we couldn't do something and have a CLOBBER. */
3369 || GET_CODE (newpat
) == CLOBBER
3370 /* Fail if this new pattern is a MULT and we didn't have one before
3371 at the outer level. */
3372 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3379 /* If the actions of the earlier insns must be kept
3380 in addition to substituting them into the latest one,
3381 we must make a new PARALLEL for the latest insn
3382 to hold additional the SETs. */
3384 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3386 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3389 if (GET_CODE (newpat
) == PARALLEL
)
3391 rtvec old
= XVEC (newpat
, 0);
3392 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3393 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3394 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3395 sizeof (old
->elem
[0]) * old
->num_elem
);
3400 total_sets
= 1 + extra_sets
;
3401 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3402 XVECEXP (newpat
, 0, 0) = old
;
3406 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3412 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3414 XVECEXP (newpat
, 0, --total_sets
) = t
;
3420 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3421 i0_feeds_i1_n
&& i0dest_in_i0src
);
3422 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3423 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3425 XVECEXP (newpat
, 0, --total_sets
) = t
;
3429 validate_replacement
:
3431 /* Note which hard regs this insn has as inputs. */
3432 mark_used_regs_combine (newpat
);
3434 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3435 consider splitting this pattern, we might need these clobbers. */
3436 if (i1
&& GET_CODE (newpat
) == PARALLEL
3437 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3439 int len
= XVECLEN (newpat
, 0);
3441 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3442 for (i
= 0; i
< len
; i
++)
3443 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3446 /* We have recognized nothing yet. */
3447 insn_code_number
= -1;
3449 /* See if this is a PARALLEL of two SETs where one SET's destination is
3450 a register that is unused and this isn't marked as an instruction that
3451 might trap in an EH region. In that case, we just need the other SET.
3452 We prefer this over the PARALLEL.
3454 This can occur when simplifying a divmod insn. We *must* test for this
3455 case here because the code below that splits two independent SETs doesn't
3456 handle this case correctly when it updates the register status.
3458 It's pointless doing this if we originally had two sets, one from
3459 i3, and one from i2. Combining then splitting the parallel results
3460 in the original i2 again plus an invalid insn (which we delete).
3461 The net effect is only to move instructions around, which makes
3462 debug info less accurate. */
3464 if (!(added_sets_2
&& i1
== 0)
3465 && is_parallel_of_n_reg_sets (newpat
, 2)
3466 && asm_noperands (newpat
) < 0)
3468 rtx set0
= XVECEXP (newpat
, 0, 0);
3469 rtx set1
= XVECEXP (newpat
, 0, 1);
3470 rtx oldpat
= newpat
;
3472 if (((REG_P (SET_DEST (set1
))
3473 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3474 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3475 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3476 && insn_nothrow_p (i3
)
3477 && !side_effects_p (SET_SRC (set1
)))
3480 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3483 else if (((REG_P (SET_DEST (set0
))
3484 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3485 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3486 && find_reg_note (i3
, REG_UNUSED
,
3487 SUBREG_REG (SET_DEST (set0
)))))
3488 && insn_nothrow_p (i3
)
3489 && !side_effects_p (SET_SRC (set0
)))
3492 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3494 if (insn_code_number
>= 0)
3495 changed_i3_dest
= 1;
3498 if (insn_code_number
< 0)
3502 /* Is the result of combination a valid instruction? */
3503 if (insn_code_number
< 0)
3504 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3506 /* If we were combining three insns and the result is a simple SET
3507 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3508 insns. There are two ways to do this. It can be split using a
3509 machine-specific method (like when you have an addition of a large
3510 constant) or by combine in the function find_split_point. */
3512 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3513 && asm_noperands (newpat
) < 0)
3515 rtx parallel
, *split
;
3516 rtx_insn
*m_split_insn
;
3518 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3519 use I2DEST as a scratch register will help. In the latter case,
3520 convert I2DEST to the mode of the source of NEWPAT if we can. */
3522 m_split_insn
= combine_split_insns (newpat
, i3
);
3524 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3525 inputs of NEWPAT. */
3527 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3528 possible to try that as a scratch reg. This would require adding
3529 more code to make it work though. */
3531 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3533 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3535 /* First try to split using the original register as a
3536 scratch register. */
3537 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3538 gen_rtvec (2, newpat
,
3539 gen_rtx_CLOBBER (VOIDmode
,
3541 m_split_insn
= combine_split_insns (parallel
, i3
);
3543 /* If that didn't work, try changing the mode of I2DEST if
3545 if (m_split_insn
== 0
3546 && new_mode
!= GET_MODE (i2dest
)
3547 && new_mode
!= VOIDmode
3548 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3550 machine_mode old_mode
= GET_MODE (i2dest
);
3553 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3554 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3557 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3558 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3561 parallel
= (gen_rtx_PARALLEL
3563 gen_rtvec (2, newpat
,
3564 gen_rtx_CLOBBER (VOIDmode
,
3566 m_split_insn
= combine_split_insns (parallel
, i3
);
3568 if (m_split_insn
== 0
3569 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3573 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3574 buf
= undobuf
.undos
;
3575 undobuf
.undos
= buf
->next
;
3576 buf
->next
= undobuf
.frees
;
3577 undobuf
.frees
= buf
;
3581 i2scratch
= m_split_insn
!= 0;
3584 /* If recog_for_combine has discarded clobbers, try to use them
3585 again for the split. */
3586 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3588 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3589 m_split_insn
= combine_split_insns (parallel
, i3
);
3592 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3594 rtx m_split_pat
= PATTERN (m_split_insn
);
3595 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3596 if (insn_code_number
>= 0)
3597 newpat
= m_split_pat
;
3599 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3600 && (next_nonnote_nondebug_insn (i2
) == i3
3601 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3604 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3605 newi2pat
= PATTERN (m_split_insn
);
3607 i3set
= single_set (NEXT_INSN (m_split_insn
));
3608 i2set
= single_set (m_split_insn
);
3610 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3612 /* If I2 or I3 has multiple SETs, we won't know how to track
3613 register status, so don't use these insns. If I2's destination
3614 is used between I2 and I3, we also can't use these insns. */
3616 if (i2_code_number
>= 0 && i2set
&& i3set
3617 && (next_nonnote_nondebug_insn (i2
) == i3
3618 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3619 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3621 if (insn_code_number
>= 0)
3624 /* It is possible that both insns now set the destination of I3.
3625 If so, we must show an extra use of it. */
3627 if (insn_code_number
>= 0)
3629 rtx new_i3_dest
= SET_DEST (i3set
);
3630 rtx new_i2_dest
= SET_DEST (i2set
);
3632 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3633 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3634 || GET_CODE (new_i3_dest
) == SUBREG
)
3635 new_i3_dest
= XEXP (new_i3_dest
, 0);
3637 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3638 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3639 || GET_CODE (new_i2_dest
) == SUBREG
)
3640 new_i2_dest
= XEXP (new_i2_dest
, 0);
3642 if (REG_P (new_i3_dest
)
3643 && REG_P (new_i2_dest
)
3644 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3645 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3646 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3650 /* If we can split it and use I2DEST, go ahead and see if that
3651 helps things be recognized. Verify that none of the registers
3652 are set between I2 and I3. */
3653 if (insn_code_number
< 0
3654 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3655 && (!HAVE_cc0
|| REG_P (i2dest
))
3656 /* We need I2DEST in the proper mode. If it is a hard register
3657 or the only use of a pseudo, we can change its mode.
3658 Make sure we don't change a hard register to have a mode that
3659 isn't valid for it, or change the number of registers. */
3660 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3661 || GET_MODE (*split
) == VOIDmode
3662 || can_change_dest_mode (i2dest
, added_sets_2
,
3664 && (next_nonnote_nondebug_insn (i2
) == i3
3665 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3666 /* We can't overwrite I2DEST if its value is still used by
3668 && ! reg_referenced_p (i2dest
, newpat
))
3670 rtx newdest
= i2dest
;
3671 enum rtx_code split_code
= GET_CODE (*split
);
3672 machine_mode split_mode
= GET_MODE (*split
);
3673 bool subst_done
= false;
3674 newi2pat
= NULL_RTX
;
3678 /* *SPLIT may be part of I2SRC, so make sure we have the
3679 original expression around for later debug processing.
3680 We should not need I2SRC any more in other cases. */
3681 if (MAY_HAVE_DEBUG_INSNS
)
3682 i2src
= copy_rtx (i2src
);
3686 /* Get NEWDEST as a register in the proper mode. We have already
3687 validated that we can do this. */
3688 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3690 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3691 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3694 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3695 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3699 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3700 an ASHIFT. This can occur if it was inside a PLUS and hence
3701 appeared to be a memory address. This is a kludge. */
3702 if (split_code
== MULT
3703 && CONST_INT_P (XEXP (*split
, 1))
3704 && INTVAL (XEXP (*split
, 1)) > 0
3705 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3707 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3708 XEXP (*split
, 0), GEN_INT (i
)));
3709 /* Update split_code because we may not have a multiply
3711 split_code
= GET_CODE (*split
);
3714 /* Similarly for (plus (mult FOO (const_int pow2))). */
3715 if (split_code
== PLUS
3716 && GET_CODE (XEXP (*split
, 0)) == MULT
3717 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3718 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3719 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3721 rtx nsplit
= XEXP (*split
, 0);
3722 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3723 XEXP (nsplit
, 0), GEN_INT (i
)));
3724 /* Update split_code because we may not have a multiply
3726 split_code
= GET_CODE (*split
);
3729 #ifdef INSN_SCHEDULING
3730 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3731 be written as a ZERO_EXTEND. */
3732 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3734 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3735 what it really is. */
3736 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3738 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3739 SUBREG_REG (*split
)));
3741 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3742 SUBREG_REG (*split
)));
3746 /* Attempt to split binary operators using arithmetic identities. */
3747 if (BINARY_P (SET_SRC (newpat
))
3748 && split_mode
== GET_MODE (SET_SRC (newpat
))
3749 && ! side_effects_p (SET_SRC (newpat
)))
3751 rtx setsrc
= SET_SRC (newpat
);
3752 machine_mode mode
= GET_MODE (setsrc
);
3753 enum rtx_code code
= GET_CODE (setsrc
);
3754 rtx src_op0
= XEXP (setsrc
, 0);
3755 rtx src_op1
= XEXP (setsrc
, 1);
3757 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3758 if (rtx_equal_p (src_op0
, src_op1
))
3760 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3761 SUBST (XEXP (setsrc
, 0), newdest
);
3762 SUBST (XEXP (setsrc
, 1), newdest
);
3765 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3766 else if ((code
== PLUS
|| code
== MULT
)
3767 && GET_CODE (src_op0
) == code
3768 && GET_CODE (XEXP (src_op0
, 0)) == code
3769 && (INTEGRAL_MODE_P (mode
)
3770 || (FLOAT_MODE_P (mode
)
3771 && flag_unsafe_math_optimizations
)))
3773 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3774 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3775 rtx r
= XEXP (src_op0
, 1);
3778 /* Split both "((X op Y) op X) op Y" and
3779 "((X op Y) op Y) op X" as "T op T" where T is
3781 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3782 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3784 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3785 SUBST (XEXP (setsrc
, 0), newdest
);
3786 SUBST (XEXP (setsrc
, 1), newdest
);
3789 /* Split "((X op X) op Y) op Y)" as "T op T" where
3791 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3793 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3794 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3795 SUBST (XEXP (setsrc
, 0), newdest
);
3796 SUBST (XEXP (setsrc
, 1), newdest
);
3804 newi2pat
= gen_rtx_SET (newdest
, *split
);
3805 SUBST (*split
, newdest
);
3808 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3810 /* recog_for_combine might have added CLOBBERs to newi2pat.
3811 Make sure NEWPAT does not depend on the clobbered regs. */
3812 if (GET_CODE (newi2pat
) == PARALLEL
)
3813 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3814 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3816 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3817 if (reg_overlap_mentioned_p (reg
, newpat
))
3824 /* If the split point was a MULT and we didn't have one before,
3825 don't use one now. */
3826 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3827 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3831 /* Check for a case where we loaded from memory in a narrow mode and
3832 then sign extended it, but we need both registers. In that case,
3833 we have a PARALLEL with both loads from the same memory location.
3834 We can split this into a load from memory followed by a register-register
3835 copy. This saves at least one insn, more if register allocation can
3838 We cannot do this if the destination of the first assignment is a
3839 condition code register or cc0. We eliminate this case by making sure
3840 the SET_DEST and SET_SRC have the same mode.
3842 We cannot do this if the destination of the second assignment is
3843 a register that we have already assumed is zero-extended. Similarly
3844 for a SUBREG of such a register. */
3846 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3847 && GET_CODE (newpat
) == PARALLEL
3848 && XVECLEN (newpat
, 0) == 2
3849 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3850 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3851 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3852 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3853 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3854 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3855 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3856 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3858 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3859 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3860 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3862 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3863 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3864 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3865 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3866 != GET_MODE_MASK (word_mode
))))
3867 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3868 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3870 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3871 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3872 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3873 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3874 != GET_MODE_MASK (word_mode
)))))
3875 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3876 SET_SRC (XVECEXP (newpat
, 0, 1)))
3877 && ! find_reg_note (i3
, REG_UNUSED
,
3878 SET_DEST (XVECEXP (newpat
, 0, 0))))
3882 newi2pat
= XVECEXP (newpat
, 0, 0);
3883 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3884 newpat
= XVECEXP (newpat
, 0, 1);
3885 SUBST (SET_SRC (newpat
),
3886 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3887 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3889 if (i2_code_number
>= 0)
3890 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3892 if (insn_code_number
>= 0)
3896 /* Similarly, check for a case where we have a PARALLEL of two independent
3897 SETs but we started with three insns. In this case, we can do the sets
3898 as two separate insns. This case occurs when some SET allows two
3899 other insns to combine, but the destination of that SET is still live.
3901 Also do this if we started with two insns and (at least) one of the
3902 resulting sets is a noop; this noop will be deleted later. */
3904 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3905 && GET_CODE (newpat
) == PARALLEL
3906 && XVECLEN (newpat
, 0) == 2
3907 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3908 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3909 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3910 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3911 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3912 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3913 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3914 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3915 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3916 XVECEXP (newpat
, 0, 0))
3917 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3918 XVECEXP (newpat
, 0, 1))
3919 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3920 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3922 rtx set0
= XVECEXP (newpat
, 0, 0);
3923 rtx set1
= XVECEXP (newpat
, 0, 1);
3925 /* Normally, it doesn't matter which of the two is done first,
3926 but the one that references cc0 can't be the second, and
3927 one which uses any regs/memory set in between i2 and i3 can't
3928 be first. The PARALLEL might also have been pre-existing in i3,
3929 so we need to make sure that we won't wrongly hoist a SET to i2
3930 that would conflict with a death note present in there. */
3931 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3932 && !(REG_P (SET_DEST (set1
))
3933 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3934 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3935 && find_reg_note (i2
, REG_DEAD
,
3936 SUBREG_REG (SET_DEST (set1
))))
3937 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3938 /* If I3 is a jump, ensure that set0 is a jump so that
3939 we do not create invalid RTL. */
3940 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3946 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3947 && !(REG_P (SET_DEST (set0
))
3948 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3949 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3950 && find_reg_note (i2
, REG_DEAD
,
3951 SUBREG_REG (SET_DEST (set0
))))
3952 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3953 /* If I3 is a jump, ensure that set1 is a jump so that
3954 we do not create invalid RTL. */
3955 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3967 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3969 if (i2_code_number
>= 0)
3971 /* recog_for_combine might have added CLOBBERs to newi2pat.
3972 Make sure NEWPAT does not depend on the clobbered regs. */
3973 if (GET_CODE (newi2pat
) == PARALLEL
)
3975 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3976 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3978 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3979 if (reg_overlap_mentioned_p (reg
, newpat
))
3987 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3991 /* If it still isn't recognized, fail and change things back the way they
3993 if ((insn_code_number
< 0
3994 /* Is the result a reasonable ASM_OPERANDS? */
3995 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4001 /* If we had to change another insn, make sure it is valid also. */
4002 if (undobuf
.other_insn
)
4004 CLEAR_HARD_REG_SET (newpat_used_regs
);
4006 other_pat
= PATTERN (undobuf
.other_insn
);
4007 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4010 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4017 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4018 they are adjacent to each other or not. */
4021 rtx_insn
*p
= prev_nonnote_insn (i3
);
4022 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4023 && sets_cc0_p (newi2pat
))
4030 /* Only allow this combination if insn_rtx_costs reports that the
4031 replacement instructions are cheaper than the originals. */
4032 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4038 if (MAY_HAVE_DEBUG_INSNS
)
4042 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4043 if (undo
->kind
== UNDO_MODE
)
4045 rtx reg
= *undo
->where
.r
;
4046 machine_mode new_mode
= GET_MODE (reg
);
4047 machine_mode old_mode
= undo
->old_contents
.m
;
4049 /* Temporarily revert mode back. */
4050 adjust_reg_mode (reg
, old_mode
);
4052 if (reg
== i2dest
&& i2scratch
)
4054 /* If we used i2dest as a scratch register with a
4055 different mode, substitute it for the original
4056 i2src while its original mode is temporarily
4057 restored, and then clear i2scratch so that we don't
4058 do it again later. */
4059 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4062 /* Put back the new mode. */
4063 adjust_reg_mode (reg
, new_mode
);
4067 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4068 rtx_insn
*first
, *last
;
4073 last
= last_combined_insn
;
4078 last
= undobuf
.other_insn
;
4080 if (DF_INSN_LUID (last
)
4081 < DF_INSN_LUID (last_combined_insn
))
4082 last
= last_combined_insn
;
4085 /* We're dealing with a reg that changed mode but not
4086 meaning, so we want to turn it into a subreg for
4087 the new mode. However, because of REG sharing and
4088 because its mode had already changed, we have to do
4089 it in two steps. First, replace any debug uses of
4090 reg, with its original mode temporarily restored,
4091 with this copy we have created; then, replace the
4092 copy with the SUBREG of the original shared reg,
4093 once again changed to the new mode. */
4094 propagate_for_debug (first
, last
, reg
, tempreg
,
4096 adjust_reg_mode (reg
, new_mode
);
4097 propagate_for_debug (first
, last
, tempreg
,
4098 lowpart_subreg (old_mode
, reg
, new_mode
),
4104 /* If we will be able to accept this, we have made a
4105 change to the destination of I3. This requires us to
4106 do a few adjustments. */
4108 if (changed_i3_dest
)
4110 PATTERN (i3
) = newpat
;
4111 adjust_for_new_dest (i3
);
4114 /* We now know that we can do this combination. Merge the insns and
4115 update the status of registers and LOG_LINKS. */
4117 if (undobuf
.other_insn
)
4121 PATTERN (undobuf
.other_insn
) = other_pat
;
4123 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4124 ensure that they are still valid. Then add any non-duplicate
4125 notes added by recog_for_combine. */
4126 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4128 next
= XEXP (note
, 1);
4130 if ((REG_NOTE_KIND (note
) == REG_DEAD
4131 && !reg_referenced_p (XEXP (note
, 0),
4132 PATTERN (undobuf
.other_insn
)))
4133 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4134 && !reg_set_p (XEXP (note
, 0),
4135 PATTERN (undobuf
.other_insn
))))
4136 remove_note (undobuf
.other_insn
, note
);
4139 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4140 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4147 struct insn_link
*link
;
4150 /* I3 now uses what used to be its destination and which is now
4151 I2's destination. This requires us to do a few adjustments. */
4152 PATTERN (i3
) = newpat
;
4153 adjust_for_new_dest (i3
);
4155 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4158 However, some later insn might be using I2's dest and have
4159 a LOG_LINK pointing at I3. We must remove this link.
4160 The simplest way to remove the link is to point it at I1,
4161 which we know will be a NOTE. */
4163 /* newi2pat is usually a SET here; however, recog_for_combine might
4164 have added some clobbers. */
4165 if (GET_CODE (newi2pat
) == PARALLEL
)
4166 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4168 ni2dest
= SET_DEST (newi2pat
);
4170 for (insn
= NEXT_INSN (i3
);
4171 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4172 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4173 insn
= NEXT_INSN (insn
))
4175 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4177 FOR_EACH_LOG_LINK (link
, insn
)
4178 if (link
->insn
== i3
)
4187 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4188 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4191 /* Compute which registers we expect to eliminate. newi2pat may be setting
4192 either i3dest or i2dest, so we must check it. */
4193 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4194 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4197 /* For i1, we need to compute both local elimination and global
4198 elimination information with respect to newi2pat because i1dest
4199 may be the same as i3dest, in which case newi2pat may be setting
4200 i1dest. Global information is used when distributing REG_DEAD
4201 note for i2 and i3, in which case it does matter if newi2pat sets
4204 Local information is used when distributing REG_DEAD note for i1,
4205 in which case it doesn't matter if newi2pat sets i1dest or not.
4206 See PR62151, if we have four insns combination:
4208 i1: r1 <- i1src (using r0)
4210 i2: r0 <- i2src (using r1)
4211 i3: r3 <- i3src (using r0)
4213 From i1's point of view, r0 is eliminated, no matter if it is set
4214 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4215 should be discarded.
4217 Note local information only affects cases in forms like "I1->I2->I3",
4218 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4219 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4221 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4224 rtx elim_i1
= (local_elim_i1
== 0
4225 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4227 /* Same case as i1. */
4228 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4230 rtx elim_i0
= (local_elim_i0
== 0
4231 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4234 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4236 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4237 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4239 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4241 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4243 /* Ensure that we do not have something that should not be shared but
4244 occurs multiple times in the new insns. Check this by first
4245 resetting all the `used' flags and then copying anything is shared. */
4247 reset_used_flags (i3notes
);
4248 reset_used_flags (i2notes
);
4249 reset_used_flags (i1notes
);
4250 reset_used_flags (i0notes
);
4251 reset_used_flags (newpat
);
4252 reset_used_flags (newi2pat
);
4253 if (undobuf
.other_insn
)
4254 reset_used_flags (PATTERN (undobuf
.other_insn
));
4256 i3notes
= copy_rtx_if_shared (i3notes
);
4257 i2notes
= copy_rtx_if_shared (i2notes
);
4258 i1notes
= copy_rtx_if_shared (i1notes
);
4259 i0notes
= copy_rtx_if_shared (i0notes
);
4260 newpat
= copy_rtx_if_shared (newpat
);
4261 newi2pat
= copy_rtx_if_shared (newi2pat
);
4262 if (undobuf
.other_insn
)
4263 reset_used_flags (PATTERN (undobuf
.other_insn
));
4265 INSN_CODE (i3
) = insn_code_number
;
4266 PATTERN (i3
) = newpat
;
4268 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4270 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4272 reset_used_flags (call_usage
);
4273 call_usage
= copy_rtx (call_usage
);
4277 /* I2SRC must still be meaningful at this point. Some splitting
4278 operations can invalidate I2SRC, but those operations do not
4281 replace_rtx (call_usage
, i2dest
, i2src
);
4285 replace_rtx (call_usage
, i1dest
, i1src
);
4287 replace_rtx (call_usage
, i0dest
, i0src
);
4289 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4292 if (undobuf
.other_insn
)
4293 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4295 /* We had one special case above where I2 had more than one set and
4296 we replaced a destination of one of those sets with the destination
4297 of I3. In that case, we have to update LOG_LINKS of insns later
4298 in this basic block. Note that this (expensive) case is rare.
4300 Also, in this case, we must pretend that all REG_NOTEs for I2
4301 actually came from I3, so that REG_UNUSED notes from I2 will be
4302 properly handled. */
4304 if (i3_subst_into_i2
)
4306 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4307 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4308 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4309 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4310 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4311 && ! find_reg_note (i2
, REG_UNUSED
,
4312 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4313 for (temp_insn
= NEXT_INSN (i2
);
4315 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4316 || BB_HEAD (this_basic_block
) != temp_insn
);
4317 temp_insn
= NEXT_INSN (temp_insn
))
4318 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4319 FOR_EACH_LOG_LINK (link
, temp_insn
)
4320 if (link
->insn
== i2
)
4326 while (XEXP (link
, 1))
4327 link
= XEXP (link
, 1);
4328 XEXP (link
, 1) = i2notes
;
4335 LOG_LINKS (i3
) = NULL
;
4337 LOG_LINKS (i2
) = NULL
;
4342 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4343 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4345 INSN_CODE (i2
) = i2_code_number
;
4346 PATTERN (i2
) = newi2pat
;
4350 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4351 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4353 SET_INSN_DELETED (i2
);
4358 LOG_LINKS (i1
) = NULL
;
4360 if (MAY_HAVE_DEBUG_INSNS
)
4361 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4363 SET_INSN_DELETED (i1
);
4368 LOG_LINKS (i0
) = NULL
;
4370 if (MAY_HAVE_DEBUG_INSNS
)
4371 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4373 SET_INSN_DELETED (i0
);
4376 /* Get death notes for everything that is now used in either I3 or
4377 I2 and used to die in a previous insn. If we built two new
4378 patterns, move from I1 to I2 then I2 to I3 so that we get the
4379 proper movement on registers that I2 modifies. */
4382 from_luid
= DF_INSN_LUID (i0
);
4384 from_luid
= DF_INSN_LUID (i1
);
4386 from_luid
= DF_INSN_LUID (i2
);
4388 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4389 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4391 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4393 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4394 elim_i2
, elim_i1
, elim_i0
);
4396 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4397 elim_i2
, elim_i1
, elim_i0
);
4399 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4400 elim_i2
, local_elim_i1
, local_elim_i0
);
4402 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4403 elim_i2
, elim_i1
, local_elim_i0
);
4405 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4406 elim_i2
, elim_i1
, elim_i0
);
4408 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4409 know these are REG_UNUSED and want them to go to the desired insn,
4410 so we always pass it as i3. */
4412 if (newi2pat
&& new_i2_notes
)
4413 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4417 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4420 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4421 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4422 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4423 in that case, it might delete I2. Similarly for I2 and I1.
4424 Show an additional death due to the REG_DEAD note we make here. If
4425 we discard it in distribute_notes, we will decrement it again. */
4429 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4430 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4431 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4434 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4435 elim_i2
, elim_i1
, elim_i0
);
4438 if (i2dest_in_i2src
)
4440 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4441 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4442 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4443 NULL_RTX
, NULL_RTX
);
4445 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4446 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4449 if (i1dest_in_i1src
)
4451 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4452 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4453 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4454 NULL_RTX
, NULL_RTX
);
4456 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4457 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4460 if (i0dest_in_i0src
)
4462 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4463 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4464 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4465 NULL_RTX
, NULL_RTX
);
4467 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4468 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4471 distribute_links (i3links
);
4472 distribute_links (i2links
);
4473 distribute_links (i1links
);
4474 distribute_links (i0links
);
4478 struct insn_link
*link
;
4479 rtx_insn
*i2_insn
= 0;
4480 rtx i2_val
= 0, set
;
4482 /* The insn that used to set this register doesn't exist, and
4483 this life of the register may not exist either. See if one of
4484 I3's links points to an insn that sets I2DEST. If it does,
4485 that is now the last known value for I2DEST. If we don't update
4486 this and I2 set the register to a value that depended on its old
4487 contents, we will get confused. If this insn is used, thing
4488 will be set correctly in combine_instructions. */
4489 FOR_EACH_LOG_LINK (link
, i3
)
4490 if ((set
= single_set (link
->insn
)) != 0
4491 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4492 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4494 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4496 /* If the reg formerly set in I2 died only once and that was in I3,
4497 zero its use count so it won't make `reload' do any work. */
4499 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4500 && ! i2dest_in_i2src
4501 && REGNO (i2dest
) < reg_n_sets_max
)
4502 INC_REG_N_SETS (REGNO (i2dest
), -1);
4505 if (i1
&& REG_P (i1dest
))
4507 struct insn_link
*link
;
4508 rtx_insn
*i1_insn
= 0;
4509 rtx i1_val
= 0, set
;
4511 FOR_EACH_LOG_LINK (link
, i3
)
4512 if ((set
= single_set (link
->insn
)) != 0
4513 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4514 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4516 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4519 && ! i1dest_in_i1src
4520 && REGNO (i1dest
) < reg_n_sets_max
)
4521 INC_REG_N_SETS (REGNO (i1dest
), -1);
4524 if (i0
&& REG_P (i0dest
))
4526 struct insn_link
*link
;
4527 rtx_insn
*i0_insn
= 0;
4528 rtx i0_val
= 0, set
;
4530 FOR_EACH_LOG_LINK (link
, i3
)
4531 if ((set
= single_set (link
->insn
)) != 0
4532 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4533 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4535 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4538 && ! i0dest_in_i0src
4539 && REGNO (i0dest
) < reg_n_sets_max
)
4540 INC_REG_N_SETS (REGNO (i0dest
), -1);
4543 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4544 been made to this insn. The order is important, because newi2pat
4545 can affect nonzero_bits of newpat. */
4547 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4548 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4551 if (undobuf
.other_insn
!= NULL_RTX
)
4555 fprintf (dump_file
, "modifying other_insn ");
4556 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4558 df_insn_rescan (undobuf
.other_insn
);
4561 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4565 fprintf (dump_file
, "modifying insn i0 ");
4566 dump_insn_slim (dump_file
, i0
);
4568 df_insn_rescan (i0
);
4571 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4575 fprintf (dump_file
, "modifying insn i1 ");
4576 dump_insn_slim (dump_file
, i1
);
4578 df_insn_rescan (i1
);
4581 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4585 fprintf (dump_file
, "modifying insn i2 ");
4586 dump_insn_slim (dump_file
, i2
);
4588 df_insn_rescan (i2
);
4591 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4595 fprintf (dump_file
, "modifying insn i3 ");
4596 dump_insn_slim (dump_file
, i3
);
4598 df_insn_rescan (i3
);
4601 /* Set new_direct_jump_p if a new return or simple jump instruction
4602 has been created. Adjust the CFG accordingly. */
4603 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4605 *new_direct_jump_p
= 1;
4606 mark_jump_label (PATTERN (i3
), i3
, 0);
4607 update_cfg_for_uncondjump (i3
);
4610 if (undobuf
.other_insn
!= NULL_RTX
4611 && (returnjump_p (undobuf
.other_insn
)
4612 || any_uncondjump_p (undobuf
.other_insn
)))
4614 *new_direct_jump_p
= 1;
4615 update_cfg_for_uncondjump (undobuf
.other_insn
);
4618 /* A noop might also need cleaning up of CFG, if it comes from the
4619 simplification of a jump. */
4621 && GET_CODE (newpat
) == SET
4622 && SET_SRC (newpat
) == pc_rtx
4623 && SET_DEST (newpat
) == pc_rtx
)
4625 *new_direct_jump_p
= 1;
4626 update_cfg_for_uncondjump (i3
);
4629 if (undobuf
.other_insn
!= NULL_RTX
4630 && JUMP_P (undobuf
.other_insn
)
4631 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4632 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4633 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4635 *new_direct_jump_p
= 1;
4636 update_cfg_for_uncondjump (undobuf
.other_insn
);
4639 combine_successes
++;
4642 if (added_links_insn
4643 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4644 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4645 return added_links_insn
;
4647 return newi2pat
? i2
: i3
;
4650 /* Get a marker for undoing to the current state. */
4653 get_undo_marker (void)
4655 return undobuf
.undos
;
4658 /* Undo the modifications up to the marker. */
4661 undo_to_marker (void *marker
)
4663 struct undo
*undo
, *next
;
4665 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4673 *undo
->where
.r
= undo
->old_contents
.r
;
4676 *undo
->where
.i
= undo
->old_contents
.i
;
4679 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4682 *undo
->where
.l
= undo
->old_contents
.l
;
4688 undo
->next
= undobuf
.frees
;
4689 undobuf
.frees
= undo
;
4692 undobuf
.undos
= (struct undo
*) marker
;
4695 /* Undo all the modifications recorded in undobuf. */
4703 /* We've committed to accepting the changes we made. Move all
4704 of the undos to the free list. */
4709 struct undo
*undo
, *next
;
4711 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4714 undo
->next
= undobuf
.frees
;
4715 undobuf
.frees
= undo
;
4720 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4721 where we have an arithmetic expression and return that point. LOC will
4724 try_combine will call this function to see if an insn can be split into
4728 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4731 enum rtx_code code
= GET_CODE (x
);
4733 unsigned HOST_WIDE_INT len
= 0;
4734 HOST_WIDE_INT pos
= 0;
4736 rtx inner
= NULL_RTX
;
4738 /* First special-case some codes. */
4742 #ifdef INSN_SCHEDULING
4743 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4745 if (MEM_P (SUBREG_REG (x
)))
4748 return find_split_point (&SUBREG_REG (x
), insn
, false);
4751 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4752 using LO_SUM and HIGH. */
4753 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4754 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4756 machine_mode address_mode
= get_address_mode (x
);
4759 gen_rtx_LO_SUM (address_mode
,
4760 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4762 return &XEXP (XEXP (x
, 0), 0);
4765 /* If we have a PLUS whose second operand is a constant and the
4766 address is not valid, perhaps will can split it up using
4767 the machine-specific way to split large constants. We use
4768 the first pseudo-reg (one of the virtual regs) as a placeholder;
4769 it will not remain in the result. */
4770 if (GET_CODE (XEXP (x
, 0)) == PLUS
4771 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4772 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4773 MEM_ADDR_SPACE (x
)))
4775 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4776 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4779 /* This should have produced two insns, each of which sets our
4780 placeholder. If the source of the second is a valid address,
4781 we can make put both sources together and make a split point
4785 && NEXT_INSN (seq
) != NULL_RTX
4786 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4787 && NONJUMP_INSN_P (seq
)
4788 && GET_CODE (PATTERN (seq
)) == SET
4789 && SET_DEST (PATTERN (seq
)) == reg
4790 && ! reg_mentioned_p (reg
,
4791 SET_SRC (PATTERN (seq
)))
4792 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4793 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4794 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4795 && memory_address_addr_space_p
4796 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4797 MEM_ADDR_SPACE (x
)))
4799 rtx src1
= SET_SRC (PATTERN (seq
));
4800 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4802 /* Replace the placeholder in SRC2 with SRC1. If we can
4803 find where in SRC2 it was placed, that can become our
4804 split point and we can replace this address with SRC2.
4805 Just try two obvious places. */
4807 src2
= replace_rtx (src2
, reg
, src1
);
4809 if (XEXP (src2
, 0) == src1
)
4810 split
= &XEXP (src2
, 0);
4811 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4812 && XEXP (XEXP (src2
, 0), 0) == src1
)
4813 split
= &XEXP (XEXP (src2
, 0), 0);
4817 SUBST (XEXP (x
, 0), src2
);
4822 /* If that didn't work, perhaps the first operand is complex and
4823 needs to be computed separately, so make a split point there.
4824 This will occur on machines that just support REG + CONST
4825 and have a constant moved through some previous computation. */
4827 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4828 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4829 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4830 return &XEXP (XEXP (x
, 0), 0);
4833 /* If we have a PLUS whose first operand is complex, try computing it
4834 separately by making a split there. */
4835 if (GET_CODE (XEXP (x
, 0)) == PLUS
4836 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4838 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4839 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4840 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4841 return &XEXP (XEXP (x
, 0), 0);
4845 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4846 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4847 we need to put the operand into a register. So split at that
4850 if (SET_DEST (x
) == cc0_rtx
4851 && GET_CODE (SET_SRC (x
)) != COMPARE
4852 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4853 && !OBJECT_P (SET_SRC (x
))
4854 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4855 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4856 return &SET_SRC (x
);
4858 /* See if we can split SET_SRC as it stands. */
4859 split
= find_split_point (&SET_SRC (x
), insn
, true);
4860 if (split
&& split
!= &SET_SRC (x
))
4863 /* See if we can split SET_DEST as it stands. */
4864 split
= find_split_point (&SET_DEST (x
), insn
, false);
4865 if (split
&& split
!= &SET_DEST (x
))
4868 /* See if this is a bitfield assignment with everything constant. If
4869 so, this is an IOR of an AND, so split it into that. */
4870 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4871 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4872 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4873 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4874 && CONST_INT_P (SET_SRC (x
))
4875 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4876 + INTVAL (XEXP (SET_DEST (x
), 2)))
4877 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4878 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4880 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4881 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4882 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4883 rtx dest
= XEXP (SET_DEST (x
), 0);
4884 machine_mode mode
= GET_MODE (dest
);
4885 unsigned HOST_WIDE_INT mask
4886 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4889 if (BITS_BIG_ENDIAN
)
4890 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4892 or_mask
= gen_int_mode (src
<< pos
, mode
);
4895 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4898 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4900 simplify_gen_binary (IOR
, mode
,
4901 simplify_gen_binary (AND
, mode
,
4906 SUBST (SET_DEST (x
), dest
);
4908 split
= find_split_point (&SET_SRC (x
), insn
, true);
4909 if (split
&& split
!= &SET_SRC (x
))
4913 /* Otherwise, see if this is an operation that we can split into two.
4914 If so, try to split that. */
4915 code
= GET_CODE (SET_SRC (x
));
4920 /* If we are AND'ing with a large constant that is only a single
4921 bit and the result is only being used in a context where we
4922 need to know if it is zero or nonzero, replace it with a bit
4923 extraction. This will avoid the large constant, which might
4924 have taken more than one insn to make. If the constant were
4925 not a valid argument to the AND but took only one insn to make,
4926 this is no worse, but if it took more than one insn, it will
4929 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4930 && REG_P (XEXP (SET_SRC (x
), 0))
4931 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4932 && REG_P (SET_DEST (x
))
4933 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4934 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4935 && XEXP (*split
, 0) == SET_DEST (x
)
4936 && XEXP (*split
, 1) == const0_rtx
)
4938 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4939 XEXP (SET_SRC (x
), 0),
4940 pos
, NULL_RTX
, 1, 1, 0, 0);
4941 if (extraction
!= 0)
4943 SUBST (SET_SRC (x
), extraction
);
4944 return find_split_point (loc
, insn
, false);
4950 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4951 is known to be on, this can be converted into a NEG of a shift. */
4952 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4953 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4954 && 1 <= (pos
= exact_log2
4955 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4956 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4958 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4962 gen_rtx_LSHIFTRT (mode
,
4963 XEXP (SET_SRC (x
), 0),
4966 split
= find_split_point (&SET_SRC (x
), insn
, true);
4967 if (split
&& split
!= &SET_SRC (x
))
4973 inner
= XEXP (SET_SRC (x
), 0);
4975 /* We can't optimize if either mode is a partial integer
4976 mode as we don't know how many bits are significant
4978 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4979 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4983 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4989 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4990 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4992 inner
= XEXP (SET_SRC (x
), 0);
4993 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4994 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4996 if (BITS_BIG_ENDIAN
)
4997 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4998 unsignedp
= (code
== ZERO_EXTRACT
);
5007 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5009 machine_mode mode
= GET_MODE (SET_SRC (x
));
5011 /* For unsigned, we have a choice of a shift followed by an
5012 AND or two shifts. Use two shifts for field sizes where the
5013 constant might be too large. We assume here that we can
5014 always at least get 8-bit constants in an AND insn, which is
5015 true for every current RISC. */
5017 if (unsignedp
&& len
<= 8)
5019 unsigned HOST_WIDE_INT mask
5020 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
5024 (mode
, gen_lowpart (mode
, inner
),
5026 gen_int_mode (mask
, mode
)));
5028 split
= find_split_point (&SET_SRC (x
), insn
, true);
5029 if (split
&& split
!= &SET_SRC (x
))
5036 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5037 gen_rtx_ASHIFT (mode
,
5038 gen_lowpart (mode
, inner
),
5039 GEN_INT (GET_MODE_PRECISION (mode
)
5041 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5043 split
= find_split_point (&SET_SRC (x
), insn
, true);
5044 if (split
&& split
!= &SET_SRC (x
))
5049 /* See if this is a simple operation with a constant as the second
5050 operand. It might be that this constant is out of range and hence
5051 could be used as a split point. */
5052 if (BINARY_P (SET_SRC (x
))
5053 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5054 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5055 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5056 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5057 return &XEXP (SET_SRC (x
), 1);
5059 /* Finally, see if this is a simple operation with its first operand
5060 not in a register. The operation might require this operand in a
5061 register, so return it as a split point. We can always do this
5062 because if the first operand were another operation, we would have
5063 already found it as a split point. */
5064 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5065 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5066 return &XEXP (SET_SRC (x
), 0);
5072 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5073 it is better to write this as (not (ior A B)) so we can split it.
5074 Similarly for IOR. */
5075 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5078 gen_rtx_NOT (GET_MODE (x
),
5079 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5081 XEXP (XEXP (x
, 0), 0),
5082 XEXP (XEXP (x
, 1), 0))));
5083 return find_split_point (loc
, insn
, set_src
);
5086 /* Many RISC machines have a large set of logical insns. If the
5087 second operand is a NOT, put it first so we will try to split the
5088 other operand first. */
5089 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5091 rtx tem
= XEXP (x
, 0);
5092 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5093 SUBST (XEXP (x
, 1), tem
);
5099 /* Canonicalization can produce (minus A (mult B C)), where C is a
5100 constant. It may be better to try splitting (plus (mult B -C) A)
5101 instead if this isn't a multiply by a power of two. */
5102 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5103 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5104 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
5106 machine_mode mode
= GET_MODE (x
);
5107 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5108 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5109 SUBST (*loc
, gen_rtx_PLUS (mode
,
5111 XEXP (XEXP (x
, 1), 0),
5112 gen_int_mode (other_int
,
5115 return find_split_point (loc
, insn
, set_src
);
5118 /* Split at a multiply-accumulate instruction. However if this is
5119 the SET_SRC, we likely do not have such an instruction and it's
5120 worthless to try this split. */
5122 && (GET_CODE (XEXP (x
, 0)) == MULT
5123 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5124 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5131 /* Otherwise, select our actions depending on our rtx class. */
5132 switch (GET_RTX_CLASS (code
))
5134 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5136 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5139 /* ... fall through ... */
5141 case RTX_COMM_ARITH
:
5143 case RTX_COMM_COMPARE
:
5144 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5147 /* ... fall through ... */
5149 /* Some machines have (and (shift ...) ...) insns. If X is not
5150 an AND, but XEXP (X, 0) is, use it as our split point. */
5151 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5152 return &XEXP (x
, 0);
5154 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5160 /* Otherwise, we don't have a split point. */
5165 /* Throughout X, replace FROM with TO, and return the result.
5166 The result is TO if X is FROM;
5167 otherwise the result is X, but its contents may have been modified.
5168 If they were modified, a record was made in undobuf so that
5169 undo_all will (among other things) return X to its original state.
5171 If the number of changes necessary is too much to record to undo,
5172 the excess changes are not made, so the result is invalid.
5173 The changes already made can still be undone.
5174 undobuf.num_undo is incremented for such changes, so by testing that
5175 the caller can tell whether the result is valid.
5177 `n_occurrences' is incremented each time FROM is replaced.
5179 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5181 IN_COND is nonzero if we are at the top level of a condition.
5183 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5184 by copying if `n_occurrences' is nonzero. */
5187 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5189 enum rtx_code code
= GET_CODE (x
);
5190 machine_mode op0_mode
= VOIDmode
;
5195 /* Two expressions are equal if they are identical copies of a shared
5196 RTX or if they are both registers with the same register number
5199 #define COMBINE_RTX_EQUAL_P(X,Y) \
5201 || (REG_P (X) && REG_P (Y) \
5202 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5204 /* Do not substitute into clobbers of regs -- this will never result in
5206 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5209 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5212 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5215 /* If X and FROM are the same register but different modes, they
5216 will not have been seen as equal above. However, the log links code
5217 will make a LOG_LINKS entry for that case. If we do nothing, we
5218 will try to rerecognize our original insn and, when it succeeds,
5219 we will delete the feeding insn, which is incorrect.
5221 So force this insn not to match in this (rare) case. */
5222 if (! in_dest
&& code
== REG
&& REG_P (from
)
5223 && reg_overlap_mentioned_p (x
, from
))
5224 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5226 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5227 of which may contain things that can be combined. */
5228 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5231 /* It is possible to have a subexpression appear twice in the insn.
5232 Suppose that FROM is a register that appears within TO.
5233 Then, after that subexpression has been scanned once by `subst',
5234 the second time it is scanned, TO may be found. If we were
5235 to scan TO here, we would find FROM within it and create a
5236 self-referent rtl structure which is completely wrong. */
5237 if (COMBINE_RTX_EQUAL_P (x
, to
))
5240 /* Parallel asm_operands need special attention because all of the
5241 inputs are shared across the arms. Furthermore, unsharing the
5242 rtl results in recognition failures. Failure to handle this case
5243 specially can result in circular rtl.
5245 Solve this by doing a normal pass across the first entry of the
5246 parallel, and only processing the SET_DESTs of the subsequent
5249 if (code
== PARALLEL
5250 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5251 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5253 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5255 /* If this substitution failed, this whole thing fails. */
5256 if (GET_CODE (new_rtx
) == CLOBBER
5257 && XEXP (new_rtx
, 0) == const0_rtx
)
5260 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5262 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5264 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5267 && GET_CODE (dest
) != CC0
5268 && GET_CODE (dest
) != PC
)
5270 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5272 /* If this substitution failed, this whole thing fails. */
5273 if (GET_CODE (new_rtx
) == CLOBBER
5274 && XEXP (new_rtx
, 0) == const0_rtx
)
5277 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5283 len
= GET_RTX_LENGTH (code
);
5284 fmt
= GET_RTX_FORMAT (code
);
5286 /* We don't need to process a SET_DEST that is a register, CC0,
5287 or PC, so set up to skip this common case. All other cases
5288 where we want to suppress replacing something inside a
5289 SET_SRC are handled via the IN_DEST operand. */
5291 && (REG_P (SET_DEST (x
))
5292 || GET_CODE (SET_DEST (x
)) == CC0
5293 || GET_CODE (SET_DEST (x
)) == PC
))
5296 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5299 op0_mode
= GET_MODE (XEXP (x
, 0));
5301 for (i
= 0; i
< len
; i
++)
5306 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5308 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5310 new_rtx
= (unique_copy
&& n_occurrences
5311 ? copy_rtx (to
) : to
);
5316 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5319 /* If this substitution failed, this whole thing
5321 if (GET_CODE (new_rtx
) == CLOBBER
5322 && XEXP (new_rtx
, 0) == const0_rtx
)
5326 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5329 else if (fmt
[i
] == 'e')
5331 /* If this is a register being set, ignore it. */
5332 new_rtx
= XEXP (x
, i
);
5335 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5337 || code
== STRICT_LOW_PART
))
5340 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5342 /* In general, don't install a subreg involving two
5343 modes not tieable. It can worsen register
5344 allocation, and can even make invalid reload
5345 insns, since the reg inside may need to be copied
5346 from in the outside mode, and that may be invalid
5347 if it is an fp reg copied in integer mode.
5349 We allow two exceptions to this: It is valid if
5350 it is inside another SUBREG and the mode of that
5351 SUBREG and the mode of the inside of TO is
5352 tieable and it is valid if X is a SET that copies
5355 if (GET_CODE (to
) == SUBREG
5356 && ! MODES_TIEABLE_P (GET_MODE (to
),
5357 GET_MODE (SUBREG_REG (to
)))
5358 && ! (code
== SUBREG
5359 && MODES_TIEABLE_P (GET_MODE (x
),
5360 GET_MODE (SUBREG_REG (to
))))
5364 && XEXP (x
, 0) == cc0_rtx
))))
5365 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5369 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5370 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5373 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5375 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5379 /* If we are in a SET_DEST, suppress most cases unless we
5380 have gone inside a MEM, in which case we want to
5381 simplify the address. We assume here that things that
5382 are actually part of the destination have their inner
5383 parts in the first expression. This is true for SUBREG,
5384 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5385 things aside from REG and MEM that should appear in a
5387 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5389 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5390 || code
== ZERO_EXTRACT
))
5393 code
== IF_THEN_ELSE
&& i
== 0,
5396 /* If we found that we will have to reject this combination,
5397 indicate that by returning the CLOBBER ourselves, rather than
5398 an expression containing it. This will speed things up as
5399 well as prevent accidents where two CLOBBERs are considered
5400 to be equal, thus producing an incorrect simplification. */
5402 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5405 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5407 machine_mode mode
= GET_MODE (x
);
5409 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5410 GET_MODE (SUBREG_REG (x
)),
5413 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5415 else if (CONST_SCALAR_INT_P (new_rtx
)
5416 && GET_CODE (x
) == ZERO_EXTEND
)
5418 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5419 new_rtx
, GET_MODE (XEXP (x
, 0)));
5423 SUBST (XEXP (x
, i
), new_rtx
);
5428 /* Check if we are loading something from the constant pool via float
5429 extension; in this case we would undo compress_float_constant
5430 optimization and degenerate constant load to an immediate value. */
5431 if (GET_CODE (x
) == FLOAT_EXTEND
5432 && MEM_P (XEXP (x
, 0))
5433 && MEM_READONLY_P (XEXP (x
, 0)))
5435 rtx tmp
= avoid_constant_pool_reference (x
);
5440 /* Try to simplify X. If the simplification changed the code, it is likely
5441 that further simplification will help, so loop, but limit the number
5442 of repetitions that will be performed. */
5444 for (i
= 0; i
< 4; i
++)
5446 /* If X is sufficiently simple, don't bother trying to do anything
5448 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5449 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5451 if (GET_CODE (x
) == code
)
5454 code
= GET_CODE (x
);
5456 /* We no longer know the original mode of operand 0 since we
5457 have changed the form of X) */
5458 op0_mode
= VOIDmode
;
5464 /* Simplify X, a piece of RTL. We just operate on the expression at the
5465 outer level; call `subst' to simplify recursively. Return the new
5468 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5469 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5473 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5476 enum rtx_code code
= GET_CODE (x
);
5477 machine_mode mode
= GET_MODE (x
);
5481 /* If this is a commutative operation, put a constant last and a complex
5482 expression first. We don't need to do this for comparisons here. */
5483 if (COMMUTATIVE_ARITH_P (x
)
5484 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5487 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5488 SUBST (XEXP (x
, 1), temp
);
5491 /* Try to fold this expression in case we have constants that weren't
5494 switch (GET_RTX_CLASS (code
))
5497 if (op0_mode
== VOIDmode
)
5498 op0_mode
= GET_MODE (XEXP (x
, 0));
5499 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5502 case RTX_COMM_COMPARE
:
5504 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5505 if (cmp_mode
== VOIDmode
)
5507 cmp_mode
= GET_MODE (XEXP (x
, 1));
5508 if (cmp_mode
== VOIDmode
)
5509 cmp_mode
= op0_mode
;
5511 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5512 XEXP (x
, 0), XEXP (x
, 1));
5515 case RTX_COMM_ARITH
:
5517 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5519 case RTX_BITFIELD_OPS
:
5521 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5522 XEXP (x
, 1), XEXP (x
, 2));
5531 code
= GET_CODE (temp
);
5532 op0_mode
= VOIDmode
;
5533 mode
= GET_MODE (temp
);
5536 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5537 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5538 things. Check for cases where both arms are testing the same
5541 Don't do anything if all operands are very simple. */
5544 && ((!OBJECT_P (XEXP (x
, 0))
5545 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5546 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5547 || (!OBJECT_P (XEXP (x
, 1))
5548 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5549 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5551 && (!OBJECT_P (XEXP (x
, 0))
5552 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5553 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5555 rtx cond
, true_rtx
, false_rtx
;
5557 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5559 /* If everything is a comparison, what we have is highly unlikely
5560 to be simpler, so don't use it. */
5561 && ! (COMPARISON_P (x
)
5562 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5564 rtx cop1
= const0_rtx
;
5565 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5567 if (cond_code
== NE
&& COMPARISON_P (cond
))
5570 /* Simplify the alternative arms; this may collapse the true and
5571 false arms to store-flag values. Be careful to use copy_rtx
5572 here since true_rtx or false_rtx might share RTL with x as a
5573 result of the if_then_else_cond call above. */
5574 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5575 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5577 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5578 is unlikely to be simpler. */
5579 if (general_operand (true_rtx
, VOIDmode
)
5580 && general_operand (false_rtx
, VOIDmode
))
5582 enum rtx_code reversed
;
5584 /* Restarting if we generate a store-flag expression will cause
5585 us to loop. Just drop through in this case. */
5587 /* If the result values are STORE_FLAG_VALUE and zero, we can
5588 just make the comparison operation. */
5589 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5590 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5592 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5593 && ((reversed
= reversed_comparison_code_parts
5594 (cond_code
, cond
, cop1
, NULL
))
5596 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5599 /* Likewise, we can make the negate of a comparison operation
5600 if the result values are - STORE_FLAG_VALUE and zero. */
5601 else if (CONST_INT_P (true_rtx
)
5602 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5603 && false_rtx
== const0_rtx
)
5604 x
= simplify_gen_unary (NEG
, mode
,
5605 simplify_gen_relational (cond_code
,
5609 else if (CONST_INT_P (false_rtx
)
5610 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5611 && true_rtx
== const0_rtx
5612 && ((reversed
= reversed_comparison_code_parts
5613 (cond_code
, cond
, cop1
, NULL
))
5615 x
= simplify_gen_unary (NEG
, mode
,
5616 simplify_gen_relational (reversed
,
5621 return gen_rtx_IF_THEN_ELSE (mode
,
5622 simplify_gen_relational (cond_code
,
5627 true_rtx
, false_rtx
);
5629 code
= GET_CODE (x
);
5630 op0_mode
= VOIDmode
;
5635 /* First see if we can apply the inverse distributive law. */
5636 if (code
== PLUS
|| code
== MINUS
5637 || code
== AND
|| code
== IOR
|| code
== XOR
)
5639 x
= apply_distributive_law (x
);
5640 code
= GET_CODE (x
);
5641 op0_mode
= VOIDmode
;
5644 /* If CODE is an associative operation not otherwise handled, see if we
5645 can associate some operands. This can win if they are constants or
5646 if they are logically related (i.e. (a & b) & a). */
5647 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5648 || code
== AND
|| code
== IOR
|| code
== XOR
5649 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5650 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5651 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5653 if (GET_CODE (XEXP (x
, 0)) == code
)
5655 rtx other
= XEXP (XEXP (x
, 0), 0);
5656 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5657 rtx inner_op1
= XEXP (x
, 1);
5660 /* Make sure we pass the constant operand if any as the second
5661 one if this is a commutative operation. */
5662 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5663 std::swap (inner_op0
, inner_op1
);
5664 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5665 : code
== DIV
? MULT
5667 mode
, inner_op0
, inner_op1
);
5669 /* For commutative operations, try the other pair if that one
5671 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5673 other
= XEXP (XEXP (x
, 0), 1);
5674 inner
= simplify_binary_operation (code
, mode
,
5675 XEXP (XEXP (x
, 0), 0),
5680 return simplify_gen_binary (code
, mode
, other
, inner
);
5684 /* A little bit of algebraic simplification here. */
5688 /* Ensure that our address has any ASHIFTs converted to MULT in case
5689 address-recognizing predicates are called later. */
5690 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5691 SUBST (XEXP (x
, 0), temp
);
5695 if (op0_mode
== VOIDmode
)
5696 op0_mode
= GET_MODE (SUBREG_REG (x
));
5698 /* See if this can be moved to simplify_subreg. */
5699 if (CONSTANT_P (SUBREG_REG (x
))
5700 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5701 /* Don't call gen_lowpart if the inner mode
5702 is VOIDmode and we cannot simplify it, as SUBREG without
5703 inner mode is invalid. */
5704 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5705 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5706 return gen_lowpart (mode
, SUBREG_REG (x
));
5708 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5712 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5717 /* If op is known to have all lower bits zero, the result is zero. */
5719 && SCALAR_INT_MODE_P (mode
)
5720 && SCALAR_INT_MODE_P (op0_mode
)
5721 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5722 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5723 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5724 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5725 & GET_MODE_MASK (mode
)) == 0)
5726 return CONST0_RTX (mode
);
5729 /* Don't change the mode of the MEM if that would change the meaning
5731 if (MEM_P (SUBREG_REG (x
))
5732 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5733 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5734 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5735 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5737 /* Note that we cannot do any narrowing for non-constants since
5738 we might have been counting on using the fact that some bits were
5739 zero. We now do this in the SET. */
5744 temp
= expand_compound_operation (XEXP (x
, 0));
5746 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5747 replaced by (lshiftrt X C). This will convert
5748 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5750 if (GET_CODE (temp
) == ASHIFTRT
5751 && CONST_INT_P (XEXP (temp
, 1))
5752 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5753 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5754 INTVAL (XEXP (temp
, 1)));
5756 /* If X has only a single bit that might be nonzero, say, bit I, convert
5757 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5758 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5759 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5760 or a SUBREG of one since we'd be making the expression more
5761 complex if it was just a register. */
5764 && ! (GET_CODE (temp
) == SUBREG
5765 && REG_P (SUBREG_REG (temp
)))
5766 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5768 rtx temp1
= simplify_shift_const
5769 (NULL_RTX
, ASHIFTRT
, mode
,
5770 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5771 GET_MODE_PRECISION (mode
) - 1 - i
),
5772 GET_MODE_PRECISION (mode
) - 1 - i
);
5774 /* If all we did was surround TEMP with the two shifts, we
5775 haven't improved anything, so don't use it. Otherwise,
5776 we are better off with TEMP1. */
5777 if (GET_CODE (temp1
) != ASHIFTRT
5778 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5779 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5785 /* We can't handle truncation to a partial integer mode here
5786 because we don't know the real bitsize of the partial
5788 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5791 if (HWI_COMPUTABLE_MODE_P (mode
))
5793 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5794 GET_MODE_MASK (mode
), 0));
5796 /* We can truncate a constant value and return it. */
5797 if (CONST_INT_P (XEXP (x
, 0)))
5798 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5800 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5801 whose value is a comparison can be replaced with a subreg if
5802 STORE_FLAG_VALUE permits. */
5803 if (HWI_COMPUTABLE_MODE_P (mode
)
5804 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5805 && (temp
= get_last_value (XEXP (x
, 0)))
5806 && COMPARISON_P (temp
))
5807 return gen_lowpart (mode
, XEXP (x
, 0));
5811 /* (const (const X)) can become (const X). Do it this way rather than
5812 returning the inner CONST since CONST can be shared with a
5814 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5815 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5819 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5820 can add in an offset. find_split_point will split this address up
5821 again if it doesn't match. */
5822 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5823 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5828 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5829 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5830 bit-field and can be replaced by either a sign_extend or a
5831 sign_extract. The `and' may be a zero_extend and the two
5832 <c>, -<c> constants may be reversed. */
5833 if (GET_CODE (XEXP (x
, 0)) == XOR
5834 && CONST_INT_P (XEXP (x
, 1))
5835 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5836 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5837 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5838 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5839 && HWI_COMPUTABLE_MODE_P (mode
)
5840 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5841 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5842 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5843 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5844 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5845 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5846 == (unsigned int) i
+ 1))))
5847 return simplify_shift_const
5848 (NULL_RTX
, ASHIFTRT
, mode
,
5849 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5850 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5851 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5852 GET_MODE_PRECISION (mode
) - (i
+ 1));
5854 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5855 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5856 the bitsize of the mode - 1. This allows simplification of
5857 "a = (b & 8) == 0;" */
5858 if (XEXP (x
, 1) == constm1_rtx
5859 && !REG_P (XEXP (x
, 0))
5860 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5861 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5862 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5863 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5864 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5865 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5866 GET_MODE_PRECISION (mode
) - 1),
5867 GET_MODE_PRECISION (mode
) - 1);
5869 /* If we are adding two things that have no bits in common, convert
5870 the addition into an IOR. This will often be further simplified,
5871 for example in cases like ((a & 1) + (a & 2)), which can
5874 if (HWI_COMPUTABLE_MODE_P (mode
)
5875 && (nonzero_bits (XEXP (x
, 0), mode
)
5876 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5878 /* Try to simplify the expression further. */
5879 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5880 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5882 /* If we could, great. If not, do not go ahead with the IOR
5883 replacement, since PLUS appears in many special purpose
5884 address arithmetic instructions. */
5885 if (GET_CODE (temp
) != CLOBBER
5886 && (GET_CODE (temp
) != IOR
5887 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5888 || XEXP (temp
, 1) != XEXP (x
, 1))
5889 && (XEXP (temp
, 0) != XEXP (x
, 1)
5890 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5896 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5897 (and <foo> (const_int pow2-1)) */
5898 if (GET_CODE (XEXP (x
, 1)) == AND
5899 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5900 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5901 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5902 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5903 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5907 /* If we have (mult (plus A B) C), apply the distributive law and then
5908 the inverse distributive law to see if things simplify. This
5909 occurs mostly in addresses, often when unrolling loops. */
5911 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5913 rtx result
= distribute_and_simplify_rtx (x
, 0);
5918 /* Try simplify a*(b/c) as (a*b)/c. */
5919 if (FLOAT_MODE_P (mode
) && flag_associative_math
5920 && GET_CODE (XEXP (x
, 0)) == DIV
)
5922 rtx tem
= simplify_binary_operation (MULT
, mode
,
5923 XEXP (XEXP (x
, 0), 0),
5926 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5931 /* If this is a divide by a power of two, treat it as a shift if
5932 its first operand is a shift. */
5933 if (CONST_INT_P (XEXP (x
, 1))
5934 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5935 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5936 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5937 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5938 || GET_CODE (XEXP (x
, 0)) == ROTATE
5939 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5940 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5944 case GT
: case GTU
: case GE
: case GEU
:
5945 case LT
: case LTU
: case LE
: case LEU
:
5946 case UNEQ
: case LTGT
:
5947 case UNGT
: case UNGE
:
5948 case UNLT
: case UNLE
:
5949 case UNORDERED
: case ORDERED
:
5950 /* If the first operand is a condition code, we can't do anything
5952 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5953 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5954 && ! CC0_P (XEXP (x
, 0))))
5956 rtx op0
= XEXP (x
, 0);
5957 rtx op1
= XEXP (x
, 1);
5958 enum rtx_code new_code
;
5960 if (GET_CODE (op0
) == COMPARE
)
5961 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5963 /* Simplify our comparison, if possible. */
5964 new_code
= simplify_comparison (code
, &op0
, &op1
);
5966 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5967 if only the low-order bit is possibly nonzero in X (such as when
5968 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5969 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5970 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5973 Remove any ZERO_EXTRACT we made when thinking this was a
5974 comparison. It may now be simpler to use, e.g., an AND. If a
5975 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5976 the call to make_compound_operation in the SET case.
5978 Don't apply these optimizations if the caller would
5979 prefer a comparison rather than a value.
5980 E.g., for the condition in an IF_THEN_ELSE most targets need
5981 an explicit comparison. */
5986 else if (STORE_FLAG_VALUE
== 1
5987 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5988 && op1
== const0_rtx
5989 && mode
== GET_MODE (op0
)
5990 && nonzero_bits (op0
, mode
) == 1)
5991 return gen_lowpart (mode
,
5992 expand_compound_operation (op0
));
5994 else if (STORE_FLAG_VALUE
== 1
5995 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5996 && op1
== const0_rtx
5997 && mode
== GET_MODE (op0
)
5998 && (num_sign_bit_copies (op0
, mode
)
5999 == GET_MODE_PRECISION (mode
)))
6001 op0
= expand_compound_operation (op0
);
6002 return simplify_gen_unary (NEG
, mode
,
6003 gen_lowpart (mode
, op0
),
6007 else if (STORE_FLAG_VALUE
== 1
6008 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6009 && op1
== const0_rtx
6010 && mode
== GET_MODE (op0
)
6011 && nonzero_bits (op0
, mode
) == 1)
6013 op0
= expand_compound_operation (op0
);
6014 return simplify_gen_binary (XOR
, mode
,
6015 gen_lowpart (mode
, op0
),
6019 else if (STORE_FLAG_VALUE
== 1
6020 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6021 && op1
== const0_rtx
6022 && mode
== GET_MODE (op0
)
6023 && (num_sign_bit_copies (op0
, mode
)
6024 == GET_MODE_PRECISION (mode
)))
6026 op0
= expand_compound_operation (op0
);
6027 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6030 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6035 else if (STORE_FLAG_VALUE
== -1
6036 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6037 && op1
== const0_rtx
6038 && mode
== GET_MODE (op0
)
6039 && (num_sign_bit_copies (op0
, mode
)
6040 == GET_MODE_PRECISION (mode
)))
6041 return gen_lowpart (mode
,
6042 expand_compound_operation (op0
));
6044 else if (STORE_FLAG_VALUE
== -1
6045 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6046 && op1
== const0_rtx
6047 && mode
== GET_MODE (op0
)
6048 && nonzero_bits (op0
, mode
) == 1)
6050 op0
= expand_compound_operation (op0
);
6051 return simplify_gen_unary (NEG
, mode
,
6052 gen_lowpart (mode
, op0
),
6056 else if (STORE_FLAG_VALUE
== -1
6057 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6058 && op1
== const0_rtx
6059 && mode
== GET_MODE (op0
)
6060 && (num_sign_bit_copies (op0
, mode
)
6061 == GET_MODE_PRECISION (mode
)))
6063 op0
= expand_compound_operation (op0
);
6064 return simplify_gen_unary (NOT
, mode
,
6065 gen_lowpart (mode
, op0
),
6069 /* If X is 0/1, (eq X 0) is X-1. */
6070 else if (STORE_FLAG_VALUE
== -1
6071 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6072 && op1
== const0_rtx
6073 && mode
== GET_MODE (op0
)
6074 && nonzero_bits (op0
, mode
) == 1)
6076 op0
= expand_compound_operation (op0
);
6077 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6080 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6081 one bit that might be nonzero, we can convert (ne x 0) to
6082 (ashift x c) where C puts the bit in the sign bit. Remove any
6083 AND with STORE_FLAG_VALUE when we are done, since we are only
6084 going to test the sign bit. */
6085 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6086 && HWI_COMPUTABLE_MODE_P (mode
)
6087 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6088 && op1
== const0_rtx
6089 && mode
== GET_MODE (op0
)
6090 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6092 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6093 expand_compound_operation (op0
),
6094 GET_MODE_PRECISION (mode
) - 1 - i
);
6095 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6101 /* If the code changed, return a whole new comparison.
6102 We also need to avoid using SUBST in cases where
6103 simplify_comparison has widened a comparison with a CONST_INT,
6104 since in that case the wider CONST_INT may fail the sanity
6105 checks in do_SUBST. */
6106 if (new_code
!= code
6107 || (CONST_INT_P (op1
)
6108 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6109 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6110 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6112 /* Otherwise, keep this operation, but maybe change its operands.
6113 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6114 SUBST (XEXP (x
, 0), op0
);
6115 SUBST (XEXP (x
, 1), op1
);
6120 return simplify_if_then_else (x
);
6126 /* If we are processing SET_DEST, we are done. */
6130 return expand_compound_operation (x
);
6133 return simplify_set (x
);
6137 return simplify_logical (x
);
6144 /* If this is a shift by a constant amount, simplify it. */
6145 if (CONST_INT_P (XEXP (x
, 1)))
6146 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6147 INTVAL (XEXP (x
, 1)));
6149 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6151 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6152 ((unsigned HOST_WIDE_INT
) 1
6153 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6165 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6168 simplify_if_then_else (rtx x
)
6170 machine_mode mode
= GET_MODE (x
);
6171 rtx cond
= XEXP (x
, 0);
6172 rtx true_rtx
= XEXP (x
, 1);
6173 rtx false_rtx
= XEXP (x
, 2);
6174 enum rtx_code true_code
= GET_CODE (cond
);
6175 int comparison_p
= COMPARISON_P (cond
);
6178 enum rtx_code false_code
;
6181 /* Simplify storing of the truth value. */
6182 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6183 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6184 XEXP (cond
, 0), XEXP (cond
, 1));
6186 /* Also when the truth value has to be reversed. */
6188 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6189 && (reversed
= reversed_comparison (cond
, mode
)))
6192 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6193 in it is being compared against certain values. Get the true and false
6194 comparisons and see if that says anything about the value of each arm. */
6197 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6199 && REG_P (XEXP (cond
, 0)))
6202 rtx from
= XEXP (cond
, 0);
6203 rtx true_val
= XEXP (cond
, 1);
6204 rtx false_val
= true_val
;
6207 /* If FALSE_CODE is EQ, swap the codes and arms. */
6209 if (false_code
== EQ
)
6211 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6212 std::swap (true_rtx
, false_rtx
);
6215 /* If we are comparing against zero and the expression being tested has
6216 only a single bit that might be nonzero, that is its value when it is
6217 not equal to zero. Similarly if it is known to be -1 or 0. */
6219 if (true_code
== EQ
&& true_val
== const0_rtx
6220 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
6223 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6225 else if (true_code
== EQ
&& true_val
== const0_rtx
6226 && (num_sign_bit_copies (from
, GET_MODE (from
))
6227 == GET_MODE_PRECISION (GET_MODE (from
))))
6230 false_val
= constm1_rtx
;
6233 /* Now simplify an arm if we know the value of the register in the
6234 branch and it is used in the arm. Be careful due to the potential
6235 of locally-shared RTL. */
6237 if (reg_mentioned_p (from
, true_rtx
))
6238 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6240 pc_rtx
, pc_rtx
, 0, 0, 0);
6241 if (reg_mentioned_p (from
, false_rtx
))
6242 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6244 pc_rtx
, pc_rtx
, 0, 0, 0);
6246 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6247 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6249 true_rtx
= XEXP (x
, 1);
6250 false_rtx
= XEXP (x
, 2);
6251 true_code
= GET_CODE (cond
);
6254 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6255 reversed, do so to avoid needing two sets of patterns for
6256 subtract-and-branch insns. Similarly if we have a constant in the true
6257 arm, the false arm is the same as the first operand of the comparison, or
6258 the false arm is more complicated than the true arm. */
6261 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6262 && (true_rtx
== pc_rtx
6263 || (CONSTANT_P (true_rtx
)
6264 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6265 || true_rtx
== const0_rtx
6266 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6267 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6268 && !OBJECT_P (false_rtx
))
6269 || reg_mentioned_p (true_rtx
, false_rtx
)
6270 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6272 true_code
= reversed_comparison_code (cond
, NULL
);
6273 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6274 SUBST (XEXP (x
, 1), false_rtx
);
6275 SUBST (XEXP (x
, 2), true_rtx
);
6277 std::swap (true_rtx
, false_rtx
);
6280 /* It is possible that the conditional has been simplified out. */
6281 true_code
= GET_CODE (cond
);
6282 comparison_p
= COMPARISON_P (cond
);
6285 /* If the two arms are identical, we don't need the comparison. */
6287 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6290 /* Convert a == b ? b : a to "a". */
6291 if (true_code
== EQ
&& ! side_effects_p (cond
)
6292 && !HONOR_NANS (mode
)
6293 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6294 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6296 else if (true_code
== NE
&& ! side_effects_p (cond
)
6297 && !HONOR_NANS (mode
)
6298 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6299 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6302 /* Look for cases where we have (abs x) or (neg (abs X)). */
6304 if (GET_MODE_CLASS (mode
) == MODE_INT
6306 && XEXP (cond
, 1) == const0_rtx
6307 && GET_CODE (false_rtx
) == NEG
6308 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6309 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6310 && ! side_effects_p (true_rtx
))
6315 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6319 simplify_gen_unary (NEG
, mode
,
6320 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6326 /* Look for MIN or MAX. */
6328 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6330 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6331 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6332 && ! side_effects_p (cond
))
6337 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6340 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6343 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6346 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6351 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6352 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6353 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6354 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6355 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6356 neither 1 or -1, but it isn't worth checking for. */
6358 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6360 && GET_MODE_CLASS (mode
) == MODE_INT
6361 && ! side_effects_p (x
))
6363 rtx t
= make_compound_operation (true_rtx
, SET
);
6364 rtx f
= make_compound_operation (false_rtx
, SET
);
6365 rtx cond_op0
= XEXP (cond
, 0);
6366 rtx cond_op1
= XEXP (cond
, 1);
6367 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6368 machine_mode m
= mode
;
6369 rtx z
= 0, c1
= NULL_RTX
;
6371 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6372 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6373 || GET_CODE (t
) == ASHIFT
6374 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6375 && rtx_equal_p (XEXP (t
, 0), f
))
6376 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6378 /* If an identity-zero op is commutative, check whether there
6379 would be a match if we swapped the operands. */
6380 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6381 || GET_CODE (t
) == XOR
)
6382 && rtx_equal_p (XEXP (t
, 1), f
))
6383 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6384 else if (GET_CODE (t
) == SIGN_EXTEND
6385 && (GET_CODE (XEXP (t
, 0)) == PLUS
6386 || GET_CODE (XEXP (t
, 0)) == MINUS
6387 || GET_CODE (XEXP (t
, 0)) == IOR
6388 || GET_CODE (XEXP (t
, 0)) == XOR
6389 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6390 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6391 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6392 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6393 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6394 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6395 && (num_sign_bit_copies (f
, GET_MODE (f
))
6397 (GET_MODE_PRECISION (mode
)
6398 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6400 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6401 extend_op
= SIGN_EXTEND
;
6402 m
= GET_MODE (XEXP (t
, 0));
6404 else if (GET_CODE (t
) == SIGN_EXTEND
6405 && (GET_CODE (XEXP (t
, 0)) == PLUS
6406 || GET_CODE (XEXP (t
, 0)) == IOR
6407 || GET_CODE (XEXP (t
, 0)) == XOR
)
6408 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6409 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6410 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6411 && (num_sign_bit_copies (f
, GET_MODE (f
))
6413 (GET_MODE_PRECISION (mode
)
6414 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6416 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6417 extend_op
= SIGN_EXTEND
;
6418 m
= GET_MODE (XEXP (t
, 0));
6420 else if (GET_CODE (t
) == ZERO_EXTEND
6421 && (GET_CODE (XEXP (t
, 0)) == PLUS
6422 || GET_CODE (XEXP (t
, 0)) == MINUS
6423 || GET_CODE (XEXP (t
, 0)) == IOR
6424 || GET_CODE (XEXP (t
, 0)) == XOR
6425 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6426 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6427 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6428 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6429 && HWI_COMPUTABLE_MODE_P (mode
)
6430 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6431 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6432 && ((nonzero_bits (f
, GET_MODE (f
))
6433 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6436 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6437 extend_op
= ZERO_EXTEND
;
6438 m
= GET_MODE (XEXP (t
, 0));
6440 else if (GET_CODE (t
) == ZERO_EXTEND
6441 && (GET_CODE (XEXP (t
, 0)) == PLUS
6442 || GET_CODE (XEXP (t
, 0)) == IOR
6443 || GET_CODE (XEXP (t
, 0)) == XOR
)
6444 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6445 && HWI_COMPUTABLE_MODE_P (mode
)
6446 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6447 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6448 && ((nonzero_bits (f
, GET_MODE (f
))
6449 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6452 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6453 extend_op
= ZERO_EXTEND
;
6454 m
= GET_MODE (XEXP (t
, 0));
6459 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6460 cond_op0
, cond_op1
),
6461 pc_rtx
, pc_rtx
, 0, 0, 0);
6462 temp
= simplify_gen_binary (MULT
, m
, temp
,
6463 simplify_gen_binary (MULT
, m
, c1
,
6465 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6466 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6468 if (extend_op
!= UNKNOWN
)
6469 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6475 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6476 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6477 negation of a single bit, we can convert this operation to a shift. We
6478 can actually do this more generally, but it doesn't seem worth it. */
6480 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6481 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6482 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6483 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6484 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6485 == GET_MODE_PRECISION (mode
))
6486 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6488 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6489 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6491 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6492 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6493 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6494 && GET_MODE (XEXP (cond
, 0)) == mode
6495 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6496 == nonzero_bits (XEXP (cond
, 0), mode
)
6497 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6498 return XEXP (cond
, 0);
6503 /* Simplify X, a SET expression. Return the new expression. */
6506 simplify_set (rtx x
)
6508 rtx src
= SET_SRC (x
);
6509 rtx dest
= SET_DEST (x
);
6511 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6512 rtx_insn
*other_insn
;
6515 /* (set (pc) (return)) gets written as (return). */
6516 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6519 /* Now that we know for sure which bits of SRC we are using, see if we can
6520 simplify the expression for the object knowing that we only need the
6523 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6525 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6526 SUBST (SET_SRC (x
), src
);
6529 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6530 the comparison result and try to simplify it unless we already have used
6531 undobuf.other_insn. */
6532 if ((GET_MODE_CLASS (mode
) == MODE_CC
6533 || GET_CODE (src
) == COMPARE
6535 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6536 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6537 && COMPARISON_P (*cc_use
)
6538 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6540 enum rtx_code old_code
= GET_CODE (*cc_use
);
6541 enum rtx_code new_code
;
6543 int other_changed
= 0;
6544 rtx inner_compare
= NULL_RTX
;
6545 machine_mode compare_mode
= GET_MODE (dest
);
6547 if (GET_CODE (src
) == COMPARE
)
6549 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6550 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6552 inner_compare
= op0
;
6553 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6557 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6559 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6562 new_code
= old_code
;
6563 else if (!CONSTANT_P (tmp
))
6565 new_code
= GET_CODE (tmp
);
6566 op0
= XEXP (tmp
, 0);
6567 op1
= XEXP (tmp
, 1);
6571 rtx pat
= PATTERN (other_insn
);
6572 undobuf
.other_insn
= other_insn
;
6573 SUBST (*cc_use
, tmp
);
6575 /* Attempt to simplify CC user. */
6576 if (GET_CODE (pat
) == SET
)
6578 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6579 if (new_rtx
!= NULL_RTX
)
6580 SUBST (SET_SRC (pat
), new_rtx
);
6583 /* Convert X into a no-op move. */
6584 SUBST (SET_DEST (x
), pc_rtx
);
6585 SUBST (SET_SRC (x
), pc_rtx
);
6589 /* Simplify our comparison, if possible. */
6590 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6592 #ifdef SELECT_CC_MODE
6593 /* If this machine has CC modes other than CCmode, check to see if we
6594 need to use a different CC mode here. */
6595 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6596 compare_mode
= GET_MODE (op0
);
6597 else if (inner_compare
6598 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6599 && new_code
== old_code
6600 && op0
== XEXP (inner_compare
, 0)
6601 && op1
== XEXP (inner_compare
, 1))
6602 compare_mode
= GET_MODE (inner_compare
);
6604 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6606 /* If the mode changed, we have to change SET_DEST, the mode in the
6607 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6608 a hard register, just build new versions with the proper mode. If it
6609 is a pseudo, we lose unless it is only time we set the pseudo, in
6610 which case we can safely change its mode. */
6611 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6613 if (can_change_dest_mode (dest
, 0, compare_mode
))
6615 unsigned int regno
= REGNO (dest
);
6618 if (regno
< FIRST_PSEUDO_REGISTER
)
6619 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6622 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6623 new_dest
= regno_reg_rtx
[regno
];
6626 SUBST (SET_DEST (x
), new_dest
);
6627 SUBST (XEXP (*cc_use
, 0), new_dest
);
6633 #endif /* SELECT_CC_MODE */
6635 /* If the code changed, we have to build a new comparison in
6636 undobuf.other_insn. */
6637 if (new_code
!= old_code
)
6639 int other_changed_previously
= other_changed
;
6640 unsigned HOST_WIDE_INT mask
;
6641 rtx old_cc_use
= *cc_use
;
6643 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6647 /* If the only change we made was to change an EQ into an NE or
6648 vice versa, OP0 has only one bit that might be nonzero, and OP1
6649 is zero, check if changing the user of the condition code will
6650 produce a valid insn. If it won't, we can keep the original code
6651 in that insn by surrounding our operation with an XOR. */
6653 if (((old_code
== NE
&& new_code
== EQ
)
6654 || (old_code
== EQ
&& new_code
== NE
))
6655 && ! other_changed_previously
&& op1
== const0_rtx
6656 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6657 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6659 rtx pat
= PATTERN (other_insn
), note
= 0;
6661 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6662 && ! check_asm_operands (pat
)))
6664 *cc_use
= old_cc_use
;
6667 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6675 undobuf
.other_insn
= other_insn
;
6677 /* Don't generate a compare of a CC with 0, just use that CC. */
6678 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6680 SUBST (SET_SRC (x
), op0
);
6683 /* Otherwise, if we didn't previously have the same COMPARE we
6684 want, create it from scratch. */
6685 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6686 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6688 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6694 /* Get SET_SRC in a form where we have placed back any
6695 compound expressions. Then do the checks below. */
6696 src
= make_compound_operation (src
, SET
);
6697 SUBST (SET_SRC (x
), src
);
6700 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6701 and X being a REG or (subreg (reg)), we may be able to convert this to
6702 (set (subreg:m2 x) (op)).
6704 We can always do this if M1 is narrower than M2 because that means that
6705 we only care about the low bits of the result.
6707 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6708 perform a narrower operation than requested since the high-order bits will
6709 be undefined. On machine where it is defined, this transformation is safe
6710 as long as M1 and M2 have the same number of words. */
6712 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6713 && !OBJECT_P (SUBREG_REG (src
))
6714 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6716 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6717 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6718 && (WORD_REGISTER_OPERATIONS
6719 || (GET_MODE_SIZE (GET_MODE (src
))
6720 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
6721 #ifdef CANNOT_CHANGE_MODE_CLASS
6722 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6723 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6724 GET_MODE (SUBREG_REG (src
)),
6728 || (GET_CODE (dest
) == SUBREG
6729 && REG_P (SUBREG_REG (dest
)))))
6731 SUBST (SET_DEST (x
),
6732 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6734 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6736 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6739 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6742 && GET_CODE (src
) == SUBREG
6743 && subreg_lowpart_p (src
)
6744 && (GET_MODE_PRECISION (GET_MODE (src
))
6745 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6747 rtx inner
= SUBREG_REG (src
);
6748 machine_mode inner_mode
= GET_MODE (inner
);
6750 /* Here we make sure that we don't have a sign bit on. */
6751 if (val_signbit_known_clear_p (GET_MODE (src
),
6752 nonzero_bits (inner
, inner_mode
)))
6754 SUBST (SET_SRC (x
), inner
);
6759 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6760 would require a paradoxical subreg. Replace the subreg with a
6761 zero_extend to avoid the reload that would otherwise be required. */
6763 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6764 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6765 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6766 && SUBREG_BYTE (src
) == 0
6767 && paradoxical_subreg_p (src
)
6768 && MEM_P (SUBREG_REG (src
)))
6771 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6772 GET_MODE (src
), SUBREG_REG (src
)));
6777 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6778 are comparing an item known to be 0 or -1 against 0, use a logical
6779 operation instead. Check for one of the arms being an IOR of the other
6780 arm with some value. We compute three terms to be IOR'ed together. In
6781 practice, at most two will be nonzero. Then we do the IOR's. */
6783 if (GET_CODE (dest
) != PC
6784 && GET_CODE (src
) == IF_THEN_ELSE
6785 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6786 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6787 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6788 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6789 && (!HAVE_conditional_move
6790 || ! can_conditionally_move_p (GET_MODE (src
)))
6791 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6792 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6793 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6794 && ! side_effects_p (src
))
6796 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6797 ? XEXP (src
, 1) : XEXP (src
, 2));
6798 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6799 ? XEXP (src
, 2) : XEXP (src
, 1));
6800 rtx term1
= const0_rtx
, term2
, term3
;
6802 if (GET_CODE (true_rtx
) == IOR
6803 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6804 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6805 else if (GET_CODE (true_rtx
) == IOR
6806 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6807 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6808 else if (GET_CODE (false_rtx
) == IOR
6809 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6810 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6811 else if (GET_CODE (false_rtx
) == IOR
6812 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6813 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6815 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6816 XEXP (XEXP (src
, 0), 0), true_rtx
);
6817 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6818 simplify_gen_unary (NOT
, GET_MODE (src
),
6819 XEXP (XEXP (src
, 0), 0),
6824 simplify_gen_binary (IOR
, GET_MODE (src
),
6825 simplify_gen_binary (IOR
, GET_MODE (src
),
6832 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6833 whole thing fail. */
6834 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6836 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6839 /* Convert this into a field assignment operation, if possible. */
6840 return make_field_assignment (x
);
6843 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6847 simplify_logical (rtx x
)
6849 machine_mode mode
= GET_MODE (x
);
6850 rtx op0
= XEXP (x
, 0);
6851 rtx op1
= XEXP (x
, 1);
6853 switch (GET_CODE (x
))
6856 /* We can call simplify_and_const_int only if we don't lose
6857 any (sign) bits when converting INTVAL (op1) to
6858 "unsigned HOST_WIDE_INT". */
6859 if (CONST_INT_P (op1
)
6860 && (HWI_COMPUTABLE_MODE_P (mode
)
6861 || INTVAL (op1
) > 0))
6863 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6864 if (GET_CODE (x
) != AND
)
6871 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6872 apply the distributive law and then the inverse distributive
6873 law to see if things simplify. */
6874 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6876 rtx result
= distribute_and_simplify_rtx (x
, 0);
6880 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6882 rtx result
= distribute_and_simplify_rtx (x
, 1);
6889 /* If we have (ior (and A B) C), apply the distributive law and then
6890 the inverse distributive law to see if things simplify. */
6892 if (GET_CODE (op0
) == AND
)
6894 rtx result
= distribute_and_simplify_rtx (x
, 0);
6899 if (GET_CODE (op1
) == AND
)
6901 rtx result
= distribute_and_simplify_rtx (x
, 1);
6914 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6915 operations" because they can be replaced with two more basic operations.
6916 ZERO_EXTEND is also considered "compound" because it can be replaced with
6917 an AND operation, which is simpler, though only one operation.
6919 The function expand_compound_operation is called with an rtx expression
6920 and will convert it to the appropriate shifts and AND operations,
6921 simplifying at each stage.
6923 The function make_compound_operation is called to convert an expression
6924 consisting of shifts and ANDs into the equivalent compound expression.
6925 It is the inverse of this function, loosely speaking. */
6928 expand_compound_operation (rtx x
)
6930 unsigned HOST_WIDE_INT pos
= 0, len
;
6932 unsigned int modewidth
;
6935 switch (GET_CODE (x
))
6940 /* We can't necessarily use a const_int for a multiword mode;
6941 it depends on implicitly extending the value.
6942 Since we don't know the right way to extend it,
6943 we can't tell whether the implicit way is right.
6945 Even for a mode that is no wider than a const_int,
6946 we can't win, because we need to sign extend one of its bits through
6947 the rest of it, and we don't know which bit. */
6948 if (CONST_INT_P (XEXP (x
, 0)))
6951 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6952 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6953 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6954 reloaded. If not for that, MEM's would very rarely be safe.
6956 Reject MODEs bigger than a word, because we might not be able
6957 to reference a two-register group starting with an arbitrary register
6958 (and currently gen_lowpart might crash for a SUBREG). */
6960 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6963 /* Reject MODEs that aren't scalar integers because turning vector
6964 or complex modes into shifts causes problems. */
6966 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6969 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6970 /* If the inner object has VOIDmode (the only way this can happen
6971 is if it is an ASM_OPERANDS), we can't do anything since we don't
6972 know how much masking to do. */
6981 /* ... fall through ... */
6984 /* If the operand is a CLOBBER, just return it. */
6985 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6988 if (!CONST_INT_P (XEXP (x
, 1))
6989 || !CONST_INT_P (XEXP (x
, 2))
6990 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6993 /* Reject MODEs that aren't scalar integers because turning vector
6994 or complex modes into shifts causes problems. */
6996 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6999 len
= INTVAL (XEXP (x
, 1));
7000 pos
= INTVAL (XEXP (x
, 2));
7002 /* This should stay within the object being extracted, fail otherwise. */
7003 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7006 if (BITS_BIG_ENDIAN
)
7007 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7014 /* Convert sign extension to zero extension, if we know that the high
7015 bit is not set, as this is easier to optimize. It will be converted
7016 back to cheaper alternative in make_extraction. */
7017 if (GET_CODE (x
) == SIGN_EXTEND
7018 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7019 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7020 & ~(((unsigned HOST_WIDE_INT
)
7021 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7025 machine_mode mode
= GET_MODE (x
);
7026 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7027 rtx temp2
= expand_compound_operation (temp
);
7029 /* Make sure this is a profitable operation. */
7030 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7031 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7033 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7034 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7040 /* We can optimize some special cases of ZERO_EXTEND. */
7041 if (GET_CODE (x
) == ZERO_EXTEND
)
7043 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7044 know that the last value didn't have any inappropriate bits
7046 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7047 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7048 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7049 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7050 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7051 return XEXP (XEXP (x
, 0), 0);
7053 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7054 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7055 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7056 && subreg_lowpart_p (XEXP (x
, 0))
7057 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7058 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7059 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7060 return SUBREG_REG (XEXP (x
, 0));
7062 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7063 is a comparison and STORE_FLAG_VALUE permits. This is like
7064 the first case, but it works even when GET_MODE (x) is larger
7065 than HOST_WIDE_INT. */
7066 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7067 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7068 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7069 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7070 <= HOST_BITS_PER_WIDE_INT
)
7071 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7072 return XEXP (XEXP (x
, 0), 0);
7074 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7075 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7076 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7077 && subreg_lowpart_p (XEXP (x
, 0))
7078 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7079 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7080 <= HOST_BITS_PER_WIDE_INT
)
7081 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7082 return SUBREG_REG (XEXP (x
, 0));
7086 /* If we reach here, we want to return a pair of shifts. The inner
7087 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7088 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7089 logical depending on the value of UNSIGNEDP.
7091 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7092 converted into an AND of a shift.
7094 We must check for the case where the left shift would have a negative
7095 count. This can happen in a case like (x >> 31) & 255 on machines
7096 that can't shift by a constant. On those machines, we would first
7097 combine the shift with the AND to produce a variable-position
7098 extraction. Then the constant of 31 would be substituted in
7099 to produce such a position. */
7101 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7102 if (modewidth
>= pos
+ len
)
7104 machine_mode mode
= GET_MODE (x
);
7105 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7106 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7108 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7109 tem
, modewidth
- pos
- len
);
7110 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7111 mode
, tem
, modewidth
- len
);
7113 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7114 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7115 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7118 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
7120 /* Any other cases we can't handle. */
7123 /* If we couldn't do this for some reason, return the original
7125 if (GET_CODE (tem
) == CLOBBER
)
7131 /* X is a SET which contains an assignment of one object into
7132 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7133 or certain SUBREGS). If possible, convert it into a series of
7136 We half-heartedly support variable positions, but do not at all
7137 support variable lengths. */
7140 expand_field_assignment (const_rtx x
)
7143 rtx pos
; /* Always counts from low bit. */
7145 rtx mask
, cleared
, masked
;
7146 machine_mode compute_mode
;
7148 /* Loop until we find something we can't simplify. */
7151 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7152 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7154 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7155 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7156 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7158 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7159 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7161 inner
= XEXP (SET_DEST (x
), 0);
7162 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7163 pos
= XEXP (SET_DEST (x
), 2);
7165 /* A constant position should stay within the width of INNER. */
7166 if (CONST_INT_P (pos
)
7167 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7170 if (BITS_BIG_ENDIAN
)
7172 if (CONST_INT_P (pos
))
7173 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7175 else if (GET_CODE (pos
) == MINUS
7176 && CONST_INT_P (XEXP (pos
, 1))
7177 && (INTVAL (XEXP (pos
, 1))
7178 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7179 /* If position is ADJUST - X, new position is X. */
7180 pos
= XEXP (pos
, 0);
7183 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7184 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7185 gen_int_mode (prec
- len
,
7192 /* A SUBREG between two modes that occupy the same numbers of words
7193 can be done by moving the SUBREG to the source. */
7194 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7195 /* We need SUBREGs to compute nonzero_bits properly. */
7196 && nonzero_sign_valid
7197 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7198 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7199 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7200 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7202 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7204 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7211 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7212 inner
= SUBREG_REG (inner
);
7214 compute_mode
= GET_MODE (inner
);
7216 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7217 if (! SCALAR_INT_MODE_P (compute_mode
))
7221 /* Don't do anything for vector or complex integral types. */
7222 if (! FLOAT_MODE_P (compute_mode
))
7225 /* Try to find an integral mode to pun with. */
7226 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7227 if (imode
== BLKmode
)
7230 compute_mode
= imode
;
7231 inner
= gen_lowpart (imode
, inner
);
7234 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7235 if (len
>= HOST_BITS_PER_WIDE_INT
)
7238 /* Now compute the equivalent expression. Make a copy of INNER
7239 for the SET_DEST in case it is a MEM into which we will substitute;
7240 we don't want shared RTL in that case. */
7241 mask
= gen_int_mode (((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7243 cleared
= simplify_gen_binary (AND
, compute_mode
,
7244 simplify_gen_unary (NOT
, compute_mode
,
7245 simplify_gen_binary (ASHIFT
,
7250 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7251 simplify_gen_binary (
7253 gen_lowpart (compute_mode
, SET_SRC (x
)),
7257 x
= gen_rtx_SET (copy_rtx (inner
),
7258 simplify_gen_binary (IOR
, compute_mode
,
7265 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7266 it is an RTX that represents the (variable) starting position; otherwise,
7267 POS is the (constant) starting bit position. Both are counted from the LSB.
7269 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7271 IN_DEST is nonzero if this is a reference in the destination of a SET.
7272 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7273 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7276 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7277 ZERO_EXTRACT should be built even for bits starting at bit 0.
7279 MODE is the desired mode of the result (if IN_DEST == 0).
7281 The result is an RTX for the extraction or NULL_RTX if the target
7285 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7286 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7287 int in_dest
, int in_compare
)
7289 /* This mode describes the size of the storage area
7290 to fetch the overall value from. Within that, we
7291 ignore the POS lowest bits, etc. */
7292 machine_mode is_mode
= GET_MODE (inner
);
7293 machine_mode inner_mode
;
7294 machine_mode wanted_inner_mode
;
7295 machine_mode wanted_inner_reg_mode
= word_mode
;
7296 machine_mode pos_mode
= word_mode
;
7297 machine_mode extraction_mode
= word_mode
;
7298 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7300 rtx orig_pos_rtx
= pos_rtx
;
7301 HOST_WIDE_INT orig_pos
;
7303 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7304 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7306 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7308 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7309 consider just the QI as the memory to extract from.
7310 The subreg adds or removes high bits; its mode is
7311 irrelevant to the meaning of this extraction,
7312 since POS and LEN count from the lsb. */
7313 if (MEM_P (SUBREG_REG (inner
)))
7314 is_mode
= GET_MODE (SUBREG_REG (inner
));
7315 inner
= SUBREG_REG (inner
);
7317 else if (GET_CODE (inner
) == ASHIFT
7318 && CONST_INT_P (XEXP (inner
, 1))
7319 && pos_rtx
== 0 && pos
== 0
7320 && len
> UINTVAL (XEXP (inner
, 1)))
7322 /* We're extracting the least significant bits of an rtx
7323 (ashift X (const_int C)), where LEN > C. Extract the
7324 least significant (LEN - C) bits of X, giving an rtx
7325 whose mode is MODE, then shift it left C times. */
7326 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7327 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7328 unsignedp
, in_dest
, in_compare
);
7330 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7332 else if (GET_CODE (inner
) == TRUNCATE
)
7333 inner
= XEXP (inner
, 0);
7335 inner_mode
= GET_MODE (inner
);
7337 /* See if this can be done without an extraction. We never can if the
7338 width of the field is not the same as that of some integer mode. For
7339 registers, we can only avoid the extraction if the position is at the
7340 low-order bit and this is either not in the destination or we have the
7341 appropriate STRICT_LOW_PART operation available.
7343 For MEM, we can avoid an extract if the field starts on an appropriate
7344 boundary and we can change the mode of the memory reference. */
7346 if (tmode
!= BLKmode
7347 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7349 && (inner_mode
== tmode
7351 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7352 || reg_truncated_to_mode (tmode
, inner
))
7355 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7356 || (MEM_P (inner
) && pos_rtx
== 0
7358 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7359 : BITS_PER_UNIT
)) == 0
7360 /* We can't do this if we are widening INNER_MODE (it
7361 may not be aligned, for one thing). */
7362 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7363 && (inner_mode
== tmode
7364 || (! mode_dependent_address_p (XEXP (inner
, 0),
7365 MEM_ADDR_SPACE (inner
))
7366 && ! MEM_VOLATILE_P (inner
))))))
7368 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7369 field. If the original and current mode are the same, we need not
7370 adjust the offset. Otherwise, we do if bytes big endian.
7372 If INNER is not a MEM, get a piece consisting of just the field
7373 of interest (in this case POS % BITS_PER_WORD must be 0). */
7377 HOST_WIDE_INT offset
;
7379 /* POS counts from lsb, but make OFFSET count in memory order. */
7380 if (BYTES_BIG_ENDIAN
)
7381 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7383 offset
= pos
/ BITS_PER_UNIT
;
7385 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7387 else if (REG_P (inner
))
7389 if (tmode
!= inner_mode
)
7391 /* We can't call gen_lowpart in a DEST since we
7392 always want a SUBREG (see below) and it would sometimes
7393 return a new hard register. */
7396 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7398 if (WORDS_BIG_ENDIAN
7399 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7400 final_word
= ((GET_MODE_SIZE (inner_mode
)
7401 - GET_MODE_SIZE (tmode
))
7402 / UNITS_PER_WORD
) - final_word
;
7404 final_word
*= UNITS_PER_WORD
;
7405 if (BYTES_BIG_ENDIAN
&&
7406 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7407 final_word
+= (GET_MODE_SIZE (inner_mode
)
7408 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7410 /* Avoid creating invalid subregs, for example when
7411 simplifying (x>>32)&255. */
7412 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7415 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7418 new_rtx
= gen_lowpart (tmode
, inner
);
7424 new_rtx
= force_to_mode (inner
, tmode
,
7425 len
>= HOST_BITS_PER_WIDE_INT
7426 ? ~(unsigned HOST_WIDE_INT
) 0
7427 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7430 /* If this extraction is going into the destination of a SET,
7431 make a STRICT_LOW_PART unless we made a MEM. */
7434 return (MEM_P (new_rtx
) ? new_rtx
7435 : (GET_CODE (new_rtx
) != SUBREG
7436 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7437 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7442 if (CONST_SCALAR_INT_P (new_rtx
))
7443 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7444 mode
, new_rtx
, tmode
);
7446 /* If we know that no extraneous bits are set, and that the high
7447 bit is not set, convert the extraction to the cheaper of
7448 sign and zero extension, that are equivalent in these cases. */
7449 if (flag_expensive_optimizations
7450 && (HWI_COMPUTABLE_MODE_P (tmode
)
7451 && ((nonzero_bits (new_rtx
, tmode
)
7452 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7455 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7456 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7458 /* Prefer ZERO_EXTENSION, since it gives more information to
7460 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7461 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7466 /* Otherwise, sign- or zero-extend unless we already are in the
7469 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7473 /* Unless this is a COMPARE or we have a funny memory reference,
7474 don't do anything with zero-extending field extracts starting at
7475 the low-order bit since they are simple AND operations. */
7476 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7477 && ! in_compare
&& unsignedp
)
7480 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7481 if the position is not a constant and the length is not 1. In all
7482 other cases, we would only be going outside our object in cases when
7483 an original shift would have been undefined. */
7485 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7486 || (pos_rtx
!= 0 && len
!= 1)))
7489 enum extraction_pattern pattern
= (in_dest
? EP_insv
7490 : unsignedp
? EP_extzv
: EP_extv
);
7492 /* If INNER is not from memory, we want it to have the mode of a register
7493 extraction pattern's structure operand, or word_mode if there is no
7494 such pattern. The same applies to extraction_mode and pos_mode
7495 and their respective operands.
7497 For memory, assume that the desired extraction_mode and pos_mode
7498 are the same as for a register operation, since at present we don't
7499 have named patterns for aligned memory structures. */
7500 struct extraction_insn insn
;
7501 if (get_best_reg_extraction_insn (&insn
, pattern
,
7502 GET_MODE_BITSIZE (inner_mode
), mode
))
7504 wanted_inner_reg_mode
= insn
.struct_mode
;
7505 pos_mode
= insn
.pos_mode
;
7506 extraction_mode
= insn
.field_mode
;
7509 /* Never narrow an object, since that might not be safe. */
7511 if (mode
!= VOIDmode
7512 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7513 extraction_mode
= mode
;
7516 wanted_inner_mode
= wanted_inner_reg_mode
;
7519 /* Be careful not to go beyond the extracted object and maintain the
7520 natural alignment of the memory. */
7521 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7522 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7523 > GET_MODE_BITSIZE (wanted_inner_mode
))
7525 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7526 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7532 if (BITS_BIG_ENDIAN
)
7534 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7535 BITS_BIG_ENDIAN style. If position is constant, compute new
7536 position. Otherwise, build subtraction.
7537 Note that POS is relative to the mode of the original argument.
7538 If it's a MEM we need to recompute POS relative to that.
7539 However, if we're extracting from (or inserting into) a register,
7540 we want to recompute POS relative to wanted_inner_mode. */
7541 int width
= (MEM_P (inner
)
7542 ? GET_MODE_BITSIZE (is_mode
)
7543 : GET_MODE_BITSIZE (wanted_inner_mode
));
7546 pos
= width
- len
- pos
;
7549 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7550 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7552 /* POS may be less than 0 now, but we check for that below.
7553 Note that it can only be less than 0 if !MEM_P (inner). */
7556 /* If INNER has a wider mode, and this is a constant extraction, try to
7557 make it smaller and adjust the byte to point to the byte containing
7559 if (wanted_inner_mode
!= VOIDmode
7560 && inner_mode
!= wanted_inner_mode
7562 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7564 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7565 && ! MEM_VOLATILE_P (inner
))
7569 /* The computations below will be correct if the machine is big
7570 endian in both bits and bytes or little endian in bits and bytes.
7571 If it is mixed, we must adjust. */
7573 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7574 adjust OFFSET to compensate. */
7575 if (BYTES_BIG_ENDIAN
7576 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7577 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7579 /* We can now move to the desired byte. */
7580 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7581 * GET_MODE_SIZE (wanted_inner_mode
);
7582 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7584 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7585 && is_mode
!= wanted_inner_mode
)
7586 offset
= (GET_MODE_SIZE (is_mode
)
7587 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7589 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7592 /* If INNER is not memory, get it into the proper mode. If we are changing
7593 its mode, POS must be a constant and smaller than the size of the new
7595 else if (!MEM_P (inner
))
7597 /* On the LHS, don't create paradoxical subregs implicitely truncating
7598 the register unless TRULY_NOOP_TRUNCATION. */
7600 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7604 if (GET_MODE (inner
) != wanted_inner_mode
7606 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7612 inner
= force_to_mode (inner
, wanted_inner_mode
,
7614 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7615 ? ~(unsigned HOST_WIDE_INT
) 0
7616 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7621 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7622 have to zero extend. Otherwise, we can just use a SUBREG. */
7624 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7626 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7627 GET_MODE (pos_rtx
));
7629 /* If we know that no extraneous bits are set, and that the high
7630 bit is not set, convert extraction to cheaper one - either
7631 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7633 if (flag_expensive_optimizations
7634 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7635 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7636 & ~(((unsigned HOST_WIDE_INT
)
7637 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7641 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7642 GET_MODE (pos_rtx
));
7644 /* Prefer ZERO_EXTENSION, since it gives more information to
7646 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7647 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7653 /* Make POS_RTX unless we already have it and it is correct. If we don't
7654 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7656 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7657 pos_rtx
= orig_pos_rtx
;
7659 else if (pos_rtx
== 0)
7660 pos_rtx
= GEN_INT (pos
);
7662 /* Make the required operation. See if we can use existing rtx. */
7663 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7664 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7666 new_rtx
= gen_lowpart (mode
, new_rtx
);
7671 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7672 with any other operations in X. Return X without that shift if so. */
7675 extract_left_shift (rtx x
, int count
)
7677 enum rtx_code code
= GET_CODE (x
);
7678 machine_mode mode
= GET_MODE (x
);
7684 /* This is the shift itself. If it is wide enough, we will return
7685 either the value being shifted if the shift count is equal to
7686 COUNT or a shift for the difference. */
7687 if (CONST_INT_P (XEXP (x
, 1))
7688 && INTVAL (XEXP (x
, 1)) >= count
)
7689 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7690 INTVAL (XEXP (x
, 1)) - count
);
7694 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7695 return simplify_gen_unary (code
, mode
, tem
, mode
);
7699 case PLUS
: case IOR
: case XOR
: case AND
:
7700 /* If we can safely shift this constant and we find the inner shift,
7701 make a new operation. */
7702 if (CONST_INT_P (XEXP (x
, 1))
7703 && (UINTVAL (XEXP (x
, 1))
7704 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7705 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7707 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7708 return simplify_gen_binary (code
, mode
, tem
,
7709 gen_int_mode (val
, mode
));
7720 /* Look at the expression rooted at X. Look for expressions
7721 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7722 Form these expressions.
7724 Return the new rtx, usually just X.
7726 Also, for machines like the VAX that don't have logical shift insns,
7727 try to convert logical to arithmetic shift operations in cases where
7728 they are equivalent. This undoes the canonicalizations to logical
7729 shifts done elsewhere.
7731 We try, as much as possible, to re-use rtl expressions to save memory.
7733 IN_CODE says what kind of expression we are processing. Normally, it is
7734 SET. In a memory address it is MEM. When processing the arguments of
7735 a comparison or a COMPARE against zero, it is COMPARE. */
7738 make_compound_operation (rtx x
, enum rtx_code in_code
)
7740 enum rtx_code code
= GET_CODE (x
);
7741 machine_mode mode
= GET_MODE (x
);
7742 int mode_width
= GET_MODE_PRECISION (mode
);
7744 enum rtx_code next_code
;
7750 /* Select the code to be used in recursive calls. Once we are inside an
7751 address, we stay there. If we have a comparison, set to COMPARE,
7752 but once inside, go back to our default of SET. */
7754 next_code
= (code
== MEM
? MEM
7755 : ((code
== COMPARE
|| COMPARISON_P (x
))
7756 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7757 : in_code
== COMPARE
? SET
: in_code
);
7759 /* Process depending on the code of this operation. If NEW is set
7760 nonzero, it will be returned. */
7765 /* Convert shifts by constants into multiplications if inside
7767 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7768 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7769 && INTVAL (XEXP (x
, 1)) >= 0
7770 && SCALAR_INT_MODE_P (mode
))
7772 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7773 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7775 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7776 if (GET_CODE (new_rtx
) == NEG
)
7778 new_rtx
= XEXP (new_rtx
, 0);
7781 multval
= trunc_int_for_mode (multval
, mode
);
7782 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7789 lhs
= make_compound_operation (lhs
, next_code
);
7790 rhs
= make_compound_operation (rhs
, next_code
);
7791 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7792 && SCALAR_INT_MODE_P (mode
))
7794 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7796 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7798 else if (GET_CODE (lhs
) == MULT
7799 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7801 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7802 simplify_gen_unary (NEG
, mode
,
7805 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7809 SUBST (XEXP (x
, 0), lhs
);
7810 SUBST (XEXP (x
, 1), rhs
);
7813 x
= gen_lowpart (mode
, new_rtx
);
7819 lhs
= make_compound_operation (lhs
, next_code
);
7820 rhs
= make_compound_operation (rhs
, next_code
);
7821 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7822 && SCALAR_INT_MODE_P (mode
))
7824 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7826 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7828 else if (GET_CODE (rhs
) == MULT
7829 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7831 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7832 simplify_gen_unary (NEG
, mode
,
7835 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7839 SUBST (XEXP (x
, 0), lhs
);
7840 SUBST (XEXP (x
, 1), rhs
);
7843 return gen_lowpart (mode
, new_rtx
);
7846 /* If the second operand is not a constant, we can't do anything
7848 if (!CONST_INT_P (XEXP (x
, 1)))
7851 /* If the constant is a power of two minus one and the first operand
7852 is a logical right shift, make an extraction. */
7853 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7854 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7856 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7857 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7858 0, in_code
== COMPARE
);
7861 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7862 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7863 && subreg_lowpart_p (XEXP (x
, 0))
7864 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7865 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7867 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7869 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7870 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7871 0, in_code
== COMPARE
);
7873 /* If that didn't give anything, see if the AND simplifies on
7875 if (!new_rtx
&& i
>= 0)
7877 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7878 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
7879 0, in_code
== COMPARE
);
7882 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7883 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7884 || GET_CODE (XEXP (x
, 0)) == IOR
)
7885 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7886 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7887 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7889 /* Apply the distributive law, and then try to make extractions. */
7890 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7891 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7893 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7895 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7898 /* If we are have (and (rotate X C) M) and C is larger than the number
7899 of bits in M, this is an extraction. */
7901 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7902 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7903 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7904 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7906 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7907 new_rtx
= make_extraction (mode
, new_rtx
,
7908 (GET_MODE_PRECISION (mode
)
7909 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7910 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7913 /* On machines without logical shifts, if the operand of the AND is
7914 a logical shift and our mask turns off all the propagated sign
7915 bits, we can replace the logical shift with an arithmetic shift. */
7916 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7917 && !have_insn_for (LSHIFTRT
, mode
)
7918 && have_insn_for (ASHIFTRT
, mode
)
7919 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7920 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7921 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7922 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7924 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7926 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7927 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7929 gen_rtx_ASHIFTRT (mode
,
7930 make_compound_operation
7931 (XEXP (XEXP (x
, 0), 0), next_code
),
7932 XEXP (XEXP (x
, 0), 1)));
7935 /* If the constant is one less than a power of two, this might be
7936 representable by an extraction even if no shift is present.
7937 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7938 we are in a COMPARE. */
7939 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7940 new_rtx
= make_extraction (mode
,
7941 make_compound_operation (XEXP (x
, 0),
7943 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7945 /* If we are in a comparison and this is an AND with a power of two,
7946 convert this into the appropriate bit extract. */
7947 else if (in_code
== COMPARE
7948 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7949 new_rtx
= make_extraction (mode
,
7950 make_compound_operation (XEXP (x
, 0),
7952 i
, NULL_RTX
, 1, 1, 0, 1);
7957 /* If the sign bit is known to be zero, replace this with an
7958 arithmetic shift. */
7959 if (have_insn_for (ASHIFTRT
, mode
)
7960 && ! have_insn_for (LSHIFTRT
, mode
)
7961 && mode_width
<= HOST_BITS_PER_WIDE_INT
7962 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7964 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7965 make_compound_operation (XEXP (x
, 0),
7971 /* ... fall through ... */
7977 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7978 this is a SIGN_EXTRACT. */
7979 if (CONST_INT_P (rhs
)
7980 && GET_CODE (lhs
) == ASHIFT
7981 && CONST_INT_P (XEXP (lhs
, 1))
7982 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7983 && INTVAL (XEXP (lhs
, 1)) >= 0
7984 && INTVAL (rhs
) < mode_width
)
7986 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7987 new_rtx
= make_extraction (mode
, new_rtx
,
7988 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7989 NULL_RTX
, mode_width
- INTVAL (rhs
),
7990 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7994 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7995 If so, try to merge the shifts into a SIGN_EXTEND. We could
7996 also do this for some cases of SIGN_EXTRACT, but it doesn't
7997 seem worth the effort; the case checked for occurs on Alpha. */
8000 && ! (GET_CODE (lhs
) == SUBREG
8001 && (OBJECT_P (SUBREG_REG (lhs
))))
8002 && CONST_INT_P (rhs
)
8003 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8004 && INTVAL (rhs
) < mode_width
8005 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8006 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8007 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8008 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8013 /* Call ourselves recursively on the inner expression. If we are
8014 narrowing the object and it has a different RTL code from
8015 what it originally did, do this SUBREG as a force_to_mode. */
8017 rtx inner
= SUBREG_REG (x
), simplified
;
8018 enum rtx_code subreg_code
= in_code
;
8020 /* If in_code is COMPARE, it isn't always safe to pass it through
8021 to the recursive make_compound_operation call. */
8022 if (subreg_code
== COMPARE
8023 && (!subreg_lowpart_p (x
)
8024 || GET_CODE (inner
) == SUBREG
8025 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8026 is (const_int 0), rather than
8027 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8028 || (GET_CODE (inner
) == AND
8029 && CONST_INT_P (XEXP (inner
, 1))
8030 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8031 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8032 >= GET_MODE_BITSIZE (mode
))))
8035 tem
= make_compound_operation (inner
, subreg_code
);
8038 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8042 if (GET_CODE (tem
) != GET_CODE (inner
)
8043 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8044 && subreg_lowpart_p (x
))
8047 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
8049 /* If we have something other than a SUBREG, we might have
8050 done an expansion, so rerun ourselves. */
8051 if (GET_CODE (newer
) != SUBREG
)
8052 newer
= make_compound_operation (newer
, in_code
);
8054 /* force_to_mode can expand compounds. If it just re-expanded the
8055 compound, use gen_lowpart to convert to the desired mode. */
8056 if (rtx_equal_p (newer
, x
)
8057 /* Likewise if it re-expanded the compound only partially.
8058 This happens for SUBREG of ZERO_EXTRACT if they extract
8059 the same number of bits. */
8060 || (GET_CODE (newer
) == SUBREG
8061 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8062 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8063 && GET_CODE (inner
) == AND
8064 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8065 return gen_lowpart (GET_MODE (x
), tem
);
8081 x
= gen_lowpart (mode
, new_rtx
);
8082 code
= GET_CODE (x
);
8085 /* Now recursively process each operand of this operation. We need to
8086 handle ZERO_EXTEND specially so that we don't lose track of the
8088 if (GET_CODE (x
) == ZERO_EXTEND
)
8090 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8091 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8092 new_rtx
, GET_MODE (XEXP (x
, 0)));
8095 SUBST (XEXP (x
, 0), new_rtx
);
8099 fmt
= GET_RTX_FORMAT (code
);
8100 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8103 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8104 SUBST (XEXP (x
, i
), new_rtx
);
8106 else if (fmt
[i
] == 'E')
8107 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8109 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8110 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8114 /* If this is a commutative operation, the changes to the operands
8115 may have made it noncanonical. */
8116 if (COMMUTATIVE_ARITH_P (x
)
8117 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
8120 SUBST (XEXP (x
, 0), XEXP (x
, 1));
8121 SUBST (XEXP (x
, 1), tem
);
8127 /* Given M see if it is a value that would select a field of bits
8128 within an item, but not the entire word. Return -1 if not.
8129 Otherwise, return the starting position of the field, where 0 is the
8132 *PLEN is set to the length of the field. */
8135 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8137 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8138 int pos
= m
? ctz_hwi (m
) : -1;
8142 /* Now shift off the low-order zero bits and see if we have a
8143 power of two minus 1. */
8144 len
= exact_log2 ((m
>> pos
) + 1);
8153 /* If X refers to a register that equals REG in value, replace these
8154 references with REG. */
8156 canon_reg_for_combine (rtx x
, rtx reg
)
8163 enum rtx_code code
= GET_CODE (x
);
8164 switch (GET_RTX_CLASS (code
))
8167 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8168 if (op0
!= XEXP (x
, 0))
8169 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8174 case RTX_COMM_ARITH
:
8175 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8176 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8177 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8178 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8182 case RTX_COMM_COMPARE
:
8183 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8184 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8185 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8186 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8187 GET_MODE (op0
), op0
, op1
);
8191 case RTX_BITFIELD_OPS
:
8192 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8193 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8194 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8195 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8196 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8197 GET_MODE (op0
), op0
, op1
, op2
);
8202 if (rtx_equal_p (get_last_value (reg
), x
)
8203 || rtx_equal_p (reg
, get_last_value (x
)))
8212 fmt
= GET_RTX_FORMAT (code
);
8214 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8217 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8218 if (op
!= XEXP (x
, i
))
8228 else if (fmt
[i
] == 'E')
8231 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8233 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8234 if (op
!= XVECEXP (x
, i
, j
))
8241 XVECEXP (x
, i
, j
) = op
;
8252 /* Return X converted to MODE. If the value is already truncated to
8253 MODE we can just return a subreg even though in the general case we
8254 would need an explicit truncation. */
8257 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8259 if (!CONST_INT_P (x
)
8260 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8261 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8262 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8264 /* Bit-cast X into an integer mode. */
8265 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8266 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8267 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8271 return gen_lowpart (mode
, x
);
8274 /* See if X can be simplified knowing that we will only refer to it in
8275 MODE and will only refer to those bits that are nonzero in MASK.
8276 If other bits are being computed or if masking operations are done
8277 that select a superset of the bits in MASK, they can sometimes be
8280 Return a possibly simplified expression, but always convert X to
8281 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8283 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8284 are all off in X. This is used when X will be complemented, by either
8285 NOT, NEG, or XOR. */
8288 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8291 enum rtx_code code
= GET_CODE (x
);
8292 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8293 machine_mode op_mode
;
8294 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8297 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8298 code below will do the wrong thing since the mode of such an
8299 expression is VOIDmode.
8301 Also do nothing if X is a CLOBBER; this can happen if X was
8302 the return value from a call to gen_lowpart. */
8303 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8306 /* We want to perform the operation in its present mode unless we know
8307 that the operation is valid in MODE, in which case we do the operation
8309 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8310 && have_insn_for (code
, mode
))
8311 ? mode
: GET_MODE (x
));
8313 /* It is not valid to do a right-shift in a narrower mode
8314 than the one it came in with. */
8315 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8316 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8317 op_mode
= GET_MODE (x
);
8319 /* Truncate MASK to fit OP_MODE. */
8321 mask
&= GET_MODE_MASK (op_mode
);
8323 /* When we have an arithmetic operation, or a shift whose count we
8324 do not know, we need to assume that all bits up to the highest-order
8325 bit in MASK will be needed. This is how we form such a mask. */
8326 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
8327 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8329 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8332 /* Determine what bits of X are guaranteed to be (non)zero. */
8333 nonzero
= nonzero_bits (x
, mode
);
8335 /* If none of the bits in X are needed, return a zero. */
8336 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8339 /* If X is a CONST_INT, return a new one. Do this here since the
8340 test below will fail. */
8341 if (CONST_INT_P (x
))
8343 if (SCALAR_INT_MODE_P (mode
))
8344 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8347 x
= GEN_INT (INTVAL (x
) & mask
);
8348 return gen_lowpart_common (mode
, x
);
8352 /* If X is narrower than MODE and we want all the bits in X's mode, just
8353 get X in the proper mode. */
8354 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8355 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8356 return gen_lowpart (mode
, x
);
8358 /* We can ignore the effect of a SUBREG if it narrows the mode or
8359 if the constant masks to zero all the bits the mode doesn't have. */
8360 if (GET_CODE (x
) == SUBREG
8361 && subreg_lowpart_p (x
)
8362 && ((GET_MODE_SIZE (GET_MODE (x
))
8363 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8365 & GET_MODE_MASK (GET_MODE (x
))
8366 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8367 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8369 /* The arithmetic simplifications here only work for scalar integer modes. */
8370 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8371 return gen_lowpart_or_truncate (mode
, x
);
8376 /* If X is a (clobber (const_int)), return it since we know we are
8377 generating something that won't match. */
8384 x
= expand_compound_operation (x
);
8385 if (GET_CODE (x
) != code
)
8386 return force_to_mode (x
, mode
, mask
, next_select
);
8390 /* Similarly for a truncate. */
8391 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8394 /* If this is an AND with a constant, convert it into an AND
8395 whose constant is the AND of that constant with MASK. If it
8396 remains an AND of MASK, delete it since it is redundant. */
8398 if (CONST_INT_P (XEXP (x
, 1)))
8400 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8401 mask
& INTVAL (XEXP (x
, 1)));
8403 /* If X is still an AND, see if it is an AND with a mask that
8404 is just some low-order bits. If so, and it is MASK, we don't
8407 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8408 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8412 /* If it remains an AND, try making another AND with the bits
8413 in the mode mask that aren't in MASK turned on. If the
8414 constant in the AND is wide enough, this might make a
8415 cheaper constant. */
8417 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8418 && GET_MODE_MASK (GET_MODE (x
)) != mask
8419 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8421 unsigned HOST_WIDE_INT cval
8422 = UINTVAL (XEXP (x
, 1))
8423 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8426 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8427 gen_int_mode (cval
, GET_MODE (x
)));
8428 if (set_src_cost (y
, GET_MODE (x
), optimize_this_for_speed_p
)
8429 < set_src_cost (x
, GET_MODE (x
), optimize_this_for_speed_p
))
8439 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8440 low-order bits (as in an alignment operation) and FOO is already
8441 aligned to that boundary, mask C1 to that boundary as well.
8442 This may eliminate that PLUS and, later, the AND. */
8445 unsigned int width
= GET_MODE_PRECISION (mode
);
8446 unsigned HOST_WIDE_INT smask
= mask
;
8448 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8449 number, sign extend it. */
8451 if (width
< HOST_BITS_PER_WIDE_INT
8452 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8453 smask
|= HOST_WIDE_INT_M1U
<< width
;
8455 if (CONST_INT_P (XEXP (x
, 1))
8456 && exact_log2 (- smask
) >= 0
8457 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8458 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8459 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8460 (INTVAL (XEXP (x
, 1)) & smask
)),
8461 mode
, smask
, next_select
);
8464 /* ... fall through ... */
8467 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8468 most significant bit in MASK since carries from those bits will
8469 affect the bits we are interested in. */
8474 /* If X is (minus C Y) where C's least set bit is larger than any bit
8475 in the mask, then we may replace with (neg Y). */
8476 if (CONST_INT_P (XEXP (x
, 0))
8477 && ((UINTVAL (XEXP (x
, 0)) & -UINTVAL (XEXP (x
, 0))) > mask
))
8479 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8481 return force_to_mode (x
, mode
, mask
, next_select
);
8484 /* Similarly, if C contains every bit in the fuller_mask, then we may
8485 replace with (not Y). */
8486 if (CONST_INT_P (XEXP (x
, 0))
8487 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8489 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8490 XEXP (x
, 1), GET_MODE (x
));
8491 return force_to_mode (x
, mode
, mask
, next_select
);
8499 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8500 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8501 operation which may be a bitfield extraction. Ensure that the
8502 constant we form is not wider than the mode of X. */
8504 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8505 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8506 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8507 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8508 && CONST_INT_P (XEXP (x
, 1))
8509 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8510 + floor_log2 (INTVAL (XEXP (x
, 1))))
8511 < GET_MODE_PRECISION (GET_MODE (x
)))
8512 && (UINTVAL (XEXP (x
, 1))
8513 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8515 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8516 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8518 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8519 XEXP (XEXP (x
, 0), 0), temp
);
8520 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8521 XEXP (XEXP (x
, 0), 1));
8522 return force_to_mode (x
, mode
, mask
, next_select
);
8526 /* For most binary operations, just propagate into the operation and
8527 change the mode if we have an operation of that mode. */
8529 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8530 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8532 /* If we ended up truncating both operands, truncate the result of the
8533 operation instead. */
8534 if (GET_CODE (op0
) == TRUNCATE
8535 && GET_CODE (op1
) == TRUNCATE
)
8537 op0
= XEXP (op0
, 0);
8538 op1
= XEXP (op1
, 0);
8541 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8542 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8544 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8545 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8549 /* For left shifts, do the same, but just for the first operand.
8550 However, we cannot do anything with shifts where we cannot
8551 guarantee that the counts are smaller than the size of the mode
8552 because such a count will have a different meaning in a
8555 if (! (CONST_INT_P (XEXP (x
, 1))
8556 && INTVAL (XEXP (x
, 1)) >= 0
8557 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8558 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8559 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8560 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8563 /* If the shift count is a constant and we can do arithmetic in
8564 the mode of the shift, refine which bits we need. Otherwise, use the
8565 conservative form of the mask. */
8566 if (CONST_INT_P (XEXP (x
, 1))
8567 && INTVAL (XEXP (x
, 1)) >= 0
8568 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8569 && HWI_COMPUTABLE_MODE_P (op_mode
))
8570 mask
>>= INTVAL (XEXP (x
, 1));
8574 op0
= gen_lowpart_or_truncate (op_mode
,
8575 force_to_mode (XEXP (x
, 0), op_mode
,
8576 mask
, next_select
));
8578 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8579 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8583 /* Here we can only do something if the shift count is a constant,
8584 this shift constant is valid for the host, and we can do arithmetic
8587 if (CONST_INT_P (XEXP (x
, 1))
8588 && INTVAL (XEXP (x
, 1)) >= 0
8589 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8590 && HWI_COMPUTABLE_MODE_P (op_mode
))
8592 rtx inner
= XEXP (x
, 0);
8593 unsigned HOST_WIDE_INT inner_mask
;
8595 /* Select the mask of the bits we need for the shift operand. */
8596 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8598 /* We can only change the mode of the shift if we can do arithmetic
8599 in the mode of the shift and INNER_MASK is no wider than the
8600 width of X's mode. */
8601 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8602 op_mode
= GET_MODE (x
);
8604 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8606 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8607 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8610 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8611 shift and AND produces only copies of the sign bit (C2 is one less
8612 than a power of two), we can do this with just a shift. */
8614 if (GET_CODE (x
) == LSHIFTRT
8615 && CONST_INT_P (XEXP (x
, 1))
8616 /* The shift puts one of the sign bit copies in the least significant
8618 && ((INTVAL (XEXP (x
, 1))
8619 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8620 >= GET_MODE_PRECISION (GET_MODE (x
)))
8621 && exact_log2 (mask
+ 1) >= 0
8622 /* Number of bits left after the shift must be more than the mask
8624 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8625 <= GET_MODE_PRECISION (GET_MODE (x
)))
8626 /* Must be more sign bit copies than the mask needs. */
8627 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8628 >= exact_log2 (mask
+ 1)))
8629 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8630 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8631 - exact_log2 (mask
+ 1)));
8636 /* If we are just looking for the sign bit, we don't need this shift at
8637 all, even if it has a variable count. */
8638 if (val_signbit_p (GET_MODE (x
), mask
))
8639 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8641 /* If this is a shift by a constant, get a mask that contains those bits
8642 that are not copies of the sign bit. We then have two cases: If
8643 MASK only includes those bits, this can be a logical shift, which may
8644 allow simplifications. If MASK is a single-bit field not within
8645 those bits, we are requesting a copy of the sign bit and hence can
8646 shift the sign bit to the appropriate location. */
8648 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8649 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8653 /* If the considered data is wider than HOST_WIDE_INT, we can't
8654 represent a mask for all its bits in a single scalar.
8655 But we only care about the lower bits, so calculate these. */
8657 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8659 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8661 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8662 is the number of bits a full-width mask would have set.
8663 We need only shift if these are fewer than nonzero can
8664 hold. If not, we must keep all bits set in nonzero. */
8666 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8667 < HOST_BITS_PER_WIDE_INT
)
8668 nonzero
>>= INTVAL (XEXP (x
, 1))
8669 + HOST_BITS_PER_WIDE_INT
8670 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8674 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8675 nonzero
>>= INTVAL (XEXP (x
, 1));
8678 if ((mask
& ~nonzero
) == 0)
8680 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8681 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8682 if (GET_CODE (x
) != ASHIFTRT
)
8683 return force_to_mode (x
, mode
, mask
, next_select
);
8686 else if ((i
= exact_log2 (mask
)) >= 0)
8688 x
= simplify_shift_const
8689 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8690 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8692 if (GET_CODE (x
) != ASHIFTRT
)
8693 return force_to_mode (x
, mode
, mask
, next_select
);
8697 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8698 even if the shift count isn't a constant. */
8700 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8701 XEXP (x
, 0), XEXP (x
, 1));
8705 /* If this is a zero- or sign-extension operation that just affects bits
8706 we don't care about, remove it. Be sure the call above returned
8707 something that is still a shift. */
8709 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8710 && CONST_INT_P (XEXP (x
, 1))
8711 && INTVAL (XEXP (x
, 1)) >= 0
8712 && (INTVAL (XEXP (x
, 1))
8713 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8714 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8715 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8716 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8723 /* If the shift count is constant and we can do computations
8724 in the mode of X, compute where the bits we care about are.
8725 Otherwise, we can't do anything. Don't change the mode of
8726 the shift or propagate MODE into the shift, though. */
8727 if (CONST_INT_P (XEXP (x
, 1))
8728 && INTVAL (XEXP (x
, 1)) >= 0)
8730 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8732 gen_int_mode (mask
, GET_MODE (x
)),
8734 if (temp
&& CONST_INT_P (temp
))
8735 x
= simplify_gen_binary (code
, GET_MODE (x
),
8736 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8737 INTVAL (temp
), next_select
),
8743 /* If we just want the low-order bit, the NEG isn't needed since it
8744 won't change the low-order bit. */
8746 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8748 /* We need any bits less significant than the most significant bit in
8749 MASK since carries from those bits will affect the bits we are
8755 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8756 same as the XOR case above. Ensure that the constant we form is not
8757 wider than the mode of X. */
8759 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8760 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8761 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8762 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8763 < GET_MODE_PRECISION (GET_MODE (x
)))
8764 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8766 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8768 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8769 XEXP (XEXP (x
, 0), 0), temp
);
8770 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8771 temp
, XEXP (XEXP (x
, 0), 1));
8773 return force_to_mode (x
, mode
, mask
, next_select
);
8776 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8777 use the full mask inside the NOT. */
8781 op0
= gen_lowpart_or_truncate (op_mode
,
8782 force_to_mode (XEXP (x
, 0), mode
, mask
,
8784 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8785 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8789 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8790 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8791 which is equal to STORE_FLAG_VALUE. */
8792 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8793 && XEXP (x
, 1) == const0_rtx
8794 && GET_MODE (XEXP (x
, 0)) == mode
8795 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8796 && (nonzero_bits (XEXP (x
, 0), mode
)
8797 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8798 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8803 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8804 written in a narrower mode. We play it safe and do not do so. */
8806 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8807 force_to_mode (XEXP (x
, 1), mode
,
8808 mask
, next_select
));
8809 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8810 force_to_mode (XEXP (x
, 2), mode
,
8811 mask
, next_select
));
8812 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8813 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8814 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8822 /* Ensure we return a value of the proper mode. */
8823 return gen_lowpart_or_truncate (mode
, x
);
8826 /* Return nonzero if X is an expression that has one of two values depending on
8827 whether some other value is zero or nonzero. In that case, we return the
8828 value that is being tested, *PTRUE is set to the value if the rtx being
8829 returned has a nonzero value, and *PFALSE is set to the other alternative.
8831 If we return zero, we set *PTRUE and *PFALSE to X. */
8834 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8836 machine_mode mode
= GET_MODE (x
);
8837 enum rtx_code code
= GET_CODE (x
);
8838 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8839 unsigned HOST_WIDE_INT nz
;
8841 /* If we are comparing a value against zero, we are done. */
8842 if ((code
== NE
|| code
== EQ
)
8843 && XEXP (x
, 1) == const0_rtx
)
8845 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8846 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8850 /* If this is a unary operation whose operand has one of two values, apply
8851 our opcode to compute those values. */
8852 else if (UNARY_P (x
)
8853 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8855 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8856 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8857 GET_MODE (XEXP (x
, 0)));
8861 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8862 make can't possibly match and would suppress other optimizations. */
8863 else if (code
== COMPARE
)
8866 /* If this is a binary operation, see if either side has only one of two
8867 values. If either one does or if both do and they are conditional on
8868 the same value, compute the new true and false values. */
8869 else if (BINARY_P (x
))
8871 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8872 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8874 if ((cond0
!= 0 || cond1
!= 0)
8875 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8877 /* If if_then_else_cond returned zero, then true/false are the
8878 same rtl. We must copy one of them to prevent invalid rtl
8881 true0
= copy_rtx (true0
);
8882 else if (cond1
== 0)
8883 true1
= copy_rtx (true1
);
8885 if (COMPARISON_P (x
))
8887 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8889 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8894 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8895 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8898 return cond0
? cond0
: cond1
;
8901 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8902 operands is zero when the other is nonzero, and vice-versa,
8903 and STORE_FLAG_VALUE is 1 or -1. */
8905 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8906 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8908 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8910 rtx op0
= XEXP (XEXP (x
, 0), 1);
8911 rtx op1
= XEXP (XEXP (x
, 1), 1);
8913 cond0
= XEXP (XEXP (x
, 0), 0);
8914 cond1
= XEXP (XEXP (x
, 1), 0);
8916 if (COMPARISON_P (cond0
)
8917 && COMPARISON_P (cond1
)
8918 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8919 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8920 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8921 || ((swap_condition (GET_CODE (cond0
))
8922 == reversed_comparison_code (cond1
, NULL
))
8923 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8924 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8925 && ! side_effects_p (x
))
8927 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8928 *pfalse
= simplify_gen_binary (MULT
, mode
,
8930 ? simplify_gen_unary (NEG
, mode
,
8938 /* Similarly for MULT, AND and UMIN, except that for these the result
8940 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8941 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8942 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8944 cond0
= XEXP (XEXP (x
, 0), 0);
8945 cond1
= XEXP (XEXP (x
, 1), 0);
8947 if (COMPARISON_P (cond0
)
8948 && COMPARISON_P (cond1
)
8949 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8950 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8951 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8952 || ((swap_condition (GET_CODE (cond0
))
8953 == reversed_comparison_code (cond1
, NULL
))
8954 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8955 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8956 && ! side_effects_p (x
))
8958 *ptrue
= *pfalse
= const0_rtx
;
8964 else if (code
== IF_THEN_ELSE
)
8966 /* If we have IF_THEN_ELSE already, extract the condition and
8967 canonicalize it if it is NE or EQ. */
8968 cond0
= XEXP (x
, 0);
8969 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8970 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8971 return XEXP (cond0
, 0);
8972 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8974 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8975 return XEXP (cond0
, 0);
8981 /* If X is a SUBREG, we can narrow both the true and false values
8982 if the inner expression, if there is a condition. */
8983 else if (code
== SUBREG
8984 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8987 true0
= simplify_gen_subreg (mode
, true0
,
8988 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8989 false0
= simplify_gen_subreg (mode
, false0
,
8990 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8991 if (true0
&& false0
)
8999 /* If X is a constant, this isn't special and will cause confusions
9000 if we treat it as such. Likewise if it is equivalent to a constant. */
9001 else if (CONSTANT_P (x
)
9002 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9005 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9006 will be least confusing to the rest of the compiler. */
9007 else if (mode
== BImode
)
9009 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9013 /* If X is known to be either 0 or -1, those are the true and
9014 false values when testing X. */
9015 else if (x
== constm1_rtx
|| x
== const0_rtx
9016 || (mode
!= VOIDmode
9017 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9019 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9023 /* Likewise for 0 or a single bit. */
9024 else if (HWI_COMPUTABLE_MODE_P (mode
)
9025 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
9027 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9031 /* Otherwise fail; show no condition with true and false values the same. */
9032 *ptrue
= *pfalse
= x
;
9036 /* Return the value of expression X given the fact that condition COND
9037 is known to be true when applied to REG as its first operand and VAL
9038 as its second. X is known to not be shared and so can be modified in
9041 We only handle the simplest cases, and specifically those cases that
9042 arise with IF_THEN_ELSE expressions. */
9045 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9047 enum rtx_code code
= GET_CODE (x
);
9051 if (side_effects_p (x
))
9054 /* If either operand of the condition is a floating point value,
9055 then we have to avoid collapsing an EQ comparison. */
9057 && rtx_equal_p (x
, reg
)
9058 && ! FLOAT_MODE_P (GET_MODE (x
))
9059 && ! FLOAT_MODE_P (GET_MODE (val
)))
9062 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9065 /* If X is (abs REG) and we know something about REG's relationship
9066 with zero, we may be able to simplify this. */
9068 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9071 case GE
: case GT
: case EQ
:
9074 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9076 GET_MODE (XEXP (x
, 0)));
9081 /* The only other cases we handle are MIN, MAX, and comparisons if the
9082 operands are the same as REG and VAL. */
9084 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9086 if (rtx_equal_p (XEXP (x
, 0), val
))
9088 std::swap (val
, reg
);
9089 cond
= swap_condition (cond
);
9092 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9094 if (COMPARISON_P (x
))
9096 if (comparison_dominates_p (cond
, code
))
9097 return const_true_rtx
;
9099 code
= reversed_comparison_code (x
, NULL
);
9101 && comparison_dominates_p (cond
, code
))
9106 else if (code
== SMAX
|| code
== SMIN
9107 || code
== UMIN
|| code
== UMAX
)
9109 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9111 /* Do not reverse the condition when it is NE or EQ.
9112 This is because we cannot conclude anything about
9113 the value of 'SMAX (x, y)' when x is not equal to y,
9114 but we can when x equals y. */
9115 if ((code
== SMAX
|| code
== UMAX
)
9116 && ! (cond
== EQ
|| cond
== NE
))
9117 cond
= reverse_condition (cond
);
9122 return unsignedp
? x
: XEXP (x
, 1);
9124 return unsignedp
? x
: XEXP (x
, 0);
9126 return unsignedp
? XEXP (x
, 1) : x
;
9128 return unsignedp
? XEXP (x
, 0) : x
;
9135 else if (code
== SUBREG
)
9137 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9138 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9140 if (SUBREG_REG (x
) != r
)
9142 /* We must simplify subreg here, before we lose track of the
9143 original inner_mode. */
9144 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9145 inner_mode
, SUBREG_BYTE (x
));
9149 SUBST (SUBREG_REG (x
), r
);
9154 /* We don't have to handle SIGN_EXTEND here, because even in the
9155 case of replacing something with a modeless CONST_INT, a
9156 CONST_INT is already (supposed to be) a valid sign extension for
9157 its narrower mode, which implies it's already properly
9158 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9159 story is different. */
9160 else if (code
== ZERO_EXTEND
)
9162 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9163 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9165 if (XEXP (x
, 0) != r
)
9167 /* We must simplify the zero_extend here, before we lose
9168 track of the original inner_mode. */
9169 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9174 SUBST (XEXP (x
, 0), r
);
9180 fmt
= GET_RTX_FORMAT (code
);
9181 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9184 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9185 else if (fmt
[i
] == 'E')
9186 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9187 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9194 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9195 assignment as a field assignment. */
9198 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9200 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9202 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9204 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9206 /* For big endian, adjust the memory offset. */
9207 if (BYTES_BIG_ENDIAN
)
9208 x
= adjust_address_nv (x
, GET_MODE (y
),
9209 -subreg_lowpart_offset (GET_MODE (x
),
9212 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9215 if (x
== y
|| rtx_equal_p (x
, y
))
9218 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9221 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9222 Note that all SUBREGs of MEM are paradoxical; otherwise they
9223 would have been rewritten. */
9224 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9225 && MEM_P (SUBREG_REG (y
))
9226 && rtx_equal_p (SUBREG_REG (y
),
9227 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9230 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9231 && MEM_P (SUBREG_REG (x
))
9232 && rtx_equal_p (SUBREG_REG (x
),
9233 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9236 /* We used to see if get_last_value of X and Y were the same but that's
9237 not correct. In one direction, we'll cause the assignment to have
9238 the wrong destination and in the case, we'll import a register into this
9239 insn that might have already have been dead. So fail if none of the
9240 above cases are true. */
9244 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9245 Return that assignment if so.
9247 We only handle the most common cases. */
9250 make_field_assignment (rtx x
)
9252 rtx dest
= SET_DEST (x
);
9253 rtx src
= SET_SRC (x
);
9258 unsigned HOST_WIDE_INT len
;
9262 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9263 a clear of a one-bit field. We will have changed it to
9264 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9267 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9268 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9269 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9270 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9272 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9275 return gen_rtx_SET (assign
, const0_rtx
);
9279 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9280 && subreg_lowpart_p (XEXP (src
, 0))
9281 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9282 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9283 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9284 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9285 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9286 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9288 assign
= make_extraction (VOIDmode
, dest
, 0,
9289 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9292 return gen_rtx_SET (assign
, const0_rtx
);
9296 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9298 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9299 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9300 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9302 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9305 return gen_rtx_SET (assign
, const1_rtx
);
9309 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9310 SRC is an AND with all bits of that field set, then we can discard
9312 if (GET_CODE (dest
) == ZERO_EXTRACT
9313 && CONST_INT_P (XEXP (dest
, 1))
9314 && GET_CODE (src
) == AND
9315 && CONST_INT_P (XEXP (src
, 1)))
9317 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9318 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9319 unsigned HOST_WIDE_INT ze_mask
;
9321 if (width
>= HOST_BITS_PER_WIDE_INT
)
9324 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9326 /* Complete overlap. We can remove the source AND. */
9327 if ((and_mask
& ze_mask
) == ze_mask
)
9328 return gen_rtx_SET (dest
, XEXP (src
, 0));
9330 /* Partial overlap. We can reduce the source AND. */
9331 if ((and_mask
& ze_mask
) != and_mask
)
9333 mode
= GET_MODE (src
);
9334 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9335 gen_int_mode (and_mask
& ze_mask
, mode
));
9336 return gen_rtx_SET (dest
, src
);
9340 /* The other case we handle is assignments into a constant-position
9341 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9342 a mask that has all one bits except for a group of zero bits and
9343 OTHER is known to have zeros where C1 has ones, this is such an
9344 assignment. Compute the position and length from C1. Shift OTHER
9345 to the appropriate position, force it to the required mode, and
9346 make the extraction. Check for the AND in both operands. */
9348 /* One or more SUBREGs might obscure the constant-position field
9349 assignment. The first one we are likely to encounter is an outer
9350 narrowing SUBREG, which we can just strip for the purposes of
9351 identifying the constant-field assignment. */
9352 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9353 src
= SUBREG_REG (src
);
9355 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9358 rhs
= expand_compound_operation (XEXP (src
, 0));
9359 lhs
= expand_compound_operation (XEXP (src
, 1));
9361 if (GET_CODE (rhs
) == AND
9362 && CONST_INT_P (XEXP (rhs
, 1))
9363 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9364 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9365 /* The second SUBREG that might get in the way is a paradoxical
9366 SUBREG around the first operand of the AND. We want to
9367 pretend the operand is as wide as the destination here. We
9368 do this by adjusting the MEM to wider mode for the sole
9369 purpose of the call to rtx_equal_for_field_assignment_p. Also
9370 note this trick only works for MEMs. */
9371 else if (GET_CODE (rhs
) == AND
9372 && paradoxical_subreg_p (XEXP (rhs
, 0))
9373 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9374 && CONST_INT_P (XEXP (rhs
, 1))
9375 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9377 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9378 else if (GET_CODE (lhs
) == AND
9379 && CONST_INT_P (XEXP (lhs
, 1))
9380 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9381 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9382 /* The second SUBREG that might get in the way is a paradoxical
9383 SUBREG around the first operand of the AND. We want to
9384 pretend the operand is as wide as the destination here. We
9385 do this by adjusting the MEM to wider mode for the sole
9386 purpose of the call to rtx_equal_for_field_assignment_p. Also
9387 note this trick only works for MEMs. */
9388 else if (GET_CODE (lhs
) == AND
9389 && paradoxical_subreg_p (XEXP (lhs
, 0))
9390 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9391 && CONST_INT_P (XEXP (lhs
, 1))
9392 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9394 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9398 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9399 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9400 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9401 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9404 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9408 /* The mode to use for the source is the mode of the assignment, or of
9409 what is inside a possible STRICT_LOW_PART. */
9410 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9411 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9413 /* Shift OTHER right POS places and make it the source, restricting it
9414 to the proper length and mode. */
9416 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9420 src
= force_to_mode (src
, mode
,
9421 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9422 ? ~(unsigned HOST_WIDE_INT
) 0
9423 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9426 /* If SRC is masked by an AND that does not make a difference in
9427 the value being stored, strip it. */
9428 if (GET_CODE (assign
) == ZERO_EXTRACT
9429 && CONST_INT_P (XEXP (assign
, 1))
9430 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9431 && GET_CODE (src
) == AND
9432 && CONST_INT_P (XEXP (src
, 1))
9433 && UINTVAL (XEXP (src
, 1))
9434 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9435 src
= XEXP (src
, 0);
9437 return gen_rtx_SET (assign
, src
);
9440 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9444 apply_distributive_law (rtx x
)
9446 enum rtx_code code
= GET_CODE (x
);
9447 enum rtx_code inner_code
;
9448 rtx lhs
, rhs
, other
;
9451 /* Distributivity is not true for floating point as it can change the
9452 value. So we don't do it unless -funsafe-math-optimizations. */
9453 if (FLOAT_MODE_P (GET_MODE (x
))
9454 && ! flag_unsafe_math_optimizations
)
9457 /* The outer operation can only be one of the following: */
9458 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9459 && code
!= PLUS
&& code
!= MINUS
)
9465 /* If either operand is a primitive we can't do anything, so get out
9467 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9470 lhs
= expand_compound_operation (lhs
);
9471 rhs
= expand_compound_operation (rhs
);
9472 inner_code
= GET_CODE (lhs
);
9473 if (inner_code
!= GET_CODE (rhs
))
9476 /* See if the inner and outer operations distribute. */
9483 /* These all distribute except over PLUS. */
9484 if (code
== PLUS
|| code
== MINUS
)
9489 if (code
!= PLUS
&& code
!= MINUS
)
9494 /* This is also a multiply, so it distributes over everything. */
9497 /* This used to handle SUBREG, but this turned out to be counter-
9498 productive, since (subreg (op ...)) usually is not handled by
9499 insn patterns, and this "optimization" therefore transformed
9500 recognizable patterns into unrecognizable ones. Therefore the
9501 SUBREG case was removed from here.
9503 It is possible that distributing SUBREG over arithmetic operations
9504 leads to an intermediate result than can then be optimized further,
9505 e.g. by moving the outer SUBREG to the other side of a SET as done
9506 in simplify_set. This seems to have been the original intent of
9507 handling SUBREGs here.
9509 However, with current GCC this does not appear to actually happen,
9510 at least on major platforms. If some case is found where removing
9511 the SUBREG case here prevents follow-on optimizations, distributing
9512 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9518 /* Set LHS and RHS to the inner operands (A and B in the example
9519 above) and set OTHER to the common operand (C in the example).
9520 There is only one way to do this unless the inner operation is
9522 if (COMMUTATIVE_ARITH_P (lhs
)
9523 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9524 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9525 else if (COMMUTATIVE_ARITH_P (lhs
)
9526 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9527 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9528 else if (COMMUTATIVE_ARITH_P (lhs
)
9529 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9530 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9531 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9532 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9536 /* Form the new inner operation, seeing if it simplifies first. */
9537 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9539 /* There is one exception to the general way of distributing:
9540 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9541 if (code
== XOR
&& inner_code
== IOR
)
9544 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9547 /* We may be able to continuing distributing the result, so call
9548 ourselves recursively on the inner operation before forming the
9549 outer operation, which we return. */
9550 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9551 apply_distributive_law (tem
), other
);
9554 /* See if X is of the form (* (+ A B) C), and if so convert to
9555 (+ (* A C) (* B C)) and try to simplify.
9557 Most of the time, this results in no change. However, if some of
9558 the operands are the same or inverses of each other, simplifications
9561 For example, (and (ior A B) (not B)) can occur as the result of
9562 expanding a bit field assignment. When we apply the distributive
9563 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9564 which then simplifies to (and (A (not B))).
9566 Note that no checks happen on the validity of applying the inverse
9567 distributive law. This is pointless since we can do it in the
9568 few places where this routine is called.
9570 N is the index of the term that is decomposed (the arithmetic operation,
9571 i.e. (+ A B) in the first example above). !N is the index of the term that
9572 is distributed, i.e. of C in the first example above. */
9574 distribute_and_simplify_rtx (rtx x
, int n
)
9577 enum rtx_code outer_code
, inner_code
;
9578 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9580 /* Distributivity is not true for floating point as it can change the
9581 value. So we don't do it unless -funsafe-math-optimizations. */
9582 if (FLOAT_MODE_P (GET_MODE (x
))
9583 && ! flag_unsafe_math_optimizations
)
9586 decomposed
= XEXP (x
, n
);
9587 if (!ARITHMETIC_P (decomposed
))
9590 mode
= GET_MODE (x
);
9591 outer_code
= GET_CODE (x
);
9592 distributed
= XEXP (x
, !n
);
9594 inner_code
= GET_CODE (decomposed
);
9595 inner_op0
= XEXP (decomposed
, 0);
9596 inner_op1
= XEXP (decomposed
, 1);
9598 /* Special case (and (xor B C) (not A)), which is equivalent to
9599 (xor (ior A B) (ior A C)) */
9600 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9602 distributed
= XEXP (distributed
, 0);
9608 /* Distribute the second term. */
9609 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9610 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9614 /* Distribute the first term. */
9615 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9616 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9619 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9621 if (GET_CODE (tmp
) != outer_code
9622 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9623 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9629 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9630 in MODE. Return an equivalent form, if different from (and VAROP
9631 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9634 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9635 unsigned HOST_WIDE_INT constop
)
9637 unsigned HOST_WIDE_INT nonzero
;
9638 unsigned HOST_WIDE_INT orig_constop
;
9643 orig_constop
= constop
;
9644 if (GET_CODE (varop
) == CLOBBER
)
9647 /* Simplify VAROP knowing that we will be only looking at some of the
9650 Note by passing in CONSTOP, we guarantee that the bits not set in
9651 CONSTOP are not significant and will never be examined. We must
9652 ensure that is the case by explicitly masking out those bits
9653 before returning. */
9654 varop
= force_to_mode (varop
, mode
, constop
, 0);
9656 /* If VAROP is a CLOBBER, we will fail so return it. */
9657 if (GET_CODE (varop
) == CLOBBER
)
9660 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9661 to VAROP and return the new constant. */
9662 if (CONST_INT_P (varop
))
9663 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9665 /* See what bits may be nonzero in VAROP. Unlike the general case of
9666 a call to nonzero_bits, here we don't care about bits outside
9669 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9671 /* Turn off all bits in the constant that are known to already be zero.
9672 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9673 which is tested below. */
9677 /* If we don't have any bits left, return zero. */
9681 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9682 a power of two, we can replace this with an ASHIFT. */
9683 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9684 && (i
= exact_log2 (constop
)) >= 0)
9685 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9687 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9688 or XOR, then try to apply the distributive law. This may eliminate
9689 operations if either branch can be simplified because of the AND.
9690 It may also make some cases more complex, but those cases probably
9691 won't match a pattern either with or without this. */
9693 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9697 apply_distributive_law
9698 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9699 simplify_and_const_int (NULL_RTX
,
9703 simplify_and_const_int (NULL_RTX
,
9708 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9709 the AND and see if one of the operands simplifies to zero. If so, we
9710 may eliminate it. */
9712 if (GET_CODE (varop
) == PLUS
9713 && exact_log2 (constop
+ 1) >= 0)
9717 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9718 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9719 if (o0
== const0_rtx
)
9721 if (o1
== const0_rtx
)
9725 /* Make a SUBREG if necessary. If we can't make it, fail. */
9726 varop
= gen_lowpart (mode
, varop
);
9727 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9730 /* If we are only masking insignificant bits, return VAROP. */
9731 if (constop
== nonzero
)
9734 if (varop
== orig_varop
&& constop
== orig_constop
)
9737 /* Otherwise, return an AND. */
9738 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9742 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9745 Return an equivalent form, if different from X. Otherwise, return X. If
9746 X is zero, we are to always construct the equivalent form. */
9749 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9750 unsigned HOST_WIDE_INT constop
)
9752 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9757 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9758 gen_int_mode (constop
, mode
));
9759 if (GET_MODE (x
) != mode
)
9760 x
= gen_lowpart (mode
, x
);
9764 /* Given a REG, X, compute which bits in X can be nonzero.
9765 We don't care about bits outside of those defined in MODE.
9767 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9768 a shift, AND, or zero_extract, we can do better. */
9771 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9772 const_rtx known_x ATTRIBUTE_UNUSED
,
9773 machine_mode known_mode ATTRIBUTE_UNUSED
,
9774 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9775 unsigned HOST_WIDE_INT
*nonzero
)
9780 /* If X is a register whose nonzero bits value is current, use it.
9781 Otherwise, if X is a register whose value we can find, use that
9782 value. Otherwise, use the previously-computed global nonzero bits
9783 for this register. */
9785 rsp
= ®_stat
[REGNO (x
)];
9786 if (rsp
->last_set_value
!= 0
9787 && (rsp
->last_set_mode
== mode
9788 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9789 && GET_MODE_CLASS (mode
) == MODE_INT
))
9790 && ((rsp
->last_set_label
>= label_tick_ebb_start
9791 && rsp
->last_set_label
< label_tick
)
9792 || (rsp
->last_set_label
== label_tick
9793 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9794 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9795 && REGNO (x
) < reg_n_sets_max
9796 && REG_N_SETS (REGNO (x
)) == 1
9798 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9801 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9803 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9804 /* We don't know anything about the upper bits. */
9805 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9811 tem
= get_last_value (x
);
9815 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
9816 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
9817 GET_MODE_PRECISION (mode
));
9821 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9823 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9825 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9826 /* We don't know anything about the upper bits. */
9827 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9835 /* Return the number of bits at the high-order end of X that are known to
9836 be equal to the sign bit. X will be used in mode MODE; if MODE is
9837 VOIDmode, X will be used in its own mode. The returned value will always
9838 be between 1 and the number of bits in MODE. */
9841 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
9842 const_rtx known_x ATTRIBUTE_UNUSED
,
9843 machine_mode known_mode
9845 unsigned int known_ret ATTRIBUTE_UNUSED
,
9846 unsigned int *result
)
9851 rsp
= ®_stat
[REGNO (x
)];
9852 if (rsp
->last_set_value
!= 0
9853 && rsp
->last_set_mode
== mode
9854 && ((rsp
->last_set_label
>= label_tick_ebb_start
9855 && rsp
->last_set_label
< label_tick
)
9856 || (rsp
->last_set_label
== label_tick
9857 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9858 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9859 && REGNO (x
) < reg_n_sets_max
9860 && REG_N_SETS (REGNO (x
)) == 1
9862 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9865 *result
= rsp
->last_set_sign_bit_copies
;
9869 tem
= get_last_value (x
);
9873 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9874 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9875 *result
= rsp
->sign_bit_copies
;
9880 /* Return the number of "extended" bits there are in X, when interpreted
9881 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9882 unsigned quantities, this is the number of high-order zero bits.
9883 For signed quantities, this is the number of copies of the sign bit
9884 minus 1. In both case, this function returns the number of "spare"
9885 bits. For example, if two quantities for which this function returns
9886 at least 1 are added, the addition is known not to overflow.
9888 This function will always return 0 unless called during combine, which
9889 implies that it must be called from a define_split. */
9892 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
9894 if (nonzero_sign_valid
== 0)
9898 ? (HWI_COMPUTABLE_MODE_P (mode
)
9899 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9900 - floor_log2 (nonzero_bits (x
, mode
)))
9902 : num_sign_bit_copies (x
, mode
) - 1);
9905 /* This function is called from `simplify_shift_const' to merge two
9906 outer operations. Specifically, we have already found that we need
9907 to perform operation *POP0 with constant *PCONST0 at the outermost
9908 position. We would now like to also perform OP1 with constant CONST1
9909 (with *POP0 being done last).
9911 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9912 the resulting operation. *PCOMP_P is set to 1 if we would need to
9913 complement the innermost operand, otherwise it is unchanged.
9915 MODE is the mode in which the operation will be done. No bits outside
9916 the width of this mode matter. It is assumed that the width of this mode
9917 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9919 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9920 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9921 result is simply *PCONST0.
9923 If the resulting operation cannot be expressed as one operation, we
9924 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9927 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
9929 enum rtx_code op0
= *pop0
;
9930 HOST_WIDE_INT const0
= *pconst0
;
9932 const0
&= GET_MODE_MASK (mode
);
9933 const1
&= GET_MODE_MASK (mode
);
9935 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9939 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9942 if (op1
== UNKNOWN
|| op0
== SET
)
9945 else if (op0
== UNKNOWN
)
9946 op0
= op1
, const0
= const1
;
9948 else if (op0
== op1
)
9972 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9973 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9976 /* If the two constants aren't the same, we can't do anything. The
9977 remaining six cases can all be done. */
9978 else if (const0
!= const1
)
9986 /* (a & b) | b == b */
9988 else /* op1 == XOR */
9989 /* (a ^ b) | b == a | b */
9995 /* (a & b) ^ b == (~a) & b */
9996 op0
= AND
, *pcomp_p
= 1;
9997 else /* op1 == IOR */
9998 /* (a | b) ^ b == a & ~b */
9999 op0
= AND
, const0
= ~const0
;
10004 /* (a | b) & b == b */
10006 else /* op1 == XOR */
10007 /* (a ^ b) & b) == (~a) & b */
10014 /* Check for NO-OP cases. */
10015 const0
&= GET_MODE_MASK (mode
);
10017 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10019 else if (const0
== 0 && op0
== AND
)
10021 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10027 /* ??? Slightly redundant with the above mask, but not entirely.
10028 Moving this above means we'd have to sign-extend the mode mask
10029 for the final test. */
10030 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10031 *pconst0
= trunc_int_for_mode (const0
, mode
);
10036 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10037 the shift in. The original shift operation CODE is performed on OP in
10038 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10039 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10040 result of the shift is subject to operation OUTER_CODE with operand
10043 static machine_mode
10044 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10045 machine_mode orig_mode
, machine_mode mode
,
10046 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10048 if (orig_mode
== mode
)
10050 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10052 /* In general we can't perform in wider mode for right shift and rotate. */
10056 /* We can still widen if the bits brought in from the left are identical
10057 to the sign bit of ORIG_MODE. */
10058 if (num_sign_bit_copies (op
, mode
)
10059 > (unsigned) (GET_MODE_PRECISION (mode
)
10060 - GET_MODE_PRECISION (orig_mode
)))
10065 /* Similarly here but with zero bits. */
10066 if (HWI_COMPUTABLE_MODE_P (mode
)
10067 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10070 /* We can also widen if the bits brought in will be masked off. This
10071 operation is performed in ORIG_MODE. */
10072 if (outer_code
== AND
)
10074 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10077 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10086 gcc_unreachable ();
10093 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10094 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10095 if we cannot simplify it. Otherwise, return a simplified value.
10097 The shift is normally computed in the widest mode we find in VAROP, as
10098 long as it isn't a different number of words than RESULT_MODE. Exceptions
10099 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10102 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10103 rtx varop
, int orig_count
)
10105 enum rtx_code orig_code
= code
;
10106 rtx orig_varop
= varop
;
10108 machine_mode mode
= result_mode
;
10109 machine_mode shift_mode
, tmode
;
10110 unsigned int mode_words
10111 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10112 /* We form (outer_op (code varop count) (outer_const)). */
10113 enum rtx_code outer_op
= UNKNOWN
;
10114 HOST_WIDE_INT outer_const
= 0;
10115 int complement_p
= 0;
10118 /* Make sure and truncate the "natural" shift on the way in. We don't
10119 want to do this inside the loop as it makes it more difficult to
10121 if (SHIFT_COUNT_TRUNCATED
)
10122 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
10124 /* If we were given an invalid count, don't do anything except exactly
10125 what was requested. */
10127 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
10130 count
= orig_count
;
10132 /* Unless one of the branches of the `if' in this loop does a `continue',
10133 we will `break' the loop after the `if'. */
10137 /* If we have an operand of (clobber (const_int 0)), fail. */
10138 if (GET_CODE (varop
) == CLOBBER
)
10141 /* Convert ROTATERT to ROTATE. */
10142 if (code
== ROTATERT
)
10144 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
10146 if (VECTOR_MODE_P (result_mode
))
10147 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
10149 count
= bitsize
- count
;
10152 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10153 mode
, outer_op
, outer_const
);
10155 /* Handle cases where the count is greater than the size of the mode
10156 minus 1. For ASHIFT, use the size minus one as the count (this can
10157 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10158 take the count modulo the size. For other shifts, the result is
10161 Since these shifts are being produced by the compiler by combining
10162 multiple operations, each of which are defined, we know what the
10163 result is supposed to be. */
10165 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
10167 if (code
== ASHIFTRT
)
10168 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10169 else if (code
== ROTATE
|| code
== ROTATERT
)
10170 count
%= GET_MODE_PRECISION (shift_mode
);
10173 /* We can't simply return zero because there may be an
10175 varop
= const0_rtx
;
10181 /* If we discovered we had to complement VAROP, leave. Making a NOT
10182 here would cause an infinite loop. */
10186 /* An arithmetic right shift of a quantity known to be -1 or 0
10188 if (code
== ASHIFTRT
10189 && (num_sign_bit_copies (varop
, shift_mode
)
10190 == GET_MODE_PRECISION (shift_mode
)))
10196 /* If we are doing an arithmetic right shift and discarding all but
10197 the sign bit copies, this is equivalent to doing a shift by the
10198 bitsize minus one. Convert it into that shift because it will often
10199 allow other simplifications. */
10201 if (code
== ASHIFTRT
10202 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
10203 >= GET_MODE_PRECISION (shift_mode
)))
10204 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10206 /* We simplify the tests below and elsewhere by converting
10207 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10208 `make_compound_operation' will convert it to an ASHIFTRT for
10209 those machines (such as VAX) that don't have an LSHIFTRT. */
10210 if (code
== ASHIFTRT
10211 && val_signbit_known_clear_p (shift_mode
,
10212 nonzero_bits (varop
, shift_mode
)))
10215 if (((code
== LSHIFTRT
10216 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10217 && !(nonzero_bits (varop
, shift_mode
) >> count
))
10219 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10220 && !((nonzero_bits (varop
, shift_mode
) << count
)
10221 & GET_MODE_MASK (shift_mode
))))
10222 && !side_effects_p (varop
))
10223 varop
= const0_rtx
;
10225 switch (GET_CODE (varop
))
10231 new_rtx
= expand_compound_operation (varop
);
10232 if (new_rtx
!= varop
)
10240 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10241 minus the width of a smaller mode, we can do this with a
10242 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10243 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10244 && ! mode_dependent_address_p (XEXP (varop
, 0),
10245 MEM_ADDR_SPACE (varop
))
10246 && ! MEM_VOLATILE_P (varop
)
10247 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10248 MODE_INT
, 1)) != BLKmode
)
10250 new_rtx
= adjust_address_nv (varop
, tmode
,
10251 BYTES_BIG_ENDIAN
? 0
10252 : count
/ BITS_PER_UNIT
);
10254 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10255 : ZERO_EXTEND
, mode
, new_rtx
);
10262 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10263 the same number of words as what we've seen so far. Then store
10264 the widest mode in MODE. */
10265 if (subreg_lowpart_p (varop
)
10266 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10267 > GET_MODE_SIZE (GET_MODE (varop
)))
10268 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10269 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10271 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10272 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10274 varop
= SUBREG_REG (varop
);
10275 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10276 mode
= GET_MODE (varop
);
10282 /* Some machines use MULT instead of ASHIFT because MULT
10283 is cheaper. But it is still better on those machines to
10284 merge two shifts into one. */
10285 if (CONST_INT_P (XEXP (varop
, 1))
10286 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10289 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10291 GEN_INT (exact_log2 (
10292 UINTVAL (XEXP (varop
, 1)))));
10298 /* Similar, for when divides are cheaper. */
10299 if (CONST_INT_P (XEXP (varop
, 1))
10300 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10303 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10305 GEN_INT (exact_log2 (
10306 UINTVAL (XEXP (varop
, 1)))));
10312 /* If we are extracting just the sign bit of an arithmetic
10313 right shift, that shift is not needed. However, the sign
10314 bit of a wider mode may be different from what would be
10315 interpreted as the sign bit in a narrower mode, so, if
10316 the result is narrower, don't discard the shift. */
10317 if (code
== LSHIFTRT
10318 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10319 && (GET_MODE_BITSIZE (result_mode
)
10320 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10322 varop
= XEXP (varop
, 0);
10326 /* ... fall through ... */
10331 /* Here we have two nested shifts. The result is usually the
10332 AND of a new shift with a mask. We compute the result below. */
10333 if (CONST_INT_P (XEXP (varop
, 1))
10334 && INTVAL (XEXP (varop
, 1)) >= 0
10335 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10336 && HWI_COMPUTABLE_MODE_P (result_mode
)
10337 && HWI_COMPUTABLE_MODE_P (mode
)
10338 && !VECTOR_MODE_P (result_mode
))
10340 enum rtx_code first_code
= GET_CODE (varop
);
10341 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10342 unsigned HOST_WIDE_INT mask
;
10345 /* We have one common special case. We can't do any merging if
10346 the inner code is an ASHIFTRT of a smaller mode. However, if
10347 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10348 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10349 we can convert it to
10350 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10351 This simplifies certain SIGN_EXTEND operations. */
10352 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10353 && count
== (GET_MODE_PRECISION (result_mode
)
10354 - GET_MODE_PRECISION (GET_MODE (varop
))))
10356 /* C3 has the low-order C1 bits zero. */
10358 mask
= GET_MODE_MASK (mode
)
10359 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
10361 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10362 XEXP (varop
, 0), mask
);
10363 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10365 count
= first_count
;
10370 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10371 than C1 high-order bits equal to the sign bit, we can convert
10372 this to either an ASHIFT or an ASHIFTRT depending on the
10375 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10377 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10378 && GET_MODE (varop
) == shift_mode
10379 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10382 varop
= XEXP (varop
, 0);
10383 count
-= first_count
;
10393 /* There are some cases we can't do. If CODE is ASHIFTRT,
10394 we can only do this if FIRST_CODE is also ASHIFTRT.
10396 We can't do the case when CODE is ROTATE and FIRST_CODE is
10399 If the mode of this shift is not the mode of the outer shift,
10400 we can't do this if either shift is a right shift or ROTATE.
10402 Finally, we can't do any of these if the mode is too wide
10403 unless the codes are the same.
10405 Handle the case where the shift codes are the same
10408 if (code
== first_code
)
10410 if (GET_MODE (varop
) != result_mode
10411 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10412 || code
== ROTATE
))
10415 count
+= first_count
;
10416 varop
= XEXP (varop
, 0);
10420 if (code
== ASHIFTRT
10421 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10422 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10423 || (GET_MODE (varop
) != result_mode
10424 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10425 || first_code
== ROTATE
10426 || code
== ROTATE
)))
10429 /* To compute the mask to apply after the shift, shift the
10430 nonzero bits of the inner shift the same way the
10431 outer shift will. */
10433 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10437 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10440 /* Give up if we can't compute an outer operation to use. */
10442 || !CONST_INT_P (mask_rtx
)
10443 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10445 result_mode
, &complement_p
))
10448 /* If the shifts are in the same direction, we add the
10449 counts. Otherwise, we subtract them. */
10450 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10451 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10452 count
+= first_count
;
10454 count
-= first_count
;
10456 /* If COUNT is positive, the new shift is usually CODE,
10457 except for the two exceptions below, in which case it is
10458 FIRST_CODE. If the count is negative, FIRST_CODE should
10461 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10462 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10464 else if (count
< 0)
10465 code
= first_code
, count
= -count
;
10467 varop
= XEXP (varop
, 0);
10471 /* If we have (A << B << C) for any shift, we can convert this to
10472 (A << C << B). This wins if A is a constant. Only try this if
10473 B is not a constant. */
10475 else if (GET_CODE (varop
) == code
10476 && CONST_INT_P (XEXP (varop
, 0))
10477 && !CONST_INT_P (XEXP (varop
, 1)))
10479 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10482 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10489 if (VECTOR_MODE_P (mode
))
10492 /* Make this fit the case below. */
10493 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10499 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10500 with C the size of VAROP - 1 and the shift is logical if
10501 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10502 we have an (le X 0) operation. If we have an arithmetic shift
10503 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10504 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10506 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10507 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10508 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10509 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10510 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10511 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10514 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10517 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10518 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10523 /* If we have (shift (logical)), move the logical to the outside
10524 to allow it to possibly combine with another logical and the
10525 shift to combine with another shift. This also canonicalizes to
10526 what a ZERO_EXTRACT looks like. Also, some machines have
10527 (and (shift)) insns. */
10529 if (CONST_INT_P (XEXP (varop
, 1))
10530 /* We can't do this if we have (ashiftrt (xor)) and the
10531 constant has its sign bit set in shift_mode with shift_mode
10532 wider than result_mode. */
10533 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10534 && result_mode
!= shift_mode
10535 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10537 && (new_rtx
= simplify_const_binary_operation
10538 (code
, result_mode
,
10539 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10540 GEN_INT (count
))) != 0
10541 && CONST_INT_P (new_rtx
)
10542 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10543 INTVAL (new_rtx
), result_mode
, &complement_p
))
10545 varop
= XEXP (varop
, 0);
10549 /* If we can't do that, try to simplify the shift in each arm of the
10550 logical expression, make a new logical expression, and apply
10551 the inverse distributive law. This also can't be done for
10552 (ashiftrt (xor)) where we've widened the shift and the constant
10553 changes the sign bit. */
10554 if (CONST_INT_P (XEXP (varop
, 1))
10555 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10556 && result_mode
!= shift_mode
10557 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10560 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10561 XEXP (varop
, 0), count
);
10562 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10563 XEXP (varop
, 1), count
);
10565 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10567 varop
= apply_distributive_law (varop
);
10575 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10576 says that the sign bit can be tested, FOO has mode MODE, C is
10577 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10578 that may be nonzero. */
10579 if (code
== LSHIFTRT
10580 && XEXP (varop
, 1) == const0_rtx
10581 && GET_MODE (XEXP (varop
, 0)) == result_mode
10582 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10583 && HWI_COMPUTABLE_MODE_P (result_mode
)
10584 && STORE_FLAG_VALUE
== -1
10585 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10586 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10589 varop
= XEXP (varop
, 0);
10596 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10597 than the number of bits in the mode is equivalent to A. */
10598 if (code
== LSHIFTRT
10599 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10600 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10602 varop
= XEXP (varop
, 0);
10607 /* NEG commutes with ASHIFT since it is multiplication. Move the
10608 NEG outside to allow shifts to combine. */
10610 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10613 varop
= XEXP (varop
, 0);
10619 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10620 is one less than the number of bits in the mode is
10621 equivalent to (xor A 1). */
10622 if (code
== LSHIFTRT
10623 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10624 && XEXP (varop
, 1) == constm1_rtx
10625 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10626 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10630 varop
= XEXP (varop
, 0);
10634 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10635 that might be nonzero in BAR are those being shifted out and those
10636 bits are known zero in FOO, we can replace the PLUS with FOO.
10637 Similarly in the other operand order. This code occurs when
10638 we are computing the size of a variable-size array. */
10640 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10641 && count
< HOST_BITS_PER_WIDE_INT
10642 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10643 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10644 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10646 varop
= XEXP (varop
, 0);
10649 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10650 && count
< HOST_BITS_PER_WIDE_INT
10651 && HWI_COMPUTABLE_MODE_P (result_mode
)
10652 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10654 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10655 & nonzero_bits (XEXP (varop
, 1),
10658 varop
= XEXP (varop
, 1);
10662 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10664 && CONST_INT_P (XEXP (varop
, 1))
10665 && (new_rtx
= simplify_const_binary_operation
10666 (ASHIFT
, result_mode
,
10667 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10668 GEN_INT (count
))) != 0
10669 && CONST_INT_P (new_rtx
)
10670 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10671 INTVAL (new_rtx
), result_mode
, &complement_p
))
10673 varop
= XEXP (varop
, 0);
10677 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10678 signbit', and attempt to change the PLUS to an XOR and move it to
10679 the outer operation as is done above in the AND/IOR/XOR case
10680 leg for shift(logical). See details in logical handling above
10681 for reasoning in doing so. */
10682 if (code
== LSHIFTRT
10683 && CONST_INT_P (XEXP (varop
, 1))
10684 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10685 && (new_rtx
= simplify_const_binary_operation
10686 (code
, result_mode
,
10687 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10688 GEN_INT (count
))) != 0
10689 && CONST_INT_P (new_rtx
)
10690 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10691 INTVAL (new_rtx
), result_mode
, &complement_p
))
10693 varop
= XEXP (varop
, 0);
10700 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10701 with C the size of VAROP - 1 and the shift is logical if
10702 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10703 we have a (gt X 0) operation. If the shift is arithmetic with
10704 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10705 we have a (neg (gt X 0)) operation. */
10707 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10708 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10709 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10710 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10711 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10712 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10713 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10716 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10719 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10720 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10727 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10728 if the truncate does not affect the value. */
10729 if (code
== LSHIFTRT
10730 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10731 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10732 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10733 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10734 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10736 rtx varop_inner
= XEXP (varop
, 0);
10739 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10740 XEXP (varop_inner
, 0),
10742 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10743 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10756 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10757 outer_op
, outer_const
);
10759 /* We have now finished analyzing the shift. The result should be
10760 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10761 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10762 to the result of the shift. OUTER_CONST is the relevant constant,
10763 but we must turn off all bits turned off in the shift. */
10765 if (outer_op
== UNKNOWN
10766 && orig_code
== code
&& orig_count
== count
10767 && varop
== orig_varop
10768 && shift_mode
== GET_MODE (varop
))
10771 /* Make a SUBREG if necessary. If we can't make it, fail. */
10772 varop
= gen_lowpart (shift_mode
, varop
);
10773 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10776 /* If we have an outer operation and we just made a shift, it is
10777 possible that we could have simplified the shift were it not
10778 for the outer operation. So try to do the simplification
10781 if (outer_op
!= UNKNOWN
)
10782 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10787 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10789 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10790 turn off all the bits that the shift would have turned off. */
10791 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10792 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10793 GET_MODE_MASK (result_mode
) >> orig_count
);
10795 /* Do the remainder of the processing in RESULT_MODE. */
10796 x
= gen_lowpart_or_truncate (result_mode
, x
);
10798 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10801 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10803 if (outer_op
!= UNKNOWN
)
10805 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10806 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10807 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10809 if (outer_op
== AND
)
10810 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10811 else if (outer_op
== SET
)
10813 /* This means that we have determined that the result is
10814 equivalent to a constant. This should be rare. */
10815 if (!side_effects_p (x
))
10816 x
= GEN_INT (outer_const
);
10818 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10819 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10821 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10822 GEN_INT (outer_const
));
10828 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10829 The result of the shift is RESULT_MODE. If we cannot simplify it,
10830 return X or, if it is NULL, synthesize the expression with
10831 simplify_gen_binary. Otherwise, return a simplified value.
10833 The shift is normally computed in the widest mode we find in VAROP, as
10834 long as it isn't a different number of words than RESULT_MODE. Exceptions
10835 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10838 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
10839 rtx varop
, int count
)
10841 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10846 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10847 if (GET_MODE (x
) != result_mode
)
10848 x
= gen_lowpart (result_mode
, x
);
10853 /* A subroutine of recog_for_combine. See there for arguments and
10857 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10859 rtx pat
= *pnewpat
;
10860 rtx pat_without_clobbers
;
10861 int insn_code_number
;
10862 int num_clobbers_to_add
= 0;
10864 rtx notes
= NULL_RTX
;
10865 rtx old_notes
, old_pat
;
10868 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10869 we use to indicate that something didn't match. If we find such a
10870 thing, force rejection. */
10871 if (GET_CODE (pat
) == PARALLEL
)
10872 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10873 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10874 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10877 old_pat
= PATTERN (insn
);
10878 old_notes
= REG_NOTES (insn
);
10879 PATTERN (insn
) = pat
;
10880 REG_NOTES (insn
) = NULL_RTX
;
10882 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10883 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10885 if (insn_code_number
< 0)
10886 fputs ("Failed to match this instruction:\n", dump_file
);
10888 fputs ("Successfully matched this instruction:\n", dump_file
);
10889 print_rtl_single (dump_file
, pat
);
10892 /* If it isn't, there is the possibility that we previously had an insn
10893 that clobbered some register as a side effect, but the combined
10894 insn doesn't need to do that. So try once more without the clobbers
10895 unless this represents an ASM insn. */
10897 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10898 && GET_CODE (pat
) == PARALLEL
)
10902 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10903 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10906 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10910 SUBST_INT (XVECLEN (pat
, 0), pos
);
10913 pat
= XVECEXP (pat
, 0, 0);
10915 PATTERN (insn
) = pat
;
10916 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10917 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10919 if (insn_code_number
< 0)
10920 fputs ("Failed to match this instruction:\n", dump_file
);
10922 fputs ("Successfully matched this instruction:\n", dump_file
);
10923 print_rtl_single (dump_file
, pat
);
10927 pat_without_clobbers
= pat
;
10929 PATTERN (insn
) = old_pat
;
10930 REG_NOTES (insn
) = old_notes
;
10932 /* Recognize all noop sets, these will be killed by followup pass. */
10933 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10934 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10936 /* If we had any clobbers to add, make a new pattern than contains
10937 them. Then check to make sure that all of them are dead. */
10938 if (num_clobbers_to_add
)
10940 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10941 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10942 ? (XVECLEN (pat
, 0)
10943 + num_clobbers_to_add
)
10944 : num_clobbers_to_add
+ 1));
10946 if (GET_CODE (pat
) == PARALLEL
)
10947 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10948 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10950 XVECEXP (newpat
, 0, 0) = pat
;
10952 add_clobbers (newpat
, insn_code_number
);
10954 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10955 i
< XVECLEN (newpat
, 0); i
++)
10957 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10958 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10960 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10962 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10963 notes
= alloc_reg_note (REG_UNUSED
,
10964 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10970 if (insn_code_number
>= 0
10971 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10973 old_pat
= PATTERN (insn
);
10974 old_notes
= REG_NOTES (insn
);
10975 old_icode
= INSN_CODE (insn
);
10976 PATTERN (insn
) = pat
;
10977 REG_NOTES (insn
) = notes
;
10979 /* Allow targets to reject combined insn. */
10980 if (!targetm
.legitimate_combined_insn (insn
))
10982 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10983 fputs ("Instruction not appropriate for target.",
10986 /* Callers expect recog_for_combine to strip
10987 clobbers from the pattern on failure. */
10988 pat
= pat_without_clobbers
;
10991 insn_code_number
= -1;
10994 PATTERN (insn
) = old_pat
;
10995 REG_NOTES (insn
) = old_notes
;
10996 INSN_CODE (insn
) = old_icode
;
11002 return insn_code_number
;
11005 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11006 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11007 Return whether anything was so changed. */
11010 change_zero_ext (rtx
*src
)
11012 bool changed
= false;
11014 subrtx_ptr_iterator::array_type array
;
11015 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11018 machine_mode mode
= GET_MODE (x
);
11021 if (GET_CODE (x
) == ZERO_EXTRACT
11022 && CONST_INT_P (XEXP (x
, 1))
11023 && CONST_INT_P (XEXP (x
, 2))
11024 && GET_MODE (XEXP (x
, 0)) == mode
)
11026 size
= INTVAL (XEXP (x
, 1));
11028 int start
= INTVAL (XEXP (x
, 2));
11029 if (BITS_BIG_ENDIAN
)
11030 start
= GET_MODE_PRECISION (mode
) - size
- start
;
11032 x
= gen_rtx_LSHIFTRT (mode
, XEXP (x
, 0), GEN_INT (start
));
11034 else if (GET_CODE (x
) == ZERO_EXTEND
11035 && GET_CODE (XEXP (x
, 0)) == SUBREG
11036 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
11037 && subreg_lowpart_p (XEXP (x
, 0)))
11039 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11040 x
= SUBREG_REG (XEXP (x
, 0));
11045 unsigned HOST_WIDE_INT mask
= 1;
11049 x
= gen_rtx_AND (mode
, x
, GEN_INT (mask
));
11058 /* Like recog, but we receive the address of a pointer to a new pattern.
11059 We try to match the rtx that the pointer points to.
11060 If that fails, we may try to modify or replace the pattern,
11061 storing the replacement into the same pointer object.
11063 Modifications include deletion or addition of CLOBBERs. If the
11064 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11065 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11066 (and undo if that fails).
11068 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11069 the CLOBBERs are placed.
11071 The value is the final insn code from the pattern ultimately matched,
11075 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11077 rtx pat
= PATTERN (insn
);
11078 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11079 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11080 return insn_code_number
;
11082 void *marker
= get_undo_marker ();
11083 bool changed
= false;
11085 if (GET_CODE (pat
) == SET
)
11086 changed
= change_zero_ext (&SET_SRC (pat
));
11087 else if (GET_CODE (pat
) == PARALLEL
)
11090 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11092 rtx set
= XVECEXP (pat
, 0, i
);
11093 if (GET_CODE (set
) == SET
)
11094 changed
|= change_zero_ext (&SET_SRC (set
));
11100 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11102 if (insn_code_number
< 0)
11103 undo_to_marker (marker
);
11106 return insn_code_number
;
11109 /* Like gen_lowpart_general but for use by combine. In combine it
11110 is not possible to create any new pseudoregs. However, it is
11111 safe to create invalid memory addresses, because combine will
11112 try to recognize them and all they will do is make the combine
11115 If for some reason this cannot do its job, an rtx
11116 (clobber (const_int 0)) is returned.
11117 An insn containing that will not be recognized. */
11120 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11122 machine_mode imode
= GET_MODE (x
);
11123 unsigned int osize
= GET_MODE_SIZE (omode
);
11124 unsigned int isize
= GET_MODE_SIZE (imode
);
11127 if (omode
== imode
)
11130 /* We can only support MODE being wider than a word if X is a
11131 constant integer or has a mode the same size. */
11132 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11133 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11136 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11137 won't know what to do. So we will strip off the SUBREG here and
11138 process normally. */
11139 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11141 x
= SUBREG_REG (x
);
11143 /* For use in case we fall down into the address adjustments
11144 further below, we need to adjust the known mode and size of
11145 x; imode and isize, since we just adjusted x. */
11146 imode
= GET_MODE (x
);
11148 if (imode
== omode
)
11151 isize
= GET_MODE_SIZE (imode
);
11154 result
= gen_lowpart_common (omode
, x
);
11163 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11165 if (MEM_VOLATILE_P (x
)
11166 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11169 /* If we want to refer to something bigger than the original memref,
11170 generate a paradoxical subreg instead. That will force a reload
11171 of the original memref X. */
11173 return gen_rtx_SUBREG (omode
, x
, 0);
11175 if (WORDS_BIG_ENDIAN
)
11176 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11178 /* Adjust the address so that the address-after-the-data is
11180 if (BYTES_BIG_ENDIAN
)
11181 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11183 return adjust_address_nv (x
, omode
, offset
);
11186 /* If X is a comparison operator, rewrite it in a new mode. This
11187 probably won't match, but may allow further simplifications. */
11188 else if (COMPARISON_P (x
))
11189 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11191 /* If we couldn't simplify X any other way, just enclose it in a
11192 SUBREG. Normally, this SUBREG won't match, but some patterns may
11193 include an explicit SUBREG or we may simplify it further in combine. */
11198 if (imode
== VOIDmode
)
11200 imode
= int_mode_for_mode (omode
);
11201 x
= gen_lowpart_common (imode
, x
);
11205 res
= lowpart_subreg (omode
, x
, imode
);
11211 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11214 /* Try to simplify a comparison between OP0 and a constant OP1,
11215 where CODE is the comparison code that will be tested, into a
11216 (CODE OP0 const0_rtx) form.
11218 The result is a possibly different comparison code to use.
11219 *POP1 may be updated. */
11221 static enum rtx_code
11222 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11223 rtx op0
, rtx
*pop1
)
11225 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11226 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11228 /* Get the constant we are comparing against and turn off all bits
11229 not on in our mode. */
11230 if (mode
!= VOIDmode
)
11231 const_op
= trunc_int_for_mode (const_op
, mode
);
11233 /* If we are comparing against a constant power of two and the value
11234 being compared can only have that single bit nonzero (e.g., it was
11235 `and'ed with that bit), we can replace this with a comparison
11238 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11239 || code
== LT
|| code
== LTU
)
11240 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11241 && exact_log2 (const_op
& GET_MODE_MASK (mode
)) >= 0
11242 && (nonzero_bits (op0
, mode
)
11243 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11245 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11249 /* Similarly, if we are comparing a value known to be either -1 or
11250 0 with -1, change it to the opposite comparison against zero. */
11252 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11253 || code
== GEU
|| code
== LTU
)
11254 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11256 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11260 /* Do some canonicalizations based on the comparison code. We prefer
11261 comparisons against zero and then prefer equality comparisons.
11262 If we can reduce the size of a constant, we will do that too. */
11266 /* < C is equivalent to <= (C - 1) */
11271 /* ... fall through to LE case below. */
11277 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11284 /* If we are doing a <= 0 comparison on a value known to have
11285 a zero sign bit, we can replace this with == 0. */
11286 else if (const_op
== 0
11287 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11288 && (nonzero_bits (op0
, mode
)
11289 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11295 /* >= C is equivalent to > (C - 1). */
11300 /* ... fall through to GT below. */
11306 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11313 /* If we are doing a > 0 comparison on a value known to have
11314 a zero sign bit, we can replace this with != 0. */
11315 else if (const_op
== 0
11316 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11317 && (nonzero_bits (op0
, mode
)
11318 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11324 /* < C is equivalent to <= (C - 1). */
11329 /* ... fall through ... */
11331 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11332 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11333 && (unsigned HOST_WIDE_INT
) const_op
11334 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11344 /* unsigned <= 0 is equivalent to == 0 */
11347 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11348 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11349 && (unsigned HOST_WIDE_INT
) const_op
11350 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11358 /* >= C is equivalent to > (C - 1). */
11363 /* ... fall through ... */
11366 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11367 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11368 && (unsigned HOST_WIDE_INT
) const_op
11369 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
11379 /* unsigned > 0 is equivalent to != 0 */
11382 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11383 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11384 && (unsigned HOST_WIDE_INT
) const_op
11385 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
11396 *pop1
= GEN_INT (const_op
);
11400 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11401 comparison code that will be tested.
11403 The result is a possibly different comparison code to use. *POP0 and
11404 *POP1 may be updated.
11406 It is possible that we might detect that a comparison is either always
11407 true or always false. However, we do not perform general constant
11408 folding in combine, so this knowledge isn't useful. Such tautologies
11409 should have been detected earlier. Hence we ignore all such cases. */
11411 static enum rtx_code
11412 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11418 machine_mode mode
, tmode
;
11420 /* Try a few ways of applying the same transformation to both operands. */
11423 #if !WORD_REGISTER_OPERATIONS
11424 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11425 so check specially. */
11426 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11427 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11428 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11429 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11430 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11431 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11432 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11433 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11434 && CONST_INT_P (XEXP (op0
, 1))
11435 && XEXP (op0
, 1) == XEXP (op1
, 1)
11436 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11437 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11438 && (INTVAL (XEXP (op0
, 1))
11439 == (GET_MODE_PRECISION (GET_MODE (op0
))
11440 - (GET_MODE_PRECISION
11441 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11443 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11444 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11448 /* If both operands are the same constant shift, see if we can ignore the
11449 shift. We can if the shift is a rotate or if the bits shifted out of
11450 this shift are known to be zero for both inputs and if the type of
11451 comparison is compatible with the shift. */
11452 if (GET_CODE (op0
) == GET_CODE (op1
)
11453 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11454 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11455 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11456 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11457 || (GET_CODE (op0
) == ASHIFTRT
11458 && (code
!= GTU
&& code
!= LTU
11459 && code
!= GEU
&& code
!= LEU
)))
11460 && CONST_INT_P (XEXP (op0
, 1))
11461 && INTVAL (XEXP (op0
, 1)) >= 0
11462 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11463 && XEXP (op0
, 1) == XEXP (op1
, 1))
11465 machine_mode mode
= GET_MODE (op0
);
11466 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11467 int shift_count
= INTVAL (XEXP (op0
, 1));
11469 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11470 mask
&= (mask
>> shift_count
) << shift_count
;
11471 else if (GET_CODE (op0
) == ASHIFT
)
11472 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11474 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11475 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11476 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11481 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11482 SUBREGs are of the same mode, and, in both cases, the AND would
11483 be redundant if the comparison was done in the narrower mode,
11484 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11485 and the operand's possibly nonzero bits are 0xffffff01; in that case
11486 if we only care about QImode, we don't need the AND). This case
11487 occurs if the output mode of an scc insn is not SImode and
11488 STORE_FLAG_VALUE == 1 (e.g., the 386).
11490 Similarly, check for a case where the AND's are ZERO_EXTEND
11491 operations from some narrower mode even though a SUBREG is not
11494 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11495 && CONST_INT_P (XEXP (op0
, 1))
11496 && CONST_INT_P (XEXP (op1
, 1)))
11498 rtx inner_op0
= XEXP (op0
, 0);
11499 rtx inner_op1
= XEXP (op1
, 0);
11500 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11501 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11504 if (paradoxical_subreg_p (inner_op0
)
11505 && GET_CODE (inner_op1
) == SUBREG
11506 && (GET_MODE (SUBREG_REG (inner_op0
))
11507 == GET_MODE (SUBREG_REG (inner_op1
)))
11508 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11509 <= HOST_BITS_PER_WIDE_INT
)
11510 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11511 GET_MODE (SUBREG_REG (inner_op0
)))))
11512 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11513 GET_MODE (SUBREG_REG (inner_op1
))))))
11515 op0
= SUBREG_REG (inner_op0
);
11516 op1
= SUBREG_REG (inner_op1
);
11518 /* The resulting comparison is always unsigned since we masked
11519 off the original sign bit. */
11520 code
= unsigned_condition (code
);
11526 for (tmode
= GET_CLASS_NARROWEST_MODE
11527 (GET_MODE_CLASS (GET_MODE (op0
)));
11528 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11529 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11531 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
11532 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
11533 code
= unsigned_condition (code
);
11542 /* If both operands are NOT, we can strip off the outer operation
11543 and adjust the comparison code for swapped operands; similarly for
11544 NEG, except that this must be an equality comparison. */
11545 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11546 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11547 && (code
== EQ
|| code
== NE
)))
11548 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11554 /* If the first operand is a constant, swap the operands and adjust the
11555 comparison code appropriately, but don't do this if the second operand
11556 is already a constant integer. */
11557 if (swap_commutative_operands_p (op0
, op1
))
11559 std::swap (op0
, op1
);
11560 code
= swap_condition (code
);
11563 /* We now enter a loop during which we will try to simplify the comparison.
11564 For the most part, we only are concerned with comparisons with zero,
11565 but some things may really be comparisons with zero but not start
11566 out looking that way. */
11568 while (CONST_INT_P (op1
))
11570 machine_mode mode
= GET_MODE (op0
);
11571 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11572 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11573 int equality_comparison_p
;
11574 int sign_bit_comparison_p
;
11575 int unsigned_comparison_p
;
11576 HOST_WIDE_INT const_op
;
11578 /* We only want to handle integral modes. This catches VOIDmode,
11579 CCmode, and the floating-point modes. An exception is that we
11580 can handle VOIDmode if OP0 is a COMPARE or a comparison
11583 if (GET_MODE_CLASS (mode
) != MODE_INT
11584 && ! (mode
== VOIDmode
11585 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11588 /* Try to simplify the compare to constant, possibly changing the
11589 comparison op, and/or changing op1 to zero. */
11590 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11591 const_op
= INTVAL (op1
);
11593 /* Compute some predicates to simplify code below. */
11595 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11596 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11597 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11600 /* If this is a sign bit comparison and we can do arithmetic in
11601 MODE, say that we will only be needing the sign bit of OP0. */
11602 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11603 op0
= force_to_mode (op0
, mode
,
11604 (unsigned HOST_WIDE_INT
) 1
11605 << (GET_MODE_PRECISION (mode
) - 1),
11608 /* Now try cases based on the opcode of OP0. If none of the cases
11609 does a "continue", we exit this loop immediately after the
11612 switch (GET_CODE (op0
))
11615 /* If we are extracting a single bit from a variable position in
11616 a constant that has only a single bit set and are comparing it
11617 with zero, we can convert this into an equality comparison
11618 between the position and the location of the single bit. */
11619 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11620 have already reduced the shift count modulo the word size. */
11621 if (!SHIFT_COUNT_TRUNCATED
11622 && CONST_INT_P (XEXP (op0
, 0))
11623 && XEXP (op0
, 1) == const1_rtx
11624 && equality_comparison_p
&& const_op
== 0
11625 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11627 if (BITS_BIG_ENDIAN
)
11628 i
= BITS_PER_WORD
- 1 - i
;
11630 op0
= XEXP (op0
, 2);
11634 /* Result is nonzero iff shift count is equal to I. */
11635 code
= reverse_condition (code
);
11639 /* ... fall through ... */
11642 tem
= expand_compound_operation (op0
);
11651 /* If testing for equality, we can take the NOT of the constant. */
11652 if (equality_comparison_p
11653 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11655 op0
= XEXP (op0
, 0);
11660 /* If just looking at the sign bit, reverse the sense of the
11662 if (sign_bit_comparison_p
)
11664 op0
= XEXP (op0
, 0);
11665 code
= (code
== GE
? LT
: GE
);
11671 /* If testing for equality, we can take the NEG of the constant. */
11672 if (equality_comparison_p
11673 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11675 op0
= XEXP (op0
, 0);
11680 /* The remaining cases only apply to comparisons with zero. */
11684 /* When X is ABS or is known positive,
11685 (neg X) is < 0 if and only if X != 0. */
11687 if (sign_bit_comparison_p
11688 && (GET_CODE (XEXP (op0
, 0)) == ABS
11689 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11690 && (nonzero_bits (XEXP (op0
, 0), mode
)
11691 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11694 op0
= XEXP (op0
, 0);
11695 code
= (code
== LT
? NE
: EQ
);
11699 /* If we have NEG of something whose two high-order bits are the
11700 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11701 if (num_sign_bit_copies (op0
, mode
) >= 2)
11703 op0
= XEXP (op0
, 0);
11704 code
= swap_condition (code
);
11710 /* If we are testing equality and our count is a constant, we
11711 can perform the inverse operation on our RHS. */
11712 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11713 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11714 op1
, XEXP (op0
, 1))) != 0)
11716 op0
= XEXP (op0
, 0);
11721 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11722 a particular bit. Convert it to an AND of a constant of that
11723 bit. This will be converted into a ZERO_EXTRACT. */
11724 if (const_op
== 0 && sign_bit_comparison_p
11725 && CONST_INT_P (XEXP (op0
, 1))
11726 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11728 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11729 ((unsigned HOST_WIDE_INT
) 1
11731 - INTVAL (XEXP (op0
, 1)))));
11732 code
= (code
== LT
? NE
: EQ
);
11736 /* Fall through. */
11739 /* ABS is ignorable inside an equality comparison with zero. */
11740 if (const_op
== 0 && equality_comparison_p
)
11742 op0
= XEXP (op0
, 0);
11748 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11749 (compare FOO CONST) if CONST fits in FOO's mode and we
11750 are either testing inequality or have an unsigned
11751 comparison with ZERO_EXTEND or a signed comparison with
11752 SIGN_EXTEND. But don't do it if we don't have a compare
11753 insn of the given mode, since we'd have to revert it
11754 later on, and then we wouldn't know whether to sign- or
11756 mode
= GET_MODE (XEXP (op0
, 0));
11757 if (GET_MODE_CLASS (mode
) == MODE_INT
11758 && ! unsigned_comparison_p
11759 && HWI_COMPUTABLE_MODE_P (mode
)
11760 && trunc_int_for_mode (const_op
, mode
) == const_op
11761 && have_insn_for (COMPARE
, mode
))
11763 op0
= XEXP (op0
, 0);
11769 /* Check for the case where we are comparing A - C1 with C2, that is
11771 (subreg:MODE (plus (A) (-C1))) op (C2)
11773 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11774 comparison in the wider mode. One of the following two conditions
11775 must be true in order for this to be valid:
11777 1. The mode extension results in the same bit pattern being added
11778 on both sides and the comparison is equality or unsigned. As
11779 C2 has been truncated to fit in MODE, the pattern can only be
11782 2. The mode extension results in the sign bit being copied on
11785 The difficulty here is that we have predicates for A but not for
11786 (A - C1) so we need to check that C1 is within proper bounds so
11787 as to perturbate A as little as possible. */
11789 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11790 && subreg_lowpart_p (op0
)
11791 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11792 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11793 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11795 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11796 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11797 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11800 && (unsigned HOST_WIDE_INT
) c1
11801 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11802 && (equality_comparison_p
|| unsigned_comparison_p
)
11803 /* (A - C1) zero-extends if it is positive and sign-extends
11804 if it is negative, C2 both zero- and sign-extends. */
11805 && ((0 == (nonzero_bits (a
, inner_mode
)
11806 & ~GET_MODE_MASK (mode
))
11808 /* (A - C1) sign-extends if it is positive and 1-extends
11809 if it is negative, C2 both sign- and 1-extends. */
11810 || (num_sign_bit_copies (a
, inner_mode
)
11811 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11814 || ((unsigned HOST_WIDE_INT
) c1
11815 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11816 /* (A - C1) always sign-extends, like C2. */
11817 && num_sign_bit_copies (a
, inner_mode
)
11818 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11819 - (mode_width
- 1))))
11821 op0
= SUBREG_REG (op0
);
11826 /* If the inner mode is narrower and we are extracting the low part,
11827 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11828 if (subreg_lowpart_p (op0
)
11829 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11830 /* Fall through */ ;
11834 /* ... fall through ... */
11837 mode
= GET_MODE (XEXP (op0
, 0));
11838 if (GET_MODE_CLASS (mode
) == MODE_INT
11839 && (unsigned_comparison_p
|| equality_comparison_p
)
11840 && HWI_COMPUTABLE_MODE_P (mode
)
11841 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11843 && have_insn_for (COMPARE
, mode
))
11845 op0
= XEXP (op0
, 0);
11851 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11852 this for equality comparisons due to pathological cases involving
11854 if (equality_comparison_p
11855 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11856 op1
, XEXP (op0
, 1))))
11858 op0
= XEXP (op0
, 0);
11863 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11864 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11865 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11867 op0
= XEXP (XEXP (op0
, 0), 0);
11868 code
= (code
== LT
? EQ
: NE
);
11874 /* We used to optimize signed comparisons against zero, but that
11875 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11876 arrive here as equality comparisons, or (GEU, LTU) are
11877 optimized away. No need to special-case them. */
11879 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11880 (eq B (minus A C)), whichever simplifies. We can only do
11881 this for equality comparisons due to pathological cases involving
11883 if (equality_comparison_p
11884 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11885 XEXP (op0
, 1), op1
)))
11887 op0
= XEXP (op0
, 0);
11892 if (equality_comparison_p
11893 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11894 XEXP (op0
, 0), op1
)))
11896 op0
= XEXP (op0
, 1);
11901 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11902 of bits in X minus 1, is one iff X > 0. */
11903 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11904 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11905 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11906 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11908 op0
= XEXP (op0
, 1);
11909 code
= (code
== GE
? LE
: GT
);
11915 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11916 if C is zero or B is a constant. */
11917 if (equality_comparison_p
11918 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11919 XEXP (op0
, 1), op1
)))
11921 op0
= XEXP (op0
, 0);
11928 case UNEQ
: case LTGT
:
11929 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11930 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11931 case UNORDERED
: case ORDERED
:
11932 /* We can't do anything if OP0 is a condition code value, rather
11933 than an actual data value. */
11935 || CC0_P (XEXP (op0
, 0))
11936 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11939 /* Get the two operands being compared. */
11940 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11941 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11943 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11945 /* Check for the cases where we simply want the result of the
11946 earlier test or the opposite of that result. */
11947 if (code
== NE
|| code
== EQ
11948 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11949 && (code
== LT
|| code
== GE
)))
11951 enum rtx_code new_code
;
11952 if (code
== LT
|| code
== NE
)
11953 new_code
= GET_CODE (op0
);
11955 new_code
= reversed_comparison_code (op0
, NULL
);
11957 if (new_code
!= UNKNOWN
)
11968 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11970 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11971 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11972 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11974 op0
= XEXP (op0
, 1);
11975 code
= (code
== GE
? GT
: LE
);
11981 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11982 will be converted to a ZERO_EXTRACT later. */
11983 if (const_op
== 0 && equality_comparison_p
11984 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11985 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11987 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11988 XEXP (XEXP (op0
, 0), 1));
11989 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11993 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11994 zero and X is a comparison and C1 and C2 describe only bits set
11995 in STORE_FLAG_VALUE, we can compare with X. */
11996 if (const_op
== 0 && equality_comparison_p
11997 && mode_width
<= HOST_BITS_PER_WIDE_INT
11998 && CONST_INT_P (XEXP (op0
, 1))
11999 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12000 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12001 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12002 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12004 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12005 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12006 if ((~STORE_FLAG_VALUE
& mask
) == 0
12007 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12008 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12009 && COMPARISON_P (tem
))))
12011 op0
= XEXP (XEXP (op0
, 0), 0);
12016 /* If we are doing an equality comparison of an AND of a bit equal
12017 to the sign bit, replace this with a LT or GE comparison of
12018 the underlying value. */
12019 if (equality_comparison_p
12021 && CONST_INT_P (XEXP (op0
, 1))
12022 && mode_width
<= HOST_BITS_PER_WIDE_INT
12023 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12024 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
12026 op0
= XEXP (op0
, 0);
12027 code
= (code
== EQ
? GE
: LT
);
12031 /* If this AND operation is really a ZERO_EXTEND from a narrower
12032 mode, the constant fits within that mode, and this is either an
12033 equality or unsigned comparison, try to do this comparison in
12038 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12039 -> (ne:DI (reg:SI 4) (const_int 0))
12041 unless TRULY_NOOP_TRUNCATION allows it or the register is
12042 known to hold a value of the required mode the
12043 transformation is invalid. */
12044 if ((equality_comparison_p
|| unsigned_comparison_p
)
12045 && CONST_INT_P (XEXP (op0
, 1))
12046 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12047 & GET_MODE_MASK (mode
))
12049 && const_op
>> i
== 0
12050 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
12052 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12056 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12057 fits in both M1 and M2 and the SUBREG is either paradoxical
12058 or represents the low part, permute the SUBREG and the AND
12060 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12061 && CONST_INT_P (XEXP (op0
, 1)))
12063 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12064 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12065 /* Require an integral mode, to avoid creating something like
12067 if (SCALAR_INT_MODE_P (tmode
)
12068 /* It is unsafe to commute the AND into the SUBREG if the
12069 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12070 not defined. As originally written the upper bits
12071 have a defined value due to the AND operation.
12072 However, if we commute the AND inside the SUBREG then
12073 they no longer have defined values and the meaning of
12074 the code has been changed.
12075 Also C1 should not change value in the smaller mode,
12076 see PR67028 (a positive C1 can become negative in the
12077 smaller mode, so that the AND does no longer mask the
12079 && ((WORD_REGISTER_OPERATIONS
12080 && mode_width
> GET_MODE_PRECISION (tmode
)
12081 && mode_width
<= BITS_PER_WORD
12082 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12083 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12084 && subreg_lowpart_p (XEXP (op0
, 0))))
12085 && mode_width
<= HOST_BITS_PER_WIDE_INT
12086 && HWI_COMPUTABLE_MODE_P (tmode
)
12087 && (c1
& ~mask
) == 0
12088 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12090 && c1
!= GET_MODE_MASK (tmode
))
12092 op0
= simplify_gen_binary (AND
, tmode
,
12093 SUBREG_REG (XEXP (op0
, 0)),
12094 gen_int_mode (c1
, tmode
));
12095 op0
= gen_lowpart (mode
, op0
);
12100 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12101 if (const_op
== 0 && equality_comparison_p
12102 && XEXP (op0
, 1) == const1_rtx
12103 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12105 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12106 XEXP (XEXP (op0
, 0), 0), 1);
12107 code
= (code
== NE
? EQ
: NE
);
12111 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12112 (eq (and (lshiftrt X) 1) 0).
12113 Also handle the case where (not X) is expressed using xor. */
12114 if (const_op
== 0 && equality_comparison_p
12115 && XEXP (op0
, 1) == const1_rtx
12116 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12118 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12119 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12121 if (GET_CODE (shift_op
) == NOT
12122 || (GET_CODE (shift_op
) == XOR
12123 && CONST_INT_P (XEXP (shift_op
, 1))
12124 && CONST_INT_P (shift_count
)
12125 && HWI_COMPUTABLE_MODE_P (mode
)
12126 && (UINTVAL (XEXP (shift_op
, 1))
12127 == (unsigned HOST_WIDE_INT
) 1
12128 << INTVAL (shift_count
))))
12131 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12132 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12133 code
= (code
== NE
? EQ
: NE
);
12140 /* If we have (compare (ashift FOO N) (const_int C)) and
12141 the high order N bits of FOO (N+1 if an inequality comparison)
12142 are known to be zero, we can do this by comparing FOO with C
12143 shifted right N bits so long as the low-order N bits of C are
12145 if (CONST_INT_P (XEXP (op0
, 1))
12146 && INTVAL (XEXP (op0
, 1)) >= 0
12147 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12148 < HOST_BITS_PER_WIDE_INT
)
12149 && (((unsigned HOST_WIDE_INT
) const_op
12150 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
12152 && mode_width
<= HOST_BITS_PER_WIDE_INT
12153 && (nonzero_bits (XEXP (op0
, 0), mode
)
12154 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12155 + ! equality_comparison_p
))) == 0)
12157 /* We must perform a logical shift, not an arithmetic one,
12158 as we want the top N bits of C to be zero. */
12159 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12161 temp
>>= INTVAL (XEXP (op0
, 1));
12162 op1
= gen_int_mode (temp
, mode
);
12163 op0
= XEXP (op0
, 0);
12167 /* If we are doing a sign bit comparison, it means we are testing
12168 a particular bit. Convert it to the appropriate AND. */
12169 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12170 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12172 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12173 ((unsigned HOST_WIDE_INT
) 1
12175 - INTVAL (XEXP (op0
, 1)))));
12176 code
= (code
== LT
? NE
: EQ
);
12180 /* If this an equality comparison with zero and we are shifting
12181 the low bit to the sign bit, we can convert this to an AND of the
12183 if (const_op
== 0 && equality_comparison_p
12184 && CONST_INT_P (XEXP (op0
, 1))
12185 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12187 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12193 /* If this is an equality comparison with zero, we can do this
12194 as a logical shift, which might be much simpler. */
12195 if (equality_comparison_p
&& const_op
== 0
12196 && CONST_INT_P (XEXP (op0
, 1)))
12198 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12200 INTVAL (XEXP (op0
, 1)));
12204 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12205 do the comparison in a narrower mode. */
12206 if (! unsigned_comparison_p
12207 && CONST_INT_P (XEXP (op0
, 1))
12208 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12209 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12210 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12211 MODE_INT
, 1)) != BLKmode
12212 && (((unsigned HOST_WIDE_INT
) const_op
12213 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12214 <= GET_MODE_MASK (tmode
)))
12216 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12220 /* Likewise if OP0 is a PLUS of a sign extension with a
12221 constant, which is usually represented with the PLUS
12222 between the shifts. */
12223 if (! unsigned_comparison_p
12224 && CONST_INT_P (XEXP (op0
, 1))
12225 && GET_CODE (XEXP (op0
, 0)) == PLUS
12226 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12227 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12228 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12229 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12230 MODE_INT
, 1)) != BLKmode
12231 && (((unsigned HOST_WIDE_INT
) const_op
12232 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12233 <= GET_MODE_MASK (tmode
)))
12235 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12236 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12237 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12238 add_const
, XEXP (op0
, 1));
12240 op0
= simplify_gen_binary (PLUS
, tmode
,
12241 gen_lowpart (tmode
, inner
),
12246 /* ... fall through ... */
12248 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12249 the low order N bits of FOO are known to be zero, we can do this
12250 by comparing FOO with C shifted left N bits so long as no
12251 overflow occurs. Even if the low order N bits of FOO aren't known
12252 to be zero, if the comparison is >= or < we can use the same
12253 optimization and for > or <= by setting all the low
12254 order N bits in the comparison constant. */
12255 if (CONST_INT_P (XEXP (op0
, 1))
12256 && INTVAL (XEXP (op0
, 1)) > 0
12257 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12258 && mode_width
<= HOST_BITS_PER_WIDE_INT
12259 && (((unsigned HOST_WIDE_INT
) const_op
12260 + (GET_CODE (op0
) != LSHIFTRT
12261 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12264 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12266 unsigned HOST_WIDE_INT low_bits
12267 = (nonzero_bits (XEXP (op0
, 0), mode
)
12268 & (((unsigned HOST_WIDE_INT
) 1
12269 << INTVAL (XEXP (op0
, 1))) - 1));
12270 if (low_bits
== 0 || !equality_comparison_p
)
12272 /* If the shift was logical, then we must make the condition
12274 if (GET_CODE (op0
) == LSHIFTRT
)
12275 code
= unsigned_condition (code
);
12277 const_op
<<= INTVAL (XEXP (op0
, 1));
12279 && (code
== GT
|| code
== GTU
12280 || code
== LE
|| code
== LEU
))
12282 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
12283 op1
= GEN_INT (const_op
);
12284 op0
= XEXP (op0
, 0);
12289 /* If we are using this shift to extract just the sign bit, we
12290 can replace this with an LT or GE comparison. */
12292 && (equality_comparison_p
|| sign_bit_comparison_p
)
12293 && CONST_INT_P (XEXP (op0
, 1))
12294 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12296 op0
= XEXP (op0
, 0);
12297 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12309 /* Now make any compound operations involved in this comparison. Then,
12310 check for an outmost SUBREG on OP0 that is not doing anything or is
12311 paradoxical. The latter transformation must only be performed when
12312 it is known that the "extra" bits will be the same in op0 and op1 or
12313 that they don't matter. There are three cases to consider:
12315 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12316 care bits and we can assume they have any convenient value. So
12317 making the transformation is safe.
12319 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12320 In this case the upper bits of op0 are undefined. We should not make
12321 the simplification in that case as we do not know the contents of
12324 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12325 UNKNOWN. In that case we know those bits are zeros or ones. We must
12326 also be sure that they are the same as the upper bits of op1.
12328 We can never remove a SUBREG for a non-equality comparison because
12329 the sign bit is in a different place in the underlying object. */
12331 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
12332 op1
= make_compound_operation (op1
, SET
);
12334 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12335 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12336 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12337 && (code
== NE
|| code
== EQ
))
12339 if (paradoxical_subreg_p (op0
))
12341 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12343 if (REG_P (SUBREG_REG (op0
)))
12345 op0
= SUBREG_REG (op0
);
12346 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12349 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12350 <= HOST_BITS_PER_WIDE_INT
)
12351 && (nonzero_bits (SUBREG_REG (op0
),
12352 GET_MODE (SUBREG_REG (op0
)))
12353 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12355 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12357 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12358 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12359 op0
= SUBREG_REG (op0
), op1
= tem
;
12363 /* We now do the opposite procedure: Some machines don't have compare
12364 insns in all modes. If OP0's mode is an integer mode smaller than a
12365 word and we can't do a compare in that mode, see if there is a larger
12366 mode for which we can do the compare. There are a number of cases in
12367 which we can use the wider mode. */
12369 mode
= GET_MODE (op0
);
12370 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12371 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12372 && ! have_insn_for (COMPARE
, mode
))
12373 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12374 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12375 tmode
= GET_MODE_WIDER_MODE (tmode
))
12376 if (have_insn_for (COMPARE
, tmode
))
12380 /* If this is a test for negative, we can make an explicit
12381 test of the sign bit. Test this first so we can use
12382 a paradoxical subreg to extend OP0. */
12384 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12385 && HWI_COMPUTABLE_MODE_P (mode
))
12387 unsigned HOST_WIDE_INT sign
12388 = (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1);
12389 op0
= simplify_gen_binary (AND
, tmode
,
12390 gen_lowpart (tmode
, op0
),
12391 gen_int_mode (sign
, tmode
));
12392 code
= (code
== LT
) ? NE
: EQ
;
12396 /* If the only nonzero bits in OP0 and OP1 are those in the
12397 narrower mode and this is an equality or unsigned comparison,
12398 we can use the wider mode. Similarly for sign-extended
12399 values, in which case it is true for all comparisons. */
12400 zero_extended
= ((code
== EQ
|| code
== NE
12401 || code
== GEU
|| code
== GTU
12402 || code
== LEU
|| code
== LTU
)
12403 && (nonzero_bits (op0
, tmode
)
12404 & ~GET_MODE_MASK (mode
)) == 0
12405 && ((CONST_INT_P (op1
)
12406 || (nonzero_bits (op1
, tmode
)
12407 & ~GET_MODE_MASK (mode
)) == 0)));
12410 || ((num_sign_bit_copies (op0
, tmode
)
12411 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12412 - GET_MODE_PRECISION (mode
)))
12413 && (num_sign_bit_copies (op1
, tmode
)
12414 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12415 - GET_MODE_PRECISION (mode
)))))
12417 /* If OP0 is an AND and we don't have an AND in MODE either,
12418 make a new AND in the proper mode. */
12419 if (GET_CODE (op0
) == AND
12420 && !have_insn_for (AND
, mode
))
12421 op0
= simplify_gen_binary (AND
, tmode
,
12422 gen_lowpart (tmode
,
12424 gen_lowpart (tmode
,
12430 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12431 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12435 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12436 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12443 /* We may have changed the comparison operands. Re-canonicalize. */
12444 if (swap_commutative_operands_p (op0
, op1
))
12446 std::swap (op0
, op1
);
12447 code
= swap_condition (code
);
12450 /* If this machine only supports a subset of valid comparisons, see if we
12451 can convert an unsupported one into a supported one. */
12452 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12460 /* Utility function for record_value_for_reg. Count number of
12465 enum rtx_code code
= GET_CODE (x
);
12469 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12470 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12472 rtx x0
= XEXP (x
, 0);
12473 rtx x1
= XEXP (x
, 1);
12476 return 1 + 2 * count_rtxs (x0
);
12478 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12479 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12480 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12481 return 2 + 2 * count_rtxs (x0
)
12482 + count_rtxs (x
== XEXP (x1
, 0)
12483 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12485 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12486 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12487 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12488 return 2 + 2 * count_rtxs (x1
)
12489 + count_rtxs (x
== XEXP (x0
, 0)
12490 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12493 fmt
= GET_RTX_FORMAT (code
);
12494 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12496 ret
+= count_rtxs (XEXP (x
, i
));
12497 else if (fmt
[i
] == 'E')
12498 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12499 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12504 /* Utility function for following routine. Called when X is part of a value
12505 being stored into last_set_value. Sets last_set_table_tick
12506 for each register mentioned. Similar to mention_regs in cse.c */
12509 update_table_tick (rtx x
)
12511 enum rtx_code code
= GET_CODE (x
);
12512 const char *fmt
= GET_RTX_FORMAT (code
);
12517 unsigned int regno
= REGNO (x
);
12518 unsigned int endregno
= END_REGNO (x
);
12521 for (r
= regno
; r
< endregno
; r
++)
12523 reg_stat_type
*rsp
= ®_stat
[r
];
12524 rsp
->last_set_table_tick
= label_tick
;
12530 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12533 /* Check for identical subexpressions. If x contains
12534 identical subexpression we only have to traverse one of
12536 if (i
== 0 && ARITHMETIC_P (x
))
12538 /* Note that at this point x1 has already been
12540 rtx x0
= XEXP (x
, 0);
12541 rtx x1
= XEXP (x
, 1);
12543 /* If x0 and x1 are identical then there is no need to
12548 /* If x0 is identical to a subexpression of x1 then while
12549 processing x1, x0 has already been processed. Thus we
12550 are done with x. */
12551 if (ARITHMETIC_P (x1
)
12552 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12555 /* If x1 is identical to a subexpression of x0 then we
12556 still have to process the rest of x0. */
12557 if (ARITHMETIC_P (x0
)
12558 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12560 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12565 update_table_tick (XEXP (x
, i
));
12567 else if (fmt
[i
] == 'E')
12568 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12569 update_table_tick (XVECEXP (x
, i
, j
));
12572 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12573 are saying that the register is clobbered and we no longer know its
12574 value. If INSN is zero, don't update reg_stat[].last_set; this is
12575 only permitted with VALUE also zero and is used to invalidate the
12579 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12581 unsigned int regno
= REGNO (reg
);
12582 unsigned int endregno
= END_REGNO (reg
);
12584 reg_stat_type
*rsp
;
12586 /* If VALUE contains REG and we have a previous value for REG, substitute
12587 the previous value. */
12588 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12592 /* Set things up so get_last_value is allowed to see anything set up to
12594 subst_low_luid
= DF_INSN_LUID (insn
);
12595 tem
= get_last_value (reg
);
12597 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12598 it isn't going to be useful and will take a lot of time to process,
12599 so just use the CLOBBER. */
12603 if (ARITHMETIC_P (tem
)
12604 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12605 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12606 tem
= XEXP (tem
, 0);
12607 else if (count_occurrences (value
, reg
, 1) >= 2)
12609 /* If there are two or more occurrences of REG in VALUE,
12610 prevent the value from growing too much. */
12611 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12612 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12615 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12619 /* For each register modified, show we don't know its value, that
12620 we don't know about its bitwise content, that its value has been
12621 updated, and that we don't know the location of the death of the
12623 for (i
= regno
; i
< endregno
; i
++)
12625 rsp
= ®_stat
[i
];
12628 rsp
->last_set
= insn
;
12630 rsp
->last_set_value
= 0;
12631 rsp
->last_set_mode
= VOIDmode
;
12632 rsp
->last_set_nonzero_bits
= 0;
12633 rsp
->last_set_sign_bit_copies
= 0;
12634 rsp
->last_death
= 0;
12635 rsp
->truncated_to_mode
= VOIDmode
;
12638 /* Mark registers that are being referenced in this value. */
12640 update_table_tick (value
);
12642 /* Now update the status of each register being set.
12643 If someone is using this register in this block, set this register
12644 to invalid since we will get confused between the two lives in this
12645 basic block. This makes using this register always invalid. In cse, we
12646 scan the table to invalidate all entries using this register, but this
12647 is too much work for us. */
12649 for (i
= regno
; i
< endregno
; i
++)
12651 rsp
= ®_stat
[i
];
12652 rsp
->last_set_label
= label_tick
;
12654 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12655 rsp
->last_set_invalid
= 1;
12657 rsp
->last_set_invalid
= 0;
12660 /* The value being assigned might refer to X (like in "x++;"). In that
12661 case, we must replace it with (clobber (const_int 0)) to prevent
12663 rsp
= ®_stat
[regno
];
12664 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12666 value
= copy_rtx (value
);
12667 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12671 /* For the main register being modified, update the value, the mode, the
12672 nonzero bits, and the number of sign bit copies. */
12674 rsp
->last_set_value
= value
;
12678 machine_mode mode
= GET_MODE (reg
);
12679 subst_low_luid
= DF_INSN_LUID (insn
);
12680 rsp
->last_set_mode
= mode
;
12681 if (GET_MODE_CLASS (mode
) == MODE_INT
12682 && HWI_COMPUTABLE_MODE_P (mode
))
12683 mode
= nonzero_bits_mode
;
12684 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12685 rsp
->last_set_sign_bit_copies
12686 = num_sign_bit_copies (value
, GET_MODE (reg
));
12690 /* Called via note_stores from record_dead_and_set_regs to handle one
12691 SET or CLOBBER in an insn. DATA is the instruction in which the
12692 set is occurring. */
12695 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12697 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12699 if (GET_CODE (dest
) == SUBREG
)
12700 dest
= SUBREG_REG (dest
);
12702 if (!record_dead_insn
)
12705 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12711 /* If we are setting the whole register, we know its value. Otherwise
12712 show that we don't know the value. We can handle SUBREG in
12714 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12715 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12716 else if (GET_CODE (setter
) == SET
12717 && GET_CODE (SET_DEST (setter
)) == SUBREG
12718 && SUBREG_REG (SET_DEST (setter
)) == dest
12719 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12720 && subreg_lowpart_p (SET_DEST (setter
)))
12721 record_value_for_reg (dest
, record_dead_insn
,
12722 gen_lowpart (GET_MODE (dest
),
12723 SET_SRC (setter
)));
12725 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12727 else if (MEM_P (dest
)
12728 /* Ignore pushes, they clobber nothing. */
12729 && ! push_operand (dest
, GET_MODE (dest
)))
12730 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12733 /* Update the records of when each REG was most recently set or killed
12734 for the things done by INSN. This is the last thing done in processing
12735 INSN in the combiner loop.
12737 We update reg_stat[], in particular fields last_set, last_set_value,
12738 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12739 last_death, and also the similar information mem_last_set (which insn
12740 most recently modified memory) and last_call_luid (which insn was the
12741 most recent subroutine call). */
12744 record_dead_and_set_regs (rtx_insn
*insn
)
12749 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12751 if (REG_NOTE_KIND (link
) == REG_DEAD
12752 && REG_P (XEXP (link
, 0)))
12754 unsigned int regno
= REGNO (XEXP (link
, 0));
12755 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12757 for (i
= regno
; i
< endregno
; i
++)
12759 reg_stat_type
*rsp
;
12761 rsp
= ®_stat
[i
];
12762 rsp
->last_death
= insn
;
12765 else if (REG_NOTE_KIND (link
) == REG_INC
)
12766 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12771 hard_reg_set_iterator hrsi
;
12772 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12774 reg_stat_type
*rsp
;
12776 rsp
= ®_stat
[i
];
12777 rsp
->last_set_invalid
= 1;
12778 rsp
->last_set
= insn
;
12779 rsp
->last_set_value
= 0;
12780 rsp
->last_set_mode
= VOIDmode
;
12781 rsp
->last_set_nonzero_bits
= 0;
12782 rsp
->last_set_sign_bit_copies
= 0;
12783 rsp
->last_death
= 0;
12784 rsp
->truncated_to_mode
= VOIDmode
;
12787 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12789 /* We can't combine into a call pattern. Remember, though, that
12790 the return value register is set at this LUID. We could
12791 still replace a register with the return value from the
12792 wrong subroutine call! */
12793 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12796 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12799 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12800 register present in the SUBREG, so for each such SUBREG go back and
12801 adjust nonzero and sign bit information of the registers that are
12802 known to have some zero/sign bits set.
12804 This is needed because when combine blows the SUBREGs away, the
12805 information on zero/sign bits is lost and further combines can be
12806 missed because of that. */
12809 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12811 struct insn_link
*links
;
12813 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12814 machine_mode mode
= GET_MODE (subreg
);
12816 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12819 for (links
= LOG_LINKS (insn
); links
;)
12821 reg_stat_type
*rsp
;
12823 insn
= links
->insn
;
12824 set
= single_set (insn
);
12826 if (! set
|| !REG_P (SET_DEST (set
))
12827 || REGNO (SET_DEST (set
)) != regno
12828 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12830 links
= links
->next
;
12834 rsp
= ®_stat
[regno
];
12835 if (rsp
->last_set
== insn
)
12837 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12838 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12841 if (REG_P (SET_SRC (set
)))
12843 regno
= REGNO (SET_SRC (set
));
12844 links
= LOG_LINKS (insn
);
12851 /* Check if X, a register, is known to contain a value already
12852 truncated to MODE. In this case we can use a subreg to refer to
12853 the truncated value even though in the generic case we would need
12854 an explicit truncation. */
12857 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
12859 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12860 machine_mode truncated
= rsp
->truncated_to_mode
;
12863 || rsp
->truncation_label
< label_tick_ebb_start
)
12865 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12867 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12872 /* If X is a hard reg or a subreg record the mode that the register is
12873 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12874 to turn a truncate into a subreg using this information. Return true
12875 if traversing X is complete. */
12878 record_truncated_value (rtx x
)
12880 machine_mode truncated_mode
;
12881 reg_stat_type
*rsp
;
12883 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12885 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12886 truncated_mode
= GET_MODE (x
);
12888 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12891 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12894 x
= SUBREG_REG (x
);
12896 /* ??? For hard-regs we now record everything. We might be able to
12897 optimize this using last_set_mode. */
12898 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12899 truncated_mode
= GET_MODE (x
);
12903 rsp
= ®_stat
[REGNO (x
)];
12904 if (rsp
->truncated_to_mode
== 0
12905 || rsp
->truncation_label
< label_tick_ebb_start
12906 || (GET_MODE_SIZE (truncated_mode
)
12907 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12909 rsp
->truncated_to_mode
= truncated_mode
;
12910 rsp
->truncation_label
= label_tick
;
12916 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12917 the modes they are used in. This can help truning TRUNCATEs into
12921 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
12923 subrtx_var_iterator::array_type array
;
12924 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
12925 if (record_truncated_value (*iter
))
12926 iter
.skip_subrtxes ();
12929 /* Scan X for promoted SUBREGs. For each one found,
12930 note what it implies to the registers used in it. */
12933 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
12935 if (GET_CODE (x
) == SUBREG
12936 && SUBREG_PROMOTED_VAR_P (x
)
12937 && REG_P (SUBREG_REG (x
)))
12938 record_promoted_value (insn
, x
);
12941 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12944 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12948 check_promoted_subreg (insn
, XEXP (x
, i
));
12952 if (XVEC (x
, i
) != 0)
12953 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12954 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12960 /* Verify that all the registers and memory references mentioned in *LOC are
12961 still valid. *LOC was part of a value set in INSN when label_tick was
12962 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12963 the invalid references with (clobber (const_int 0)) and return 1. This
12964 replacement is useful because we often can get useful information about
12965 the form of a value (e.g., if it was produced by a shift that always
12966 produces -1 or 0) even though we don't know exactly what registers it
12967 was produced from. */
12970 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
12973 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12974 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12979 unsigned int regno
= REGNO (x
);
12980 unsigned int endregno
= END_REGNO (x
);
12983 for (j
= regno
; j
< endregno
; j
++)
12985 reg_stat_type
*rsp
= ®_stat
[j
];
12986 if (rsp
->last_set_invalid
12987 /* If this is a pseudo-register that was only set once and not
12988 live at the beginning of the function, it is always valid. */
12989 || (! (regno
>= FIRST_PSEUDO_REGISTER
12990 && regno
< reg_n_sets_max
12991 && REG_N_SETS (regno
) == 1
12992 && (!REGNO_REG_SET_P
12993 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
12995 && rsp
->last_set_label
> tick
))
12998 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13005 /* If this is a memory reference, make sure that there were no stores after
13006 it that might have clobbered the value. We don't have alias info, so we
13007 assume any store invalidates it. Moreover, we only have local UIDs, so
13008 we also assume that there were stores in the intervening basic blocks. */
13009 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13010 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13013 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13017 for (i
= 0; i
< len
; i
++)
13021 /* Check for identical subexpressions. If x contains
13022 identical subexpression we only have to traverse one of
13024 if (i
== 1 && ARITHMETIC_P (x
))
13026 /* Note that at this point x0 has already been checked
13027 and found valid. */
13028 rtx x0
= XEXP (x
, 0);
13029 rtx x1
= XEXP (x
, 1);
13031 /* If x0 and x1 are identical then x is also valid. */
13035 /* If x1 is identical to a subexpression of x0 then
13036 while checking x0, x1 has already been checked. Thus
13037 it is valid and so as x. */
13038 if (ARITHMETIC_P (x0
)
13039 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13042 /* If x0 is identical to a subexpression of x1 then x is
13043 valid iff the rest of x1 is valid. */
13044 if (ARITHMETIC_P (x1
)
13045 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13047 get_last_value_validate (&XEXP (x1
,
13048 x0
== XEXP (x1
, 0) ? 1 : 0),
13049 insn
, tick
, replace
);
13052 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13056 else if (fmt
[i
] == 'E')
13057 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13058 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13059 insn
, tick
, replace
) == 0)
13063 /* If we haven't found a reason for it to be invalid, it is valid. */
13067 /* Get the last value assigned to X, if known. Some registers
13068 in the value may be replaced with (clobber (const_int 0)) if their value
13069 is known longer known reliably. */
13072 get_last_value (const_rtx x
)
13074 unsigned int regno
;
13076 reg_stat_type
*rsp
;
13078 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13079 then convert it to the desired mode. If this is a paradoxical SUBREG,
13080 we cannot predict what values the "extra" bits might have. */
13081 if (GET_CODE (x
) == SUBREG
13082 && subreg_lowpart_p (x
)
13083 && !paradoxical_subreg_p (x
)
13084 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13085 return gen_lowpart (GET_MODE (x
), value
);
13091 rsp
= ®_stat
[regno
];
13092 value
= rsp
->last_set_value
;
13094 /* If we don't have a value, or if it isn't for this basic block and
13095 it's either a hard register, set more than once, or it's a live
13096 at the beginning of the function, return 0.
13098 Because if it's not live at the beginning of the function then the reg
13099 is always set before being used (is never used without being set).
13100 And, if it's set only once, and it's always set before use, then all
13101 uses must have the same last value, even if it's not from this basic
13105 || (rsp
->last_set_label
< label_tick_ebb_start
13106 && (regno
< FIRST_PSEUDO_REGISTER
13107 || regno
>= reg_n_sets_max
13108 || REG_N_SETS (regno
) != 1
13110 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13113 /* If the value was set in a later insn than the ones we are processing,
13114 we can't use it even if the register was only set once. */
13115 if (rsp
->last_set_label
== label_tick
13116 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13119 /* If the value has all its registers valid, return it. */
13120 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13123 /* Otherwise, make a copy and replace any invalid register with
13124 (clobber (const_int 0)). If that fails for some reason, return 0. */
13126 value
= copy_rtx (value
);
13127 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13133 /* Return nonzero if expression X refers to a REG or to memory
13134 that is set in an instruction more recent than FROM_LUID. */
13137 use_crosses_set_p (const_rtx x
, int from_luid
)
13141 enum rtx_code code
= GET_CODE (x
);
13145 unsigned int regno
= REGNO (x
);
13146 unsigned endreg
= END_REGNO (x
);
13148 #ifdef PUSH_ROUNDING
13149 /* Don't allow uses of the stack pointer to be moved,
13150 because we don't know whether the move crosses a push insn. */
13151 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13154 for (; regno
< endreg
; regno
++)
13156 reg_stat_type
*rsp
= ®_stat
[regno
];
13158 && rsp
->last_set_label
== label_tick
13159 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13165 if (code
== MEM
&& mem_last_set
> from_luid
)
13168 fmt
= GET_RTX_FORMAT (code
);
13170 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13175 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13176 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13179 else if (fmt
[i
] == 'e'
13180 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13186 /* Define three variables used for communication between the following
13189 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13190 static int reg_dead_flag
;
13192 /* Function called via note_stores from reg_dead_at_p.
13194 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13195 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13198 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13200 unsigned int regno
, endregno
;
13205 regno
= REGNO (dest
);
13206 endregno
= END_REGNO (dest
);
13207 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13208 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13211 /* Return nonzero if REG is known to be dead at INSN.
13213 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13214 referencing REG, it is dead. If we hit a SET referencing REG, it is
13215 live. Otherwise, see if it is live or dead at the start of the basic
13216 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13217 must be assumed to be always live. */
13220 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13225 /* Set variables for reg_dead_at_p_1. */
13226 reg_dead_regno
= REGNO (reg
);
13227 reg_dead_endregno
= END_REGNO (reg
);
13231 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13232 we allow the machine description to decide whether use-and-clobber
13233 patterns are OK. */
13234 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13236 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13237 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13241 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13242 beginning of basic block. */
13243 block
= BLOCK_FOR_INSN (insn
);
13248 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13251 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13253 return reg_dead_flag
== 1 ? 1 : 0;
13255 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13259 if (insn
== BB_HEAD (block
))
13262 insn
= PREV_INSN (insn
);
13265 /* Look at live-in sets for the basic block that we were in. */
13266 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13267 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13273 /* Note hard registers in X that are used. */
13276 mark_used_regs_combine (rtx x
)
13278 RTX_CODE code
= GET_CODE (x
);
13279 unsigned int regno
;
13290 case ADDR_DIFF_VEC
:
13292 /* CC0 must die in the insn after it is set, so we don't need to take
13293 special note of it here. */
13298 /* If we are clobbering a MEM, mark any hard registers inside the
13299 address as used. */
13300 if (MEM_P (XEXP (x
, 0)))
13301 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13306 /* A hard reg in a wide mode may really be multiple registers.
13307 If so, mark all of them just like the first. */
13308 if (regno
< FIRST_PSEUDO_REGISTER
)
13310 /* None of this applies to the stack, frame or arg pointers. */
13311 if (regno
== STACK_POINTER_REGNUM
13312 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13313 && regno
== HARD_FRAME_POINTER_REGNUM
)
13314 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13315 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13316 || regno
== FRAME_POINTER_REGNUM
)
13319 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13325 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13327 rtx testreg
= SET_DEST (x
);
13329 while (GET_CODE (testreg
) == SUBREG
13330 || GET_CODE (testreg
) == ZERO_EXTRACT
13331 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13332 testreg
= XEXP (testreg
, 0);
13334 if (MEM_P (testreg
))
13335 mark_used_regs_combine (XEXP (testreg
, 0));
13337 mark_used_regs_combine (SET_SRC (x
));
13345 /* Recursively scan the operands of this expression. */
13348 const char *fmt
= GET_RTX_FORMAT (code
);
13350 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13353 mark_used_regs_combine (XEXP (x
, i
));
13354 else if (fmt
[i
] == 'E')
13358 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13359 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13365 /* Remove register number REGNO from the dead registers list of INSN.
13367 Return the note used to record the death, if there was one. */
13370 remove_death (unsigned int regno
, rtx_insn
*insn
)
13372 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13375 remove_note (insn
, note
);
13380 /* For each register (hardware or pseudo) used within expression X, if its
13381 death is in an instruction with luid between FROM_LUID (inclusive) and
13382 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13383 list headed by PNOTES.
13385 That said, don't move registers killed by maybe_kill_insn.
13387 This is done when X is being merged by combination into TO_INSN. These
13388 notes will then be distributed as needed. */
13391 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13396 enum rtx_code code
= GET_CODE (x
);
13400 unsigned int regno
= REGNO (x
);
13401 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13403 /* Don't move the register if it gets killed in between from and to. */
13404 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13405 && ! reg_referenced_p (x
, maybe_kill_insn
))
13409 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13410 && DF_INSN_LUID (where_dead
) >= from_luid
13411 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13413 rtx note
= remove_death (regno
, where_dead
);
13415 /* It is possible for the call above to return 0. This can occur
13416 when last_death points to I2 or I1 that we combined with.
13417 In that case make a new note.
13419 We must also check for the case where X is a hard register
13420 and NOTE is a death note for a range of hard registers
13421 including X. In that case, we must put REG_DEAD notes for
13422 the remaining registers in place of NOTE. */
13424 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13425 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13426 > GET_MODE_SIZE (GET_MODE (x
))))
13428 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13429 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13430 unsigned int ourend
= END_REGNO (x
);
13433 for (i
= deadregno
; i
< deadend
; i
++)
13434 if (i
< regno
|| i
>= ourend
)
13435 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13438 /* If we didn't find any note, or if we found a REG_DEAD note that
13439 covers only part of the given reg, and we have a multi-reg hard
13440 register, then to be safe we must check for REG_DEAD notes
13441 for each register other than the first. They could have
13442 their own REG_DEAD notes lying around. */
13443 else if ((note
== 0
13445 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13446 < GET_MODE_SIZE (GET_MODE (x
)))))
13447 && regno
< FIRST_PSEUDO_REGISTER
13448 && REG_NREGS (x
) > 1)
13450 unsigned int ourend
= END_REGNO (x
);
13451 unsigned int i
, offset
;
13455 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13459 for (i
= regno
+ offset
; i
< ourend
; i
++)
13460 move_deaths (regno_reg_rtx
[i
],
13461 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13464 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13466 XEXP (note
, 1) = *pnotes
;
13470 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13476 else if (GET_CODE (x
) == SET
)
13478 rtx dest
= SET_DEST (x
);
13480 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13482 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13483 that accesses one word of a multi-word item, some
13484 piece of everything register in the expression is used by
13485 this insn, so remove any old death. */
13486 /* ??? So why do we test for equality of the sizes? */
13488 if (GET_CODE (dest
) == ZERO_EXTRACT
13489 || GET_CODE (dest
) == STRICT_LOW_PART
13490 || (GET_CODE (dest
) == SUBREG
13491 && (((GET_MODE_SIZE (GET_MODE (dest
))
13492 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13493 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13494 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13496 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13500 /* If this is some other SUBREG, we know it replaces the entire
13501 value, so use that as the destination. */
13502 if (GET_CODE (dest
) == SUBREG
)
13503 dest
= SUBREG_REG (dest
);
13505 /* If this is a MEM, adjust deaths of anything used in the address.
13506 For a REG (the only other possibility), the entire value is
13507 being replaced so the old value is not used in this insn. */
13510 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13515 else if (GET_CODE (x
) == CLOBBER
)
13518 len
= GET_RTX_LENGTH (code
);
13519 fmt
= GET_RTX_FORMAT (code
);
13521 for (i
= 0; i
< len
; i
++)
13526 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13527 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13530 else if (fmt
[i
] == 'e')
13531 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13535 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13536 pattern of an insn. X must be a REG. */
13539 reg_bitfield_target_p (rtx x
, rtx body
)
13543 if (GET_CODE (body
) == SET
)
13545 rtx dest
= SET_DEST (body
);
13547 unsigned int regno
, tregno
, endregno
, endtregno
;
13549 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13550 target
= XEXP (dest
, 0);
13551 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13552 target
= SUBREG_REG (XEXP (dest
, 0));
13556 if (GET_CODE (target
) == SUBREG
)
13557 target
= SUBREG_REG (target
);
13559 if (!REG_P (target
))
13562 tregno
= REGNO (target
), regno
= REGNO (x
);
13563 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13564 return target
== x
;
13566 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13567 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13569 return endregno
> tregno
&& regno
< endtregno
;
13572 else if (GET_CODE (body
) == PARALLEL
)
13573 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13574 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13580 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13581 as appropriate. I3 and I2 are the insns resulting from the combination
13582 insns including FROM (I2 may be zero).
13584 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13585 not need REG_DEAD notes because they are being substituted for. This
13586 saves searching in the most common cases.
13588 Each note in the list is either ignored or placed on some insns, depending
13589 on the type of note. */
13592 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13593 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13595 rtx note
, next_note
;
13597 rtx_insn
*tem_insn
;
13599 for (note
= notes
; note
; note
= next_note
)
13601 rtx_insn
*place
= 0, *place2
= 0;
13603 next_note
= XEXP (note
, 1);
13604 switch (REG_NOTE_KIND (note
))
13608 /* Doesn't matter much where we put this, as long as it's somewhere.
13609 It is preferable to keep these notes on branches, which is most
13610 likely to be i3. */
13614 case REG_NON_LOCAL_GOTO
:
13619 gcc_assert (i2
&& JUMP_P (i2
));
13624 case REG_EH_REGION
:
13625 /* These notes must remain with the call or trapping instruction. */
13628 else if (i2
&& CALL_P (i2
))
13632 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13633 if (may_trap_p (i3
))
13635 else if (i2
&& may_trap_p (i2
))
13637 /* ??? Otherwise assume we've combined things such that we
13638 can now prove that the instructions can't trap. Drop the
13639 note in this case. */
13643 case REG_ARGS_SIZE
:
13644 /* ??? How to distribute between i3-i1. Assume i3 contains the
13645 entire adjustment. Assert i3 contains at least some adjust. */
13646 if (!noop_move_p (i3
))
13648 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13649 /* fixup_args_size_notes looks at REG_NORETURN note,
13650 so ensure the note is placed there first. */
13654 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13655 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13659 XEXP (n
, 1) = REG_NOTES (i3
);
13660 REG_NOTES (i3
) = n
;
13664 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13665 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13666 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13667 gcc_assert (old_size
!= args_size
13669 && !ACCUMULATE_OUTGOING_ARGS
13670 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13677 case REG_CALL_DECL
:
13678 /* These notes must remain with the call. It should not be
13679 possible for both I2 and I3 to be a call. */
13684 gcc_assert (i2
&& CALL_P (i2
));
13690 /* Any clobbers for i3 may still exist, and so we must process
13691 REG_UNUSED notes from that insn.
13693 Any clobbers from i2 or i1 can only exist if they were added by
13694 recog_for_combine. In that case, recog_for_combine created the
13695 necessary REG_UNUSED notes. Trying to keep any original
13696 REG_UNUSED notes from these insns can cause incorrect output
13697 if it is for the same register as the original i3 dest.
13698 In that case, we will notice that the register is set in i3,
13699 and then add a REG_UNUSED note for the destination of i3, which
13700 is wrong. However, it is possible to have REG_UNUSED notes from
13701 i2 or i1 for register which were both used and clobbered, so
13702 we keep notes from i2 or i1 if they will turn into REG_DEAD
13705 /* If this register is set or clobbered in I3, put the note there
13706 unless there is one already. */
13707 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13709 if (from_insn
!= i3
)
13712 if (! (REG_P (XEXP (note
, 0))
13713 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13714 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13717 /* Otherwise, if this register is used by I3, then this register
13718 now dies here, so we must put a REG_DEAD note here unless there
13720 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13721 && ! (REG_P (XEXP (note
, 0))
13722 ? find_regno_note (i3
, REG_DEAD
,
13723 REGNO (XEXP (note
, 0)))
13724 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13726 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13734 /* These notes say something about results of an insn. We can
13735 only support them if they used to be on I3 in which case they
13736 remain on I3. Otherwise they are ignored.
13738 If the note refers to an expression that is not a constant, we
13739 must also ignore the note since we cannot tell whether the
13740 equivalence is still true. It might be possible to do
13741 slightly better than this (we only have a problem if I2DEST
13742 or I1DEST is present in the expression), but it doesn't
13743 seem worth the trouble. */
13745 if (from_insn
== i3
13746 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13751 /* These notes say something about how a register is used. They must
13752 be present on any use of the register in I2 or I3. */
13753 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13756 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13765 case REG_LABEL_TARGET
:
13766 case REG_LABEL_OPERAND
:
13767 /* This can show up in several ways -- either directly in the
13768 pattern, or hidden off in the constant pool with (or without?)
13769 a REG_EQUAL note. */
13770 /* ??? Ignore the without-reg_equal-note problem for now. */
13771 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13772 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13773 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13774 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13778 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13779 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13780 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13781 && LABEL_REF_LABEL (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13789 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13790 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13792 if (place
&& JUMP_P (place
)
13793 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13794 && (JUMP_LABEL (place
) == NULL
13795 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13797 rtx label
= JUMP_LABEL (place
);
13800 JUMP_LABEL (place
) = XEXP (note
, 0);
13801 else if (LABEL_P (label
))
13802 LABEL_NUSES (label
)--;
13805 if (place2
&& JUMP_P (place2
)
13806 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13807 && (JUMP_LABEL (place2
) == NULL
13808 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13810 rtx label
= JUMP_LABEL (place2
);
13813 JUMP_LABEL (place2
) = XEXP (note
, 0);
13814 else if (LABEL_P (label
))
13815 LABEL_NUSES (label
)--;
13821 /* This note says something about the value of a register prior
13822 to the execution of an insn. It is too much trouble to see
13823 if the note is still correct in all situations. It is better
13824 to simply delete it. */
13828 /* If we replaced the right hand side of FROM_INSN with a
13829 REG_EQUAL note, the original use of the dying register
13830 will not have been combined into I3 and I2. In such cases,
13831 FROM_INSN is guaranteed to be the first of the combined
13832 instructions, so we simply need to search back before
13833 FROM_INSN for the previous use or set of this register,
13834 then alter the notes there appropriately.
13836 If the register is used as an input in I3, it dies there.
13837 Similarly for I2, if it is nonzero and adjacent to I3.
13839 If the register is not used as an input in either I3 or I2
13840 and it is not one of the registers we were supposed to eliminate,
13841 there are two possibilities. We might have a non-adjacent I2
13842 or we might have somehow eliminated an additional register
13843 from a computation. For example, we might have had A & B where
13844 we discover that B will always be zero. In this case we will
13845 eliminate the reference to A.
13847 In both cases, we must search to see if we can find a previous
13848 use of A and put the death note there. */
13851 && from_insn
== i2mod
13852 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13853 tem_insn
= from_insn
;
13857 && CALL_P (from_insn
)
13858 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13860 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13862 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13863 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13865 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13867 && reg_overlap_mentioned_p (XEXP (note
, 0),
13869 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13870 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13873 /* If the new I2 sets the same register that is marked dead
13874 in the note, the note now should not be put on I2, as the
13875 note refers to a previous incarnation of the reg. */
13876 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
13882 basic_block bb
= this_basic_block
;
13884 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13886 if (!NONDEBUG_INSN_P (tem_insn
))
13888 if (tem_insn
== BB_HEAD (bb
))
13893 /* If the register is being set at TEM_INSN, see if that is all
13894 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13895 into a REG_UNUSED note instead. Don't delete sets to
13896 global register vars. */
13897 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13898 || !global_regs
[REGNO (XEXP (note
, 0))])
13899 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
13901 rtx set
= single_set (tem_insn
);
13902 rtx inner_dest
= 0;
13903 rtx_insn
*cc0_setter
= NULL
;
13906 for (inner_dest
= SET_DEST (set
);
13907 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13908 || GET_CODE (inner_dest
) == SUBREG
13909 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13910 inner_dest
= XEXP (inner_dest
, 0))
13913 /* Verify that it was the set, and not a clobber that
13914 modified the register.
13916 CC0 targets must be careful to maintain setter/user
13917 pairs. If we cannot delete the setter due to side
13918 effects, mark the user with an UNUSED note instead
13921 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13922 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13924 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13925 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
13926 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
13928 /* Move the notes and links of TEM_INSN elsewhere.
13929 This might delete other dead insns recursively.
13930 First set the pattern to something that won't use
13932 rtx old_notes
= REG_NOTES (tem_insn
);
13934 PATTERN (tem_insn
) = pc_rtx
;
13935 REG_NOTES (tem_insn
) = NULL
;
13937 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
13938 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13939 distribute_links (LOG_LINKS (tem_insn
));
13941 SET_INSN_DELETED (tem_insn
);
13942 if (tem_insn
== i2
)
13945 /* Delete the setter too. */
13948 PATTERN (cc0_setter
) = pc_rtx
;
13949 old_notes
= REG_NOTES (cc0_setter
);
13950 REG_NOTES (cc0_setter
) = NULL
;
13952 distribute_notes (old_notes
, cc0_setter
,
13954 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13955 distribute_links (LOG_LINKS (cc0_setter
));
13957 SET_INSN_DELETED (cc0_setter
);
13958 if (cc0_setter
== i2
)
13964 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13966 /* If there isn't already a REG_UNUSED note, put one
13967 here. Do not place a REG_DEAD note, even if
13968 the register is also used here; that would not
13969 match the algorithm used in lifetime analysis
13970 and can cause the consistency check in the
13971 scheduler to fail. */
13972 if (! find_regno_note (tem_insn
, REG_UNUSED
,
13973 REGNO (XEXP (note
, 0))))
13978 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
13979 || (CALL_P (tem_insn
)
13980 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
13984 /* If we are doing a 3->2 combination, and we have a
13985 register which formerly died in i3 and was not used
13986 by i2, which now no longer dies in i3 and is used in
13987 i2 but does not die in i2, and place is between i2
13988 and i3, then we may need to move a link from place to
13990 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13992 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13993 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13995 struct insn_link
*links
= LOG_LINKS (place
);
13996 LOG_LINKS (place
) = NULL
;
13997 distribute_links (links
);
14002 if (tem_insn
== BB_HEAD (bb
))
14008 /* If the register is set or already dead at PLACE, we needn't do
14009 anything with this note if it is still a REG_DEAD note.
14010 We check here if it is set at all, not if is it totally replaced,
14011 which is what `dead_or_set_p' checks, so also check for it being
14014 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14016 unsigned int regno
= REGNO (XEXP (note
, 0));
14017 reg_stat_type
*rsp
= ®_stat
[regno
];
14019 if (dead_or_set_p (place
, XEXP (note
, 0))
14020 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14022 /* Unless the register previously died in PLACE, clear
14023 last_death. [I no longer understand why this is
14025 if (rsp
->last_death
!= place
)
14026 rsp
->last_death
= 0;
14030 rsp
->last_death
= place
;
14032 /* If this is a death note for a hard reg that is occupying
14033 multiple registers, ensure that we are still using all
14034 parts of the object. If we find a piece of the object
14035 that is unused, we must arrange for an appropriate REG_DEAD
14036 note to be added for it. However, we can't just emit a USE
14037 and tag the note to it, since the register might actually
14038 be dead; so we recourse, and the recursive call then finds
14039 the previous insn that used this register. */
14041 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14043 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14044 bool all_used
= true;
14047 for (i
= regno
; i
< endregno
; i
++)
14048 if ((! refers_to_regno_p (i
, PATTERN (place
))
14049 && ! find_regno_fusage (place
, USE
, i
))
14050 || dead_or_set_regno_p (place
, i
))
14058 /* Put only REG_DEAD notes for pieces that are
14059 not already dead or set. */
14061 for (i
= regno
; i
< endregno
;
14062 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14064 rtx piece
= regno_reg_rtx
[i
];
14065 basic_block bb
= this_basic_block
;
14067 if (! dead_or_set_p (place
, piece
)
14068 && ! reg_bitfield_target_p (piece
,
14071 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14074 distribute_notes (new_note
, place
, place
,
14075 NULL
, NULL_RTX
, NULL_RTX
,
14078 else if (! refers_to_regno_p (i
, PATTERN (place
))
14079 && ! find_regno_fusage (place
, USE
, i
))
14080 for (tem_insn
= PREV_INSN (place
); ;
14081 tem_insn
= PREV_INSN (tem_insn
))
14083 if (!NONDEBUG_INSN_P (tem_insn
))
14085 if (tem_insn
== BB_HEAD (bb
))
14089 if (dead_or_set_p (tem_insn
, piece
)
14090 || reg_bitfield_target_p (piece
,
14091 PATTERN (tem_insn
)))
14093 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14106 /* Any other notes should not be present at this point in the
14108 gcc_unreachable ();
14113 XEXP (note
, 1) = REG_NOTES (place
);
14114 REG_NOTES (place
) = note
;
14118 add_shallow_copy_of_reg_note (place2
, note
);
14122 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14123 I3, I2, and I1 to new locations. This is also called to add a link
14124 pointing at I3 when I3's destination is changed. */
14127 distribute_links (struct insn_link
*links
)
14129 struct insn_link
*link
, *next_link
;
14131 for (link
= links
; link
; link
= next_link
)
14133 rtx_insn
*place
= 0;
14137 next_link
= link
->next
;
14139 /* If the insn that this link points to is a NOTE, ignore it. */
14140 if (NOTE_P (link
->insn
))
14144 rtx pat
= PATTERN (link
->insn
);
14145 if (GET_CODE (pat
) == SET
)
14147 else if (GET_CODE (pat
) == PARALLEL
)
14150 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14152 set
= XVECEXP (pat
, 0, i
);
14153 if (GET_CODE (set
) != SET
)
14156 reg
= SET_DEST (set
);
14157 while (GET_CODE (reg
) == ZERO_EXTRACT
14158 || GET_CODE (reg
) == STRICT_LOW_PART
14159 || GET_CODE (reg
) == SUBREG
)
14160 reg
= XEXP (reg
, 0);
14165 if (REGNO (reg
) == link
->regno
)
14168 if (i
== XVECLEN (pat
, 0))
14174 reg
= SET_DEST (set
);
14176 while (GET_CODE (reg
) == ZERO_EXTRACT
14177 || GET_CODE (reg
) == STRICT_LOW_PART
14178 || GET_CODE (reg
) == SUBREG
)
14179 reg
= XEXP (reg
, 0);
14181 /* A LOG_LINK is defined as being placed on the first insn that uses
14182 a register and points to the insn that sets the register. Start
14183 searching at the next insn after the target of the link and stop
14184 when we reach a set of the register or the end of the basic block.
14186 Note that this correctly handles the link that used to point from
14187 I3 to I2. Also note that not much searching is typically done here
14188 since most links don't point very far away. */
14190 for (insn
= NEXT_INSN (link
->insn
);
14191 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14192 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14193 insn
= NEXT_INSN (insn
))
14194 if (DEBUG_INSN_P (insn
))
14196 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14198 if (reg_referenced_p (reg
, PATTERN (insn
)))
14202 else if (CALL_P (insn
)
14203 && find_reg_fusage (insn
, USE
, reg
))
14208 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14211 /* If we found a place to put the link, place it there unless there
14212 is already a link to the same insn as LINK at that point. */
14216 struct insn_link
*link2
;
14218 FOR_EACH_LOG_LINK (link2
, place
)
14219 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14224 link
->next
= LOG_LINKS (place
);
14225 LOG_LINKS (place
) = link
;
14227 /* Set added_links_insn to the earliest insn we added a
14229 if (added_links_insn
== 0
14230 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14231 added_links_insn
= place
;
14237 /* Check for any register or memory mentioned in EQUIV that is not
14238 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14239 of EXPR where some registers may have been replaced by constants. */
14242 unmentioned_reg_p (rtx equiv
, rtx expr
)
14244 subrtx_iterator::array_type array
;
14245 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14247 const_rtx x
= *iter
;
14248 if ((REG_P (x
) || MEM_P (x
))
14249 && !reg_mentioned_p (x
, expr
))
14255 DEBUG_FUNCTION
void
14256 dump_combine_stats (FILE *file
)
14260 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14261 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14265 dump_combine_total_stats (FILE *file
)
14269 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14270 total_attempts
, total_merges
, total_extras
, total_successes
);
14273 /* Try combining insns through substitution. */
14274 static unsigned int
14275 rest_of_handle_combine (void)
14277 int rebuild_jump_labels_after_combine
;
14279 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14280 df_note_add_problem ();
14283 regstat_init_n_sets_and_refs ();
14284 reg_n_sets_max
= max_reg_num ();
14286 rebuild_jump_labels_after_combine
14287 = combine_instructions (get_insns (), max_reg_num ());
14289 /* Combining insns may have turned an indirect jump into a
14290 direct jump. Rebuild the JUMP_LABEL fields of jumping
14292 if (rebuild_jump_labels_after_combine
)
14294 timevar_push (TV_JUMP
);
14295 rebuild_jump_labels (get_insns ());
14297 timevar_pop (TV_JUMP
);
14300 regstat_free_n_sets_and_refs ();
14306 const pass_data pass_data_combine
=
14308 RTL_PASS
, /* type */
14309 "combine", /* name */
14310 OPTGROUP_NONE
, /* optinfo_flags */
14311 TV_COMBINE
, /* tv_id */
14312 PROP_cfglayout
, /* properties_required */
14313 0, /* properties_provided */
14314 0, /* properties_destroyed */
14315 0, /* todo_flags_start */
14316 TODO_df_finish
, /* todo_flags_finish */
14319 class pass_combine
: public rtl_opt_pass
14322 pass_combine (gcc::context
*ctxt
)
14323 : rtl_opt_pass (pass_data_combine
, ctxt
)
14326 /* opt_pass methods: */
14327 virtual bool gate (function
*) { return (optimize
> 0); }
14328 virtual unsigned int execute (function
*)
14330 return rest_of_handle_combine ();
14333 }; // class pass_combine
14335 } // anon namespace
14338 make_pass_combine (gcc::context
*ctxt
)
14340 return new pass_combine (ctxt
);