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1 /* IA-32 common hooks.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
24 #include "tm.h"
25 #include "memmodel.h"
26 #include "tm_p.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
29 #include "opts.h"
30 #include "flags.h"
31
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
34
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
81 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS
82 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW
83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
85 #define OPTION_MASK_ISA_AVX512VNNI_SET \
86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
89 #define OPTION_MASK_ISA_AVX512BITALG_SET \
90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
91 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
92 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
93 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
94 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
95 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
96 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
97 #define OPTION_MASK_ISA_XSAVES_SET \
98 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE)
99 #define OPTION_MASK_ISA_XSAVEC_SET \
100 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE)
101 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
102
103 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
104 as -msse4.2. */
105 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
106
107 #define OPTION_MASK_ISA_SSE4A_SET \
108 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
109 #define OPTION_MASK_ISA_FMA4_SET \
110 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
111 | OPTION_MASK_ISA_AVX_SET)
112 #define OPTION_MASK_ISA_XOP_SET \
113 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
114 #define OPTION_MASK_ISA_LWP_SET \
115 OPTION_MASK_ISA_LWP
116
117 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
118 #define OPTION_MASK_ISA_AES_SET \
119 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
120 #define OPTION_MASK_ISA_SHA_SET \
121 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
122 #define OPTION_MASK_ISA_PCLMUL_SET \
123 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
124
125 #define OPTION_MASK_ISA_ABM_SET \
126 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
127
128 #define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG
129 #define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD
130 #define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX
131 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
132 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
133 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
134 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
135 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
136 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
137 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
138 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
139 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
140
141 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
142 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
143 #define OPTION_MASK_ISA_F16C_SET \
144 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
145 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
146 #define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO
147 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
148 #define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID
149 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
150 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
151 #define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES
152 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
153 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
154 #define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B
155 #define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG
156
157 /* Define a set of ISAs which aren't available when a given ISA is
158 disabled. MMX and SSE ISAs are handled separately. */
159
160 #define OPTION_MASK_ISA_MMX_UNSET \
161 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
162 #define OPTION_MASK_ISA_3DNOW_UNSET \
163 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
164 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
165
166 #define OPTION_MASK_ISA_SSE_UNSET \
167 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
168 #define OPTION_MASK_ISA_SSE2_UNSET \
169 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
170 #define OPTION_MASK_ISA_SSE3_UNSET \
171 (OPTION_MASK_ISA_SSE3 \
172 | OPTION_MASK_ISA_SSSE3_UNSET \
173 | OPTION_MASK_ISA_SSE4A_UNSET )
174 #define OPTION_MASK_ISA_SSSE3_UNSET \
175 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
176 #define OPTION_MASK_ISA_SSE4_1_UNSET \
177 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
178 #define OPTION_MASK_ISA_SSE4_2_UNSET \
179 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
180 #define OPTION_MASK_ISA_AVX_UNSET \
181 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
182 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
183 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
184 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
185 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
186 #define OPTION_MASK_ISA_XSAVE_UNSET \
187 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET)
188 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
189 #define OPTION_MASK_ISA_AVX2_UNSET \
190 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
191 #define OPTION_MASK_ISA_AVX512F_UNSET \
192 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
193 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
194 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
195 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
196 | OPTION_MASK_ISA_AVX512VNNI_UNSET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
197 | OPTION_MASK_ISA_AVX512BITALG_UNSET)
198 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
199 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
200 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
201 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
202 #define OPTION_MASK_ISA_AVX512BW_UNSET \
203 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
204 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
205 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
206 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
207 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS
208 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW
209 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
210 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
211 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
212 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
213 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
214 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
215 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
216 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
217 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
218 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
219 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
220 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
221 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
222 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
223 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
224 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
225 #define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID
226 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
227 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
228 #define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES
229 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
230 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
231 #define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B
232 #define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG
233
234 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
235 as -mno-sse4.1. */
236 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
237
238 #define OPTION_MASK_ISA_SSE4A_UNSET \
239 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
240
241 #define OPTION_MASK_ISA_FMA4_UNSET \
242 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
243 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
244 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
245
246 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
247 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
248 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
249 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
250 #define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG
251 #define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD
252 #define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX
253 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
254 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
255 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
256 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
257 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
258 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
259 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
260 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
261 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
262
263 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
264 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
265 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
266
267 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
268 (OPTION_MASK_ISA_MMX_UNSET \
269 | OPTION_MASK_ISA_SSE_UNSET)
270
271 #define OPTION_MASK_ISA2_AVX512F_UNSET \
272 (OPTION_MASK_ISA_AVX5124FMAPS_UNSET | OPTION_MASK_ISA_AVX5124VNNIW_UNSET)
273 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
274 (OPTION_MASK_ISA2_AVX512F_UNSET | OPTION_MASK_ISA_MPX)
275
276 /* Implement TARGET_HANDLE_OPTION. */
277
278 bool
279 ix86_handle_option (struct gcc_options *opts,
280 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
281 const struct cl_decoded_option *decoded,
282 location_t loc)
283 {
284 size_t code = decoded->opt_index;
285 int value = decoded->value;
286
287 switch (code)
288 {
289 case OPT_mgeneral_regs_only:
290 if (value)
291 {
292 /* Disable MPX, MMX, SSE and x87 instructions if only
293 general registers are allowed. */
294 opts->x_ix86_isa_flags
295 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
296 opts->x_ix86_isa_flags2
297 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
298 opts->x_ix86_isa_flags_explicit
299 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
300 opts->x_ix86_isa_flags2_explicit
301 |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
302
303 opts->x_target_flags &= ~MASK_80387;
304 }
305 else
306 gcc_unreachable ();
307 return true;
308
309 case OPT_mmmx:
310 if (value)
311 {
312 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
313 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
314 }
315 else
316 {
317 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
318 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
319 }
320 return true;
321
322 case OPT_m3dnow:
323 if (value)
324 {
325 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
326 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
327 }
328 else
329 {
330 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
331 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
332 }
333 return true;
334
335 case OPT_m3dnowa:
336 if (value)
337 {
338 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
339 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
340 }
341 else
342 {
343 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
344 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
345 }
346 return true;
347
348 case OPT_msse:
349 if (value)
350 {
351 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
352 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
353 }
354 else
355 {
356 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
357 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
358 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
359 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
360 }
361 return true;
362
363 case OPT_msse2:
364 if (value)
365 {
366 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
367 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
368 }
369 else
370 {
371 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
372 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
373 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
374 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
375 }
376 return true;
377
378 case OPT_msse3:
379 if (value)
380 {
381 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
382 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
383 }
384 else
385 {
386 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
387 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
388 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
389 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
390 }
391 return true;
392
393 case OPT_mssse3:
394 if (value)
395 {
396 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
397 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
398 }
399 else
400 {
401 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
402 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
403 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
404 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
405 }
406 return true;
407
408 case OPT_msse4_1:
409 if (value)
410 {
411 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
412 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
413 }
414 else
415 {
416 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
417 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
418 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
419 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
420 }
421 return true;
422
423 case OPT_msse4_2:
424 if (value)
425 {
426 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
427 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
428 }
429 else
430 {
431 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
432 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
433 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
434 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
435 }
436 return true;
437
438 case OPT_mavx:
439 if (value)
440 {
441 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
442 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
443 }
444 else
445 {
446 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
447 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
448 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
449 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
450 }
451 return true;
452
453 case OPT_mavx2:
454 if (value)
455 {
456 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
457 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
458 }
459 else
460 {
461 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
462 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
463 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
464 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
465 }
466 return true;
467
468 case OPT_mavx512f:
469 if (value)
470 {
471 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
472 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
473 }
474 else
475 {
476 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
477 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
478 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
479 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
480 }
481 return true;
482
483 case OPT_mavx512cd:
484 if (value)
485 {
486 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
487 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
488 }
489 else
490 {
491 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
492 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
493 }
494 return true;
495
496 case OPT_mavx512pf:
497 if (value)
498 {
499 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
500 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
501 }
502 else
503 {
504 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
505 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
506 }
507 return true;
508
509 case OPT_mavx512er:
510 if (value)
511 {
512 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
513 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
514 }
515 else
516 {
517 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
518 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
519 }
520 return true;
521
522 case OPT_mrdpid:
523 if (value)
524 {
525 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET;
526 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET;
527 }
528 else
529 {
530 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET;
531 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET;
532 }
533 return true;
534
535 case OPT_mgfni:
536 if (value)
537 {
538 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
539 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
540 }
541 else
542 {
543 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
544 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
545 }
546 return true;
547
548 case OPT_mshstk:
549 if (value)
550 {
551 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
552 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
553 }
554 else
555 {
556 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
557 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
558 }
559 return true;
560
561 case OPT_mvaes:
562 if (value)
563 {
564 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET;
565 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET;
566 }
567 else
568 {
569 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET;
570 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET;
571 }
572 return true;
573
574 case OPT_mvpclmulqdq:
575 if (value)
576 {
577 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
578 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
579 }
580 else
581 {
582 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
583 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
584 }
585 return true;
586
587 case OPT_mmovdiri:
588 if (value)
589 {
590 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
591 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
592 }
593 else
594 {
595 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
596 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
597 }
598 return true;
599
600 case OPT_mmovdir64b:
601 if (value)
602 {
603 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET;
604 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET;
605 }
606 else
607 {
608 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET;
609 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET;
610 }
611 return true;
612
613 case OPT_mwaitpkg:
614 if (value)
615 {
616 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WAITPKG_SET;
617 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_SET;
618 }
619 else
620 {
621 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WAITPKG_UNSET;
622 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_UNSET;
623 }
624 return true;
625
626 case OPT_mavx5124fmaps:
627 if (value)
628 {
629 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
630 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
631 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
632 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
633 }
634 else
635 {
636 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
637 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
638 }
639 return true;
640
641 case OPT_mavx5124vnniw:
642 if (value)
643 {
644 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
645 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
646 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
647 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
648 }
649 else
650 {
651 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
652 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
653 }
654 return true;
655
656 case OPT_mavx512vbmi2:
657 if (value)
658 {
659 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
660 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
661 }
662 else
663 {
664 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
665 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
666 }
667 return true;
668
669 case OPT_mavx512vnni:
670 if (value)
671 {
672 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
673 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
674 }
675 else
676 {
677 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
678 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
679 }
680 return true;
681
682 case OPT_mavx512vpopcntdq:
683 if (value)
684 {
685 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
686 opts->x_ix86_isa_flags_explicit
687 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
688 }
689 else
690 {
691 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
692 opts->x_ix86_isa_flags_explicit
693 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
694 }
695 return true;
696
697 case OPT_mavx512bitalg:
698 if (value)
699 {
700 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
701 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
702 }
703 else
704 {
705 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
706 opts->x_ix86_isa_flags_explicit
707 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
708 }
709 return true;
710
711 case OPT_msgx:
712 if (value)
713 {
714 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET;
715 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET;
716 }
717 else
718 {
719 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET;
720 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET;
721 }
722 return true;
723
724 case OPT_mpconfig:
725 if (value)
726 {
727 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET;
728 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET;
729 }
730 else
731 {
732 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET;
733 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET;
734 }
735 return true;
736
737 case OPT_mwbnoinvd:
738 if (value)
739 {
740 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET;
741 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET;
742 }
743 else
744 {
745 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET;
746 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET;
747 }
748 return true;
749
750 case OPT_mavx512dq:
751 if (value)
752 {
753 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
754 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
755 }
756 else
757 {
758 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
759 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
760 }
761 return true;
762
763 case OPT_mavx512bw:
764 if (value)
765 {
766 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
767 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
768 }
769 else
770 {
771 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
772 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
773 }
774 return true;
775
776 case OPT_mavx512vl:
777 if (value)
778 {
779 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
780 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
781 }
782 else
783 {
784 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
785 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
786 }
787 return true;
788
789 case OPT_mavx512ifma:
790 if (value)
791 {
792 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
793 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
794 }
795 else
796 {
797 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
798 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
799 }
800 return true;
801
802 case OPT_mavx512vbmi:
803 if (value)
804 {
805 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
806 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
807 }
808 else
809 {
810 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
811 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
812 }
813 return true;
814
815 case OPT_mfma:
816 if (value)
817 {
818 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
819 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
820 }
821 else
822 {
823 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
824 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
825 }
826 return true;
827
828 case OPT_mrtm:
829 if (value)
830 {
831 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
832 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
833 }
834 else
835 {
836 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
837 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
838 }
839 return true;
840
841 case OPT_msse4:
842 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
843 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
844 return true;
845
846 case OPT_mno_sse4:
847 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
848 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
849 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
850 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
851 return true;
852
853 case OPT_msse4a:
854 if (value)
855 {
856 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
857 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
858 }
859 else
860 {
861 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
862 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
863 }
864 return true;
865
866 case OPT_mfma4:
867 if (value)
868 {
869 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
870 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
871 }
872 else
873 {
874 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
875 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
876 }
877 return true;
878
879 case OPT_mxop:
880 if (value)
881 {
882 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
883 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
884 }
885 else
886 {
887 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
888 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
889 }
890 return true;
891
892 case OPT_mlwp:
893 if (value)
894 {
895 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
896 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
897 }
898 else
899 {
900 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
901 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
902 }
903 return true;
904
905 case OPT_mabm:
906 if (value)
907 {
908 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
909 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
910 }
911 else
912 {
913 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
914 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
915 }
916 return true;
917
918 case OPT_mbmi:
919 if (value)
920 {
921 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
922 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
923 }
924 else
925 {
926 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
927 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
928 }
929 return true;
930
931 case OPT_mbmi2:
932 if (value)
933 {
934 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
935 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
936 }
937 else
938 {
939 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
940 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
941 }
942 return true;
943
944 case OPT_mlzcnt:
945 if (value)
946 {
947 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
948 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
949 }
950 else
951 {
952 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
953 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
954 }
955 return true;
956
957 case OPT_mtbm:
958 if (value)
959 {
960 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
961 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
962 }
963 else
964 {
965 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
966 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
967 }
968 return true;
969
970 case OPT_mpopcnt:
971 if (value)
972 {
973 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
974 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
975 }
976 else
977 {
978 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
979 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
980 }
981 return true;
982
983 case OPT_msahf:
984 if (value)
985 {
986 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
987 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
988 }
989 else
990 {
991 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
992 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
993 }
994 return true;
995
996 case OPT_mcx16:
997 if (value)
998 {
999 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET;
1000 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET;
1001 }
1002 else
1003 {
1004 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET;
1005 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET;
1006 }
1007 return true;
1008
1009 case OPT_mmovbe:
1010 if (value)
1011 {
1012 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET;
1013 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET;
1014 }
1015 else
1016 {
1017 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET;
1018 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
1019 }
1020 return true;
1021
1022 case OPT_mcrc32:
1023 if (value)
1024 {
1025 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1026 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1027 }
1028 else
1029 {
1030 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1031 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1032 }
1033 return true;
1034
1035 case OPT_maes:
1036 if (value)
1037 {
1038 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1039 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1040 }
1041 else
1042 {
1043 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1044 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1045 }
1046 return true;
1047
1048 case OPT_msha:
1049 if (value)
1050 {
1051 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1052 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1053 }
1054 else
1055 {
1056 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1057 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1058 }
1059 return true;
1060
1061 case OPT_mpclmul:
1062 if (value)
1063 {
1064 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1065 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1066 }
1067 else
1068 {
1069 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1070 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1071 }
1072 return true;
1073
1074 case OPT_mfsgsbase:
1075 if (value)
1076 {
1077 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1078 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1079 }
1080 else
1081 {
1082 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1083 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1084 }
1085 return true;
1086
1087 case OPT_mrdrnd:
1088 if (value)
1089 {
1090 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1091 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1092 }
1093 else
1094 {
1095 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1096 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1097 }
1098 return true;
1099
1100 case OPT_mf16c:
1101 if (value)
1102 {
1103 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1104 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1105 }
1106 else
1107 {
1108 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1109 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1110 }
1111 return true;
1112
1113 case OPT_mfxsr:
1114 if (value)
1115 {
1116 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1117 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1118 }
1119 else
1120 {
1121 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1122 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1123 }
1124 return true;
1125
1126 case OPT_mxsave:
1127 if (value)
1128 {
1129 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1130 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1131 }
1132 else
1133 {
1134 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1135 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1136 }
1137 return true;
1138
1139 case OPT_mxsaveopt:
1140 if (value)
1141 {
1142 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1143 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1144 }
1145 else
1146 {
1147 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1148 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1149 }
1150 return true;
1151
1152 case OPT_mxsavec:
1153 if (value)
1154 {
1155 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1156 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1157 }
1158 else
1159 {
1160 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1161 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1162 }
1163 return true;
1164
1165 case OPT_mxsaves:
1166 if (value)
1167 {
1168 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1169 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1170 }
1171 else
1172 {
1173 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1174 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1175 }
1176 return true;
1177
1178 case OPT_mrdseed:
1179 if (value)
1180 {
1181 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1182 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1183 }
1184 else
1185 {
1186 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1187 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1188 }
1189 return true;
1190
1191 case OPT_mprfchw:
1192 if (value)
1193 {
1194 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1195 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1196 }
1197 else
1198 {
1199 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1200 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1201 }
1202 return true;
1203
1204 case OPT_madx:
1205 if (value)
1206 {
1207 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1208 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1209 }
1210 else
1211 {
1212 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1213 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1214 }
1215 return true;
1216
1217 case OPT_mprefetchwt1:
1218 if (value)
1219 {
1220 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1221 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1222 }
1223 else
1224 {
1225 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1226 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1227 }
1228 return true;
1229
1230 case OPT_mclflushopt:
1231 if (value)
1232 {
1233 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1234 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1235 }
1236 else
1237 {
1238 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1239 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1240 }
1241 return true;
1242
1243 case OPT_mclwb:
1244 if (value)
1245 {
1246 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1247 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1248 }
1249 else
1250 {
1251 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1252 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1253 }
1254 return true;
1255
1256 case OPT_mmwaitx:
1257 if (value)
1258 {
1259 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET;
1260 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET;
1261 }
1262 else
1263 {
1264 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET;
1265 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET;
1266 }
1267 return true;
1268
1269 case OPT_mclzero:
1270 if (value)
1271 {
1272 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET;
1273 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET;
1274 }
1275 else
1276 {
1277 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET;
1278 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET;
1279 }
1280 return true;
1281
1282 case OPT_mpku:
1283 if (value)
1284 {
1285 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1286 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1287 }
1288 else
1289 {
1290 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1291 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1292 }
1293 return true;
1294
1295
1296 /* Comes from final.c -- no real reason to change it. */
1297 #define MAX_CODE_ALIGN 16
1298
1299 case OPT_malign_loops_:
1300 warning_at (loc, 0, "-malign-loops is obsolete, use -falign-loops");
1301 if (value > MAX_CODE_ALIGN)
1302 error_at (loc, "-malign-loops=%d is not between 0 and %d",
1303 value, MAX_CODE_ALIGN);
1304 else
1305 opts->x_align_loops = 1 << value;
1306 return true;
1307
1308 case OPT_malign_jumps_:
1309 warning_at (loc, 0, "-malign-jumps is obsolete, use -falign-jumps");
1310 if (value > MAX_CODE_ALIGN)
1311 error_at (loc, "-malign-jumps=%d is not between 0 and %d",
1312 value, MAX_CODE_ALIGN);
1313 else
1314 opts->x_align_jumps = 1 << value;
1315 return true;
1316
1317 case OPT_malign_functions_:
1318 warning_at (loc, 0,
1319 "-malign-functions is obsolete, use -falign-functions");
1320 if (value > MAX_CODE_ALIGN)
1321 error_at (loc, "-malign-functions=%d is not between 0 and %d",
1322 value, MAX_CODE_ALIGN);
1323 else
1324 opts->x_align_functions = 1 << value;
1325 return true;
1326
1327 case OPT_mbranch_cost_:
1328 if (value > 5)
1329 {
1330 error_at (loc, "-mbranch-cost=%d is not between 0 and 5", value);
1331 opts->x_ix86_branch_cost = 5;
1332 }
1333 return true;
1334
1335 default:
1336 return true;
1337 }
1338 }
1339
1340 static const struct default_options ix86_option_optimization_table[] =
1341 {
1342 /* Enable redundant extension instructions removal at -O2 and higher. */
1343 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
1344 /* Enable function splitting at -O2 and higher. */
1345 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
1346 /* The STC algorithm produces the smallest code at -Os, for x86. */
1347 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1348 REORDER_BLOCKS_ALGORITHM_STC },
1349 /* Turn off -fschedule-insns by default. It tends to make the
1350 problem with not enough registers even worse. */
1351 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1352
1353 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1354 SUBTARGET_OPTIMIZATION_OPTIONS,
1355 #endif
1356 { OPT_LEVELS_NONE, 0, NULL, 0 }
1357 };
1358
1359 /* Implement TARGET_OPTION_INIT_STRUCT. */
1360
1361 static void
1362 ix86_option_init_struct (struct gcc_options *opts)
1363 {
1364 if (TARGET_MACHO)
1365 /* The Darwin libraries never set errno, so we might as well
1366 avoid calling them when that's the only reason we would. */
1367 opts->x_flag_errno_math = 0;
1368
1369 opts->x_flag_pcc_struct_return = 2;
1370 opts->x_flag_asynchronous_unwind_tables = 2;
1371 }
1372
1373 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1374 field in the TCB, so they can not be used together. */
1375
1376 static bool
1377 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
1378 struct gcc_options *opts ATTRIBUTE_UNUSED)
1379 {
1380 bool ret = true;
1381
1382 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
1383 if (report)
1384 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1385 ret = false;
1386 #else
1387 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1388 {
1389 if (report)
1390 error ("%<-fsplit-stack%> requires "
1391 "assembler support for CFI directives");
1392 ret = false;
1393 }
1394 #endif
1395
1396 return ret;
1397 }
1398
1399 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
1400
1401 static enum unwind_info_type
1402 i386_except_unwind_info (struct gcc_options *opts)
1403 {
1404 /* Honor the --enable-sjlj-exceptions configure switch. */
1405 #ifdef CONFIG_SJLJ_EXCEPTIONS
1406 if (CONFIG_SJLJ_EXCEPTIONS)
1407 return UI_SJLJ;
1408 #endif
1409
1410 /* On windows 64, prefer SEH exceptions over anything else. */
1411 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1412 return UI_SEH;
1413
1414 if (DWARF2_UNWIND_INFO)
1415 return UI_DWARF2;
1416
1417 return UI_SJLJ;
1418 }
1419
1420 #undef TARGET_EXCEPT_UNWIND_INFO
1421 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1422
1423 #undef TARGET_DEFAULT_TARGET_FLAGS
1424 #define TARGET_DEFAULT_TARGET_FLAGS \
1425 (TARGET_DEFAULT \
1426 | TARGET_SUBTARGET_DEFAULT \
1427 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1428
1429 #undef TARGET_HANDLE_OPTION
1430 #define TARGET_HANDLE_OPTION ix86_handle_option
1431
1432 #undef TARGET_OPTION_OPTIMIZATION_TABLE
1433 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1434 #undef TARGET_OPTION_INIT_STRUCT
1435 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1436
1437 #undef TARGET_SUPPORTS_SPLIT_STACK
1438 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1439
1440 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;