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1 /* IA-32 common hooks.
2 Copyright (C) 1988-2023 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
24 #include "tm.h"
25 #include "memmodel.h"
26 #include "tm_p.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
29 #include "opts.h"
30 #include "flags.h"
31
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
34
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA
80 #define OPTION_MASK_ISA_AVX512VBMI_SET \
81 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
82 #define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS
83 #define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW
84 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
85 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
86 #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
87 #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
88 #define OPTION_MASK_ISA_AVX512VNNI_SET \
89 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
90 #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
91 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
92 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
93 #define OPTION_MASK_ISA_AVX512BITALG_SET \
94 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
95 #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
96 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
97 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
98 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
99 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
100 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
101 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
102 #define OPTION_MASK_ISA_XSAVES_SET \
103 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
104 #define OPTION_MASK_ISA_XSAVEC_SET \
105 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
106 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
107 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
108 #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
109 #define OPTION_MASK_ISA2_AMX_INT8_SET \
110 (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8)
111 #define OPTION_MASK_ISA2_AMX_BF16_SET \
112 (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_BF16)
113 #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8
114 #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT
115 #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD
116 #define OPTION_MASK_ISA2_AMX_FP16_SET \
117 (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_FP16)
118 #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI
119 #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
120
121 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
122 as -msse4.2. */
123 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
124
125 #define OPTION_MASK_ISA_SSE4A_SET \
126 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
127 #define OPTION_MASK_ISA_FMA4_SET \
128 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
129 | OPTION_MASK_ISA_AVX_SET)
130 #define OPTION_MASK_ISA_XOP_SET \
131 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
132 #define OPTION_MASK_ISA_LWP_SET \
133 OPTION_MASK_ISA_LWP
134
135 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
136 #define OPTION_MASK_ISA_AES_SET \
137 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
138 #define OPTION_MASK_ISA_SHA_SET \
139 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
140 #define OPTION_MASK_ISA_PCLMUL_SET \
141 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
142
143 #define OPTION_MASK_ISA_ABM_SET \
144 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
145
146 #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
147 #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
148 #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
149 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
150 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
151 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
152 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
153 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
154 #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
155 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
156 #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
157 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
158
159 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
160 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
161 #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
162 #define OPTION_MASK_ISA_F16C_SET \
163 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
164 #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
165 #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
166 #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
167 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
168 #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
169 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
170 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
171 #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
172 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
173 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
174 #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
175 #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
176 #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
177 #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
178 #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
179 #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
180 #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
181 #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
182 #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
183 #define OPTION_MASK_ISA2_WIDEKL_SET \
184 (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
185
186 /* Define a set of ISAs which aren't available when a given ISA is
187 disabled. MMX and SSE ISAs are handled separately. */
188
189 #define OPTION_MASK_ISA_MMX_UNSET \
190 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
191 #define OPTION_MASK_ISA_3DNOW_UNSET \
192 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
193 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
194
195 #define OPTION_MASK_ISA_SSE_UNSET \
196 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
197 #define OPTION_MASK_ISA_SSE2_UNSET \
198 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
199 #define OPTION_MASK_ISA_SSE3_UNSET \
200 (OPTION_MASK_ISA_SSE3 \
201 | OPTION_MASK_ISA_SSSE3_UNSET \
202 | OPTION_MASK_ISA_SSE4A_UNSET )
203 #define OPTION_MASK_ISA_SSSE3_UNSET \
204 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
205 #define OPTION_MASK_ISA_SSE4_1_UNSET \
206 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
207 #define OPTION_MASK_ISA_SSE4_2_UNSET \
208 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
209 #define OPTION_MASK_ISA_AVX_UNSET \
210 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
211 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
212 | OPTION_MASK_ISA_AVX2_UNSET )
213 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
214 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
215 #define OPTION_MASK_ISA_XSAVE_UNSET \
216 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
217 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
218 | OPTION_MASK_ISA_AVX_UNSET)
219 #define OPTION_MASK_ISA2_XSAVE_UNSET \
220 (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
221 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
222 #define OPTION_MASK_ISA_AVX2_UNSET \
223 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
224 #define OPTION_MASK_ISA2_AVX2_UNSET \
225 (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
226 | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
227 | OPTION_MASK_ISA2_AVX512F_UNSET)
228 #define OPTION_MASK_ISA_AVX512F_UNSET \
229 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
230 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
231 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
232 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
233 | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
234 | OPTION_MASK_ISA_AVX512VNNI_UNSET \
235 | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
236 | OPTION_MASK_ISA_AVX512BITALG_UNSET)
237 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
238 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
239 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
240 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
241 #define OPTION_MASK_ISA_AVX512BW_UNSET \
242 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
243 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
244 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
245 #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA
246 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
247 #define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS
248 #define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW
249 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
250 #define OPTION_MASK_ISA_AVX512FP16_UNSET OPTION_MASK_ISA_AVX512BW_UNSET
251 #define OPTION_MASK_ISA2_AVX512FP16_UNSET OPTION_MASK_ISA2_AVX512FP16
252 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
253 #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
254 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
255 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
256 #define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
257 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
258 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
259 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
260 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
261 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
262 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
263 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
264 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
265 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
266 #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
267 #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
268 #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
269 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
270 #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
271 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
272 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
273 #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
274 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
275 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
276 #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
277 #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
278 #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
279 #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
280 #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
281 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
282 #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
283 #define OPTION_MASK_ISA2_AMX_TILE_UNSET \
284 (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
285 | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET)
286 #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
287 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
288 #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
289 #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
290 #define OPTION_MASK_ISA2_KL_UNSET \
291 (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
292 #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
293 #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8
294 #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT
295 #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD
296 #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16
297 #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
298 #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
299
300 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
301 as -mno-sse4.1. */
302 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
303
304 #define OPTION_MASK_ISA_SSE4A_UNSET \
305 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
306
307 #define OPTION_MASK_ISA_FMA4_UNSET \
308 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
309 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
310 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
311
312 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
313 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
314 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
315 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
316 #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
317 #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
318 #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
319 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
320 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
321 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
322 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
323 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
324 #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
325 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
326 #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
327 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
328
329 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
330 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
331 #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
332 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
333
334 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
335 (OPTION_MASK_ISA_MMX_UNSET \
336 | OPTION_MASK_ISA_SSE_UNSET)
337
338 #define OPTION_MASK_ISA2_AVX512F_UNSET \
339 (OPTION_MASK_ISA2_AVX512BW_UNSET \
340 | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
341 | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
342 | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
343 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
344 OPTION_MASK_ISA2_SSE_UNSET
345 #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET
346 #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
347 #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
348 #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
349 #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
350 #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
351 #define OPTION_MASK_ISA2_SSE2_UNSET \
352 (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
353 #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
354
355 #define OPTION_MASK_ISA2_AVX512BW_UNSET \
356 (OPTION_MASK_ISA2_AVX512BF16_UNSET \
357 | OPTION_MASK_ISA2_AVX512FP16_UNSET)
358
359 /* Set 1 << value as value of -malign-FLAG option. */
360
361 static void
362 set_malign_value (const char **flag, unsigned value)
363 {
364 char *r = XNEWVEC (char, 6);
365 sprintf (r, "%d", 1 << value);
366 *flag = r;
367 }
368
369 /* Implement TARGET_HANDLE_OPTION. */
370
371 bool
372 ix86_handle_option (struct gcc_options *opts,
373 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
374 const struct cl_decoded_option *decoded,
375 location_t loc)
376 {
377 size_t code = decoded->opt_index;
378 int value = decoded->value;
379
380 switch (code)
381 {
382 case OPT_mgeneral_regs_only:
383 if (value)
384 {
385 HOST_WIDE_INT general_regs_only_flags = 0;
386 HOST_WIDE_INT general_regs_only_flags2 = 0;
387
388 /* NB: Enable the GPR only instructions which are enabled
389 implicitly by SSE ISAs unless they have been disabled
390 explicitly. */
391 if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
392 {
393 if (!TARGET_EXPLICIT_CRC32_P (opts))
394 general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
395 if (!TARGET_EXPLICIT_POPCNT_P (opts))
396 general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
397 }
398 if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
399 {
400 if (!TARGET_EXPLICIT_MWAIT_P (opts))
401 general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
402 }
403
404 /* Disable MMX, SSE and x87 instructions if only
405 general registers are allowed. */
406 opts->x_ix86_isa_flags
407 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
408 opts->x_ix86_isa_flags2
409 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
410 opts->x_ix86_isa_flags |= general_regs_only_flags;
411 opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
412 opts->x_ix86_isa_flags_explicit
413 |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
414 | general_regs_only_flags);
415 opts->x_ix86_isa_flags2_explicit
416 |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
417 | general_regs_only_flags2);
418
419 opts->x_target_flags &= ~MASK_80387;
420 }
421 else
422 gcc_unreachable ();
423 return true;
424
425 case OPT_mmmx:
426 if (value)
427 {
428 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
429 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
430 }
431 else
432 {
433 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
434 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
435 }
436 return true;
437
438 case OPT_m3dnow:
439 if (value)
440 {
441 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
442 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
443 }
444 else
445 {
446 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
447 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
448 }
449 return true;
450
451 case OPT_m3dnowa:
452 if (value)
453 {
454 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
455 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
456 }
457 else
458 {
459 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
460 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
461 }
462 return true;
463
464 case OPT_msse:
465 if (value)
466 {
467 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
468 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
469 }
470 else
471 {
472 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
473 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
474 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
475 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
476 }
477 return true;
478
479 case OPT_msse2:
480 if (value)
481 {
482 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
483 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
484 }
485 else
486 {
487 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
488 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
489 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
490 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
491 }
492 return true;
493
494 case OPT_msse3:
495 if (value)
496 {
497 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
498 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
499 }
500 else
501 {
502 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
503 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
504 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
505 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
506 }
507 return true;
508
509 case OPT_mssse3:
510 if (value)
511 {
512 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
513 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
514 }
515 else
516 {
517 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
518 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
519 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
520 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
521 }
522 return true;
523
524 case OPT_msse4_1:
525 if (value)
526 {
527 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
528 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
529 }
530 else
531 {
532 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
533 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
534 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
535 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
536 }
537 return true;
538
539 case OPT_msse4_2:
540 if (value)
541 {
542 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
543 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
544 }
545 else
546 {
547 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
548 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
549 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
550 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
551 }
552 return true;
553
554 case OPT_mavx:
555 if (value)
556 {
557 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
558 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
559 }
560 else
561 {
562 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
563 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
564 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
565 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
566 }
567 return true;
568
569 case OPT_mavx2:
570 if (value)
571 {
572 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
573 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
574 }
575 else
576 {
577 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
578 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
579 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
580 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
581 }
582 return true;
583
584 case OPT_mavx512f:
585 if (value)
586 {
587 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
588 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
589 }
590 else
591 {
592 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
593 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
594 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
595 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
596 }
597 return true;
598
599 case OPT_mavx512cd:
600 if (value)
601 {
602 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
603 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
604 }
605 else
606 {
607 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
608 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
609 }
610 return true;
611
612 case OPT_mavx512pf:
613 if (value)
614 {
615 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
616 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
617 }
618 else
619 {
620 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
621 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
622 }
623 return true;
624
625 case OPT_mavx512er:
626 if (value)
627 {
628 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
629 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
630 }
631 else
632 {
633 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
634 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
635 }
636 return true;
637
638 case OPT_mrdpid:
639 if (value)
640 {
641 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
642 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
643 }
644 else
645 {
646 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
647 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
648 }
649 return true;
650
651 case OPT_mgfni:
652 if (value)
653 {
654 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
655 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
656 }
657 else
658 {
659 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
660 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
661 }
662 return true;
663
664 case OPT_mshstk:
665 if (value)
666 {
667 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
668 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
669 }
670 else
671 {
672 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
673 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
674 }
675 return true;
676
677 case OPT_mvaes:
678 if (value)
679 {
680 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
681 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
682 }
683 else
684 {
685 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
686 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
687 }
688 return true;
689
690 case OPT_mvpclmulqdq:
691 if (value)
692 {
693 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
694 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
695 }
696 else
697 {
698 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
699 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
700 }
701 return true;
702
703 case OPT_mmovdiri:
704 if (value)
705 {
706 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
707 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
708 }
709 else
710 {
711 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
712 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
713 }
714 return true;
715
716 case OPT_mmovdir64b:
717 if (value)
718 {
719 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
720 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
721 }
722 else
723 {
724 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
725 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
726 }
727 return true;
728
729 case OPT_mcldemote:
730 if (value)
731 {
732 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
733 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
734 }
735 else
736 {
737 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
738 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
739 }
740 return true;
741
742 case OPT_mwaitpkg:
743 if (value)
744 {
745 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
746 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
747 }
748 else
749 {
750 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
751 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
752 }
753 return true;
754
755 case OPT_menqcmd:
756 if (value)
757 {
758 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
759 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
760 }
761 else
762 {
763 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
764 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
765 }
766 return true;
767
768 case OPT_mkl:
769 if (value)
770 {
771 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
772 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
773
774 /* The Keylocker instructions need XMM registers from SSE2. */
775 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
776 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
777 }
778 else
779 {
780 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
781 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
782 }
783 return true;
784
785 case OPT_mwidekl:
786 if (value)
787 {
788 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
789 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
790
791 /* The Widekl instructions need XMM registers from SSE2. */
792 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
793 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
794 }
795 else
796 {
797 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
798 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
799 }
800 return true;
801
802 case OPT_mserialize:
803 if (value)
804 {
805 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
806 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
807 }
808 else
809 {
810 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
811 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
812 }
813 return true;
814
815 case OPT_muintr:
816 if (value)
817 {
818 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
819 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
820 }
821 else
822 {
823 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
824 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
825 }
826 return true;
827
828 case OPT_mhreset:
829 if (value)
830 {
831 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
832 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
833 }
834 else
835 {
836 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
837 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
838 }
839 return true;
840
841 case OPT_mavx5124fmaps:
842 if (value)
843 {
844 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
845 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
846 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
847 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
848 }
849 else
850 {
851 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
852 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
853 }
854 return true;
855
856 case OPT_mavx5124vnniw:
857 if (value)
858 {
859 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
860 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
861 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
862 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
863 }
864 else
865 {
866 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
867 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
868 }
869 return true;
870
871 case OPT_mavx512vbmi2:
872 if (value)
873 {
874 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
875 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
876 }
877 else
878 {
879 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
880 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
881 }
882 return true;
883
884 case OPT_mavx512fp16:
885 if (value)
886 {
887 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET;
888 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET;
889 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET;
890 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET;
891 }
892 else
893 {
894 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
895 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
896 }
897 return true;
898
899 case OPT_mavx512vnni:
900 if (value)
901 {
902 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
903 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
904 }
905 else
906 {
907 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
908 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
909 }
910 return true;
911
912 case OPT_mavx512vpopcntdq:
913 if (value)
914 {
915 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
916 opts->x_ix86_isa_flags_explicit
917 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
918 }
919 else
920 {
921 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
922 opts->x_ix86_isa_flags_explicit
923 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
924 }
925 return true;
926
927 case OPT_mavx512bitalg:
928 if (value)
929 {
930 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
931 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
932 }
933 else
934 {
935 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
936 opts->x_ix86_isa_flags_explicit
937 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
938 }
939 return true;
940
941 case OPT_mavx512bf16:
942 if (value)
943 {
944 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
945 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
946 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
947 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
948 }
949 else
950 {
951 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
952 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
953 }
954 return true;
955
956 case OPT_mavxvnni:
957 if (value)
958 {
959 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
960 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;
961 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
962 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
963 }
964 else
965 {
966 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET;
967 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
968 }
969 return true;
970
971 case OPT_msgx:
972 if (value)
973 {
974 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
975 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
976 }
977 else
978 {
979 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
980 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
981 }
982 return true;
983
984 case OPT_mpconfig:
985 if (value)
986 {
987 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
988 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
989 }
990 else
991 {
992 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
993 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
994 }
995 return true;
996
997 case OPT_mwbnoinvd:
998 if (value)
999 {
1000 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
1001 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
1002 }
1003 else
1004 {
1005 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
1006 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
1007 }
1008 return true;
1009
1010 case OPT_mavx512dq:
1011 if (value)
1012 {
1013 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1014 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1015 }
1016 else
1017 {
1018 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
1019 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
1020 }
1021 return true;
1022
1023 case OPT_mavx512bw:
1024 if (value)
1025 {
1026 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
1027 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
1028 }
1029 else
1030 {
1031 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
1032 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
1033 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
1034 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
1035 }
1036 return true;
1037
1038 case OPT_mavx512vl:
1039 if (value)
1040 {
1041 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
1042 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
1043 }
1044 else
1045 {
1046 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
1047 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
1048 }
1049 return true;
1050
1051 case OPT_mavx512ifma:
1052 if (value)
1053 {
1054 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
1055 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
1056 }
1057 else
1058 {
1059 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
1060 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
1061 }
1062 return true;
1063
1064 case OPT_mavx512vbmi:
1065 if (value)
1066 {
1067 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
1068 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
1069 }
1070 else
1071 {
1072 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
1073 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
1074 }
1075 return true;
1076
1077 case OPT_mavx512vp2intersect:
1078 if (value)
1079 {
1080 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1081 opts->x_ix86_isa_flags2_explicit |=
1082 OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1083 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1084 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1085 }
1086 else
1087 {
1088 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1089 opts->x_ix86_isa_flags2_explicit |=
1090 OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1091 }
1092 return true;
1093
1094 case OPT_mtsxldtrk:
1095 if (value)
1096 {
1097 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1098 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1099 }
1100 else
1101 {
1102 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1103 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1104 }
1105 return true;
1106
1107 case OPT_mamx_tile:
1108 if (value)
1109 {
1110 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
1111 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
1112 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1113 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1114 }
1115 else
1116 {
1117 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
1118 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
1119 }
1120 return true;
1121
1122 case OPT_mamx_int8:
1123 if (value)
1124 {
1125 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
1126 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
1127 }
1128 else
1129 {
1130 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
1131 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
1132 }
1133 return true;
1134
1135 case OPT_mamx_bf16:
1136 if (value)
1137 {
1138 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
1139 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
1140 }
1141 else
1142 {
1143 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
1144 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
1145 }
1146 return true;
1147
1148 case OPT_mavxifma:
1149 if (value)
1150 {
1151 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXIFMA_SET;
1152 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_SET;
1153 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1154 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1155 }
1156 else
1157 {
1158 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXIFMA_UNSET;
1159 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_UNSET;
1160 }
1161 return true;
1162
1163 case OPT_mavxvnniint8:
1164 if (value)
1165 {
1166 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1167 opts->x_ix86_isa_flags2_explicit |=
1168 OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1169 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1170 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1171 }
1172 else
1173 {
1174 opts->x_ix86_isa_flags2 &=
1175 ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1176 opts->x_ix86_isa_flags2_explicit |=
1177 OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1178 }
1179 return true;
1180
1181 case OPT_mavxneconvert:
1182 if (value)
1183 {
1184 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1185 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1186 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1187 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1188 }
1189 else
1190 {
1191 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1192 opts->x_ix86_isa_flags2_explicit
1193 |= OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1194 }
1195 return true;
1196
1197 case OPT_mcmpccxadd:
1198 if (value)
1199 {
1200 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1201 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1202 }
1203 else
1204 {
1205 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1206 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1207 }
1208 return true;
1209
1210 case OPT_mamx_fp16:
1211 if (value)
1212 {
1213 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP16_SET;
1214 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_SET;
1215 }
1216 else
1217 {
1218 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP16_UNSET;
1219 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_UNSET;
1220 }
1221 return true;
1222
1223 case OPT_mprefetchi:
1224 if (value)
1225 {
1226 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PREFETCHI_SET;
1227 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_SET;
1228 }
1229 else
1230 {
1231 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PREFETCHI_UNSET;
1232 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_UNSET;
1233 }
1234 return true;
1235
1236 case OPT_mraoint:
1237 if (value)
1238 {
1239 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RAOINT_SET;
1240 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_SET;
1241 }
1242 else
1243 {
1244 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RAOINT_UNSET;
1245 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_UNSET;
1246 }
1247 return true;
1248
1249 case OPT_mfma:
1250 if (value)
1251 {
1252 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
1253 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
1254 }
1255 else
1256 {
1257 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
1258 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
1259 }
1260 return true;
1261
1262 case OPT_mrtm:
1263 if (value)
1264 {
1265 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
1266 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
1267 }
1268 else
1269 {
1270 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
1271 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
1272 }
1273 return true;
1274
1275 case OPT_msse4:
1276 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1277 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1278 return true;
1279
1280 case OPT_mno_sse4:
1281 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1282 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1283 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
1284 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
1285 return true;
1286
1287 case OPT_msse4a:
1288 if (value)
1289 {
1290 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1291 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1292 }
1293 else
1294 {
1295 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1296 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1297 }
1298 return true;
1299
1300 case OPT_mfma4:
1301 if (value)
1302 {
1303 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
1304 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
1305 }
1306 else
1307 {
1308 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
1309 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
1310 }
1311 return true;
1312
1313 case OPT_mxop:
1314 if (value)
1315 {
1316 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
1317 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
1318 }
1319 else
1320 {
1321 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
1322 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
1323 }
1324 return true;
1325
1326 case OPT_mlwp:
1327 if (value)
1328 {
1329 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
1330 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
1331 }
1332 else
1333 {
1334 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
1335 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
1336 }
1337 return true;
1338
1339 case OPT_mabm:
1340 if (value)
1341 {
1342 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
1343 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
1344 }
1345 else
1346 {
1347 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
1348 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
1349 }
1350 return true;
1351
1352 case OPT_mbmi:
1353 if (value)
1354 {
1355 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
1356 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
1357 }
1358 else
1359 {
1360 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
1361 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
1362 }
1363 return true;
1364
1365 case OPT_mbmi2:
1366 if (value)
1367 {
1368 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1369 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1370 }
1371 else
1372 {
1373 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1374 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1375 }
1376 return true;
1377
1378 case OPT_mlzcnt:
1379 if (value)
1380 {
1381 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1382 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1383 }
1384 else
1385 {
1386 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1387 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1388 }
1389 return true;
1390
1391 case OPT_mtbm:
1392 if (value)
1393 {
1394 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1395 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1396 }
1397 else
1398 {
1399 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1400 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1401 }
1402 return true;
1403
1404 case OPT_mpopcnt:
1405 if (value)
1406 {
1407 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1408 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1409 }
1410 else
1411 {
1412 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1413 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1414 }
1415 return true;
1416
1417 case OPT_msahf:
1418 if (value)
1419 {
1420 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1421 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1422 }
1423 else
1424 {
1425 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1426 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1427 }
1428 return true;
1429
1430 case OPT_mcx16:
1431 if (value)
1432 {
1433 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1434 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1435 }
1436 else
1437 {
1438 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1439 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1440 }
1441 return true;
1442
1443 case OPT_mmovbe:
1444 if (value)
1445 {
1446 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1447 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1448 }
1449 else
1450 {
1451 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1452 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1453 }
1454 return true;
1455
1456 case OPT_mcrc32:
1457 if (value)
1458 {
1459 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1460 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1461 }
1462 else
1463 {
1464 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1465 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1466 }
1467 return true;
1468
1469 case OPT_maes:
1470 if (value)
1471 {
1472 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1473 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1474 }
1475 else
1476 {
1477 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1478 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1479 }
1480 return true;
1481
1482 case OPT_msha:
1483 if (value)
1484 {
1485 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1486 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1487 }
1488 else
1489 {
1490 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1491 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1492 }
1493 return true;
1494
1495 case OPT_mpclmul:
1496 if (value)
1497 {
1498 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1499 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1500 }
1501 else
1502 {
1503 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1504 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1505 }
1506 return true;
1507
1508 case OPT_mfsgsbase:
1509 if (value)
1510 {
1511 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1512 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1513 }
1514 else
1515 {
1516 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1517 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1518 }
1519 return true;
1520
1521 case OPT_mrdrnd:
1522 if (value)
1523 {
1524 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1525 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1526 }
1527 else
1528 {
1529 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1530 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1531 }
1532 return true;
1533
1534 case OPT_mptwrite:
1535 if (value)
1536 {
1537 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1538 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1539 }
1540 else
1541 {
1542 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1543 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1544 }
1545 return true;
1546
1547 case OPT_mf16c:
1548 if (value)
1549 {
1550 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1551 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1552 }
1553 else
1554 {
1555 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1556 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1557 }
1558 return true;
1559
1560 case OPT_mfxsr:
1561 if (value)
1562 {
1563 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1564 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1565 }
1566 else
1567 {
1568 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1569 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1570 }
1571 return true;
1572
1573 case OPT_mxsave:
1574 if (value)
1575 {
1576 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1577 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1578 }
1579 else
1580 {
1581 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1582 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1583 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
1584 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
1585 }
1586 return true;
1587
1588 case OPT_mxsaveopt:
1589 if (value)
1590 {
1591 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1592 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1593 }
1594 else
1595 {
1596 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1597 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1598 }
1599 return true;
1600
1601 case OPT_mxsavec:
1602 if (value)
1603 {
1604 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1605 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1606 }
1607 else
1608 {
1609 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1610 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1611 }
1612 return true;
1613
1614 case OPT_mxsaves:
1615 if (value)
1616 {
1617 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1618 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1619 }
1620 else
1621 {
1622 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1623 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1624 }
1625 return true;
1626
1627 case OPT_mrdseed:
1628 if (value)
1629 {
1630 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1631 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1632 }
1633 else
1634 {
1635 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1636 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1637 }
1638 return true;
1639
1640 case OPT_mprfchw:
1641 if (value)
1642 {
1643 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1644 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1645 }
1646 else
1647 {
1648 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1649 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1650 }
1651 return true;
1652
1653 case OPT_madx:
1654 if (value)
1655 {
1656 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1657 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1658 }
1659 else
1660 {
1661 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1662 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1663 }
1664 return true;
1665
1666 case OPT_mprefetchwt1:
1667 if (value)
1668 {
1669 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1670 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1671 }
1672 else
1673 {
1674 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1675 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1676 }
1677 return true;
1678
1679 case OPT_mclflushopt:
1680 if (value)
1681 {
1682 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1683 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1684 }
1685 else
1686 {
1687 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1688 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1689 }
1690 return true;
1691
1692 case OPT_mclwb:
1693 if (value)
1694 {
1695 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1696 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1697 }
1698 else
1699 {
1700 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1701 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1702 }
1703 return true;
1704
1705 case OPT_mmwaitx:
1706 if (value)
1707 {
1708 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1709 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1710 }
1711 else
1712 {
1713 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1714 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1715 }
1716 return true;
1717
1718 case OPT_mmwait:
1719 if (value)
1720 {
1721 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET;
1722 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET;
1723 }
1724 else
1725 {
1726 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET;
1727 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET;
1728 }
1729 return true;
1730
1731 case OPT_mclzero:
1732 if (value)
1733 {
1734 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1735 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1736 }
1737 else
1738 {
1739 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1740 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1741 }
1742 return true;
1743
1744 case OPT_mpku:
1745 if (value)
1746 {
1747 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1748 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1749 }
1750 else
1751 {
1752 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1753 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1754 }
1755 return true;
1756
1757
1758 case OPT_malign_loops_:
1759 warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
1760 "use %<-falign-loops%>");
1761 if (value > MAX_CODE_ALIGN)
1762 error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
1763 value, MAX_CODE_ALIGN);
1764 else
1765 set_malign_value (&opts->x_str_align_loops, value);
1766 return true;
1767
1768 case OPT_malign_jumps_:
1769 warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
1770 "use %<-falign-jumps%>");
1771 if (value > MAX_CODE_ALIGN)
1772 error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
1773 value, MAX_CODE_ALIGN);
1774 else
1775 set_malign_value (&opts->x_str_align_jumps, value);
1776 return true;
1777
1778 case OPT_malign_functions_:
1779 warning_at (loc, 0,
1780 "%<-malign-functions%> is obsolete, "
1781 "use %<-falign-functions%>");
1782 if (value > MAX_CODE_ALIGN)
1783 error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
1784 value, MAX_CODE_ALIGN);
1785 else
1786 set_malign_value (&opts->x_str_align_functions, value);
1787 return true;
1788
1789 case OPT_mbranch_cost_:
1790 if (value > 5)
1791 {
1792 error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
1793 opts->x_ix86_branch_cost = 5;
1794 }
1795 return true;
1796
1797 default:
1798 return true;
1799 }
1800 }
1801
1802 static const struct default_options ix86_option_optimization_table[] =
1803 {
1804 /* Enable redundant extension instructions removal at -O2 and higher. */
1805 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
1806 /* Enable function splitting at -O2 and higher. */
1807 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
1808 /* The STC algorithm produces the smallest code at -Os, for x86. */
1809 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1810 REORDER_BLOCKS_ALGORITHM_STC },
1811
1812 /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
1813 loop unrolling at -O2. */
1814 { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },
1815 { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 },
1816 /* Turns off -frename-registers and -fweb which are enabled by
1817 funroll-loops. */
1818 { OPT_LEVELS_ALL, OPT_frename_registers, NULL, 0 },
1819 { OPT_LEVELS_ALL, OPT_fweb, NULL, 0 },
1820 /* Turn off -fschedule-insns by default. It tends to make the
1821 problem with not enough registers even worse. */
1822 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1823
1824 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1825 SUBTARGET_OPTIMIZATION_OPTIONS,
1826 #endif
1827 { OPT_LEVELS_NONE, 0, NULL, 0 }
1828 };
1829
1830 /* Implement TARGET_OPTION_INIT_STRUCT. */
1831
1832 static void
1833 ix86_option_init_struct (struct gcc_options *opts)
1834 {
1835 if (TARGET_MACHO)
1836 /* The Darwin libraries never set errno, so we might as well
1837 avoid calling them when that's the only reason we would. */
1838 opts->x_flag_errno_math = 0;
1839
1840 opts->x_flag_pcc_struct_return = 2;
1841 opts->x_flag_asynchronous_unwind_tables = 2;
1842 }
1843
1844 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1845 field in the TCB, so they cannot be used together. */
1846
1847 static bool
1848 ix86_supports_split_stack (bool report,
1849 struct gcc_options *opts ATTRIBUTE_UNUSED)
1850 {
1851 #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P)
1852 if (!OPTION_GLIBC_P (opts))
1853 #endif
1854 {
1855 if (report)
1856 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1857 return false;
1858 }
1859
1860 bool ret = true;
1861
1862 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
1863 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1864 {
1865 if (report)
1866 error ("%<-fsplit-stack%> requires "
1867 "assembler support for CFI directives");
1868 ret = false;
1869 }
1870 #endif
1871
1872 return ret;
1873 }
1874
1875 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
1876
1877 static enum unwind_info_type
1878 i386_except_unwind_info (struct gcc_options *opts)
1879 {
1880 /* Honor the --enable-sjlj-exceptions configure switch. */
1881 #ifdef CONFIG_SJLJ_EXCEPTIONS
1882 if (CONFIG_SJLJ_EXCEPTIONS)
1883 return UI_SJLJ;
1884 #endif
1885
1886 /* On windows 64, prefer SEH exceptions over anything else. */
1887 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1888 return UI_SEH;
1889
1890 if (DWARF2_UNWIND_INFO)
1891 return UI_DWARF2;
1892
1893 return UI_SJLJ;
1894 }
1895
1896 #undef TARGET_EXCEPT_UNWIND_INFO
1897 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1898
1899 #undef TARGET_DEFAULT_TARGET_FLAGS
1900 #define TARGET_DEFAULT_TARGET_FLAGS \
1901 (TARGET_DEFAULT \
1902 | TARGET_SUBTARGET_DEFAULT \
1903 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1904
1905 #undef TARGET_HANDLE_OPTION
1906 #define TARGET_HANDLE_OPTION ix86_handle_option
1907
1908 #undef TARGET_OPTION_OPTIMIZATION_TABLE
1909 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1910 #undef TARGET_OPTION_INIT_STRUCT
1911 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1912
1913 #undef TARGET_SUPPORTS_SPLIT_STACK
1914 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1915
1916 /* This table must be in sync with enum processor_type in i386.h. */
1917 const char *const processor_names[] =
1918 {
1919 "generic",
1920 "i386",
1921 "i486",
1922 "pentium",
1923 "lakemont",
1924 "pentiumpro",
1925 "pentium4",
1926 "nocona",
1927 "core2",
1928 "nehalem",
1929 "sandybridge",
1930 "haswell",
1931 "bonnell",
1932 "silvermont",
1933 "goldmont",
1934 "goldmont-plus",
1935 "tremont",
1936 "sierraforest",
1937 "grandridge",
1938 "knl",
1939 "knm",
1940 "skylake",
1941 "skylake-avx512",
1942 "cannonlake",
1943 "icelake-client",
1944 "icelake-server",
1945 "cascadelake",
1946 "tigerlake",
1947 "cooperlake",
1948 "sapphirerapids",
1949 "alderlake",
1950 "rocketlake",
1951 "graniterapids",
1952 "intel",
1953 "lujiazui",
1954 "geode",
1955 "k6",
1956 "athlon",
1957 "k8",
1958 "amdfam10",
1959 "bdver1",
1960 "bdver2",
1961 "bdver3",
1962 "bdver4",
1963 "btver1",
1964 "btver2",
1965 "znver1",
1966 "znver2",
1967 "znver3",
1968 "znver4"
1969 };
1970
1971 /* Guarantee that the array is aligned with enum processor_type. */
1972 STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
1973
1974 const pta processor_alias_table[] =
1975 {
1976 {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
1977 {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
1978 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
1979 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
1980 {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
1981 0, P_NONE},
1982 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
1983 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
1984 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
1985 0, P_NONE},
1986 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
1987 {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
1988 0, P_NONE},
1989 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1990 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1991 {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1992 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1993 {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1994 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
1995 {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1996 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
1997 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
1998 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
1999 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
2000 0, P_NONE},
2001 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2002 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2003 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2004 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2005 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2006 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2007 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2008 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2009 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2010 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2011 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2012 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2013 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2014 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2015 | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2016 {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
2017 M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
2018 {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2019 M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
2020 {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2021 M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
2022 {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
2023 M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
2024 {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2025 PTA_SANDYBRIDGE,
2026 M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
2027 {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2028 PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
2029 {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2030 PTA_IVYBRIDGE,
2031 M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
2032 {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2033 PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
2034 {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2035 M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
2036 {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2037 0, P_PROC_DYNAMIC},
2038 {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
2039 M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
2040 {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
2041 M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
2042 {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
2043 PTA_SKYLAKE_AVX512,
2044 M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
2045 {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
2046 M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
2047 {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
2048 PTA_ICELAKE_CLIENT,
2049 M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
2050 {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
2051 PTA_ROCKETLAKE,
2052 M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
2053 {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
2054 PTA_ICELAKE_SERVER,
2055 M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
2056 {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
2057 PTA_CASCADELAKE,
2058 M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
2059 {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
2060 M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
2061 {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
2062 M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
2063 {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2064 M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2065 {"emeraldrapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2066 M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2067 {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2068 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2069 {"raptorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2070 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2071 {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2072 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2073 {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
2074 M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX512F},
2075 {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2076 M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2077 {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2078 M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2079 {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2080 M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2081 {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2082 M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2083 {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
2084 M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
2085 {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
2086 M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
2087 {"tremont", PROCESSOR_TREMONT, CPU_HASWELL, PTA_TREMONT,
2088 M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
2089 {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST,
2090 M_CPU_SUBTYPE (INTEL_SIERRAFOREST), P_PROC_AVX2},
2091 {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE,
2092 M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2},
2093 {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL,
2094 M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F},
2095 {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM,
2096 M_CPU_TYPE (INTEL_KNM), P_PROC_AVX512F},
2097 {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM,
2098 M_VENDOR (VENDOR_INTEL), P_NONE},
2099 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2100 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2101 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
2102 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2103 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2104 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2105 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2106 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2107 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2108 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2109 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2110 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2111 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2112 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2113 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2114 {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
2115 {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
2116 0, P_NONE},
2117 {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
2118 0, P_NONE},
2119 {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
2120 0, P_NONE},
2121 {"eden-x2", PROCESSOR_K8, CPU_K8,
2122 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
2123 0, P_NONE},
2124 {"nano", PROCESSOR_K8, CPU_K8,
2125 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2126 | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2127 {"nano-1000", PROCESSOR_K8, CPU_K8,
2128 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2129 | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2130 {"nano-2000", PROCESSOR_K8, CPU_K8,
2131 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2132 | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2133 {"nano-3000", PROCESSOR_K8, CPU_K8,
2134 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2135 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2136 {"nano-x2", PROCESSOR_K8, CPU_K8,
2137 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2138 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2139 {"eden-x4", PROCESSOR_K8, CPU_K8,
2140 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2141 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2142 {"nano-x4", PROCESSOR_K8, CPU_K8,
2143 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2144 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2145 {"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
2146 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2147 | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2148 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_BMI | PTA_BMI2
2149 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
2150 | PTA_RDRND | PTA_MOVBE | PTA_ADX | PTA_RDSEED | PTA_POPCNT,
2151 M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_NONE},
2152 {"k8", PROCESSOR_K8, CPU_K8,
2153 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2154 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2155 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2156 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2157 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2158 {"opteron", PROCESSOR_K8, CPU_K8,
2159 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2160 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2161 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2162 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2163 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2164 {"athlon64", PROCESSOR_K8, CPU_K8,
2165 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2166 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2167 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2168 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2169 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2170 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2171 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2172 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2173 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2174 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2175 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2176 0, P_PROC_DYNAMIC},
2177 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2178 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2179 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2180 M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
2181 {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
2182 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2183 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2184 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
2185 | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
2186 M_CPU_TYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
2187 {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
2188 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2189 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2190 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
2191 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
2192 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
2193 M_CPU_TYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
2194 {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
2195 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2196 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2197 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
2198 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
2199 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
2200 | PTA_XSAVEOPT | PTA_FSGSBASE,
2201 M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
2202 {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
2203 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2204 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2205 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
2206 | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
2207 | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
2208 | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
2209 | PTA_MOVBE | PTA_MWAITX,
2210 M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
2211 {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
2212 PTA_ZNVER1,
2213 M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
2214 {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
2215 PTA_ZNVER2,
2216 M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
2217 {"znver3", PROCESSOR_ZNVER3, CPU_ZNVER3,
2218 PTA_ZNVER3,
2219 M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), P_PROC_AVX2},
2220 {"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
2221 PTA_ZNVER4,
2222 M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
2223 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
2224 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2225 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
2226 | PTA_FXSR | PTA_XSAVE,
2227 M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_SSE4_A},
2228 {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
2229 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2230 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
2231 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
2232 | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
2233 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT,
2234 M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
2235
2236 {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
2237 PTA_64BIT
2238 | PTA_HLE /* flags are only used for -march switch. */,
2239 0, P_NONE},
2240
2241 {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2242 M_VENDOR (VENDOR_AMD), P_NONE},
2243 {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2244 M_CPU_TYPE (AMDFAM10H), P_NONE},
2245 {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2246 M_CPU_TYPE (AMDFAM15H), P_NONE},
2247 {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2248 M_CPU_TYPE (AMDFAM17H), P_NONE},
2249 {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2250 M_CPU_TYPE (AMDFAM19H), P_NONE},
2251 {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2252 M_CPU_TYPE (AMDFAM10H_SHANGHAI), P_NONE},
2253 {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2254 M_CPU_TYPE (AMDFAM10H_ISTANBUL), P_NONE},
2255 };
2256
2257 /* NB: processor_alias_table stops at the "generic" entry. */
2258 unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7;
2259 unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
2260
2261 /* Provide valid option values for -march and -mtune options. */
2262
2263 vec<const char *>
2264 ix86_get_valid_option_values (int option_code,
2265 const char *prefix ATTRIBUTE_UNUSED)
2266 {
2267 vec<const char *> v;
2268 v.create (0);
2269 opt_code opt = (opt_code) option_code;
2270
2271 switch (opt)
2272 {
2273 case OPT_march_:
2274 for (unsigned i = 0; i < pta_size; i++)
2275 {
2276 const char *name = processor_alias_table[i].name;
2277 gcc_checking_assert (name != NULL);
2278 v.safe_push (name);
2279 }
2280 #ifdef HAVE_LOCAL_CPU_DETECT
2281 /* Add also "native" as possible value. */
2282 v.safe_push ("native");
2283 #endif
2284
2285 break;
2286 case OPT_mtune_:
2287 for (unsigned i = 0; i < PROCESSOR_max; i++)
2288 {
2289 const char *name = processor_names[i];
2290 gcc_checking_assert (name != NULL);
2291 v.safe_push (name);
2292 }
2293 break;
2294 default:
2295 break;
2296 }
2297
2298 return v;
2299 }
2300
2301 #undef TARGET_GET_VALID_OPTION_VALUES
2302 #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2303
2304 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git