1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2012-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
22 builtins for each of the modes described by <ITERATOR>. When adding
23 new builtins to this list, a helpful idiom to follow is to add
24 a line for each pattern in the md file. Thus, ADDP, which has one
25 pattern defined for the VD_BHSI iterator, and one for DImode, has two
28 Parameter 1 is the 'type' of the intrinsic. This is used to
29 describe the type modifiers (for example; unsigned) applied to
30 each of the parameters to the intrinsic function.
32 Parameter 2 is the name of the intrinsic. This is appended
33 to `__builtin_aarch64_<name><mode>` to give the intrinsic name
34 as exported to the front-ends.
36 Parameter 3 describes how to map from the name to the CODE_FOR_
37 macro holding the RTL pattern for the intrinsic. This mapping is:
38 0 - CODE_FOR_aarch64_<name><mode>
39 1-9 - CODE_FOR_<name><mode><1-9>
40 10 - CODE_FOR_<name><mode>. */
42 BUILTIN_VDC (COMBINE, combine, 0)
43 BUILTIN_VB (BINOP, pmul, 0)
44 BUILTIN_VALLF (BINOP, fmulx, 0)
45 BUILTIN_VDQF_DF (UNOP, sqrt, 2)
46 BUILTIN_VD_BHSI (BINOP, addp, 0)
47 VAR1 (UNOP, addp, 0, di)
48 BUILTIN_VDQ_BHSI (UNOP, clrsb, 2)
49 BUILTIN_VDQ_BHSI (UNOP, clz, 2)
50 BUILTIN_VS (UNOP, ctz, 2)
51 BUILTIN_VB (UNOP, popcount, 2)
53 /* Implemented by aarch64_<sur>q<r>shl<mode>. */
54 BUILTIN_VSDQ_I (BINOP, sqshl, 0)
55 BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)
56 BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
57 BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0)
58 /* Implemented by aarch64_<su_optab><optab><mode>. */
59 BUILTIN_VSDQ_I (BINOP, sqadd, 0)
60 BUILTIN_VSDQ_I (BINOPU, uqadd, 0)
61 BUILTIN_VSDQ_I (BINOP, sqsub, 0)
62 BUILTIN_VSDQ_I (BINOPU, uqsub, 0)
63 /* Implemented by aarch64_<sur>qadd<mode>. */
64 BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0)
65 BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
67 /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */
68 BUILTIN_VDC (GETREG, get_dregoi, 0)
69 BUILTIN_VDC (GETREG, get_dregci, 0)
70 BUILTIN_VDC (GETREG, get_dregxi, 0)
71 /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */
72 BUILTIN_VQ (GETREG, get_qregoi, 0)
73 BUILTIN_VQ (GETREG, get_qregci, 0)
74 BUILTIN_VQ (GETREG, get_qregxi, 0)
75 /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */
76 BUILTIN_VQ (SETREG, set_qregoi, 0)
77 BUILTIN_VQ (SETREG, set_qregci, 0)
78 BUILTIN_VQ (SETREG, set_qregxi, 0)
79 /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */
80 BUILTIN_VDC (LOADSTRUCT, ld2, 0)
81 BUILTIN_VDC (LOADSTRUCT, ld3, 0)
82 BUILTIN_VDC (LOADSTRUCT, ld4, 0)
83 /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */
84 BUILTIN_VQ (LOADSTRUCT, ld2, 0)
85 BUILTIN_VQ (LOADSTRUCT, ld3, 0)
86 BUILTIN_VQ (LOADSTRUCT, ld4, 0)
87 /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>. */
88 BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0)
89 BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0)
90 BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0)
91 /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>. */
92 BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0)
93 BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0)
94 BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0)
95 /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */
96 BUILTIN_VDC (STORESTRUCT, st2, 0)
97 BUILTIN_VDC (STORESTRUCT, st3, 0)
98 BUILTIN_VDC (STORESTRUCT, st4, 0)
99 /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */
100 BUILTIN_VQ (STORESTRUCT, st2, 0)
101 BUILTIN_VQ (STORESTRUCT, st3, 0)
102 BUILTIN_VQ (STORESTRUCT, st4, 0)
104 BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0)
105 BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0)
106 BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0)
108 BUILTIN_VQW (BINOP, saddl2, 0)
109 BUILTIN_VQW (BINOP, uaddl2, 0)
110 BUILTIN_VQW (BINOP, ssubl2, 0)
111 BUILTIN_VQW (BINOP, usubl2, 0)
112 BUILTIN_VQW (BINOP, saddw2, 0)
113 BUILTIN_VQW (BINOP, uaddw2, 0)
114 BUILTIN_VQW (BINOP, ssubw2, 0)
115 BUILTIN_VQW (BINOP, usubw2, 0)
116 /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */
117 BUILTIN_VD_BHSI (BINOP, saddl, 0)
118 BUILTIN_VD_BHSI (BINOP, uaddl, 0)
119 BUILTIN_VD_BHSI (BINOP, ssubl, 0)
120 BUILTIN_VD_BHSI (BINOP, usubl, 0)
121 /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */
122 BUILTIN_VD_BHSI (BINOP, saddw, 0)
123 BUILTIN_VD_BHSI (BINOP, uaddw, 0)
124 BUILTIN_VD_BHSI (BINOP, ssubw, 0)
125 BUILTIN_VD_BHSI (BINOP, usubw, 0)
126 /* Implemented by aarch64_<sur>h<addsub><mode>. */
127 BUILTIN_VDQ_BHSI (BINOP, shadd, 0)
128 BUILTIN_VDQ_BHSI (BINOP, shsub, 0)
129 BUILTIN_VDQ_BHSI (BINOP, uhadd, 0)
130 BUILTIN_VDQ_BHSI (BINOP, uhsub, 0)
131 BUILTIN_VDQ_BHSI (BINOP, srhadd, 0)
132 BUILTIN_VDQ_BHSI (BINOP, urhadd, 0)
133 /* Implemented by aarch64_<sur><addsub>hn<mode>. */
134 BUILTIN_VQN (BINOP, addhn, 0)
135 BUILTIN_VQN (BINOP, subhn, 0)
136 BUILTIN_VQN (BINOP, raddhn, 0)
137 BUILTIN_VQN (BINOP, rsubhn, 0)
138 /* Implemented by aarch64_<sur><addsub>hn2<mode>. */
139 BUILTIN_VQN (TERNOP, addhn2, 0)
140 BUILTIN_VQN (TERNOP, subhn2, 0)
141 BUILTIN_VQN (TERNOP, raddhn2, 0)
142 BUILTIN_VQN (TERNOP, rsubhn2, 0)
144 BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
145 /* Implemented by aarch64_<sur>qmovn<mode>. */
146 BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
147 BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
148 /* Implemented by aarch64_s<optab><mode>. */
149 BUILTIN_VSDQ_I (UNOP, sqabs, 0)
150 BUILTIN_VSDQ_I (UNOP, sqneg, 0)
152 /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */
153 BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
154 BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
155 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>. */
156 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0)
157 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0)
158 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>. */
159 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0)
160 BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0)
161 /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */
162 BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
163 BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
165 BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
166 BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
167 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0)
168 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0)
169 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0)
170 BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0)
171 BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
172 BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
174 BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
175 BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0)
176 BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0)
177 BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
178 BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
179 BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0)
180 BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0)
181 BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
182 /* Implemented by aarch64_sq<r>dmulh<mode>. */
183 BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
184 BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
185 /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */
186 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0)
187 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0)
188 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0)
189 BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0)
191 BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
192 /* Implemented by aarch64_<sur>shl<mode>. */
193 BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
194 BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0)
195 BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
196 BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
198 BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
199 VAR1 (SHIFTIMM, ashr_simd, 0, di)
200 BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
201 VAR1 (USHIFTIMM, lshr_simd, 0, di)
202 /* Implemented by aarch64_<sur>shr_n<mode>. */
203 BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
204 BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0)
205 /* Implemented by aarch64_<sur>sra_n<mode>. */
206 BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
207 BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0)
208 BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
209 BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
210 /* Implemented by aarch64_<sur>shll_n<mode>. */
211 BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0)
212 BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0)
213 /* Implemented by aarch64_<sur>shll2_n<mode>. */
214 BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
215 BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
216 /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */
217 BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
218 BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
219 BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
220 BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0)
221 BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
222 BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0)
223 /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */
224 BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
225 BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
226 BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
227 BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
228 /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */
229 BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
230 BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
231 BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
233 /* Implemented by aarch64_reduc_plus_<mode>. */
234 BUILTIN_VALL (UNOP, reduc_plus_scal_, 10)
236 /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar). */
237 BUILTIN_VDQIF (UNOP, reduc_smax_scal_, 10)
238 BUILTIN_VDQIF (UNOP, reduc_smin_scal_, 10)
239 BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10)
240 BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10)
241 BUILTIN_VDQF (UNOP, reduc_smax_nan_scal_, 10)
242 BUILTIN_VDQF (UNOP, reduc_smin_nan_scal_, 10)
244 /* Implemented by <maxmin><mode>3.
245 smax variants map to fmaxnm,
246 smax_nan variants map to fmax. */
247 BUILTIN_VDQIF (BINOP, smax, 3)
248 BUILTIN_VDQIF (BINOP, smin, 3)
249 BUILTIN_VDQ_BHSI (BINOP, umax, 3)
250 BUILTIN_VDQ_BHSI (BINOP, umin, 3)
251 BUILTIN_VDQF (BINOP, smax_nan, 3)
252 BUILTIN_VDQF (BINOP, smin_nan, 3)
254 /* Implemented by aarch64_<maxmin_uns>p<mode>. */
255 BUILTIN_VDQ_BHSI (BINOP, smaxp, 0)
256 BUILTIN_VDQ_BHSI (BINOP, sminp, 0)
257 BUILTIN_VDQ_BHSI (BINOP, umaxp, 0)
258 BUILTIN_VDQ_BHSI (BINOP, uminp, 0)
259 BUILTIN_VDQF (BINOP, smaxp, 0)
260 BUILTIN_VDQF (BINOP, sminp, 0)
261 BUILTIN_VDQF (BINOP, smax_nanp, 0)
262 BUILTIN_VDQF (BINOP, smin_nanp, 0)
264 /* Implemented by <frint_pattern><mode>2. */
265 BUILTIN_VDQF (UNOP, btrunc, 2)
266 BUILTIN_VDQF (UNOP, ceil, 2)
267 BUILTIN_VDQF (UNOP, floor, 2)
268 BUILTIN_VDQF (UNOP, nearbyint, 2)
269 BUILTIN_VDQF (UNOP, rint, 2)
270 BUILTIN_VDQF (UNOP, round, 2)
271 BUILTIN_VDQF_DF (UNOP, frintn, 2)
273 /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */
274 VAR1 (UNOP, lbtruncv2sf, 2, v2si)
275 VAR1 (UNOP, lbtruncv4sf, 2, v4si)
276 VAR1 (UNOP, lbtruncv2df, 2, v2di)
278 VAR1 (UNOPUS, lbtruncuv2sf, 2, v2si)
279 VAR1 (UNOPUS, lbtruncuv4sf, 2, v4si)
280 VAR1 (UNOPUS, lbtruncuv2df, 2, v2di)
282 VAR1 (UNOP, lroundv2sf, 2, v2si)
283 VAR1 (UNOP, lroundv4sf, 2, v4si)
284 VAR1 (UNOP, lroundv2df, 2, v2di)
285 /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2. */
286 VAR1 (UNOP, lroundsf, 2, si)
287 VAR1 (UNOP, lrounddf, 2, di)
289 VAR1 (UNOPUS, lrounduv2sf, 2, v2si)
290 VAR1 (UNOPUS, lrounduv4sf, 2, v4si)
291 VAR1 (UNOPUS, lrounduv2df, 2, v2di)
292 VAR1 (UNOPUS, lroundusf, 2, si)
293 VAR1 (UNOPUS, lroundudf, 2, di)
295 VAR1 (UNOP, lceilv2sf, 2, v2si)
296 VAR1 (UNOP, lceilv4sf, 2, v4si)
297 VAR1 (UNOP, lceilv2df, 2, v2di)
299 VAR1 (UNOPUS, lceiluv2sf, 2, v2si)
300 VAR1 (UNOPUS, lceiluv4sf, 2, v4si)
301 VAR1 (UNOPUS, lceiluv2df, 2, v2di)
302 VAR1 (UNOPUS, lceilusf, 2, si)
303 VAR1 (UNOPUS, lceiludf, 2, di)
305 VAR1 (UNOP, lfloorv2sf, 2, v2si)
306 VAR1 (UNOP, lfloorv4sf, 2, v4si)
307 VAR1 (UNOP, lfloorv2df, 2, v2di)
309 VAR1 (UNOPUS, lflooruv2sf, 2, v2si)
310 VAR1 (UNOPUS, lflooruv4sf, 2, v4si)
311 VAR1 (UNOPUS, lflooruv2df, 2, v2di)
312 VAR1 (UNOPUS, lfloorusf, 2, si)
313 VAR1 (UNOPUS, lfloorudf, 2, di)
315 VAR1 (UNOP, lfrintnv2sf, 2, v2si)
316 VAR1 (UNOP, lfrintnv4sf, 2, v4si)
317 VAR1 (UNOP, lfrintnv2df, 2, v2di)
318 VAR1 (UNOP, lfrintnsf, 2, si)
319 VAR1 (UNOP, lfrintndf, 2, di)
321 VAR1 (UNOPUS, lfrintnuv2sf, 2, v2si)
322 VAR1 (UNOPUS, lfrintnuv4sf, 2, v4si)
323 VAR1 (UNOPUS, lfrintnuv2df, 2, v2di)
324 VAR1 (UNOPUS, lfrintnusf, 2, si)
325 VAR1 (UNOPUS, lfrintnudf, 2, di)
327 /* Implemented by <optab><fcvt_target><VDQF:mode>2. */
328 VAR1 (UNOP, floatv2si, 2, v2sf)
329 VAR1 (UNOP, floatv4si, 2, v4sf)
330 VAR1 (UNOP, floatv2di, 2, v2df)
332 VAR1 (UNOP, floatunsv2si, 2, v2sf)
333 VAR1 (UNOP, floatunsv4si, 2, v4sf)
334 VAR1 (UNOP, floatunsv2di, 2, v2df)
336 VAR5 (UNOPU, bswap, 2, v4hi, v8hi, v2si, v4si, v2di)
338 BUILTIN_VB (UNOP, rbit, 0)
341 aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */
342 BUILTIN_VALL (BINOP, zip1, 0)
343 BUILTIN_VALL (BINOP, zip2, 0)
344 BUILTIN_VALL (BINOP, uzp1, 0)
345 BUILTIN_VALL (BINOP, uzp2, 0)
346 BUILTIN_VALL (BINOP, trn1, 0)
347 BUILTIN_VALL (BINOP, trn2, 0)
350 aarch64_frecp<FRECP:frecp_suffix><mode>. */
351 BUILTIN_GPF (UNOP, frecpe, 0)
352 BUILTIN_GPF (BINOP, frecps, 0)
353 BUILTIN_GPF (UNOP, frecpx, 0)
355 BUILTIN_VDQ_SI (UNOP, urecpe, 0)
357 BUILTIN_VDQF (UNOP, frecpe, 0)
358 BUILTIN_VDQF (BINOP, frecps, 0)
360 /* Implemented by a mixture of abs2 patterns. Note the DImode builtin is
361 only ever used for the int64x1_t intrinsic, there is no scalar version. */
362 BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
363 BUILTIN_VDQF (UNOP, abs, 2)
365 BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10)
366 VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
367 VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
369 VAR1 (UNOP, float_extend_lo_, 0, v2df)
370 VAR1 (UNOP, float_extend_lo_, 0, v4sf)
371 BUILTIN_VDF (UNOP, float_truncate_lo_, 0)
373 /* Implemented by aarch64_ld1<VALL_F16:mode>. */
374 BUILTIN_VALL_F16 (LOAD1, ld1, 0)
376 /* Implemented by aarch64_st1<VALL_F16:mode>. */
377 BUILTIN_VALL_F16 (STORE1, st1, 0)
379 /* Implemented by fma<mode>4. */
380 BUILTIN_VDQF (TERNOP, fma, 4)
382 /* Implemented by aarch64_simd_bsl<mode>. */
383 BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
384 BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
385 BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
387 /* Implemented by aarch64_crypto_aes<op><mode>. */
388 VAR1 (BINOPU, crypto_aese, 0, v16qi)
389 VAR1 (BINOPU, crypto_aesd, 0, v16qi)
390 VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
391 VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
393 /* Implemented by aarch64_crypto_sha1<op><mode>. */
394 VAR1 (UNOPU, crypto_sha1h, 0, si)
395 VAR1 (BINOPU, crypto_sha1su1, 0, v4si)
396 VAR1 (TERNOPU, crypto_sha1c, 0, v4si)
397 VAR1 (TERNOPU, crypto_sha1m, 0, v4si)
398 VAR1 (TERNOPU, crypto_sha1p, 0, v4si)
399 VAR1 (TERNOPU, crypto_sha1su0, 0, v4si)
401 /* Implemented by aarch64_crypto_sha256<op><mode>. */
402 VAR1 (TERNOPU, crypto_sha256h, 0, v4si)
403 VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
404 VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
405 VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
407 /* Implemented by aarch64_crypto_pmull<mode>. */
408 VAR1 (BINOPP, crypto_pmull, 0, di)
409 VAR1 (BINOPP, crypto_pmull, 0, v2di)
411 /* Implemented by aarch64_tbl3<mode>. */
412 VAR1 (BINOP, tbl3, 0, v8qi)
413 VAR1 (BINOP, tbl3, 0, v16qi)
415 /* Implemented by aarch64_qtbl3<mode>. */
416 VAR1 (BINOP, qtbl3, 0, v8qi)
417 VAR1 (BINOP, qtbl3, 0, v16qi)
419 /* Implemented by aarch64_qtbl4<mode>. */
420 VAR1 (BINOP, qtbl4, 0, v8qi)
421 VAR1 (BINOP, qtbl4, 0, v16qi)
423 /* Implemented by aarch64_tbx4<mode>. */
424 VAR1 (TERNOP, tbx4, 0, v8qi)
425 VAR1 (TERNOP, tbx4, 0, v16qi)
427 /* Implemented by aarch64_qtbx3<mode>. */
428 VAR1 (TERNOP, qtbx3, 0, v8qi)
429 VAR1 (TERNOP, qtbx3, 0, v16qi)
431 /* Implemented by aarch64_qtbx4<mode>. */
432 VAR1 (TERNOP, qtbx4, 0, v8qi)
433 VAR1 (TERNOP, qtbx4, 0, v16qi)
435 /* Builtins for ARMv8.1 Adv.SIMD instructions. */
437 /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>. */
438 BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0)
439 BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0)
441 /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>. */
442 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0)
443 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0)
445 /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>. */
446 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0)
447 BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
449 /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3. */
450 BUILTIN_VSDQ_SDI (BINOP, scvtf, 3)
451 BUILTIN_VSDQ_SDI (BINOP_SUS, ucvtf, 3)
452 BUILTIN_VALLF (BINOP, fcvtzs, 3)
453 BUILTIN_VALLF (BINOP_USS, fcvtzu, 3)
455 /* Implemented by aarch64_rsqrte<mode>. */
456 BUILTIN_VALLF (UNOP, rsqrte, 0)
458 /* Implemented by aarch64_rsqrts<mode>. */
459 BUILTIN_VALLF (BINOP, rsqrts, 0)