gcc/config/aarch64/aarch64-simd-builtins.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2014 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
  22    builtins for each of the modes described by <ITERATOR>.  When adding
  23    new builtins to this list, a helpful idiom to follow is to add
  24    a line for each pattern in the md file.  Thus, ADDP, which has one
  25    pattern defined for the VD_BHSI iterator, and one for DImode, has two
  26    entries below.
  27
  28    Parameter 1 is the 'type' of the intrinsic.  This is used to
  29    describe the type modifiers (for example; unsigned) applied to
  30    each of the parameters to the intrinsic function.
  31
  32    Parameter 2 is the name of the intrinsic.  This is appended
  33    to `__builtin_aarch64_<name><mode>` to give the intrinsic name
  34    as exported to the front-ends.
  35
  36    Parameter 3 describes how to map from the name to the CODE_FOR_
  37    macro holding the RTL pattern for the intrinsic.  This mapping is:
  38    0 - CODE_FOR_aarch64_<name><mode>
  39    1-9 - CODE_FOR_<name><mode><1-9>
  40    10 - CODE_FOR_<name><mode>.  */
  41
  42   BUILTIN_VDC (COMBINE, combine, 0)
  43   BUILTIN_VB (BINOP, pmul, 0)
  44   BUILTIN_VDQF (UNOP, sqrt, 2)
  45   BUILTIN_VD_BHSI (BINOP, addp, 0)
  46   VAR1 (UNOP, addp, 0, di)
  47   BUILTIN_VDQ_BHSI (UNOP, clz, 2)
  48
  49   /* be_checked_get_lane does its own lane swapping, so not a lane index.  */
  50   BUILTIN_VALL (GETREG, be_checked_get_lane, 0)
  51
  52   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
  53   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
  54   BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)
  55   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
  56   BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0)
  57   /* Implemented by aarch64_<su_optab><optab><mode>.  */
  58   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
  59   BUILTIN_VSDQ_I (BINOPU, uqadd, 0)
  60   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
  61   BUILTIN_VSDQ_I (BINOPU, uqsub, 0)
  62   /* Implemented by aarch64_<sur>qadd<mode>.  */
  63   BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0)
  64   BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
  65
  66   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
  67   BUILTIN_VDC (GETREG, get_dregoi, 0)
  68   BUILTIN_VDC (GETREG, get_dregci, 0)
  69   BUILTIN_VDC (GETREG, get_dregxi, 0)
  70   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
  71   BUILTIN_VQ (GETREG, get_qregoi, 0)
  72   BUILTIN_VQ (GETREG, get_qregci, 0)
  73   BUILTIN_VQ (GETREG, get_qregxi, 0)
  74   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
  75   BUILTIN_VQ (SETREG, set_qregoi, 0)
  76   BUILTIN_VQ (SETREG, set_qregci, 0)
  77   BUILTIN_VQ (SETREG, set_qregxi, 0)
  78   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
  79   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
  80   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
  81   BUILTIN_VDC (LOADSTRUCT, ld4, 0)
  82   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
  83   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
  84   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
  85   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
  86   /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>.  */
  87   BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0)
  88   BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0)
  89   BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0)
  90   /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>.  */
  91   BUILTIN_VQ (LOADSTRUCT_LANE, ld2_lane, 0)
  92   BUILTIN_VQ (LOADSTRUCT_LANE, ld3_lane, 0)
  93   BUILTIN_VQ (LOADSTRUCT_LANE, ld4_lane, 0)
  94   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
  95   BUILTIN_VDC (STORESTRUCT, st2, 0)
  96   BUILTIN_VDC (STORESTRUCT, st3, 0)
  97   BUILTIN_VDC (STORESTRUCT, st4, 0)
  98   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
  99   BUILTIN_VQ (STORESTRUCT, st2, 0)
 100   BUILTIN_VQ (STORESTRUCT, st3, 0)
 101   BUILTIN_VQ (STORESTRUCT, st4, 0)
 102
 103   BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0)
 104   BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0)
 105   BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0)
 106
 107   BUILTIN_VQW (BINOP, saddl2, 0)
 108   BUILTIN_VQW (BINOP, uaddl2, 0)
 109   BUILTIN_VQW (BINOP, ssubl2, 0)
 110   BUILTIN_VQW (BINOP, usubl2, 0)
 111   BUILTIN_VQW (BINOP, saddw2, 0)
 112   BUILTIN_VQW (BINOP, uaddw2, 0)
 113   BUILTIN_VQW (BINOP, ssubw2, 0)
 114   BUILTIN_VQW (BINOP, usubw2, 0)
 115   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
 116   BUILTIN_VDW (BINOP, saddl, 0)
 117   BUILTIN_VDW (BINOP, uaddl, 0)
 118   BUILTIN_VDW (BINOP, ssubl, 0)
 119   BUILTIN_VDW (BINOP, usubl, 0)
 120   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
 121   BUILTIN_VDW (BINOP, saddw, 0)
 122   BUILTIN_VDW (BINOP, uaddw, 0)
 123   BUILTIN_VDW (BINOP, ssubw, 0)
 124   BUILTIN_VDW (BINOP, usubw, 0)
 125   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
 126   BUILTIN_VQ_S (BINOP, shadd, 0)
 127   BUILTIN_VQ_S (BINOP, uhadd, 0)
 128   BUILTIN_VQ_S (BINOP, srhadd, 0)
 129   BUILTIN_VQ_S (BINOP, urhadd, 0)
 130   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
 131   BUILTIN_VQN (BINOP, addhn, 0)
 132   BUILTIN_VQN (BINOP, raddhn, 0)
 133   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
 134   BUILTIN_VQN (TERNOP, addhn2, 0)
 135   BUILTIN_VQN (TERNOP, raddhn2, 0)
 136
 137   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
 138   /* Implemented by aarch64_<sur>qmovn<mode>.  */
 139   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
 140   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
 141   /* Implemented by aarch64_s<optab><mode>.  */
 142   BUILTIN_VSDQ_I (UNOP, sqabs, 0)
 143   BUILTIN_VSDQ_I (UNOP, sqneg, 0)
 144
 145   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
 146   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
 147   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
 148   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>.  */
 149   BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0)
 150   BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0)
 151   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>.  */
 152   BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0)
 153   BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0)
 154   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
 155   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
 156   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 157
 158   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
 159   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
 160   BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0)
 161   BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0)
 162   BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0)
 163   BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0)
 164   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
 165   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
 166
 167   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
 168   BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0)
 169   BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0)
 170   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
 171   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
 172   BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0)
 173   BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0)
 174   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
 175   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
 176   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
 177   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
 178   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
 179   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0)
 180   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0)
 181   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0)
 182   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0)
 183
 184   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
 185   /* Implemented by aarch64_<sur>shl<mode>.  */
 186   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
 187   BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0)
 188   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
 189   BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
 190
 191   BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
 192   VAR1 (SHIFTIMM, ashr_simd, 0, di)
 193   BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
 194   VAR1 (USHIFTIMM, lshr_simd, 0, di)
 195   /* Implemented by aarch64_<sur>shr_n<mode>.  */
 196   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
 197   BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0)
 198   /* Implemented by aarch64_<sur>sra_n<mode>.  */
 199   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
 200   BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0)
 201   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
 202   BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
 203   /* Implemented by aarch64_<sur>shll_n<mode>.  */
 204   BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
 205   BUILTIN_VDW (USHIFTIMM, ushll_n, 0)
 206   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
 207   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
 208   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
 209   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
 210   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
 211   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
 212   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
 213   BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0)
 214   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
 215   BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0)
 216   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
 217   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
 218   BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
 219   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
 220   BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
 221   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
 222   BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
 223   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
 224   BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
 225
 226   /* Implemented by aarch64_reduc_plus_<mode>.  */
 227   BUILTIN_VALL (UNOP, reduc_plus_scal_, 10)
 228
 229   /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar).  */
 230   BUILTIN_VDQIF (UNOP, reduc_smax_scal_, 10)
 231   BUILTIN_VDQIF (UNOP, reduc_smin_scal_, 10)
 232   BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10)
 233   BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10)
 234   BUILTIN_VDQF (UNOP, reduc_smax_nan_scal_, 10)
 235   BUILTIN_VDQF (UNOP, reduc_smin_nan_scal_, 10)
 236
 237   /* Implemented by <maxmin><mode>3.
 238      smax variants map to fmaxnm,
 239      smax_nan variants map to fmax.  */
 240   BUILTIN_VDQIF (BINOP, smax, 3)
 241   BUILTIN_VDQIF (BINOP, smin, 3)
 242   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
 243   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
 244   BUILTIN_VDQF (BINOP, smax_nan, 3)
 245   BUILTIN_VDQF (BINOP, smin_nan, 3)
 246
 247   /* Implemented by <frint_pattern><mode>2.  */
 248   BUILTIN_VDQF (UNOP, btrunc, 2)
 249   BUILTIN_VDQF (UNOP, ceil, 2)
 250   BUILTIN_VDQF (UNOP, floor, 2)
 251   BUILTIN_VDQF (UNOP, nearbyint, 2)
 252   BUILTIN_VDQF (UNOP, rint, 2)
 253   BUILTIN_VDQF (UNOP, round, 2)
 254   BUILTIN_VDQF_DF (UNOP, frintn, 2)
 255
 256   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
 257   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
 258   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
 259   VAR1 (UNOP, lbtruncv2df, 2, v2di)
 260
 261   VAR1 (UNOP, lbtruncuv2sf, 2, v2si)
 262   VAR1 (UNOP, lbtruncuv4sf, 2, v4si)
 263   VAR1 (UNOP, lbtruncuv2df, 2, v2di)
 264
 265   VAR1 (UNOP, lroundv2sf, 2, v2si)
 266   VAR1 (UNOP, lroundv4sf, 2, v4si)
 267   VAR1 (UNOP, lroundv2df, 2, v2di)
 268   /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2.  */
 269   VAR1 (UNOP, lroundsf, 2, si)
 270   VAR1 (UNOP, lrounddf, 2, di)
 271
 272   VAR1 (UNOP, lrounduv2sf, 2, v2si)
 273   VAR1 (UNOP, lrounduv4sf, 2, v4si)
 274   VAR1 (UNOP, lrounduv2df, 2, v2di)
 275   VAR1 (UNOP, lroundusf, 2, si)
 276   VAR1 (UNOP, lroundudf, 2, di)
 277
 278   VAR1 (UNOP, lceilv2sf, 2, v2si)
 279   VAR1 (UNOP, lceilv4sf, 2, v4si)
 280   VAR1 (UNOP, lceilv2df, 2, v2di)
 281
 282   VAR1 (UNOP, lceiluv2sf, 2, v2si)
 283   VAR1 (UNOP, lceiluv4sf, 2, v4si)
 284   VAR1 (UNOP, lceiluv2df, 2, v2di)
 285   VAR1 (UNOP, lceilusf, 2, si)
 286   VAR1 (UNOP, lceiludf, 2, di)
 287
 288   VAR1 (UNOP, lfloorv2sf, 2, v2si)
 289   VAR1 (UNOP, lfloorv4sf, 2, v4si)
 290   VAR1 (UNOP, lfloorv2df, 2, v2di)
 291
 292   VAR1 (UNOP, lflooruv2sf, 2, v2si)
 293   VAR1 (UNOP, lflooruv4sf, 2, v4si)
 294   VAR1 (UNOP, lflooruv2df, 2, v2di)
 295   VAR1 (UNOP, lfloorusf, 2, si)
 296   VAR1 (UNOP, lfloorudf, 2, di)
 297
 298   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
 299   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
 300   VAR1 (UNOP, lfrintnv2df, 2, v2di)
 301   VAR1 (UNOP, lfrintnsf, 2, si)
 302   VAR1 (UNOP, lfrintndf, 2, di)
 303
 304   VAR1 (UNOP, lfrintnuv2sf, 2, v2si)
 305   VAR1 (UNOP, lfrintnuv4sf, 2, v4si)
 306   VAR1 (UNOP, lfrintnuv2df, 2, v2di)
 307   VAR1 (UNOP, lfrintnusf, 2, si)
 308   VAR1 (UNOP, lfrintnudf, 2, di)
 309
 310   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
 311   VAR1 (UNOP, floatv2si, 2, v2sf)
 312   VAR1 (UNOP, floatv4si, 2, v4sf)
 313   VAR1 (UNOP, floatv2di, 2, v2df)
 314
 315   VAR1 (UNOP, floatunsv2si, 2, v2sf)
 316   VAR1 (UNOP, floatunsv4si, 2, v4sf)
 317   VAR1 (UNOP, floatunsv2di, 2, v2df)
 318
 319   VAR5 (UNOPU, bswap, 10, v4hi, v8hi, v2si, v4si, v2di)
 320
 321   BUILTIN_VB (UNOP, rbit, 0)
 322
 323   /* Implemented by
 324      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
 325   BUILTIN_VALL (BINOP, zip1, 0)
 326   BUILTIN_VALL (BINOP, zip2, 0)
 327   BUILTIN_VALL (BINOP, uzp1, 0)
 328   BUILTIN_VALL (BINOP, uzp2, 0)
 329   BUILTIN_VALL (BINOP, trn1, 0)
 330   BUILTIN_VALL (BINOP, trn2, 0)
 331
 332   /* Implemented by
 333      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
 334   BUILTIN_GPF (UNOP, frecpe, 0)
 335   BUILTIN_GPF (BINOP, frecps, 0)
 336   BUILTIN_GPF (UNOP, frecpx, 0)
 337
 338   BUILTIN_VDQF (UNOP, frecpe, 0)
 339   BUILTIN_VDQF (BINOP, frecps, 0)
 340
 341   /* Implemented by a mixture of abs2 patterns.  Note the DImode builtin is
 342      only ever used for the int64x1_t intrinsic, there is no scalar version.  */
 343   BUILTIN_VALLDI (UNOP, abs, 2)
 344
 345   VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
 346   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
 347
 348   VAR1 (UNOP, float_extend_lo_, 0, v2df)
 349   VAR1 (UNOP, float_truncate_lo_, 0, v2sf)
 350
 351   /* Implemented by aarch64_ld1<VALL:mode>.  */
 352   BUILTIN_VALL (LOAD1, ld1, 0)
 353
 354   /* Implemented by aarch64_st1<VALL:mode>.  */
 355   BUILTIN_VALL (STORE1, st1, 0)
 356
 357   /* Implemented by fma<mode>4.  */
 358   BUILTIN_VDQF (TERNOP, fma, 4)
 359
 360   /* Implemented by aarch64_simd_bsl<mode>.  */
 361   BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
 362   BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
 363   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
 364
 365   /* Implemented by aarch64_crypto_aes<op><mode>.  */
 366   VAR1 (BINOPU, crypto_aese, 0, v16qi)
 367   VAR1 (BINOPU, crypto_aesd, 0, v16qi)
 368   VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
 369   VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
 370
 371   /* Implemented by aarch64_crypto_sha1<op><mode>.  */
 372   VAR1 (UNOPU, crypto_sha1h, 0, si)
 373   VAR1 (BINOPU, crypto_sha1su1, 0, v4si)
 374   VAR1 (TERNOPU, crypto_sha1c, 0, v4si)
 375   VAR1 (TERNOPU, crypto_sha1m, 0, v4si)
 376   VAR1 (TERNOPU, crypto_sha1p, 0, v4si)
 377   VAR1 (TERNOPU, crypto_sha1su0, 0, v4si)
 378
 379   /* Implemented by aarch64_crypto_sha256<op><mode>.  */
 380   VAR1 (TERNOPU, crypto_sha256h, 0, v4si)
 381   VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
 382   VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
 383   VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
 384
 385   /* Implemented by aarch64_crypto_pmull<mode>.  */
 386   VAR1 (BINOPP, crypto_pmull, 0, di)
 387   VAR1 (BINOPP, crypto_pmull, 0, v2di)
 388
 389   /* Meta-op to check lane bounds of immediate in aarch64_expand_builtin.  */
 390   VAR1 (BINOPV, im_lane_bound, 0, si)