gcc/config/aarch64/aarch64-simd-builtins.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2014 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
  22    builtins for each of the modes described by <ITERATOR>.  When adding
  23    new builtins to this list, a helpful idiom to follow is to add
  24    a line for each pattern in the md file.  Thus, ADDP, which has one
  25    pattern defined for the VD_BHSI iterator, and one for DImode, has two
  26    entries below.
  27
  28    Parameter 1 is the 'type' of the intrinsic.  This is used to
  29    describe the type modifiers (for example; unsigned) applied to
  30    each of the parameters to the intrinsic function.
  31
  32    Parameter 2 is the name of the intrinsic.  This is appended
  33    to `__builtin_aarch64_<name><mode>` to give the intrinsic name
  34    as exported to the front-ends.
  35
  36    Parameter 3 describes how to map from the name to the CODE_FOR_
  37    macro holding the RTL pattern for the intrinsic.  This mapping is:
  38    0 - CODE_FOR_aarch64_<name><mode>
  39    1-9 - CODE_FOR_<name><mode><1-9>
  40    10 - CODE_FOR_<name><mode>.  */
  41
  42   BUILTIN_VD_RE (CREATE, create, 0)
  43   BUILTIN_VDC (COMBINE, combine, 0)
  44   BUILTIN_VB (BINOP, pmul, 0)
  45   BUILTIN_VDQF (UNOP, sqrt, 2)
  46   BUILTIN_VD_BHSI (BINOP, addp, 0)
  47   VAR1 (UNOP, addp, 0, di)
  48   BUILTIN_VDQ_BHSI (UNOP, clz, 2)
  49
  50   BUILTIN_VALL (GETLANE, get_lane, 0)
  51   VAR1 (GETLANE, get_lane, 0, di)
  52   BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
  53
  54   VAR1 (REINTERP_SS, reinterpretdi, 0, df)
  55   VAR1 (REINTERP_SS, reinterpretv8qi, 0, df)
  56   VAR1 (REINTERP_SS, reinterpretv4hi, 0, df)
  57   VAR1 (REINTERP_SS, reinterpretv2si, 0, df)
  58   VAR1 (REINTERP_SS, reinterpretv2sf, 0, df)
  59   BUILTIN_VD (REINTERP_SS, reinterpretdf, 0)
  60
  61   BUILTIN_VD (REINTERP_SU, reinterpretdf, 0)
  62
  63   VAR1 (REINTERP_US, reinterpretdi, 0, df)
  64   VAR1 (REINTERP_US, reinterpretv8qi, 0, df)
  65   VAR1 (REINTERP_US, reinterpretv4hi, 0, df)
  66   VAR1 (REINTERP_US, reinterpretv2si, 0, df)
  67   VAR1 (REINTERP_US, reinterpretv2sf, 0, df)
  68
  69   BUILTIN_VD (REINTERP_SP, reinterpretdf, 0)
  70
  71   VAR1 (REINTERP_PS, reinterpretdi, 0, df)
  72   VAR1 (REINTERP_PS, reinterpretv8qi, 0, df)
  73   VAR1 (REINTERP_PS, reinterpretv4hi, 0, df)
  74   VAR1 (REINTERP_PS, reinterpretv2si, 0, df)
  75   VAR1 (REINTERP_PS, reinterpretv2sf, 0, df)
  76
  77   BUILTIN_VDQ_I (BINOP, dup_lane, 0)
  78   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
  79   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
  80   BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)
  81   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
  82   BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0)
  83   /* Implemented by aarch64_<su_optab><optab><mode>.  */
  84   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
  85   BUILTIN_VSDQ_I (BINOPU, uqadd, 0)
  86   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
  87   BUILTIN_VSDQ_I (BINOPU, uqsub, 0)
  88   /* Implemented by aarch64_<sur>qadd<mode>.  */
  89   BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0)
  90   BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
  91
  92   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
  93   BUILTIN_VDC (GETLANE, get_dregoi, 0)
  94   BUILTIN_VDC (GETLANE, get_dregci, 0)
  95   BUILTIN_VDC (GETLANE, get_dregxi, 0)
  96   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
  97   BUILTIN_VQ (GETLANE, get_qregoi, 0)
  98   BUILTIN_VQ (GETLANE, get_qregci, 0)
  99   BUILTIN_VQ (GETLANE, get_qregxi, 0)
 100   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
 101   BUILTIN_VQ (SETLANE, set_qregoi, 0)
 102   BUILTIN_VQ (SETLANE, set_qregci, 0)
 103   BUILTIN_VQ (SETLANE, set_qregxi, 0)
 104   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
 105   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
 106   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
 107   BUILTIN_VDC (LOADSTRUCT, ld4, 0)
 108   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
 109   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
 110   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
 111   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
 112   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
 113   BUILTIN_VDC (STORESTRUCT, st2, 0)
 114   BUILTIN_VDC (STORESTRUCT, st3, 0)
 115   BUILTIN_VDC (STORESTRUCT, st4, 0)
 116   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
 117   BUILTIN_VQ (STORESTRUCT, st2, 0)
 118   BUILTIN_VQ (STORESTRUCT, st3, 0)
 119   BUILTIN_VQ (STORESTRUCT, st4, 0)
 120
 121   BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0)
 122   BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0)
 123   BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0)
 124
 125   BUILTIN_VQW (BINOP, saddl2, 0)
 126   BUILTIN_VQW (BINOP, uaddl2, 0)
 127   BUILTIN_VQW (BINOP, ssubl2, 0)
 128   BUILTIN_VQW (BINOP, usubl2, 0)
 129   BUILTIN_VQW (BINOP, saddw2, 0)
 130   BUILTIN_VQW (BINOP, uaddw2, 0)
 131   BUILTIN_VQW (BINOP, ssubw2, 0)
 132   BUILTIN_VQW (BINOP, usubw2, 0)
 133   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
 134   BUILTIN_VDW (BINOP, saddl, 0)
 135   BUILTIN_VDW (BINOP, uaddl, 0)
 136   BUILTIN_VDW (BINOP, ssubl, 0)
 137   BUILTIN_VDW (BINOP, usubl, 0)
 138   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
 139   BUILTIN_VDW (BINOP, saddw, 0)
 140   BUILTIN_VDW (BINOP, uaddw, 0)
 141   BUILTIN_VDW (BINOP, ssubw, 0)
 142   BUILTIN_VDW (BINOP, usubw, 0)
 143   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
 144   BUILTIN_VQ_S (BINOP, shadd, 0)
 145   BUILTIN_VQ_S (BINOP, uhadd, 0)
 146   BUILTIN_VQ_S (BINOP, srhadd, 0)
 147   BUILTIN_VQ_S (BINOP, urhadd, 0)
 148   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
 149   BUILTIN_VQN (BINOP, addhn, 0)
 150   BUILTIN_VQN (BINOP, raddhn, 0)
 151   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
 152   BUILTIN_VQN (TERNOP, addhn2, 0)
 153   BUILTIN_VQN (TERNOP, raddhn2, 0)
 154
 155   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
 156   /* Implemented by aarch64_<sur>qmovn<mode>.  */
 157   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
 158   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
 159   /* Implemented by aarch64_s<optab><mode>.  */
 160   BUILTIN_VSDQ_I (UNOP, sqabs, 0)
 161   BUILTIN_VSDQ_I (UNOP, sqneg, 0)
 162
 163   BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
 164   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)
 165   BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0)
 166   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0)
 167   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
 168   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
 169   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0)
 170   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0)
 171   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0)
 172   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0)
 173   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
 174   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
 175   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
 176   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
 177   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
 178   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
 179   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
 180   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 181
 182   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
 183   BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0)
 184   BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0)
 185   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
 186   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
 187   BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0)
 188   BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0)
 189   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
 190   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
 191   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
 192   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
 193   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
 194   BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0)
 195   BUILTIN_VDQHS (TERNOP, sqdmulh_laneq, 0)
 196   BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0)
 197   BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq, 0)
 198   BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0)
 199   BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0)
 200
 201   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
 202   /* Implemented by aarch64_<sur>shl<mode>.  */
 203   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
 204   BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0)
 205   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
 206   BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
 207
 208   BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
 209   VAR1 (SHIFTIMM, ashr_simd, 0, di)
 210   BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
 211   VAR1 (USHIFTIMM, lshr_simd, 0, di)
 212   /* Implemented by aarch64_<sur>shr_n<mode>.  */
 213   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
 214   BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0)
 215   /* Implemented by aarch64_<sur>sra_n<mode>.  */
 216   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
 217   BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0)
 218   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
 219   BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
 220   /* Implemented by aarch64_<sur>shll_n<mode>.  */
 221   BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
 222   BUILTIN_VDW (USHIFTIMM, ushll_n, 0)
 223   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
 224   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
 225   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
 226   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
 227   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
 228   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
 229   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
 230   BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0)
 231   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
 232   BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0)
 233   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
 234   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
 235   BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
 236   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
 237   BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
 238   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
 239   BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
 240   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
 241   BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
 242
 243   /* Implemented by aarch64_cm<cmp><mode>.  */
 244   BUILTIN_VALLDI (BINOP, cmeq, 0)
 245   BUILTIN_VALLDI (BINOP, cmge, 0)
 246   BUILTIN_VALLDI (BINOP, cmgt, 0)
 247   BUILTIN_VALLDI (BINOP, cmle, 0)
 248   BUILTIN_VALLDI (BINOP, cmlt, 0)
 249   /* Implemented by aarch64_cm<cmp><mode>.  */
 250   BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0)
 251   BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
 252   BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
 253
 254   /* Implemented by reduc_<sur>plus_<mode>.  */
 255   BUILTIN_VALL (UNOP, reduc_splus_, 10)
 256   BUILTIN_VDQ (UNOP, reduc_uplus_, 10)
 257
 258   /* Implemented by reduc_<maxmin_uns>_<mode>.  */
 259   BUILTIN_VDQIF (UNOP, reduc_smax_, 10)
 260   BUILTIN_VDQIF (UNOP, reduc_smin_, 10)
 261   BUILTIN_VDQ_BHSI (UNOP, reduc_umax_, 10)
 262   BUILTIN_VDQ_BHSI (UNOP, reduc_umin_, 10)
 263   BUILTIN_VDQF (UNOP, reduc_smax_nan_, 10)
 264   BUILTIN_VDQF (UNOP, reduc_smin_nan_, 10)
 265
 266   /* Implemented by <maxmin><mode>3.
 267      smax variants map to fmaxnm,
 268      smax_nan variants map to fmax.  */
 269   BUILTIN_VDQIF (BINOP, smax, 3)
 270   BUILTIN_VDQIF (BINOP, smin, 3)
 271   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
 272   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
 273   BUILTIN_VDQF (BINOP, smax_nan, 3)
 274   BUILTIN_VDQF (BINOP, smin_nan, 3)
 275
 276   /* Implemented by <frint_pattern><mode>2.  */
 277   BUILTIN_VDQF (UNOP, btrunc, 2)
 278   BUILTIN_VDQF (UNOP, ceil, 2)
 279   BUILTIN_VDQF (UNOP, floor, 2)
 280   BUILTIN_VDQF (UNOP, nearbyint, 2)
 281   BUILTIN_VDQF (UNOP, rint, 2)
 282   BUILTIN_VDQF (UNOP, round, 2)
 283   BUILTIN_VDQF_DF (UNOP, frintn, 2)
 284
 285   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
 286   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
 287   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
 288   VAR1 (UNOP, lbtruncv2df, 2, v2di)
 289
 290   VAR1 (UNOP, lbtruncuv2sf, 2, v2si)
 291   VAR1 (UNOP, lbtruncuv4sf, 2, v4si)
 292   VAR1 (UNOP, lbtruncuv2df, 2, v2di)
 293
 294   VAR1 (UNOP, lroundv2sf, 2, v2si)
 295   VAR1 (UNOP, lroundv4sf, 2, v4si)
 296   VAR1 (UNOP, lroundv2df, 2, v2di)
 297   /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2.  */
 298   VAR1 (UNOP, lroundsf, 2, si)
 299   VAR1 (UNOP, lrounddf, 2, di)
 300
 301   VAR1 (UNOP, lrounduv2sf, 2, v2si)
 302   VAR1 (UNOP, lrounduv4sf, 2, v4si)
 303   VAR1 (UNOP, lrounduv2df, 2, v2di)
 304   VAR1 (UNOP, lroundusf, 2, si)
 305   VAR1 (UNOP, lroundudf, 2, di)
 306
 307   VAR1 (UNOP, lceilv2sf, 2, v2si)
 308   VAR1 (UNOP, lceilv4sf, 2, v4si)
 309   VAR1 (UNOP, lceilv2df, 2, v2di)
 310
 311   VAR1 (UNOP, lceiluv2sf, 2, v2si)
 312   VAR1 (UNOP, lceiluv4sf, 2, v4si)
 313   VAR1 (UNOP, lceiluv2df, 2, v2di)
 314   VAR1 (UNOP, lceilusf, 2, si)
 315   VAR1 (UNOP, lceiludf, 2, di)
 316
 317   VAR1 (UNOP, lfloorv2sf, 2, v2si)
 318   VAR1 (UNOP, lfloorv4sf, 2, v4si)
 319   VAR1 (UNOP, lfloorv2df, 2, v2di)
 320
 321   VAR1 (UNOP, lflooruv2sf, 2, v2si)
 322   VAR1 (UNOP, lflooruv4sf, 2, v4si)
 323   VAR1 (UNOP, lflooruv2df, 2, v2di)
 324   VAR1 (UNOP, lfloorusf, 2, si)
 325   VAR1 (UNOP, lfloorudf, 2, di)
 326
 327   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
 328   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
 329   VAR1 (UNOP, lfrintnv2df, 2, v2di)
 330   VAR1 (UNOP, lfrintnsf, 2, si)
 331   VAR1 (UNOP, lfrintndf, 2, di)
 332
 333   VAR1 (UNOP, lfrintnuv2sf, 2, v2si)
 334   VAR1 (UNOP, lfrintnuv4sf, 2, v4si)
 335   VAR1 (UNOP, lfrintnuv2df, 2, v2di)
 336   VAR1 (UNOP, lfrintnusf, 2, si)
 337   VAR1 (UNOP, lfrintnudf, 2, di)
 338
 339   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
 340   VAR1 (UNOP, floatv2si, 2, v2sf)
 341   VAR1 (UNOP, floatv4si, 2, v4sf)
 342   VAR1 (UNOP, floatv2di, 2, v2df)
 343
 344   VAR1 (UNOP, floatunsv2si, 2, v2sf)
 345   VAR1 (UNOP, floatunsv4si, 2, v4sf)
 346   VAR1 (UNOP, floatunsv2di, 2, v2df)
 347
 348   VAR5 (UNOPU, bswap, 10, v4hi, v8hi, v2si, v4si, v2di)
 349
 350   /* Implemented by
 351      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
 352   BUILTIN_VALL (BINOP, zip1, 0)
 353   BUILTIN_VALL (BINOP, zip2, 0)
 354   BUILTIN_VALL (BINOP, uzp1, 0)
 355   BUILTIN_VALL (BINOP, uzp2, 0)
 356   BUILTIN_VALL (BINOP, trn1, 0)
 357   BUILTIN_VALL (BINOP, trn2, 0)
 358
 359   /* Implemented by
 360      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
 361   BUILTIN_GPF (UNOP, frecpe, 0)
 362   BUILTIN_GPF (BINOP, frecps, 0)
 363   BUILTIN_GPF (UNOP, frecpx, 0)
 364
 365   BUILTIN_VDQF (UNOP, frecpe, 0)
 366   BUILTIN_VDQF (BINOP, frecps, 0)
 367
 368   BUILTIN_VALLDI (UNOP, abs, 2)
 369
 370   VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
 371   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
 372
 373   VAR1 (UNOP, float_extend_lo_, 0, v2df)
 374   VAR1 (UNOP, float_truncate_lo_, 0, v2sf)
 375
 376   /* Implemented by aarch64_ld1<VALL:mode>.  */
 377   BUILTIN_VALL (LOAD1, ld1, 0)
 378
 379   /* Implemented by aarch64_st1<VALL:mode>.  */
 380   BUILTIN_VALL (STORE1, st1, 0)
 381
 382   /* Implemented by fma<mode>4.  */
 383   BUILTIN_VDQF (TERNOP, fma, 4)
 384
 385   /* Implemented by aarch64_simd_bsl<mode>.  */
 386   BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
 387   BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
 388   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
 389
 390   /* Implemented by aarch64_crypto_aes<op><mode>.  */
 391   VAR1 (BINOPU, crypto_aese, 0, v16qi)
 392   VAR1 (BINOPU, crypto_aesd, 0, v16qi)
 393   VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
 394   VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
 395
 396   /* Implemented by aarch64_crypto_sha1<op><mode>.  */
 397   VAR1 (UNOPU, crypto_sha1h, 0, si)
 398   VAR1 (BINOPU, crypto_sha1su1, 0, v4si)
 399   VAR1 (TERNOPU, crypto_sha1c, 0, v4si)
 400   VAR1 (TERNOPU, crypto_sha1m, 0, v4si)
 401   VAR1 (TERNOPU, crypto_sha1p, 0, v4si)
 402   VAR1 (TERNOPU, crypto_sha1su0, 0, v4si)
 403
 404   /* Implemented by aarch64_crypto_sha256<op><mode>.  */
 405   VAR1 (TERNOPU, crypto_sha256h, 0, v4si)
 406   VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
 407   VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
 408   VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
 409
 410   /* Implemented by aarch64_crypto_pmull<mode>.  */
 411   VAR1 (BINOPP, crypto_pmull, 0, di)
 412   VAR1 (BINOPP, crypto_pmull, 0, v2di)
 413
 414   /* Meta-op to check lane bounds of immediate in aarch64_expand_builtin.  */
 415   VAR1 (BINOPV, im_lane_bound, 0, si)