gcc/config/aarch64/aarch64-simd-builtins.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2014 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
  22    builtins for each of the modes described by <ITERATOR>.  When adding
  23    new builtins to this list, a helpful idiom to follow is to add
  24    a line for each pattern in the md file.  Thus, ADDP, which has one
  25    pattern defined for the VD_BHSI iterator, and one for DImode, has two
  26    entries below.
  27
  28    Parameter 1 is the 'type' of the intrinsic.  This is used to
  29    describe the type modifiers (for example; unsigned) applied to
  30    each of the parameters to the intrinsic function.
  31
  32    Parameter 2 is the name of the intrinsic.  This is appended
  33    to `__builtin_aarch64_<name><mode>` to give the intrinsic name
  34    as exported to the front-ends.
  35
  36    Parameter 3 describes how to map from the name to the CODE_FOR_
  37    macro holding the RTL pattern for the intrinsic.  This mapping is:
  38    0 - CODE_FOR_aarch64_<name><mode>
  39    1-9 - CODE_FOR_<name><mode><1-9>
  40    10 - CODE_FOR_<name><mode>.  */
  41
  42   BUILTIN_VD1 (CREATE, create, 0)
  43   BUILTIN_VDC (COMBINE, combine, 0)
  44   BUILTIN_VB (BINOP, pmul, 0)
  45   BUILTIN_VDQF (UNOP, sqrt, 2)
  46   BUILTIN_VD_BHSI (BINOP, addp, 0)
  47   VAR1 (UNOP, addp, 0, di)
  48   BUILTIN_VDQ_BHSI (UNOP, clz, 2)
  49
  50   BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
  51
  52   VAR1 (REINTERP_SS, reinterpretdi, 0, v1df)
  53   VAR1 (REINTERP_SS, reinterpretv8qi, 0, v1df)
  54   VAR1 (REINTERP_SS, reinterpretv4hi, 0, v1df)
  55   VAR1 (REINTERP_SS, reinterpretv2si, 0, v1df)
  56   VAR1 (REINTERP_SS, reinterpretv2sf, 0, v1df)
  57   BUILTIN_VD (REINTERP_SS, reinterpretv1df, 0)
  58
  59   BUILTIN_VD (REINTERP_SU, reinterpretv1df, 0)
  60
  61   VAR1 (REINTERP_US, reinterpretdi, 0, v1df)
  62   VAR1 (REINTERP_US, reinterpretv8qi, 0, v1df)
  63   VAR1 (REINTERP_US, reinterpretv4hi, 0, v1df)
  64   VAR1 (REINTERP_US, reinterpretv2si, 0, v1df)
  65   VAR1 (REINTERP_US, reinterpretv2sf, 0, v1df)
  66
  67   BUILTIN_VD (REINTERP_SP, reinterpretv1df, 0)
  68
  69   VAR1 (REINTERP_PS, reinterpretdi, 0, v1df)
  70   VAR1 (REINTERP_PS, reinterpretv8qi, 0, v1df)
  71   VAR1 (REINTERP_PS, reinterpretv4hi, 0, v1df)
  72   VAR1 (REINTERP_PS, reinterpretv2si, 0, v1df)
  73   VAR1 (REINTERP_PS, reinterpretv2sf, 0, v1df)
  74
  75   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
  76   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
  77   BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)
  78   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
  79   BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0)
  80   /* Implemented by aarch64_<su_optab><optab><mode>.  */
  81   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
  82   BUILTIN_VSDQ_I (BINOPU, uqadd, 0)
  83   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
  84   BUILTIN_VSDQ_I (BINOPU, uqsub, 0)
  85   /* Implemented by aarch64_<sur>qadd<mode>.  */
  86   BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0)
  87   BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
  88
  89   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
  90   BUILTIN_VDC (GETLANE, get_dregoi, 0)
  91   BUILTIN_VDC (GETLANE, get_dregci, 0)
  92   BUILTIN_VDC (GETLANE, get_dregxi, 0)
  93   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
  94   BUILTIN_VQ (GETLANE, get_qregoi, 0)
  95   BUILTIN_VQ (GETLANE, get_qregci, 0)
  96   BUILTIN_VQ (GETLANE, get_qregxi, 0)
  97   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
  98   BUILTIN_VQ (SETLANE, set_qregoi, 0)
  99   BUILTIN_VQ (SETLANE, set_qregci, 0)
 100   BUILTIN_VQ (SETLANE, set_qregxi, 0)
 101   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
 102   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
 103   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
 104   BUILTIN_VDC (LOADSTRUCT, ld4, 0)
 105   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
 106   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
 107   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
 108   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
 109   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
 110   BUILTIN_VDC (STORESTRUCT, st2, 0)
 111   BUILTIN_VDC (STORESTRUCT, st3, 0)
 112   BUILTIN_VDC (STORESTRUCT, st4, 0)
 113   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
 114   BUILTIN_VQ (STORESTRUCT, st2, 0)
 115   BUILTIN_VQ (STORESTRUCT, st3, 0)
 116   BUILTIN_VQ (STORESTRUCT, st4, 0)
 117
 118   BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0)
 119   BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0)
 120   BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0)
 121
 122   BUILTIN_VQW (BINOP, saddl2, 0)
 123   BUILTIN_VQW (BINOP, uaddl2, 0)
 124   BUILTIN_VQW (BINOP, ssubl2, 0)
 125   BUILTIN_VQW (BINOP, usubl2, 0)
 126   BUILTIN_VQW (BINOP, saddw2, 0)
 127   BUILTIN_VQW (BINOP, uaddw2, 0)
 128   BUILTIN_VQW (BINOP, ssubw2, 0)
 129   BUILTIN_VQW (BINOP, usubw2, 0)
 130   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
 131   BUILTIN_VDW (BINOP, saddl, 0)
 132   BUILTIN_VDW (BINOP, uaddl, 0)
 133   BUILTIN_VDW (BINOP, ssubl, 0)
 134   BUILTIN_VDW (BINOP, usubl, 0)
 135   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
 136   BUILTIN_VDW (BINOP, saddw, 0)
 137   BUILTIN_VDW (BINOP, uaddw, 0)
 138   BUILTIN_VDW (BINOP, ssubw, 0)
 139   BUILTIN_VDW (BINOP, usubw, 0)
 140   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
 141   BUILTIN_VQ_S (BINOP, shadd, 0)
 142   BUILTIN_VQ_S (BINOP, uhadd, 0)
 143   BUILTIN_VQ_S (BINOP, srhadd, 0)
 144   BUILTIN_VQ_S (BINOP, urhadd, 0)
 145   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
 146   BUILTIN_VQN (BINOP, addhn, 0)
 147   BUILTIN_VQN (BINOP, raddhn, 0)
 148   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
 149   BUILTIN_VQN (TERNOP, addhn2, 0)
 150   BUILTIN_VQN (TERNOP, raddhn2, 0)
 151
 152   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
 153   /* Implemented by aarch64_<sur>qmovn<mode>.  */
 154   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
 155   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
 156   /* Implemented by aarch64_s<optab><mode>.  */
 157   BUILTIN_VSDQ_I (UNOP, sqabs, 0)
 158   BUILTIN_VSDQ_I (UNOP, sqneg, 0)
 159
 160   BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
 161   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)
 162   BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0)
 163   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0)
 164   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
 165   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
 166   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0)
 167   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0)
 168   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0)
 169   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0)
 170   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
 171   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
 172   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
 173   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
 174   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
 175   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
 176   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
 177   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 178
 179   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
 180   BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0)
 181   BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0)
 182   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
 183   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
 184   BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0)
 185   BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0)
 186   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
 187   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
 188   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
 189   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
 190   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
 191   BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0)
 192   BUILTIN_VSDQ_HSI (TERNOP, sqdmulh_laneq, 0)
 193   BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0)
 194   BUILTIN_VSDQ_HSI (TERNOP, sqrdmulh_laneq, 0)
 195   BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0)
 196   BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0)
 197
 198   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
 199   /* Implemented by aarch64_<sur>shl<mode>.  */
 200   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
 201   BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0)
 202   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
 203   BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
 204
 205   BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
 206   VAR1 (SHIFTIMM, ashr_simd, 0, di)
 207   BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
 208   VAR1 (USHIFTIMM, lshr_simd, 0, di)
 209   /* Implemented by aarch64_<sur>shr_n<mode>.  */
 210   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
 211   BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0)
 212   /* Implemented by aarch64_<sur>sra_n<mode>.  */
 213   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
 214   BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0)
 215   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
 216   BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
 217   /* Implemented by aarch64_<sur>shll_n<mode>.  */
 218   BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
 219   BUILTIN_VDW (USHIFTIMM, ushll_n, 0)
 220   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
 221   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
 222   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
 223   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
 224   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
 225   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
 226   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
 227   BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0)
 228   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
 229   BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0)
 230   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
 231   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
 232   BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
 233   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
 234   BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
 235   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
 236   BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
 237   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
 238   BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
 239
 240   /* Implemented by aarch64_cm<cmp><mode>.  */
 241   BUILTIN_VALLDI (BINOP, cmeq, 0)
 242   BUILTIN_VALLDI (BINOP, cmge, 0)
 243   BUILTIN_VALLDI (BINOP, cmgt, 0)
 244   BUILTIN_VALLDI (BINOP, cmle, 0)
 245   BUILTIN_VALLDI (BINOP, cmlt, 0)
 246   /* Implemented by aarch64_cm<cmp><mode>.  */
 247   BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0)
 248   BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
 249   BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
 250
 251   /* Implemented by reduc_<sur>plus_<mode>.  */
 252   BUILTIN_VALL (UNOP, reduc_splus_, 10)
 253   BUILTIN_VDQ (UNOP, reduc_uplus_, 10)
 254
 255   /* Implemented by reduc_<maxmin_uns>_<mode>.  */
 256   BUILTIN_VDQIF (UNOP, reduc_smax_, 10)
 257   BUILTIN_VDQIF (UNOP, reduc_smin_, 10)
 258   BUILTIN_VDQ_BHSI (UNOP, reduc_umax_, 10)
 259   BUILTIN_VDQ_BHSI (UNOP, reduc_umin_, 10)
 260   BUILTIN_VDQF (UNOP, reduc_smax_nan_, 10)
 261   BUILTIN_VDQF (UNOP, reduc_smin_nan_, 10)
 262
 263   /* Implemented by <maxmin><mode>3.
 264      smax variants map to fmaxnm,
 265      smax_nan variants map to fmax.  */
 266   BUILTIN_VDQIF (BINOP, smax, 3)
 267   BUILTIN_VDQIF (BINOP, smin, 3)
 268   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
 269   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
 270   BUILTIN_VDQF (BINOP, smax_nan, 3)
 271   BUILTIN_VDQF (BINOP, smin_nan, 3)
 272
 273   /* Implemented by <frint_pattern><mode>2.  */
 274   BUILTIN_VDQF (UNOP, btrunc, 2)
 275   BUILTIN_VDQF (UNOP, ceil, 2)
 276   BUILTIN_VDQF (UNOP, floor, 2)
 277   BUILTIN_VDQF (UNOP, nearbyint, 2)
 278   BUILTIN_VDQF (UNOP, rint, 2)
 279   BUILTIN_VDQF (UNOP, round, 2)
 280   BUILTIN_VDQF_DF (UNOP, frintn, 2)
 281
 282   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
 283   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
 284   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
 285   VAR1 (UNOP, lbtruncv2df, 2, v2di)
 286
 287   VAR1 (UNOP, lbtruncuv2sf, 2, v2si)
 288   VAR1 (UNOP, lbtruncuv4sf, 2, v4si)
 289   VAR1 (UNOP, lbtruncuv2df, 2, v2di)
 290
 291   VAR1 (UNOP, lroundv2sf, 2, v2si)
 292   VAR1 (UNOP, lroundv4sf, 2, v4si)
 293   VAR1 (UNOP, lroundv2df, 2, v2di)
 294   /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2.  */
 295   VAR1 (UNOP, lroundsf, 2, si)
 296   VAR1 (UNOP, lrounddf, 2, di)
 297
 298   VAR1 (UNOP, lrounduv2sf, 2, v2si)
 299   VAR1 (UNOP, lrounduv4sf, 2, v4si)
 300   VAR1 (UNOP, lrounduv2df, 2, v2di)
 301   VAR1 (UNOP, lroundusf, 2, si)
 302   VAR1 (UNOP, lroundudf, 2, di)
 303
 304   VAR1 (UNOP, lceilv2sf, 2, v2si)
 305   VAR1 (UNOP, lceilv4sf, 2, v4si)
 306   VAR1 (UNOP, lceilv2df, 2, v2di)
 307
 308   VAR1 (UNOP, lceiluv2sf, 2, v2si)
 309   VAR1 (UNOP, lceiluv4sf, 2, v4si)
 310   VAR1 (UNOP, lceiluv2df, 2, v2di)
 311   VAR1 (UNOP, lceilusf, 2, si)
 312   VAR1 (UNOP, lceiludf, 2, di)
 313
 314   VAR1 (UNOP, lfloorv2sf, 2, v2si)
 315   VAR1 (UNOP, lfloorv4sf, 2, v4si)
 316   VAR1 (UNOP, lfloorv2df, 2, v2di)
 317
 318   VAR1 (UNOP, lflooruv2sf, 2, v2si)
 319   VAR1 (UNOP, lflooruv4sf, 2, v4si)
 320   VAR1 (UNOP, lflooruv2df, 2, v2di)
 321   VAR1 (UNOP, lfloorusf, 2, si)
 322   VAR1 (UNOP, lfloorudf, 2, di)
 323
 324   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
 325   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
 326   VAR1 (UNOP, lfrintnv2df, 2, v2di)
 327   VAR1 (UNOP, lfrintnsf, 2, si)
 328   VAR1 (UNOP, lfrintndf, 2, di)
 329
 330   VAR1 (UNOP, lfrintnuv2sf, 2, v2si)
 331   VAR1 (UNOP, lfrintnuv4sf, 2, v4si)
 332   VAR1 (UNOP, lfrintnuv2df, 2, v2di)
 333   VAR1 (UNOP, lfrintnusf, 2, si)
 334   VAR1 (UNOP, lfrintnudf, 2, di)
 335
 336   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
 337   VAR1 (UNOP, floatv2si, 2, v2sf)
 338   VAR1 (UNOP, floatv4si, 2, v4sf)
 339   VAR1 (UNOP, floatv2di, 2, v2df)
 340
 341   VAR1 (UNOP, floatunsv2si, 2, v2sf)
 342   VAR1 (UNOP, floatunsv4si, 2, v4sf)
 343   VAR1 (UNOP, floatunsv2di, 2, v2df)
 344
 345   VAR5 (UNOPU, bswap, 10, v4hi, v8hi, v2si, v4si, v2di)
 346
 347   /* Implemented by
 348      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
 349   BUILTIN_VALL (BINOP, zip1, 0)
 350   BUILTIN_VALL (BINOP, zip2, 0)
 351   BUILTIN_VALL (BINOP, uzp1, 0)
 352   BUILTIN_VALL (BINOP, uzp2, 0)
 353   BUILTIN_VALL (BINOP, trn1, 0)
 354   BUILTIN_VALL (BINOP, trn2, 0)
 355
 356   /* Implemented by
 357      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
 358   BUILTIN_GPF (UNOP, frecpe, 0)
 359   BUILTIN_GPF (BINOP, frecps, 0)
 360   BUILTIN_GPF (UNOP, frecpx, 0)
 361
 362   BUILTIN_VDQF (UNOP, frecpe, 0)
 363   BUILTIN_VDQF (BINOP, frecps, 0)
 364
 365   /* Implemented by a mixture of abs2 patterns.  Note the DImode builtin is
 366      only ever used for the int64x1_t intrinsic, there is no scalar version.  */
 367   BUILTIN_VALLDI (UNOP, abs, 2)
 368
 369   VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
 370   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
 371
 372   VAR1 (UNOP, float_extend_lo_, 0, v2df)
 373   VAR1 (UNOP, float_truncate_lo_, 0, v2sf)
 374
 375   /* Implemented by aarch64_ld1<VALL:mode>.  */
 376   BUILTIN_VALL (LOAD1, ld1, 0)
 377
 378   /* Implemented by aarch64_st1<VALL:mode>.  */
 379   BUILTIN_VALL (STORE1, st1, 0)
 380
 381   /* Implemented by fma<mode>4.  */
 382   BUILTIN_VDQF (TERNOP, fma, 4)
 383
 384   /* Implemented by aarch64_simd_bsl<mode>.  */
 385   BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
 386   BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
 387   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
 388
 389   /* Implemented by aarch64_crypto_aes<op><mode>.  */
 390   VAR1 (BINOPU, crypto_aese, 0, v16qi)
 391   VAR1 (BINOPU, crypto_aesd, 0, v16qi)
 392   VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
 393   VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
 394
 395   /* Implemented by aarch64_crypto_sha1<op><mode>.  */
 396   VAR1 (UNOPU, crypto_sha1h, 0, si)
 397   VAR1 (BINOPU, crypto_sha1su1, 0, v4si)
 398   VAR1 (TERNOPU, crypto_sha1c, 0, v4si)
 399   VAR1 (TERNOPU, crypto_sha1m, 0, v4si)
 400   VAR1 (TERNOPU, crypto_sha1p, 0, v4si)
 401   VAR1 (TERNOPU, crypto_sha1su0, 0, v4si)
 402
 403   /* Implemented by aarch64_crypto_sha256<op><mode>.  */
 404   VAR1 (TERNOPU, crypto_sha256h, 0, v4si)
 405   VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
 406   VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
 407   VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
 408
 409   /* Implemented by aarch64_crypto_pmull<mode>.  */
 410   VAR1 (BINOPP, crypto_pmull, 0, di)
 411   VAR1 (BINOPP, crypto_pmull, 0, v2di)
 412
 413   /* Meta-op to check lane bounds of immediate in aarch64_expand_builtin.  */
 414   VAR1 (BINOPV, im_lane_bound, 0, si)