gcc/config/aarch64/aarch64.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2017 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_H
  23 #define GCC_AARCH64_H
  24
  25 /* Target CPU builtins.  */
  26 #define TARGET_CPU_CPP_BUILTINS()       \
  27   aarch64_cpu_cpp_builtins (pfile)
  28
  29 \f
  30
  31 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
  32
  33 /* Target machine storage layout.  */
  34
  35 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  36   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  37       && GET_MODE_SIZE (MODE) < 4)              \
  38     {                                           \
  39       if (MODE == QImode || MODE == HImode)     \
  40         {                                       \
  41           MODE = SImode;                        \
  42         }                                       \
  43     }
  44
  45 /* Bits are always numbered from the LSBit.  */
  46 #define BITS_BIG_ENDIAN 0
  47
  48 /* Big/little-endian flavour.  */
  49 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
  50 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
  51
  52 /* AdvSIMD is supported in the default configuration, unless disabled by
  53    -mgeneral-regs-only or by the +nosimd extension.  */
  54 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
  55 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
  56
  57 #define UNITS_PER_WORD          8
  58
  59 #define UNITS_PER_VREG          16
  60
  61 #define PARM_BOUNDARY           64
  62
  63 #define STACK_BOUNDARY          128
  64
  65 #define FUNCTION_BOUNDARY       32
  66
  67 #define EMPTY_FIELD_BOUNDARY    32
  68
  69 #define BIGGEST_ALIGNMENT       128
  70
  71 #define SHORT_TYPE_SIZE         16
  72
  73 #define INT_TYPE_SIZE           32
  74
  75 #define LONG_TYPE_SIZE          (TARGET_ILP32 ? 32 : 64)
  76
  77 #define POINTER_SIZE            (TARGET_ILP32 ? 32 : 64)
  78
  79 #define LONG_LONG_TYPE_SIZE     64
  80
  81 #define FLOAT_TYPE_SIZE         32
  82
  83 #define DOUBLE_TYPE_SIZE        64
  84
  85 #define LONG_DOUBLE_TYPE_SIZE   128
  86
  87 /* The architecture reserves all bits of the address for hardware use,
  88    so the vbit must go into the delta field of pointers to member
  89    functions.  This is the same config as that in the AArch32
  90    port.  */
  91 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
  92
  93 /* Make strings word-aligned so that strcpy from constants will be
  94    faster.  */
  95 #define CONSTANT_ALIGNMENT(EXP, ALIGN)          \
  96   ((TREE_CODE (EXP) == STRING_CST               \
  97     && !optimize_size                           \
  98     && (ALIGN) < BITS_PER_WORD)                 \
  99    ? BITS_PER_WORD : ALIGN)
 100
 101 /* Align definitions of arrays, unions and structures so that
 102    initializations and copies can be made more efficient.  This is not
 103    ABI-changing, so it only affects places where we can see the
 104    definition.  Increasing the alignment tends to introduce padding,
 105    so don't do this when optimizing for size/conserving stack space.  */
 106 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN)                      \
 107   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 108     && (TREE_CODE (EXP) == ARRAY_TYPE                                   \
 109         || TREE_CODE (EXP) == UNION_TYPE                                \
 110         || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 111
 112 /* Align global data.  */
 113 #define DATA_ALIGNMENT(EXP, ALIGN)                      \
 114   AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN)
 115
 116 /* Similarly, make sure that objects on the stack are sensibly aligned.  */
 117 #define LOCAL_ALIGNMENT(EXP, ALIGN)                             \
 118   AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN)
 119
 120 #define STRUCTURE_SIZE_BOUNDARY         8
 121
 122 /* Defined by the ABI */
 123 #define WCHAR_TYPE "unsigned int"
 124 #define WCHAR_TYPE_SIZE                 32
 125
 126 /* Using long long breaks -ansi and -std=c90, so these will need to be
 127    made conditional for an LLP64 ABI.  */
 128
 129 #define SIZE_TYPE       "long unsigned int"
 130
 131 #define PTRDIFF_TYPE    "long int"
 132
 133 #define PCC_BITFIELD_TYPE_MATTERS       1
 134
 135 /* Major revision number of the ARM Architecture implemented by the target.  */
 136 extern unsigned aarch64_architecture_version;
 137
 138 /* Instruction tuning/selection flags.  */
 139
 140 /* Bit values used to identify processor capabilities.  */
 141 #define AARCH64_FL_SIMD       (1 << 0)  /* Has SIMD instructions.  */
 142 #define AARCH64_FL_FP         (1 << 1)  /* Has FP.  */
 143 #define AARCH64_FL_CRYPTO     (1 << 2)  /* Has crypto.  */
 144 #define AARCH64_FL_CRC        (1 << 3)  /* Has CRC.  */
 145 /* ARMv8.1-A architecture extensions.  */
 146 #define AARCH64_FL_LSE        (1 << 4)  /* Has Large System Extensions.  */
 147 #define AARCH64_FL_RDMA       (1 << 5)  /* Has Round Double Multiply Add.  */
 148 #define AARCH64_FL_V8_1       (1 << 6)  /* Has ARMv8.1-A extensions.  */
 149 /* ARMv8.2-A architecture extensions.  */
 150 #define AARCH64_FL_V8_2       (1 << 8)  /* Has ARMv8.2-A features.  */
 151 #define AARCH64_FL_F16        (1 << 9)  /* Has ARMv8.2-A FP16 extensions.  */
 152 /* ARMv8.3-A architecture extensions.  */
 153 #define AARCH64_FL_V8_3       (1 << 10)  /* Has ARMv8.3-A features.  */
 154 #define AARCH64_FL_RCPC       (1 << 11)  /* Has support for RCpc model.  */
 155
 156 /* Has FP and SIMD.  */
 157 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
 158
 159 /* Has FP without SIMD.  */
 160 #define AARCH64_FL_FPQ16      (AARCH64_FL_FP & ~AARCH64_FL_SIMD)
 161
 162 /* Architecture flags that effect instruction selection.  */
 163 #define AARCH64_FL_FOR_ARCH8       (AARCH64_FL_FPSIMD)
 164 #define AARCH64_FL_FOR_ARCH8_1                         \
 165   (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \
 166    | AARCH64_FL_RDMA | AARCH64_FL_V8_1)
 167 #define AARCH64_FL_FOR_ARCH8_2                  \
 168   (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
 169 #define AARCH64_FL_FOR_ARCH8_3                  \
 170   (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3)
 171
 172 /* Macros to test ISA flags.  */
 173
 174 #define AARCH64_ISA_CRC            (aarch64_isa_flags & AARCH64_FL_CRC)
 175 #define AARCH64_ISA_CRYPTO         (aarch64_isa_flags & AARCH64_FL_CRYPTO)
 176 #define AARCH64_ISA_FP             (aarch64_isa_flags & AARCH64_FL_FP)
 177 #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
 178 #define AARCH64_ISA_LSE            (aarch64_isa_flags & AARCH64_FL_LSE)
 179 #define AARCH64_ISA_RDMA           (aarch64_isa_flags & AARCH64_FL_RDMA)
 180 #define AARCH64_ISA_V8_2           (aarch64_isa_flags & AARCH64_FL_V8_2)
 181 #define AARCH64_ISA_F16            (aarch64_isa_flags & AARCH64_FL_F16)
 182 #define AARCH64_ISA_V8_3           (aarch64_isa_flags & AARCH64_FL_V8_3)
 183
 184 /* Crypto is an optional extension to AdvSIMD.  */
 185 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
 186
 187 /* CRC instructions that can be enabled through +crc arch extension.  */
 188 #define TARGET_CRC32 (AARCH64_ISA_CRC)
 189
 190 /* Atomic instructions that can be enabled through the +lse extension.  */
 191 #define TARGET_LSE (AARCH64_ISA_LSE)
 192
 193 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension.  */
 194 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
 195 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
 196
 197 /* ARMv8.3-A features.  */
 198 #define TARGET_ARMV8_3  (AARCH64_ISA_V8_3)
 199
 200 /* Make sure this is always defined so we don't have to check for ifdefs
 201    but rather use normal ifs.  */
 202 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
 203 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0
 204 #else
 205 #undef TARGET_FIX_ERR_A53_835769_DEFAULT
 206 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1
 207 #endif
 208
 209 /* Apply the workaround for Cortex-A53 erratum 835769.  */
 210 #define TARGET_FIX_ERR_A53_835769       \
 211   ((aarch64_fix_a53_err835769 == 2)     \
 212   ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
 213
 214 /* Make sure this is always defined so we don't have to check for ifdefs
 215    but rather use normal ifs.  */
 216 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
 217 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0
 218 #else
 219 #undef TARGET_FIX_ERR_A53_843419_DEFAULT
 220 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1
 221 #endif
 222
 223 /* Apply the workaround for Cortex-A53 erratum 843419.  */
 224 #define TARGET_FIX_ERR_A53_843419       \
 225   ((aarch64_fix_a53_err843419 == 2)     \
 226   ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
 227
 228 /* ARMv8.1-A Adv.SIMD support.  */
 229 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
 230
 231 /* Standard register usage.  */
 232
 233 /* 31 64-bit general purpose registers R0-R30:
 234    R30          LR (link register)
 235    R29          FP (frame pointer)
 236    R19-R28      Callee-saved registers
 237    R18          The platform register; use as temporary register.
 238    R17          IP1 The second intra-procedure-call temporary register
 239                 (can be used by call veneers and PLT code); otherwise use
 240                 as a temporary register
 241    R16          IP0 The first intra-procedure-call temporary register (can
 242                 be used by call veneers and PLT code); otherwise use as a
 243                 temporary register
 244    R9-R15       Temporary registers
 245    R8           Structure value parameter / temporary register
 246    R0-R7        Parameter/result registers
 247
 248    SP           stack pointer, encoded as X/R31 where permitted.
 249    ZR           zero register, encoded as X/R31 elsewhere
 250
 251    32 x 128-bit floating-point/vector registers
 252    V16-V31      Caller-saved (temporary) registers
 253    V8-V15       Callee-saved registers
 254    V0-V7        Parameter/result registers
 255
 256    The vector register V0 holds scalar B0, H0, S0 and D0 in its least
 257    significant bits.  Unlike AArch32 S1 is not packed into D0,
 258    etc.  */
 259
 260 /* Note that we don't mark X30 as a call-clobbered register.  The idea is
 261    that it's really the call instructions themselves which clobber X30.
 262    We don't care what the called function does with it afterwards.
 263
 264    This approach makes it easier to implement sibcalls.  Unlike normal
 265    calls, sibcalls don't clobber X30, so the register reaches the
 266    called function intact.  EPILOGUE_USES says that X30 is useful
 267    to the called function.  */
 268
 269 #define FIXED_REGISTERS                                 \
 270   {                                                     \
 271     0, 0, 0, 0,   0, 0, 0, 0,   /* R0 - R7 */           \
 272     0, 0, 0, 0,   0, 0, 0, 0,   /* R8 - R15 */          \
 273     0, 0, 0, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 274     0, 0, 0, 0,   0, 1, 0, 1,   /* R24 - R30, SP */     \
 275     0, 0, 0, 0,   0, 0, 0, 0,   /* V0 - V7 */           \
 276     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 277     0, 0, 0, 0,   0, 0, 0, 0,   /* V16 - V23 */         \
 278     0, 0, 0, 0,   0, 0, 0, 0,   /* V24 - V31 */         \
 279     1, 1, 1,                    /* SFP, AP, CC */       \
 280   }
 281
 282 #define CALL_USED_REGISTERS                             \
 283   {                                                     \
 284     1, 1, 1, 1,   1, 1, 1, 1,   /* R0 - R7 */           \
 285     1, 1, 1, 1,   1, 1, 1, 1,   /* R8 - R15 */          \
 286     1, 1, 1, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 287     0, 0, 0, 0,   0, 1, 1, 1,   /* R24 - R30, SP */     \
 288     1, 1, 1, 1,   1, 1, 1, 1,   /* V0 - V7 */           \
 289     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 290     1, 1, 1, 1,   1, 1, 1, 1,   /* V16 - V23 */         \
 291     1, 1, 1, 1,   1, 1, 1, 1,   /* V24 - V31 */         \
 292     1, 1, 1,                    /* SFP, AP, CC */       \
 293   }
 294
 295 #define REGISTER_NAMES                                          \
 296   {                                                             \
 297     "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",      \
 298     "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",     \
 299     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",     \
 300     "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp",      \
 301     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",      \
 302     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",     \
 303     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",     \
 304     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",     \
 305     "sfp", "ap",  "cc",                                         \
 306   }
 307
 308 /* Generate the register aliases for core register N */
 309 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
 310                      {"w" # N, R0_REGNUM + (N)}
 311
 312 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
 313                      {"d" # N, V0_REGNUM + (N)}, \
 314                      {"s" # N, V0_REGNUM + (N)}, \
 315                      {"h" # N, V0_REGNUM + (N)}, \
 316                      {"b" # N, V0_REGNUM + (N)}
 317
 318 /* Provide aliases for all of the ISA defined register name forms.
 319    These aliases are convenient for use in the clobber lists of inline
 320    asm statements.  */
 321
 322 #define ADDITIONAL_REGISTER_NAMES \
 323   { R_ALIASES(0),  R_ALIASES(1),  R_ALIASES(2),  R_ALIASES(3),  \
 324     R_ALIASES(4),  R_ALIASES(5),  R_ALIASES(6),  R_ALIASES(7),  \
 325     R_ALIASES(8),  R_ALIASES(9),  R_ALIASES(10), R_ALIASES(11), \
 326     R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
 327     R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
 328     R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
 329     R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
 330     R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
 331     V_ALIASES(0),  V_ALIASES(1),  V_ALIASES(2),  V_ALIASES(3),  \
 332     V_ALIASES(4),  V_ALIASES(5),  V_ALIASES(6),  V_ALIASES(7),  \
 333     V_ALIASES(8),  V_ALIASES(9),  V_ALIASES(10), V_ALIASES(11), \
 334     V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
 335     V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
 336     V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
 337     V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
 338     V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31)  \
 339   }
 340
 341 /* Say that the epilogue uses the return address register.  Note that
 342    in the case of sibcalls, the values "used by the epilogue" are
 343    considered live at the start of the called function.  */
 344
 345 #define EPILOGUE_USES(REGNO) \
 346   (epilogue_completed && (REGNO) == LR_REGNUM)
 347
 348 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 349    the stack pointer does not matter.  The value is tested only in
 350    functions that have frame pointers.  */
 351 #define EXIT_IGNORE_STACK       1
 352
 353 #define STATIC_CHAIN_REGNUM             R18_REGNUM
 354 #define HARD_FRAME_POINTER_REGNUM       R29_REGNUM
 355 #define FRAME_POINTER_REGNUM            SFP_REGNUM
 356 #define STACK_POINTER_REGNUM            SP_REGNUM
 357 #define ARG_POINTER_REGNUM              AP_REGNUM
 358 #define FIRST_PSEUDO_REGISTER           67
 359
 360 /* The number of (integer) argument register available.  */
 361 #define NUM_ARG_REGS                    8
 362 #define NUM_FP_ARG_REGS                 8
 363
 364 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
 365    four members.  */
 366 #define HA_MAX_NUM_FLDS         4
 367
 368 /* External dwarf register number scheme.  These number are used to
 369    identify registers in dwarf debug information, the values are
 370    defined by the AArch64 ABI.  The numbering scheme is independent of
 371    GCC's internal register numbering scheme.  */
 372
 373 #define AARCH64_DWARF_R0        0
 374
 375 /* The number of R registers, note 31! not 32.  */
 376 #define AARCH64_DWARF_NUMBER_R 31
 377
 378 #define AARCH64_DWARF_SP       31
 379 #define AARCH64_DWARF_V0       64
 380
 381 /* The number of V registers.  */
 382 #define AARCH64_DWARF_NUMBER_V 32
 383
 384 /* For signal frames we need to use an alternative return column.  This
 385    value must not correspond to a hard register and must be out of the
 386    range of DWARF_FRAME_REGNUM().  */
 387 #define DWARF_ALT_FRAME_RETURN_COLUMN   \
 388   (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
 389
 390 /* We add 1 extra frame register for use as the
 391    DWARF_ALT_FRAME_RETURN_COLUMN.  */
 392 #define DWARF_FRAME_REGISTERS           (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
 393
 394
 395 #define DBX_REGISTER_NUMBER(REGNO)      aarch64_dbx_register_number (REGNO)
 396 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
 397    can use DWARF_ALT_FRAME_RETURN_COLUMN defined below.  This is just the same
 398    as the default definition in dwarf2out.c.  */
 399 #undef DWARF_FRAME_REGNUM
 400 #define DWARF_FRAME_REGNUM(REGNO)       DBX_REGISTER_NUMBER (REGNO)
 401
 402 #define DWARF_FRAME_RETURN_COLUMN       DWARF_FRAME_REGNUM (LR_REGNUM)
 403
 404 #define HARD_REGNO_NREGS(REGNO, MODE)   aarch64_hard_regno_nregs (REGNO, MODE)
 405
 406 #define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2)
 407
 408 #define DWARF2_UNWIND_INFO 1
 409
 410 /* Use R0 through R3 to pass exception handling information.  */
 411 #define EH_RETURN_DATA_REGNO(N) \
 412   ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
 413
 414 /* Select a format to encode pointers in exception handling data.  */
 415 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
 416   aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
 417
 418 /* Output the assembly strings we want to add to a function definition.  */
 419 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)      \
 420   aarch64_declare_function_name (STR, NAME, DECL)
 421
 422 /* For EH returns X4 contains the stack adjustment.  */
 423 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, R4_REGNUM)
 424 #define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
 425
 426 /* Don't use __builtin_setjmp until we've defined it.  */
 427 #undef DONT_USE_BUILTIN_SETJMP
 428 #define DONT_USE_BUILTIN_SETJMP 1
 429
 430 /* Register in which the structure value is to be returned.  */
 431 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
 432
 433 /* Non-zero if REGNO is part of the Core register set.
 434
 435    The rather unusual way of expressing this check is to avoid
 436    warnings when building the compiler when R0_REGNUM is 0 and REGNO
 437    is unsigned.  */
 438 #define GP_REGNUM_P(REGNO)                                              \
 439   (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
 440
 441 #define FP_REGNUM_P(REGNO)                      \
 442   (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
 443
 444 #define FP_LO_REGNUM_P(REGNO)            \
 445   (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
 446
 447 \f
 448 /* Register and constant classes.  */
 449
 450 enum reg_class
 451 {
 452   NO_REGS,
 453   CALLER_SAVE_REGS,
 454   GENERAL_REGS,
 455   STACK_REG,
 456   POINTER_REGS,
 457   FP_LO_REGS,
 458   FP_REGS,
 459   ALL_REGS,
 460   LIM_REG_CLASSES               /* Last */
 461 };
 462
 463 #define N_REG_CLASSES   ((int) LIM_REG_CLASSES)
 464
 465 #define REG_CLASS_NAMES                         \
 466 {                                               \
 467   "NO_REGS",                                    \
 468   "CALLER_SAVE_REGS",                           \
 469   "GENERAL_REGS",                               \
 470   "STACK_REG",                                  \
 471   "POINTER_REGS",                               \
 472   "FP_LO_REGS",                                 \
 473   "FP_REGS",                                    \
 474   "ALL_REGS"                                    \
 475 }
 476
 477 #define REG_CLASS_CONTENTS                                              \
 478 {                                                                       \
 479   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 480   { 0x0007ffff, 0x00000000, 0x00000000 },       /* CALLER_SAVE_REGS */  \
 481   { 0x7fffffff, 0x00000000, 0x00000003 },       /* GENERAL_REGS */      \
 482   { 0x80000000, 0x00000000, 0x00000000 },       /* STACK_REG */         \
 483   { 0xffffffff, 0x00000000, 0x00000003 },       /* POINTER_REGS */      \
 484   { 0x00000000, 0x0000ffff, 0x00000000 },       /* FP_LO_REGS  */       \
 485   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS  */          \
 486   { 0xffffffff, 0xffffffff, 0x00000007 }        /* ALL_REGS */          \
 487 }
 488
 489 #define REGNO_REG_CLASS(REGNO)  aarch64_regno_regclass (REGNO)
 490
 491 #define INDEX_REG_CLASS GENERAL_REGS
 492 #define BASE_REG_CLASS  POINTER_REGS
 493
 494 /* Register pairs used to eliminate unneeded registers that point into
 495    the stack frame.  */
 496 #define ELIMINABLE_REGS                                                 \
 497 {                                                                       \
 498   { ARG_POINTER_REGNUM,         STACK_POINTER_REGNUM            },      \
 499   { ARG_POINTER_REGNUM,         HARD_FRAME_POINTER_REGNUM       },      \
 500   { FRAME_POINTER_REGNUM,       STACK_POINTER_REGNUM            },      \
 501   { FRAME_POINTER_REGNUM,       HARD_FRAME_POINTER_REGNUM       },      \
 502 }
 503
 504 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 505   (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
 506
 507 /* CPU/ARCH option handling.  */
 508 #include "config/aarch64/aarch64-opts.h"
 509
 510 enum target_cpus
 511 {
 512 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
 513   TARGET_CPU_##INTERNAL_IDENT,
 514 #include "aarch64-cores.def"
 515   TARGET_CPU_generic
 516 };
 517
 518 /* If there is no CPU defined at configure, use generic as default.  */
 519 #ifndef TARGET_CPU_DEFAULT
 520 #define TARGET_CPU_DEFAULT \
 521   (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6))
 522 #endif
 523
 524 /* If inserting NOP before a mult-accumulate insn remember to adjust the
 525    length so that conditional branching code is updated appropriately.  */
 526 #define ADJUST_INSN_LENGTH(insn, length)        \
 527   do                                            \
 528     {                                           \
 529        if (aarch64_madd_needs_nop (insn))       \
 530          length += 4;                           \
 531     } while (0)
 532
 533 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)      \
 534     aarch64_final_prescan_insn (INSN);                  \
 535
 536 /* The processor for which instructions should be scheduled.  */
 537 extern enum aarch64_processor aarch64_tune;
 538
 539 /* RTL generation support.  */
 540 #define INIT_EXPANDERS aarch64_init_expanders ()
 541 \f
 542
 543 /* Stack layout; function entry, exit and calling.  */
 544 #define STACK_GROWS_DOWNWARD    1
 545
 546 #define FRAME_GROWS_DOWNWARD    1
 547
 548 #define STARTING_FRAME_OFFSET   0
 549
 550 #define ACCUMULATE_OUTGOING_ARGS        1
 551
 552 #define FIRST_PARM_OFFSET(FNDECL) 0
 553
 554 /* Fix for VFP */
 555 #define LIBCALL_VALUE(MODE)  \
 556   gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
 557
 558 #define DEFAULT_PCC_STRUCT_RETURN 0
 559
 560 #ifdef HOST_WIDE_INT
 561 struct GTY (()) aarch64_frame
 562 {
 563   HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
 564
 565   /* The number of extra stack bytes taken up by register varargs.
 566      This area is allocated by the callee at the very top of the
 567      frame.  This value is rounded up to a multiple of
 568      STACK_BOUNDARY.  */
 569   HOST_WIDE_INT saved_varargs_size;
 570
 571   /* The size of the saved callee-save int/FP registers.  */
 572
 573   HOST_WIDE_INT saved_regs_size;
 574
 575   /* Offset from the base of the frame (incomming SP) to the
 576      top of the locals area.  This value is always a multiple of
 577      STACK_BOUNDARY.  */
 578   HOST_WIDE_INT locals_offset;
 579
 580   /* Offset from the base of the frame (incomming SP) to the
 581      hard_frame_pointer.  This value is always a multiple of
 582      STACK_BOUNDARY.  */
 583   HOST_WIDE_INT hard_fp_offset;
 584
 585   /* The size of the frame.  This value is the offset from base of the
 586    * frame (incomming SP) to the stack_pointer.  This value is always
 587    * a multiple of STACK_BOUNDARY.  */
 588   HOST_WIDE_INT frame_size;
 589
 590   /* The size of the initial stack adjustment before saving callee-saves.  */
 591   HOST_WIDE_INT initial_adjust;
 592
 593   /* The writeback value when pushing callee-save registers.
 594      It is zero when no push is used.  */
 595   HOST_WIDE_INT callee_adjust;
 596
 597   /* The offset from SP to the callee-save registers after initial_adjust.
 598      It may be non-zero if no push is used (ie. callee_adjust == 0).  */
 599   HOST_WIDE_INT callee_offset;
 600
 601   /* The size of the stack adjustment after saving callee-saves.  */
 602   HOST_WIDE_INT final_adjust;
 603
 604   unsigned wb_candidate1;
 605   unsigned wb_candidate2;
 606
 607   bool laid_out;
 608 };
 609
 610 typedef struct GTY (()) machine_function
 611 {
 612   struct aarch64_frame frame;
 613   /* One entry for each hard register.  */
 614   bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
 615 } machine_function;
 616 #endif
 617
 618 /* Which ABI to use.  */
 619 enum aarch64_abi_type
 620 {
 621   AARCH64_ABI_LP64 = 0,
 622   AARCH64_ABI_ILP32 = 1
 623 };
 624
 625 #ifndef AARCH64_ABI_DEFAULT
 626 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
 627 #endif
 628
 629 #define TARGET_ILP32    (aarch64_abi & AARCH64_ABI_ILP32)
 630
 631 enum arm_pcs
 632 {
 633   ARM_PCS_AAPCS64,              /* Base standard AAPCS for 64 bit.  */
 634   ARM_PCS_UNKNOWN
 635 };
 636
 637
 638
 639
 640 /* We can't use machine_mode inside a generator file because it
 641    hasn't been created yet; we shouldn't be using any code that
 642    needs the real definition though, so this ought to be safe.  */
 643 #ifdef GENERATOR_FILE
 644 #define MACHMODE int
 645 #else
 646 #include "insn-modes.h"
 647 #define MACHMODE machine_mode
 648 #endif
 649
 650 #ifndef USED_FOR_TARGET
 651 /* AAPCS related state tracking.  */
 652 typedef struct
 653 {
 654   enum arm_pcs pcs_variant;
 655   int aapcs_arg_processed;      /* No need to lay out this argument again.  */
 656   int aapcs_ncrn;               /* Next Core register number.  */
 657   int aapcs_nextncrn;           /* Next next core register number.  */
 658   int aapcs_nvrn;               /* Next Vector register number.  */
 659   int aapcs_nextnvrn;           /* Next Next Vector register number.  */
 660   rtx aapcs_reg;                /* Register assigned to this argument.  This
 661                                    is NULL_RTX if this parameter goes on
 662                                    the stack.  */
 663   MACHMODE aapcs_vfp_rmode;
 664   int aapcs_stack_words;        /* If the argument is passed on the stack, this
 665                                    is the number of words needed, after rounding
 666                                    up.  Only meaningful when
 667                                    aapcs_reg == NULL_RTX.  */
 668   int aapcs_stack_size;         /* The total size (in words, per 8 byte) of the
 669                                    stack arg area so far.  */
 670 } CUMULATIVE_ARGS;
 671 #endif
 672
 673 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
 674   (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward)
 675
 676 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
 677   (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
 678
 679 #define PAD_VARARGS_DOWN        0
 680
 681 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 682   aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
 683
 684 #define FUNCTION_ARG_REGNO_P(REGNO) \
 685   aarch64_function_arg_regno_p(REGNO)
 686 \f
 687
 688 /* ISA Features.  */
 689
 690 /* Addressing modes, etc.  */
 691 #define HAVE_POST_INCREMENT     1
 692 #define HAVE_PRE_INCREMENT      1
 693 #define HAVE_POST_DECREMENT     1
 694 #define HAVE_PRE_DECREMENT      1
 695 #define HAVE_POST_MODIFY_DISP   1
 696 #define HAVE_PRE_MODIFY_DISP    1
 697
 698 #define MAX_REGS_PER_ADDRESS    2
 699
 700 #define CONSTANT_ADDRESS_P(X)           aarch64_constant_address_p(X)
 701
 702 #define REGNO_OK_FOR_BASE_P(REGNO)      \
 703   aarch64_regno_ok_for_base_p (REGNO, true)
 704
 705 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 706   aarch64_regno_ok_for_index_p (REGNO, true)
 707
 708 #define LEGITIMATE_PIC_OPERAND_P(X) \
 709   aarch64_legitimate_pic_operand_p (X)
 710
 711 #define CASE_VECTOR_MODE Pmode
 712
 713 #define DEFAULT_SIGNED_CHAR 0
 714
 715 /* An integer expression for the size in bits of the largest integer machine
 716    mode that should actually be used.  We allow pairs of registers.  */
 717 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
 718
 719 /* Maximum bytes moved by a single instruction (load/store pair).  */
 720 #define MOVE_MAX (UNITS_PER_WORD * 2)
 721
 722 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends.  */
 723 #define AARCH64_CALL_RATIO 8
 724
 725 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
 726    move_by_pieces will continually copy the largest safe chunks.  So a
 727    7-byte copy is a 4-byte + 2-byte + byte copy.  This proves inefficient
 728    for both size and speed of copy, so we will instead use the "movmem"
 729    standard name to implement the copy.  This logic does not apply when
 730    targeting -mstrict-align, so keep a sensible default in that case.  */
 731 #define MOVE_RATIO(speed) \
 732   (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
 733
 734 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 735    of the length of a memset call, but use the default otherwise.  */
 736 #define CLEAR_RATIO(speed) \
 737   ((speed) ? 15 : AARCH64_CALL_RATIO)
 738
 739 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when
 740    optimizing for size adjust the ratio to account for the overhead of loading
 741    the constant.  */
 742 #define SET_RATIO(speed) \
 743   ((speed) ? 15 : AARCH64_CALL_RATIO - 2)
 744
 745 /* Disable auto-increment in move_by_pieces et al.  Use of auto-increment is
 746    rarely a good idea in straight-line code since it adds an extra address
 747    dependency between each instruction.  Better to use incrementing offsets.  */
 748 #define USE_LOAD_POST_INCREMENT(MODE)   0
 749 #define USE_LOAD_POST_DECREMENT(MODE)   0
 750 #define USE_LOAD_PRE_INCREMENT(MODE)    0
 751 #define USE_LOAD_PRE_DECREMENT(MODE)    0
 752 #define USE_STORE_POST_INCREMENT(MODE)  0
 753 #define USE_STORE_POST_DECREMENT(MODE)  0
 754 #define USE_STORE_PRE_INCREMENT(MODE)   0
 755 #define USE_STORE_PRE_DECREMENT(MODE)   0
 756
 757 /* WORD_REGISTER_OPERATIONS does not hold for AArch64.
 758    The assigned word_mode is DImode but operations narrower than SImode
 759    behave as 32-bit operations if using the W-form of the registers rather
 760    than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
 761    expects.  */
 762 #define WORD_REGISTER_OPERATIONS 0
 763
 764 /* Define if loading from memory in MODE, an integral mode narrower than
 765    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
 766    macro should be the code that says which one of the two operations is
 767    implicitly done, or UNKNOWN if none.  */
 768 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 769
 770 /* Define this macro to be non-zero if instructions will fail to work
 771    if given data not on the nominal alignment.  */
 772 #define STRICT_ALIGNMENT                TARGET_STRICT_ALIGN
 773
 774 /* Define this macro to be non-zero if accessing less than a word of
 775    memory is no faster than accessing a word of memory, i.e., if such
 776    accesses require more than one instruction or if there is no
 777    difference in cost.
 778    Although there's no difference in instruction count or cycles,
 779    in AArch64 we don't want to expand to a sub-word to a 64-bit access
 780    if we don't have to, for power-saving reasons.  */
 781 #define SLOW_BYTE_ACCESS                0
 782
 783 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 784
 785 #define NO_FUNCTION_CSE 1
 786
 787 /* Specify the machine mode that the hardware addresses have.
 788    After generation of rtl, the compiler makes no further distinction
 789    between pointers and any other objects of this machine mode.  */
 790 #define Pmode           DImode
 791
 792 /* A C expression whose value is zero if pointers that need to be extended
 793    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
 794    greater then zero if they are zero-extended and less then zero if the
 795    ptr_extend instruction should be used.  */
 796 #define POINTERS_EXTEND_UNSIGNED 1
 797
 798 /* Mode of a function address in a call instruction (for indexing purposes).  */
 799 #define FUNCTION_MODE   Pmode
 800
 801 #define SELECT_CC_MODE(OP, X, Y)        aarch64_select_cc_mode (OP, X, Y)
 802
 803 #define REVERSIBLE_CC_MODE(MODE) 1
 804
 805 #define REVERSE_CONDITION(CODE, MODE)           \
 806   (((MODE) == CCFPmode || (MODE) == CCFPEmode)  \
 807    ? reverse_condition_maybe_unordered (CODE)   \
 808    : reverse_condition (CODE))
 809
 810 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 811   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 812 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
 813   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 814
 815 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
 816
 817 #define RETURN_ADDR_RTX aarch64_return_addr
 818
 819 /* 3 insns + padding + 2 pointer-sized entries.  */
 820 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32)
 821
 822 /* Trampolines contain dwords, so must be dword aligned.  */
 823 #define TRAMPOLINE_ALIGNMENT 64
 824
 825 /* Put trampolines in the text section so that mapping symbols work
 826    correctly.  */
 827 #define TRAMPOLINE_SECTION text_section
 828
 829 /* To start with.  */
 830 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
 831   (aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
 832 \f
 833
 834 /* Assembly output.  */
 835
 836 /* For now we'll make all jump tables pc-relative.  */
 837 #define CASE_VECTOR_PC_RELATIVE 1
 838
 839 #define CASE_VECTOR_SHORTEN_MODE(min, max, body)        \
 840   ((min < -0x1fff0 || max > 0x1fff0) ? SImode           \
 841    : (min < -0x1f0 || max > 0x1f0) ? HImode             \
 842    : QImode)
 843
 844 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL.  */
 845 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
 846
 847 #define MCOUNT_NAME "_mcount"
 848
 849 #define NO_PROFILE_COUNTERS 1
 850
 851 /* Emit rtl for profiling.  Output assembler code to FILE
 852    to call "_mcount" for profiling a function entry.  */
 853 #define PROFILE_HOOK(LABEL)                                             \
 854   {                                                                     \
 855     rtx fun, lr;                                                        \
 856     lr = get_hard_reg_initial_val (Pmode, LR_REGNUM);                   \
 857     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 858     emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode);           \
 859   }
 860
 861 /* All the work done in PROFILE_HOOK, but still required.  */
 862 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 863
 864 /* For some reason, the Linux headers think they know how to define
 865    these macros.  They don't!!!  */
 866 #undef ASM_APP_ON
 867 #undef ASM_APP_OFF
 868 #define ASM_APP_ON      "\t" ASM_COMMENT_START " Start of user assembly\n"
 869 #define ASM_APP_OFF     "\t" ASM_COMMENT_START " End of user assembly\n"
 870
 871 #define CONSTANT_POOL_BEFORE_FUNCTION 0
 872
 873 /* This definition should be relocated to aarch64-elf-raw.h.  This macro
 874    should be undefined in aarch64-linux.h and a clear_cache pattern
 875    implmented to emit either the call to __aarch64_sync_cache_range()
 876    directly or preferably the appropriate sycall or cache clear
 877    instructions inline.  */
 878 #define CLEAR_INSN_CACHE(beg, end)                              \
 879   extern void  __aarch64_sync_cache_range (void *, void *);     \
 880   __aarch64_sync_cache_range (beg, end)
 881
 882 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
 883
 884 /* Choose appropriate mode for caller saves, so we do the minimum
 885    required size of load/store.  */
 886 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
 887   aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
 888
 889 #undef SWITCHABLE_TARGET
 890 #define SWITCHABLE_TARGET 1
 891
 892 /* Check TLS Descriptors mechanism is selected.  */
 893 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
 894
 895 extern enum aarch64_code_model aarch64_cmodel;
 896
 897 /* When using the tiny addressing model conditional and unconditional branches
 898    can span the whole of the available address space (1MB).  */
 899 #define HAS_LONG_COND_BRANCH                            \
 900   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 901    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 902
 903 #define HAS_LONG_UNCOND_BRANCH                          \
 904   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
 905    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
 906
 907 #define TARGET_SUPPORTS_WIDE_INT 1
 908
 909 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register.  */
 910 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
 911   ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
 912    || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
 913    || (MODE) == DFmode)
 914
 915 /* Modes valid for AdvSIMD Q registers.  */
 916 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
 917   ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
 918    || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \
 919    || (MODE) == V2DFmode)
 920
 921 #define ENDIAN_LANE_N(mode, n)  \
 922   (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
 923
 924 /* Support for a configure-time default CPU, etc.  We currently support
 925    --with-arch and --with-cpu.  Both are ignored if either is specified
 926    explicitly on the command line at run time.  */
 927 #define OPTION_DEFAULT_SPECS                            \
 928   {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" },  \
 929   {"cpu",  "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" },
 930
 931 #define MCPU_TO_MARCH_SPEC \
 932    " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
 933
 934 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
 935 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
 936   { "rewrite_mcpu", aarch64_rewrite_mcpu },
 937
 938 #if defined(__aarch64__)
 939 extern const char *host_detect_local_cpu (int argc, const char **argv);
 940 # define EXTRA_SPEC_FUNCTIONS                                           \
 941   { "local_cpu_detect", host_detect_local_cpu },                        \
 942   MCPU_TO_MARCH_SPEC_FUNCTIONS
 943
 944 # define MCPU_MTUNE_NATIVE_SPECS                                        \
 945    " %{march=native:%<march=native %:local_cpu_detect(arch)}"           \
 946    " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}"              \
 947    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
 948 #else
 949 # define MCPU_MTUNE_NATIVE_SPECS ""
 950 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS
 951 #endif
 952
 953 #define ASM_CPU_SPEC \
 954    MCPU_TO_MARCH_SPEC
 955
 956 #define EXTRA_SPECS                                             \
 957   { "asm_cpu_spec",             ASM_CPU_SPEC }
 958
 959 #define ASM_OUTPUT_POOL_EPILOGUE  aarch64_asm_output_pool_epilogue
 960
 961 /* This type is the user-visible __fp16, and a pointer to that type.  We
 962    need it in many places in the backend.  Defined in aarch64-builtins.c.  */
 963 extern tree aarch64_fp16_type_node;
 964 extern tree aarch64_fp16_ptr_type_node;
 965
 966 #endif /* GCC_AARCH64_H */