gcc/config/aarch64/constraints.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2014 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_register_constraint "k" "STACK_REG"
  22   "@internal The stack register.")
  23
  24 (define_register_constraint "w" "FP_REGS"
  25   "Floating point and SIMD vector registers.")
  26
  27 (define_register_constraint "x" "FP_LO_REGS"
  28   "Floating point and SIMD vector registers V0 - V15.")
  29
  30 (define_constraint "I"
  31  "A constant that can be used with an ADD operation."
  32  (and (match_code "const_int")
  33       (match_test "aarch64_uimm12_shift (ival)")))
  34
  35 (define_constraint "J"
  36  "A constant that can be used with a SUB operation (once negated)."
  37  (and (match_code "const_int")
  38       (match_test "aarch64_uimm12_shift (-ival)")))
  39
  40 ;; We can't use the mode of a CONST_INT to determine the context in
  41 ;; which it is being used, so we must have a separate constraint for
  42 ;; each context.
  43
  44 (define_constraint "K"
  45  "A constant that can be used with a 32-bit logical operation."
  46  (and (match_code "const_int")
  47       (match_test "aarch64_bitmask_imm (ival, SImode)")))
  48
  49 (define_constraint "L"
  50  "A constant that can be used with a 64-bit logical operation."
  51  (and (match_code "const_int")
  52       (match_test "aarch64_bitmask_imm (ival, DImode)")))
  53
  54 (define_constraint "M"
  55  "A constant that can be used with a 32-bit MOV immediate operation."
  56  (and (match_code "const_int")
  57       (match_test "aarch64_move_imm (ival, SImode)")))
  58
  59 (define_constraint "N"
  60  "A constant that can be used with a 64-bit MOV immediate operation."
  61  (and (match_code "const_int")
  62       (match_test "aarch64_move_imm (ival, DImode)")))
  63
  64 (define_constraint "S"
  65   "A constraint that matches an absolute symbolic address."
  66   (and (match_code "const,symbol_ref,label_ref")
  67        (match_test "aarch64_symbolic_address_p (op)")))
  68
  69 (define_constraint "Y"
  70   "Floating point constant zero."
  71   (and (match_code "const_double")
  72        (match_test "aarch64_float_const_zero_rtx_p (op)")))
  73
  74 (define_constraint "Z"
  75   "Integer constant zero."
  76   (match_test "op == const0_rtx"))
  77
  78 (define_constraint "Ush"
  79   "A constraint that matches an absolute symbolic address high part."
  80   (and (match_code "high")
  81        (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
  82
  83 (define_constraint "Uss"
  84   "@internal
  85   A constraint that matches an immediate shift constant in SImode."
  86   (and (match_code "const_int")
  87        (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
  88
  89 (define_constraint "Usd"
  90   "@internal
  91   A constraint that matches an immediate shift constant in DImode."
  92   (and (match_code "const_int")
  93        (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
  94
  95 (define_constraint "UsM"
  96   "@internal
  97   A constraint that matches the immediate constant -1."
  98   (match_test "op == constm1_rtx"))
  99
 100 (define_constraint "Ui1"
 101   "@internal
 102   A constraint that matches the immediate constant +1."
 103   (match_test "op == const1_rtx"))
 104
 105 (define_constraint "Ui3"
 106   "@internal
 107   A constraint that matches the integers 0...4."
 108   (and (match_code "const_int")
 109        (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
 110
 111 (define_constraint "Up3"
 112   "@internal
 113   A constraint that matches the integers 2^(0...4)."
 114   (and (match_code "const_int")
 115        (match_test "(unsigned) exact_log2 (ival) <= 4")))
 116
 117 (define_memory_constraint "Q"
 118  "A memory address which uses a single base register with no offset."
 119  (and (match_code "mem")
 120       (match_test "REG_P (XEXP (op, 0))")))
 121
 122 (define_memory_constraint "Ump"
 123   "@internal
 124   A memory address suitable for a load/store pair operation."
 125   (and (match_code "mem")
 126        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 127                                                   PARALLEL, 1)")))
 128
 129 (define_memory_constraint "Utv"
 130   "@internal
 131    An address valid for loading/storing opaque structure
 132    types wider than TImode."
 133   (and (match_code "mem")
 134        (match_test "aarch64_simd_mem_operand_p (op)")))
 135
 136 (define_constraint "Ufc"
 137   "A floating point constant which can be used with an\
 138    FMOV immediate operation."
 139   (and (match_code "const_double")
 140        (match_test "aarch64_float_const_representable_p (op)")))
 141
 142 (define_constraint "Dn"
 143   "@internal
 144  A constraint that matches vector of immediates."
 145  (and (match_code "const_vector")
 146       (match_test "aarch64_simd_valid_immediate (op, GET_MODE (op),
 147                                                  false, NULL)")))
 148
 149 (define_constraint "Dh"
 150   "@internal
 151  A constraint that matches an immediate operand valid for\
 152  AdvSIMD scalar move in HImode."
 153  (and (match_code "const_int")
 154       (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
 155                                                  HImode)")))
 156
 157 (define_constraint "Dq"
 158   "@internal
 159  A constraint that matches an immediate operand valid for\
 160  AdvSIMD scalar move in QImode."
 161  (and (match_code "const_int")
 162       (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
 163                                                  QImode)")))
 164
 165 (define_constraint "Dl"
 166   "@internal
 167  A constraint that matches vector of immediates for left shifts."
 168  (and (match_code "const_vector")
 169       (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
 170                                                  true)")))
 171
 172 (define_constraint "Dr"
 173   "@internal
 174  A constraint that matches vector of immediates for right shifts."
 175  (and (match_code "const_vector")
 176       (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
 177                                                  false)")))
 178 (define_constraint "Dz"
 179   "@internal
 180  A constraint that matches vector of immediate zero."
 181  (and (match_code "const_vector")
 182       (match_test "aarch64_simd_imm_zero_p (op, GET_MODE (op))")))
 183
 184 (define_constraint "Dd"
 185   "@internal
 186  A constraint that matches an immediate operand valid for AdvSIMD scalar."
 187  (and (match_code "const_int")
 188       (match_test "aarch64_simd_imm_scalar_p (op, GET_MODE (op))")))