gcc/config/aarch64/constraints.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2024 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_register_constraint "k" "STACK_REG"
  22   "@internal The stack register.")
  23
  24 (define_register_constraint "Uci" "W8_W11_REGS"
  25   "@internal r8-r11, which can be used to index ZA.")
  26
  27 (define_register_constraint "Ucj" "W12_W15_REGS"
  28   "@internal r12-r15, which can be used to index ZA.")
  29
  30 (define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
  31   "@internal Registers suitable for an indirect tail call")
  32
  33 (define_register_constraint "Ucr"
  34     "aarch64_harden_sls_blr_p () ? STUB_REGS : GENERAL_REGS"
  35   "@internal Registers to be used for an indirect call.
  36    This is usually the general registers, but when we are hardening against
  37    Straight Line Speculation we disallow x16, x17, and x30 so we can use
  38    indirection stubs.  These indirection stubs cannot use the above registers
  39    since they will be reached by a BL that may have to go through a linker
  40    veneer.")
  41
  42 (define_register_constraint "w" "FP_REGS"
  43   "Floating point and SIMD vector registers.")
  44
  45 (define_register_constraint "x" "FP_LO_REGS"
  46   "Floating point and SIMD vector registers V0 - V15.")
  47
  48 (define_register_constraint "y" "FP_LO8_REGS"
  49   "Floating point and SIMD vector registers V0 - V7.")
  50
  51 (define_register_constraint "Uw2" "FP_REGS"
  52   "Even floating point and SIMD vector registers."
  53   "regno % 2 == 0")
  54
  55 (define_register_constraint "Uw4" "FP_REGS"
  56   "4-tuple-aligned floating point and SIMD vector registers."
  57   "regno % 4 == 0")
  58
  59 (define_register_constraint "Uwd" "FP_REGS"
  60   "@internal The first register in a tuple of 2 strided FPRs."
  61   "(regno & 0x8) == 0")
  62
  63 (define_register_constraint "Uwt" "FP_REGS"
  64   "@internal The first register in a tuple of 4 strided FPRs."
  65   "(regno & 0xc) == 0")
  66
  67 (define_register_constraint "Upa" "PR_REGS"
  68   "SVE predicate registers p0 - p15.")
  69
  70 (define_register_constraint "Up2" "PR_REGS"
  71   "An even SVE predicate register, p0 - p14."
  72   "regno % 2 == 0")
  73
  74 (define_register_constraint "Upl" "PR_LO_REGS"
  75   "SVE predicate registers p0 - p7.")
  76
  77 (define_register_constraint "Uph" "PR_HI_REGS"
  78   "SVE predicate registers p8 - p15.")
  79
  80 (define_constraint "c"
  81  "@internal The condition code register."
  82   (match_operand 0 "cc_register"))
  83
  84 (define_constraint "I"
  85  "A constant that can be used with an ADD operation."
  86  (and (match_code "const_int")
  87       (match_test "aarch64_uimm12_shift (ival)")))
  88
  89 (define_constraint "Uaa"
  90   "@internal A constant that matches two uses of add instructions."
  91   (and (match_code "const_int")
  92        (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
  93
  94 (define_constraint "Uai"
  95   "@internal
  96    A constraint that matches a VG-based constant that can be added by
  97    a single INC or DEC."
  98   (match_operand 0 "aarch64_sve_scalar_inc_dec_immediate"))
  99
 100 (define_constraint "Uav"
 101   "@internal
 102    A constraint that matches a VG-based constant that can be added by
 103    a single ADDVL or ADDPL."
 104  (match_operand 0 "aarch64_sve_addvl_addpl_immediate"))
 105
 106 (define_constraint "UaV"
 107   "@internal
 108    A constraint that matches a VG-based constant that can be added by
 109    a single ADDSVL or ADDSPL."
 110  (match_operand 0 "aarch64_addsvl_addspl_immediate"))
 111
 112 (define_constraint "Uat"
 113   "@internal
 114    A constraint that matches a VG-based constant that can be added by
 115    using multiple instructions, with one temporary register."
 116  (match_operand 0 "aarch64_split_add_offset_immediate"))
 117
 118 (define_constraint "J"
 119  "A constant that can be used with a SUB operation (once negated)."
 120  (and (match_code "const_int")
 121       (match_test "aarch64_uimm12_shift (-ival)")))
 122
 123 ;; We can't use the mode of a CONST_INT to determine the context in
 124 ;; which it is being used, so we must have a separate constraint for
 125 ;; each context.
 126
 127 (define_constraint "K"
 128  "A constant that can be used with a 32-bit logical operation."
 129  (and (match_code "const_int")
 130       (match_test "aarch64_bitmask_imm (ival, SImode)")))
 131
 132 (define_constraint "L"
 133  "A constant that can be used with a 64-bit logical operation."
 134  (and (match_code "const_int")
 135       (match_test "aarch64_bitmask_imm (ival, DImode)")))
 136
 137 (define_constraint "M"
 138  "A constant that can be used with a 32-bit MOV immediate operation."
 139  (and (match_code "const_int")
 140       (match_test "aarch64_move_imm (ival, SImode)")))
 141
 142 (define_constraint "N"
 143  "A constant that can be used with a 64-bit MOV immediate operation."
 144  (and (match_code "const_int")
 145       (match_test "aarch64_is_mov_xn_imm (ival)")))
 146
 147 (define_constraint "O"
 148  "A constant that can be used with a 32 or 64-bit MOV immediate operation."
 149  (and (match_code "const_int")
 150       (match_test "aarch64_move_imm (ival, DImode)")))
 151
 152 (define_constraint "Uti"
 153  "A constant that can be used with a 128-bit MOV immediate operation."
 154  (and (ior (match_code "const_int")
 155            (match_code "const_wide_int"))
 156       (match_test "aarch64_mov128_immediate (op)")))
 157
 158 (define_constraint "UsO"
 159  "A constant that can be used with a 32-bit and operation."
 160  (and (match_code "const_int")
 161       (match_test "aarch64_and_bitmask_imm (ival, SImode)")))
 162
 163 (define_constraint "UsP"
 164  "A constant that can be used with a 64-bit and operation."
 165  (and (match_code "const_int")
 166       (match_test "aarch64_and_bitmask_imm (ival, DImode)")))
 167
 168 (define_constraint "S"
 169   "A constraint that matches an absolute symbolic address."
 170   (and (match_code "const,symbol_ref,label_ref")
 171        (match_test "aarch64_symbolic_address_p (op)")))
 172
 173 (define_constraint "Y"
 174   "Floating point constant zero."
 175   (and (match_code "const_double")
 176        (match_test "aarch64_float_const_zero_rtx_p (op)")))
 177
 178 (define_constraint "Z"
 179   "Integer or floating-point constant zero."
 180   (match_test "op == CONST0_RTX (GET_MODE (op))"))
 181
 182 (define_constraint "Ush"
 183   "A constraint that matches an absolute symbolic address high part."
 184   (and (match_code "high")
 185        (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
 186
 187 (define_constraint "Usa"
 188   "@internal
 189    A constraint that matches an absolute symbolic address that can be
 190    loaded by a single ADR."
 191   (and (match_code "const,symbol_ref,label_ref")
 192        (match_test "aarch64_symbolic_address_p (op)")
 193        (match_test "aarch64_mov_operand_p (op, GET_MODE (op))")))
 194
 195 (define_constraint "Usm"
 196  "A constant that can be used with the S[MIN/MAX] CSSC instructions."
 197  (and (match_code "const_int")
 198       (match_test "aarch64_sminmax_immediate (op, VOIDmode)")))
 199
 200 ;; const is needed here to support UNSPEC_SALT_ADDR.
 201 (define_constraint "Usw"
 202   "@internal
 203    A constraint that matches a small GOT access."
 204   (and (match_code "const,symbol_ref")
 205        (match_test "aarch64_classify_symbolic_expression (op)
 206                      == SYMBOL_SMALL_GOT_4G")))
 207
 208 (define_constraint "Uss"
 209   "@internal
 210   A constraint that matches an immediate shift constant in SImode."
 211   (and (match_code "const_int")
 212        (match_test "(unsigned HOST_WIDE_INT) ival < 32")))
 213
 214 (define_constraint "Usn"
 215  "A constant that can be used with a CCMN operation (once negated)."
 216  (and (match_code "const_int")
 217       (match_test "IN_RANGE (ival, -31, 0)")))
 218
 219 (define_constraint "Usd"
 220   "@internal
 221   A constraint that matches an immediate shift constant in DImode."
 222   (and (match_code "const_int")
 223        (match_test "(unsigned HOST_WIDE_INT) ival < 64")))
 224
 225 (define_constraint "Usf"
 226   "@internal Usf is a symbol reference under the context where plt stub allowed."
 227   (and (match_code "symbol_ref")
 228        (match_test "!(aarch64_is_noplt_call_p (op)
 229                       || aarch64_is_long_call_p (op))")))
 230
 231 (define_constraint "Usg"
 232   "@internal
 233   A constraint that matches an immediate right shift constant in SImode
 234   suitable for a SISD instruction."
 235   (and (match_code "const_int")
 236        (match_test "IN_RANGE (ival, 1, 31)")))
 237
 238 (define_constraint "Usj"
 239   "@internal
 240   A constraint that matches an immediate right shift constant in DImode
 241   suitable for a SISD instruction."
 242   (and (match_code "const_int")
 243        (match_test "IN_RANGE (ival, 1, 63)")))
 244
 245 (define_constraint "UsM"
 246   "@internal
 247   A constraint that matches the immediate constant -1."
 248   (match_test "op == constm1_rtx"))
 249
 250 (define_constraint "Ulc"
 251  "@internal
 252  A constraint that matches a constant integer whose bits are consecutive ones
 253  from the MSB."
 254  (and (match_code "const_int")
 255       (match_test "aarch64_high_bits_all_ones_p (ival)")))
 256
 257 (define_constraint "Usr"
 258   "@internal
 259    A constraint that matches a value produced by RDVL."
 260  (and (match_code "const_poly_int")
 261       (match_test "aarch64_sve_rdvl_immediate_p (op)")))
 262
 263 (define_constraint "UsR"
 264   "@internal
 265    A constraint that matches a value produced by RDSVL."
 266  (and (match_code "const")
 267       (match_test "aarch64_rdsvl_immediate_p (op)")))
 268
 269 (define_constraint "Usv"
 270   "@internal
 271    A constraint that matches a VG-based constant that can be loaded by
 272    a single CNT[BHWD]."
 273  (match_operand 0 "aarch64_sve_cnt_immediate"))
 274
 275 (define_constraint "Usi"
 276   "@internal
 277  A constraint that matches an immediate operand valid for
 278  the SVE INDEX instruction."
 279  (match_operand 0 "aarch64_sve_index_immediate"))
 280
 281 (define_constraint "Ui1"
 282   "@internal
 283   A constraint that matches the immediate constant +1."
 284   (match_test "op == const1_rtx"))
 285
 286 (define_constraint "Ui2"
 287   "@internal
 288   A constraint that matches the integers 0...3."
 289   (and (match_code "const_int")
 290        (match_test "(unsigned HOST_WIDE_INT) ival <= 3")))
 291
 292 (define_constraint "Ui3"
 293   "@internal
 294   A constraint that matches the integers 0...4."
 295   (and (match_code "const_int")
 296        (match_test "(unsigned HOST_WIDE_INT) ival <= 4")))
 297
 298 (define_constraint "Ui7"
 299   "@internal
 300   A constraint that matches the integers 0...7."
 301   (and (match_code "const_int")
 302        (match_test "(unsigned HOST_WIDE_INT) ival <= 7")))
 303
 304 (define_constraint "Up3"
 305   "@internal
 306   A constraint that matches the integers 2^(0...4)."
 307   (and (match_code "const_int")
 308        (match_test "(unsigned) exact_log2 (ival) <= 4")))
 309
 310 (define_constraint "Uih"
 311   "@internal
 312   A constraint that matches HImode integers zero extendable to
 313   SImode plus_operand."
 314   (and (match_code "const_int")
 315        (match_test "aarch64_plushi_immediate (op, VOIDmode)")))
 316
 317 (define_memory_constraint "Q"
 318  "A memory address which uses a single base register with no offset."
 319  (and (match_code "mem")
 320       (match_test "REG_P (XEXP (op, 0))")))
 321
 322 (define_memory_constraint "Ust"
 323   "@internal
 324   A memory address with 9bit unscaled offset."
 325   (match_operand 0 "aarch64_9bit_offset_memory_operand"))
 326
 327 (define_memory_constraint "Ump"
 328   "@internal
 329   A memory address suitable for a load/store pair operation."
 330   (and (match_code "mem")
 331        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 332                                                   true, ADDR_QUERY_LDP_STP)")))
 333
 334 ;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP
 335 ;; as a vector-concat.  The address mode uses the same constraints as if it
 336 ;; were for a single value.
 337 (define_relaxed_memory_constraint "Umn"
 338   "@internal
 339   A memory address suitable for a load/store pair operation."
 340   (and (match_code "mem")
 341        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 342                                                   true,
 343                                                   ADDR_QUERY_LDP_STP_N)")))
 344
 345 (define_address_constraint "UPb"
 346   "@internal
 347    An address valid for SVE PRFB instructions."
 348   (match_test "aarch64_sve_prefetch_operand_p (op, VNx16QImode)"))
 349
 350 (define_address_constraint "UPd"
 351   "@internal
 352    An address valid for SVE PRFD instructions."
 353   (match_test "aarch64_sve_prefetch_operand_p (op, VNx2DImode)"))
 354
 355 (define_address_constraint "UPh"
 356   "@internal
 357    An address valid for SVE PRFH instructions."
 358   (match_test "aarch64_sve_prefetch_operand_p (op, VNx8HImode)"))
 359
 360 (define_address_constraint "UPw"
 361   "@internal
 362    An address valid for SVE PRFW instructions."
 363   (match_test "aarch64_sve_prefetch_operand_p (op, VNx4SImode)"))
 364
 365 (define_memory_constraint "Utf"
 366   "@internal
 367    An address valid for SVE LDFF1 instructions."
 368   (and (match_code "mem")
 369        (match_test "aarch64_sve_ldff1_operand_p (op)")))
 370
 371 (define_memory_constraint "Utn"
 372   "@internal
 373    An address valid for SVE LDNF1 instructions."
 374   (and (match_code "mem")
 375        (match_test "aarch64_sve_ldnf1_operand_p (op)")))
 376
 377 (define_memory_constraint "Utr"
 378   "@internal
 379    An address valid for SVE LDR and STR instructions (as distinct from
 380    LD[1234] and ST[1234] patterns)."
 381   (and (match_code "mem")
 382        (match_test "aarch64_sve_ldr_operand_p (op)")))
 383
 384 (define_memory_constraint "Utv"
 385   "@internal
 386    An address valid for loading/storing opaque structure
 387    types wider than TImode."
 388   (and (match_code "mem")
 389        (match_test "aarch64_simd_mem_operand_p (op)")))
 390
 391 (define_relaxed_memory_constraint "Utq"
 392   "@internal
 393    An address valid for loading or storing a 128-bit AdvSIMD register"
 394   (and (match_code "mem")
 395        (match_test "aarch64_legitimate_address_p (GET_MODE (op),
 396                                                   XEXP (op, 0), 1)")
 397        (match_test "aarch64_legitimate_address_p (V2DImode,
 398                                                   XEXP (op, 0), 1)")))
 399
 400 (define_relaxed_memory_constraint "UtQ"
 401   "@internal
 402    An address valid for SVE LD1RQs."
 403   (and (match_code "mem")
 404        (match_test "aarch64_sve_ld1rq_operand_p (op)")))
 405
 406 (define_relaxed_memory_constraint "UOb"
 407   "@internal
 408    An address valid for SVE LD1ROH."
 409   (and (match_code "mem")
 410        (match_test "aarch64_sve_ld1ro_operand_p (op, QImode)")))
 411
 412 (define_relaxed_memory_constraint "UOh"
 413   "@internal
 414    An address valid for SVE LD1ROH."
 415   (and (match_code "mem")
 416        (match_test "aarch64_sve_ld1ro_operand_p (op, HImode)")))
 417
 418
 419 (define_relaxed_memory_constraint "UOw"
 420   "@internal
 421    An address valid for SVE LD1ROW."
 422   (and (match_code "mem")
 423        (match_test "aarch64_sve_ld1ro_operand_p (op, SImode)")))
 424
 425 (define_relaxed_memory_constraint "UOd"
 426   "@internal
 427    An address valid for SVE LD1ROD."
 428   (and (match_code "mem")
 429        (match_test "aarch64_sve_ld1ro_operand_p (op, DImode)")))
 430
 431 (define_relaxed_memory_constraint "Uty"
 432   "@internal
 433    An address valid for SVE LD1Rs."
 434   (and (match_code "mem")
 435        (match_test "aarch64_sve_ld1r_operand_p (op)")))
 436
 437 (define_memory_constraint "Utx"
 438   "@internal
 439    An address valid for SVE structure mov patterns (as distinct from
 440    LD[234] and ST[234] patterns)."
 441   (match_operand 0 "aarch64_sve_struct_memory_operand"))
 442
 443 (define_constraint "Ufc"
 444   "A floating point constant which can be used with an\
 445    FMOV immediate operation."
 446   (and (match_code "const_double,const_vector")
 447        (match_test "aarch64_float_const_representable_p (op)")))
 448
 449 (define_constraint "Uum"
 450  "A constant that can be used with the U[MIN/MAX] CSSC instructions."
 451  (and (match_code "const_int")
 452       (match_test "aarch64_uminmax_immediate (op, VOIDmode)")))
 453
 454 (define_constraint "Uvi"
 455   "A floating point constant which can be used with a\
 456    MOVI immediate operation."
 457   (and (match_code "const_double")
 458        (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
 459
 460 (define_constraint "Do"
 461   "@internal
 462    A constraint that matches vector of immediates for orr."
 463  (and (match_code "const_vector")
 464       (match_test "aarch64_simd_valid_immediate (op, NULL,
 465                                                  AARCH64_CHECK_ORR)")))
 466
 467 (define_constraint "Db"
 468   "@internal
 469    A constraint that matches vector of immediates for bic."
 470  (and (match_code "const_vector")
 471       (match_test "aarch64_simd_valid_immediate (op, NULL,
 472                                                  AARCH64_CHECK_BIC)")))
 473
 474 (define_constraint "Dn"
 475   "@internal
 476  A constraint that matches vector of immediates."
 477  (and (match_code "const,const_vector")
 478       (match_test "aarch64_simd_valid_immediate (op, NULL)")))
 479
 480 (define_constraint "Dh"
 481   "@internal
 482  A constraint that matches an immediate operand valid for\
 483  AdvSIMD scalar move in HImode."
 484  (and (match_code "const_int")
 485       (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
 486                                                  HImode)")))
 487
 488 (define_constraint "Dq"
 489   "@internal
 490  A constraint that matches an immediate operand valid for\
 491  AdvSIMD scalar move in QImode."
 492  (and (match_code "const_int")
 493       (match_test "aarch64_simd_scalar_immediate_valid_for_move (op,
 494                                                  QImode)")))
 495
 496 (define_constraint "Dt"
 497   "@internal
 498  A const_double which is the reciprocal of an exact power of two, can be
 499  used in an scvtf with fract bits operation"
 500  (and (match_code "const_double")
 501       (match_test "aarch64_fpconst_pow2_recip (op) > 0")))
 502
 503 (define_constraint "Dl"
 504   "@internal
 505  A constraint that matches vector of immediates for left shifts."
 506  (and (match_code "const,const_vector")
 507       (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
 508                                                  true)")))
 509
 510 (define_constraint "D1"
 511   "@internal
 512  A constraint that matches vector of immediates that is bits(mode)-1."
 513  (and (match_code "const,const_vector")
 514       (match_test "aarch64_const_vec_all_same_in_range_p (op,
 515                         GET_MODE_UNIT_BITSIZE (mode) - 1,
 516                         GET_MODE_UNIT_BITSIZE (mode) - 1)")))
 517
 518 (define_constraint "D2"
 519   "@internal
 520  A constraint that matches vector of immediates that is bits(mode)/2."
 521  (and (match_code "const,const_vector")
 522       (match_test "aarch64_simd_shift_imm_vec_exact_top (op, mode)")))
 523
 524 (define_constraint "DL"
 525   "@internal
 526  A constraint that matches vector of immediates for left shift long.
 527  That is immediates between 0 to (bits(mode)/2)-1."
 528  (and (match_code "const,const_vector")
 529       (match_test "aarch64_const_vec_all_same_in_range_p (op, 0,
 530                         (GET_MODE_UNIT_BITSIZE (mode) / 2) - 1)")))
 531
 532 (define_constraint "Dr"
 533   "@internal
 534  A constraint that matches vector of immediates for right shifts."
 535  (and (match_code "const,const_vector")
 536       (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op),
 537                                                  false)")))
 538
 539 (define_constraint "Dx"
 540   "@internal
 541  A constraint that matches a vector of 64-bit immediates which we don't have a
 542  single instruction to create but that we can create in creative ways."
 543  (and (match_code "const_int,const,const_vector")
 544       (match_test "aarch64_simd_special_constant_p (op, DImode)")))
 545
 546 (define_constraint "Dz"
 547   "@internal
 548  A constraint that matches a vector of immediate zero."
 549  (and (match_code "const,const_vector")
 550       (match_test "op == CONST0_RTX (GET_MODE (op))")))
 551
 552 (define_constraint "Dm"
 553   "@internal
 554  A constraint that matches a vector of immediate minus one."
 555  (and (match_code "const,const_vector")
 556       (match_test "op == CONST1_RTX (GET_MODE (op))")))
 557
 558 (define_constraint "Dd"
 559   "@internal
 560  A constraint that matches an integer immediate operand valid\
 561  for AdvSIMD scalar operations in DImode."
 562  (and (match_code "const_int")
 563       (match_test "aarch64_can_const_movi_rtx_p (op, DImode)")))
 564
 565 (define_constraint "Ds"
 566   "@internal
 567  A constraint that matches an integer immediate operand valid\
 568  for AdvSIMD scalar operations in SImode."
 569  (and (match_code "const_int")
 570       (match_test "aarch64_can_const_movi_rtx_p (op, SImode)")))
 571
 572 (define_address_constraint "Dp"
 573   "@internal
 574  An address valid for a prefetch instruction."
 575  (match_test "aarch64_address_valid_for_prefetch_p (op, true)"))
 576
 577 (define_constraint "vgb"
 578   "@internal
 579    A constraint that matches an immediate offset valid for SVE LD1B
 580    gather instructions."
 581  (match_operand 0 "aarch64_sve_gather_immediate_b"))
 582
 583 (define_constraint "vgd"
 584   "@internal
 585    A constraint that matches an immediate offset valid for SVE LD1D
 586    gather instructions."
 587  (match_operand 0 "aarch64_sve_gather_immediate_d"))
 588
 589 (define_constraint "vgh"
 590   "@internal
 591    A constraint that matches an immediate offset valid for SVE LD1H
 592    gather instructions."
 593  (match_operand 0 "aarch64_sve_gather_immediate_h"))
 594
 595 (define_constraint "vgw"
 596   "@internal
 597    A constraint that matches an immediate offset valid for SVE LD1W
 598    gather instructions."
 599  (match_operand 0 "aarch64_sve_gather_immediate_w"))
 600
 601 (define_constraint "vsa"
 602   "@internal
 603    A constraint that matches an immediate operand valid for SVE
 604    arithmetic instructions."
 605  (match_operand 0 "aarch64_sve_arith_immediate"))
 606
 607 (define_constraint "vsb"
 608   "@internal
 609    A constraint that matches an immediate operand valid for SVE UMAX
 610    and UMIN operations."
 611  (match_operand 0 "aarch64_sve_vsb_immediate"))
 612
 613 (define_constraint "vsc"
 614   "@internal
 615    A constraint that matches a signed immediate operand valid for SVE
 616    CMP instructions."
 617  (match_operand 0 "aarch64_sve_cmp_vsc_immediate"))
 618
 619 (define_constraint "vss"
 620   "@internal
 621    A constraint that matches a signed immediate operand valid for SVE
 622    DUP instructions."
 623  (match_test "aarch64_sve_dup_immediate_p (op)"))
 624
 625 (define_constraint "vsd"
 626   "@internal
 627    A constraint that matches an unsigned immediate operand valid for SVE
 628    CMP instructions."
 629  (match_operand 0 "aarch64_sve_cmp_vsd_immediate"))
 630
 631 (define_constraint "vsi"
 632   "@internal
 633    A constraint that matches a vector count operand valid for SVE INC and
 634    DEC instructions."
 635  (match_operand 0 "aarch64_sve_vector_inc_dec_immediate"))
 636
 637 (define_constraint "vsn"
 638   "@internal
 639    A constraint that matches an immediate operand whose negative
 640    is valid for SVE SUB instructions."
 641  (match_operand 0 "aarch64_sve_sub_arith_immediate"))
 642
 643 (define_constraint "vsQ"
 644   "@internal
 645    Like vsa, but additionally check that the immediate is nonnegative
 646    when interpreted as a signed value."
 647  (match_operand 0 "aarch64_sve_qadd_immediate"))
 648
 649 (define_constraint "vsS"
 650   "@internal
 651    Like vsn, but additionally check that the immediate is negative
 652    when interpreted as a signed value."
 653  (match_operand 0 "aarch64_sve_qsub_immediate"))
 654
 655 (define_constraint "vsl"
 656   "@internal
 657    A constraint that matches an immediate operand valid for SVE logical
 658    operations."
 659  (match_operand 0 "aarch64_sve_logical_immediate"))
 660
 661 (define_constraint "vsm"
 662   "@internal
 663    A constraint that matches an immediate operand valid for SVE MUL,
 664    SMAX and SMIN operations."
 665  (match_operand 0 "aarch64_sve_vsm_immediate"))
 666
 667 (define_constraint "vsA"
 668   "@internal
 669    A constraint that matches an immediate operand valid for SVE FADD
 670    and FSUB operations."
 671  (match_operand 0 "aarch64_sve_float_arith_immediate"))
 672
 673 ;; "B" for "bound".
 674 (define_constraint "vsB"
 675   "@internal
 676    A constraint that matches an immediate operand valid for SVE FMAX
 677    and FMIN operations."
 678  (match_operand 0 "aarch64_sve_float_maxmin_immediate"))
 679
 680 (define_constraint "vsM"
 681   "@internal
 682    A constraint that matches an immediate operand valid for SVE FMUL
 683    operations."
 684  (match_operand 0 "aarch64_sve_float_mul_immediate"))
 685
 686 (define_constraint "vsN"
 687   "@internal
 688    A constraint that matches the negative of vsA"
 689  (match_operand 0 "aarch64_sve_float_negated_arith_immediate"))