gcc/config/aarch64/iterators.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; -------------------------------------------------------------------
  22 ;; Mode Iterators
  23 ;; -------------------------------------------------------------------
  24
  25
  26 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
  27 (define_mode_iterator GPI [SI DI])
  28
  29 ;; Iterator for HI, SI, DI, some instructions can only work on these modes.
  30 (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
  31
  32 ;; Iterator for QI and HI modes
  33 (define_mode_iterator SHORT [QI HI])
  34
  35 ;; Iterator for all integer modes (up to 64-bit)
  36 (define_mode_iterator ALLI [QI HI SI DI])
  37
  38 ;; Iterator for all integer modes (up to 128-bit)
  39 (define_mode_iterator ALLI_TI [QI HI SI DI TI])
  40
  41 ;; Iterator for all integer modes that can be extended (up to 64-bit)
  42 (define_mode_iterator ALLX [QI HI SI])
  43
  44 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
  45 (define_mode_iterator GPF [SF DF])
  46
  47 ;; Iterator for all scalar floating point modes (HF, SF, DF)
  48 (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
  49
  50 ;; Iterator for all scalar floating point modes (HF, SF, DF)
  51 (define_mode_iterator GPF_HF [HF SF DF])
  52
  53 ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
  54 (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
  55
  56 ;; Double vector modes.
  57 (define_mode_iterator VDF [V2SF V4HF])
  58
  59 ;; Iterator for all scalar floating point modes (SF, DF and TF)
  60 (define_mode_iterator GPF_TF [SF DF TF])
  61
  62 ;; Integer Advanced SIMD modes.
  63 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
  64
  65 ;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
  66 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
  67
  68 ;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
  69 ;; integer modes; 64-bit scalar integer mode.
  70 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
  71
  72 ;; Double vector modes.
  73 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
  74
  75 ;; All modes stored in registers d0-d31.
  76 (define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
  77
  78 ;; Copy of the above.
  79 (define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
  80
  81 ;; Advanced SIMD, 64-bit container, all integer modes.
  82 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
  83
  84 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
  85 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
  86
  87 ;; Quad vector modes.
  88 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
  89
  90 ;; Copy of the above.
  91 (define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
  92
  93 ;; Quad integer vector modes.
  94 (define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
  95
  96 ;; VQ without 2 element modes.
  97 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
  98
  99 ;; Quad vector with only 2 element modes.
 100 (define_mode_iterator VQ_2E [V2DI V2DF])
 101
 102 ;; This mode iterator allows :P to be used for patterns that operate on
 103 ;; addresses in different modes.  In LP64, only DI will match, while in
 104 ;; ILP32, either can match.
 105 (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
 106                          (DI "ptr_mode == DImode || Pmode == DImode")])
 107
 108 ;; This mode iterator allows :PTR to be used for patterns that operate on
 109 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
 110 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
 111
 112 ;; Advanced SIMD Float modes suitable for moving, loading and storing.
 113 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
 114
 115 ;; Advanced SIMD Float modes.
 116 (define_mode_iterator VDQF [V2SF V4SF V2DF])
 117 (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
 118                              (V8HF "TARGET_SIMD_F16INST")
 119                              V2SF V4SF V2DF])
 120
 121 ;; Advanced SIMD Float modes, and DF.
 122 (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
 123                                 (V8HF "TARGET_SIMD_F16INST")
 124                                 V2SF V4SF V2DF DF])
 125 (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
 126                                   (V8HF "TARGET_SIMD_F16INST")
 127                                   V2SF V4SF V2DF
 128                                   (HF "TARGET_SIMD_F16INST")
 129                                   SF DF])
 130
 131 ;; Advanced SIMD single Float modes.
 132 (define_mode_iterator VDQSF [V2SF V4SF])
 133
 134 ;; Quad vector Float modes with half/single elements.
 135 (define_mode_iterator VQ_HSF [V8HF V4SF])
 136
 137 ;; Modes suitable to use as the return type of a vcond expression.
 138 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
 139
 140 ;; All scalar and Advanced SIMD Float modes.
 141 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
 142
 143 ;; Advanced SIMD Float modes with 2 elements.
 144 (define_mode_iterator V2F [V2SF V2DF])
 145
 146 ;; All Advanced SIMD modes on which we support any arithmetic operations.
 147 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
 148
 149 ;; All Advanced SIMD modes suitable for moving, loading, and storing.
 150 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
 151                                 V4HF V8HF V2SF V4SF V2DF])
 152
 153 ;; The VALL_F16 modes except the 128-bit 2-element ones.
 154 (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
 155                                 V4HF V8HF V2SF V4SF])
 156
 157 ;; All Advanced SIMD modes barring HF modes, plus DI.
 158 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
 159
 160 ;; All Advanced SIMD modes and DI.
 161 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
 162                                   V4HF V8HF V2SF V4SF V2DF DI])
 163
 164 ;; All Advanced SIMD modes, plus DI and DF.
 165 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
 166                                V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
 167
 168 ;; Advanced SIMD modes for Integer reduction across lanes.
 169 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
 170
 171 ;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
 172 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
 173
 174 ;; All double integer narrow-able modes.
 175 (define_mode_iterator VDN [V4HI V2SI DI])
 176
 177 ;; All quad integer narrow-able modes.
 178 (define_mode_iterator VQN [V8HI V4SI V2DI])
 179
 180 ;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
 181 ;; integer modes
 182 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
 183
 184 ;; All quad integer widen-able modes.
 185 (define_mode_iterator VQW [V16QI V8HI V4SI])
 186
 187 ;; Double vector modes for combines.
 188 (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
 189
 190 ;; Advanced SIMD modes except double int.
 191 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 192 (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
 193                                  V4HF V8HF V2SF V4SF V2DF])
 194
 195 ;; Advanced SIMD modes for S type.
 196 (define_mode_iterator VDQ_SI [V2SI V4SI])
 197
 198 ;; Advanced SIMD modes for S and D.
 199 (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
 200
 201 ;; Advanced SIMD modes for H, S and D.
 202 (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
 203                                 (V8HI "TARGET_SIMD_F16INST")
 204                                 V2SI V4SI V2DI])
 205
 206 ;; Scalar and Advanced SIMD modes for S and D.
 207 (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
 208
 209 ;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
 210 (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
 211                                  (V8HI "TARGET_SIMD_F16INST")
 212                                  V2SI V4SI V2DI
 213                                  (HI "TARGET_SIMD_F16INST")
 214                                  SI DI])
 215
 216 ;; Advanced SIMD modes for Q and H types.
 217 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
 218
 219 ;; Advanced SIMD modes for H and S types.
 220 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
 221
 222 ;; Advanced SIMD modes for H, S and D types.
 223 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
 224
 225 ;; Advanced SIMD and scalar integer modes for H and S.
 226 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
 227
 228 ;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
 229 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
 230
 231 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
 232 (define_mode_iterator VD_HSI [V4HI V2SI])
 233
 234 ;; Scalar 64-bit container: 16, 32-bit integer modes
 235 (define_mode_iterator SD_HSI [HI SI])
 236
 237 ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
 238 (define_mode_iterator VQ_HSI [V8HI V4SI])
 239
 240 ;; All byte modes.
 241 (define_mode_iterator VB [V8QI V16QI])
 242
 243 ;; 2 and 4 lane SI modes.
 244 (define_mode_iterator VS [V2SI V4SI])
 245
 246 (define_mode_iterator TX [TI TF])
 247
 248 ;; Advanced SIMD opaque structure modes.
 249 (define_mode_iterator VSTRUCT [OI CI XI])
 250
 251 ;; Double scalar modes
 252 (define_mode_iterator DX [DI DF])
 253
 254 ;; Duplicate of the above
 255 (define_mode_iterator DX2 [DI DF])
 256
 257 ;; Single scalar modes
 258 (define_mode_iterator SX [SI SF])
 259
 260 ;; Duplicate of the above
 261 (define_mode_iterator SX2 [SI SF])
 262
 263 ;; Single and double integer and float modes
 264 (define_mode_iterator DSX [DF DI SF SI])
 265
 266
 267 ;; Modes available for Advanced SIMD <f>mul lane operations.
 268 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
 269                             (V4HF "TARGET_SIMD_F16INST")
 270                             (V8HF "TARGET_SIMD_F16INST")
 271                             V2SF V4SF V2DF])
 272
 273 ;; Modes available for Advanced SIMD <f>mul lane operations changing lane
 274 ;; count.
 275 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
 276
 277 ;; All SVE vector modes.
 278 (define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
 279                                VNx8HF VNx4SF VNx2DF])
 280
 281 ;; All SVE vector structure modes.
 282 (define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
 283                                   VNx16HF VNx8SF VNx4DF
 284                                   VNx48QI VNx24HI VNx12SI VNx6DI
 285                                   VNx24HF VNx12SF VNx6DF
 286                                   VNx64QI VNx32HI VNx16SI VNx8DI
 287                                   VNx32HF VNx16SF VNx8DF])
 288
 289 ;; All SVE vector modes that have 8-bit or 16-bit elements.
 290 (define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
 291
 292 ;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
 293 (define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
 294
 295 ;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
 296 (define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
 297
 298 ;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
 299 (define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI])
 300
 301 ;; All SVE floating-point vector modes that have 16-bit or 32-bit elements.
 302 (define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
 303
 304 ;; All SVE vector modes that have 32-bit or 64-bit elements.
 305 (define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
 306
 307 ;; All SVE vector modes that have 32-bit elements.
 308 (define_mode_iterator SVE_S [VNx4SI VNx4SF])
 309
 310 ;; All SVE vector modes that have 64-bit elements.
 311 (define_mode_iterator SVE_D [VNx2DI VNx2DF])
 312
 313 ;; All SVE integer vector modes that have 32-bit or 64-bit elements.
 314 (define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
 315
 316 ;; All SVE integer vector modes.
 317 (define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
 318
 319 ;; All SVE floating-point vector modes.
 320 (define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
 321
 322 ;; All SVE predicate modes.
 323 (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
 324
 325 ;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
 326 (define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
 327
 328 ;; ------------------------------------------------------------------
 329 ;; Unspec enumerations for Advance SIMD. These could well go into
 330 ;; aarch64.md but for their use in int_iterators here.
 331 ;; ------------------------------------------------------------------
 332
 333 (define_c_enum "unspec"
 334  [
 335     UNSPEC_ASHIFT_SIGNED        ; Used in aarch-simd.md.
 336     UNSPEC_ASHIFT_UNSIGNED      ; Used in aarch64-simd.md.
 337     UNSPEC_ABS          ; Used in aarch64-simd.md.
 338     UNSPEC_FMAX         ; Used in aarch64-simd.md.
 339     UNSPEC_FMAXNMV      ; Used in aarch64-simd.md.
 340     UNSPEC_FMAXV        ; Used in aarch64-simd.md.
 341     UNSPEC_FMIN         ; Used in aarch64-simd.md.
 342     UNSPEC_FMINNMV      ; Used in aarch64-simd.md.
 343     UNSPEC_FMINV        ; Used in aarch64-simd.md.
 344     UNSPEC_FADDV        ; Used in aarch64-simd.md.
 345     UNSPEC_ADDV         ; Used in aarch64-simd.md.
 346     UNSPEC_SMAXV        ; Used in aarch64-simd.md.
 347     UNSPEC_SMINV        ; Used in aarch64-simd.md.
 348     UNSPEC_UMAXV        ; Used in aarch64-simd.md.
 349     UNSPEC_UMINV        ; Used in aarch64-simd.md.
 350     UNSPEC_SHADD        ; Used in aarch64-simd.md.
 351     UNSPEC_UHADD        ; Used in aarch64-simd.md.
 352     UNSPEC_SRHADD       ; Used in aarch64-simd.md.
 353     UNSPEC_URHADD       ; Used in aarch64-simd.md.
 354     UNSPEC_SHSUB        ; Used in aarch64-simd.md.
 355     UNSPEC_UHSUB        ; Used in aarch64-simd.md.
 356     UNSPEC_SRHSUB       ; Used in aarch64-simd.md.
 357     UNSPEC_URHSUB       ; Used in aarch64-simd.md.
 358     UNSPEC_ADDHN        ; Used in aarch64-simd.md.
 359     UNSPEC_RADDHN       ; Used in aarch64-simd.md.
 360     UNSPEC_SUBHN        ; Used in aarch64-simd.md.
 361     UNSPEC_RSUBHN       ; Used in aarch64-simd.md.
 362     UNSPEC_ADDHN2       ; Used in aarch64-simd.md.
 363     UNSPEC_RADDHN2      ; Used in aarch64-simd.md.
 364     UNSPEC_SUBHN2       ; Used in aarch64-simd.md.
 365     UNSPEC_RSUBHN2      ; Used in aarch64-simd.md.
 366     UNSPEC_SQDMULH      ; Used in aarch64-simd.md.
 367     UNSPEC_SQRDMULH     ; Used in aarch64-simd.md.
 368     UNSPEC_PMUL         ; Used in aarch64-simd.md.
 369     UNSPEC_FMULX        ; Used in aarch64-simd.md.
 370     UNSPEC_USQADD       ; Used in aarch64-simd.md.
 371     UNSPEC_SUQADD       ; Used in aarch64-simd.md.
 372     UNSPEC_SQXTUN       ; Used in aarch64-simd.md.
 373     UNSPEC_SQXTN        ; Used in aarch64-simd.md.
 374     UNSPEC_UQXTN        ; Used in aarch64-simd.md.
 375     UNSPEC_SSRA         ; Used in aarch64-simd.md.
 376     UNSPEC_USRA         ; Used in aarch64-simd.md.
 377     UNSPEC_SRSRA        ; Used in aarch64-simd.md.
 378     UNSPEC_URSRA        ; Used in aarch64-simd.md.
 379     UNSPEC_SRSHR        ; Used in aarch64-simd.md.
 380     UNSPEC_URSHR        ; Used in aarch64-simd.md.
 381     UNSPEC_SQSHLU       ; Used in aarch64-simd.md.
 382     UNSPEC_SQSHL        ; Used in aarch64-simd.md.
 383     UNSPEC_UQSHL        ; Used in aarch64-simd.md.
 384     UNSPEC_SQSHRUN      ; Used in aarch64-simd.md.
 385     UNSPEC_SQRSHRUN     ; Used in aarch64-simd.md.
 386     UNSPEC_SQSHRN       ; Used in aarch64-simd.md.
 387     UNSPEC_UQSHRN       ; Used in aarch64-simd.md.
 388     UNSPEC_SQRSHRN      ; Used in aarch64-simd.md.
 389     UNSPEC_UQRSHRN      ; Used in aarch64-simd.md.
 390     UNSPEC_SSHL         ; Used in aarch64-simd.md.
 391     UNSPEC_USHL         ; Used in aarch64-simd.md.
 392     UNSPEC_SRSHL        ; Used in aarch64-simd.md.
 393     UNSPEC_URSHL        ; Used in aarch64-simd.md.
 394     UNSPEC_SQRSHL       ; Used in aarch64-simd.md.
 395     UNSPEC_UQRSHL       ; Used in aarch64-simd.md.
 396     UNSPEC_SSLI         ; Used in aarch64-simd.md.
 397     UNSPEC_USLI         ; Used in aarch64-simd.md.
 398     UNSPEC_SSRI         ; Used in aarch64-simd.md.
 399     UNSPEC_USRI         ; Used in aarch64-simd.md.
 400     UNSPEC_SSHLL        ; Used in aarch64-simd.md.
 401     UNSPEC_USHLL        ; Used in aarch64-simd.md.
 402     UNSPEC_ADDP         ; Used in aarch64-simd.md.
 403     UNSPEC_TBL          ; Used in vector permute patterns.
 404     UNSPEC_TBX          ; Used in vector permute patterns.
 405     UNSPEC_CONCAT       ; Used in vector permute patterns.
 406
 407     ;; The following permute unspecs are generated directly by
 408     ;; aarch64_expand_vec_perm_const, so any changes to the underlying
 409     ;; instructions would need a corresponding change there.
 410     UNSPEC_ZIP1         ; Used in vector permute patterns.
 411     UNSPEC_ZIP2         ; Used in vector permute patterns.
 412     UNSPEC_UZP1         ; Used in vector permute patterns.
 413     UNSPEC_UZP2         ; Used in vector permute patterns.
 414     UNSPEC_TRN1         ; Used in vector permute patterns.
 415     UNSPEC_TRN2         ; Used in vector permute patterns.
 416     UNSPEC_EXT          ; Used in vector permute patterns.
 417     UNSPEC_REV64        ; Used in vector reverse patterns (permute).
 418     UNSPEC_REV32        ; Used in vector reverse patterns (permute).
 419     UNSPEC_REV16        ; Used in vector reverse patterns (permute).
 420
 421     UNSPEC_AESE         ; Used in aarch64-simd.md.
 422     UNSPEC_AESD         ; Used in aarch64-simd.md.
 423     UNSPEC_AESMC        ; Used in aarch64-simd.md.
 424     UNSPEC_AESIMC       ; Used in aarch64-simd.md.
 425     UNSPEC_SHA1C        ; Used in aarch64-simd.md.
 426     UNSPEC_SHA1M        ; Used in aarch64-simd.md.
 427     UNSPEC_SHA1P        ; Used in aarch64-simd.md.
 428     UNSPEC_SHA1H        ; Used in aarch64-simd.md.
 429     UNSPEC_SHA1SU0      ; Used in aarch64-simd.md.
 430     UNSPEC_SHA1SU1      ; Used in aarch64-simd.md.
 431     UNSPEC_SHA256H      ; Used in aarch64-simd.md.
 432     UNSPEC_SHA256H2     ; Used in aarch64-simd.md.
 433     UNSPEC_SHA256SU0    ; Used in aarch64-simd.md.
 434     UNSPEC_SHA256SU1    ; Used in aarch64-simd.md.
 435     UNSPEC_PMULL        ; Used in aarch64-simd.md.
 436     UNSPEC_PMULL2       ; Used in aarch64-simd.md.
 437     UNSPEC_REV_REGLIST  ; Used in aarch64-simd.md.
 438     UNSPEC_VEC_SHR      ; Used in aarch64-simd.md.
 439     UNSPEC_SQRDMLAH     ; Used in aarch64-simd.md.
 440     UNSPEC_SQRDMLSH     ; Used in aarch64-simd.md.
 441     UNSPEC_FMAXNM       ; Used in aarch64-simd.md.
 442     UNSPEC_FMINNM       ; Used in aarch64-simd.md.
 443     UNSPEC_SDOT         ; Used in aarch64-simd.md.
 444     UNSPEC_UDOT         ; Used in aarch64-simd.md.
 445     UNSPEC_SM3SS1       ; Used in aarch64-simd.md.
 446     UNSPEC_SM3TT1A      ; Used in aarch64-simd.md.
 447     UNSPEC_SM3TT1B      ; Used in aarch64-simd.md.
 448     UNSPEC_SM3TT2A      ; Used in aarch64-simd.md.
 449     UNSPEC_SM3TT2B      ; Used in aarch64-simd.md.
 450     UNSPEC_SM3PARTW1    ; Used in aarch64-simd.md.
 451     UNSPEC_SM3PARTW2    ; Used in aarch64-simd.md.
 452     UNSPEC_SM4E         ; Used in aarch64-simd.md.
 453     UNSPEC_SM4EKEY      ; Used in aarch64-simd.md.
 454     UNSPEC_SHA512H      ; Used in aarch64-simd.md.
 455     UNSPEC_SHA512H2     ; Used in aarch64-simd.md.
 456     UNSPEC_SHA512SU0    ; Used in aarch64-simd.md.
 457     UNSPEC_SHA512SU1    ; Used in aarch64-simd.md.
 458     UNSPEC_FMLAL        ; Used in aarch64-simd.md.
 459     UNSPEC_FMLSL        ; Used in aarch64-simd.md.
 460     UNSPEC_FMLAL2       ; Used in aarch64-simd.md.
 461     UNSPEC_FMLSL2       ; Used in aarch64-simd.md.
 462     UNSPEC_SEL          ; Used in aarch64-sve.md.
 463     UNSPEC_ANDV         ; Used in aarch64-sve.md.
 464     UNSPEC_IORV         ; Used in aarch64-sve.md.
 465     UNSPEC_XORV         ; Used in aarch64-sve.md.
 466     UNSPEC_ANDF         ; Used in aarch64-sve.md.
 467     UNSPEC_IORF         ; Used in aarch64-sve.md.
 468     UNSPEC_XORF         ; Used in aarch64-sve.md.
 469     UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
 470     UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
 471     UNSPEC_COND_ADD     ; Used in aarch64-sve.md.
 472     UNSPEC_COND_SUB     ; Used in aarch64-sve.md.
 473     UNSPEC_COND_MUL     ; Used in aarch64-sve.md.
 474     UNSPEC_COND_DIV     ; Used in aarch64-sve.md.
 475     UNSPEC_COND_MAX     ; Used in aarch64-sve.md.
 476     UNSPEC_COND_MIN     ; Used in aarch64-sve.md.
 477     UNSPEC_COND_FMLA    ; Used in aarch64-sve.md.
 478     UNSPEC_COND_FMLS    ; Used in aarch64-sve.md.
 479     UNSPEC_COND_FNMLA   ; Used in aarch64-sve.md.
 480     UNSPEC_COND_FNMLS   ; Used in aarch64-sve.md.
 481     UNSPEC_COND_LT      ; Used in aarch64-sve.md.
 482     UNSPEC_COND_LE      ; Used in aarch64-sve.md.
 483     UNSPEC_COND_EQ      ; Used in aarch64-sve.md.
 484     UNSPEC_COND_NE      ; Used in aarch64-sve.md.
 485     UNSPEC_COND_GE      ; Used in aarch64-sve.md.
 486     UNSPEC_COND_GT      ; Used in aarch64-sve.md.
 487     UNSPEC_LASTB        ; Used in aarch64-sve.md.
 488 ])
 489
 490 ;; ------------------------------------------------------------------
 491 ;; Unspec enumerations for Atomics.  They are here so that they can be
 492 ;; used in the int_iterators for atomic operations.
 493 ;; ------------------------------------------------------------------
 494
 495 (define_c_enum "unspecv"
 496  [
 497     UNSPECV_LX                  ; Represent a load-exclusive.
 498     UNSPECV_SX                  ; Represent a store-exclusive.
 499     UNSPECV_LDA                 ; Represent an atomic load or load-acquire.
 500     UNSPECV_STL                 ; Represent an atomic store or store-release.
 501     UNSPECV_ATOMIC_CMPSW        ; Represent an atomic compare swap.
 502     UNSPECV_ATOMIC_EXCHG        ; Represent an atomic exchange.
 503     UNSPECV_ATOMIC_CAS          ; Represent an atomic CAS.
 504     UNSPECV_ATOMIC_SWP          ; Represent an atomic SWP.
 505     UNSPECV_ATOMIC_OP           ; Represent an atomic operation.
 506     UNSPECV_ATOMIC_LDOP_OR      ; Represent an atomic load-or
 507     UNSPECV_ATOMIC_LDOP_BIC     ; Represent an atomic load-bic
 508     UNSPECV_ATOMIC_LDOP_XOR     ; Represent an atomic load-xor
 509     UNSPECV_ATOMIC_LDOP_PLUS    ; Represent an atomic load-add
 510 ])
 511
 512 ;; -------------------------------------------------------------------
 513 ;; Mode attributes
 514 ;; -------------------------------------------------------------------
 515
 516 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
 517 ;; 32-bit version and "%x0" in the 64-bit version.
 518 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
 519
 520 ;; The size of access, in bytes.
 521 (define_mode_attr ldst_sz [(SI "4") (DI "8")])
 522 ;; Likewise for load/store pair.
 523 (define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
 524
 525 ;; For inequal width int to float conversion
 526 (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
 527 (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
 528
 529 ;; For width of fp registers in fcvt instruction
 530 (define_mode_attr fpw [(DI "s") (SI "d")])
 531
 532 (define_mode_attr short_mask [(HI "65535") (QI "255")])
 533
 534 ;; For constraints used in scalar immediate vector moves
 535 (define_mode_attr hq [(HI "h") (QI "q")])
 536
 537 ;; For doubling width of an integer mode
 538 (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
 539
 540 (define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
 541
 542 (define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
 543
 544 ;; For scalar usage of vector/FP registers
 545 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
 546                     (HF  "h") (SF "s") (DF "d")
 547                     (V8QI "") (V16QI "")
 548                     (V4HI "") (V8HI "")
 549                     (V2SI "") (V4SI  "")
 550                     (V2DI "") (V2SF "")
 551                     (V4SF "") (V4HF "")
 552                     (V8HF "") (V2DF "")])
 553
 554 ;; For scalar usage of vector/FP registers, narrowing
 555 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
 556                     (V8QI "") (V16QI "")
 557                     (V4HI "") (V8HI "")
 558                     (V2SI "") (V4SI  "")
 559                     (V2DI "") (V2SF "")
 560                     (V4SF "") (V2DF "")])
 561
 562 ;; For scalar usage of vector/FP registers, widening
 563 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
 564                     (V8QI "") (V16QI "")
 565                     (V4HI "") (V8HI "")
 566                     (V2SI "") (V4SI  "")
 567                     (V2DI "") (V2SF "")
 568                     (V4SF "") (V2DF "")])
 569
 570 ;; Register Type Name and Vector Arrangement Specifier for when
 571 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
 572 ;; lane 0).
 573 (define_mode_attr rtn [(DI "d") (SI "")])
 574 (define_mode_attr vas [(DI "") (SI ".2s")])
 575
 576 ;; Map a vector to the number of units in it, if the size of the mode
 577 ;; is constant.
 578 (define_mode_attr nunits [(V8QI "8") (V16QI "16")
 579                           (V4HI "4") (V8HI "8")
 580                           (V2SI "2") (V4SI "4")
 581                                      (V2DI "2")
 582                           (V4HF "4") (V8HF "8")
 583                           (V2SF "2") (V4SF "4")
 584                           (V1DF "1") (V2DF "2")
 585                           (DI "1") (DF "1")])
 586
 587 ;; Map a mode to the number of bits in it, if the size of the mode
 588 ;; is constant.
 589 (define_mode_attr bitsize [(V8QI "64") (V16QI "128")
 590                            (V4HI "64") (V8HI "128")
 591                            (V2SI "64") (V4SI "128")
 592                                        (V2DI "128")])
 593
 594 ;; Map a floating point or integer mode to the appropriate register name prefix
 595 (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
 596
 597 ;; Give the length suffix letter for a sign- or zero-extension.
 598 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
 599
 600 ;; Give the number of bits in the mode
 601 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
 602
 603 ;; Give the ordinal of the MSB in the mode
 604 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")
 605                           (HF "#15") (SF "#31") (DF "#63")])
 606
 607 ;; Attribute to describe constants acceptable in logical operations
 608 (define_mode_attr lconst [(SI "K") (DI "L")])
 609
 610 ;; Attribute to describe constants acceptable in logical and operations
 611 (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
 612
 613 ;; Map a mode to a specific constraint character.
 614 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
 615
 616 ;; Map modes to Usg and Usj constraints for SISD right shifts
 617 (define_mode_attr cmode_simd [(SI "g") (DI "j")])
 618
 619 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
 620                          (V4HI "4h") (V8HI  "8h")
 621                          (V2SI "2s") (V4SI  "4s")
 622                          (DI   "1d") (DF    "1d")
 623                          (V2DI "2d") (V2SF "2s")
 624                          (V4SF "4s") (V2DF "2d")
 625                          (V4HF "4h") (V8HF "8h")])
 626
 627 (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
 628                             (V4SI "32") (V2DI "64")])
 629
 630 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
 631                          (V4HI ".4h") (V8HI  ".8h")
 632                          (V2SI ".2s") (V4SI  ".4s")
 633                          (V2DI ".2d") (V4HF ".4h")
 634                          (V8HF ".8h") (V2SF ".2s")
 635                          (V4SF ".4s") (V2DF ".2d")
 636                          (DI   "")    (SI   "")
 637                          (HI   "")    (QI   "")
 638                          (TI   "")    (HF   "")
 639                          (SF   "")    (DF   "")])
 640
 641 ;; Register suffix narrowed modes for VQN.
 642 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
 643                            (V2DI ".2s")
 644                            (DI   "")    (SI   "")
 645                            (HI   "")])
 646
 647 ;; Mode-to-individual element type mapping.
 648 (define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
 649                           (V4HI "h") (V8HI  "h") (VNx8HI  "h") (VNx8BI  "h")
 650                           (V2SI "s") (V4SI  "s") (VNx4SI  "s") (VNx4BI  "s")
 651                           (V2DI "d")             (VNx2DI  "d") (VNx2BI  "d")
 652                           (V4HF "h") (V8HF  "h") (VNx8HF  "h")
 653                           (V2SF "s") (V4SF  "s") (VNx4SF  "s")
 654                           (V2DF "d")             (VNx2DF  "d")
 655                           (HF   "h")
 656                           (SF   "s") (DF  "d")
 657                           (QI "b")   (HI "h")
 658                           (SI "s")   (DI "d")])
 659
 660 ;; Equivalent of "size" for a vector element.
 661 (define_mode_attr Vesize [(VNx16QI "b")
 662                           (VNx8HI  "h") (VNx8HF  "h")
 663                           (VNx4SI  "w") (VNx4SF  "w")
 664                           (VNx2DI  "d") (VNx2DF  "d")
 665                           (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
 666                           (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
 667                           (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
 668                           (VNx8SI  "w") (VNx12SI "w") (VNx16SI "w")
 669                           (VNx8SF  "w") (VNx12SF "w") (VNx16SF "w")
 670                           (VNx4DI  "d") (VNx6DI  "d") (VNx8DI  "d")
 671                           (VNx4DF  "d") (VNx6DF  "d") (VNx8DF  "d")])
 672
 673 ;; Vetype is used everywhere in scheduling type and assembly output,
 674 ;; sometimes they are not the same, for example HF modes on some
 675 ;; instructions.  stype is defined to represent scheduling type
 676 ;; more accurately.
 677 (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
 678                          (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
 679                          (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
 680                          (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
 681                          (SI "s") (DI "d")])
 682
 683 ;; Mode-to-bitwise operation type mapping.
 684 (define_mode_attr Vbtype [(V8QI "8b")  (V16QI "16b")
 685                           (V4HI "8b") (V8HI  "16b")
 686                           (V2SI "8b") (V4SI  "16b")
 687                           (V2DI "16b") (V4HF "8b")
 688                           (V8HF "16b") (V2SF  "8b")
 689                           (V4SF "16b") (V2DF  "16b")
 690                           (DI   "8b")  (DF    "8b")
 691                           (SI   "8b")  (SF    "8b")])
 692
 693 ;; Define element mode for each vector mode.
 694 (define_mode_attr VEL [(V8QI  "QI") (V16QI "QI") (VNx16QI "QI")
 695                         (V4HI "HI") (V8HI  "HI") (VNx8HI  "HI")
 696                         (V2SI "SI") (V4SI  "SI") (VNx4SI  "SI")
 697                         (DI   "DI") (V2DI  "DI") (VNx2DI  "DI")
 698                         (V4HF "HF") (V8HF  "HF") (VNx8HF  "HF")
 699                         (V2SF "SF") (V4SF  "SF") (VNx4SF  "SF")
 700                         (DF   "DF") (V2DF  "DF") (VNx2DF  "DF")
 701                         (SI   "SI") (HI    "HI")
 702                         (QI   "QI")])
 703
 704 ;; Define element mode for each vector mode (lower case).
 705 (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
 706                         (V4HI "hi") (V8HI "hi") (VNx8HI  "hi")
 707                         (V2SI "si") (V4SI "si") (VNx4SI  "si")
 708                         (DI "di")   (V2DI "di") (VNx2DI  "di")
 709                         (V4HF "hf") (V8HF "hf") (VNx8HF  "hf")
 710                         (V2SF "sf") (V4SF "sf") (VNx4SF  "sf")
 711                         (V2DF "df") (DF "df")   (VNx2DF  "df")
 712                         (SI   "si") (HI   "hi")
 713                         (QI   "qi")])
 714
 715 ;; Element mode with floating-point values replaced by like-sized integers.
 716 (define_mode_attr VEL_INT [(VNx16QI "QI")
 717                            (VNx8HI  "HI") (VNx8HF "HI")
 718                            (VNx4SI  "SI") (VNx4SF "SI")
 719                            (VNx2DI  "DI") (VNx2DF "DI")])
 720
 721 ;; Gives the mode of the 128-bit lowpart of an SVE vector.
 722 (define_mode_attr V128 [(VNx16QI "V16QI")
 723                         (VNx8HI  "V8HI") (VNx8HF "V8HF")
 724                         (VNx4SI  "V4SI") (VNx4SF "V4SF")
 725                         (VNx2DI  "V2DI") (VNx2DF "V2DF")])
 726
 727 ;; ...and again in lower case.
 728 (define_mode_attr v128 [(VNx16QI "v16qi")
 729                         (VNx8HI  "v8hi") (VNx8HF "v8hf")
 730                         (VNx4SI  "v4si") (VNx4SF "v4sf")
 731                         (VNx2DI  "v2di") (VNx2DF "v2df")])
 732
 733 ;; 64-bit container modes the inner or scalar source mode.
 734 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
 735                          (V4HI "V4HI") (V8HI "V4HI")
 736                          (V2SI "V2SI") (V4SI "V2SI")
 737                          (DI   "DI") (V2DI "DI")
 738                          (V2SF "V2SF") (V4SF "V2SF")
 739                          (V2DF "DF")])
 740
 741 ;; 128-bit container modes the inner or scalar source mode.
 742 (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
 743                          (V4HI "V8HI") (V8HI "V8HI")
 744                          (V2SI "V4SI") (V4SI "V4SI")
 745                          (DI   "V2DI") (V2DI "V2DI")
 746                          (V4HF "V8HF") (V8HF "V8HF")
 747                          (V2SF "V2SF") (V4SF "V4SF")
 748                          (V2DF "V2DF") (SI   "V4SI")
 749                          (HI   "V8HI") (QI   "V16QI")])
 750
 751 ;; Half modes of all vector modes.
 752 (define_mode_attr VHALF [(V8QI "V4QI")  (V16QI "V8QI")
 753                          (V4HI "V2HI")  (V8HI  "V4HI")
 754                          (V2SI "SI")    (V4SI  "V2SI")
 755                          (V2DI "DI")    (V2SF  "SF")
 756                          (V4SF "V2SF")  (V4HF "V2HF")
 757                          (V8HF "V4HF")  (V2DF  "DF")])
 758
 759 ;; Half modes of all vector modes, in lower-case.
 760 (define_mode_attr Vhalf [(V8QI "v4qi")  (V16QI "v8qi")
 761                          (V4HI "v2hi")  (V8HI  "v4hi")
 762                          (V2SI "si")    (V4SI  "v2si")
 763                          (V2DI "di")    (V2SF  "sf")
 764                          (V4SF "v2sf")  (V2DF  "df")])
 765
 766 ;; Double modes of vector modes.
 767 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
 768                         (V4HF "V8HF")
 769                         (V2SI "V4SI")  (V2SF "V4SF")
 770                         (SI   "V2SI")  (DI   "V2DI")
 771                         (DF   "V2DF")])
 772
 773 ;; Register suffix for double-length mode.
 774 (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
 775
 776 ;; Double modes of vector modes (lower case).
 777 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
 778                         (V4HF "v8hf")
 779                         (V2SI "v4si")  (V2SF "v4sf")
 780                         (SI   "v2si")  (DI   "v2di")
 781                         (DF   "v2df")])
 782
 783 ;; Modes with double-width elements.
 784 (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
 785                   (V4HI "V2SI") (V8HI "V4SI")
 786                   (V2SI "DI")   (V4SI "V2DI")])
 787
 788 ;; Narrowed modes for VDN.
 789 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
 790                             (DI   "V2SI")])
 791
 792 ;; Narrowed double-modes for VQN (Used for XTN).
 793 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
 794                             (V2DI "V2SI")
 795                             (DI   "SI")   (SI   "HI")
 796                             (HI   "QI")])
 797
 798 ;; Narrowed quad-modes for VQN (Used for XTN2).
 799 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
 800                              (V2DI "V4SI")])
 801
 802 ;; Register suffix narrowed modes for VQN.
 803 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
 804                           (V2DI "2s")])
 805
 806 ;; Register suffix narrowed modes for VQN.
 807 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
 808                            (V2DI "4s")])
 809
 810 ;; Widened modes of vector modes.
 811 (define_mode_attr VWIDE [(V8QI  "V8HI")  (V4HI  "V4SI")
 812                          (V2SI  "V2DI")  (V16QI "V8HI")
 813                          (V8HI  "V4SI")  (V4SI  "V2DI")
 814                          (HI    "SI")    (SI    "DI")
 815                          (V8HF  "V4SF")  (V4SF  "V2DF")
 816                          (V4HF  "V4SF")  (V2SF  "V2DF")
 817                          (VNx8HF  "VNx4SF") (VNx4SF "VNx2DF")
 818                          (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
 819                          (VNx4SI  "VNx2DI")
 820                          (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
 821                          (VNx4BI  "VNx2BI")])
 822
 823 ;; Predicate mode associated with VWIDE.
 824 (define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
 825
 826 ;; Widened modes of vector modes, lowercase
 827 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
 828                          (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
 829                          (VNx4SI  "vnx2di")
 830                          (VNx8HF  "vnx4sf") (VNx4SF "vnx2df")
 831                          (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
 832                          (VNx4BI  "vnx2bi")])
 833
 834 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
 835 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
 836                           (V2SI "2d") (V16QI "8h")
 837                           (V8HI "4s") (V4SI "2d")
 838                           (V8HF "4s") (V4SF "2d")])
 839
 840 ;; SVE vector after widening
 841 (define_mode_attr Vewtype [(VNx16QI "h")
 842                            (VNx8HI  "s") (VNx8HF "s")
 843                            (VNx4SI  "d") (VNx4SF "d")])
 844
 845 ;; Widened mode register suffixes for VDW/VQW.
 846 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
 847                            (V2SI ".2d") (V16QI ".8h")
 848                            (V8HI ".4s") (V4SI ".2d")
 849                            (V4HF ".4s") (V2SF ".2d")
 850                            (SI   "")    (HI   "")])
 851
 852 ;; Lower part register suffixes for VQW/VQ_HSF.
 853 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
 854                              (V4SI "2s") (V8HF "4h")
 855                              (V4SF "2s")])
 856
 857 ;; Define corresponding core/FP element mode for each vector mode.
 858 (define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
 859                       (V4HI "w") (V8HI "w") (VNx8HI "w")
 860                       (V2SI "w") (V4SI "w") (VNx4SI "w")
 861                       (DI   "x") (V2DI "x") (VNx2DI "x")
 862                       (VNx8HF "h")
 863                       (V2SF "s") (V4SF "s") (VNx4SF "s")
 864                       (V2DF "d") (VNx2DF "d")])
 865
 866 ;; Corresponding core element mode for each vector mode.  This is a
 867 ;; variation on <vw> mapping FP modes to GP regs.
 868 (define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
 869                           (V4HI "w") (V8HI "w") (VNx8HI "w")
 870                           (V2SI "w") (V4SI "w") (VNx4SI "w")
 871                           (DI   "x") (V2DI "x") (VNx2DI "x")
 872                           (V4HF "w") (V8HF "w") (VNx8HF "w")
 873                           (V2SF "w") (V4SF "w") (VNx4SF "w")
 874                           (V2DF "x") (VNx2DF "x")])
 875
 876 ;; Double vector types for ALLX.
 877 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
 878
 879 ;; Mode with floating-point values replaced by like-sized integers.
 880 (define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
 881                                (V4HI "V4HI") (V8HI  "V8HI")
 882                                (V2SI "V2SI") (V4SI  "V4SI")
 883                                (DI   "DI")   (V2DI  "V2DI")
 884                                (V4HF "V4HI") (V8HF  "V8HI")
 885                                (V2SF "V2SI") (V4SF  "V4SI")
 886                                (DF   "DI")   (V2DF  "V2DI")
 887                                (SF   "SI")   (SI    "SI")
 888                                (HF    "HI")
 889                                (VNx16QI "VNx16QI")
 890                                (VNx8HI  "VNx8HI") (VNx8HF "VNx8HI")
 891                                (VNx4SI  "VNx4SI") (VNx4SF "VNx4SI")
 892                                (VNx2DI  "VNx2DI") (VNx2DF "VNx2DI")
 893 ])
 894
 895 ;; Lower case mode with floating-point values replaced by like-sized integers.
 896 (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
 897                                (V4HI "v4hi") (V8HI  "v8hi")
 898                                (V2SI "v2si") (V4SI  "v4si")
 899                                (DI   "di")   (V2DI  "v2di")
 900                                (V4HF "v4hi") (V8HF  "v8hi")
 901                                (V2SF "v2si") (V4SF  "v4si")
 902                                (DF   "di")   (V2DF  "v2di")
 903                                (SF   "si")
 904                                (VNx16QI "vnx16qi")
 905                                (VNx8HI  "vnx8hi") (VNx8HF "vnx8hi")
 906                                (VNx4SI  "vnx4si") (VNx4SF "vnx4si")
 907                                (VNx2DI  "vnx2di") (VNx2DF "vnx2di")
 908 ])
 909
 910 ;; Floating-point equivalent of selected modes.
 911 (define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
 912                               (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
 913 (define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
 914                               (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
 915
 916 ;; Mode for vector conditional operations where the comparison has
 917 ;; different type from the lhs.
 918 (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
 919                                (V2DI "V2DF") (V2SF "V2SI")
 920                                (V4SF "V4SI") (V2DF "V2DI")])
 921
 922 (define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
 923                                (V2DI "v2df") (V2SF "v2si")
 924                                (V4SF "v4si") (V2DF "v2di")])
 925
 926 ;; Lower case element modes (as used in shift immediate patterns).
 927 (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
 928                            (V4HI "hi") (V8HI  "hi")
 929                            (V2SI "si") (V4SI  "si")
 930                            (DI   "di") (V2DI  "di")
 931                            (QI   "qi") (HI    "hi")
 932                            (SI   "si")])
 933
 934 ;; Vm for lane instructions is restricted to FP_LO_REGS.
 935 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
 936                        (V2SI "w") (V4SI "w") (SI "w")])
 937
 938 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
 939
 940 ;; This is both the number of Q-Registers needed to hold the corresponding
 941 ;; opaque large integer mode, and the number of elements touched by the
 942 ;; ld..._lane and st..._lane operations.
 943 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
 944
 945 ;; Mode for atomic operation suffixes
 946 (define_mode_attr atomic_sfx
 947   [(QI "b") (HI "h") (SI "") (DI "")])
 948
 949 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
 950                                (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
 951                                (SF "si") (DF "di") (SI "sf") (DI "df")
 952                                (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
 953                                (V8HI "v8hf") (HF "hi") (HI "hf")])
 954 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
 955                                (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
 956                                (SF "SI") (DF "DI") (SI "SF") (DI "DF")
 957                                (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
 958                                (V8HI "V8HF") (HF "HI") (HI "HF")])
 959
 960
 961 ;; for the inequal width integer to fp conversions
 962 (define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
 963 (define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
 964
 965 (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
 966                                 (V4HI "V8HI") (V8HI  "V4HI")
 967                                 (V2SI "V4SI") (V4SI  "V2SI")
 968                                 (DI   "V2DI") (V2DI  "DI")
 969                                 (V2SF "V4SF") (V4SF  "V2SF")
 970                                 (V4HF "V8HF") (V8HF  "V4HF")
 971                                 (DF   "V2DF") (V2DF  "DF")])
 972
 973 (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
 974                                     (V4HI "to_128") (V8HI  "to_64")
 975                                     (V2SI "to_128") (V4SI  "to_64")
 976                                     (DI   "to_128") (V2DI  "to_64")
 977                                     (V4HF "to_128") (V8HF  "to_64")
 978                                     (V2SF "to_128") (V4SF  "to_64")
 979                                     (DF   "to_128") (V2DF  "to_64")])
 980
 981 ;; For certain vector-by-element multiplication instructions we must
 982 ;; constrain the 16-bit cases to use only V0-V15.  This is covered by
 983 ;; the 'x' constraint.  All other modes may use the 'w' constraint.
 984 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
 985                          (V4HI "x") (V8HI "x")
 986                          (V4HF "x") (V8HF "x")
 987                          (V2SF "w") (V4SF "w")
 988                          (V2DF "w") (DF "w")])
 989
 990 ;; Defined to 'f' for types whose element type is a float type.
 991 (define_mode_attr f [(V8QI "")  (V16QI "")
 992                      (V4HI "")  (V8HI  "")
 993                      (V2SI "")  (V4SI  "")
 994                      (DI   "")  (V2DI  "")
 995                      (V4HF "f") (V8HF  "f")
 996                      (V2SF "f") (V4SF  "f")
 997                      (V2DF "f") (DF    "f")])
 998
 999 ;; Defined to '_fp' for types whose element type is a float type.
1000 (define_mode_attr fp [(V8QI "")  (V16QI "")
1001                       (V4HI "")  (V8HI  "")
1002                       (V2SI "")  (V4SI  "")
1003                       (DI   "")  (V2DI  "")
1004                       (V4HF "_fp") (V8HF  "_fp")
1005                       (V2SF "_fp") (V4SF  "_fp")
1006                       (V2DF "_fp") (DF    "_fp")
1007                       (SF "_fp")])
1008
1009 ;; Defined to '_q' for 128-bit types.
1010 (define_mode_attr q [(V8QI "") (V16QI "_q")
1011                      (V4HI "") (V8HI  "_q")
1012                      (V2SI "") (V4SI  "_q")
1013                      (DI   "") (V2DI  "_q")
1014                      (V4HF "") (V8HF "_q")
1015                      (V2SF "") (V4SF  "_q")
1016                                (V2DF  "_q")
1017                      (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
1018
1019 (define_mode_attr vp [(V8QI "v") (V16QI "v")
1020                       (V4HI "v") (V8HI  "v")
1021                       (V2SI "p") (V4SI  "v")
1022                       (V2DI "p") (V2DF  "p")
1023                       (V2SF "p") (V4SF  "v")
1024                       (V4HF "v") (V8HF  "v")])
1025
1026 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
1027 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
1028
1029
1030 ;; Register suffix for DOTPROD input types from the return type.
1031 (define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1032
1033 ;; Sum of lengths of instructions needed to move vector registers of a mode.
1034 (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1035
1036 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1037 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1038 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1039
1040 ;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1041 (define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1042
1043 (define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1044
1045 (define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1046
1047 (define_code_attr f16mac [(plus "a") (minus "s")])
1048
1049 ;; The number of subvectors in an SVE_STRUCT.
1050 (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1051                                 (VNx8SI  "2") (VNx4DI  "2")
1052                                 (VNx16HF "2") (VNx8SF  "2") (VNx4DF "2")
1053                                 (VNx48QI "3") (VNx24HI "3")
1054                                 (VNx12SI "3") (VNx6DI  "3")
1055                                 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1056                                 (VNx64QI "4") (VNx32HI "4")
1057                                 (VNx16SI "4") (VNx8DI  "4")
1058                                 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1059
1060 ;; The number of instruction bytes needed for an SVE_STRUCT move.  This is
1061 ;; equal to vector_count * 4.
1062 (define_mode_attr insn_length [(VNx32QI "8")  (VNx16HI "8")
1063                                (VNx8SI  "8")  (VNx4DI  "8")
1064                                (VNx16HF "8")  (VNx8SF  "8")  (VNx4DF "8")
1065                                (VNx48QI "12") (VNx24HI "12")
1066                                (VNx12SI "12") (VNx6DI  "12")
1067                                (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1068                                (VNx64QI "16") (VNx32HI "16")
1069                                (VNx16SI "16") (VNx8DI  "16")
1070                                (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1071
1072 ;; The type of a subvector in an SVE_STRUCT.
1073 (define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1074                            (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1075                            (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1076                            (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1077                            (VNx48QI "VNx16QI")
1078                            (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1079                            (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1080                            (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1081                            (VNx64QI "VNx16QI")
1082                            (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1083                            (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1084                            (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1085
1086 ;; ...and again in lower case.
1087 (define_mode_attr vsingle [(VNx32QI "vnx16qi")
1088                            (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1089                            (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1090                            (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1091                            (VNx48QI "vnx16qi")
1092                            (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1093                            (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1094                            (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1095                            (VNx64QI "vnx16qi")
1096                            (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1097                            (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1098                            (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1099
1100 ;; The predicate mode associated with an SVE data mode.  For structure modes
1101 ;; this is equivalent to the <VPRED> of the subvector mode.
1102 (define_mode_attr VPRED [(VNx16QI "VNx16BI")
1103                          (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
1104                          (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
1105                          (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
1106                          (VNx32QI "VNx16BI")
1107                          (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1108                          (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1109                          (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1110                          (VNx48QI "VNx16BI")
1111                          (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1112                          (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1113                          (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1114                          (VNx64QI "VNx16BI")
1115                          (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1116                          (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1117                          (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
1118
1119 ;; ...and again in lower case.
1120 (define_mode_attr vpred [(VNx16QI "vnx16bi")
1121                          (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
1122                          (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
1123                          (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
1124                          (VNx32QI "vnx16bi")
1125                          (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1126                          (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1127                          (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1128                          (VNx48QI "vnx16bi")
1129                          (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1130                          (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1131                          (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1132                          (VNx64QI "vnx16bi")
1133                          (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1134                          (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1135                          (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
1136
1137 ;; -------------------------------------------------------------------
1138 ;; Code Iterators
1139 ;; -------------------------------------------------------------------
1140
1141 ;; This code iterator allows the various shifts supported on the core
1142 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1143
1144 ;; This code iterator allows the shifts supported in arithmetic instructions
1145 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1146
1147 ;; Code iterator for logical operations
1148 (define_code_iterator LOGICAL [and ior xor])
1149
1150 ;; LOGICAL without AND.
1151 (define_code_iterator LOGICAL_OR [ior xor])
1152
1153 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1154 (define_code_iterator NLOGICAL [and ior])
1155
1156 ;; Code iterator for unary negate and bitwise complement.
1157 (define_code_iterator NEG_NOT [neg not])
1158
1159 ;; Code iterator for sign/zero extension
1160 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1161
1162 ;; All division operations (signed/unsigned)
1163 (define_code_iterator ANY_DIV [div udiv])
1164
1165 ;; Code iterator for sign/zero extraction
1166 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1167
1168 ;; Code iterator for equality comparisons
1169 (define_code_iterator EQL [eq ne])
1170
1171 ;; Code iterator for less-than and greater/equal-to
1172 (define_code_iterator LTGE [lt ge])
1173
1174 ;; Iterator for __sync_<op> operations that where the operation can be
1175 ;; represented directly RTL.  This is all of the sync operations bar
1176 ;; nand.
1177 (define_code_iterator atomic_op [plus minus ior xor and])
1178
1179 ;; Iterator for integer conversions
1180 (define_code_iterator FIXUORS [fix unsigned_fix])
1181
1182 ;; Iterator for float conversions
1183 (define_code_iterator FLOATUORS [float unsigned_float])
1184
1185 ;; Code iterator for variants of vector max and min.
1186 (define_code_iterator MAXMIN [smax smin umax umin])
1187
1188 (define_code_iterator FMAXMIN [smax smin])
1189
1190 ;; Code iterator for variants of vector max and min.
1191 (define_code_iterator ADDSUB [plus minus])
1192
1193 ;; Code iterator for variants of vector saturating binary ops.
1194 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1195
1196 ;; Code iterator for variants of vector saturating unary ops.
1197 (define_code_iterator UNQOPS [ss_neg ss_abs])
1198
1199 ;; Code iterator for signed variants of vector saturating binary ops.
1200 (define_code_iterator SBINQOPS [ss_plus ss_minus])
1201
1202 ;; Comparison operators for <F>CM.
1203 (define_code_iterator COMPARISONS [lt le eq ge gt])
1204
1205 ;; Unsigned comparison operators.
1206 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1207
1208 ;; Unsigned comparison operators.
1209 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
1210
1211 ;; SVE integer unary operations.
1212 (define_code_iterator SVE_INT_UNARY [abs neg not popcount])
1213
1214 ;; SVE floating-point unary operations.
1215 (define_code_iterator SVE_FP_UNARY [abs neg sqrt])
1216
1217 ;; SVE integer binary operations.
1218 (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
1219                                       and ior xor])
1220
1221 ;; SVE integer binary division operations.
1222 (define_code_iterator SVE_INT_BINARY_SD [div udiv])
1223
1224 ;; SVE floating-point operations with an unpredicated all-register form.
1225 (define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult])
1226
1227 ;; SVE integer comparisons.
1228 (define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1229
1230 ;; SVE floating-point comparisons.
1231 (define_code_iterator SVE_FP_CMP [lt le eq ne ge gt])
1232
1233 ;; -------------------------------------------------------------------
1234 ;; Code Attributes
1235 ;; -------------------------------------------------------------------
1236 ;; Map rtl objects to optab names
1237 (define_code_attr optab [(ashift "ashl")
1238                          (ashiftrt "ashr")
1239                          (lshiftrt "lshr")
1240                          (rotatert "rotr")
1241                          (sign_extend "extend")
1242                          (zero_extend "zero_extend")
1243                          (sign_extract "extv")
1244                          (zero_extract "extzv")
1245                          (fix "fix")
1246                          (unsigned_fix "fixuns")
1247                          (float "float")
1248                          (unsigned_float "floatuns")
1249                          (popcount "popcount")
1250                          (and "and")
1251                          (ior "ior")
1252                          (xor "xor")
1253                          (not "one_cmpl")
1254                          (neg "neg")
1255                          (plus "add")
1256                          (minus "sub")
1257                          (mult "mul")
1258                          (div "div")
1259                          (udiv "udiv")
1260                          (ss_plus "qadd")
1261                          (us_plus "qadd")
1262                          (ss_minus "qsub")
1263                          (us_minus "qsub")
1264                          (ss_neg "qneg")
1265                          (ss_abs "qabs")
1266                          (smin "smin")
1267                          (smax "smax")
1268                          (umin "umin")
1269                          (umax "umax")
1270                          (eq "eq")
1271                          (ne "ne")
1272                          (lt "lt")
1273                          (ge "ge")
1274                          (le "le")
1275                          (gt "gt")
1276                          (ltu "ltu")
1277                          (leu "leu")
1278                          (geu "geu")
1279                          (gtu "gtu")
1280                          (abs "abs")
1281                          (sqrt "sqrt")])
1282
1283 ;; For comparison operators we use the FCM* and CM* instructions.
1284 ;; As there are no CMLE or CMLT instructions which act on 3 vector
1285 ;; operands, we must use CMGE or CMGT and swap the order of the
1286 ;; source operands.
1287
1288 (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1289                            (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1290 (define_code_attr cmp_1   [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1291                            (ltu "2") (leu "2") (geu "1") (gtu "1")])
1292 (define_code_attr cmp_2   [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1293                            (ltu "1") (leu "1") (geu "2") (gtu "2")])
1294
1295 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
1296                         (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1297                         (gtu "GTU")])
1298
1299 ;; The AArch64 condition associated with an rtl comparison code.
1300 (define_code_attr cmp_op [(lt "lt")
1301                           (le "le")
1302                           (eq "eq")
1303                           (ne "ne")
1304                           (ge "ge")
1305                           (gt "gt")
1306                           (ltu "lo")
1307                           (leu "ls")
1308                           (geu "hs")
1309                           (gtu "hi")])
1310
1311 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
1312                                    (unsigned_fix "fixuns_trunc")])
1313
1314 ;; Optab prefix for sign/zero-extending operations
1315 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1316                             (div "") (udiv "u")
1317                             (fix "") (unsigned_fix "u")
1318                             (float "s") (unsigned_float "u")
1319                             (ss_plus "s") (us_plus "u")
1320                             (ss_minus "s") (us_minus "u")])
1321
1322 ;; Similar for the instruction mnemonics
1323 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1324                          (lshiftrt "lsr") (rotatert "ror")])
1325
1326 ;; Map shift operators onto underlying bit-field instructions
1327 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1328                            (lshiftrt "ubfx") (rotatert "extr")])
1329
1330 ;; Logical operator instruction mnemonics
1331 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1332
1333 ;; Operation names for negate and bitwise complement.
1334 (define_code_attr neg_not_op [(neg "neg") (not "not")])
1335
1336 ;; Similar, but when the second operand is inverted.
1337 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1338
1339 ;; Similar, but when both operands are inverted.
1340 (define_code_attr logical_nn [(and "nor") (ior "nand")])
1341
1342 ;; Sign- or zero-extending data-op
1343 (define_code_attr su [(sign_extend "s") (zero_extend "u")
1344                       (sign_extract "s") (zero_extract "u")
1345                       (fix "s") (unsigned_fix "u")
1346                       (div "s") (udiv "u")
1347                       (smax "s") (umax "u")
1348                       (smin "s") (umin "u")])
1349
1350 ;; Whether a shift is left or right.
1351 (define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1352
1353 ;; Emit conditional branch instructions.
1354 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1355
1356 ;; Emit cbz/cbnz depending on comparison type.
1357 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1358
1359 ;; Emit inverted cbz/cbnz depending on comparison type.
1360 (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1361
1362 ;; Emit tbz/tbnz depending on comparison type.
1363 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1364
1365 ;; Emit inverted tbz/tbnz depending on comparison type.
1366 (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1367
1368 ;; Max/min attributes.
1369 (define_code_attr maxmin [(smax "max")
1370                           (smin "min")
1371                           (umax "max")
1372                           (umin "min")])
1373
1374 ;; MLA/MLS attributes.
1375 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
1376
1377 ;; Atomic operations
1378 (define_code_attr atomic_optab
1379   [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1380
1381 (define_code_attr atomic_op_operand
1382   [(ior "aarch64_logical_operand")
1383    (xor "aarch64_logical_operand")
1384    (and "aarch64_logical_operand")
1385    (plus "aarch64_plus_operand")
1386    (minus "aarch64_plus_operand")])
1387
1388 ;; Constants acceptable for atomic operations.
1389 ;; This definition must appear in this file before the iterators it refers to.
1390 (define_code_attr const_atomic
1391  [(plus "IJ") (minus "IJ")
1392   (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1393   (and "<lconst_atomic>")])
1394
1395 ;; Attribute to describe constants acceptable in atomic logical operations
1396 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1397
1398 ;; The integer SVE instruction that implements an rtx code.
1399 (define_code_attr sve_int_op [(plus "add")
1400                               (minus "sub")
1401                               (mult "mul")
1402                               (div "sdiv")
1403                               (udiv "udiv")
1404                               (abs "abs")
1405                               (neg "neg")
1406                               (smin "smin")
1407                               (smax "smax")
1408                               (umin "umin")
1409                               (umax "umax")
1410                               (and "and")
1411                               (ior "orr")
1412                               (xor "eor")
1413                               (not "not")
1414                               (popcount "cnt")])
1415
1416 (define_code_attr sve_int_op_rev [(plus "add")
1417                                   (minus "subr")
1418                                   (mult "mul")
1419                                   (div "sdivr")
1420                                   (udiv "udivr")
1421                                   (smin "smin")
1422                                   (smax "smax")
1423                                   (umin "umin")
1424                                   (umax "umax")
1425                                   (and "and")
1426                                   (ior "orr")
1427                                   (xor "eor")])
1428
1429 ;; The floating-point SVE instruction that implements an rtx code.
1430 (define_code_attr sve_fp_op [(plus "fadd")
1431                              (minus "fsub")
1432                              (mult "fmul")
1433                              (neg "fneg")
1434                              (abs "fabs")
1435                              (sqrt "fsqrt")])
1436
1437 ;; The SVE immediate constraint to use for an rtl code.
1438 (define_code_attr sve_imm_con [(eq "vsc")
1439                                (ne "vsc")
1440                                (lt "vsc")
1441                                (ge "vsc")
1442                                (le "vsc")
1443                                (gt "vsc")
1444                                (ltu "vsd")
1445                                (leu "vsd")
1446                                (geu "vsd")
1447                                (gtu "vsd")])
1448
1449 ;; -------------------------------------------------------------------
1450 ;; Int Iterators.
1451 ;; -------------------------------------------------------------------
1452
1453 ;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1454 (define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1455
1456 ;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1457 (define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1458
1459 ;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1460 (define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1461
1462 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1463                               UNSPEC_SMAXV UNSPEC_SMINV])
1464
1465 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1466                                UNSPEC_FMAXNMV UNSPEC_FMINNMV])
1467
1468 (define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV])
1469
1470 (define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1471
1472 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1473                               UNSPEC_SRHADD UNSPEC_URHADD
1474                               UNSPEC_SHSUB UNSPEC_UHSUB
1475                               UNSPEC_SRHSUB UNSPEC_URHSUB])
1476
1477 (define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
1478
1479 (define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
1480
1481 (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
1482
1483 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1484                                UNSPEC_SUBHN UNSPEC_RSUBHN])
1485
1486 (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1487                                 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1488
1489 (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1490                                   UNSPEC_FMAXNM UNSPEC_FMINNM])
1491
1492 (define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP])
1493
1494 (define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716])
1495
1496 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1497
1498 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1499
1500 (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1501
1502 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1503                            UNSPEC_SRSHL UNSPEC_URSHL])
1504
1505 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1506
1507 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1508                             UNSPEC_SQRSHL UNSPEC_UQRSHL])
1509
1510 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1511                              UNSPEC_SRSRA UNSPEC_URSRA])
1512
1513 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1514                               UNSPEC_SSRI UNSPEC_USRI])
1515
1516
1517 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1518
1519 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1520
1521 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1522                                UNSPEC_SQSHRN UNSPEC_UQSHRN
1523                                UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1524
1525 (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1526
1527 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1528                               UNSPEC_TRN1 UNSPEC_TRN2
1529                               UNSPEC_UZP1 UNSPEC_UZP2])
1530
1531 (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1532                                     UNSPEC_UZP1 UNSPEC_UZP2])
1533
1534 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1535
1536 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
1537                              UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1538                              UNSPEC_FRINTA])
1539
1540 (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
1541                             UNSPEC_FRINTA UNSPEC_FRINTN])
1542
1543 (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1544 (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1545
1546 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1547                           UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1548                           UNSPEC_CRC32CW UNSPEC_CRC32CX])
1549
1550 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1551 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1552
1553 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1554
1555 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1556
1557 (define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1558
1559 (define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1560                                    UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1561
1562 (define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1563
1564 ;; Iterators for fp16 operations
1565
1566 (define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1567
1568 (define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1569
1570 (define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1571                              UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1572
1573 (define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1574
1575 (define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1576
1577 (define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_ADD UNSPEC_COND_SUB
1578                                          UNSPEC_COND_MUL UNSPEC_COND_DIV
1579                                          UNSPEC_COND_MAX UNSPEC_COND_MIN])
1580
1581 (define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
1582                                           UNSPEC_COND_FMLS
1583                                           UNSPEC_COND_FNMLA
1584                                           UNSPEC_COND_FNMLS])
1585
1586 (define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE
1587                                       UNSPEC_COND_EQ UNSPEC_COND_NE
1588                                       UNSPEC_COND_GE UNSPEC_COND_GT])
1589
1590 ;; Iterators for atomic operations.
1591
1592 (define_int_iterator ATOMIC_LDOP
1593  [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1594   UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1595
1596 (define_int_attr atomic_ldop
1597  [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1598   (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1599
1600 (define_int_attr atomic_ldoptab
1601  [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic")
1602   (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1603
1604 ;; -------------------------------------------------------------------
1605 ;; Int Iterators Attributes.
1606 ;; -------------------------------------------------------------------
1607
1608 ;; The optab associated with an operation.  Note that for ANDF, IORF
1609 ;; and XORF, the optab pattern is not actually defined; we just use this
1610 ;; name for consistency with the integer patterns.
1611 (define_int_attr optab [(UNSPEC_ANDF "and")
1612                         (UNSPEC_IORF "ior")
1613                         (UNSPEC_XORF "xor")
1614                         (UNSPEC_ANDV "and")
1615                         (UNSPEC_IORV "ior")
1616                         (UNSPEC_XORV "xor")
1617                         (UNSPEC_COND_ADD "add")
1618                         (UNSPEC_COND_SUB "sub")
1619                         (UNSPEC_COND_MUL "mul")
1620                         (UNSPEC_COND_DIV "div")
1621                         (UNSPEC_COND_MAX "smax")
1622                         (UNSPEC_COND_MIN "smin")
1623                         (UNSPEC_COND_FMLA "fma")
1624                         (UNSPEC_COND_FMLS "fnma")
1625                         (UNSPEC_COND_FNMLA "fnms")
1626                         (UNSPEC_COND_FNMLS "fms")])
1627
1628 (define_int_attr  maxmin_uns [(UNSPEC_UMAXV "umax")
1629                               (UNSPEC_UMINV "umin")
1630                               (UNSPEC_SMAXV "smax")
1631                               (UNSPEC_SMINV "smin")
1632                               (UNSPEC_FMAX  "smax_nan")
1633                               (UNSPEC_FMAXNMV "smax")
1634                               (UNSPEC_FMAXV "smax_nan")
1635                               (UNSPEC_FMIN "smin_nan")
1636                               (UNSPEC_FMINNMV "smin")
1637                               (UNSPEC_FMINV "smin_nan")
1638                               (UNSPEC_FMAXNM "fmax")
1639                               (UNSPEC_FMINNM "fmin")])
1640
1641 (define_int_attr  maxmin_uns_op [(UNSPEC_UMAXV "umax")
1642                                  (UNSPEC_UMINV "umin")
1643                                  (UNSPEC_SMAXV "smax")
1644                                  (UNSPEC_SMINV "smin")
1645                                  (UNSPEC_FMAX "fmax")
1646                                  (UNSPEC_FMAXNMV "fmaxnm")
1647                                  (UNSPEC_FMAXV "fmax")
1648                                  (UNSPEC_FMIN "fmin")
1649                                  (UNSPEC_FMINNMV "fminnm")
1650                                  (UNSPEC_FMINV "fmin")
1651                                  (UNSPEC_FMAXNM "fmaxnm")
1652                                  (UNSPEC_FMINNM "fminnm")])
1653
1654 (define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv")
1655                                (UNSPEC_IORV "orv")
1656                                (UNSPEC_XORV "eorv")])
1657
1658 ;; The SVE logical instruction that implements an unspec.
1659 (define_int_attr logicalf_op [(UNSPEC_ANDF "and")
1660                               (UNSPEC_IORF "orr")
1661                               (UNSPEC_XORF "eor")])
1662
1663 ;; "s" for signed operations and "u" for unsigned ones.
1664 (define_int_attr su [(UNSPEC_UNPACKSHI "s")
1665                      (UNSPEC_UNPACKUHI "u")
1666                      (UNSPEC_UNPACKSLO "s")
1667                      (UNSPEC_UNPACKULO "u")
1668                      (UNSPEC_SMUL_HIGHPART "s")
1669                      (UNSPEC_UMUL_HIGHPART "u")])
1670
1671 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1672                       (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1673                       (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1674                       (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1675                       (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
1676                       (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
1677                       (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
1678                       (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
1679                       (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1680                       (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1681                       (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1682                       (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1683                       (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1684                       (UNSPEC_SSLI  "s") (UNSPEC_USLI  "u")
1685                       (UNSPEC_SSRI  "s") (UNSPEC_USRI  "u")
1686                       (UNSPEC_USRA  "u") (UNSPEC_SSRA  "s")
1687                       (UNSPEC_URSRA  "ur") (UNSPEC_SRSRA  "sr")
1688                       (UNSPEC_URSHR  "ur") (UNSPEC_SRSHR  "sr")
1689                       (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL   "s")
1690                       (UNSPEC_UQSHL  "u")
1691                       (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1692                       (UNSPEC_SQSHRN "s")  (UNSPEC_UQSHRN "u")
1693                       (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1694                       (UNSPEC_USHL  "u")   (UNSPEC_SSHL  "s")
1695                       (UNSPEC_USHLL  "u")  (UNSPEC_SSHLL "s")
1696                       (UNSPEC_URSHL  "ur") (UNSPEC_SRSHL  "sr")
1697                       (UNSPEC_UQRSHL  "u") (UNSPEC_SQRSHL  "s")
1698                       (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
1699 ])
1700
1701 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1702                     (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1703                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
1704                     (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1705                     (UNSPEC_SQSHL   "")  (UNSPEC_UQSHL  "")
1706                     (UNSPEC_SQRSHL   "r")(UNSPEC_UQRSHL  "r")
1707 ])
1708
1709 (define_int_attr lr [(UNSPEC_SSLI  "l") (UNSPEC_USLI  "l")
1710                      (UNSPEC_SSRI  "r") (UNSPEC_USRI  "r")])
1711
1712 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1713                     (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1714                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
1715                     (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
1716                     (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
1717                     (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
1718
1719 (define_int_attr addsub [(UNSPEC_SHADD "add")
1720                          (UNSPEC_UHADD "add")
1721                          (UNSPEC_SRHADD "add")
1722                          (UNSPEC_URHADD "add")
1723                          (UNSPEC_SHSUB "sub")
1724                          (UNSPEC_UHSUB "sub")
1725                          (UNSPEC_SRHSUB "sub")
1726                          (UNSPEC_URHSUB "sub")
1727                          (UNSPEC_ADDHN "add")
1728                          (UNSPEC_SUBHN "sub")
1729                          (UNSPEC_RADDHN "add")
1730                          (UNSPEC_RSUBHN "sub")
1731                          (UNSPEC_ADDHN2 "add")
1732                          (UNSPEC_SUBHN2 "sub")
1733                          (UNSPEC_RADDHN2 "add")
1734                          (UNSPEC_RSUBHN2 "sub")])
1735
1736 (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1737                            (UNSPEC_SSRI "offset_")
1738                            (UNSPEC_USRI "offset_")])
1739
1740 ;; Standard pattern names for floating-point rounding instructions.
1741 (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1742                                 (UNSPEC_FRINTP "ceil")
1743                                 (UNSPEC_FRINTM "floor")
1744                                 (UNSPEC_FRINTI "nearbyint")
1745                                 (UNSPEC_FRINTX "rint")
1746                                 (UNSPEC_FRINTA "round")
1747                                 (UNSPEC_FRINTN "frintn")])
1748
1749 ;; frint suffix for floating-point rounding instructions.
1750 (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1751                                (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
1752                                (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1753                                (UNSPEC_FRINTN "n")])
1754
1755 (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
1756                                (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1757                                (UNSPEC_FRINTN "frintn")])
1758
1759 (define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1760                                   (UNSPEC_UCVTF "ucvtf")
1761                                   (UNSPEC_FCVTZS "fcvtzs")
1762                                   (UNSPEC_FCVTZU "fcvtzu")])
1763
1764 ;; Pointer authentication mnemonic prefix.
1765 (define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci")
1766                                     (UNSPEC_AUTISP "auti")
1767                                     (UNSPEC_PACI1716 "paci")
1768                                     (UNSPEC_AUTI1716 "auti")])
1769
1770 ;; Pointer authentication HINT number for NOP space instructions using A Key.
1771 (define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25")
1772                                     (UNSPEC_AUTISP "29")
1773                                     (UNSPEC_PACI1716 "8")
1774                                     (UNSPEC_AUTI1716 "12")])
1775
1776 (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1777                             (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1778                             (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1779
1780 ; op code for REV instructions (size within which elements are reversed).
1781 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1782                          (UNSPEC_REV16 "16")])
1783
1784 (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1785                             (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
1786                             (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")
1787                             (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
1788                             (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
1789
1790 ;; Return true if the associated optab refers to the high-numbered lanes,
1791 ;; false if it refers to the low-numbered lanes.  The convention is for
1792 ;; "hi" to refer to the low-numbered lanes (the first ones in memory)
1793 ;; for big-endian.
1794 (define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
1795                                  (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
1796                                  (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
1797                                  (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
1798
1799 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1800                         (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1801                         (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1802                         (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1803
1804 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1805                         (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1806                         (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1807                         (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1808
1809 (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1810 (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
1811
1812 (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1813                           (UNSPEC_SHA1M "m")])
1814
1815 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
1816
1817 (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
1818
1819 (define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
1820
1821 (define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
1822                            (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
1823
1824 (define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
1825
1826 (define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
1827                           (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
1828
1829 ;; The condition associated with an UNSPEC_COND_<xx>.
1830 (define_int_attr cmp_op [(UNSPEC_COND_LT "lt")
1831                          (UNSPEC_COND_LE "le")
1832                          (UNSPEC_COND_EQ "eq")
1833                          (UNSPEC_COND_NE "ne")
1834                          (UNSPEC_COND_GE "ge")
1835                          (UNSPEC_COND_GT "gt")])
1836
1837 (define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd")
1838                             (UNSPEC_COND_SUB "fsub")
1839                             (UNSPEC_COND_MUL "fmul")
1840                             (UNSPEC_COND_DIV "fdiv")
1841                             (UNSPEC_COND_MAX "fmaxnm")
1842                             (UNSPEC_COND_MIN "fminnm")])
1843
1844 (define_int_attr sve_fp_op_rev [(UNSPEC_COND_ADD "fadd")
1845                                 (UNSPEC_COND_SUB "fsubr")
1846                                 (UNSPEC_COND_MUL "fmul")
1847                                 (UNSPEC_COND_DIV "fdivr")
1848                                 (UNSPEC_COND_MAX "fmaxnm")
1849                                 (UNSPEC_COND_MIN "fminnm")])
1850
1851 (define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
1852                               (UNSPEC_COND_FMLS "fmls")
1853                               (UNSPEC_COND_FNMLA "fnmla")
1854                               (UNSPEC_COND_FNMLS "fnmls")])
1855
1856 (define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
1857                               (UNSPEC_COND_FMLS "fmsb")
1858                               (UNSPEC_COND_FNMLA "fnmad")
1859                               (UNSPEC_COND_FNMLS "fnmsb")])
1860
1861 (define_int_attr commutative [(UNSPEC_COND_ADD "true")
1862                               (UNSPEC_COND_SUB "false")
1863                               (UNSPEC_COND_MUL "true")
1864                               (UNSPEC_COND_DIV "false")
1865                               (UNSPEC_COND_MIN "true")
1866                               (UNSPEC_COND_MAX "true")])