gcc/config/aarch64/iterators.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2016 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; -------------------------------------------------------------------
  22 ;; Mode Iterators
  23 ;; -------------------------------------------------------------------
  24
  25
  26 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
  27 (define_mode_iterator GPI [SI DI])
  28
  29 ;; Iterator for QI and HI modes
  30 (define_mode_iterator SHORT [QI HI])
  31
  32 ;; Iterator for all integer modes (up to 64-bit)
  33 (define_mode_iterator ALLI [QI HI SI DI])
  34
  35 ;; Iterator for all integer modes that can be extended (up to 64-bit)
  36 (define_mode_iterator ALLX [QI HI SI])
  37
  38 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
  39 (define_mode_iterator GPF [SF DF])
  40
  41 ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
  42 (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
  43
  44 ;; Double vector modes.
  45 (define_mode_iterator VDF [V2SF V4HF])
  46
  47 ;; Iterator for all scalar floating point modes (SF, DF and TF)
  48 (define_mode_iterator GPF_TF [SF DF TF])
  49
  50 ;; Integer vector modes.
  51 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
  52
  53 ;; vector and scalar, 64 & 128-bit container, all integer modes
  54 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
  55
  56 ;; vector and scalar, 64 & 128-bit container: all vector integer modes;
  57 ;; 64-bit scalar integer mode
  58 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
  59
  60 ;; Double vector modes.
  61 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
  62
  63 ;; vector, 64-bit container, all integer modes
  64 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
  65
  66 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
  67 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
  68
  69 ;; Quad vector modes.
  70 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
  71
  72 ;; VQ without 2 element modes.
  73 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
  74
  75 ;; Quad vector with only 2 element modes.
  76 (define_mode_iterator VQ_2E [V2DI V2DF])
  77
  78 ;; This mode iterator allows :P to be used for patterns that operate on
  79 ;; addresses in different modes.  In LP64, only DI will match, while in
  80 ;; ILP32, either can match.
  81 (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
  82                          (DI "ptr_mode == DImode || Pmode == DImode")])
  83
  84 ;; This mode iterator allows :PTR to be used for patterns that operate on
  85 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
  86 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
  87
  88 ;; Vector Float modes suitable for moving, loading and storing.
  89 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
  90
  91 ;; Vector Float modes, barring HF modes.
  92 (define_mode_iterator VDQF [V2SF V4SF V2DF])
  93
  94 ;; Vector Float modes, and DF.
  95 (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF])
  96
  97 ;; Vector single Float modes.
  98 (define_mode_iterator VDQSF [V2SF V4SF])
  99
 100 ;; Quad vector Float modes with half/single elements.
 101 (define_mode_iterator VQ_HSF [V8HF V4SF])
 102
 103 ;; Modes suitable to use as the return type of a vcond expression.
 104 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
 105
 106 ;; All Float modes.
 107 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
 108
 109 ;; Vector Float modes with 2 elements.
 110 (define_mode_iterator V2F [V2SF V2DF])
 111
 112 ;; All vector modes on which we support any arithmetic operations.
 113 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
 114
 115 ;; All vector modes suitable for moving, loading, and storing.
 116 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
 117                                 V4HF V8HF V2SF V4SF V2DF])
 118
 119 ;; All vector modes barring HF modes, plus DI.
 120 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
 121
 122 ;; All vector modes and DI.
 123 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
 124                                   V4HF V8HF V2SF V4SF V2DF DI])
 125
 126 ;; All vector modes, plus DI and DF.
 127 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
 128                                V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
 129
 130 ;; Vector modes for Integer reduction across lanes.
 131 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
 132
 133 ;; Vector modes(except V2DI) for Integer reduction across lanes.
 134 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
 135
 136 ;; All double integer narrow-able modes.
 137 (define_mode_iterator VDN [V4HI V2SI DI])
 138
 139 ;; All quad integer narrow-able modes.
 140 (define_mode_iterator VQN [V8HI V4SI V2DI])
 141
 142 ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
 143 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
 144
 145 ;; All quad integer widen-able modes.
 146 (define_mode_iterator VQW [V16QI V8HI V4SI])
 147
 148 ;; Double vector modes for combines.
 149 (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
 150
 151 ;; Vector modes except double int.
 152 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 153
 154 ;; Vector modes for S type.
 155 (define_mode_iterator VDQ_SI [V2SI V4SI])
 156
 157 ;; Vector modes for Q and H types.
 158 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
 159
 160 ;; Vector modes for H and S types.
 161 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
 162
 163 ;; Vector modes for H, S and D types.
 164 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
 165
 166 ;; Vector and scalar integer modes for H and S
 167 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
 168
 169 ;; Vector and scalar 64-bit container: 16, 32-bit integer modes
 170 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
 171
 172 ;; Vector 64-bit container: 16, 32-bit integer modes
 173 (define_mode_iterator VD_HSI [V4HI V2SI])
 174
 175 ;; Scalar 64-bit container: 16, 32-bit integer modes
 176 (define_mode_iterator SD_HSI [HI SI])
 177
 178 ;; Vector 64-bit container: 16, 32-bit integer modes
 179 (define_mode_iterator VQ_HSI [V8HI V4SI])
 180
 181 ;; All byte modes.
 182 (define_mode_iterator VB [V8QI V16QI])
 183
 184 ;; 2 and 4 lane SI modes.
 185 (define_mode_iterator VS [V2SI V4SI])
 186
 187 (define_mode_iterator TX [TI TF])
 188
 189 ;; Opaque structure modes.
 190 (define_mode_iterator VSTRUCT [OI CI XI])
 191
 192 ;; Double scalar modes
 193 (define_mode_iterator DX [DI DF])
 194
 195 ;; Modes available for <f>mul lane operations.
 196 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 197
 198 ;; Modes available for <f>mul lane operations changing lane count.
 199 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
 200
 201 ;; ------------------------------------------------------------------
 202 ;; Unspec enumerations for Advance SIMD. These could well go into
 203 ;; aarch64.md but for their use in int_iterators here.
 204 ;; ------------------------------------------------------------------
 205
 206 (define_c_enum "unspec"
 207  [
 208     UNSPEC_ASHIFT_SIGNED        ; Used in aarch-simd.md.
 209     UNSPEC_ASHIFT_UNSIGNED      ; Used in aarch64-simd.md.
 210     UNSPEC_ABS          ; Used in aarch64-simd.md.
 211     UNSPEC_FMAX         ; Used in aarch64-simd.md.
 212     UNSPEC_FMAXNMV      ; Used in aarch64-simd.md.
 213     UNSPEC_FMAXV        ; Used in aarch64-simd.md.
 214     UNSPEC_FMIN         ; Used in aarch64-simd.md.
 215     UNSPEC_FMINNMV      ; Used in aarch64-simd.md.
 216     UNSPEC_FMINV        ; Used in aarch64-simd.md.
 217     UNSPEC_FADDV        ; Used in aarch64-simd.md.
 218     UNSPEC_ADDV         ; Used in aarch64-simd.md.
 219     UNSPEC_SMAXV        ; Used in aarch64-simd.md.
 220     UNSPEC_SMINV        ; Used in aarch64-simd.md.
 221     UNSPEC_UMAXV        ; Used in aarch64-simd.md.
 222     UNSPEC_UMINV        ; Used in aarch64-simd.md.
 223     UNSPEC_SHADD        ; Used in aarch64-simd.md.
 224     UNSPEC_UHADD        ; Used in aarch64-simd.md.
 225     UNSPEC_SRHADD       ; Used in aarch64-simd.md.
 226     UNSPEC_URHADD       ; Used in aarch64-simd.md.
 227     UNSPEC_SHSUB        ; Used in aarch64-simd.md.
 228     UNSPEC_UHSUB        ; Used in aarch64-simd.md.
 229     UNSPEC_SRHSUB       ; Used in aarch64-simd.md.
 230     UNSPEC_URHSUB       ; Used in aarch64-simd.md.
 231     UNSPEC_ADDHN        ; Used in aarch64-simd.md.
 232     UNSPEC_RADDHN       ; Used in aarch64-simd.md.
 233     UNSPEC_SUBHN        ; Used in aarch64-simd.md.
 234     UNSPEC_RSUBHN       ; Used in aarch64-simd.md.
 235     UNSPEC_ADDHN2       ; Used in aarch64-simd.md.
 236     UNSPEC_RADDHN2      ; Used in aarch64-simd.md.
 237     UNSPEC_SUBHN2       ; Used in aarch64-simd.md.
 238     UNSPEC_RSUBHN2      ; Used in aarch64-simd.md.
 239     UNSPEC_SQDMULH      ; Used in aarch64-simd.md.
 240     UNSPEC_SQRDMULH     ; Used in aarch64-simd.md.
 241     UNSPEC_PMUL         ; Used in aarch64-simd.md.
 242     UNSPEC_FMULX        ; Used in aarch64-simd.md.
 243     UNSPEC_USQADD       ; Used in aarch64-simd.md.
 244     UNSPEC_SUQADD       ; Used in aarch64-simd.md.
 245     UNSPEC_SQXTUN       ; Used in aarch64-simd.md.
 246     UNSPEC_SQXTN        ; Used in aarch64-simd.md.
 247     UNSPEC_UQXTN        ; Used in aarch64-simd.md.
 248     UNSPEC_SSRA         ; Used in aarch64-simd.md.
 249     UNSPEC_USRA         ; Used in aarch64-simd.md.
 250     UNSPEC_SRSRA        ; Used in aarch64-simd.md.
 251     UNSPEC_URSRA        ; Used in aarch64-simd.md.
 252     UNSPEC_SRSHR        ; Used in aarch64-simd.md.
 253     UNSPEC_URSHR        ; Used in aarch64-simd.md.
 254     UNSPEC_SQSHLU       ; Used in aarch64-simd.md.
 255     UNSPEC_SQSHL        ; Used in aarch64-simd.md.
 256     UNSPEC_UQSHL        ; Used in aarch64-simd.md.
 257     UNSPEC_SQSHRUN      ; Used in aarch64-simd.md.
 258     UNSPEC_SQRSHRUN     ; Used in aarch64-simd.md.
 259     UNSPEC_SQSHRN       ; Used in aarch64-simd.md.
 260     UNSPEC_UQSHRN       ; Used in aarch64-simd.md.
 261     UNSPEC_SQRSHRN      ; Used in aarch64-simd.md.
 262     UNSPEC_UQRSHRN      ; Used in aarch64-simd.md.
 263     UNSPEC_SSHL         ; Used in aarch64-simd.md.
 264     UNSPEC_USHL         ; Used in aarch64-simd.md.
 265     UNSPEC_SRSHL        ; Used in aarch64-simd.md.
 266     UNSPEC_URSHL        ; Used in aarch64-simd.md.
 267     UNSPEC_SQRSHL       ; Used in aarch64-simd.md.
 268     UNSPEC_UQRSHL       ; Used in aarch64-simd.md.
 269     UNSPEC_SSLI         ; Used in aarch64-simd.md.
 270     UNSPEC_USLI         ; Used in aarch64-simd.md.
 271     UNSPEC_SSRI         ; Used in aarch64-simd.md.
 272     UNSPEC_USRI         ; Used in aarch64-simd.md.
 273     UNSPEC_SSHLL        ; Used in aarch64-simd.md.
 274     UNSPEC_USHLL        ; Used in aarch64-simd.md.
 275     UNSPEC_ADDP         ; Used in aarch64-simd.md.
 276     UNSPEC_TBL          ; Used in vector permute patterns.
 277     UNSPEC_TBX          ; Used in vector permute patterns.
 278     UNSPEC_CONCAT       ; Used in vector permute patterns.
 279     UNSPEC_ZIP1         ; Used in vector permute patterns.
 280     UNSPEC_ZIP2         ; Used in vector permute patterns.
 281     UNSPEC_UZP1         ; Used in vector permute patterns.
 282     UNSPEC_UZP2         ; Used in vector permute patterns.
 283     UNSPEC_TRN1         ; Used in vector permute patterns.
 284     UNSPEC_TRN2         ; Used in vector permute patterns.
 285     UNSPEC_EXT          ; Used in aarch64-simd.md.
 286     UNSPEC_REV64        ; Used in vector reverse patterns (permute).
 287     UNSPEC_REV32        ; Used in vector reverse patterns (permute).
 288     UNSPEC_REV16        ; Used in vector reverse patterns (permute).
 289     UNSPEC_AESE         ; Used in aarch64-simd.md.
 290     UNSPEC_AESD         ; Used in aarch64-simd.md.
 291     UNSPEC_AESMC        ; Used in aarch64-simd.md.
 292     UNSPEC_AESIMC       ; Used in aarch64-simd.md.
 293     UNSPEC_SHA1C        ; Used in aarch64-simd.md.
 294     UNSPEC_SHA1M        ; Used in aarch64-simd.md.
 295     UNSPEC_SHA1P        ; Used in aarch64-simd.md.
 296     UNSPEC_SHA1H        ; Used in aarch64-simd.md.
 297     UNSPEC_SHA1SU0      ; Used in aarch64-simd.md.
 298     UNSPEC_SHA1SU1      ; Used in aarch64-simd.md.
 299     UNSPEC_SHA256H      ; Used in aarch64-simd.md.
 300     UNSPEC_SHA256H2     ; Used in aarch64-simd.md.
 301     UNSPEC_SHA256SU0    ; Used in aarch64-simd.md.
 302     UNSPEC_SHA256SU1    ; Used in aarch64-simd.md.
 303     UNSPEC_PMULL        ; Used in aarch64-simd.md.
 304     UNSPEC_PMULL2       ; Used in aarch64-simd.md.
 305     UNSPEC_REV_REGLIST  ; Used in aarch64-simd.md.
 306     UNSPEC_VEC_SHR      ; Used in aarch64-simd.md.
 307     UNSPEC_SQRDMLAH     ; Used in aarch64-simd.md.
 308     UNSPEC_SQRDMLSH     ; Used in aarch64-simd.md.
 309     UNSPEC_FMAXNM       ; Used in aarch64-simd.md.
 310     UNSPEC_FMINNM       ; Used in aarch64-simd.md.
 311 ])
 312
 313 ;; ------------------------------------------------------------------
 314 ;; Unspec enumerations for Atomics.  They are here so that they can be
 315 ;; used in the int_iterators for atomic operations.
 316 ;; ------------------------------------------------------------------
 317
 318 (define_c_enum "unspecv"
 319  [
 320     UNSPECV_LX                  ; Represent a load-exclusive.
 321     UNSPECV_SX                  ; Represent a store-exclusive.
 322     UNSPECV_LDA                 ; Represent an atomic load or load-acquire.
 323     UNSPECV_STL                 ; Represent an atomic store or store-release.
 324     UNSPECV_ATOMIC_CMPSW        ; Represent an atomic compare swap.
 325     UNSPECV_ATOMIC_EXCHG        ; Represent an atomic exchange.
 326     UNSPECV_ATOMIC_CAS          ; Represent an atomic CAS.
 327     UNSPECV_ATOMIC_SWP          ; Represent an atomic SWP.
 328     UNSPECV_ATOMIC_OP           ; Represent an atomic operation.
 329     UNSPECV_ATOMIC_LDOP         ; Represent an atomic load-operation
 330     UNSPECV_ATOMIC_LDOP_OR      ; Represent an atomic load-or
 331     UNSPECV_ATOMIC_LDOP_BIC     ; Represent an atomic load-bic
 332     UNSPECV_ATOMIC_LDOP_XOR     ; Represent an atomic load-xor
 333     UNSPECV_ATOMIC_LDOP_PLUS    ; Represent an atomic load-add
 334 ])
 335
 336 ;; -------------------------------------------------------------------
 337 ;; Mode attributes
 338 ;; -------------------------------------------------------------------
 339
 340 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
 341 ;; 32-bit version and "%x0" in the 64-bit version.
 342 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
 343
 344 ;; For inequal width int to float conversion
 345 (define_mode_attr w1 [(SF "w") (DF "x")])
 346 (define_mode_attr w2 [(SF "x") (DF "w")])
 347
 348 ;; For constraints used in scalar immediate vector moves
 349 (define_mode_attr hq [(HI "h") (QI "q")])
 350
 351 ;; For scalar usage of vector/FP registers
 352 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
 353                     (SF "s") (DF "d")
 354                     (V8QI "") (V16QI "")
 355                     (V4HI "") (V8HI "")
 356                     (V2SI "") (V4SI  "")
 357                     (V2DI "") (V2SF "")
 358                     (V4SF "") (V2DF "")])
 359
 360 ;; For scalar usage of vector/FP registers, narrowing
 361 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
 362                     (V8QI "") (V16QI "")
 363                     (V4HI "") (V8HI "")
 364                     (V2SI "") (V4SI  "")
 365                     (V2DI "") (V2SF "")
 366                     (V4SF "") (V2DF "")])
 367
 368 ;; For scalar usage of vector/FP registers, widening
 369 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
 370                     (V8QI "") (V16QI "")
 371                     (V4HI "") (V8HI "")
 372                     (V2SI "") (V4SI  "")
 373                     (V2DI "") (V2SF "")
 374                     (V4SF "") (V2DF "")])
 375
 376 ;; Register Type Name and Vector Arrangement Specifier for when
 377 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
 378 ;; lane 0).
 379 (define_mode_attr rtn [(DI "d") (SI "")])
 380 (define_mode_attr vas [(DI "") (SI ".2s")])
 381
 382 ;; Map a floating point mode to the appropriate register name prefix
 383 (define_mode_attr s [(SF "s") (DF "d")])
 384
 385 ;; Give the length suffix letter for a sign- or zero-extension.
 386 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
 387
 388 ;; Give the number of bits in the mode
 389 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
 390
 391 ;; Give the ordinal of the MSB in the mode
 392 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
 393
 394 ;; Attribute to describe constants acceptable in logical operations
 395 (define_mode_attr lconst [(SI "K") (DI "L")])
 396
 397 ;; Map a mode to a specific constraint character.
 398 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
 399
 400 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
 401                          (V4HI "4h") (V8HI  "8h")
 402                          (V2SI "2s") (V4SI  "4s")
 403                          (DI   "1d") (DF    "1d")
 404                          (V2DI "2d") (V2SF "2s")
 405                          (V4SF "4s") (V2DF "2d")
 406                          (V4HF "4h") (V8HF "8h")])
 407
 408 (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
 409                             (V4SI "32") (V2DI "64")])
 410
 411 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
 412                          (V4HI ".4h") (V8HI  ".8h")
 413                          (V2SI ".2s") (V4SI  ".4s")
 414                          (V2DI ".2d") (V4HF ".4h")
 415                          (V8HF ".8h") (V2SF ".2s")
 416                          (V4SF ".4s") (V2DF ".2d")
 417                          (DI   "")    (SI   "")
 418                          (HI   "")    (QI   "")
 419                          (TI   "")    (SF   "")
 420                          (DF   "")])
 421
 422 ;; Register suffix narrowed modes for VQN.
 423 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
 424                            (V2DI ".2s")
 425                            (DI   "")    (SI   "")
 426                            (HI   "")])
 427
 428 ;; Mode-to-individual element type mapping.
 429 (define_mode_attr Vetype [(V8QI "b") (V16QI "b")
 430                           (V4HI "h") (V8HI  "h")
 431                           (V2SI "s") (V4SI  "s")
 432                           (V2DI "d") (V4HF "h")
 433                           (V8HF "h") (V2SF  "s")
 434                           (V4SF "s") (V2DF  "d")
 435                           (SF   "s") (DF  "d")
 436                           (QI "b")   (HI "h")
 437                           (SI "s")   (DI "d")])
 438
 439 ;; Mode-to-bitwise operation type mapping.
 440 (define_mode_attr Vbtype [(V8QI "8b")  (V16QI "16b")
 441                           (V4HI "8b") (V8HI  "16b")
 442                           (V2SI "8b") (V4SI  "16b")
 443                           (V2DI "16b") (V4HF "8b")
 444                           (V8HF "16b") (V2SF  "8b")
 445                           (V4SF "16b") (V2DF  "16b")
 446                           (DI   "8b")  (DF    "8b")
 447                           (SI   "8b")])
 448
 449 ;; Define element mode for each vector mode.
 450 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
 451                         (V4HI "HI") (V8HI "HI")
 452                         (V2SI "SI") (V4SI "SI")
 453                         (DI "DI")   (V2DI "DI")
 454                         (V4HF "HF") (V8HF "HF")
 455                         (V2SF "SF") (V4SF "SF")
 456                         (V2DF "DF") (DF "DF")
 457                         (SI   "SI") (HI   "HI")
 458                         (QI   "QI")])
 459
 460 ;; 64-bit container modes the inner or scalar source mode.
 461 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
 462                          (V4HI "V4HI") (V8HI "V4HI")
 463                          (V2SI "V2SI") (V4SI "V2SI")
 464                          (DI   "DI") (V2DI "DI")
 465                          (V2SF "V2SF") (V4SF "V2SF")
 466                          (V2DF "DF")])
 467
 468 ;; 128-bit container modes the inner or scalar source mode.
 469 (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
 470                          (V4HI "V8HI") (V8HI "V8HI")
 471                          (V2SI "V4SI") (V4SI "V4SI")
 472                          (DI   "V2DI") (V2DI "V2DI")
 473                          (V4HF "V8HF") (V8HF "V8HF")
 474                          (V2SF "V2SF") (V4SF "V4SF")
 475                          (V2DF "V2DF") (SI   "V4SI")
 476                          (HI   "V8HI") (QI   "V16QI")])
 477
 478 ;; Half modes of all vector modes.
 479 (define_mode_attr VHALF [(V8QI "V4QI")  (V16QI "V8QI")
 480                          (V4HI "V2HI")  (V8HI  "V4HI")
 481                          (V2SI "SI")    (V4SI  "V2SI")
 482                          (V2DI "DI")    (V2SF  "SF")
 483                          (V4SF "V2SF")  (V4HF "V2HF")
 484                          (V8HF "V4HF")  (V2DF  "DF")])
 485
 486 ;; Half modes of all vector modes, in lower-case.
 487 (define_mode_attr Vhalf [(V8QI "v4qi")  (V16QI "v8qi")
 488                          (V4HI "v2hi")  (V8HI  "v4hi")
 489                          (V2SI "si")    (V4SI  "v2si")
 490                          (V2DI "di")    (V2SF  "sf")
 491                          (V4SF "v2sf")  (V2DF  "df")])
 492
 493 ;; Double modes of vector modes.
 494 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
 495                         (V4HF "V8HF")
 496                         (V2SI "V4SI")  (V2SF "V4SF")
 497                         (SI   "V2SI")  (DI   "V2DI")
 498                         (DF   "V2DF")])
 499
 500 ;; Register suffix for double-length mode.
 501 (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
 502
 503 ;; Double modes of vector modes (lower case).
 504 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
 505                         (V4HF "v8hf")
 506                         (V2SI "v4si")  (V2SF "v4sf")
 507                         (SI   "v2si")  (DI   "v2di")
 508                         (DF   "v2df")])
 509
 510 ;; Modes with double-width elements.
 511 (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
 512                   (V4HI "V2SI") (V8HI "V4SI")
 513                   (V2SI "DI")   (V4SI "V2DI")])
 514
 515 ;; Narrowed modes for VDN.
 516 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
 517                             (DI   "V2SI")])
 518
 519 ;; Narrowed double-modes for VQN (Used for XTN).
 520 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
 521                             (V2DI "V2SI")
 522                             (DI   "SI")   (SI   "HI")
 523                             (HI   "QI")])
 524
 525 ;; Narrowed quad-modes for VQN (Used for XTN2).
 526 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
 527                              (V2DI "V4SI")])
 528
 529 ;; Register suffix narrowed modes for VQN.
 530 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
 531                           (V2DI "2s")])
 532
 533 ;; Register suffix narrowed modes for VQN.
 534 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
 535                            (V2DI "4s")])
 536
 537 ;; Widened modes of vector modes.
 538 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
 539                          (V2SI "V2DI") (V16QI "V8HI")
 540                          (V8HI "V4SI") (V4SI "V2DI")
 541                          (HI "SI")     (SI "DI")
 542                          (V8HF "V4SF") (V4SF "V2DF")
 543                          (V4HF "V4SF") (V2SF "V2DF")]
 544 )
 545
 546 ;; Widened modes of vector modes, lowercase
 547 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")])
 548
 549 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
 550 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
 551                           (V2SI "2d") (V16QI "8h")
 552                           (V8HI "4s") (V4SI "2d")
 553                           (V8HF "4s") (V4SF "2d")])
 554
 555 ;; Widened mode register suffixes for VDW/VQW.
 556 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
 557                            (V2SI ".2d") (V16QI ".8h")
 558                            (V8HI ".4s") (V4SI ".2d")
 559                            (V4HF ".4s") (V2SF ".2d")
 560                            (SI   "")    (HI   "")])
 561
 562 ;; Lower part register suffixes for VQW/VQ_HSF.
 563 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
 564                              (V4SI "2s") (V8HF "4h")
 565                              (V4SF "2s")])
 566
 567 ;; Define corresponding core/FP element mode for each vector mode.
 568 (define_mode_attr vw   [(V8QI "w") (V16QI "w")
 569                         (V4HI "w") (V8HI "w")
 570                         (V2SI "w") (V4SI "w")
 571                         (DI   "x") (V2DI "x")
 572                         (V2SF "s") (V4SF "s")
 573                         (V2DF "d")])
 574
 575 ;; Corresponding core element mode for each vector mode.  This is a
 576 ;; variation on <vw> mapping FP modes to GP regs.
 577 (define_mode_attr vwcore  [(V8QI "w") (V16QI "w")
 578                            (V4HI "w") (V8HI "w")
 579                            (V2SI "w") (V4SI "w")
 580                            (DI   "x") (V2DI "x")
 581                            (V4HF "w") (V8HF "w")
 582                            (V2SF "w") (V4SF "w")
 583                            (V2DF "x")])
 584
 585 ;; Double vector types for ALLX.
 586 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
 587
 588 ;; Mode of result of comparison operations.
 589 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
 590                                 (V4HI "V4HI") (V8HI  "V8HI")
 591                                 (V2SI "V2SI") (V4SI  "V4SI")
 592                                 (DI   "DI")   (V2DI  "V2DI")
 593                                 (V4HF "V4HI") (V8HF  "V8HI")
 594                                 (V2SF "V2SI") (V4SF  "V4SI")
 595                                 (V2DF "V2DI") (DF    "DI")
 596                                 (SF   "SI")])
 597
 598 ;; Lower case mode of results of comparison operations.
 599 (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
 600                                 (V4HI "v4hi") (V8HI  "v8hi")
 601                                 (V2SI "v2si") (V4SI  "v4si")
 602                                 (DI   "di")   (V2DI  "v2di")
 603                                 (V4HF "v4hi") (V8HF  "v8hi")
 604                                 (V2SF "v2si") (V4SF  "v4si")
 605                                 (V2DF "v2di") (DF    "di")
 606                                 (SF   "si")])
 607
 608 ;; Lower case element modes (as used in shift immediate patterns).
 609 (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
 610                            (V4HI "hi") (V8HI  "hi")
 611                            (V2SI "si") (V4SI  "si")
 612                            (DI   "di") (V2DI  "di")
 613                            (QI   "qi") (HI    "hi")
 614                            (SI   "si")])
 615
 616 ;; Vm for lane instructions is restricted to FP_LO_REGS.
 617 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
 618                        (V2SI "w") (V4SI "w") (SI "w")])
 619
 620 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
 621
 622 ;; This is both the number of Q-Registers needed to hold the corresponding
 623 ;; opaque large integer mode, and the number of elements touched by the
 624 ;; ld..._lane and st..._lane operations.
 625 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
 626
 627 (define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI")
 628                         (V4HF "V16HF")
 629                         (V2SI "V8SI")  (V2SF "V8SF")
 630                         (DI   "V4DI")  (DF   "V4DF")])
 631
 632 (define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI")
 633                         (V4HF "V24HF")
 634                         (V2SI "V12SI")  (V2SF "V12SF")
 635                         (DI   "V6DI")  (DF   "V6DF")])
 636
 637 (define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI")
 638                         (V4HF "V32HF")
 639                         (V2SI "V16SI")  (V2SF "V16SF")
 640                         (DI   "V8DI")  (DF   "V8DF")])
 641
 642 ;; Mode for atomic operation suffixes
 643 (define_mode_attr atomic_sfx
 644   [(QI "b") (HI "h") (SI "") (DI "")])
 645
 646 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") (SF "si") (DF "di")])
 647 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (SF "SI") (DF "DI")])
 648
 649 ;; for the inequal width integer to fp conversions
 650 (define_mode_attr fcvt_iesize [(SF "di") (DF "si")])
 651 (define_mode_attr FCVT_IESIZE [(SF "DI") (DF "SI")])
 652
 653 (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
 654                                 (V4HI "V8HI") (V8HI  "V4HI")
 655                                 (V2SI "V4SI") (V4SI  "V2SI")
 656                                 (DI   "V2DI") (V2DI  "DI")
 657                                 (V2SF "V4SF") (V4SF  "V2SF")
 658                                 (V4HF "V8HF") (V8HF  "V4HF")
 659                                 (DF   "V2DF") (V2DF  "DF")])
 660
 661 (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
 662                                     (V4HI "to_128") (V8HI  "to_64")
 663                                     (V2SI "to_128") (V4SI  "to_64")
 664                                     (DI   "to_128") (V2DI  "to_64")
 665                                     (V4HF "to_128") (V8HF  "to_64")
 666                                     (V2SF "to_128") (V4SF  "to_64")
 667                                     (DF   "to_128") (V2DF  "to_64")])
 668
 669 ;; For certain vector-by-element multiplication instructions we must
 670 ;; constrain the HI cases to use only V0-V15.  This is covered by
 671 ;; the 'x' constraint.  All other modes may use the 'w' constraint.
 672 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
 673                          (V4HI "x") (V8HI "x")
 674                          (V2SF "w") (V4SF "w")
 675                          (V2DF "w") (DF "w")])
 676
 677 ;; Defined to 'f' for types whose element type is a float type.
 678 (define_mode_attr f [(V8QI "")  (V16QI "")
 679                      (V4HI "")  (V8HI  "")
 680                      (V2SI "")  (V4SI  "")
 681                      (DI   "")  (V2DI  "")
 682                      (V2SF "f") (V4SF  "f")
 683                      (V2DF "f") (DF    "f")])
 684
 685 ;; Defined to '_fp' for types whose element type is a float type.
 686 (define_mode_attr fp [(V8QI "")  (V16QI "")
 687                       (V4HI "")  (V8HI  "")
 688                       (V2SI "")  (V4SI  "")
 689                       (DI   "")  (V2DI  "")
 690                       (V2SF "_fp") (V4SF  "_fp")
 691                       (V2DF "_fp") (DF    "_fp")
 692                       (SF "_fp")])
 693
 694 ;; Defined to '_q' for 128-bit types.
 695 (define_mode_attr q [(V8QI "") (V16QI "_q")
 696                      (V4HI "") (V8HI  "_q")
 697                      (V2SI "") (V4SI  "_q")
 698                      (DI   "") (V2DI  "_q")
 699                      (V4HF "") (V8HF "_q")
 700                      (V2SF "") (V4SF  "_q")
 701                                (V2DF  "_q")
 702                      (QI "") (HI "") (SI "") (DI "") (SF "") (DF "")])
 703
 704 (define_mode_attr vp [(V8QI "v") (V16QI "v")
 705                       (V4HI "v") (V8HI  "v")
 706                       (V2SI "p") (V4SI  "v")
 707                       (V2DI  "p") (V2DF  "p")
 708                       (V2SF "p") (V4SF  "v")])
 709
 710 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
 711 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
 712
 713 (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
 714
 715 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
 716 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
 717 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
 718
 719 ;; -------------------------------------------------------------------
 720 ;; Code Iterators
 721 ;; -------------------------------------------------------------------
 722
 723 ;; This code iterator allows the various shifts supported on the core
 724 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
 725
 726 ;; This code iterator allows the shifts supported in arithmetic instructions
 727 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
 728
 729 ;; Code iterator for logical operations
 730 (define_code_iterator LOGICAL [and ior xor])
 731
 732 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
 733 (define_code_iterator NLOGICAL [and ior])
 734
 735 ;; Code iterator for unary negate and bitwise complement.
 736 (define_code_iterator NEG_NOT [neg not])
 737
 738 ;; Code iterator for sign/zero extension
 739 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
 740
 741 ;; All division operations (signed/unsigned)
 742 (define_code_iterator ANY_DIV [div udiv])
 743
 744 ;; Code iterator for sign/zero extraction
 745 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
 746
 747 ;; Code iterator for equality comparisons
 748 (define_code_iterator EQL [eq ne])
 749
 750 ;; Code iterator for less-than and greater/equal-to
 751 (define_code_iterator LTGE [lt ge])
 752
 753 ;; Iterator for __sync_<op> operations that where the operation can be
 754 ;; represented directly RTL.  This is all of the sync operations bar
 755 ;; nand.
 756 (define_code_iterator atomic_op [plus minus ior xor and])
 757
 758 ;; Iterator for integer conversions
 759 (define_code_iterator FIXUORS [fix unsigned_fix])
 760
 761 ;; Iterator for float conversions
 762 (define_code_iterator FLOATUORS [float unsigned_float])
 763
 764 ;; Code iterator for variants of vector max and min.
 765 (define_code_iterator MAXMIN [smax smin umax umin])
 766
 767 (define_code_iterator FMAXMIN [smax smin])
 768
 769 ;; Code iterator for variants of vector max and min.
 770 (define_code_iterator ADDSUB [plus minus])
 771
 772 ;; Code iterator for variants of vector saturating binary ops.
 773 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
 774
 775 ;; Code iterator for variants of vector saturating unary ops.
 776 (define_code_iterator UNQOPS [ss_neg ss_abs])
 777
 778 ;; Code iterator for signed variants of vector saturating binary ops.
 779 (define_code_iterator SBINQOPS [ss_plus ss_minus])
 780
 781 ;; Comparison operators for <F>CM.
 782 (define_code_iterator COMPARISONS [lt le eq ge gt])
 783
 784 ;; Unsigned comparison operators.
 785 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
 786
 787 ;; Unsigned comparison operators.
 788 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
 789
 790 ;; -------------------------------------------------------------------
 791 ;; Code Attributes
 792 ;; -------------------------------------------------------------------
 793 ;; Map rtl objects to optab names
 794 (define_code_attr optab [(ashift "ashl")
 795                          (ashiftrt "ashr")
 796                          (lshiftrt "lshr")
 797                          (rotatert "rotr")
 798                          (sign_extend "extend")
 799                          (zero_extend "zero_extend")
 800                          (sign_extract "extv")
 801                          (zero_extract "extzv")
 802                          (fix "fix")
 803                          (unsigned_fix "fixuns")
 804                          (float "float")
 805                          (unsigned_float "floatuns")
 806                          (and "and")
 807                          (ior "ior")
 808                          (xor "xor")
 809                          (not "one_cmpl")
 810                          (neg "neg")
 811                          (plus "add")
 812                          (minus "sub")
 813                          (ss_plus "qadd")
 814                          (us_plus "qadd")
 815                          (ss_minus "qsub")
 816                          (us_minus "qsub")
 817                          (ss_neg "qneg")
 818                          (ss_abs "qabs")
 819                          (eq "eq")
 820                          (ne "ne")
 821                          (lt "lt")
 822                          (ge "ge")
 823                          (le "le")
 824                          (gt "gt")
 825                          (ltu "ltu")
 826                          (leu "leu")
 827                          (geu "geu")
 828                          (gtu "gtu")])
 829
 830 ;; For comparison operators we use the FCM* and CM* instructions.
 831 ;; As there are no CMLE or CMLT instructions which act on 3 vector
 832 ;; operands, we must use CMGE or CMGT and swap the order of the
 833 ;; source operands.
 834
 835 (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
 836                            (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
 837 (define_code_attr cmp_1   [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
 838                            (ltu "2") (leu "2") (geu "1") (gtu "1")])
 839 (define_code_attr cmp_2   [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
 840                            (ltu "1") (leu "1") (geu "2") (gtu "2")])
 841
 842 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
 843                         (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
 844                         (gtu "GTU")])
 845
 846 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
 847                                    (unsigned_fix "fixuns_trunc")])
 848
 849 ;; Optab prefix for sign/zero-extending operations
 850 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
 851                             (div "") (udiv "u")
 852                             (fix "") (unsigned_fix "u")
 853                             (float "s") (unsigned_float "u")
 854                             (ss_plus "s") (us_plus "u")
 855                             (ss_minus "s") (us_minus "u")])
 856
 857 ;; Similar for the instruction mnemonics
 858 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
 859                          (lshiftrt "lsr") (rotatert "ror")])
 860
 861 ;; Map shift operators onto underlying bit-field instructions
 862 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
 863                            (lshiftrt "ubfx") (rotatert "extr")])
 864
 865 ;; Logical operator instruction mnemonics
 866 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
 867
 868 ;; Operation names for negate and bitwise complement.
 869 (define_code_attr neg_not_op [(neg "neg") (not "not")])
 870
 871 ;; Similar, but when not(op)
 872 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
 873
 874 ;; Sign- or zero-extending load
 875 (define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")])
 876
 877 ;; Sign- or zero-extending data-op
 878 (define_code_attr su [(sign_extend "s") (zero_extend "u")
 879                       (sign_extract "s") (zero_extract "u")
 880                       (fix "s") (unsigned_fix "u")
 881                       (div "s") (udiv "u")
 882                       (smax "s") (umax "u")
 883                       (smin "s") (umin "u")])
 884
 885 ;; Emit conditional branch instructions.
 886 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
 887
 888 ;; Emit cbz/cbnz depending on comparison type.
 889 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
 890
 891 ;; Emit inverted cbz/cbnz depending on comparison type.
 892 (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
 893
 894 ;; Emit tbz/tbnz depending on comparison type.
 895 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
 896
 897 ;; Emit inverted tbz/tbnz depending on comparison type.
 898 (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
 899
 900 ;; Max/min attributes.
 901 (define_code_attr maxmin [(smax "max")
 902                           (smin "min")
 903                           (umax "max")
 904                           (umin "min")])
 905
 906 ;; MLA/MLS attributes.
 907 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
 908
 909 ;; Atomic operations
 910 (define_code_attr atomic_optab
 911   [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
 912
 913 (define_code_attr atomic_op_operand
 914   [(ior "aarch64_logical_operand")
 915    (xor "aarch64_logical_operand")
 916    (and "aarch64_logical_operand")
 917    (plus "aarch64_plus_operand")
 918    (minus "aarch64_plus_operand")])
 919
 920 ;; Constants acceptable for atomic operations.
 921 ;; This definition must appear in this file before the iterators it refers to.
 922 (define_code_attr const_atomic
 923  [(plus "IJ") (minus "IJ")
 924   (xor "<lconst_atomic>") (ior "<lconst_atomic>")
 925   (and "<lconst_atomic>")])
 926
 927 ;; Attribute to describe constants acceptable in atomic logical operations
 928 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
 929
 930 ;; -------------------------------------------------------------------
 931 ;; Int Iterators.
 932 ;; -------------------------------------------------------------------
 933 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
 934                               UNSPEC_SMAXV UNSPEC_SMINV])
 935
 936 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
 937                                UNSPEC_FMAXNMV UNSPEC_FMINNMV])
 938
 939 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
 940                               UNSPEC_SRHADD UNSPEC_URHADD
 941                               UNSPEC_SHSUB UNSPEC_UHSUB
 942                               UNSPEC_SRHSUB UNSPEC_URHSUB])
 943
 944
 945 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
 946                                UNSPEC_SUBHN UNSPEC_RSUBHN])
 947
 948 (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
 949                                 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
 950
 951 (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN])
 952
 953 (define_int_iterator FMAXMIN [UNSPEC_FMAXNM UNSPEC_FMINNM])
 954
 955 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
 956
 957 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
 958
 959 (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
 960
 961 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
 962                            UNSPEC_SRSHL UNSPEC_URSHL])
 963
 964 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
 965
 966 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
 967                             UNSPEC_SQRSHL UNSPEC_UQRSHL])
 968
 969 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
 970                              UNSPEC_SRSRA UNSPEC_URSRA])
 971
 972 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
 973                               UNSPEC_SSRI UNSPEC_USRI])
 974
 975
 976 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
 977
 978 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
 979
 980 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
 981                                UNSPEC_SQSHRN UNSPEC_UQSHRN
 982                                UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
 983
 984 (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
 985
 986 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
 987                               UNSPEC_TRN1 UNSPEC_TRN2
 988                               UNSPEC_UZP1 UNSPEC_UZP2])
 989
 990 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
 991
 992 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
 993                              UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
 994                              UNSPEC_FRINTA])
 995
 996 (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
 997                             UNSPEC_FRINTA UNSPEC_FRINTN])
 998
 999 (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
1000
1001 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1002                           UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1003                           UNSPEC_CRC32CW UNSPEC_CRC32CX])
1004
1005 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1006 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1007
1008 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1009
1010 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1011
1012 ;; Iterators for atomic operations.
1013
1014 (define_int_iterator ATOMIC_LDOP
1015  [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1016   UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1017
1018 (define_int_attr atomic_ldop
1019  [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1020   (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1021
1022 ;; -------------------------------------------------------------------
1023 ;; Int Iterators Attributes.
1024 ;; -------------------------------------------------------------------
1025 (define_int_attr  maxmin_uns [(UNSPEC_UMAXV "umax")
1026                               (UNSPEC_UMINV "umin")
1027                               (UNSPEC_SMAXV "smax")
1028                               (UNSPEC_SMINV "smin")
1029                               (UNSPEC_FMAX  "smax_nan")
1030                               (UNSPEC_FMAXNMV "smax")
1031                               (UNSPEC_FMAXV "smax_nan")
1032                               (UNSPEC_FMIN "smin_nan")
1033                               (UNSPEC_FMINNMV "smin")
1034                               (UNSPEC_FMINV "smin_nan")])
1035
1036 (define_int_attr  maxmin_uns_op [(UNSPEC_UMAXV "umax")
1037                                  (UNSPEC_UMINV "umin")
1038                                  (UNSPEC_SMAXV "smax")
1039                                  (UNSPEC_SMINV "smin")
1040                                  (UNSPEC_FMAX "fmax")
1041                                  (UNSPEC_FMAXNMV "fmaxnm")
1042                                  (UNSPEC_FMAXV "fmax")
1043                                  (UNSPEC_FMIN "fmin")
1044                                  (UNSPEC_FMINNMV "fminnm")
1045                                  (UNSPEC_FMINV "fmin")])
1046
1047 (define_int_attr fmaxmin [(UNSPEC_FMAXNM "fmax")
1048                           (UNSPEC_FMINNM "fmin")])
1049
1050 (define_int_attr fmaxmin_op [(UNSPEC_FMAXNM "fmaxnm")
1051                              (UNSPEC_FMINNM "fminnm")])
1052
1053 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1054                       (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1055                       (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1056                       (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1057                       (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
1058                       (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1059                       (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1060                       (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1061                       (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1062                       (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1063                       (UNSPEC_SSLI  "s") (UNSPEC_USLI  "u")
1064                       (UNSPEC_SSRI  "s") (UNSPEC_USRI  "u")
1065                       (UNSPEC_USRA  "u") (UNSPEC_SSRA  "s")
1066                       (UNSPEC_URSRA  "ur") (UNSPEC_SRSRA  "sr")
1067                       (UNSPEC_URSHR  "ur") (UNSPEC_SRSHR  "sr")
1068                       (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL   "s")
1069                       (UNSPEC_UQSHL  "u")
1070                       (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1071                       (UNSPEC_SQSHRN "s")  (UNSPEC_UQSHRN "u")
1072                       (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1073                       (UNSPEC_USHL  "u")   (UNSPEC_SSHL  "s")
1074                       (UNSPEC_USHLL  "u")  (UNSPEC_SSHLL "s")
1075                       (UNSPEC_URSHL  "ur") (UNSPEC_SRSHL  "sr")
1076                       (UNSPEC_UQRSHL  "u") (UNSPEC_SQRSHL  "s")
1077 ])
1078
1079 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1080                     (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1081                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
1082                     (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1083                     (UNSPEC_SQSHL   "")  (UNSPEC_UQSHL  "")
1084                     (UNSPEC_SQRSHL   "r")(UNSPEC_UQRSHL  "r")
1085 ])
1086
1087 (define_int_attr lr [(UNSPEC_SSLI  "l") (UNSPEC_USLI  "l")
1088                      (UNSPEC_SSRI  "r") (UNSPEC_USRI  "r")])
1089
1090 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1091                     (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1092                     (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
1093                     (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
1094
1095 (define_int_attr addsub [(UNSPEC_SHADD "add")
1096                          (UNSPEC_UHADD "add")
1097                          (UNSPEC_SRHADD "add")
1098                          (UNSPEC_URHADD "add")
1099                          (UNSPEC_SHSUB "sub")
1100                          (UNSPEC_UHSUB "sub")
1101                          (UNSPEC_SRHSUB "sub")
1102                          (UNSPEC_URHSUB "sub")
1103                          (UNSPEC_ADDHN "add")
1104                          (UNSPEC_SUBHN "sub")
1105                          (UNSPEC_RADDHN "add")
1106                          (UNSPEC_RSUBHN "sub")
1107                          (UNSPEC_ADDHN2 "add")
1108                          (UNSPEC_SUBHN2 "sub")
1109                          (UNSPEC_RADDHN2 "add")
1110                          (UNSPEC_RSUBHN2 "sub")])
1111
1112 (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1113                            (UNSPEC_SSRI "offset_")
1114                            (UNSPEC_USRI "offset_")])
1115
1116 ;; Standard pattern names for floating-point rounding instructions.
1117 (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1118                                 (UNSPEC_FRINTP "ceil")
1119                                 (UNSPEC_FRINTM "floor")
1120                                 (UNSPEC_FRINTI "nearbyint")
1121                                 (UNSPEC_FRINTX "rint")
1122                                 (UNSPEC_FRINTA "round")
1123                                 (UNSPEC_FRINTN "frintn")])
1124
1125 ;; frint suffix for floating-point rounding instructions.
1126 (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1127                                (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
1128                                (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1129                                (UNSPEC_FRINTN "n")])
1130
1131 (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
1132                                (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1133                                (UNSPEC_FRINTN "frintn")])
1134
1135 (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1136                             (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1137                             (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1138
1139 ; op code for REV instructions (size within which elements are reversed).
1140 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1141                          (UNSPEC_REV16 "16")])
1142
1143 (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1144                             (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
1145                             (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
1146
1147 (define_int_attr frecp_suffix  [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
1148
1149 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1150                         (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1151                         (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1152                         (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1153
1154 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1155                         (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1156                         (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1157                         (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1158
1159 (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1160 (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
1161
1162 (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1163                           (UNSPEC_SHA1M "m")])
1164
1165 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
1166
1167 (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])