1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2014 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_special_predicate "cc_register"
22 (and (match_code "reg")
23 (and (match_test "REGNO (op) == CC_REGNUM")
24 (ior (match_test "mode == GET_MODE (op)")
25 (match_test "mode == VOIDmode
26 && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
29 (define_predicate "aarch64_simd_register"
30 (and (match_code "reg")
31 (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
32 (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
34 (define_predicate "aarch64_reg_or_zero"
35 (and (match_code "reg,subreg,const_int")
36 (ior (match_operand 0 "register_operand")
37 (match_test "op == const0_rtx"))))
39 (define_predicate "aarch64_reg_or_fp_zero"
40 (and (match_code "reg,subreg,const_double")
41 (ior (match_operand 0 "register_operand")
42 (match_test "aarch64_float_const_zero_rtx_p (op)"))))
44 (define_predicate "aarch64_reg_zero_or_m1_or_1"
45 (and (match_code "reg,subreg,const_int")
46 (ior (match_operand 0 "register_operand")
47 (ior (match_test "op == const0_rtx")
48 (ior (match_test "op == constm1_rtx")
49 (match_test "op == const1_rtx"))))))
51 (define_predicate "aarch64_fp_compare_operand"
52 (ior (match_operand 0 "register_operand")
53 (and (match_code "const_double")
54 (match_test "aarch64_float_const_zero_rtx_p (op)"))))
56 (define_predicate "aarch64_plus_immediate"
57 (and (match_code "const_int")
58 (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
59 (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
61 (define_predicate "aarch64_plus_operand"
62 (ior (match_operand 0 "register_operand")
63 (match_operand 0 "aarch64_plus_immediate")))
65 (define_predicate "aarch64_pluslong_immediate"
66 (and (match_code "const_int")
67 (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
69 (define_predicate "aarch64_pluslong_operand"
70 (ior (match_operand 0 "register_operand")
71 (match_operand 0 "aarch64_pluslong_immediate")))
73 (define_predicate "aarch64_logical_immediate"
74 (and (match_code "const_int")
75 (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
77 (define_predicate "aarch64_logical_operand"
78 (ior (match_operand 0 "register_operand")
79 (match_operand 0 "aarch64_logical_immediate")))
81 (define_predicate "aarch64_shift_imm_si"
82 (and (match_code "const_int")
83 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
85 (define_predicate "aarch64_shift_imm_di"
86 (and (match_code "const_int")
87 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
89 (define_predicate "aarch64_reg_or_shift_imm_si"
90 (ior (match_operand 0 "register_operand")
91 (match_operand 0 "aarch64_shift_imm_si")))
93 (define_predicate "aarch64_reg_or_shift_imm_di"
94 (ior (match_operand 0 "register_operand")
95 (match_operand 0 "aarch64_shift_imm_di")))
97 ;; The imm3 field is a 3-bit field that only accepts immediates in the
99 (define_predicate "aarch64_imm3"
100 (and (match_code "const_int")
101 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
103 (define_predicate "aarch64_pwr_imm3"
104 (and (match_code "const_int")
105 (match_test "INTVAL (op) != 0
106 && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
108 (define_predicate "aarch64_pwr_2_si"
109 (and (match_code "const_int")
110 (match_test "INTVAL (op) != 0
111 && (unsigned) exact_log2 (INTVAL (op)) < 32")))
113 (define_predicate "aarch64_pwr_2_di"
114 (and (match_code "const_int")
115 (match_test "INTVAL (op) != 0
116 && (unsigned) exact_log2 (INTVAL (op)) < 64")))
118 (define_predicate "aarch64_mem_pair_operand"
119 (and (match_code "mem")
120 (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
123 (define_predicate "aarch64_valid_symref"
124 (match_code "const, symbol_ref, label_ref")
126 return (aarch64_classify_symbolic_expression (op, SYMBOL_CONTEXT_ADR)
127 != SYMBOL_FORCE_TO_MEM);
130 (define_predicate "aarch64_tls_ie_symref"
131 (match_code "const, symbol_ref, label_ref")
133 switch (GET_CODE (op))
137 if (GET_CODE (op) != PLUS
138 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
139 || GET_CODE (XEXP (op, 1)) != CONST_INT)
144 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
151 (define_predicate "aarch64_tls_le_symref"
152 (match_code "const, symbol_ref, label_ref")
154 switch (GET_CODE (op))
158 if (GET_CODE (op) != PLUS
159 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
160 || GET_CODE (XEXP (op, 1)) != CONST_INT)
165 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
172 (define_predicate "aarch64_mov_operand"
173 (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high")
174 (ior (match_operand 0 "register_operand")
175 (ior (match_operand 0 "memory_operand")
176 (match_test "aarch64_mov_operand_p (op, SYMBOL_CONTEXT_ADR, mode)")))))
178 (define_predicate "aarch64_movti_operand"
179 (and (match_code "reg,subreg,mem,const_int")
180 (ior (match_operand 0 "register_operand")
181 (ior (match_operand 0 "memory_operand")
182 (match_operand 0 "const_int_operand")))))
184 (define_predicate "aarch64_reg_or_imm"
185 (and (match_code "reg,subreg,const_int")
186 (ior (match_operand 0 "register_operand")
187 (match_operand 0 "const_int_operand"))))
189 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
190 (define_special_predicate "aarch64_comparison_operator"
191 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
193 ;; True if the operand is memory reference suitable for a load/store exclusive.
194 (define_predicate "aarch64_sync_memory_operand"
195 (and (match_operand 0 "memory_operand")
196 (match_code "reg" "0")))
198 ;; Predicates for parallel expanders based on mode.
199 (define_special_predicate "vect_par_cnst_hi_half"
200 (match_code "parallel")
202 HOST_WIDE_INT count = XVECLEN (op, 0);
203 int nunits = GET_MODE_NUNITS (mode);
207 || count != nunits / 2)
210 if (!VECTOR_MODE_P (mode))
213 for (i = 0; i < count; i++)
215 rtx elt = XVECEXP (op, 0, i);
218 if (GET_CODE (elt) != CONST_INT)
222 if (val != (nunits / 2) + i)
228 (define_special_predicate "vect_par_cnst_lo_half"
229 (match_code "parallel")
231 HOST_WIDE_INT count = XVECLEN (op, 0);
232 int nunits = GET_MODE_NUNITS (mode);
236 || count != nunits / 2)
239 if (!VECTOR_MODE_P (mode))
242 for (i = 0; i < count; i++)
244 rtx elt = XVECEXP (op, 0, i);
247 if (GET_CODE (elt) != CONST_INT)
258 (define_special_predicate "aarch64_simd_lshift_imm"
259 (match_code "const_vector")
261 return aarch64_simd_shift_imm_p (op, mode, true);
264 (define_special_predicate "aarch64_simd_rshift_imm"
265 (match_code "const_vector")
267 return aarch64_simd_shift_imm_p (op, mode, false);
270 (define_predicate "aarch64_simd_reg_or_zero"
271 (and (match_code "reg,subreg,const_int,const_vector")
272 (ior (match_operand 0 "register_operand")
273 (ior (match_test "op == const0_rtx")
274 (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
276 (define_predicate "aarch64_simd_struct_operand"
277 (and (match_code "mem")
278 (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
280 ;; Like general_operand but allow only valid SIMD addressing modes.
281 (define_predicate "aarch64_simd_general_operand"
282 (and (match_operand 0 "general_operand")
283 (match_test "!MEM_P (op)
284 || GET_CODE (XEXP (op, 0)) == POST_INC
285 || GET_CODE (XEXP (op, 0)) == REG")))
287 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
288 (define_predicate "aarch64_simd_nonimmediate_operand"
289 (and (match_operand 0 "nonimmediate_operand")
290 (match_test "!MEM_P (op)
291 || GET_CODE (XEXP (op, 0)) == POST_INC
292 || GET_CODE (XEXP (op, 0)) == REG")))
294 (define_special_predicate "aarch64_simd_imm_zero"
295 (match_code "const_vector")
297 return aarch64_simd_imm_zero_p (op, mode);