gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 ;; Return true if OP a (const_int 0) operand.
  34 (define_predicate "const0_operand"
  35   (and (match_code "const_int")
  36        (match_test "op == CONST0_RTX (mode)")))
  37
  38 (define_predicate "aarch64_ccmp_immediate"
  39   (and (match_code "const_int")
  40        (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
  41
  42 (define_predicate "aarch64_ccmp_operand"
  43   (ior (match_operand 0 "register_operand")
  44        (match_operand 0 "aarch64_ccmp_immediate")))
  45
  46 (define_predicate "aarch64_simd_register"
  47   (and (match_code "reg")
  48        (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
  49             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
  50
  51 (define_predicate "aarch64_reg_or_zero"
  52   (and (match_code "reg,subreg,const_int")
  53        (ior (match_operand 0 "register_operand")
  54             (match_test "op == const0_rtx"))))
  55
  56 (define_predicate "aarch64_reg_or_fp_zero"
  57   (ior (match_operand 0 "register_operand")
  58         (and (match_code "const_double")
  59              (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  60
  61 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  62   (and (match_code "reg,subreg,const_int")
  63        (ior (match_operand 0 "register_operand")
  64             (ior (match_test "op == const0_rtx")
  65                  (ior (match_test "op == constm1_rtx")
  66                       (match_test "op == const1_rtx"))))))
  67
  68 (define_predicate "aarch64_fp_compare_operand"
  69   (ior (match_operand 0 "register_operand")
  70        (and (match_code "const_double")
  71             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  72
  73 (define_predicate "aarch64_fp_pow2"
  74   (and (match_code "const_double")
  75         (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
  76
  77 (define_predicate "aarch64_fp_vec_pow2"
  78   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
  79
  80 (define_predicate "aarch64_sub_immediate"
  81   (and (match_code "const_int")
  82        (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
  83
  84 (define_predicate "aarch64_plus_immediate"
  85   (and (match_code "const_int")
  86        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
  87             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
  88
  89 (define_predicate "aarch64_plus_operand"
  90   (ior (match_operand 0 "register_operand")
  91        (match_operand 0 "aarch64_plus_immediate")))
  92
  93 (define_predicate "aarch64_pluslong_immediate"
  94   (and (match_code "const_int")
  95        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
  96
  97 (define_predicate "aarch64_pluslong_strict_immedate"
  98   (and (match_operand 0 "aarch64_pluslong_immediate")
  99        (not (match_operand 0 "aarch64_plus_immediate"))))
 100
 101 (define_predicate "aarch64_pluslong_operand"
 102   (ior (match_operand 0 "register_operand")
 103        (match_operand 0 "aarch64_pluslong_immediate")))
 104
 105 (define_predicate "aarch64_logical_immediate"
 106   (and (match_code "const_int")
 107        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
 108
 109 (define_predicate "aarch64_logical_operand"
 110   (ior (match_operand 0 "register_operand")
 111        (match_operand 0 "aarch64_logical_immediate")))
 112
 113 (define_predicate "aarch64_logical_and_immediate"
 114   (and (match_code "const_int")
 115        (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
 116
 117 (define_predicate "aarch64_shift_imm_si"
 118   (and (match_code "const_int")
 119        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
 120
 121 (define_predicate "aarch64_shift_imm_di"
 122   (and (match_code "const_int")
 123        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
 124
 125 (define_predicate "aarch64_shift_imm64_di"
 126   (and (match_code "const_int")
 127        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
 128
 129 (define_predicate "aarch64_reg_or_shift_imm_si"
 130   (ior (match_operand 0 "register_operand")
 131        (match_operand 0 "aarch64_shift_imm_si")))
 132
 133 (define_predicate "aarch64_reg_or_shift_imm_di"
 134   (ior (match_operand 0 "register_operand")
 135        (match_operand 0 "aarch64_shift_imm_di")))
 136
 137 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 138 ;; range 0..4.
 139 (define_predicate "aarch64_imm3"
 140   (and (match_code "const_int")
 141        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 142
 143 ;; An immediate that fits into 24 bits.
 144 (define_predicate "aarch64_imm24"
 145   (and (match_code "const_int")
 146        (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
 147
 148 (define_predicate "aarch64_pwr_imm3"
 149   (and (match_code "const_int")
 150        (match_test "INTVAL (op) != 0
 151                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 152
 153 (define_predicate "aarch64_pwr_2_si"
 154   (and (match_code "const_int")
 155        (match_test "INTVAL (op) != 0
 156                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 157
 158 (define_predicate "aarch64_pwr_2_di"
 159   (and (match_code "const_int")
 160        (match_test "INTVAL (op) != 0
 161                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 162
 163 (define_predicate "aarch64_mem_pair_offset"
 164   (and (match_code "const_int")
 165        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 166
 167 (define_predicate "aarch64_mem_pair_operand"
 168   (and (match_code "mem")
 169        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
 170                                                0)")))
 171
 172 (define_predicate "aarch64_prefetch_operand"
 173   (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
 174
 175 (define_predicate "aarch64_valid_symref"
 176   (match_code "const, symbol_ref, label_ref")
 177 {
 178   return (aarch64_classify_symbolic_expression (op)
 179           != SYMBOL_FORCE_TO_MEM);
 180 })
 181
 182 (define_predicate "aarch64_tls_ie_symref"
 183   (match_code "const, symbol_ref, label_ref")
 184 {
 185   switch (GET_CODE (op))
 186     {
 187     case CONST:
 188       op = XEXP (op, 0);
 189       if (GET_CODE (op) != PLUS
 190           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 191           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 192         return false;
 193       op = XEXP (op, 0);
 194       /* FALLTHRU */
 195
 196     case SYMBOL_REF:
 197       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 198
 199     default:
 200       gcc_unreachable ();
 201     }
 202 })
 203
 204 (define_predicate "aarch64_tls_le_symref"
 205   (match_code "const, symbol_ref, label_ref")
 206 {
 207   switch (GET_CODE (op))
 208     {
 209     case CONST:
 210       op = XEXP (op, 0);
 211       if (GET_CODE (op) != PLUS
 212           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 213           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 214         return false;
 215       op = XEXP (op, 0);
 216       /* FALLTHRU */
 217
 218     case SYMBOL_REF:
 219       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 220
 221     default:
 222       gcc_unreachable ();
 223     }
 224 })
 225
 226 (define_predicate "aarch64_mov_operand"
 227   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high")
 228        (ior (match_operand 0 "register_operand")
 229             (ior (match_operand 0 "memory_operand")
 230                  (match_test "aarch64_mov_operand_p (op, mode)")))))
 231
 232 (define_predicate "aarch64_movti_operand"
 233   (and (match_code "reg,subreg,mem,const_int")
 234        (ior (match_operand 0 "register_operand")
 235             (ior (match_operand 0 "memory_operand")
 236                  (match_operand 0 "const_int_operand")))))
 237
 238 (define_predicate "aarch64_reg_or_imm"
 239   (and (match_code "reg,subreg,const_int")
 240        (ior (match_operand 0 "register_operand")
 241             (match_operand 0 "const_int_operand"))))
 242
 243 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 244 (define_special_predicate "aarch64_comparison_operator"
 245   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 246                ordered,unlt,unle,unge,ungt"))
 247
 248 ;; Same as aarch64_comparison_operator but don't ignore the mode.
 249 ;; RTL SET operations require their operands source and destination have
 250 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 251 (define_predicate "aarch64_comparison_operator_mode"
 252   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 253                ordered,unlt,unle,unge,ungt"))
 254
 255 (define_special_predicate "aarch64_comparison_operation"
 256   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 257                ordered,unlt,unle,unge,ungt")
 258 {
 259   if (XEXP (op, 1) != const0_rtx)
 260     return false;
 261   rtx op0 = XEXP (op, 0);
 262   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 263     return false;
 264   return aarch64_get_condition_code (op) >= 0;
 265 })
 266
 267 (define_special_predicate "aarch64_carry_operation"
 268   (match_code "ne,geu")
 269 {
 270   if (XEXP (op, 1) != const0_rtx)
 271     return false;
 272   machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
 273   rtx op0 = XEXP (op, 0);
 274   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 275 })
 276
 277 (define_special_predicate "aarch64_borrow_operation"
 278   (match_code "eq,ltu")
 279 {
 280   if (XEXP (op, 1) != const0_rtx)
 281     return false;
 282   machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
 283   rtx op0 = XEXP (op, 0);
 284   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 285 })
 286
 287 ;; True if the operand is memory reference suitable for a load/store exclusive.
 288 (define_predicate "aarch64_sync_memory_operand"
 289   (and (match_operand 0 "memory_operand")
 290        (match_code "reg" "0")))
 291
 292 ;; Predicates for parallel expanders based on mode.
 293 (define_special_predicate "vect_par_cnst_hi_half"
 294   (match_code "parallel")
 295 {
 296   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 297 })
 298
 299 (define_special_predicate "vect_par_cnst_lo_half"
 300   (match_code "parallel")
 301 {
 302   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 303 })
 304
 305 (define_special_predicate "aarch64_simd_lshift_imm"
 306   (match_code "const_vector")
 307 {
 308   return aarch64_simd_shift_imm_p (op, mode, true);
 309 })
 310
 311 (define_special_predicate "aarch64_simd_rshift_imm"
 312   (match_code "const_vector")
 313 {
 314   return aarch64_simd_shift_imm_p (op, mode, false);
 315 })
 316
 317 (define_predicate "aarch64_simd_reg_or_zero"
 318   (and (match_code "reg,subreg,const_int,const_double,const_vector")
 319        (ior (match_operand 0 "register_operand")
 320            (ior (match_test "op == const0_rtx")
 321                 (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
 322
 323 (define_predicate "aarch64_simd_struct_operand"
 324   (and (match_code "mem")
 325        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 326
 327 ;; Like general_operand but allow only valid SIMD addressing modes.
 328 (define_predicate "aarch64_simd_general_operand"
 329   (and (match_operand 0 "general_operand")
 330        (match_test "!MEM_P (op)
 331                     || GET_CODE (XEXP (op, 0)) == POST_INC
 332                     || GET_CODE (XEXP (op, 0)) == REG")))
 333
 334 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 335 (define_predicate "aarch64_simd_nonimmediate_operand"
 336   (and (match_operand 0 "nonimmediate_operand")
 337        (match_test "!MEM_P (op)
 338                     || GET_CODE (XEXP (op, 0)) == POST_INC
 339                     || GET_CODE (XEXP (op, 0)) == REG")))
 340
 341 (define_special_predicate "aarch64_simd_imm_zero"
 342   (match_code "const_vector")
 343 {
 344   return aarch64_simd_imm_zero_p (op, mode);
 345 })
 346
 347 (define_special_predicate "aarch64_simd_imm_minus_one"
 348   (match_code "const_vector")
 349 {
 350   return aarch64_const_vec_all_same_int_p (op, -1);
 351 })
 352
 353 ;; Predicates used by the various SIMD shift operations.  These
 354 ;; fall in to 3 categories.
 355 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 356 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 357 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 358 (define_predicate "aarch64_simd_shift_imm_qi"
 359   (and (match_code "const_int")
 360        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 361
 362 (define_predicate "aarch64_simd_shift_imm_hi"
 363   (and (match_code "const_int")
 364        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 365
 366 (define_predicate "aarch64_simd_shift_imm_si"
 367   (and (match_code "const_int")
 368        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 369
 370 (define_predicate "aarch64_simd_shift_imm_di"
 371   (and (match_code "const_int")
 372        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 373
 374 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 375   (and (match_code "const_int")
 376        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 377
 378 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 379   (and (match_code "const_int")
 380        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 381
 382 (define_predicate "aarch64_simd_shift_imm_offset_si"
 383   (and (match_code "const_int")
 384        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 385
 386 (define_predicate "aarch64_simd_shift_imm_offset_di"
 387   (and (match_code "const_int")
 388        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 389
 390 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 391   (and (match_code "const_int")
 392        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 393
 394 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 395   (and (match_code "const_int")
 396        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 397
 398 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 399   (and (match_code "const_int")
 400        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 401
 402 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 403   (and (match_code "const_int")
 404        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
 405
 406 (define_predicate "aarch64_constant_pool_symref"
 407    (and (match_code "symbol_ref")
 408         (match_test "CONSTANT_POOL_ADDRESS_P (op)")))