gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 (define_predicate "aarch64_general_reg"
  34   (and (match_operand 0 "register_operand")
  35        (match_test "REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS")))
  36
  37 ;; Return true if OP a (const_int 0) operand.
  38 (define_predicate "const0_operand"
  39   (and (match_code "const_int")
  40        (match_test "op == CONST0_RTX (mode)")))
  41
  42 (define_predicate "const_1_to_3_operand"
  43   (match_code "const_int,const_vector")
  44 {
  45   op = unwrap_const_vec_duplicate (op);
  46   return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 1, 3);
  47 })
  48
  49 (define_special_predicate "subreg_lowpart_operator"
  50   (and (match_code "subreg")
  51        (match_test "subreg_lowpart_p (op)")))
  52
  53 (define_predicate "aarch64_ccmp_immediate"
  54   (and (match_code "const_int")
  55        (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
  56
  57 (define_predicate "aarch64_ccmp_operand"
  58   (ior (match_operand 0 "register_operand")
  59        (match_operand 0 "aarch64_ccmp_immediate")))
  60
  61 (define_predicate "aarch64_simd_register"
  62   (and (match_code "reg")
  63        (match_test "FP_REGNUM_P (REGNO (op))")))
  64
  65 (define_predicate "aarch64_reg_or_zero"
  66   (and (match_code "reg,subreg,const_int,const_double")
  67        (ior (match_operand 0 "register_operand")
  68             (match_test "op == CONST0_RTX (GET_MODE (op))"))))
  69
  70 (define_predicate "aarch64_reg_or_fp_zero"
  71   (ior (match_operand 0 "register_operand")
  72         (and (match_code "const_double")
  73              (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  74
  75 (define_predicate "aarch64_reg_zero_or_fp_zero"
  76   (ior (match_operand 0 "aarch64_reg_or_fp_zero")
  77        (match_operand 0 "aarch64_reg_or_zero")))
  78
  79 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  80   (and (match_code "reg,subreg,const_int")
  81        (ior (match_operand 0 "register_operand")
  82             (ior (match_test "op == const0_rtx")
  83                  (ior (match_test "op == constm1_rtx")
  84                       (match_test "op == const1_rtx"))))))
  85
  86 (define_predicate "aarch64_reg_or_orr_imm"
  87    (ior (match_operand 0 "register_operand")
  88         (and (match_code "const_vector")
  89              (match_test "aarch64_simd_valid_immediate (op, NULL,
  90                                                         AARCH64_CHECK_ORR)"))))
  91
  92 (define_predicate "aarch64_reg_or_bic_imm"
  93    (ior (match_operand 0 "register_operand")
  94         (and (match_code "const_vector")
  95              (match_test "aarch64_simd_valid_immediate (op, NULL,
  96                                                         AARCH64_CHECK_BIC)"))))
  97
  98 (define_predicate "aarch64_fp_compare_operand"
  99   (ior (match_operand 0 "register_operand")
 100        (and (match_code "const_double")
 101             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
 102
 103 (define_predicate "aarch64_fp_pow2"
 104   (and (match_code "const_double")
 105         (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
 106
 107 (define_predicate "aarch64_fp_vec_pow2"
 108   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
 109
 110 (define_predicate "aarch64_sve_cnt_immediate"
 111   (and (match_code "const_poly_int")
 112        (match_test "aarch64_sve_cnt_immediate_p (op)")))
 113
 114 (define_predicate "aarch64_sub_immediate"
 115   (and (match_code "const_int")
 116        (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
 117
 118 (define_predicate "aarch64_plus_immediate"
 119   (and (match_code "const_int")
 120        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
 121             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
 122
 123 (define_predicate "aarch64_plus_operand"
 124   (ior (match_operand 0 "register_operand")
 125        (match_operand 0 "aarch64_plus_immediate")))
 126
 127 (define_predicate "aarch64_plushi_immediate"
 128   (match_code "const_int")
 129 {
 130   HOST_WIDE_INT val = INTVAL (op);
 131   /* The HImode value must be zero-extendable to an SImode plus_operand.  */
 132   return ((val & 0xfff) == val || sext_hwi (val & 0xf000, 16) == val);
 133 })
 134
 135 (define_predicate "aarch64_plushi_operand"
 136   (ior (match_operand 0 "register_operand")
 137        (match_operand 0 "aarch64_plushi_immediate")))
 138
 139 (define_predicate "aarch64_pluslong_immediate"
 140   (and (match_code "const_int")
 141        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
 142
 143 (define_predicate "aarch64_pluslong_strict_immedate"
 144   (and (match_operand 0 "aarch64_pluslong_immediate")
 145        (not (match_operand 0 "aarch64_plus_immediate"))))
 146
 147 (define_predicate "aarch64_sve_addvl_addpl_immediate"
 148   (and (match_code "const_poly_int")
 149        (match_test "aarch64_sve_addvl_addpl_immediate_p (op)")))
 150
 151 (define_predicate "aarch64_split_add_offset_immediate"
 152   (and (match_code "const_poly_int")
 153        (match_test "aarch64_add_offset_temporaries (op) == 1")))
 154
 155 (define_predicate "aarch64_pluslong_operand"
 156   (ior (match_operand 0 "register_operand")
 157        (match_operand 0 "aarch64_pluslong_immediate")
 158        (match_operand 0 "aarch64_sve_addvl_addpl_immediate")))
 159
 160 (define_predicate "aarch64_pluslong_or_poly_operand"
 161   (ior (match_operand 0 "aarch64_pluslong_operand")
 162        (match_operand 0 "aarch64_split_add_offset_immediate")))
 163
 164 (define_predicate "aarch64_logical_immediate"
 165   (and (match_code "const_int")
 166        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
 167
 168 (define_predicate "aarch64_logical_operand"
 169   (ior (match_operand 0 "register_operand")
 170        (match_operand 0 "aarch64_logical_immediate")))
 171
 172 (define_predicate "aarch64_mov_imm_operand"
 173   (and (match_code "const_int")
 174        (match_test "aarch64_move_imm (INTVAL (op), mode)")))
 175
 176 (define_predicate "aarch64_logical_and_immediate"
 177   (and (match_code "const_int")
 178        (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
 179
 180 (define_predicate "aarch64_shift_imm_si"
 181   (and (match_code "const_int")
 182        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
 183
 184 (define_predicate "aarch64_shift_imm_di"
 185   (and (match_code "const_int")
 186        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
 187
 188 (define_predicate "aarch64_shift_imm64_di"
 189   (and (match_code "const_int")
 190        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
 191
 192 (define_predicate "aarch64_reg_or_shift_imm_si"
 193   (ior (match_operand 0 "register_operand")
 194        (match_operand 0 "aarch64_shift_imm_si")))
 195
 196 (define_predicate "aarch64_reg_or_shift_imm_di"
 197   (ior (match_operand 0 "register_operand")
 198        (match_operand 0 "aarch64_shift_imm_di")))
 199
 200 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 201 ;; range 0..4.
 202 (define_predicate "aarch64_imm3"
 203   (and (match_code "const_int")
 204        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 205
 206 ;; The imm2 field is a 2-bit field that only accepts immediates in the
 207 ;; range 0..3.
 208 (define_predicate "aarch64_imm2"
 209   (and (match_code "const_int")
 210        (match_test "UINTVAL (op) <= 3")))
 211
 212 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 213 ;; range 0..7.
 214 (define_predicate "aarch64_lane_imm3"
 215   (and (match_code "const_int")
 216        (match_test "UINTVAL (op) <= 7")))
 217
 218 ;; An immediate that fits into 24 bits.
 219 (define_predicate "aarch64_imm24"
 220   (and (match_code "const_int")
 221        (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
 222
 223 (define_predicate "aarch64_pwr_imm3"
 224   (and (match_code "const_int")
 225        (match_test "INTVAL (op) != 0
 226                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 227
 228 (define_predicate "aarch64_pwr_2_si"
 229   (and (match_code "const_int")
 230        (match_test "INTVAL (op) != 0
 231                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 232
 233 (define_predicate "aarch64_pwr_2_di"
 234   (and (match_code "const_int")
 235        (match_test "INTVAL (op) != 0
 236                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 237
 238 (define_predicate "aarch64_mem_pair_offset"
 239   (and (match_code "const_int")
 240        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 241
 242 (define_predicate "aarch64_mem_pair_operand"
 243   (and (match_code "mem")
 244        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false,
 245                                                   ADDR_QUERY_LDP_STP)")))
 246
 247 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
 248 ;; as a 128-bit vec_concat.
 249 (define_predicate "aarch64_mem_pair_lanes_operand"
 250   (and (match_code "mem")
 251        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 252                                                   false,
 253                                                   ADDR_QUERY_LDP_STP_N)")))
 254
 255 (define_predicate "aarch64_prefetch_operand"
 256   (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
 257
 258 (define_predicate "aarch64_valid_symref"
 259   (match_code "const, symbol_ref, label_ref")
 260 {
 261   return (aarch64_classify_symbolic_expression (op)
 262           != SYMBOL_FORCE_TO_MEM);
 263 })
 264
 265 (define_predicate "aarch64_tls_ie_symref"
 266   (match_code "const, symbol_ref, label_ref")
 267 {
 268   switch (GET_CODE (op))
 269     {
 270     case CONST:
 271       op = XEXP (op, 0);
 272       if (GET_CODE (op) != PLUS
 273           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 274           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 275         return false;
 276       op = XEXP (op, 0);
 277       /* FALLTHRU */
 278
 279     case SYMBOL_REF:
 280       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 281
 282     default:
 283       gcc_unreachable ();
 284     }
 285 })
 286
 287 (define_predicate "aarch64_tls_le_symref"
 288   (match_code "const, symbol_ref, label_ref")
 289 {
 290   switch (GET_CODE (op))
 291     {
 292     case CONST:
 293       op = XEXP (op, 0);
 294       if (GET_CODE (op) != PLUS
 295           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 296           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 297         return false;
 298       op = XEXP (op, 0);
 299       /* FALLTHRU */
 300
 301     case SYMBOL_REF:
 302       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 303
 304     default:
 305       gcc_unreachable ();
 306     }
 307 })
 308
 309 (define_predicate "aarch64_mov_operand"
 310   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high,
 311                     const_poly_int,const_vector")
 312        (ior (match_operand 0 "register_operand")
 313             (ior (match_operand 0 "memory_operand")
 314                  (match_test "aarch64_mov_operand_p (op, mode)")))))
 315
 316 (define_predicate "aarch64_nonmemory_operand"
 317   (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high,
 318                     const_poly_int,const_vector")
 319        (ior (match_operand 0 "register_operand")
 320             (match_test "aarch64_mov_operand_p (op, mode)"))))
 321
 322 (define_predicate "aarch64_movti_operand"
 323   (ior (match_operand 0 "register_operand")
 324        (match_operand 0 "memory_operand")
 325        (and (match_operand 0 "const_scalar_int_operand")
 326             (match_test "aarch64_mov128_immediate (op)"))))
 327
 328 (define_predicate "aarch64_reg_or_imm"
 329   (ior (match_operand 0 "register_operand")
 330        (match_operand 0 "const_scalar_int_operand")))
 331
 332 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 333 (define_special_predicate "aarch64_comparison_operator"
 334   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 335                ordered,unlt,unle,unge,ungt"))
 336
 337 ;; Same as aarch64_comparison_operator but don't ignore the mode.
 338 ;; RTL SET operations require their operands source and destination have
 339 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 340 (define_predicate "aarch64_comparison_operator_mode"
 341   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 342                ordered,unlt,unle,unge,ungt"))
 343
 344 (define_special_predicate "aarch64_comparison_operation"
 345   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 346                ordered,unlt,unle,unge,ungt")
 347 {
 348   if (XEXP (op, 1) != const0_rtx)
 349     return false;
 350   rtx op0 = XEXP (op, 0);
 351   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 352     return false;
 353   return aarch64_get_condition_code (op) >= 0;
 354 })
 355
 356 (define_special_predicate "aarch64_equality_operator"
 357   (match_code "eq,ne"))
 358
 359 (define_special_predicate "aarch64_carry_operation"
 360   (match_code "ltu,geu")
 361 {
 362   if (XEXP (op, 1) != const0_rtx)
 363     return false;
 364   rtx op0 = XEXP (op, 0);
 365   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 366     return false;
 367   machine_mode ccmode = GET_MODE (op0);
 368   if (ccmode == CC_Cmode)
 369     return GET_CODE (op) == LTU;
 370   if (ccmode == CC_ADCmode || ccmode == CCmode)
 371     return GET_CODE (op) == GEU;
 372   return false;
 373 })
 374
 375 ; borrow is essentially the inverse of carry since the sense of the C flag
 376 ; is inverted during subtraction.  See the note in aarch64-modes.def.
 377 (define_special_predicate "aarch64_borrow_operation"
 378   (match_code "geu,ltu")
 379 {
 380   if (XEXP (op, 1) != const0_rtx)
 381     return false;
 382   rtx op0 = XEXP (op, 0);
 383   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 384     return false;
 385   machine_mode ccmode = GET_MODE (op0);
 386   if (ccmode == CC_Cmode)
 387     return GET_CODE (op) == GEU;
 388   if (ccmode == CC_ADCmode || ccmode == CCmode)
 389     return GET_CODE (op) == LTU;
 390   return false;
 391 })
 392
 393 ;; True if the operand is memory reference suitable for a load/store exclusive.
 394 (define_predicate "aarch64_sync_memory_operand"
 395   (and (match_operand 0 "memory_operand")
 396        (match_code "reg" "0")))
 397
 398 (define_predicate "aarch64_9bit_offset_memory_operand"
 399   (and (match_operand 0 "memory_operand")
 400        (ior (match_code "reg" "0")
 401             (and (match_code "plus" "0")
 402                  (match_code "reg"  "00")
 403                  (match_code "const_int" "01"))))
 404 {
 405   rtx mem_op = XEXP (op, 0);
 406
 407   if (REG_P (mem_op))
 408     return GET_MODE (mem_op) == DImode;
 409
 410   rtx plus_op0 = XEXP (mem_op, 0);
 411   rtx plus_op1 = XEXP (mem_op, 1);
 412
 413   if (GET_MODE (plus_op0) != DImode)
 414     return false;
 415
 416   poly_int64 offset;
 417   if (!poly_int_rtx_p (plus_op1, &offset))
 418     gcc_unreachable ();
 419
 420   return aarch64_offset_9bit_signed_unscaled_p (mode, offset);
 421 })
 422
 423 (define_predicate "aarch64_rcpc_memory_operand"
 424   (if_then_else (match_test "AARCH64_ISA_RCPC8_4")
 425     (match_operand 0 "aarch64_9bit_offset_memory_operand")
 426     (match_operand 0 "aarch64_sync_memory_operand")))
 427
 428 ;; Predicates for parallel expanders based on mode.
 429 (define_special_predicate "vect_par_cnst_hi_half"
 430   (match_code "parallel")
 431 {
 432   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 433 })
 434
 435 (define_special_predicate "vect_par_cnst_lo_half"
 436   (match_code "parallel")
 437 {
 438   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 439 })
 440
 441 (define_predicate "descending_int_parallel"
 442   (match_code "parallel")
 443 {
 444   return aarch64_stepped_int_parallel_p (op, -1);
 445 })
 446
 447 (define_special_predicate "aarch64_simd_lshift_imm"
 448   (match_code "const,const_vector")
 449 {
 450   return aarch64_simd_shift_imm_p (op, mode, true);
 451 })
 452
 453 (define_special_predicate "aarch64_simd_rshift_imm"
 454   (match_code "const,const_vector")
 455 {
 456   return aarch64_simd_shift_imm_p (op, mode, false);
 457 })
 458
 459 (define_predicate "aarch64_simd_imm_zero"
 460   (and (match_code "const,const_vector")
 461        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 462
 463 (define_predicate "aarch64_simd_or_scalar_imm_zero"
 464   (and (match_code "const_int,const_double,const,const_vector")
 465        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 466
 467 (define_predicate "aarch64_simd_imm_minus_one"
 468   (and (match_code "const,const_vector")
 469        (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
 470
 471 (define_predicate "aarch64_simd_reg_or_zero"
 472   (and (match_code "reg,subreg,const_int,const_double,const,const_vector")
 473        (ior (match_operand 0 "register_operand")
 474             (match_test "op == const0_rtx")
 475             (match_operand 0 "aarch64_simd_or_scalar_imm_zero"))))
 476
 477 (define_predicate "aarch64_simd_struct_operand"
 478   (and (match_code "mem")
 479        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 480
 481 ;; Like general_operand but allow only valid SIMD addressing modes.
 482 (define_predicate "aarch64_simd_general_operand"
 483   (and (match_operand 0 "general_operand")
 484        (match_test "!MEM_P (op)
 485                     || GET_CODE (XEXP (op, 0)) == POST_INC
 486                     || GET_CODE (XEXP (op, 0)) == REG")))
 487
 488 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 489 (define_predicate "aarch64_simd_nonimmediate_operand"
 490   (and (match_operand 0 "nonimmediate_operand")
 491        (match_test "!MEM_P (op)
 492                     || GET_CODE (XEXP (op, 0)) == POST_INC
 493                     || GET_CODE (XEXP (op, 0)) == REG")))
 494
 495 ;; Predicates used by the various SIMD shift operations.  These
 496 ;; fall in to 3 categories.
 497 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 498 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 499 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 500 (define_predicate "aarch64_simd_shift_imm_qi"
 501   (and (match_code "const_int")
 502        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 503
 504 (define_predicate "aarch64_simd_shift_imm_hi"
 505   (and (match_code "const_int")
 506        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 507
 508 (define_predicate "aarch64_simd_shift_imm_si"
 509   (and (match_code "const_int")
 510        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 511
 512 (define_predicate "aarch64_simd_shift_imm_di"
 513   (and (match_code "const_int")
 514        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 515
 516 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 517   (and (match_code "const_int")
 518        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 519
 520 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 521   (and (match_code "const_int")
 522        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 523
 524 (define_predicate "aarch64_simd_shift_imm_offset_si"
 525   (and (match_code "const_int")
 526        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 527
 528 (define_predicate "aarch64_simd_shift_imm_offset_di"
 529   (and (match_code "const_int")
 530        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 531
 532 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 533   (and (match_code "const_int")
 534        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 535
 536 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 537   (and (match_code "const_int")
 538        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 539
 540 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 541   (and (match_code "const_int")
 542        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 543
 544 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 545   (and (match_code "const_int")
 546        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
 547
 548 (define_predicate "aarch64_constant_pool_symref"
 549    (and (match_code "symbol_ref")
 550         (match_test "CONSTANT_POOL_ADDRESS_P (op)")))
 551
 552 (define_predicate "aarch64_constant_vector_operand"
 553   (match_code "const,const_vector"))
 554
 555 (define_predicate "aarch64_sve_ld1r_operand"
 556   (and (match_operand 0 "memory_operand")
 557        (match_test "aarch64_sve_ld1r_operand_p (op)")))
 558
 559 (define_predicate "aarch64_sve_ld1rq_operand"
 560   (and (match_code "mem")
 561        (match_test "aarch64_sve_ld1rq_operand_p (op)")))
 562
 563 ;; Like memory_operand, but restricted to addresses that are valid for
 564 ;; SVE LDR and STR instructions.
 565 (define_predicate "aarch64_sve_ldr_operand"
 566   (and (match_code "mem")
 567        (match_test "aarch64_sve_ldr_operand_p (op)")))
 568
 569 (define_predicate "aarch64_sve_nonimmediate_operand"
 570   (ior (match_operand 0 "register_operand")
 571        (match_operand 0 "aarch64_sve_ldr_operand")))
 572
 573 (define_predicate "aarch64_sve_general_operand"
 574   (and (match_code "reg,subreg,mem,const,const_vector")
 575        (ior (match_operand 0 "register_operand")
 576             (match_operand 0 "aarch64_sve_ldr_operand")
 577             (match_test "aarch64_mov_operand_p (op, mode)"))))
 578
 579 (define_predicate "aarch64_sve_struct_memory_operand"
 580   (and (match_code "mem")
 581        (match_test "aarch64_sve_struct_memory_operand_p (op)")))
 582
 583 (define_predicate "aarch64_sve_struct_nonimmediate_operand"
 584   (ior (match_operand 0 "register_operand")
 585        (match_operand 0 "aarch64_sve_struct_memory_operand")))
 586
 587 ;; Doesn't include immediates, since those are handled by the move
 588 ;; patterns instead.
 589 (define_predicate "aarch64_sve_dup_operand"
 590   (ior (match_operand 0 "register_operand")
 591        (match_operand 0 "aarch64_sve_ld1r_operand")))
 592
 593 (define_predicate "aarch64_sve_arith_immediate"
 594   (and (match_code "const,const_vector")
 595        (match_test "aarch64_sve_arith_immediate_p (op, false)")))
 596
 597 (define_predicate "aarch64_sve_sub_arith_immediate"
 598   (and (match_code "const,const_vector")
 599        (match_test "aarch64_sve_arith_immediate_p (op, true)")))
 600
 601 (define_predicate "aarch64_sve_inc_dec_immediate"
 602   (and (match_code "const,const_vector")
 603        (match_test "aarch64_sve_inc_dec_immediate_p (op)")))
 604
 605 (define_predicate "aarch64_sve_uxtw_immediate"
 606   (and (match_code "const_vector")
 607        (match_test "GET_MODE_UNIT_BITSIZE (GET_MODE (op)) > 32")
 608        (match_test "aarch64_const_vec_all_same_int_p (op, 0xffffffff)")))
 609
 610 (define_predicate "aarch64_sve_logical_immediate"
 611   (and (match_code "const,const_vector")
 612        (match_test "aarch64_sve_bitmask_immediate_p (op)")))
 613
 614 (define_predicate "aarch64_sve_mul_immediate"
 615   (and (match_code "const,const_vector")
 616        (match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)")))
 617
 618 (define_predicate "aarch64_sve_dup_immediate"
 619   (and (match_code "const,const_vector")
 620        (match_test "aarch64_sve_dup_immediate_p (op)")))
 621
 622 (define_predicate "aarch64_sve_cmp_vsc_immediate"
 623   (and (match_code "const,const_vector")
 624        (match_test "aarch64_sve_cmp_immediate_p (op, true)")))
 625
 626 (define_predicate "aarch64_sve_cmp_vsd_immediate"
 627   (and (match_code "const,const_vector")
 628        (match_test "aarch64_sve_cmp_immediate_p (op, false)")))
 629
 630 (define_predicate "aarch64_sve_index_immediate"
 631   (and (match_code "const_int")
 632        (match_test "aarch64_sve_index_immediate_p (op)")))
 633
 634 (define_predicate "aarch64_sve_float_arith_immediate"
 635   (and (match_code "const,const_vector")
 636        (match_test "aarch64_sve_float_arith_immediate_p (op, false)")))
 637
 638 (define_predicate "aarch64_sve_float_arith_with_sub_immediate"
 639   (and (match_code "const,const_vector")
 640        (match_test "aarch64_sve_float_arith_immediate_p (op, true)")))
 641
 642 (define_predicate "aarch64_sve_float_mul_immediate"
 643   (and (match_code "const,const_vector")
 644        (match_test "aarch64_sve_float_mul_immediate_p (op)")))
 645
 646 (define_predicate "aarch64_sve_arith_operand"
 647   (ior (match_operand 0 "register_operand")
 648        (match_operand 0 "aarch64_sve_arith_immediate")))
 649
 650 (define_predicate "aarch64_sve_add_operand"
 651   (ior (match_operand 0 "aarch64_sve_arith_operand")
 652        (match_operand 0 "aarch64_sve_sub_arith_immediate")
 653        (match_operand 0 "aarch64_sve_inc_dec_immediate")))
 654
 655 (define_predicate "aarch64_sve_logical_operand"
 656   (ior (match_operand 0 "register_operand")
 657        (match_operand 0 "aarch64_sve_logical_immediate")))
 658
 659 (define_predicate "aarch64_sve_lshift_operand"
 660   (ior (match_operand 0 "register_operand")
 661        (match_operand 0 "aarch64_simd_lshift_imm")))
 662
 663 (define_predicate "aarch64_sve_rshift_operand"
 664   (ior (match_operand 0 "register_operand")
 665        (match_operand 0 "aarch64_simd_rshift_imm")))
 666
 667 (define_predicate "aarch64_sve_mul_operand"
 668   (ior (match_operand 0 "register_operand")
 669        (match_operand 0 "aarch64_sve_mul_immediate")))
 670
 671 (define_predicate "aarch64_sve_cmp_vsc_operand"
 672   (ior (match_operand 0 "register_operand")
 673        (match_operand 0 "aarch64_sve_cmp_vsc_immediate")))
 674
 675 (define_predicate "aarch64_sve_cmp_vsd_operand"
 676   (ior (match_operand 0 "register_operand")
 677        (match_operand 0 "aarch64_sve_cmp_vsd_immediate")))
 678
 679 (define_predicate "aarch64_sve_index_operand"
 680   (ior (match_operand 0 "register_operand")
 681        (match_operand 0 "aarch64_sve_index_immediate")))
 682
 683 (define_predicate "aarch64_sve_float_arith_operand"
 684   (ior (match_operand 0 "register_operand")
 685        (match_operand 0 "aarch64_sve_float_arith_immediate")))
 686
 687 (define_predicate "aarch64_sve_float_arith_with_sub_operand"
 688   (ior (match_operand 0 "aarch64_sve_float_arith_operand")
 689        (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate")))
 690
 691 (define_predicate "aarch64_sve_float_mul_operand"
 692   (ior (match_operand 0 "register_operand")
 693        (match_operand 0 "aarch64_sve_float_mul_immediate")))
 694
 695 (define_predicate "aarch64_sve_vec_perm_operand"
 696   (ior (match_operand 0 "register_operand")
 697        (match_operand 0 "aarch64_constant_vector_operand")))
 698
 699 (define_predicate "aarch64_sve_ptrue_flag"
 700   (and (match_code "const_int")
 701        (ior (match_test "INTVAL (op) == SVE_MAYBE_NOT_PTRUE")
 702             (match_test "INTVAL (op) == SVE_KNOWN_PTRUE"))))
 703
 704 (define_predicate "aarch64_sve_gp_strictness"
 705   (and (match_code "const_int")
 706        (ior (match_test "INTVAL (op) == SVE_RELAXED_GP")
 707             (match_test "INTVAL (op) == SVE_STRICT_GP"))))
 708
 709 (define_predicate "aarch64_gather_scale_operand_w"
 710   (and (match_code "const_int")
 711        (match_test "INTVAL (op) == 1 || INTVAL (op) == 4")))
 712
 713 (define_predicate "aarch64_gather_scale_operand_d"
 714   (and (match_code "const_int")
 715        (match_test "INTVAL (op) == 1 || INTVAL (op) == 8")))
 716
 717 ;; A special predicate that doesn't match a particular mode.
 718 (define_special_predicate "aarch64_any_register_operand"
 719   (match_code "reg"))
 720
 721 (define_predicate "aarch64_sve_any_binary_operator"
 722   (match_code "plus,minus,mult,div,udiv,smax,umax,smin,umin,and,ior,xor"))