gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2013 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_reg_or_zero"
  30   (and (match_code "reg,subreg,const_int")
  31        (ior (match_operand 0 "register_operand")
  32             (match_test "op == const0_rtx"))))
  33
  34 (define_predicate "aarch64_reg_or_fp_zero"
  35   (and (match_code "reg,subreg,const_double")
  36        (ior (match_operand 0 "register_operand")
  37             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  38
  39 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  40   (and (match_code "reg,subreg,const_int")
  41        (ior (match_operand 0 "register_operand")
  42             (ior (match_test "op == const0_rtx")
  43                  (ior (match_test "op == constm1_rtx")
  44                       (match_test "op == const1_rtx"))))))
  45
  46 (define_predicate "aarch64_fp_compare_operand"
  47   (ior (match_operand 0 "register_operand")
  48        (and (match_code "const_double")
  49             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  50
  51 (define_predicate "aarch64_plus_immediate"
  52   (and (match_code "const_int")
  53        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
  54             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
  55
  56 (define_predicate "aarch64_plus_operand"
  57   (ior (match_operand 0 "register_operand")
  58        (match_operand 0 "aarch64_plus_immediate")))
  59
  60 (define_predicate "aarch64_pluslong_immediate"
  61   (and (match_code "const_int")
  62        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
  63
  64 (define_predicate "aarch64_pluslong_operand"
  65   (ior (match_operand 0 "register_operand")
  66        (match_operand 0 "aarch64_pluslong_immediate")))
  67
  68 (define_predicate "aarch64_logical_immediate"
  69   (and (match_code "const_int")
  70        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
  71
  72 (define_predicate "aarch64_logical_operand"
  73   (ior (match_operand 0 "register_operand")
  74        (match_operand 0 "aarch64_logical_immediate")))
  75
  76 (define_predicate "aarch64_shift_imm_si"
  77   (and (match_code "const_int")
  78        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
  79
  80 (define_predicate "aarch64_shift_imm_di"
  81   (and (match_code "const_int")
  82        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
  83
  84 (define_predicate "aarch64_reg_or_shift_imm_si"
  85   (ior (match_operand 0 "register_operand")
  86        (match_operand 0 "aarch64_shift_imm_si")))
  87
  88 (define_predicate "aarch64_reg_or_shift_imm_di"
  89   (ior (match_operand 0 "register_operand")
  90        (match_operand 0 "aarch64_shift_imm_di")))
  91
  92 ;; The imm3 field is a 3-bit field that only accepts immediates in the
  93 ;; range 0..4.
  94 (define_predicate "aarch64_imm3"
  95   (and (match_code "const_int")
  96        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
  97
  98 (define_predicate "aarch64_pwr_imm3"
  99   (and (match_code "const_int")
 100        (match_test "INTVAL (op) != 0
 101                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 102
 103 (define_predicate "aarch64_pwr_2_si"
 104   (and (match_code "const_int")
 105        (match_test "INTVAL (op) != 0
 106                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 107
 108 (define_predicate "aarch64_pwr_2_di"
 109   (and (match_code "const_int")
 110        (match_test "INTVAL (op) != 0
 111                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 112
 113 (define_predicate "aarch64_mem_pair_operand"
 114   (and (match_code "mem")
 115        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
 116                                                0)")))
 117
 118 (define_predicate "aarch64_valid_symref"
 119   (match_code "const, symbol_ref, label_ref")
 120 {
 121   enum aarch64_symbol_type symbol_type;
 122   return (aarch64_symbolic_constant_p (op, SYMBOL_CONTEXT_ADR, &symbol_type)
 123          && symbol_type != SYMBOL_FORCE_TO_MEM);
 124 })
 125
 126 (define_predicate "aarch64_tls_ie_symref"
 127   (match_code "const, symbol_ref, label_ref")
 128 {
 129   switch (GET_CODE (op))
 130     {
 131     case CONST:
 132       op = XEXP (op, 0);
 133       if (GET_CODE (op) != PLUS
 134           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 135           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 136         return false;
 137       op = XEXP (op, 0);
 138
 139     case SYMBOL_REF:
 140       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 141
 142     default:
 143       gcc_unreachable ();
 144     }
 145 })
 146
 147 (define_predicate "aarch64_tls_le_symref"
 148   (match_code "const, symbol_ref, label_ref")
 149 {
 150   switch (GET_CODE (op))
 151     {
 152     case CONST:
 153       op = XEXP (op, 0);
 154       if (GET_CODE (op) != PLUS
 155           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 156           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 157         return false;
 158       op = XEXP (op, 0);
 159
 160     case SYMBOL_REF:
 161       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 162
 163     default:
 164       gcc_unreachable ();
 165     }
 166 })
 167
 168 (define_predicate "aarch64_mov_operand"
 169   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high")
 170        (ior (match_operand 0 "register_operand")
 171             (ior (match_operand 0 "memory_operand")
 172                  (match_test "aarch64_mov_operand_p (op, SYMBOL_CONTEXT_ADR, mode)")))))
 173
 174 (define_predicate "aarch64_movti_operand"
 175   (and (match_code "reg,subreg,mem,const_int")
 176        (ior (match_operand 0 "register_operand")
 177             (ior (match_operand 0 "memory_operand")
 178                  (match_operand 0 "const_int_operand")))))
 179
 180 (define_predicate "aarch64_reg_or_imm"
 181   (and (match_code "reg,subreg,const_int")
 182        (ior (match_operand 0 "register_operand")
 183             (match_operand 0 "const_int_operand"))))
 184
 185 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 186 (define_special_predicate "aarch64_comparison_operator"
 187   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
 188
 189 ;; True if the operand is memory reference suitable for a load/store exclusive.
 190 (define_predicate "aarch64_sync_memory_operand"
 191   (and (match_operand 0 "memory_operand")
 192        (match_code "reg" "0")))
 193
 194 ;; Predicates for parallel expanders based on mode.
 195 (define_special_predicate "vect_par_cnst_hi_half"
 196   (match_code "parallel")
 197 {
 198   HOST_WIDE_INT count = XVECLEN (op, 0);
 199   int nunits = GET_MODE_NUNITS (mode);
 200   int i;
 201
 202   if (count < 1
 203       || count != nunits / 2)
 204     return false;
 205
 206   if (!VECTOR_MODE_P (mode))
 207     return false;
 208
 209   for (i = 0; i < count; i++)
 210    {
 211      rtx elt = XVECEXP (op, 0, i);
 212      int val;
 213
 214      if (GET_CODE (elt) != CONST_INT)
 215        return false;
 216
 217      val = INTVAL (elt);
 218      if (val != (nunits / 2) + i)
 219        return false;
 220    }
 221   return true;
 222 })
 223
 224 (define_special_predicate "vect_par_cnst_lo_half"
 225   (match_code "parallel")
 226 {
 227   HOST_WIDE_INT count = XVECLEN (op, 0);
 228   int nunits = GET_MODE_NUNITS (mode);
 229   int i;
 230
 231   if (count < 1
 232       || count != nunits / 2)
 233     return false;
 234
 235   if (!VECTOR_MODE_P (mode))
 236     return false;
 237
 238   for (i = 0; i < count; i++)
 239    {
 240      rtx elt = XVECEXP (op, 0, i);
 241      int val;
 242
 243      if (GET_CODE (elt) != CONST_INT)
 244        return false;
 245
 246      val = INTVAL (elt);
 247      if (val != i)
 248        return false;
 249    }
 250   return true;
 251 })
 252
 253
 254 (define_special_predicate "aarch64_simd_lshift_imm"
 255   (match_code "const_vector")
 256 {
 257   return aarch64_simd_shift_imm_p (op, mode, true);
 258 })
 259
 260 (define_special_predicate "aarch64_simd_rshift_imm"
 261   (match_code "const_vector")
 262 {
 263   return aarch64_simd_shift_imm_p (op, mode, false);
 264 })
 265
 266 (define_predicate "aarch64_simd_reg_or_zero"
 267   (and (match_code "reg,subreg,const_int,const_vector")
 268        (ior (match_operand 0 "register_operand")
 269            (ior (match_test "op == const0_rtx")
 270                 (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
 271
 272 (define_predicate "aarch64_simd_struct_operand"
 273   (and (match_code "mem")
 274        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 275
 276 ;; Like general_operand but allow only valid SIMD addressing modes.
 277 (define_predicate "aarch64_simd_general_operand"
 278   (and (match_operand 0 "general_operand")
 279        (match_test "!MEM_P (op)
 280                     || GET_CODE (XEXP (op, 0)) == POST_INC
 281                     || GET_CODE (XEXP (op, 0)) == REG")))
 282
 283 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 284 (define_predicate "aarch64_simd_nonimmediate_operand"
 285   (and (match_operand 0 "nonimmediate_operand")
 286        (match_test "!MEM_P (op)
 287                     || GET_CODE (XEXP (op, 0)) == POST_INC
 288                     || GET_CODE (XEXP (op, 0)) == REG")))
 289
 290 (define_special_predicate "aarch64_simd_imm_zero"
 291   (match_code "const_vector")
 292 {
 293   return aarch64_simd_imm_zero_p (op, mode);
 294 })