gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 ;; Return true if OP a (const_int 0) operand.
  34 (define_predicate "const0_operand"
  35   (and (match_code "const_int")
  36        (match_test "op == CONST0_RTX (mode)")))
  37
  38 (define_special_predicate "subreg_lowpart_operator"
  39   (and (match_code "subreg")
  40        (match_test "subreg_lowpart_p (op)")))
  41
  42 (define_predicate "aarch64_ccmp_immediate"
  43   (and (match_code "const_int")
  44        (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
  45
  46 (define_predicate "aarch64_ccmp_operand"
  47   (ior (match_operand 0 "register_operand")
  48        (match_operand 0 "aarch64_ccmp_immediate")))
  49
  50 (define_predicate "aarch64_simd_register"
  51   (and (match_code "reg")
  52        (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
  53             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
  54
  55 (define_predicate "aarch64_reg_or_zero"
  56   (and (match_code "reg,subreg,const_int")
  57        (ior (match_operand 0 "register_operand")
  58             (match_test "op == const0_rtx"))))
  59
  60 (define_predicate "aarch64_reg_or_fp_zero"
  61   (ior (match_operand 0 "register_operand")
  62         (and (match_code "const_double")
  63              (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  64
  65 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  66   (and (match_code "reg,subreg,const_int")
  67        (ior (match_operand 0 "register_operand")
  68             (ior (match_test "op == const0_rtx")
  69                  (ior (match_test "op == constm1_rtx")
  70                       (match_test "op == const1_rtx"))))))
  71
  72 (define_predicate "aarch64_reg_or_orr_imm"
  73    (ior (match_operand 0 "register_operand")
  74         (match_test "aarch64_simd_valid_immediate (op, mode, false,
  75                                                    NULL, AARCH64_CHECK_ORR)")))
  76
  77 (define_predicate "aarch64_reg_or_bic_imm"
  78    (ior (match_operand 0 "register_operand")
  79         (match_test "aarch64_simd_valid_immediate (op, mode, false,
  80                                                    NULL, AARCH64_CHECK_BIC)")))
  81
  82 (define_predicate "aarch64_fp_compare_operand"
  83   (ior (match_operand 0 "register_operand")
  84        (and (match_code "const_double")
  85             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  86
  87 (define_predicate "aarch64_fp_pow2"
  88   (and (match_code "const_double")
  89         (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
  90
  91 (define_predicate "aarch64_fp_vec_pow2"
  92   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
  93
  94 (define_predicate "aarch64_sub_immediate"
  95   (and (match_code "const_int")
  96        (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
  97
  98 (define_predicate "aarch64_plus_immediate"
  99   (and (match_code "const_int")
 100        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
 101             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
 102
 103 (define_predicate "aarch64_plus_operand"
 104   (ior (match_operand 0 "register_operand")
 105        (match_operand 0 "aarch64_plus_immediate")))
 106
 107 (define_predicate "aarch64_pluslong_immediate"
 108   (and (match_code "const_int")
 109        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
 110
 111 (define_predicate "aarch64_pluslong_strict_immedate"
 112   (and (match_operand 0 "aarch64_pluslong_immediate")
 113        (not (match_operand 0 "aarch64_plus_immediate"))))
 114
 115 (define_predicate "aarch64_pluslong_operand"
 116   (ior (match_operand 0 "register_operand")
 117        (match_operand 0 "aarch64_pluslong_immediate")))
 118
 119 (define_predicate "aarch64_logical_immediate"
 120   (and (match_code "const_int")
 121        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
 122
 123 (define_predicate "aarch64_logical_operand"
 124   (ior (match_operand 0 "register_operand")
 125        (match_operand 0 "aarch64_logical_immediate")))
 126
 127 (define_predicate "aarch64_mov_imm_operand"
 128   (and (match_code "const_int")
 129        (match_test "aarch64_move_imm (INTVAL (op), mode)")))
 130
 131 (define_predicate "aarch64_logical_and_immediate"
 132   (and (match_code "const_int")
 133        (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
 134
 135 (define_predicate "aarch64_shift_imm_si"
 136   (and (match_code "const_int")
 137        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
 138
 139 (define_predicate "aarch64_shift_imm_di"
 140   (and (match_code "const_int")
 141        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
 142
 143 (define_predicate "aarch64_shift_imm64_di"
 144   (and (match_code "const_int")
 145        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
 146
 147 (define_predicate "aarch64_reg_or_shift_imm_si"
 148   (ior (match_operand 0 "register_operand")
 149        (match_operand 0 "aarch64_shift_imm_si")))
 150
 151 (define_predicate "aarch64_reg_or_shift_imm_di"
 152   (ior (match_operand 0 "register_operand")
 153        (match_operand 0 "aarch64_shift_imm_di")))
 154
 155 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 156 ;; range 0..4.
 157 (define_predicate "aarch64_imm3"
 158   (and (match_code "const_int")
 159        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 160
 161 ;; An immediate that fits into 24 bits.
 162 (define_predicate "aarch64_imm24"
 163   (and (match_code "const_int")
 164        (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
 165
 166 (define_predicate "aarch64_pwr_imm3"
 167   (and (match_code "const_int")
 168        (match_test "INTVAL (op) != 0
 169                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 170
 171 (define_predicate "aarch64_pwr_2_si"
 172   (and (match_code "const_int")
 173        (match_test "INTVAL (op) != 0
 174                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 175
 176 (define_predicate "aarch64_pwr_2_di"
 177   (and (match_code "const_int")
 178        (match_test "INTVAL (op) != 0
 179                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 180
 181 (define_predicate "aarch64_mem_pair_offset"
 182   (and (match_code "const_int")
 183        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 184
 185 (define_predicate "aarch64_mem_pair_operand"
 186   (and (match_code "mem")
 187        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
 188                                                0)")))
 189
 190 (define_predicate "aarch64_prefetch_operand"
 191   (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
 192
 193 (define_predicate "aarch64_valid_symref"
 194   (match_code "const, symbol_ref, label_ref")
 195 {
 196   return (aarch64_classify_symbolic_expression (op)
 197           != SYMBOL_FORCE_TO_MEM);
 198 })
 199
 200 (define_predicate "aarch64_tls_ie_symref"
 201   (match_code "const, symbol_ref, label_ref")
 202 {
 203   switch (GET_CODE (op))
 204     {
 205     case CONST:
 206       op = XEXP (op, 0);
 207       if (GET_CODE (op) != PLUS
 208           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 209           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 210         return false;
 211       op = XEXP (op, 0);
 212       /* FALLTHRU */
 213
 214     case SYMBOL_REF:
 215       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 216
 217     default:
 218       gcc_unreachable ();
 219     }
 220 })
 221
 222 (define_predicate "aarch64_tls_le_symref"
 223   (match_code "const, symbol_ref, label_ref")
 224 {
 225   switch (GET_CODE (op))
 226     {
 227     case CONST:
 228       op = XEXP (op, 0);
 229       if (GET_CODE (op) != PLUS
 230           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 231           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 232         return false;
 233       op = XEXP (op, 0);
 234       /* FALLTHRU */
 235
 236     case SYMBOL_REF:
 237       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 238
 239     default:
 240       gcc_unreachable ();
 241     }
 242 })
 243
 244 (define_predicate "aarch64_mov_operand"
 245   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high")
 246        (ior (match_operand 0 "register_operand")
 247             (ior (match_operand 0 "memory_operand")
 248                  (match_test "aarch64_mov_operand_p (op, mode)")))))
 249
 250 (define_predicate "aarch64_movti_operand"
 251   (and (match_code "reg,subreg,mem,const_int")
 252        (ior (match_operand 0 "register_operand")
 253             (ior (match_operand 0 "memory_operand")
 254                  (match_operand 0 "const_int_operand")))))
 255
 256 (define_predicate "aarch64_reg_or_imm"
 257   (and (match_code "reg,subreg,const_int")
 258        (ior (match_operand 0 "register_operand")
 259             (match_operand 0 "const_int_operand"))))
 260
 261 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 262 (define_special_predicate "aarch64_comparison_operator"
 263   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 264                ordered,unlt,unle,unge,ungt"))
 265
 266 ;; Same as aarch64_comparison_operator but don't ignore the mode.
 267 ;; RTL SET operations require their operands source and destination have
 268 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 269 (define_predicate "aarch64_comparison_operator_mode"
 270   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 271                ordered,unlt,unle,unge,ungt"))
 272
 273 (define_special_predicate "aarch64_comparison_operation"
 274   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 275                ordered,unlt,unle,unge,ungt")
 276 {
 277   if (XEXP (op, 1) != const0_rtx)
 278     return false;
 279   rtx op0 = XEXP (op, 0);
 280   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 281     return false;
 282   return aarch64_get_condition_code (op) >= 0;
 283 })
 284
 285 (define_special_predicate "aarch64_carry_operation"
 286   (match_code "ne,geu")
 287 {
 288   if (XEXP (op, 1) != const0_rtx)
 289     return false;
 290   machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
 291   rtx op0 = XEXP (op, 0);
 292   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 293 })
 294
 295 (define_special_predicate "aarch64_borrow_operation"
 296   (match_code "eq,ltu")
 297 {
 298   if (XEXP (op, 1) != const0_rtx)
 299     return false;
 300   machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
 301   rtx op0 = XEXP (op, 0);
 302   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 303 })
 304
 305 ;; True if the operand is memory reference suitable for a load/store exclusive.
 306 (define_predicate "aarch64_sync_memory_operand"
 307   (and (match_operand 0 "memory_operand")
 308        (match_code "reg" "0")))
 309
 310 ;; Predicates for parallel expanders based on mode.
 311 (define_special_predicate "vect_par_cnst_hi_half"
 312   (match_code "parallel")
 313 {
 314   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 315 })
 316
 317 (define_special_predicate "vect_par_cnst_lo_half"
 318   (match_code "parallel")
 319 {
 320   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 321 })
 322
 323 (define_special_predicate "aarch64_simd_lshift_imm"
 324   (match_code "const_vector")
 325 {
 326   return aarch64_simd_shift_imm_p (op, mode, true);
 327 })
 328
 329 (define_special_predicate "aarch64_simd_rshift_imm"
 330   (match_code "const_vector")
 331 {
 332   return aarch64_simd_shift_imm_p (op, mode, false);
 333 })
 334
 335 (define_predicate "aarch64_simd_reg_or_zero"
 336   (and (match_code "reg,subreg,const_int,const_double,const_vector")
 337        (ior (match_operand 0 "register_operand")
 338            (ior (match_test "op == const0_rtx")
 339                 (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
 340
 341 (define_predicate "aarch64_simd_struct_operand"
 342   (and (match_code "mem")
 343        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 344
 345 ;; Like general_operand but allow only valid SIMD addressing modes.
 346 (define_predicate "aarch64_simd_general_operand"
 347   (and (match_operand 0 "general_operand")
 348        (match_test "!MEM_P (op)
 349                     || GET_CODE (XEXP (op, 0)) == POST_INC
 350                     || GET_CODE (XEXP (op, 0)) == REG")))
 351
 352 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 353 (define_predicate "aarch64_simd_nonimmediate_operand"
 354   (and (match_operand 0 "nonimmediate_operand")
 355        (match_test "!MEM_P (op)
 356                     || GET_CODE (XEXP (op, 0)) == POST_INC
 357                     || GET_CODE (XEXP (op, 0)) == REG")))
 358
 359 (define_special_predicate "aarch64_simd_imm_zero"
 360   (match_code "const_vector")
 361 {
 362   return aarch64_simd_imm_zero_p (op, mode);
 363 })
 364
 365 (define_special_predicate "aarch64_simd_imm_minus_one"
 366   (match_code "const_vector")
 367 {
 368   return aarch64_const_vec_all_same_int_p (op, -1);
 369 })
 370
 371 ;; Predicates used by the various SIMD shift operations.  These
 372 ;; fall in to 3 categories.
 373 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 374 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 375 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 376 (define_predicate "aarch64_simd_shift_imm_qi"
 377   (and (match_code "const_int")
 378        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 379
 380 (define_predicate "aarch64_simd_shift_imm_hi"
 381   (and (match_code "const_int")
 382        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 383
 384 (define_predicate "aarch64_simd_shift_imm_si"
 385   (and (match_code "const_int")
 386        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 387
 388 (define_predicate "aarch64_simd_shift_imm_di"
 389   (and (match_code "const_int")
 390        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 391
 392 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 393   (and (match_code "const_int")
 394        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 395
 396 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 397   (and (match_code "const_int")
 398        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 399
 400 (define_predicate "aarch64_simd_shift_imm_offset_si"
 401   (and (match_code "const_int")
 402        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 403
 404 (define_predicate "aarch64_simd_shift_imm_offset_di"
 405   (and (match_code "const_int")
 406        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 407
 408 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 409   (and (match_code "const_int")
 410        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 411
 412 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 413   (and (match_code "const_int")
 414        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 415
 416 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 417   (and (match_code "const_int")
 418        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 419
 420 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 421   (and (match_code "const_int")
 422        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
 423
 424 (define_predicate "aarch64_constant_pool_symref"
 425    (and (match_code "symbol_ref")
 426         (match_test "CONSTANT_POOL_ADDRESS_P (op)")))