gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 ;; Return true if OP a (const_int 0) operand.
  34 (define_predicate "const0_operand"
  35   (and (match_code "const_int")
  36        (match_test "op == CONST0_RTX (mode)")))
  37
  38 (define_special_predicate "subreg_lowpart_operator"
  39   (and (match_code "subreg")
  40        (match_test "subreg_lowpart_p (op)")))
  41
  42 (define_predicate "aarch64_ccmp_immediate"
  43   (and (match_code "const_int")
  44        (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
  45
  46 (define_predicate "aarch64_ccmp_operand"
  47   (ior (match_operand 0 "register_operand")
  48        (match_operand 0 "aarch64_ccmp_immediate")))
  49
  50 (define_predicate "aarch64_simd_register"
  51   (and (match_code "reg")
  52        (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
  53             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
  54
  55 (define_predicate "aarch64_reg_or_zero"
  56   (and (match_code "reg,subreg,const_int")
  57        (ior (match_operand 0 "register_operand")
  58             (match_test "op == const0_rtx"))))
  59
  60 (define_predicate "aarch64_reg_or_fp_zero"
  61   (ior (match_operand 0 "register_operand")
  62         (and (match_code "const_double")
  63              (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  64
  65 (define_predicate "aarch64_reg_zero_or_fp_zero"
  66   (ior (match_operand 0 "aarch64_reg_or_fp_zero")
  67        (match_operand 0 "aarch64_reg_or_zero")))
  68
  69 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  70   (and (match_code "reg,subreg,const_int")
  71        (ior (match_operand 0 "register_operand")
  72             (ior (match_test "op == const0_rtx")
  73                  (ior (match_test "op == constm1_rtx")
  74                       (match_test "op == const1_rtx"))))))
  75
  76 (define_predicate "aarch64_reg_or_orr_imm"
  77    (ior (match_operand 0 "register_operand")
  78         (and (match_code "const_vector")
  79              (match_test "aarch64_simd_valid_immediate (op, NULL,
  80                                                         AARCH64_CHECK_ORR)"))))
  81
  82 (define_predicate "aarch64_reg_or_bic_imm"
  83    (ior (match_operand 0 "register_operand")
  84         (and (match_code "const_vector")
  85              (match_test "aarch64_simd_valid_immediate (op, NULL,
  86                                                         AARCH64_CHECK_BIC)"))))
  87
  88 (define_predicate "aarch64_fp_compare_operand"
  89   (ior (match_operand 0 "register_operand")
  90        (and (match_code "const_double")
  91             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  92
  93 (define_predicate "aarch64_fp_pow2"
  94   (and (match_code "const_double")
  95         (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
  96
  97 (define_predicate "aarch64_fp_vec_pow2"
  98   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
  99
 100 (define_predicate "aarch64_sve_cnt_immediate"
 101   (and (match_code "const_poly_int")
 102        (match_test "aarch64_sve_cnt_immediate_p (op)")))
 103
 104 (define_predicate "aarch64_sub_immediate"
 105   (and (match_code "const_int")
 106        (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
 107
 108 (define_predicate "aarch64_plus_immediate"
 109   (and (match_code "const_int")
 110        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
 111             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
 112
 113 (define_predicate "aarch64_plus_operand"
 114   (ior (match_operand 0 "register_operand")
 115        (match_operand 0 "aarch64_plus_immediate")))
 116
 117 (define_predicate "aarch64_pluslong_immediate"
 118   (and (match_code "const_int")
 119        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
 120
 121 (define_predicate "aarch64_pluslong_strict_immedate"
 122   (and (match_operand 0 "aarch64_pluslong_immediate")
 123        (not (match_operand 0 "aarch64_plus_immediate"))))
 124
 125 (define_predicate "aarch64_sve_addvl_addpl_immediate"
 126   (and (match_code "const_poly_int")
 127        (match_test "aarch64_sve_addvl_addpl_immediate_p (op)")))
 128
 129 (define_predicate "aarch64_split_add_offset_immediate"
 130   (and (match_code "const_poly_int")
 131        (match_test "aarch64_add_offset_temporaries (op) == 1")))
 132
 133 (define_predicate "aarch64_pluslong_operand"
 134   (ior (match_operand 0 "register_operand")
 135        (match_operand 0 "aarch64_pluslong_immediate")
 136        (match_operand 0 "aarch64_sve_addvl_addpl_immediate")))
 137
 138 (define_predicate "aarch64_pluslong_or_poly_operand"
 139   (ior (match_operand 0 "aarch64_pluslong_operand")
 140        (match_operand 0 "aarch64_split_add_offset_immediate")))
 141
 142 (define_predicate "aarch64_logical_immediate"
 143   (and (match_code "const_int")
 144        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
 145
 146 (define_predicate "aarch64_logical_operand"
 147   (ior (match_operand 0 "register_operand")
 148        (match_operand 0 "aarch64_logical_immediate")))
 149
 150 (define_predicate "aarch64_mov_imm_operand"
 151   (and (match_code "const_int")
 152        (match_test "aarch64_move_imm (INTVAL (op), mode)")))
 153
 154 (define_predicate "aarch64_logical_and_immediate"
 155   (and (match_code "const_int")
 156        (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
 157
 158 (define_predicate "aarch64_shift_imm_si"
 159   (and (match_code "const_int")
 160        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
 161
 162 (define_predicate "aarch64_shift_imm_di"
 163   (and (match_code "const_int")
 164        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
 165
 166 (define_predicate "aarch64_shift_imm64_di"
 167   (and (match_code "const_int")
 168        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
 169
 170 (define_predicate "aarch64_reg_or_shift_imm_si"
 171   (ior (match_operand 0 "register_operand")
 172        (match_operand 0 "aarch64_shift_imm_si")))
 173
 174 (define_predicate "aarch64_reg_or_shift_imm_di"
 175   (ior (match_operand 0 "register_operand")
 176        (match_operand 0 "aarch64_shift_imm_di")))
 177
 178 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 179 ;; range 0..4.
 180 (define_predicate "aarch64_imm3"
 181   (and (match_code "const_int")
 182        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 183
 184 ;; The imm2 field is a 2-bit field that only accepts immediates in the
 185 ;; range 0..3.
 186 (define_predicate "aarch64_imm2"
 187   (and (match_code "const_int")
 188        (match_test "UINTVAL (op) <= 3")))
 189
 190 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 191 ;; range 0..7.
 192 (define_predicate "aarch64_lane_imm3"
 193   (and (match_code "const_int")
 194        (match_test "UINTVAL (op) <= 7")))
 195
 196 ;; An immediate that fits into 24 bits.
 197 (define_predicate "aarch64_imm24"
 198   (and (match_code "const_int")
 199        (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
 200
 201 (define_predicate "aarch64_pwr_imm3"
 202   (and (match_code "const_int")
 203        (match_test "INTVAL (op) != 0
 204                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 205
 206 (define_predicate "aarch64_pwr_2_si"
 207   (and (match_code "const_int")
 208        (match_test "INTVAL (op) != 0
 209                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 210
 211 (define_predicate "aarch64_pwr_2_di"
 212   (and (match_code "const_int")
 213        (match_test "INTVAL (op) != 0
 214                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 215
 216 (define_predicate "aarch64_mem_pair_offset"
 217   (and (match_code "const_int")
 218        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 219
 220 (define_predicate "aarch64_mem_pair_operand"
 221   (and (match_code "mem")
 222        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false,
 223                                                   ADDR_QUERY_LDP_STP)")))
 224
 225 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
 226 ;; as a 128-bit vec_concat.
 227 (define_predicate "aarch64_mem_pair_lanes_operand"
 228   (and (match_code "mem")
 229        (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), false,
 230                                                   ADDR_QUERY_LDP_STP)")))
 231
 232 (define_predicate "aarch64_prefetch_operand"
 233   (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
 234
 235 (define_predicate "aarch64_valid_symref"
 236   (match_code "const, symbol_ref, label_ref")
 237 {
 238   return (aarch64_classify_symbolic_expression (op)
 239           != SYMBOL_FORCE_TO_MEM);
 240 })
 241
 242 (define_predicate "aarch64_tls_ie_symref"
 243   (match_code "const, symbol_ref, label_ref")
 244 {
 245   switch (GET_CODE (op))
 246     {
 247     case CONST:
 248       op = XEXP (op, 0);
 249       if (GET_CODE (op) != PLUS
 250           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 251           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 252         return false;
 253       op = XEXP (op, 0);
 254       /* FALLTHRU */
 255
 256     case SYMBOL_REF:
 257       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 258
 259     default:
 260       gcc_unreachable ();
 261     }
 262 })
 263
 264 (define_predicate "aarch64_tls_le_symref"
 265   (match_code "const, symbol_ref, label_ref")
 266 {
 267   switch (GET_CODE (op))
 268     {
 269     case CONST:
 270       op = XEXP (op, 0);
 271       if (GET_CODE (op) != PLUS
 272           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 273           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 274         return false;
 275       op = XEXP (op, 0);
 276       /* FALLTHRU */
 277
 278     case SYMBOL_REF:
 279       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 280
 281     default:
 282       gcc_unreachable ();
 283     }
 284 })
 285
 286 (define_predicate "aarch64_mov_operand"
 287   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high,
 288                     const_poly_int,const_vector")
 289        (ior (match_operand 0 "register_operand")
 290             (ior (match_operand 0 "memory_operand")
 291                  (match_test "aarch64_mov_operand_p (op, mode)")))))
 292
 293 (define_predicate "aarch64_nonmemory_operand"
 294   (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high,
 295                     const_poly_int,const_vector")
 296        (ior (match_operand 0 "register_operand")
 297             (match_test "aarch64_mov_operand_p (op, mode)"))))
 298
 299 (define_predicate "aarch64_movti_operand"
 300   (ior (match_operand 0 "register_operand")
 301        (match_operand 0 "memory_operand")
 302        (and (match_operand 0 "const_scalar_int_operand")
 303             (match_test "aarch64_mov128_immediate (op)"))))
 304
 305 (define_predicate "aarch64_reg_or_imm"
 306   (ior (match_operand 0 "register_operand")
 307        (match_operand 0 "const_scalar_int_operand")))
 308
 309 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 310 (define_special_predicate "aarch64_comparison_operator"
 311   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 312                ordered,unlt,unle,unge,ungt"))
 313
 314 ;; Same as aarch64_comparison_operator but don't ignore the mode.
 315 ;; RTL SET operations require their operands source and destination have
 316 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 317 (define_predicate "aarch64_comparison_operator_mode"
 318   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 319                ordered,unlt,unle,unge,ungt"))
 320
 321 (define_special_predicate "aarch64_comparison_operation"
 322   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 323                ordered,unlt,unle,unge,ungt")
 324 {
 325   if (XEXP (op, 1) != const0_rtx)
 326     return false;
 327   rtx op0 = XEXP (op, 0);
 328   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 329     return false;
 330   return aarch64_get_condition_code (op) >= 0;
 331 })
 332
 333 (define_special_predicate "aarch64_equality_operator"
 334   (match_code "eq,ne"))
 335
 336 (define_special_predicate "aarch64_carry_operation"
 337   (match_code "ne,geu")
 338 {
 339   if (XEXP (op, 1) != const0_rtx)
 340     return false;
 341   machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
 342   rtx op0 = XEXP (op, 0);
 343   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 344 })
 345
 346 (define_special_predicate "aarch64_borrow_operation"
 347   (match_code "eq,ltu")
 348 {
 349   if (XEXP (op, 1) != const0_rtx)
 350     return false;
 351   machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
 352   rtx op0 = XEXP (op, 0);
 353   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 354 })
 355
 356 ;; True if the operand is memory reference suitable for a load/store exclusive.
 357 (define_predicate "aarch64_sync_memory_operand"
 358   (and (match_operand 0 "memory_operand")
 359        (match_code "reg" "0")))
 360
 361 ;; Predicates for parallel expanders based on mode.
 362 (define_special_predicate "vect_par_cnst_hi_half"
 363   (match_code "parallel")
 364 {
 365   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 366 })
 367
 368 (define_special_predicate "vect_par_cnst_lo_half"
 369   (match_code "parallel")
 370 {
 371   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 372 })
 373
 374 (define_special_predicate "aarch64_simd_lshift_imm"
 375   (match_code "const,const_vector")
 376 {
 377   return aarch64_simd_shift_imm_p (op, mode, true);
 378 })
 379
 380 (define_special_predicate "aarch64_simd_rshift_imm"
 381   (match_code "const,const_vector")
 382 {
 383   return aarch64_simd_shift_imm_p (op, mode, false);
 384 })
 385
 386 (define_predicate "aarch64_simd_imm_zero"
 387   (and (match_code "const,const_vector")
 388        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 389
 390 (define_predicate "aarch64_simd_or_scalar_imm_zero"
 391   (and (match_code "const_int,const_double,const,const_vector")
 392        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 393
 394 (define_predicate "aarch64_simd_imm_minus_one"
 395   (and (match_code "const,const_vector")
 396        (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
 397
 398 (define_predicate "aarch64_simd_reg_or_zero"
 399   (and (match_code "reg,subreg,const_int,const_double,const,const_vector")
 400        (ior (match_operand 0 "register_operand")
 401             (match_test "op == const0_rtx")
 402             (match_operand 0 "aarch64_simd_or_scalar_imm_zero"))))
 403
 404 (define_predicate "aarch64_simd_struct_operand"
 405   (and (match_code "mem")
 406        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 407
 408 ;; Like general_operand but allow only valid SIMD addressing modes.
 409 (define_predicate "aarch64_simd_general_operand"
 410   (and (match_operand 0 "general_operand")
 411        (match_test "!MEM_P (op)
 412                     || GET_CODE (XEXP (op, 0)) == POST_INC
 413                     || GET_CODE (XEXP (op, 0)) == REG")))
 414
 415 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 416 (define_predicate "aarch64_simd_nonimmediate_operand"
 417   (and (match_operand 0 "nonimmediate_operand")
 418        (match_test "!MEM_P (op)
 419                     || GET_CODE (XEXP (op, 0)) == POST_INC
 420                     || GET_CODE (XEXP (op, 0)) == REG")))
 421
 422 ;; Predicates used by the various SIMD shift operations.  These
 423 ;; fall in to 3 categories.
 424 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 425 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 426 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 427 (define_predicate "aarch64_simd_shift_imm_qi"
 428   (and (match_code "const_int")
 429        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 430
 431 (define_predicate "aarch64_simd_shift_imm_hi"
 432   (and (match_code "const_int")
 433        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 434
 435 (define_predicate "aarch64_simd_shift_imm_si"
 436   (and (match_code "const_int")
 437        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 438
 439 (define_predicate "aarch64_simd_shift_imm_di"
 440   (and (match_code "const_int")
 441        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 442
 443 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 444   (and (match_code "const_int")
 445        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 446
 447 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 448   (and (match_code "const_int")
 449        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 450
 451 (define_predicate "aarch64_simd_shift_imm_offset_si"
 452   (and (match_code "const_int")
 453        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 454
 455 (define_predicate "aarch64_simd_shift_imm_offset_di"
 456   (and (match_code "const_int")
 457        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 458
 459 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 460   (and (match_code "const_int")
 461        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 462
 463 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 464   (and (match_code "const_int")
 465        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 466
 467 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 468   (and (match_code "const_int")
 469        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 470
 471 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 472   (and (match_code "const_int")
 473        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
 474
 475 (define_predicate "aarch64_constant_pool_symref"
 476    (and (match_code "symbol_ref")
 477         (match_test "CONSTANT_POOL_ADDRESS_P (op)")))
 478
 479 (define_predicate "aarch64_constant_vector_operand"
 480   (match_code "const,const_vector"))
 481
 482 (define_predicate "aarch64_sve_ld1r_operand"
 483   (and (match_operand 0 "memory_operand")
 484        (match_test "aarch64_sve_ld1r_operand_p (op)")))
 485
 486 ;; Like memory_operand, but restricted to addresses that are valid for
 487 ;; SVE LDR and STR instructions.
 488 (define_predicate "aarch64_sve_ldr_operand"
 489   (and (match_code "mem")
 490        (match_test "aarch64_sve_ldr_operand_p (op)")))
 491
 492 (define_predicate "aarch64_sve_nonimmediate_operand"
 493   (ior (match_operand 0 "register_operand")
 494        (match_operand 0 "aarch64_sve_ldr_operand")))
 495
 496 (define_predicate "aarch64_sve_general_operand"
 497   (and (match_code "reg,subreg,mem,const,const_vector")
 498        (ior (match_operand 0 "register_operand")
 499             (match_operand 0 "aarch64_sve_ldr_operand")
 500             (match_test "aarch64_mov_operand_p (op, mode)"))))
 501
 502 (define_predicate "aarch64_sve_struct_memory_operand"
 503   (and (match_code "mem")
 504        (match_test "aarch64_sve_struct_memory_operand_p (op)")))
 505
 506 (define_predicate "aarch64_sve_struct_nonimmediate_operand"
 507   (ior (match_operand 0 "register_operand")
 508        (match_operand 0 "aarch64_sve_struct_memory_operand")))
 509
 510 ;; Doesn't include immediates, since those are handled by the move
 511 ;; patterns instead.
 512 (define_predicate "aarch64_sve_dup_operand"
 513   (ior (match_operand 0 "register_operand")
 514        (match_operand 0 "aarch64_sve_ld1r_operand")))
 515
 516 (define_predicate "aarch64_sve_arith_immediate"
 517   (and (match_code "const,const_vector")
 518        (match_test "aarch64_sve_arith_immediate_p (op, false)")))
 519
 520 (define_predicate "aarch64_sve_sub_arith_immediate"
 521   (and (match_code "const,const_vector")
 522        (match_test "aarch64_sve_arith_immediate_p (op, true)")))
 523
 524 (define_predicate "aarch64_sve_inc_dec_immediate"
 525   (and (match_code "const,const_vector")
 526        (match_test "aarch64_sve_inc_dec_immediate_p (op)")))
 527
 528 (define_predicate "aarch64_sve_logical_immediate"
 529   (and (match_code "const,const_vector")
 530        (match_test "aarch64_sve_bitmask_immediate_p (op)")))
 531
 532 (define_predicate "aarch64_sve_mul_immediate"
 533   (and (match_code "const,const_vector")
 534        (match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)")))
 535
 536 (define_predicate "aarch64_sve_dup_immediate"
 537   (and (match_code "const,const_vector")
 538        (match_test "aarch64_sve_dup_immediate_p (op)")))
 539
 540 (define_predicate "aarch64_sve_cmp_vsc_immediate"
 541   (and (match_code "const,const_vector")
 542        (match_test "aarch64_sve_cmp_immediate_p (op, true)")))
 543
 544 (define_predicate "aarch64_sve_cmp_vsd_immediate"
 545   (and (match_code "const,const_vector")
 546        (match_test "aarch64_sve_cmp_immediate_p (op, false)")))
 547
 548 (define_predicate "aarch64_sve_index_immediate"
 549   (and (match_code "const_int")
 550        (match_test "aarch64_sve_index_immediate_p (op)")))
 551
 552 (define_predicate "aarch64_sve_float_arith_immediate"
 553   (and (match_code "const,const_vector")
 554        (match_test "aarch64_sve_float_arith_immediate_p (op, false)")))
 555
 556 (define_predicate "aarch64_sve_float_arith_with_sub_immediate"
 557   (and (match_code "const,const_vector")
 558        (match_test "aarch64_sve_float_arith_immediate_p (op, true)")))
 559
 560 (define_predicate "aarch64_sve_float_mul_immediate"
 561   (and (match_code "const,const_vector")
 562        (match_test "aarch64_sve_float_mul_immediate_p (op)")))
 563
 564 (define_predicate "aarch64_sve_arith_operand"
 565   (ior (match_operand 0 "register_operand")
 566        (match_operand 0 "aarch64_sve_arith_immediate")))
 567
 568 (define_predicate "aarch64_sve_add_operand"
 569   (ior (match_operand 0 "aarch64_sve_arith_operand")
 570        (match_operand 0 "aarch64_sve_sub_arith_immediate")
 571        (match_operand 0 "aarch64_sve_inc_dec_immediate")))
 572
 573 (define_predicate "aarch64_sve_logical_operand"
 574   (ior (match_operand 0 "register_operand")
 575        (match_operand 0 "aarch64_sve_logical_immediate")))
 576
 577 (define_predicate "aarch64_sve_lshift_operand"
 578   (ior (match_operand 0 "register_operand")
 579        (match_operand 0 "aarch64_simd_lshift_imm")))
 580
 581 (define_predicate "aarch64_sve_rshift_operand"
 582   (ior (match_operand 0 "register_operand")
 583        (match_operand 0 "aarch64_simd_rshift_imm")))
 584
 585 (define_predicate "aarch64_sve_mul_operand"
 586   (ior (match_operand 0 "register_operand")
 587        (match_operand 0 "aarch64_sve_mul_immediate")))
 588
 589 (define_predicate "aarch64_sve_cmp_vsc_operand"
 590   (ior (match_operand 0 "register_operand")
 591        (match_operand 0 "aarch64_sve_cmp_vsc_immediate")))
 592
 593 (define_predicate "aarch64_sve_cmp_vsd_operand"
 594   (ior (match_operand 0 "register_operand")
 595        (match_operand 0 "aarch64_sve_cmp_vsd_immediate")))
 596
 597 (define_predicate "aarch64_sve_index_operand"
 598   (ior (match_operand 0 "register_operand")
 599        (match_operand 0 "aarch64_sve_index_immediate")))
 600
 601 (define_predicate "aarch64_sve_float_arith_operand"
 602   (ior (match_operand 0 "register_operand")
 603        (match_operand 0 "aarch64_sve_float_arith_immediate")))
 604
 605 (define_predicate "aarch64_sve_float_arith_with_sub_operand"
 606   (ior (match_operand 0 "aarch64_sve_float_arith_operand")
 607        (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate")))
 608
 609 (define_predicate "aarch64_sve_float_mul_operand"
 610   (ior (match_operand 0 "register_operand")
 611        (match_operand 0 "aarch64_sve_float_mul_immediate")))
 612
 613 (define_predicate "aarch64_sve_vec_perm_operand"
 614   (ior (match_operand 0 "register_operand")
 615        (match_operand 0 "aarch64_constant_vector_operand")))
 616
 617 (define_predicate "aarch64_gather_scale_operand_w"
 618   (and (match_code "const_int")
 619        (match_test "INTVAL (op) == 1 || INTVAL (op) == 4")))
 620
 621 (define_predicate "aarch64_gather_scale_operand_d"
 622   (and (match_code "const_int")
 623        (match_test "INTVAL (op) == 1 || INTVAL (op) == 8")))
 624
 625 ;; A special predicate that doesn't match a particular mode.
 626 (define_special_predicate "aarch64_any_register_operand"
 627   (match_code "reg"))