gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2014 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 (define_predicate "aarch64_simd_register"
  34   (and (match_code "reg")
  35        (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
  36             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
  37
  38 (define_predicate "aarch64_reg_or_zero"
  39   (and (match_code "reg,subreg,const_int")
  40        (ior (match_operand 0 "register_operand")
  41             (match_test "op == const0_rtx"))))
  42
  43 (define_predicate "aarch64_reg_or_fp_zero"
  44   (and (match_code "reg,subreg,const_double")
  45        (ior (match_operand 0 "register_operand")
  46             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  47
  48 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  49   (and (match_code "reg,subreg,const_int")
  50        (ior (match_operand 0 "register_operand")
  51             (ior (match_test "op == const0_rtx")
  52                  (ior (match_test "op == constm1_rtx")
  53                       (match_test "op == const1_rtx"))))))
  54
  55 (define_predicate "aarch64_fp_compare_operand"
  56   (ior (match_operand 0 "register_operand")
  57        (and (match_code "const_double")
  58             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  59
  60 (define_predicate "aarch64_plus_immediate"
  61   (and (match_code "const_int")
  62        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
  63             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
  64
  65 (define_predicate "aarch64_plus_operand"
  66   (ior (match_operand 0 "register_operand")
  67        (match_operand 0 "aarch64_plus_immediate")))
  68
  69 (define_predicate "aarch64_pluslong_immediate"
  70   (and (match_code "const_int")
  71        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
  72
  73 (define_predicate "aarch64_pluslong_operand"
  74   (ior (match_operand 0 "register_operand")
  75        (match_operand 0 "aarch64_pluslong_immediate")))
  76
  77 (define_predicate "aarch64_logical_immediate"
  78   (and (match_code "const_int")
  79        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
  80
  81 (define_predicate "aarch64_logical_operand"
  82   (ior (match_operand 0 "register_operand")
  83        (match_operand 0 "aarch64_logical_immediate")))
  84
  85 (define_predicate "aarch64_shift_imm_si"
  86   (and (match_code "const_int")
  87        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
  88
  89 (define_predicate "aarch64_shift_imm_di"
  90   (and (match_code "const_int")
  91        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
  92
  93 (define_predicate "aarch64_shift_imm64_di"
  94   (and (match_code "const_int")
  95        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
  96
  97 (define_predicate "aarch64_reg_or_shift_imm_si"
  98   (ior (match_operand 0 "register_operand")
  99        (match_operand 0 "aarch64_shift_imm_si")))
 100
 101 (define_predicate "aarch64_reg_or_shift_imm_di"
 102   (ior (match_operand 0 "register_operand")
 103        (match_operand 0 "aarch64_shift_imm_di")))
 104
 105 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 106 ;; range 0..4.
 107 (define_predicate "aarch64_imm3"
 108   (and (match_code "const_int")
 109        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 110
 111 (define_predicate "aarch64_pwr_imm3"
 112   (and (match_code "const_int")
 113        (match_test "INTVAL (op) != 0
 114                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 115
 116 (define_predicate "aarch64_pwr_2_si"
 117   (and (match_code "const_int")
 118        (match_test "INTVAL (op) != 0
 119                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 120
 121 (define_predicate "aarch64_pwr_2_di"
 122   (and (match_code "const_int")
 123        (match_test "INTVAL (op) != 0
 124                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 125
 126 (define_predicate "aarch64_mem_pair_offset"
 127   (and (match_code "const_int")
 128        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 129
 130 (define_predicate "aarch64_mem_pair_operand"
 131   (and (match_code "mem")
 132        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
 133                                                0)")))
 134
 135 (define_predicate "aarch64_valid_symref"
 136   (match_code "const, symbol_ref, label_ref")
 137 {
 138   return (aarch64_classify_symbolic_expression (op, SYMBOL_CONTEXT_ADR)
 139           != SYMBOL_FORCE_TO_MEM);
 140 })
 141
 142 (define_predicate "aarch64_tls_ie_symref"
 143   (match_code "const, symbol_ref, label_ref")
 144 {
 145   switch (GET_CODE (op))
 146     {
 147     case CONST:
 148       op = XEXP (op, 0);
 149       if (GET_CODE (op) != PLUS
 150           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 151           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 152         return false;
 153       op = XEXP (op, 0);
 154
 155     case SYMBOL_REF:
 156       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 157
 158     default:
 159       gcc_unreachable ();
 160     }
 161 })
 162
 163 (define_predicate "aarch64_tls_le_symref"
 164   (match_code "const, symbol_ref, label_ref")
 165 {
 166   switch (GET_CODE (op))
 167     {
 168     case CONST:
 169       op = XEXP (op, 0);
 170       if (GET_CODE (op) != PLUS
 171           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 172           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 173         return false;
 174       op = XEXP (op, 0);
 175
 176     case SYMBOL_REF:
 177       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 178
 179     default:
 180       gcc_unreachable ();
 181     }
 182 })
 183
 184 (define_predicate "aarch64_mov_operand"
 185   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high")
 186        (ior (match_operand 0 "register_operand")
 187             (ior (match_operand 0 "memory_operand")
 188                  (match_test "aarch64_mov_operand_p (op, SYMBOL_CONTEXT_ADR, mode)")))))
 189
 190 (define_predicate "aarch64_movti_operand"
 191   (and (match_code "reg,subreg,mem,const_int")
 192        (ior (match_operand 0 "register_operand")
 193             (ior (match_operand 0 "memory_operand")
 194                  (match_operand 0 "const_int_operand")))))
 195
 196 (define_predicate "aarch64_reg_or_imm"
 197   (and (match_code "reg,subreg,const_int")
 198        (ior (match_operand 0 "register_operand")
 199             (match_operand 0 "const_int_operand"))))
 200
 201 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 202 (define_special_predicate "aarch64_comparison_operator"
 203   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt"))
 204
 205 (define_special_predicate "aarch64_comparison_operation"
 206   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")
 207 {
 208   if (XEXP (op, 1) != const0_rtx)
 209     return false;
 210   rtx op0 = XEXP (op, 0);
 211   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 212     return false;
 213   return aarch64_get_condition_code (op) >= 0;
 214 })
 215
 216
 217 ;; True if the operand is memory reference suitable for a load/store exclusive.
 218 (define_predicate "aarch64_sync_memory_operand"
 219   (and (match_operand 0 "memory_operand")
 220        (match_code "reg" "0")))
 221
 222 ;; Predicates for parallel expanders based on mode.
 223 (define_special_predicate "vect_par_cnst_hi_half"
 224   (match_code "parallel")
 225 {
 226   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 227 })
 228
 229 (define_special_predicate "vect_par_cnst_lo_half"
 230   (match_code "parallel")
 231 {
 232   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 233 })
 234
 235 (define_special_predicate "aarch64_simd_lshift_imm"
 236   (match_code "const_vector")
 237 {
 238   return aarch64_simd_shift_imm_p (op, mode, true);
 239 })
 240
 241 (define_special_predicate "aarch64_simd_rshift_imm"
 242   (match_code "const_vector")
 243 {
 244   return aarch64_simd_shift_imm_p (op, mode, false);
 245 })
 246
 247 (define_predicate "aarch64_simd_reg_or_zero"
 248   (and (match_code "reg,subreg,const_int,const_vector")
 249        (ior (match_operand 0 "register_operand")
 250            (ior (match_test "op == const0_rtx")
 251                 (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
 252
 253 (define_predicate "aarch64_simd_struct_operand"
 254   (and (match_code "mem")
 255        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 256
 257 ;; Like general_operand but allow only valid SIMD addressing modes.
 258 (define_predicate "aarch64_simd_general_operand"
 259   (and (match_operand 0 "general_operand")
 260        (match_test "!MEM_P (op)
 261                     || GET_CODE (XEXP (op, 0)) == POST_INC
 262                     || GET_CODE (XEXP (op, 0)) == REG")))
 263
 264 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 265 (define_predicate "aarch64_simd_nonimmediate_operand"
 266   (and (match_operand 0 "nonimmediate_operand")
 267        (match_test "!MEM_P (op)
 268                     || GET_CODE (XEXP (op, 0)) == POST_INC
 269                     || GET_CODE (XEXP (op, 0)) == REG")))
 270
 271 (define_special_predicate "aarch64_simd_imm_zero"
 272   (match_code "const_vector")
 273 {
 274   return aarch64_simd_imm_zero_p (op, mode);
 275 })
 276
 277 (define_special_predicate "aarch64_simd_imm_minus_one"
 278   (match_code "const_vector")
 279 {
 280   return aarch64_const_vec_all_same_int_p (op, -1);
 281 })
 282
 283 ;; Predicates used by the various SIMD shift operations.  These
 284 ;; fall in to 3 categories.
 285 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 286 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 287 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 288 (define_predicate "aarch64_simd_shift_imm_qi"
 289   (and (match_code "const_int")
 290        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 291
 292 (define_predicate "aarch64_simd_shift_imm_hi"
 293   (and (match_code "const_int")
 294        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 295
 296 (define_predicate "aarch64_simd_shift_imm_si"
 297   (and (match_code "const_int")
 298        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 299
 300 (define_predicate "aarch64_simd_shift_imm_di"
 301   (and (match_code "const_int")
 302        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 303
 304 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 305   (and (match_code "const_int")
 306        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 307
 308 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 309   (and (match_code "const_int")
 310        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 311
 312 (define_predicate "aarch64_simd_shift_imm_offset_si"
 313   (and (match_code "const_int")
 314        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 315
 316 (define_predicate "aarch64_simd_shift_imm_offset_di"
 317   (and (match_code "const_int")
 318        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 319
 320 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 321   (and (match_code "const_int")
 322        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 323
 324 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 325   (and (match_code "const_int")
 326        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 327
 328 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 329   (and (match_code "const_int")
 330        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 331
 332 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 333   (and (match_code "const_int")
 334        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))