gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 ;; Return true if OP a (const_int 0) operand.
  34 (define_predicate "const0_operand"
  35   (and (match_code "const_int")
  36        (match_test "op == CONST0_RTX (mode)")))
  37
  38 (define_predicate "aarch64_ccmp_immediate"
  39   (and (match_code "const_int")
  40        (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
  41
  42 (define_predicate "aarch64_ccmp_operand"
  43   (ior (match_operand 0 "register_operand")
  44        (match_operand 0 "aarch64_ccmp_immediate")))
  45
  46 (define_predicate "aarch64_simd_register"
  47   (and (match_code "reg")
  48        (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
  49             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
  50
  51 (define_predicate "aarch64_reg_or_zero"
  52   (and (match_code "reg,subreg,const_int")
  53        (ior (match_operand 0 "register_operand")
  54             (match_test "op == const0_rtx"))))
  55
  56 (define_predicate "aarch64_reg_or_fp_zero"
  57   (ior (match_operand 0 "register_operand")
  58         (and (match_code "const_double")
  59              (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  60
  61 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  62   (and (match_code "reg,subreg,const_int")
  63        (ior (match_operand 0 "register_operand")
  64             (ior (match_test "op == const0_rtx")
  65                  (ior (match_test "op == constm1_rtx")
  66                       (match_test "op == const1_rtx"))))))
  67
  68 (define_predicate "aarch64_fp_compare_operand"
  69   (ior (match_operand 0 "register_operand")
  70        (and (match_code "const_double")
  71             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  72
  73 (define_predicate "aarch64_fp_pow2"
  74   (and (match_code "const_double")
  75         (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
  76
  77 (define_predicate "aarch64_fp_vec_pow2"
  78   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
  79
  80 (define_predicate "aarch64_plus_immediate"
  81   (and (match_code "const_int")
  82        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
  83             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
  84
  85 (define_predicate "aarch64_plus_operand"
  86   (ior (match_operand 0 "register_operand")
  87        (match_operand 0 "aarch64_plus_immediate")))
  88
  89 (define_predicate "aarch64_pluslong_immediate"
  90   (and (match_code "const_int")
  91        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
  92
  93 (define_predicate "aarch64_pluslong_strict_immedate"
  94   (and (match_operand 0 "aarch64_pluslong_immediate")
  95        (not (match_operand 0 "aarch64_plus_immediate"))))
  96
  97 (define_predicate "aarch64_pluslong_operand"
  98   (ior (match_operand 0 "register_operand")
  99        (match_operand 0 "aarch64_pluslong_immediate")))
 100
 101 (define_predicate "aarch64_logical_immediate"
 102   (and (match_code "const_int")
 103        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
 104
 105 (define_predicate "aarch64_logical_operand"
 106   (ior (match_operand 0 "register_operand")
 107        (match_operand 0 "aarch64_logical_immediate")))
 108
 109 (define_predicate "aarch64_logical_and_immediate"
 110   (and (match_code "const_int")
 111        (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
 112
 113 (define_predicate "aarch64_shift_imm_si"
 114   (and (match_code "const_int")
 115        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
 116
 117 (define_predicate "aarch64_shift_imm_di"
 118   (and (match_code "const_int")
 119        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
 120
 121 (define_predicate "aarch64_shift_imm64_di"
 122   (and (match_code "const_int")
 123        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
 124
 125 (define_predicate "aarch64_reg_or_shift_imm_si"
 126   (ior (match_operand 0 "register_operand")
 127        (match_operand 0 "aarch64_shift_imm_si")))
 128
 129 (define_predicate "aarch64_reg_or_shift_imm_di"
 130   (ior (match_operand 0 "register_operand")
 131        (match_operand 0 "aarch64_shift_imm_di")))
 132
 133 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 134 ;; range 0..4.
 135 (define_predicate "aarch64_imm3"
 136   (and (match_code "const_int")
 137        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 138
 139 ;; An immediate that fits into 24 bits.
 140 (define_predicate "aarch64_imm24"
 141   (and (match_code "const_int")
 142        (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
 143
 144 (define_predicate "aarch64_pwr_imm3"
 145   (and (match_code "const_int")
 146        (match_test "INTVAL (op) != 0
 147                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 148
 149 (define_predicate "aarch64_pwr_2_si"
 150   (and (match_code "const_int")
 151        (match_test "INTVAL (op) != 0
 152                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 153
 154 (define_predicate "aarch64_pwr_2_di"
 155   (and (match_code "const_int")
 156        (match_test "INTVAL (op) != 0
 157                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 158
 159 (define_predicate "aarch64_mem_pair_offset"
 160   (and (match_code "const_int")
 161        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 162
 163 (define_predicate "aarch64_mem_pair_operand"
 164   (and (match_code "mem")
 165        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
 166                                                0)")))
 167
 168 (define_predicate "aarch64_valid_symref"
 169   (match_code "const, symbol_ref, label_ref")
 170 {
 171   return (aarch64_classify_symbolic_expression (op)
 172           != SYMBOL_FORCE_TO_MEM);
 173 })
 174
 175 (define_predicate "aarch64_tls_ie_symref"
 176   (match_code "const, symbol_ref, label_ref")
 177 {
 178   switch (GET_CODE (op))
 179     {
 180     case CONST:
 181       op = XEXP (op, 0);
 182       if (GET_CODE (op) != PLUS
 183           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 184           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 185         return false;
 186       op = XEXP (op, 0);
 187       /* FALLTHRU */
 188
 189     case SYMBOL_REF:
 190       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 191
 192     default:
 193       gcc_unreachable ();
 194     }
 195 })
 196
 197 (define_predicate "aarch64_tls_le_symref"
 198   (match_code "const, symbol_ref, label_ref")
 199 {
 200   switch (GET_CODE (op))
 201     {
 202     case CONST:
 203       op = XEXP (op, 0);
 204       if (GET_CODE (op) != PLUS
 205           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 206           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 207         return false;
 208       op = XEXP (op, 0);
 209       /* FALLTHRU */
 210
 211     case SYMBOL_REF:
 212       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 213
 214     default:
 215       gcc_unreachable ();
 216     }
 217 })
 218
 219 (define_predicate "aarch64_mov_operand"
 220   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high")
 221        (ior (match_operand 0 "register_operand")
 222             (ior (match_operand 0 "memory_operand")
 223                  (match_test "aarch64_mov_operand_p (op, mode)")))))
 224
 225 (define_predicate "aarch64_movti_operand"
 226   (and (match_code "reg,subreg,mem,const_int")
 227        (ior (match_operand 0 "register_operand")
 228             (ior (match_operand 0 "memory_operand")
 229                  (match_operand 0 "const_int_operand")))))
 230
 231 (define_predicate "aarch64_reg_or_imm"
 232   (and (match_code "reg,subreg,const_int")
 233        (ior (match_operand 0 "register_operand")
 234             (match_operand 0 "const_int_operand"))))
 235
 236 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 237 (define_special_predicate "aarch64_comparison_operator"
 238   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 239                ordered,unlt,unle,unge,ungt"))
 240
 241 ;; Same as aarch64_comparison_operator but don't ignore the mode.
 242 ;; RTL SET operations require their operands source and destination have
 243 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 244 (define_predicate "aarch64_comparison_operator_mode"
 245   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 246                ordered,unlt,unle,unge,ungt"))
 247
 248 (define_special_predicate "aarch64_comparison_operation"
 249   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 250                ordered,unlt,unle,unge,ungt")
 251 {
 252   if (XEXP (op, 1) != const0_rtx)
 253     return false;
 254   rtx op0 = XEXP (op, 0);
 255   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 256     return false;
 257   return aarch64_get_condition_code (op) >= 0;
 258 })
 259
 260 (define_special_predicate "aarch64_carry_operation"
 261   (match_code "ne,geu")
 262 {
 263   if (XEXP (op, 1) != const0_rtx)
 264     return false;
 265   machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
 266   rtx op0 = XEXP (op, 0);
 267   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 268 })
 269
 270 (define_special_predicate "aarch64_borrow_operation"
 271   (match_code "eq,ltu")
 272 {
 273   if (XEXP (op, 1) != const0_rtx)
 274     return false;
 275   machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
 276   rtx op0 = XEXP (op, 0);
 277   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 278 })
 279
 280 ;; True if the operand is memory reference suitable for a load/store exclusive.
 281 (define_predicate "aarch64_sync_memory_operand"
 282   (and (match_operand 0 "memory_operand")
 283        (match_code "reg" "0")))
 284
 285 ;; Predicates for parallel expanders based on mode.
 286 (define_special_predicate "vect_par_cnst_hi_half"
 287   (match_code "parallel")
 288 {
 289   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 290 })
 291
 292 (define_special_predicate "vect_par_cnst_lo_half"
 293   (match_code "parallel")
 294 {
 295   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 296 })
 297
 298 (define_special_predicate "aarch64_simd_lshift_imm"
 299   (match_code "const_vector")
 300 {
 301   return aarch64_simd_shift_imm_p (op, mode, true);
 302 })
 303
 304 (define_special_predicate "aarch64_simd_rshift_imm"
 305   (match_code "const_vector")
 306 {
 307   return aarch64_simd_shift_imm_p (op, mode, false);
 308 })
 309
 310 (define_predicate "aarch64_simd_reg_or_zero"
 311   (and (match_code "reg,subreg,const_int,const_double,const_vector")
 312        (ior (match_operand 0 "register_operand")
 313            (ior (match_test "op == const0_rtx")
 314                 (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
 315
 316 (define_predicate "aarch64_simd_struct_operand"
 317   (and (match_code "mem")
 318        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 319
 320 ;; Like general_operand but allow only valid SIMD addressing modes.
 321 (define_predicate "aarch64_simd_general_operand"
 322   (and (match_operand 0 "general_operand")
 323        (match_test "!MEM_P (op)
 324                     || GET_CODE (XEXP (op, 0)) == POST_INC
 325                     || GET_CODE (XEXP (op, 0)) == REG")))
 326
 327 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 328 (define_predicate "aarch64_simd_nonimmediate_operand"
 329   (and (match_operand 0 "nonimmediate_operand")
 330        (match_test "!MEM_P (op)
 331                     || GET_CODE (XEXP (op, 0)) == POST_INC
 332                     || GET_CODE (XEXP (op, 0)) == REG")))
 333
 334 (define_special_predicate "aarch64_simd_imm_zero"
 335   (match_code "const_vector")
 336 {
 337   return aarch64_simd_imm_zero_p (op, mode);
 338 })
 339
 340 (define_special_predicate "aarch64_simd_imm_minus_one"
 341   (match_code "const_vector")
 342 {
 343   return aarch64_const_vec_all_same_int_p (op, -1);
 344 })
 345
 346 ;; Predicates used by the various SIMD shift operations.  These
 347 ;; fall in to 3 categories.
 348 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 349 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 350 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 351 (define_predicate "aarch64_simd_shift_imm_qi"
 352   (and (match_code "const_int")
 353        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 354
 355 (define_predicate "aarch64_simd_shift_imm_hi"
 356   (and (match_code "const_int")
 357        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 358
 359 (define_predicate "aarch64_simd_shift_imm_si"
 360   (and (match_code "const_int")
 361        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 362
 363 (define_predicate "aarch64_simd_shift_imm_di"
 364   (and (match_code "const_int")
 365        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 366
 367 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 368   (and (match_code "const_int")
 369        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 370
 371 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 372   (and (match_code "const_int")
 373        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 374
 375 (define_predicate "aarch64_simd_shift_imm_offset_si"
 376   (and (match_code "const_int")
 377        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 378
 379 (define_predicate "aarch64_simd_shift_imm_offset_di"
 380   (and (match_code "const_int")
 381        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 382
 383 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 384   (and (match_code "const_int")
 385        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 386
 387 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 388   (and (match_code "const_int")
 389        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 390
 391 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 392   (and (match_code "const_int")
 393        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 394
 395 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 396   (and (match_code "const_int")
 397        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
 398
 399 (define_predicate "aarch64_constant_pool_symref"
 400    (and (match_code "symbol_ref")
 401         (match_test "CONSTANT_POOL_ADDRESS_P (op)")))