gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 ;; Return true if OP a (const_int 0) operand.
  34 (define_predicate "const0_operand"
  35   (and (match_code "const_int")
  36        (match_test "op == CONST0_RTX (mode)")))
  37
  38 (define_special_predicate "subreg_lowpart_operator"
  39   (and (match_code "subreg")
  40        (match_test "subreg_lowpart_p (op)")))
  41
  42 (define_predicate "aarch64_ccmp_immediate"
  43   (and (match_code "const_int")
  44        (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
  45
  46 (define_predicate "aarch64_ccmp_operand"
  47   (ior (match_operand 0 "register_operand")
  48        (match_operand 0 "aarch64_ccmp_immediate")))
  49
  50 (define_predicate "aarch64_simd_register"
  51   (and (match_code "reg")
  52        (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
  53             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
  54
  55 (define_predicate "aarch64_reg_or_zero"
  56   (and (match_code "reg,subreg,const_int")
  57        (ior (match_operand 0 "register_operand")
  58             (match_test "op == const0_rtx"))))
  59
  60 (define_predicate "aarch64_reg_or_fp_zero"
  61   (ior (match_operand 0 "register_operand")
  62         (and (match_code "const_double")
  63              (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  64
  65 (define_predicate "aarch64_reg_zero_or_fp_zero"
  66   (ior (match_operand 0 "aarch64_reg_or_fp_zero")
  67        (match_operand 0 "aarch64_reg_or_zero")))
  68
  69 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  70   (and (match_code "reg,subreg,const_int")
  71        (ior (match_operand 0 "register_operand")
  72             (ior (match_test "op == const0_rtx")
  73                  (ior (match_test "op == constm1_rtx")
  74                       (match_test "op == const1_rtx"))))))
  75
  76 (define_predicate "aarch64_reg_or_orr_imm"
  77    (ior (match_operand 0 "register_operand")
  78         (and (match_code "const_vector")
  79              (match_test "aarch64_simd_valid_immediate (op, NULL,
  80                                                         AARCH64_CHECK_ORR)"))))
  81
  82 (define_predicate "aarch64_reg_or_bic_imm"
  83    (ior (match_operand 0 "register_operand")
  84         (and (match_code "const_vector")
  85              (match_test "aarch64_simd_valid_immediate (op, NULL,
  86                                                         AARCH64_CHECK_BIC)"))))
  87
  88 (define_predicate "aarch64_fp_compare_operand"
  89   (ior (match_operand 0 "register_operand")
  90        (and (match_code "const_double")
  91             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  92
  93 (define_predicate "aarch64_fp_pow2"
  94   (and (match_code "const_double")
  95         (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
  96
  97 (define_predicate "aarch64_fp_vec_pow2"
  98   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
  99
 100 (define_predicate "aarch64_sve_cnt_immediate"
 101   (and (match_code "const_poly_int")
 102        (match_test "aarch64_sve_cnt_immediate_p (op)")))
 103
 104 (define_predicate "aarch64_sub_immediate"
 105   (and (match_code "const_int")
 106        (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
 107
 108 (define_predicate "aarch64_plus_immediate"
 109   (and (match_code "const_int")
 110        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
 111             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
 112
 113 (define_predicate "aarch64_plus_operand"
 114   (ior (match_operand 0 "register_operand")
 115        (match_operand 0 "aarch64_plus_immediate")))
 116
 117 (define_predicate "aarch64_plushi_immediate"
 118   (match_code "const_int")
 119 {
 120   HOST_WIDE_INT val = INTVAL (op);
 121   /* The HImode value must be zero-extendable to an SImode plus_operand.  */
 122   return ((val & 0xfff) == val || sext_hwi (val & 0xf000, 16) == val);
 123 })
 124
 125 (define_predicate "aarch64_plushi_operand"
 126   (ior (match_operand 0 "register_operand")
 127        (match_operand 0 "aarch64_plushi_immediate")))
 128
 129 (define_predicate "aarch64_pluslong_immediate"
 130   (and (match_code "const_int")
 131        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
 132
 133 (define_predicate "aarch64_pluslong_strict_immedate"
 134   (and (match_operand 0 "aarch64_pluslong_immediate")
 135        (not (match_operand 0 "aarch64_plus_immediate"))))
 136
 137 (define_predicate "aarch64_sve_addvl_addpl_immediate"
 138   (and (match_code "const_poly_int")
 139        (match_test "aarch64_sve_addvl_addpl_immediate_p (op)")))
 140
 141 (define_predicate "aarch64_split_add_offset_immediate"
 142   (and (match_code "const_poly_int")
 143        (match_test "aarch64_add_offset_temporaries (op) == 1")))
 144
 145 (define_predicate "aarch64_pluslong_operand"
 146   (ior (match_operand 0 "register_operand")
 147        (match_operand 0 "aarch64_pluslong_immediate")
 148        (match_operand 0 "aarch64_sve_addvl_addpl_immediate")))
 149
 150 (define_predicate "aarch64_pluslong_or_poly_operand"
 151   (ior (match_operand 0 "aarch64_pluslong_operand")
 152        (match_operand 0 "aarch64_split_add_offset_immediate")))
 153
 154 (define_predicate "aarch64_logical_immediate"
 155   (and (match_code "const_int")
 156        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
 157
 158 (define_predicate "aarch64_logical_operand"
 159   (ior (match_operand 0 "register_operand")
 160        (match_operand 0 "aarch64_logical_immediate")))
 161
 162 (define_predicate "aarch64_mov_imm_operand"
 163   (and (match_code "const_int")
 164        (match_test "aarch64_move_imm (INTVAL (op), mode)")))
 165
 166 (define_predicate "aarch64_logical_and_immediate"
 167   (and (match_code "const_int")
 168        (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
 169
 170 (define_predicate "aarch64_shift_imm_si"
 171   (and (match_code "const_int")
 172        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
 173
 174 (define_predicate "aarch64_shift_imm_di"
 175   (and (match_code "const_int")
 176        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
 177
 178 (define_predicate "aarch64_shift_imm64_di"
 179   (and (match_code "const_int")
 180        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
 181
 182 (define_predicate "aarch64_reg_or_shift_imm_si"
 183   (ior (match_operand 0 "register_operand")
 184        (match_operand 0 "aarch64_shift_imm_si")))
 185
 186 (define_predicate "aarch64_reg_or_shift_imm_di"
 187   (ior (match_operand 0 "register_operand")
 188        (match_operand 0 "aarch64_shift_imm_di")))
 189
 190 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 191 ;; range 0..4.
 192 (define_predicate "aarch64_imm3"
 193   (and (match_code "const_int")
 194        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 195
 196 ;; The imm2 field is a 2-bit field that only accepts immediates in the
 197 ;; range 0..3.
 198 (define_predicate "aarch64_imm2"
 199   (and (match_code "const_int")
 200        (match_test "UINTVAL (op) <= 3")))
 201
 202 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 203 ;; range 0..7.
 204 (define_predicate "aarch64_lane_imm3"
 205   (and (match_code "const_int")
 206        (match_test "UINTVAL (op) <= 7")))
 207
 208 ;; An immediate that fits into 24 bits.
 209 (define_predicate "aarch64_imm24"
 210   (and (match_code "const_int")
 211        (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
 212
 213 (define_predicate "aarch64_pwr_imm3"
 214   (and (match_code "const_int")
 215        (match_test "INTVAL (op) != 0
 216                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 217
 218 (define_predicate "aarch64_pwr_2_si"
 219   (and (match_code "const_int")
 220        (match_test "INTVAL (op) != 0
 221                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 222
 223 (define_predicate "aarch64_pwr_2_di"
 224   (and (match_code "const_int")
 225        (match_test "INTVAL (op) != 0
 226                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 227
 228 (define_predicate "aarch64_mem_pair_offset"
 229   (and (match_code "const_int")
 230        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 231
 232 (define_predicate "aarch64_mem_pair_operand"
 233   (and (match_code "mem")
 234        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false,
 235                                                   ADDR_QUERY_LDP_STP)")))
 236
 237 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
 238 ;; as a 128-bit vec_concat.
 239 (define_predicate "aarch64_mem_pair_lanes_operand"
 240   (and (match_code "mem")
 241        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 242                                                   false,
 243                                                   ADDR_QUERY_LDP_STP_N)")))
 244
 245 (define_predicate "aarch64_prefetch_operand"
 246   (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
 247
 248 (define_predicate "aarch64_valid_symref"
 249   (match_code "const, symbol_ref, label_ref")
 250 {
 251   return (aarch64_classify_symbolic_expression (op)
 252           != SYMBOL_FORCE_TO_MEM);
 253 })
 254
 255 (define_predicate "aarch64_tls_ie_symref"
 256   (match_code "const, symbol_ref, label_ref")
 257 {
 258   switch (GET_CODE (op))
 259     {
 260     case CONST:
 261       op = XEXP (op, 0);
 262       if (GET_CODE (op) != PLUS
 263           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 264           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 265         return false;
 266       op = XEXP (op, 0);
 267       /* FALLTHRU */
 268
 269     case SYMBOL_REF:
 270       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 271
 272     default:
 273       gcc_unreachable ();
 274     }
 275 })
 276
 277 (define_predicate "aarch64_tls_le_symref"
 278   (match_code "const, symbol_ref, label_ref")
 279 {
 280   switch (GET_CODE (op))
 281     {
 282     case CONST:
 283       op = XEXP (op, 0);
 284       if (GET_CODE (op) != PLUS
 285           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 286           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 287         return false;
 288       op = XEXP (op, 0);
 289       /* FALLTHRU */
 290
 291     case SYMBOL_REF:
 292       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 293
 294     default:
 295       gcc_unreachable ();
 296     }
 297 })
 298
 299 (define_predicate "aarch64_mov_operand"
 300   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high,
 301                     const_poly_int,const_vector")
 302        (ior (match_operand 0 "register_operand")
 303             (ior (match_operand 0 "memory_operand")
 304                  (match_test "aarch64_mov_operand_p (op, mode)")))))
 305
 306 (define_predicate "aarch64_nonmemory_operand"
 307   (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high,
 308                     const_poly_int,const_vector")
 309        (ior (match_operand 0 "register_operand")
 310             (match_test "aarch64_mov_operand_p (op, mode)"))))
 311
 312 (define_predicate "aarch64_movti_operand"
 313   (ior (match_operand 0 "register_operand")
 314        (match_operand 0 "memory_operand")
 315        (and (match_operand 0 "const_scalar_int_operand")
 316             (match_test "aarch64_mov128_immediate (op)"))))
 317
 318 (define_predicate "aarch64_reg_or_imm"
 319   (ior (match_operand 0 "register_operand")
 320        (match_operand 0 "const_scalar_int_operand")))
 321
 322 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 323 (define_special_predicate "aarch64_comparison_operator"
 324   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 325                ordered,unlt,unle,unge,ungt"))
 326
 327 ;; Same as aarch64_comparison_operator but don't ignore the mode.
 328 ;; RTL SET operations require their operands source and destination have
 329 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 330 (define_predicate "aarch64_comparison_operator_mode"
 331   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 332                ordered,unlt,unle,unge,ungt"))
 333
 334 (define_special_predicate "aarch64_comparison_operation"
 335   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 336                ordered,unlt,unle,unge,ungt")
 337 {
 338   if (XEXP (op, 1) != const0_rtx)
 339     return false;
 340   rtx op0 = XEXP (op, 0);
 341   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 342     return false;
 343   return aarch64_get_condition_code (op) >= 0;
 344 })
 345
 346 (define_special_predicate "aarch64_equality_operator"
 347   (match_code "eq,ne"))
 348
 349 (define_special_predicate "aarch64_carry_operation"
 350   (match_code "ltu,geu")
 351 {
 352   if (XEXP (op, 1) != const0_rtx)
 353     return false;
 354   rtx op0 = XEXP (op, 0);
 355   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 356     return false;
 357   machine_mode ccmode = GET_MODE (op0);
 358   if (ccmode == CC_Cmode)
 359     return GET_CODE (op) == LTU;
 360   if (ccmode == CC_ADCmode || ccmode == CCmode)
 361     return GET_CODE (op) == GEU;
 362   return false;
 363 })
 364
 365 ; borrow is essentially the inverse of carry since the sense of the C flag
 366 ; is inverted during subtraction.  See the note in aarch64-modes.def.
 367 (define_special_predicate "aarch64_borrow_operation"
 368   (match_code "geu,ltu")
 369 {
 370   if (XEXP (op, 1) != const0_rtx)
 371     return false;
 372   rtx op0 = XEXP (op, 0);
 373   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 374     return false;
 375   machine_mode ccmode = GET_MODE (op0);
 376   if (ccmode == CC_Cmode)
 377     return GET_CODE (op) == GEU;
 378   if (ccmode == CC_ADCmode || ccmode == CCmode)
 379     return GET_CODE (op) == LTU;
 380   return false;
 381 })
 382
 383 ;; True if the operand is memory reference suitable for a load/store exclusive.
 384 (define_predicate "aarch64_sync_memory_operand"
 385   (and (match_operand 0 "memory_operand")
 386        (match_code "reg" "0")))
 387
 388 (define_predicate "aarch64_9bit_offset_memory_operand"
 389   (and (match_operand 0 "memory_operand")
 390        (ior (match_code "reg" "0")
 391             (and (match_code "plus" "0")
 392                  (match_code "reg"  "00")
 393                  (match_code "const_int" "01"))))
 394 {
 395   rtx mem_op = XEXP (op, 0);
 396
 397   if (REG_P (mem_op))
 398     return GET_MODE (mem_op) == DImode;
 399
 400   rtx plus_op0 = XEXP (mem_op, 0);
 401   rtx plus_op1 = XEXP (mem_op, 1);
 402
 403   if (GET_MODE (plus_op0) != DImode)
 404     return false;
 405
 406   poly_int64 offset;
 407   if (!poly_int_rtx_p (plus_op1, &offset))
 408     gcc_unreachable ();
 409
 410   return aarch64_offset_9bit_signed_unscaled_p (mode, offset);
 411 })
 412
 413 (define_predicate "aarch64_rcpc_memory_operand"
 414   (if_then_else (match_test "AARCH64_ISA_RCPC8_4")
 415     (match_operand 0 "aarch64_9bit_offset_memory_operand")
 416     (match_operand 0 "aarch64_sync_memory_operand")))
 417
 418 ;; Predicates for parallel expanders based on mode.
 419 (define_special_predicate "vect_par_cnst_hi_half"
 420   (match_code "parallel")
 421 {
 422   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 423 })
 424
 425 (define_special_predicate "vect_par_cnst_lo_half"
 426   (match_code "parallel")
 427 {
 428   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 429 })
 430
 431 (define_special_predicate "aarch64_simd_lshift_imm"
 432   (match_code "const,const_vector")
 433 {
 434   return aarch64_simd_shift_imm_p (op, mode, true);
 435 })
 436
 437 (define_special_predicate "aarch64_simd_rshift_imm"
 438   (match_code "const,const_vector")
 439 {
 440   return aarch64_simd_shift_imm_p (op, mode, false);
 441 })
 442
 443 (define_predicate "aarch64_simd_imm_zero"
 444   (and (match_code "const,const_vector")
 445        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 446
 447 (define_predicate "aarch64_simd_or_scalar_imm_zero"
 448   (and (match_code "const_int,const_double,const,const_vector")
 449        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 450
 451 (define_predicate "aarch64_simd_imm_minus_one"
 452   (and (match_code "const,const_vector")
 453        (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
 454
 455 (define_predicate "aarch64_simd_reg_or_zero"
 456   (and (match_code "reg,subreg,const_int,const_double,const,const_vector")
 457        (ior (match_operand 0 "register_operand")
 458             (match_test "op == const0_rtx")
 459             (match_operand 0 "aarch64_simd_or_scalar_imm_zero"))))
 460
 461 (define_predicate "aarch64_simd_struct_operand"
 462   (and (match_code "mem")
 463        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 464
 465 ;; Like general_operand but allow only valid SIMD addressing modes.
 466 (define_predicate "aarch64_simd_general_operand"
 467   (and (match_operand 0 "general_operand")
 468        (match_test "!MEM_P (op)
 469                     || GET_CODE (XEXP (op, 0)) == POST_INC
 470                     || GET_CODE (XEXP (op, 0)) == REG")))
 471
 472 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 473 (define_predicate "aarch64_simd_nonimmediate_operand"
 474   (and (match_operand 0 "nonimmediate_operand")
 475        (match_test "!MEM_P (op)
 476                     || GET_CODE (XEXP (op, 0)) == POST_INC
 477                     || GET_CODE (XEXP (op, 0)) == REG")))
 478
 479 ;; Predicates used by the various SIMD shift operations.  These
 480 ;; fall in to 3 categories.
 481 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 482 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 483 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 484 (define_predicate "aarch64_simd_shift_imm_qi"
 485   (and (match_code "const_int")
 486        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 487
 488 (define_predicate "aarch64_simd_shift_imm_hi"
 489   (and (match_code "const_int")
 490        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 491
 492 (define_predicate "aarch64_simd_shift_imm_si"
 493   (and (match_code "const_int")
 494        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 495
 496 (define_predicate "aarch64_simd_shift_imm_di"
 497   (and (match_code "const_int")
 498        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 499
 500 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 501   (and (match_code "const_int")
 502        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 503
 504 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 505   (and (match_code "const_int")
 506        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 507
 508 (define_predicate "aarch64_simd_shift_imm_offset_si"
 509   (and (match_code "const_int")
 510        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 511
 512 (define_predicate "aarch64_simd_shift_imm_offset_di"
 513   (and (match_code "const_int")
 514        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 515
 516 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 517   (and (match_code "const_int")
 518        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 519
 520 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 521   (and (match_code "const_int")
 522        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 523
 524 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 525   (and (match_code "const_int")
 526        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 527
 528 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 529   (and (match_code "const_int")
 530        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
 531
 532 (define_predicate "aarch64_constant_pool_symref"
 533    (and (match_code "symbol_ref")
 534         (match_test "CONSTANT_POOL_ADDRESS_P (op)")))
 535
 536 (define_predicate "aarch64_constant_vector_operand"
 537   (match_code "const,const_vector"))
 538
 539 (define_predicate "aarch64_sve_ld1r_operand"
 540   (and (match_operand 0 "memory_operand")
 541        (match_test "aarch64_sve_ld1r_operand_p (op)")))
 542
 543 ;; Like memory_operand, but restricted to addresses that are valid for
 544 ;; SVE LDR and STR instructions.
 545 (define_predicate "aarch64_sve_ldr_operand"
 546   (and (match_code "mem")
 547        (match_test "aarch64_sve_ldr_operand_p (op)")))
 548
 549 (define_predicate "aarch64_sve_nonimmediate_operand"
 550   (ior (match_operand 0 "register_operand")
 551        (match_operand 0 "aarch64_sve_ldr_operand")))
 552
 553 (define_predicate "aarch64_sve_general_operand"
 554   (and (match_code "reg,subreg,mem,const,const_vector")
 555        (ior (match_operand 0 "register_operand")
 556             (match_operand 0 "aarch64_sve_ldr_operand")
 557             (match_test "aarch64_mov_operand_p (op, mode)"))))
 558
 559 (define_predicate "aarch64_sve_struct_memory_operand"
 560   (and (match_code "mem")
 561        (match_test "aarch64_sve_struct_memory_operand_p (op)")))
 562
 563 (define_predicate "aarch64_sve_struct_nonimmediate_operand"
 564   (ior (match_operand 0 "register_operand")
 565        (match_operand 0 "aarch64_sve_struct_memory_operand")))
 566
 567 ;; Doesn't include immediates, since those are handled by the move
 568 ;; patterns instead.
 569 (define_predicate "aarch64_sve_dup_operand"
 570   (ior (match_operand 0 "register_operand")
 571        (match_operand 0 "aarch64_sve_ld1r_operand")))
 572
 573 (define_predicate "aarch64_sve_arith_immediate"
 574   (and (match_code "const,const_vector")
 575        (match_test "aarch64_sve_arith_immediate_p (op, false)")))
 576
 577 (define_predicate "aarch64_sve_sub_arith_immediate"
 578   (and (match_code "const,const_vector")
 579        (match_test "aarch64_sve_arith_immediate_p (op, true)")))
 580
 581 (define_predicate "aarch64_sve_inc_dec_immediate"
 582   (and (match_code "const,const_vector")
 583        (match_test "aarch64_sve_inc_dec_immediate_p (op)")))
 584
 585 (define_predicate "aarch64_sve_logical_immediate"
 586   (and (match_code "const,const_vector")
 587        (match_test "aarch64_sve_bitmask_immediate_p (op)")))
 588
 589 (define_predicate "aarch64_sve_mul_immediate"
 590   (and (match_code "const,const_vector")
 591        (match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)")))
 592
 593 (define_predicate "aarch64_sve_dup_immediate"
 594   (and (match_code "const,const_vector")
 595        (match_test "aarch64_sve_dup_immediate_p (op)")))
 596
 597 (define_predicate "aarch64_sve_cmp_vsc_immediate"
 598   (and (match_code "const,const_vector")
 599        (match_test "aarch64_sve_cmp_immediate_p (op, true)")))
 600
 601 (define_predicate "aarch64_sve_cmp_vsd_immediate"
 602   (and (match_code "const,const_vector")
 603        (match_test "aarch64_sve_cmp_immediate_p (op, false)")))
 604
 605 (define_predicate "aarch64_sve_index_immediate"
 606   (and (match_code "const_int")
 607        (match_test "aarch64_sve_index_immediate_p (op)")))
 608
 609 (define_predicate "aarch64_sve_float_arith_immediate"
 610   (and (match_code "const,const_vector")
 611        (match_test "aarch64_sve_float_arith_immediate_p (op, false)")))
 612
 613 (define_predicate "aarch64_sve_float_arith_with_sub_immediate"
 614   (and (match_code "const,const_vector")
 615        (match_test "aarch64_sve_float_arith_immediate_p (op, true)")))
 616
 617 (define_predicate "aarch64_sve_float_mul_immediate"
 618   (and (match_code "const,const_vector")
 619        (match_test "aarch64_sve_float_mul_immediate_p (op)")))
 620
 621 (define_predicate "aarch64_sve_arith_operand"
 622   (ior (match_operand 0 "register_operand")
 623        (match_operand 0 "aarch64_sve_arith_immediate")))
 624
 625 (define_predicate "aarch64_sve_add_operand"
 626   (ior (match_operand 0 "aarch64_sve_arith_operand")
 627        (match_operand 0 "aarch64_sve_sub_arith_immediate")
 628        (match_operand 0 "aarch64_sve_inc_dec_immediate")))
 629
 630 (define_predicate "aarch64_sve_logical_operand"
 631   (ior (match_operand 0 "register_operand")
 632        (match_operand 0 "aarch64_sve_logical_immediate")))
 633
 634 (define_predicate "aarch64_sve_lshift_operand"
 635   (ior (match_operand 0 "register_operand")
 636        (match_operand 0 "aarch64_simd_lshift_imm")))
 637
 638 (define_predicate "aarch64_sve_rshift_operand"
 639   (ior (match_operand 0 "register_operand")
 640        (match_operand 0 "aarch64_simd_rshift_imm")))
 641
 642 (define_predicate "aarch64_sve_mul_operand"
 643   (ior (match_operand 0 "register_operand")
 644        (match_operand 0 "aarch64_sve_mul_immediate")))
 645
 646 (define_predicate "aarch64_sve_cmp_vsc_operand"
 647   (ior (match_operand 0 "register_operand")
 648        (match_operand 0 "aarch64_sve_cmp_vsc_immediate")))
 649
 650 (define_predicate "aarch64_sve_cmp_vsd_operand"
 651   (ior (match_operand 0 "register_operand")
 652        (match_operand 0 "aarch64_sve_cmp_vsd_immediate")))
 653
 654 (define_predicate "aarch64_sve_index_operand"
 655   (ior (match_operand 0 "register_operand")
 656        (match_operand 0 "aarch64_sve_index_immediate")))
 657
 658 (define_predicate "aarch64_sve_float_arith_operand"
 659   (ior (match_operand 0 "register_operand")
 660        (match_operand 0 "aarch64_sve_float_arith_immediate")))
 661
 662 (define_predicate "aarch64_sve_float_arith_with_sub_operand"
 663   (ior (match_operand 0 "aarch64_sve_float_arith_operand")
 664        (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate")))
 665
 666 (define_predicate "aarch64_sve_float_mul_operand"
 667   (ior (match_operand 0 "register_operand")
 668        (match_operand 0 "aarch64_sve_float_mul_immediate")))
 669
 670 (define_predicate "aarch64_sve_vec_perm_operand"
 671   (ior (match_operand 0 "register_operand")
 672        (match_operand 0 "aarch64_constant_vector_operand")))
 673
 674 (define_predicate "aarch64_gather_scale_operand_w"
 675   (and (match_code "const_int")
 676        (match_test "INTVAL (op) == 1 || INTVAL (op) == 4")))
 677
 678 (define_predicate "aarch64_gather_scale_operand_d"
 679   (and (match_code "const_int")
 680        (match_test "INTVAL (op) == 1 || INTVAL (op) == 8")))
 681
 682 ;; A special predicate that doesn't match a particular mode.
 683 (define_special_predicate "aarch64_any_register_operand"
 684   (match_code "reg"))
 685
 686 (define_predicate "aarch64_sve_any_binary_operator"
 687   (match_code "plus,minus,mult,div,udiv,smax,umax,smin,umin,and,ior,xor"))