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AArch64: Refactor costs models to different files.
[thirdparty/gcc.git] / gcc / config / aarch64 / tuning_models / ampere1.h
1 /* Tuning model description for AArch64 architecture.
2 Copyright (C) 2009-2023 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #ifndef GCC_AARCH64_H_AMPERE1
21 #define GCC_AARCH64_H_AMPERE1
22
23 #include "generic.h"
24
25 static const advsimd_vec_cost ampere1_advsimd_vector_cost =
26 {
27 1, /* int_stmt_cost */
28 3, /* fp_stmt_cost */
29 0, /* ld2_st2_permute_cost */
30 0, /* ld3_st3_permute_cost */
31 0, /* ld4_st4_permute_cost */
32 2, /* permute_cost */
33 12, /* reduc_i8_cost */
34 9, /* reduc_i16_cost */
35 6, /* reduc_i32_cost */
36 5, /* reduc_i64_cost */
37 9, /* reduc_f16_cost */
38 6, /* reduc_f32_cost */
39 5, /* reduc_f64_cost */
40 8, /* store_elt_extra_cost */
41 6, /* vec_to_scalar_cost */
42 7, /* scalar_to_vec_cost */
43 4, /* align_load_cost */
44 4, /* unalign_load_cost */
45 1, /* unalign_store_cost */
46 1 /* store_cost */
47 };
48
49 /* Ampere-1 costs for vector insn classes. */
50 static const struct cpu_vector_cost ampere1_vector_cost =
51 {
52 1, /* scalar_int_stmt_cost */
53 3, /* scalar_fp_stmt_cost */
54 4, /* scalar_load_cost */
55 1, /* scalar_store_cost */
56 1, /* cond_taken_branch_cost */
57 1, /* cond_not_taken_branch_cost */
58 &ampere1_advsimd_vector_cost, /* advsimd */
59 nullptr, /* sve */
60 nullptr /* issue_info */
61 };
62
63 static const cpu_prefetch_tune ampere1_prefetch_tune =
64 {
65 0, /* num_slots */
66 64, /* l1_cache_size */
67 64, /* l1_cache_line_size */
68 2048, /* l2_cache_size */
69 true, /* prefetch_dynamic_strides */
70 -1, /* minimum_stride */
71 -1 /* default_opt_level */
72 };
73
74 static const struct tune_params ampere1_tunings =
75 {
76 &ampere1_extra_costs,
77 &generic_addrcost_table,
78 &generic_regmove_cost,
79 &ampere1_vector_cost,
80 &generic_branch_cost,
81 &generic_approx_modes,
82 SVE_NOT_IMPLEMENTED, /* sve_width */
83 { 4, /* load_int. */
84 4, /* store_int. */
85 4, /* load_fp. */
86 4, /* store_fp. */
87 4, /* load_pred. */
88 4 /* store_pred. */
89 }, /* memmov_cost. */
90 4, /* issue_rate */
91 (AARCH64_FUSE_ADRP_ADD | AARCH64_FUSE_AES_AESMC |
92 AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_MOVK_MOVK |
93 AARCH64_FUSE_ALU_BRANCH /* adds, ands, bics, ccmp, ccmn */ |
94 AARCH64_FUSE_CMP_BRANCH),
95 /* fusible_ops */
96 "32", /* function_align. */
97 "4", /* jump_align. */
98 "32:16", /* loop_align. */
99 2, /* int_reassoc_width. */
100 4, /* fp_reassoc_width. */
101 4, /* fma_reassoc_width. */
102 2, /* vec_reassoc_width. */
103 2, /* min_div_recip_mul_sf. */
104 2, /* min_div_recip_mul_df. */
105 0, /* max_case_values. */
106 tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */
107 (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */
108 &ampere1_prefetch_tune,
109 AARCH64_LDP_STP_POLICY_ALIGNED, /* ldp_policy_model. */
110 AARCH64_LDP_STP_POLICY_ALIGNED /* stp_policy_model. */
111 };
112
113 #endif /* GCC_AARCH64_H_AMPERE1. */