gcc/config/aarch64/tuning_models/neoversen2.h

   1 /* Tuning model description for AArch64 architecture.
   2    Copyright (C) 2009-2024 Free Software Foundation, Inc.
   3
   4    This file is part of GCC.
   5
   6    GCC is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    GCC is distributed in the hope that it will be useful, but
  12    WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14    General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GCC; see the file COPYING3.  If not see
  18    <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef GCC_AARCH64_H_NEOVERSEN2
  21 #define GCC_AARCH64_H_NEOVERSEN2
  22
  23 #include "generic.h"
  24
  25 static const struct cpu_addrcost_table neoversen2_addrcost_table =
  26 {
  27     {
  28       1, /* hi  */
  29       0, /* si  */
  30       0, /* di  */
  31       1, /* ti  */
  32     },
  33   0, /* pre_modify  */
  34   0, /* post_modify  */
  35   2, /* post_modify_ld3_st3  */
  36   2, /* post_modify_ld4_st4  */
  37   0, /* register_offset  */
  38   0, /* register_sextend  */
  39   0, /* register_zextend  */
  40   0 /* imm_offset  */
  41 };
  42
  43 static const struct cpu_regmove_cost neoversen2_regmove_cost =
  44 {
  45   1, /* GP2GP  */
  46   /* Spilling to int<->fp instead of memory is recommended so set
  47      realistic costs compared to memmov_cost.  */
  48   3, /* GP2FP  */
  49   2, /* FP2GP  */
  50   2 /* FP2FP  */
  51 };
  52
  53 static const advsimd_vec_cost neoversen2_advsimd_vector_cost =
  54 {
  55   2, /* int_stmt_cost  */
  56   2, /* fp_stmt_cost  */
  57   2, /* ld2_st2_permute_cost */
  58   2, /* ld3_st3_permute_cost  */
  59   3, /* ld4_st4_permute_cost  */
  60   3, /* permute_cost  */
  61   4, /* reduc_i8_cost  */
  62   4, /* reduc_i16_cost  */
  63   2, /* reduc_i32_cost  */
  64   2, /* reduc_i64_cost  */
  65   6, /* reduc_f16_cost  */
  66   4, /* reduc_f32_cost  */
  67   2, /* reduc_f64_cost  */
  68   2, /* store_elt_extra_cost  */
  69   /* This value is just inherited from the Cortex-A57 table.  */
  70   8, /* vec_to_scalar_cost  */
  71   /* This depends very much on what the scalar value is and
  72      where it comes from.  E.g. some constants take two dependent
  73      instructions or a load, while others might be moved from a GPR.
  74      4 seems to be a reasonable compromise in practice.  */
  75   4, /* scalar_to_vec_cost  */
  76   4, /* align_load_cost  */
  77   4, /* unalign_load_cost  */
  78   /* Although stores have a latency of 2 and compete for the
  79      vector pipes, in practice it's better not to model that.  */
  80   1, /* unalign_store_cost  */
  81   1  /* store_cost  */
  82 };
  83
  84 static const sve_vec_cost neoversen2_sve_vector_cost =
  85 {
  86   {
  87     2, /* int_stmt_cost  */
  88     2, /* fp_stmt_cost  */
  89     3, /* ld2_st2_permute_cost  */
  90     4, /* ld3_st3_permute_cost  */
  91     4, /* ld4_st4_permute_cost  */
  92     3, /* permute_cost  */
  93     /* Theoretically, a reduction involving 15 scalar ADDs could
  94        complete in ~5 cycles and would have a cost of 15.  [SU]ADDV
  95        completes in 11 cycles, so give it a cost of 15 + 6.  */
  96     21, /* reduc_i8_cost  */
  97     /* Likewise for 7 scalar ADDs (~3 cycles) vs. 9: 7 + 6.  */
  98     13, /* reduc_i16_cost  */
  99     /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 6.  */
 100     9, /* reduc_i32_cost  */
 101     /* Likewise for 1 scalar ADD (~1 cycles) vs. 2: 1 + 1.  */
 102     2, /* reduc_i64_cost  */
 103     /* Theoretically, a reduction involving 7 scalar FADDs could
 104        complete in ~8 cycles and would have a cost of 14.  FADDV
 105        completes in 6 cycles, so give it a cost of 14 - 2.  */
 106     12, /* reduc_f16_cost  */
 107     /* Likewise for 3 scalar FADDs (~4 cycles) vs. 4: 6 - 0.  */
 108     6, /* reduc_f32_cost  */
 109     /* Likewise for 1 scalar FADD (~2 cycles) vs. 2: 2 - 0.  */
 110     2, /* reduc_f64_cost  */
 111     2, /* store_elt_extra_cost  */
 112     /* This value is just inherited from the Cortex-A57 table.  */
 113     8, /* vec_to_scalar_cost  */
 114     /* See the comment above the Advanced SIMD versions.  */
 115     4, /* scalar_to_vec_cost  */
 116     4, /* align_load_cost  */
 117     4, /* unalign_load_cost  */
 118     /* Although stores have a latency of 2 and compete for the
 119        vector pipes, in practice it's better not to model that.  */
 120     1, /* unalign_store_cost  */
 121     1  /* store_cost  */
 122   },
 123   3, /* clast_cost  */
 124   10, /* fadda_f16_cost  */
 125   6, /* fadda_f32_cost  */
 126   4, /* fadda_f64_cost  */
 127   /* A strided Advanced SIMD x64 load would take two parallel FP loads
 128      (8 cycles) plus an insertion (2 cycles).  Assume a 64-bit SVE gather
 129      is 1 cycle more.  The Advanced SIMD version is costed as 2 scalar loads
 130      (cost 8) and a vec_construct (cost 2).  Add a full vector operation
 131      (cost 2) to that, to avoid the difference being lost in rounding.
 132
 133      There is no easy comparison between a strided Advanced SIMD x32 load
 134      and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
 135      operation more than a 64-bit gather.  */
 136   14, /* gather_load_x32_cost  */
 137   12, /* gather_load_x64_cost  */
 138   3 /* scatter_store_elt_cost  */
 139 };
 140
 141 static const aarch64_scalar_vec_issue_info neoversen2_scalar_issue_info =
 142 {
 143   3, /* loads_stores_per_cycle  */
 144   2, /* stores_per_cycle  */
 145   4, /* general_ops_per_cycle  */
 146   0, /* fp_simd_load_general_ops  */
 147   1 /* fp_simd_store_general_ops  */
 148 };
 149
 150 static const aarch64_advsimd_vec_issue_info neoversen2_advsimd_issue_info =
 151 {
 152   {
 153     3, /* loads_stores_per_cycle  */
 154     2, /* stores_per_cycle  */
 155     2, /* general_ops_per_cycle  */
 156     0, /* fp_simd_load_general_ops  */
 157     1 /* fp_simd_store_general_ops  */
 158   },
 159   2, /* ld2_st2_general_ops  */
 160   2, /* ld3_st3_general_ops  */
 161   3 /* ld4_st4_general_ops  */
 162 };
 163
 164 static const aarch64_sve_vec_issue_info neoversen2_sve_issue_info =
 165 {
 166   {
 167     {
 168       3, /* loads_per_cycle  */
 169       2, /* stores_per_cycle  */
 170       2, /* general_ops_per_cycle  */
 171       0, /* fp_simd_load_general_ops  */
 172       1 /* fp_simd_store_general_ops  */
 173     },
 174     2, /* ld2_st2_general_ops  */
 175     3, /* ld3_st3_general_ops  */
 176     3 /* ld4_st4_general_ops  */
 177   },
 178   2, /* pred_ops_per_cycle  */
 179   2, /* while_pred_ops  */
 180   2, /* int_cmp_pred_ops  */
 181   1, /* fp_cmp_pred_ops  */
 182   1, /* gather_scatter_pair_general_ops  */
 183   1 /* gather_scatter_pair_pred_ops  */
 184 };
 185
 186 static const aarch64_vec_issue_info neoversen2_vec_issue_info =
 187 {
 188   &neoversen2_scalar_issue_info,
 189   &neoversen2_advsimd_issue_info,
 190   &neoversen2_sve_issue_info
 191 };
 192
 193 /* Neoverse N2 costs for vector insn classes.  */
 194 static const struct cpu_vector_cost neoversen2_vector_cost =
 195 {
 196   1, /* scalar_int_stmt_cost  */
 197   2, /* scalar_fp_stmt_cost  */
 198   4, /* scalar_load_cost  */
 199   1, /* scalar_store_cost  */
 200   1, /* cond_taken_branch_cost  */
 201   1, /* cond_not_taken_branch_cost  */
 202   &neoversen2_advsimd_vector_cost, /* advsimd  */
 203   &neoversen2_sve_vector_cost, /* sve  */
 204   &neoversen2_vec_issue_info /* issue_info  */
 205 };
 206
 207 static const struct tune_params neoversen2_tunings =
 208 {
 209   &cortexa76_extra_costs,
 210   &neoversen2_addrcost_table,
 211   &neoversen2_regmove_cost,
 212   &neoversen2_vector_cost,
 213   &generic_branch_cost,
 214   &generic_approx_modes,
 215   SVE_128, /* sve_width  */
 216   { 4, /* load_int.  */
 217     1, /* store_int.  */
 218     6, /* load_fp.  */
 219     2, /* store_fp.  */
 220     6, /* load_pred.  */
 221     1 /* store_pred.  */
 222   }, /* memmov_cost.  */
 223   3, /* issue_rate  */
 224   (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_CMP_BRANCH), /* fusible_ops  */
 225   "32:16",      /* function_align.  */
 226   "4",          /* jump_align.  */
 227   "32:16",      /* loop_align.  */
 228   2,    /* int_reassoc_width.  */
 229   4,    /* fp_reassoc_width.  */
 230   1,    /* fma_reassoc_width.  */
 231   2,    /* vec_reassoc_width.  */
 232   2,    /* min_div_recip_mul_sf.  */
 233   2,    /* min_div_recip_mul_df.  */
 234   0,    /* max_case_values.  */
 235   tune_params::AUTOPREFETCHER_WEAK,     /* autoprefetcher_model.  */
 236   (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
 237    | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
 238    | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
 239    | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT),     /* tune_flags.  */
 240   &generic_prefetch_tune,
 241   AARCH64_LDP_STP_POLICY_ALWAYS,   /* ldp_policy_model.  */
 242   AARCH64_LDP_STP_POLICY_ALWAYS    /* stp_policy_model.  */
 243 };
 244
 245 #endif /* GCC_AARCH64_H_NEOVERSEN2.  */