1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
44 #include "diagnostic-core.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
52 #include "splay-tree.h"
53 #include "cfglayout.h"
55 #include "tree-flow.h"
56 #include "tree-stdarg.h"
57 #include "tm-constrs.h"
62 /* Specify which cpu to schedule for. */
63 enum processor_type alpha_tune
;
65 /* Which cpu we're generating code for. */
66 enum processor_type alpha_cpu
;
68 static const char * const alpha_cpu_name
[] =
73 /* Specify how accurate floating-point traps need to be. */
75 enum alpha_trap_precision alpha_tp
;
77 /* Specify the floating-point rounding mode. */
79 enum alpha_fp_rounding_mode alpha_fprm
;
81 /* Specify which things cause traps. */
83 enum alpha_fp_trap_mode alpha_fptm
;
85 /* Nonzero if inside of a function, because the Alpha asm can't
86 handle .files inside of functions. */
88 static int inside_function
= FALSE
;
90 /* The number of cycles of latency we should assume on memory reads. */
92 int alpha_memory_latency
= 3;
94 /* Whether the function needs the GP. */
96 static int alpha_function_needs_gp
;
98 /* The alias set for prologue/epilogue register save/restore. */
100 static GTY(()) alias_set_type alpha_sr_alias_set
;
102 /* The assembler name of the current function. */
104 static const char *alpha_fnname
;
106 /* The next explicit relocation sequence number. */
107 extern GTY(()) int alpha_next_sequence_number
;
108 int alpha_next_sequence_number
= 1;
110 /* The literal and gpdisp sequence numbers for this insn, as printed
111 by %# and %* respectively. */
112 extern GTY(()) int alpha_this_literal_sequence_number
;
113 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
114 int alpha_this_literal_sequence_number
;
115 int alpha_this_gpdisp_sequence_number
;
117 /* Costs of various operations on the different architectures. */
119 struct alpha_rtx_cost_data
121 unsigned char fp_add
;
122 unsigned char fp_mult
;
123 unsigned char fp_div_sf
;
124 unsigned char fp_div_df
;
125 unsigned char int_mult_si
;
126 unsigned char int_mult_di
;
127 unsigned char int_shift
;
128 unsigned char int_cmov
;
129 unsigned short int_div
;
132 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
135 COSTS_N_INSNS (6), /* fp_add */
136 COSTS_N_INSNS (6), /* fp_mult */
137 COSTS_N_INSNS (34), /* fp_div_sf */
138 COSTS_N_INSNS (63), /* fp_div_df */
139 COSTS_N_INSNS (23), /* int_mult_si */
140 COSTS_N_INSNS (23), /* int_mult_di */
141 COSTS_N_INSNS (2), /* int_shift */
142 COSTS_N_INSNS (2), /* int_cmov */
143 COSTS_N_INSNS (97), /* int_div */
146 COSTS_N_INSNS (4), /* fp_add */
147 COSTS_N_INSNS (4), /* fp_mult */
148 COSTS_N_INSNS (15), /* fp_div_sf */
149 COSTS_N_INSNS (22), /* fp_div_df */
150 COSTS_N_INSNS (8), /* int_mult_si */
151 COSTS_N_INSNS (12), /* int_mult_di */
152 COSTS_N_INSNS (1) + 1, /* int_shift */
153 COSTS_N_INSNS (1), /* int_cmov */
154 COSTS_N_INSNS (83), /* int_div */
157 COSTS_N_INSNS (4), /* fp_add */
158 COSTS_N_INSNS (4), /* fp_mult */
159 COSTS_N_INSNS (12), /* fp_div_sf */
160 COSTS_N_INSNS (15), /* fp_div_df */
161 COSTS_N_INSNS (7), /* int_mult_si */
162 COSTS_N_INSNS (7), /* int_mult_di */
163 COSTS_N_INSNS (1), /* int_shift */
164 COSTS_N_INSNS (2), /* int_cmov */
165 COSTS_N_INSNS (86), /* int_div */
169 /* Similar but tuned for code size instead of execution latency. The
170 extra +N is fractional cost tuning based on latency. It's used to
171 encourage use of cheaper insns like shift, but only if there's just
174 static struct alpha_rtx_cost_data
const alpha_rtx_cost_size
=
176 COSTS_N_INSNS (1), /* fp_add */
177 COSTS_N_INSNS (1), /* fp_mult */
178 COSTS_N_INSNS (1), /* fp_div_sf */
179 COSTS_N_INSNS (1) + 1, /* fp_div_df */
180 COSTS_N_INSNS (1) + 1, /* int_mult_si */
181 COSTS_N_INSNS (1) + 2, /* int_mult_di */
182 COSTS_N_INSNS (1), /* int_shift */
183 COSTS_N_INSNS (1), /* int_cmov */
184 COSTS_N_INSNS (6), /* int_div */
187 /* Get the number of args of a function in one of two ways. */
188 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
189 #define NUM_ARGS crtl->args.info.num_args
191 #define NUM_ARGS crtl->args.info
197 /* Declarations of static functions. */
198 static struct machine_function
*alpha_init_machine_status (void);
199 static rtx
alpha_emit_xfloating_compare (enum rtx_code
*, rtx
, rtx
);
201 #if TARGET_ABI_OPEN_VMS
202 static void alpha_write_linkage (FILE *, const char *, tree
);
203 static bool vms_valid_pointer_mode (enum machine_mode
);
206 static void unicosmk_output_deferred_case_vectors (FILE *);
207 static void unicosmk_gen_dsib (unsigned long *);
208 static void unicosmk_output_ssib (FILE *, const char *);
209 static int unicosmk_need_dex (rtx
);
211 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
212 static const struct default_options alpha_option_optimization_table
[] =
214 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
215 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
218 /* Implement TARGET_HANDLE_OPTION. */
221 alpha_handle_option (struct gcc_options
*opts
, struct gcc_options
*opts_set
,
222 const struct cl_decoded_option
*decoded
,
223 location_t loc ATTRIBUTE_UNUSED
)
225 size_t code
= decoded
->opt_index
;
226 const char *arg
= decoded
->arg
;
227 int value
= decoded
->value
;
229 gcc_assert (opts
== &global_options
);
230 gcc_assert (opts_set
== &global_options_set
);
236 target_flags
|= MASK_SOFT_FP
;
240 case OPT_mieee_with_inexact
:
241 target_flags
|= MASK_IEEE_CONFORMANT
;
245 if (value
!= 16 && value
!= 32 && value
!= 64)
246 error ("bad value %qs for -mtls-size switch", arg
);
253 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
254 /* Implement TARGET_MANGLE_TYPE. */
257 alpha_mangle_type (const_tree type
)
259 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
260 && TARGET_LONG_DOUBLE_128
)
263 /* For all other types, use normal C++ mangling. */
268 /* Parse target option strings. */
271 alpha_option_override (void)
273 static const struct cpu_table
{
274 const char *const name
;
275 const enum processor_type processor
;
278 { "ev4", PROCESSOR_EV4
, 0 },
279 { "ev45", PROCESSOR_EV4
, 0 },
280 { "21064", PROCESSOR_EV4
, 0 },
281 { "ev5", PROCESSOR_EV5
, 0 },
282 { "21164", PROCESSOR_EV5
, 0 },
283 { "ev56", PROCESSOR_EV5
, MASK_BWX
},
284 { "21164a", PROCESSOR_EV5
, MASK_BWX
},
285 { "pca56", PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
286 { "21164PC",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
287 { "21164pc",PROCESSOR_EV5
, MASK_BWX
|MASK_MAX
},
288 { "ev6", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
289 { "21264", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
},
290 { "ev67", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
},
291 { "21264a", PROCESSOR_EV6
, MASK_BWX
|MASK_MAX
|MASK_FIX
|MASK_CIX
}
294 int const ct_size
= ARRAY_SIZE (cpu_table
);
297 #ifdef SUBTARGET_OVERRIDE_OPTIONS
298 SUBTARGET_OVERRIDE_OPTIONS
;
301 /* Unicos/Mk doesn't have shared libraries. */
302 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
304 warning (0, "-f%s ignored for Unicos/Mk (not supported)",
305 (flag_pic
> 1) ? "PIC" : "pic");
309 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
310 floating-point instructions. Make that the default for this target. */
311 if (TARGET_ABI_UNICOSMK
)
312 alpha_fprm
= ALPHA_FPRM_DYN
;
314 alpha_fprm
= ALPHA_FPRM_NORM
;
316 alpha_tp
= ALPHA_TP_PROG
;
317 alpha_fptm
= ALPHA_FPTM_N
;
319 /* We cannot use su and sui qualifiers for conversion instructions on
320 Unicos/Mk. I'm not sure if this is due to assembler or hardware
321 limitations. Right now, we issue a warning if -mieee is specified
322 and then ignore it; eventually, we should either get it right or
323 disable the option altogether. */
327 if (TARGET_ABI_UNICOSMK
)
328 warning (0, "-mieee not supported on Unicos/Mk");
331 alpha_tp
= ALPHA_TP_INSN
;
332 alpha_fptm
= ALPHA_FPTM_SU
;
336 if (TARGET_IEEE_WITH_INEXACT
)
338 if (TARGET_ABI_UNICOSMK
)
339 warning (0, "-mieee-with-inexact not supported on Unicos/Mk");
342 alpha_tp
= ALPHA_TP_INSN
;
343 alpha_fptm
= ALPHA_FPTM_SUI
;
349 if (! strcmp (alpha_tp_string
, "p"))
350 alpha_tp
= ALPHA_TP_PROG
;
351 else if (! strcmp (alpha_tp_string
, "f"))
352 alpha_tp
= ALPHA_TP_FUNC
;
353 else if (! strcmp (alpha_tp_string
, "i"))
354 alpha_tp
= ALPHA_TP_INSN
;
356 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string
);
359 if (alpha_fprm_string
)
361 if (! strcmp (alpha_fprm_string
, "n"))
362 alpha_fprm
= ALPHA_FPRM_NORM
;
363 else if (! strcmp (alpha_fprm_string
, "m"))
364 alpha_fprm
= ALPHA_FPRM_MINF
;
365 else if (! strcmp (alpha_fprm_string
, "c"))
366 alpha_fprm
= ALPHA_FPRM_CHOP
;
367 else if (! strcmp (alpha_fprm_string
,"d"))
368 alpha_fprm
= ALPHA_FPRM_DYN
;
370 error ("bad value %qs for -mfp-rounding-mode switch",
374 if (alpha_fptm_string
)
376 if (strcmp (alpha_fptm_string
, "n") == 0)
377 alpha_fptm
= ALPHA_FPTM_N
;
378 else if (strcmp (alpha_fptm_string
, "u") == 0)
379 alpha_fptm
= ALPHA_FPTM_U
;
380 else if (strcmp (alpha_fptm_string
, "su") == 0)
381 alpha_fptm
= ALPHA_FPTM_SU
;
382 else if (strcmp (alpha_fptm_string
, "sui") == 0)
383 alpha_fptm
= ALPHA_FPTM_SUI
;
385 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string
);
388 if (alpha_cpu_string
)
390 for (i
= 0; i
< ct_size
; i
++)
391 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
393 alpha_tune
= alpha_cpu
= cpu_table
[i
].processor
;
394 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
);
395 target_flags
|= cpu_table
[i
].flags
;
399 error ("bad value %qs for -mcpu switch", alpha_cpu_string
);
402 if (alpha_tune_string
)
404 for (i
= 0; i
< ct_size
; i
++)
405 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
407 alpha_tune
= cpu_table
[i
].processor
;
411 error ("bad value %qs for -mtune switch", alpha_tune_string
);
414 /* Do some sanity checks on the above options. */
416 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
418 warning (0, "trap mode not supported on Unicos/Mk");
419 alpha_fptm
= ALPHA_FPTM_N
;
422 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
423 && alpha_tp
!= ALPHA_TP_INSN
&& alpha_cpu
!= PROCESSOR_EV6
)
425 warning (0, "fp software completion requires -mtrap-precision=i");
426 alpha_tp
= ALPHA_TP_INSN
;
429 if (alpha_cpu
== PROCESSOR_EV6
)
431 /* Except for EV6 pass 1 (not released), we always have precise
432 arithmetic traps. Which means we can do software completion
433 without minding trap shadows. */
434 alpha_tp
= ALPHA_TP_PROG
;
437 if (TARGET_FLOAT_VAX
)
439 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
441 warning (0, "rounding mode not supported for VAX floats");
442 alpha_fprm
= ALPHA_FPRM_NORM
;
444 if (alpha_fptm
== ALPHA_FPTM_SUI
)
446 warning (0, "trap mode not supported for VAX floats");
447 alpha_fptm
= ALPHA_FPTM_SU
;
449 if (target_flags_explicit
& MASK_LONG_DOUBLE_128
)
450 warning (0, "128-bit long double not supported for VAX floats");
451 target_flags
&= ~MASK_LONG_DOUBLE_128
;
458 if (!alpha_mlat_string
)
459 alpha_mlat_string
= "L1";
461 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
462 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
464 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
465 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
466 && alpha_mlat_string
[2] == '\0')
468 static int const cache_latency
[][4] =
470 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
471 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
472 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
475 lat
= alpha_mlat_string
[1] - '0';
476 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_tune
][lat
-1] == -1)
478 warning (0, "L%d cache latency unknown for %s",
479 lat
, alpha_cpu_name
[alpha_tune
]);
483 lat
= cache_latency
[alpha_tune
][lat
-1];
485 else if (! strcmp (alpha_mlat_string
, "main"))
487 /* Most current memories have about 370ns latency. This is
488 a reasonable guess for a fast cpu. */
493 warning (0, "bad value %qs for -mmemory-latency", alpha_mlat_string
);
497 alpha_memory_latency
= lat
;
500 /* Default the definition of "small data" to 8 bytes. */
501 if (!global_options_set
.x_g_switch_value
)
504 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
506 target_flags
|= MASK_SMALL_DATA
;
507 else if (flag_pic
== 2)
508 target_flags
&= ~MASK_SMALL_DATA
;
510 /* Align labels and loops for optimal branching. */
511 /* ??? Kludge these by not doing anything if we don't optimize and also if
512 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
513 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
515 if (align_loops
<= 0)
517 if (align_jumps
<= 0)
520 if (align_functions
<= 0)
521 align_functions
= 16;
523 /* Acquire a unique set number for our register saves and restores. */
524 alpha_sr_alias_set
= new_alias_set ();
526 /* Register variables and functions with the garbage collector. */
528 /* Set up function hooks. */
529 init_machine_status
= alpha_init_machine_status
;
531 /* Tell the compiler when we're using VAX floating point. */
532 if (TARGET_FLOAT_VAX
)
534 REAL_MODE_FORMAT (SFmode
) = &vax_f_format
;
535 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
536 REAL_MODE_FORMAT (TFmode
) = NULL
;
539 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
540 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
541 target_flags
|= MASK_LONG_DOUBLE_128
;
544 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
545 can be optimized to ap = __builtin_next_arg (0). */
546 if (TARGET_ABI_UNICOSMK
)
547 targetm
.expand_builtin_va_start
= NULL
;
550 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
553 zap_mask (HOST_WIDE_INT value
)
557 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
559 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
565 /* Return true if OP is valid for a particular TLS relocation.
566 We are already guaranteed that OP is a CONST. */
569 tls_symbolic_operand_1 (rtx op
, int size
, int unspec
)
573 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
575 op
= XVECEXP (op
, 0, 0);
577 if (GET_CODE (op
) != SYMBOL_REF
)
580 switch (SYMBOL_REF_TLS_MODEL (op
))
582 case TLS_MODEL_LOCAL_DYNAMIC
:
583 return unspec
== UNSPEC_DTPREL
&& size
== alpha_tls_size
;
584 case TLS_MODEL_INITIAL_EXEC
:
585 return unspec
== UNSPEC_TPREL
&& size
== 64;
586 case TLS_MODEL_LOCAL_EXEC
:
587 return unspec
== UNSPEC_TPREL
&& size
== alpha_tls_size
;
593 /* Used by aligned_memory_operand and unaligned_memory_operand to
594 resolve what reload is going to do with OP if it's a register. */
597 resolve_reload_operand (rtx op
)
599 if (reload_in_progress
)
602 if (GET_CODE (tmp
) == SUBREG
)
603 tmp
= SUBREG_REG (tmp
);
605 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
607 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
615 /* The scalar modes supported differs from the default check-what-c-supports
616 version in that sometimes TFmode is available even when long double
617 indicates only DFmode. On unicosmk, we have the situation that HImode
618 doesn't map to any C type, but of course we still support that. */
621 alpha_scalar_mode_supported_p (enum machine_mode mode
)
629 case TImode
: /* via optabs.c */
637 return TARGET_HAS_XFLOATING_LIBS
;
644 /* Alpha implements a couple of integer vector mode operations when
645 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
646 which allows the vectorizer to operate on e.g. move instructions,
647 or when expand_vector_operations can do something useful. */
650 alpha_vector_mode_supported_p (enum machine_mode mode
)
652 return mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
;
655 /* Return 1 if this function can directly return via $26. */
660 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
662 && alpha_sa_size () == 0
663 && get_frame_size () == 0
664 && crtl
->outgoing_args_size
== 0
665 && crtl
->args
.pretend_args_size
== 0);
668 /* Return the ADDR_VEC associated with a tablejump insn. */
671 alpha_tablejump_addr_vec (rtx insn
)
675 tmp
= JUMP_LABEL (insn
);
678 tmp
= NEXT_INSN (tmp
);
682 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
683 return PATTERN (tmp
);
687 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
690 alpha_tablejump_best_label (rtx insn
)
692 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
693 rtx best_label
= NULL_RTX
;
695 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
696 there for edge frequency counts from profile data. */
700 int n_labels
= XVECLEN (jump_table
, 1);
704 for (i
= 0; i
< n_labels
; i
++)
708 for (j
= i
+ 1; j
< n_labels
; j
++)
709 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
710 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
713 if (count
> best_count
)
714 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
718 return best_label
? best_label
: const0_rtx
;
721 /* Return the TLS model to use for SYMBOL. */
723 static enum tls_model
724 tls_symbolic_operand_type (rtx symbol
)
726 enum tls_model model
;
728 if (GET_CODE (symbol
) != SYMBOL_REF
)
729 return TLS_MODEL_NONE
;
730 model
= SYMBOL_REF_TLS_MODEL (symbol
);
732 /* Local-exec with a 64-bit size is the same code as initial-exec. */
733 if (model
== TLS_MODEL_LOCAL_EXEC
&& alpha_tls_size
== 64)
734 model
= TLS_MODEL_INITIAL_EXEC
;
739 /* Return true if the function DECL will share the same GP as any
740 function in the current unit of translation. */
743 decl_has_samegp (const_tree decl
)
745 /* Functions that are not local can be overridden, and thus may
746 not share the same gp. */
747 if (!(*targetm
.binds_local_p
) (decl
))
750 /* If -msmall-data is in effect, assume that there is only one GP
751 for the module, and so any local symbol has this property. We
752 need explicit relocations to be able to enforce this for symbols
753 not defined in this unit of translation, however. */
754 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
757 /* Functions that are not external are defined in this UoT. */
758 /* ??? Irritatingly, static functions not yet emitted are still
759 marked "external". Apply this to non-static functions only. */
760 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
763 /* Return true if EXP should be placed in the small data section. */
766 alpha_in_small_data_p (const_tree exp
)
768 /* We want to merge strings, so we never consider them small data. */
769 if (TREE_CODE (exp
) == STRING_CST
)
772 /* Functions are never in the small data area. Duh. */
773 if (TREE_CODE (exp
) == FUNCTION_DECL
)
776 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
778 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
779 if (strcmp (section
, ".sdata") == 0
780 || strcmp (section
, ".sbss") == 0)
785 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
787 /* If this is an incomplete type with size 0, then we can't put it
788 in sdata because it might be too big when completed. */
789 if (size
> 0 && size
<= g_switch_value
)
796 #if TARGET_ABI_OPEN_VMS
798 vms_valid_pointer_mode (enum machine_mode mode
)
800 return (mode
== SImode
|| mode
== DImode
);
804 alpha_linkage_symbol_p (const char *symname
)
806 int symlen
= strlen (symname
);
809 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
814 #define LINKAGE_SYMBOL_REF_P(X) \
815 ((GET_CODE (X) == SYMBOL_REF \
816 && alpha_linkage_symbol_p (XSTR (X, 0))) \
817 || (GET_CODE (X) == CONST \
818 && GET_CODE (XEXP (X, 0)) == PLUS \
819 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
820 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
823 /* legitimate_address_p recognizes an RTL expression that is a valid
824 memory address for an instruction. The MODE argument is the
825 machine mode for the MEM expression that wants to use this address.
827 For Alpha, we have either a constant address or the sum of a
828 register and a constant address, or just a register. For DImode,
829 any of those forms can be surrounded with an AND that clear the
830 low-order three bits; this is an "unaligned" access. */
833 alpha_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
835 /* If this is an ldq_u type address, discard the outer AND. */
837 && GET_CODE (x
) == AND
838 && CONST_INT_P (XEXP (x
, 1))
839 && INTVAL (XEXP (x
, 1)) == -8)
842 /* Discard non-paradoxical subregs. */
843 if (GET_CODE (x
) == SUBREG
844 && (GET_MODE_SIZE (GET_MODE (x
))
845 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
848 /* Unadorned general registers are valid. */
851 ? STRICT_REG_OK_FOR_BASE_P (x
)
852 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
855 /* Constant addresses (i.e. +/- 32k) are valid. */
856 if (CONSTANT_ADDRESS_P (x
))
859 #if TARGET_ABI_OPEN_VMS
860 if (LINKAGE_SYMBOL_REF_P (x
))
864 /* Register plus a small constant offset is valid. */
865 if (GET_CODE (x
) == PLUS
)
867 rtx ofs
= XEXP (x
, 1);
870 /* Discard non-paradoxical subregs. */
871 if (GET_CODE (x
) == SUBREG
872 && (GET_MODE_SIZE (GET_MODE (x
))
873 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
879 && NONSTRICT_REG_OK_FP_BASE_P (x
)
880 && CONST_INT_P (ofs
))
883 ? STRICT_REG_OK_FOR_BASE_P (x
)
884 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
885 && CONSTANT_ADDRESS_P (ofs
))
890 /* If we're managing explicit relocations, LO_SUM is valid, as are small
891 data symbols. Avoid explicit relocations of modes larger than word
892 mode since i.e. $LC0+8($1) can fold around +/- 32k offset. */
893 else if (TARGET_EXPLICIT_RELOCS
894 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
896 if (small_symbolic_operand (x
, Pmode
))
899 if (GET_CODE (x
) == LO_SUM
)
901 rtx ofs
= XEXP (x
, 1);
904 /* Discard non-paradoxical subregs. */
905 if (GET_CODE (x
) == SUBREG
906 && (GET_MODE_SIZE (GET_MODE (x
))
907 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
910 /* Must have a valid base register. */
913 ? STRICT_REG_OK_FOR_BASE_P (x
)
914 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
917 /* The symbol must be local. */
918 if (local_symbolic_operand (ofs
, Pmode
)
919 || dtp32_symbolic_operand (ofs
, Pmode
)
920 || tp32_symbolic_operand (ofs
, Pmode
))
928 /* Build the SYMBOL_REF for __tls_get_addr. */
930 static GTY(()) rtx tls_get_addr_libfunc
;
933 get_tls_get_addr (void)
935 if (!tls_get_addr_libfunc
)
936 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
937 return tls_get_addr_libfunc
;
940 /* Try machine-dependent ways of modifying an illegitimate address
941 to be legitimate. If we find one, return the new, valid address. */
944 alpha_legitimize_address_1 (rtx x
, rtx scratch
, enum machine_mode mode
)
946 HOST_WIDE_INT addend
;
948 /* If the address is (plus reg const_int) and the CONST_INT is not a
949 valid offset, compute the high part of the constant and add it to
950 the register. Then our address is (plus temp low-part-const). */
951 if (GET_CODE (x
) == PLUS
952 && REG_P (XEXP (x
, 0))
953 && CONST_INT_P (XEXP (x
, 1))
954 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
956 addend
= INTVAL (XEXP (x
, 1));
961 /* If the address is (const (plus FOO const_int)), find the low-order
962 part of the CONST_INT. Then load FOO plus any high-order part of the
963 CONST_INT into a register. Our address is (plus reg low-part-const).
964 This is done to reduce the number of GOT entries. */
965 if (can_create_pseudo_p ()
966 && GET_CODE (x
) == CONST
967 && GET_CODE (XEXP (x
, 0)) == PLUS
968 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))
970 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
971 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
975 /* If we have a (plus reg const), emit the load as in (2), then add
976 the two registers, and finally generate (plus reg low-part-const) as
978 if (can_create_pseudo_p ()
979 && GET_CODE (x
) == PLUS
980 && REG_P (XEXP (x
, 0))
981 && GET_CODE (XEXP (x
, 1)) == CONST
982 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
983 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 1), 0), 1)))
985 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
986 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
987 XEXP (XEXP (XEXP (x
, 1), 0), 0),
988 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
992 /* If this is a local symbol, split the address into HIGH/LO_SUM parts.
993 Avoid modes larger than word mode since i.e. $LC0+8($1) can fold
994 around +/- 32k offset. */
995 if (TARGET_EXPLICIT_RELOCS
996 && GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
997 && symbolic_operand (x
, Pmode
))
999 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
1001 switch (tls_symbolic_operand_type (x
))
1003 case TLS_MODEL_NONE
:
1006 case TLS_MODEL_GLOBAL_DYNAMIC
:
1009 r0
= gen_rtx_REG (Pmode
, 0);
1010 r16
= gen_rtx_REG (Pmode
, 16);
1011 tga
= get_tls_get_addr ();
1012 dest
= gen_reg_rtx (Pmode
);
1013 seq
= GEN_INT (alpha_next_sequence_number
++);
1015 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
1016 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
1017 insn
= emit_call_insn (insn
);
1018 RTL_CONST_CALL_P (insn
) = 1;
1019 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1021 insn
= get_insns ();
1024 emit_libcall_block (insn
, dest
, r0
, x
);
1027 case TLS_MODEL_LOCAL_DYNAMIC
:
1030 r0
= gen_rtx_REG (Pmode
, 0);
1031 r16
= gen_rtx_REG (Pmode
, 16);
1032 tga
= get_tls_get_addr ();
1033 scratch
= gen_reg_rtx (Pmode
);
1034 seq
= GEN_INT (alpha_next_sequence_number
++);
1036 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
1037 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
1038 insn
= emit_call_insn (insn
);
1039 RTL_CONST_CALL_P (insn
) = 1;
1040 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
1042 insn
= get_insns ();
1045 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1046 UNSPEC_TLSLDM_CALL
);
1047 emit_libcall_block (insn
, scratch
, r0
, eqv
);
1049 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
1050 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1052 if (alpha_tls_size
== 64)
1054 dest
= gen_reg_rtx (Pmode
);
1055 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
1056 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
1059 if (alpha_tls_size
== 32)
1061 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1062 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
1063 scratch
= gen_reg_rtx (Pmode
);
1064 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
1066 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
1068 case TLS_MODEL_INITIAL_EXEC
:
1069 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1070 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1071 tp
= gen_reg_rtx (Pmode
);
1072 scratch
= gen_reg_rtx (Pmode
);
1073 dest
= gen_reg_rtx (Pmode
);
1075 emit_insn (gen_load_tp (tp
));
1076 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
1077 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
1080 case TLS_MODEL_LOCAL_EXEC
:
1081 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
1082 eqv
= gen_rtx_CONST (Pmode
, eqv
);
1083 tp
= gen_reg_rtx (Pmode
);
1085 emit_insn (gen_load_tp (tp
));
1086 if (alpha_tls_size
== 32)
1088 insn
= gen_rtx_HIGH (Pmode
, eqv
);
1089 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
1090 tp
= gen_reg_rtx (Pmode
);
1091 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
1093 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
1099 if (local_symbolic_operand (x
, Pmode
))
1101 if (small_symbolic_operand (x
, Pmode
))
1105 if (can_create_pseudo_p ())
1106 scratch
= gen_reg_rtx (Pmode
);
1107 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1108 gen_rtx_HIGH (Pmode
, x
)));
1109 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1118 HOST_WIDE_INT low
, high
;
1120 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1122 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1126 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1127 (!can_create_pseudo_p () ? scratch
: NULL_RTX
),
1128 1, OPTAB_LIB_WIDEN
);
1130 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1131 (!can_create_pseudo_p () ? scratch
: NULL_RTX
),
1132 1, OPTAB_LIB_WIDEN
);
1134 return plus_constant (x
, low
);
1139 /* Try machine-dependent ways of modifying an illegitimate address
1140 to be legitimate. Return X or the new, valid address. */
1143 alpha_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1144 enum machine_mode mode
)
1146 rtx new_x
= alpha_legitimize_address_1 (x
, NULL_RTX
, mode
);
1147 return new_x
? new_x
: x
;
1150 /* Primarily this is required for TLS symbols, but given that our move
1151 patterns *ought* to be able to handle any symbol at any time, we
1152 should never be spilling symbolic operands to the constant pool, ever. */
1155 alpha_cannot_force_const_mem (rtx x
)
1157 enum rtx_code code
= GET_CODE (x
);
1158 return code
== SYMBOL_REF
|| code
== LABEL_REF
|| code
== CONST
;
1161 /* We do not allow indirect calls to be optimized into sibling calls, nor
1162 can we allow a call to a function with a different GP to be optimized
1166 alpha_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
1168 /* Can't do indirect tail calls, since we don't know if the target
1169 uses the same GP. */
1173 /* Otherwise, we can make a tail call if the target function shares
1175 return decl_has_samegp (decl
);
1179 some_small_symbolic_operand_int (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1183 /* Don't re-split. */
1184 if (GET_CODE (x
) == LO_SUM
)
1187 return small_symbolic_operand (x
, Pmode
) != 0;
1191 split_small_symbolic_operand_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
1195 /* Don't re-split. */
1196 if (GET_CODE (x
) == LO_SUM
)
1199 if (small_symbolic_operand (x
, Pmode
))
1201 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1210 split_small_symbolic_operand (rtx x
)
1213 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
1217 /* Indicate that INSN cannot be duplicated. This is true for any insn
1218 that we've marked with gpdisp relocs, since those have to stay in
1219 1-1 correspondence with one another.
1221 Technically we could copy them if we could set up a mapping from one
1222 sequence number to another, across the set of insns to be duplicated.
1223 This seems overly complicated and error-prone since interblock motion
1224 from sched-ebb could move one of the pair of insns to a different block.
1226 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1227 then they'll be in a different block from their ldgp. Which could lead
1228 the bb reorder code to think that it would be ok to copy just the block
1229 containing the call and branch to the block containing the ldgp. */
1232 alpha_cannot_copy_insn_p (rtx insn
)
1234 if (!reload_completed
|| !TARGET_EXPLICIT_RELOCS
)
1236 if (recog_memoized (insn
) >= 0)
1237 return get_attr_cannot_copy (insn
);
1243 /* Try a machine-dependent way of reloading an illegitimate address
1244 operand. If we find one, push the reload and return the new rtx. */
1247 alpha_legitimize_reload_address (rtx x
,
1248 enum machine_mode mode ATTRIBUTE_UNUSED
,
1249 int opnum
, int type
,
1250 int ind_levels ATTRIBUTE_UNUSED
)
1252 /* We must recognize output that we have already generated ourselves. */
1253 if (GET_CODE (x
) == PLUS
1254 && GET_CODE (XEXP (x
, 0)) == PLUS
1255 && REG_P (XEXP (XEXP (x
, 0), 0))
1256 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
1257 && CONST_INT_P (XEXP (x
, 1)))
1259 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1260 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1261 opnum
, (enum reload_type
) type
);
1265 /* We wish to handle large displacements off a base register by
1266 splitting the addend across an ldah and the mem insn. This
1267 cuts number of extra insns needed from 3 to 1. */
1268 if (GET_CODE (x
) == PLUS
1269 && REG_P (XEXP (x
, 0))
1270 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1271 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1272 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1274 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1275 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1277 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1279 /* Check for 32-bit overflow. */
1280 if (high
+ low
!= val
)
1283 /* Reload the high part into a base reg; leave the low part
1284 in the mem directly. */
1285 x
= gen_rtx_PLUS (GET_MODE (x
),
1286 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1290 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1291 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1292 opnum
, (enum reload_type
) type
);
1299 /* Compute a (partial) cost for rtx X. Return true if the complete
1300 cost has been computed, and false if subexpressions should be
1301 scanned. In either case, *TOTAL contains the cost result. */
1304 alpha_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
1307 enum machine_mode mode
= GET_MODE (x
);
1308 bool float_mode_p
= FLOAT_MODE_P (mode
);
1309 const struct alpha_rtx_cost_data
*cost_data
;
1312 cost_data
= &alpha_rtx_cost_size
;
1314 cost_data
= &alpha_rtx_cost_data
[alpha_tune
];
1319 /* If this is an 8-bit constant, return zero since it can be used
1320 nearly anywhere with no cost. If it is a valid operand for an
1321 ADD or AND, likewise return 0 if we know it will be used in that
1322 context. Otherwise, return 2 since it might be used there later.
1323 All other constants take at least two insns. */
1324 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
1332 if (x
== CONST0_RTX (mode
))
1334 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
1335 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
1337 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
1340 *total
= COSTS_N_INSNS (2);
1346 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
1347 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
1348 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
1349 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
1350 else if (tls_symbolic_operand_type (x
))
1351 /* Estimate of cost for call_pal rduniq. */
1352 /* ??? How many insns do we emit here? More than one... */
1353 *total
= COSTS_N_INSNS (15);
1355 /* Otherwise we do a load from the GOT. */
1356 *total
= COSTS_N_INSNS (!speed
? 1 : alpha_memory_latency
);
1360 /* This is effectively an add_operand. */
1367 *total
= cost_data
->fp_add
;
1368 else if (GET_CODE (XEXP (x
, 0)) == MULT
1369 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
1371 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0),
1372 (enum rtx_code
) outer_code
, speed
)
1373 + rtx_cost (XEXP (x
, 1),
1374 (enum rtx_code
) outer_code
, speed
)
1375 + COSTS_N_INSNS (1));
1382 *total
= cost_data
->fp_mult
;
1383 else if (mode
== DImode
)
1384 *total
= cost_data
->int_mult_di
;
1386 *total
= cost_data
->int_mult_si
;
1390 if (CONST_INT_P (XEXP (x
, 1))
1391 && INTVAL (XEXP (x
, 1)) <= 3)
1393 *total
= COSTS_N_INSNS (1);
1400 *total
= cost_data
->int_shift
;
1405 *total
= cost_data
->fp_add
;
1407 *total
= cost_data
->int_cmov
;
1415 *total
= cost_data
->int_div
;
1416 else if (mode
== SFmode
)
1417 *total
= cost_data
->fp_div_sf
;
1419 *total
= cost_data
->fp_div_df
;
1423 *total
= COSTS_N_INSNS (!speed
? 1 : alpha_memory_latency
);
1429 *total
= COSTS_N_INSNS (1);
1437 *total
= COSTS_N_INSNS (1) + cost_data
->int_cmov
;
1443 case UNSIGNED_FLOAT
:
1446 case FLOAT_TRUNCATE
:
1447 *total
= cost_data
->fp_add
;
1451 if (MEM_P (XEXP (x
, 0)))
1454 *total
= cost_data
->fp_add
;
1462 /* REF is an alignable memory location. Place an aligned SImode
1463 reference into *PALIGNED_MEM and the number of bits to shift into
1464 *PBITNUM. SCRATCH is a free register for use in reloading out
1465 of range stack slots. */
1468 get_aligned_mem (rtx ref
, rtx
*paligned_mem
, rtx
*pbitnum
)
1471 HOST_WIDE_INT disp
, offset
;
1473 gcc_assert (MEM_P (ref
));
1475 if (reload_in_progress
1476 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1478 base
= find_replacement (&XEXP (ref
, 0));
1479 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1482 base
= XEXP (ref
, 0);
1484 if (GET_CODE (base
) == PLUS
)
1485 disp
= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1489 /* Find the byte offset within an aligned word. If the memory itself is
1490 claimed to be aligned, believe it. Otherwise, aligned_memory_operand
1491 will have examined the base register and determined it is aligned, and
1492 thus displacements from it are naturally alignable. */
1493 if (MEM_ALIGN (ref
) >= 32)
1498 /* The location should not cross aligned word boundary. */
1499 gcc_assert (offset
+ GET_MODE_SIZE (GET_MODE (ref
))
1500 <= GET_MODE_SIZE (SImode
));
1502 /* Access the entire aligned word. */
1503 *paligned_mem
= widen_memory_access (ref
, SImode
, -offset
);
1505 /* Convert the byte offset within the word to a bit offset. */
1506 if (WORDS_BIG_ENDIAN
)
1507 offset
= 32 - (GET_MODE_BITSIZE (GET_MODE (ref
)) + offset
* 8);
1510 *pbitnum
= GEN_INT (offset
);
1513 /* Similar, but just get the address. Handle the two reload cases.
1514 Add EXTRA_OFFSET to the address we return. */
1517 get_unaligned_address (rtx ref
)
1520 HOST_WIDE_INT offset
= 0;
1522 gcc_assert (MEM_P (ref
));
1524 if (reload_in_progress
1525 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
1527 base
= find_replacement (&XEXP (ref
, 0));
1529 gcc_assert (memory_address_p (GET_MODE (ref
), base
));
1532 base
= XEXP (ref
, 0);
1534 if (GET_CODE (base
) == PLUS
)
1535 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
1537 return plus_constant (base
, offset
);
1540 /* Compute a value X, such that X & 7 == (ADDR + OFS) & 7.
1541 X is always returned in a register. */
1544 get_unaligned_offset (rtx addr
, HOST_WIDE_INT ofs
)
1546 if (GET_CODE (addr
) == PLUS
)
1548 ofs
+= INTVAL (XEXP (addr
, 1));
1549 addr
= XEXP (addr
, 0);
1552 return expand_simple_binop (Pmode
, PLUS
, addr
, GEN_INT (ofs
& 7),
1553 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1556 /* On the Alpha, all (non-symbolic) constants except zero go into
1557 a floating-point register via memory. Note that we cannot
1558 return anything that is not a subset of RCLASS, and that some
1559 symbolic constants cannot be dropped to memory. */
1562 alpha_preferred_reload_class(rtx x
, enum reg_class rclass
)
1564 /* Zero is present in any register class. */
1565 if (x
== CONST0_RTX (GET_MODE (x
)))
1568 /* These sorts of constants we can easily drop to memory. */
1570 || GET_CODE (x
) == CONST_DOUBLE
1571 || GET_CODE (x
) == CONST_VECTOR
)
1573 if (rclass
== FLOAT_REGS
)
1575 if (rclass
== ALL_REGS
)
1576 return GENERAL_REGS
;
1580 /* All other kinds of constants should not (and in the case of HIGH
1581 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1582 secondary reload. */
1584 return (rclass
== ALL_REGS
? GENERAL_REGS
: rclass
);
1589 /* Inform reload about cases where moving X with a mode MODE to a register in
1590 RCLASS requires an extra scratch or immediate register. Return the class
1591 needed for the immediate register. */
1594 alpha_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
1595 enum machine_mode mode
, secondary_reload_info
*sri
)
1597 enum reg_class rclass
= (enum reg_class
) rclass_i
;
1599 /* Loading and storing HImode or QImode values to and from memory
1600 usually requires a scratch register. */
1601 if (!TARGET_BWX
&& (mode
== QImode
|| mode
== HImode
|| mode
== CQImode
))
1603 if (any_memory_operand (x
, mode
))
1607 if (!aligned_memory_operand (x
, mode
))
1608 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
1611 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
1616 /* We also cannot do integral arithmetic into FP regs, as might result
1617 from register elimination into a DImode fp register. */
1618 if (rclass
== FLOAT_REGS
)
1620 if (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == AND
)
1621 return GENERAL_REGS
;
1622 if (in_p
&& INTEGRAL_MODE_P (mode
)
1623 && !MEM_P (x
) && !REG_P (x
) && !CONST_INT_P (x
))
1624 return GENERAL_REGS
;
1630 /* Subfunction of the following function. Update the flags of any MEM
1631 found in part of X. */
1634 alpha_set_memflags_1 (rtx
*xp
, void *data
)
1636 rtx x
= *xp
, orig
= (rtx
) data
;
1641 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (orig
);
1642 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (orig
);
1643 MEM_SCALAR_P (x
) = MEM_SCALAR_P (orig
);
1644 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (orig
);
1645 MEM_READONLY_P (x
) = MEM_READONLY_P (orig
);
1647 /* Sadly, we cannot use alias sets because the extra aliasing
1648 produced by the AND interferes. Given that two-byte quantities
1649 are the only thing we would be able to differentiate anyway,
1650 there does not seem to be any point in convoluting the early
1651 out of the alias check. */
1656 /* Given SEQ, which is an INSN list, look for any MEMs in either
1657 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1658 volatile flags from REF into each of the MEMs found. If REF is not
1659 a MEM, don't do anything. */
1662 alpha_set_memflags (rtx seq
, rtx ref
)
1669 /* This is only called from alpha.md, after having had something
1670 generated from one of the insn patterns. So if everything is
1671 zero, the pattern is already up-to-date. */
1672 if (!MEM_VOLATILE_P (ref
)
1673 && !MEM_IN_STRUCT_P (ref
)
1674 && !MEM_SCALAR_P (ref
)
1675 && !MEM_NOTRAP_P (ref
)
1676 && !MEM_READONLY_P (ref
))
1679 for (insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
1681 for_each_rtx (&PATTERN (insn
), alpha_set_memflags_1
, (void *) ref
);
1686 static rtx
alpha_emit_set_const (rtx
, enum machine_mode
, HOST_WIDE_INT
,
1689 /* Internal routine for alpha_emit_set_const to check for N or below insns.
1690 If NO_OUTPUT is true, then we only check to see if N insns are possible,
1691 and return pc_rtx if successful. */
1694 alpha_emit_set_const_1 (rtx target
, enum machine_mode mode
,
1695 HOST_WIDE_INT c
, int n
, bool no_output
)
1697 HOST_WIDE_INT new_const
;
1699 /* Use a pseudo if highly optimizing and still generating RTL. */
1701 = (flag_expensive_optimizations
&& can_create_pseudo_p () ? 0 : target
);
1704 /* If this is a sign-extended 32-bit constant, we can do this in at most
1705 three insns, so do it if we have enough insns left. We always have
1706 a sign-extended 32-bit constant when compiling on a narrow machine. */
1708 if (HOST_BITS_PER_WIDE_INT
!= 64
1709 || c
>> 31 == -1 || c
>> 31 == 0)
1711 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1712 HOST_WIDE_INT tmp1
= c
- low
;
1713 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
1714 HOST_WIDE_INT extra
= 0;
1716 /* If HIGH will be interpreted as negative but the constant is
1717 positive, we must adjust it to do two ldha insns. */
1719 if ((high
& 0x8000) != 0 && c
>= 0)
1723 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
1726 if (c
== low
|| (low
== 0 && extra
== 0))
1728 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1729 but that meant that we can't handle INT_MIN on 32-bit machines
1730 (like NT/Alpha), because we recurse indefinitely through
1731 emit_move_insn to gen_movdi. So instead, since we know exactly
1732 what we want, create it explicitly. */
1737 target
= gen_reg_rtx (mode
);
1738 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
1741 else if (n
>= 2 + (extra
!= 0))
1745 if (!can_create_pseudo_p ())
1747 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (high
<< 16)));
1751 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16),
1754 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1755 This means that if we go through expand_binop, we'll try to
1756 generate extensions, etc, which will require new pseudos, which
1757 will fail during some split phases. The SImode add patterns
1758 still exist, but are not named. So build the insns by hand. */
1763 subtarget
= gen_reg_rtx (mode
);
1764 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
1765 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
1771 target
= gen_reg_rtx (mode
);
1772 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
1773 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
1779 /* If we couldn't do it that way, try some other methods. But if we have
1780 no instructions left, don't bother. Likewise, if this is SImode and
1781 we can't make pseudos, we can't do anything since the expand_binop
1782 and expand_unop calls will widen and try to make pseudos. */
1784 if (n
== 1 || (mode
== SImode
&& !can_create_pseudo_p ()))
1787 /* Next, see if we can load a related constant and then shift and possibly
1788 negate it to get the constant we want. Try this once each increasing
1789 numbers of insns. */
1791 for (i
= 1; i
< n
; i
++)
1793 /* First, see if minus some low bits, we've an easy load of
1796 new_const
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
1799 temp
= alpha_emit_set_const (subtarget
, mode
, c
- new_const
, i
, no_output
);
1804 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new_const
),
1805 target
, 0, OPTAB_WIDEN
);
1809 /* Next try complementing. */
1810 temp
= alpha_emit_set_const (subtarget
, mode
, ~c
, i
, no_output
);
1815 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
1818 /* Next try to form a constant and do a left shift. We can do this
1819 if some low-order bits are zero; the exact_log2 call below tells
1820 us that information. The bits we are shifting out could be any
1821 value, but here we'll just try the 0- and sign-extended forms of
1822 the constant. To try to increase the chance of having the same
1823 constant in more than one insn, start at the highest number of
1824 bits to shift, but try all possibilities in case a ZAPNOT will
1827 bits
= exact_log2 (c
& -c
);
1829 for (; bits
> 0; bits
--)
1831 new_const
= c
>> bits
;
1832 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, i
, no_output
);
1835 new_const
= (unsigned HOST_WIDE_INT
)c
>> bits
;
1836 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
,
1843 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
1844 target
, 0, OPTAB_WIDEN
);
1848 /* Now try high-order zero bits. Here we try the shifted-in bits as
1849 all zero and all ones. Be careful to avoid shifting outside the
1850 mode and to avoid shifting outside the host wide int size. */
1851 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1852 confuse the recursive call and set all of the high 32 bits. */
1854 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1855 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64));
1857 for (; bits
> 0; bits
--)
1859 new_const
= c
<< bits
;
1860 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, i
, no_output
);
1863 new_const
= (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1864 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
,
1871 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
1872 target
, 1, OPTAB_WIDEN
);
1876 /* Now try high-order 1 bits. We get that with a sign-extension.
1877 But one bit isn't enough here. Be careful to avoid shifting outside
1878 the mode and to avoid shifting outside the host wide int size. */
1880 bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
1881 - floor_log2 (~ c
) - 2);
1883 for (; bits
> 0; bits
--)
1885 new_const
= c
<< bits
;
1886 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, i
, no_output
);
1889 new_const
= (c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1);
1890 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
,
1897 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
1898 target
, 0, OPTAB_WIDEN
);
1903 #if HOST_BITS_PER_WIDE_INT == 64
1904 /* Finally, see if can load a value into the target that is the same as the
1905 constant except that all bytes that are 0 are changed to be 0xff. If we
1906 can, then we can do a ZAPNOT to obtain the desired constant. */
1909 for (i
= 0; i
< 64; i
+= 8)
1910 if ((new_const
& ((HOST_WIDE_INT
) 0xff << i
)) == 0)
1911 new_const
|= (HOST_WIDE_INT
) 0xff << i
;
1913 /* We are only called for SImode and DImode. If this is SImode, ensure that
1914 we are sign extended to a full word. */
1917 new_const
= ((new_const
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1921 temp
= alpha_emit_set_const (subtarget
, mode
, new_const
, n
- 1, no_output
);
1926 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new_const
),
1927 target
, 0, OPTAB_WIDEN
);
1935 /* Try to output insns to set TARGET equal to the constant C if it can be
1936 done in less than N insns. Do all computations in MODE. Returns the place
1937 where the output has been placed if it can be done and the insns have been
1938 emitted. If it would take more than N insns, zero is returned and no
1939 insns and emitted. */
1942 alpha_emit_set_const (rtx target
, enum machine_mode mode
,
1943 HOST_WIDE_INT c
, int n
, bool no_output
)
1945 enum machine_mode orig_mode
= mode
;
1946 rtx orig_target
= target
;
1950 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1951 can't load this constant in one insn, do this in DImode. */
1952 if (!can_create_pseudo_p () && mode
== SImode
1953 && REG_P (target
) && REGNO (target
) < FIRST_PSEUDO_REGISTER
)
1955 result
= alpha_emit_set_const_1 (target
, mode
, c
, 1, no_output
);
1959 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1962 else if (mode
== V8QImode
|| mode
== V4HImode
|| mode
== V2SImode
)
1964 target
= no_output
? NULL
: gen_lowpart (DImode
, target
);
1968 /* Try 1 insn, then 2, then up to N. */
1969 for (i
= 1; i
<= n
; i
++)
1971 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
, no_output
);
1979 insn
= get_last_insn ();
1980 set
= single_set (insn
);
1981 if (! CONSTANT_P (SET_SRC (set
)))
1982 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
1987 /* Allow for the case where we changed the mode of TARGET. */
1990 if (result
== target
)
1991 result
= orig_target
;
1992 else if (mode
!= orig_mode
)
1993 result
= gen_lowpart (orig_mode
, result
);
1999 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2000 fall back to a straight forward decomposition. We do this to avoid
2001 exponential run times encountered when looking for longer sequences
2002 with alpha_emit_set_const. */
2005 alpha_emit_set_long_const (rtx target
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
2007 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2009 /* Decompose the entire word */
2010 #if HOST_BITS_PER_WIDE_INT >= 64
2011 gcc_assert (c2
== -(c1
< 0));
2012 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2014 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2015 c1
= (c1
- d2
) >> 32;
2016 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2018 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2019 gcc_assert (c1
== d4
);
2021 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2023 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2024 gcc_assert (c1
== d2
);
2026 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2028 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2029 gcc_assert (c2
== d4
);
2032 /* Construct the high word */
2035 emit_move_insn (target
, GEN_INT (d4
));
2037 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2040 emit_move_insn (target
, GEN_INT (d3
));
2042 /* Shift it into place */
2043 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2045 /* Add in the low bits. */
2047 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2049 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2054 /* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
2058 alpha_extract_integer (rtx x
, HOST_WIDE_INT
*p0
, HOST_WIDE_INT
*p1
)
2060 HOST_WIDE_INT i0
, i1
;
2062 if (GET_CODE (x
) == CONST_VECTOR
)
2063 x
= simplify_subreg (DImode
, x
, GET_MODE (x
), 0);
2066 if (CONST_INT_P (x
))
2071 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2073 i0
= CONST_DOUBLE_LOW (x
);
2078 i0
= CONST_DOUBLE_LOW (x
);
2079 i1
= CONST_DOUBLE_HIGH (x
);
2086 /* Implement LEGITIMATE_CONSTANT_P. This is all constants for which we
2087 are willing to load the value into a register via a move pattern.
2088 Normally this is all symbolic constants, integral constants that
2089 take three or fewer instructions, and floating-point zero. */
2092 alpha_legitimate_constant_p (rtx x
)
2094 enum machine_mode mode
= GET_MODE (x
);
2095 HOST_WIDE_INT i0
, i1
;
2097 switch (GET_CODE (x
))
2104 if (GET_CODE (XEXP (x
, 0)) == PLUS
2105 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2106 x
= XEXP (XEXP (x
, 0), 0);
2110 if (GET_CODE (x
) != SYMBOL_REF
)
2116 /* TLS symbols are never valid. */
2117 return SYMBOL_REF_TLS_MODEL (x
) == 0;
2120 if (x
== CONST0_RTX (mode
))
2122 if (FLOAT_MODE_P (mode
))
2127 if (x
== CONST0_RTX (mode
))
2129 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
2131 if (GET_MODE_SIZE (mode
) != 8)
2137 if (TARGET_BUILD_CONSTANTS
)
2139 alpha_extract_integer (x
, &i0
, &i1
);
2140 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== (-i0
< 0))
2141 return alpha_emit_set_const_1 (x
, mode
, i0
, 3, true) != NULL
;
2149 /* Operand 1 is known to be a constant, and should require more than one
2150 instruction to load. Emit that multi-part load. */
2153 alpha_split_const_mov (enum machine_mode mode
, rtx
*operands
)
2155 HOST_WIDE_INT i0
, i1
;
2156 rtx temp
= NULL_RTX
;
2158 alpha_extract_integer (operands
[1], &i0
, &i1
);
2160 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2161 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3, false);
2163 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2164 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2168 if (!rtx_equal_p (operands
[0], temp
))
2169 emit_move_insn (operands
[0], temp
);
2176 /* Expand a move instruction; return true if all work is done.
2177 We don't handle non-bwx subword loads here. */
2180 alpha_expand_mov (enum machine_mode mode
, rtx
*operands
)
2184 /* If the output is not a register, the input must be. */
2185 if (MEM_P (operands
[0])
2186 && ! reg_or_0_operand (operands
[1], mode
))
2187 operands
[1] = force_reg (mode
, operands
[1]);
2189 /* Allow legitimize_address to perform some simplifications. */
2190 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2192 tmp
= alpha_legitimize_address_1 (operands
[1], operands
[0], mode
);
2195 if (tmp
== operands
[0])
2202 /* Early out for non-constants and valid constants. */
2203 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2206 /* Split large integers. */
2207 if (CONST_INT_P (operands
[1])
2208 || GET_CODE (operands
[1]) == CONST_DOUBLE
2209 || GET_CODE (operands
[1]) == CONST_VECTOR
)
2211 if (alpha_split_const_mov (mode
, operands
))
2215 /* Otherwise we've nothing left but to drop the thing to memory. */
2216 tmp
= force_const_mem (mode
, operands
[1]);
2218 if (tmp
== NULL_RTX
)
2221 if (reload_in_progress
)
2223 emit_move_insn (operands
[0], XEXP (tmp
, 0));
2224 operands
[1] = replace_equiv_address (tmp
, operands
[0]);
2227 operands
[1] = validize_mem (tmp
);
2231 /* Expand a non-bwx QImode or HImode move instruction;
2232 return true if all work is done. */
2235 alpha_expand_mov_nobwx (enum machine_mode mode
, rtx
*operands
)
2239 /* If the output is not a register, the input must be. */
2240 if (MEM_P (operands
[0]))
2241 operands
[1] = force_reg (mode
, operands
[1]);
2243 /* Handle four memory cases, unaligned and aligned for either the input
2244 or the output. The only case where we can be called during reload is
2245 for aligned loads; all other cases require temporaries. */
2247 if (any_memory_operand (operands
[1], mode
))
2249 if (aligned_memory_operand (operands
[1], mode
))
2251 if (reload_in_progress
)
2254 seq
= gen_reload_inqi_aligned (operands
[0], operands
[1]);
2256 seq
= gen_reload_inhi_aligned (operands
[0], operands
[1]);
2261 rtx aligned_mem
, bitnum
;
2262 rtx scratch
= gen_reg_rtx (SImode
);
2266 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2268 subtarget
= operands
[0];
2269 if (REG_P (subtarget
))
2270 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2272 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2275 seq
= gen_aligned_loadqi (subtarget
, aligned_mem
,
2278 seq
= gen_aligned_loadhi (subtarget
, aligned_mem
,
2283 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2288 /* Don't pass these as parameters since that makes the generated
2289 code depend on parameter evaluation order which will cause
2290 bootstrap failures. */
2292 rtx temp1
, temp2
, subtarget
, ua
;
2295 temp1
= gen_reg_rtx (DImode
);
2296 temp2
= gen_reg_rtx (DImode
);
2298 subtarget
= operands
[0];
2299 if (REG_P (subtarget
))
2300 subtarget
= gen_lowpart (DImode
, subtarget
), copyout
= false;
2302 subtarget
= gen_reg_rtx (DImode
), copyout
= true;
2304 ua
= get_unaligned_address (operands
[1]);
2306 seq
= gen_unaligned_loadqi (subtarget
, ua
, temp1
, temp2
);
2308 seq
= gen_unaligned_loadhi (subtarget
, ua
, temp1
, temp2
);
2310 alpha_set_memflags (seq
, operands
[1]);
2314 emit_move_insn (operands
[0], gen_lowpart (mode
, subtarget
));
2319 if (any_memory_operand (operands
[0], mode
))
2321 if (aligned_memory_operand (operands
[0], mode
))
2323 rtx aligned_mem
, bitnum
;
2324 rtx temp1
= gen_reg_rtx (SImode
);
2325 rtx temp2
= gen_reg_rtx (SImode
);
2327 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2329 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2334 rtx temp1
= gen_reg_rtx (DImode
);
2335 rtx temp2
= gen_reg_rtx (DImode
);
2336 rtx temp3
= gen_reg_rtx (DImode
);
2337 rtx ua
= get_unaligned_address (operands
[0]);
2340 seq
= gen_unaligned_storeqi (ua
, operands
[1], temp1
, temp2
, temp3
);
2342 seq
= gen_unaligned_storehi (ua
, operands
[1], temp1
, temp2
, temp3
);
2344 alpha_set_memflags (seq
, operands
[0]);
2353 /* Implement the movmisalign patterns. One of the operands is a memory
2354 that is not naturally aligned. Emit instructions to load it. */
2357 alpha_expand_movmisalign (enum machine_mode mode
, rtx
*operands
)
2359 /* Honor misaligned loads, for those we promised to do so. */
2360 if (MEM_P (operands
[1]))
2364 if (register_operand (operands
[0], mode
))
2367 tmp
= gen_reg_rtx (mode
);
2369 alpha_expand_unaligned_load (tmp
, operands
[1], 8, 0, 0);
2370 if (tmp
!= operands
[0])
2371 emit_move_insn (operands
[0], tmp
);
2373 else if (MEM_P (operands
[0]))
2375 if (!reg_or_0_operand (operands
[1], mode
))
2376 operands
[1] = force_reg (mode
, operands
[1]);
2377 alpha_expand_unaligned_store (operands
[0], operands
[1], 8, 0);
2383 /* Generate an unsigned DImode to FP conversion. This is the same code
2384 optabs would emit if we didn't have TFmode patterns.
2386 For SFmode, this is the only construction I've found that can pass
2387 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2388 intermediates will work, because you'll get intermediate rounding
2389 that ruins the end result. Some of this could be fixed by turning
2390 on round-to-positive-infinity, but that requires diddling the fpsr,
2391 which kills performance. I tried turning this around and converting
2392 to a negative number, so that I could turn on /m, but either I did
2393 it wrong or there's something else cause I wound up with the exact
2394 same single-bit error. There is a branch-less form of this same code:
2405 fcmoveq $f10,$f11,$f0
2407 I'm not using it because it's the same number of instructions as
2408 this branch-full form, and it has more serialized long latency
2409 instructions on the critical path.
2411 For DFmode, we can avoid rounding errors by breaking up the word
2412 into two pieces, converting them separately, and adding them back:
2414 LC0: .long 0,0x5f800000
2419 cpyse $f11,$f31,$f10
2420 cpyse $f31,$f11,$f11
2428 This doesn't seem to be a clear-cut win over the optabs form.
2429 It probably all depends on the distribution of numbers being
2430 converted -- in the optabs form, all but high-bit-set has a
2431 much lower minimum execution time. */
2434 alpha_emit_floatuns (rtx operands
[2])
2436 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2437 enum machine_mode mode
;
2440 in
= force_reg (DImode
, operands
[1]);
2441 mode
= GET_MODE (out
);
2442 neglab
= gen_label_rtx ();
2443 donelab
= gen_label_rtx ();
2444 i0
= gen_reg_rtx (DImode
);
2445 i1
= gen_reg_rtx (DImode
);
2446 f0
= gen_reg_rtx (mode
);
2448 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2450 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2451 emit_jump_insn (gen_jump (donelab
));
2454 emit_label (neglab
);
2456 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2457 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2458 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2459 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2460 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2462 emit_label (donelab
);
2465 /* Generate the comparison for a conditional branch. */
2468 alpha_emit_conditional_branch (rtx operands
[], enum machine_mode cmp_mode
)
2470 enum rtx_code cmp_code
, branch_code
;
2471 enum machine_mode branch_mode
= VOIDmode
;
2472 enum rtx_code code
= GET_CODE (operands
[0]);
2473 rtx op0
= operands
[1], op1
= operands
[2];
2476 if (cmp_mode
== TFmode
)
2478 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2483 /* The general case: fold the comparison code to the types of compares
2484 that we have, choosing the branch as necessary. */
2487 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2489 /* We have these compares: */
2490 cmp_code
= code
, branch_code
= NE
;
2495 /* These must be reversed. */
2496 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2499 case GE
: case GT
: case GEU
: case GTU
:
2500 /* For FP, we swap them, for INT, we reverse them. */
2501 if (cmp_mode
== DFmode
)
2503 cmp_code
= swap_condition (code
);
2505 tem
= op0
, op0
= op1
, op1
= tem
;
2509 cmp_code
= reverse_condition (code
);
2518 if (cmp_mode
== DFmode
)
2520 if (flag_unsafe_math_optimizations
&& cmp_code
!= UNORDERED
)
2522 /* When we are not as concerned about non-finite values, and we
2523 are comparing against zero, we can branch directly. */
2524 if (op1
== CONST0_RTX (DFmode
))
2525 cmp_code
= UNKNOWN
, branch_code
= code
;
2526 else if (op0
== CONST0_RTX (DFmode
))
2528 /* Undo the swap we probably did just above. */
2529 tem
= op0
, op0
= op1
, op1
= tem
;
2530 branch_code
= swap_condition (cmp_code
);
2536 /* ??? We mark the branch mode to be CCmode to prevent the
2537 compare and branch from being combined, since the compare
2538 insn follows IEEE rules that the branch does not. */
2539 branch_mode
= CCmode
;
2544 /* The following optimizations are only for signed compares. */
2545 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2547 /* Whee. Compare and branch against 0 directly. */
2548 if (op1
== const0_rtx
)
2549 cmp_code
= UNKNOWN
, branch_code
= code
;
2551 /* If the constants doesn't fit into an immediate, but can
2552 be generated by lda/ldah, we adjust the argument and
2553 compare against zero, so we can use beq/bne directly. */
2554 /* ??? Don't do this when comparing against symbols, otherwise
2555 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2556 be declared false out of hand (at least for non-weak). */
2557 else if (CONST_INT_P (op1
)
2558 && (code
== EQ
|| code
== NE
)
2559 && !(symbolic_operand (op0
, VOIDmode
)
2560 || (REG_P (op0
) && REG_POINTER (op0
))))
2562 rtx n_op1
= GEN_INT (-INTVAL (op1
));
2564 if (! satisfies_constraint_I (op1
)
2565 && (satisfies_constraint_K (n_op1
)
2566 || satisfies_constraint_L (n_op1
)))
2567 cmp_code
= PLUS
, branch_code
= code
, op1
= n_op1
;
2571 if (!reg_or_0_operand (op0
, DImode
))
2572 op0
= force_reg (DImode
, op0
);
2573 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2574 op1
= force_reg (DImode
, op1
);
2577 /* Emit an initial compare instruction, if necessary. */
2579 if (cmp_code
!= UNKNOWN
)
2581 tem
= gen_reg_rtx (cmp_mode
);
2582 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2585 /* Emit the branch instruction. */
2586 tem
= gen_rtx_SET (VOIDmode
, pc_rtx
,
2587 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2588 gen_rtx_fmt_ee (branch_code
,
2590 CONST0_RTX (cmp_mode
)),
2591 gen_rtx_LABEL_REF (VOIDmode
,
2594 emit_jump_insn (tem
);
2597 /* Certain simplifications can be done to make invalid setcc operations
2598 valid. Return the final comparison, or NULL if we can't work. */
2601 alpha_emit_setcc (rtx operands
[], enum machine_mode cmp_mode
)
2603 enum rtx_code cmp_code
;
2604 enum rtx_code code
= GET_CODE (operands
[1]);
2605 rtx op0
= operands
[2], op1
= operands
[3];
2608 if (cmp_mode
== TFmode
)
2610 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2615 if (cmp_mode
== DFmode
&& !TARGET_FIX
)
2618 /* The general case: fold the comparison code to the types of compares
2619 that we have, choosing the branch as necessary. */
2624 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2626 /* We have these compares. */
2627 if (cmp_mode
== DFmode
)
2628 cmp_code
= code
, code
= NE
;
2632 if (cmp_mode
== DImode
&& op1
== const0_rtx
)
2637 cmp_code
= reverse_condition (code
);
2641 case GE
: case GT
: case GEU
: case GTU
:
2642 /* These normally need swapping, but for integer zero we have
2643 special patterns that recognize swapped operands. */
2644 if (cmp_mode
== DImode
&& op1
== const0_rtx
)
2646 code
= swap_condition (code
);
2647 if (cmp_mode
== DFmode
)
2648 cmp_code
= code
, code
= NE
;
2649 tmp
= op0
, op0
= op1
, op1
= tmp
;
2656 if (cmp_mode
== DImode
)
2658 if (!register_operand (op0
, DImode
))
2659 op0
= force_reg (DImode
, op0
);
2660 if (!reg_or_8bit_operand (op1
, DImode
))
2661 op1
= force_reg (DImode
, op1
);
2664 /* Emit an initial compare instruction, if necessary. */
2665 if (cmp_code
!= UNKNOWN
)
2667 tmp
= gen_reg_rtx (cmp_mode
);
2668 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
2669 gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
)));
2671 op0
= cmp_mode
!= DImode
? gen_lowpart (DImode
, tmp
) : tmp
;
2675 /* Emit the setcc instruction. */
2676 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2677 gen_rtx_fmt_ee (code
, DImode
, op0
, op1
)));
2682 /* Rewrite a comparison against zero CMP of the form
2683 (CODE (cc0) (const_int 0)) so it can be written validly in
2684 a conditional move (if_then_else CMP ...).
2685 If both of the operands that set cc0 are nonzero we must emit
2686 an insn to perform the compare (it can't be done within
2687 the conditional move). */
2690 alpha_emit_conditional_move (rtx cmp
, enum machine_mode mode
)
2692 enum rtx_code code
= GET_CODE (cmp
);
2693 enum rtx_code cmov_code
= NE
;
2694 rtx op0
= XEXP (cmp
, 0);
2695 rtx op1
= XEXP (cmp
, 1);
2696 enum machine_mode cmp_mode
2697 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
2698 enum machine_mode cmov_mode
= VOIDmode
;
2699 int local_fast_math
= flag_unsafe_math_optimizations
;
2702 if (cmp_mode
== TFmode
)
2704 op0
= alpha_emit_xfloating_compare (&code
, op0
, op1
);
2709 gcc_assert (cmp_mode
== DFmode
|| cmp_mode
== DImode
);
2711 if (FLOAT_MODE_P (cmp_mode
) != FLOAT_MODE_P (mode
))
2713 enum rtx_code cmp_code
;
2718 /* If we have fp<->int register move instructions, do a cmov by
2719 performing the comparison in fp registers, and move the
2720 zero/nonzero value to integer registers, where we can then
2721 use a normal cmov, or vice-versa. */
2725 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2726 /* We have these compares. */
2727 cmp_code
= code
, code
= NE
;
2731 /* This must be reversed. */
2732 cmp_code
= EQ
, code
= EQ
;
2735 case GE
: case GT
: case GEU
: case GTU
:
2736 /* These normally need swapping, but for integer zero we have
2737 special patterns that recognize swapped operands. */
2738 if (cmp_mode
== DImode
&& op1
== const0_rtx
)
2739 cmp_code
= code
, code
= NE
;
2742 cmp_code
= swap_condition (code
);
2744 tem
= op0
, op0
= op1
, op1
= tem
;
2752 tem
= gen_reg_rtx (cmp_mode
);
2753 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
2754 gen_rtx_fmt_ee (cmp_code
, cmp_mode
,
2757 cmp_mode
= cmp_mode
== DImode
? DFmode
: DImode
;
2758 op0
= gen_lowpart (cmp_mode
, tem
);
2759 op1
= CONST0_RTX (cmp_mode
);
2760 local_fast_math
= 1;
2763 /* We may be able to use a conditional move directly.
2764 This avoids emitting spurious compares. */
2765 if (signed_comparison_operator (cmp
, VOIDmode
)
2766 && (cmp_mode
== DImode
|| local_fast_math
)
2767 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
2768 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
2770 /* We can't put the comparison inside the conditional move;
2771 emit a compare instruction and put that inside the
2772 conditional move. Make sure we emit only comparisons we have;
2773 swap or reverse as necessary. */
2775 if (!can_create_pseudo_p ())
2780 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2781 /* We have these compares: */
2785 /* This must be reversed. */
2786 code
= reverse_condition (code
);
2790 case GE
: case GT
: case GEU
: case GTU
:
2791 /* These must be swapped. */
2792 if (op1
!= CONST0_RTX (cmp_mode
))
2794 code
= swap_condition (code
);
2795 tem
= op0
, op0
= op1
, op1
= tem
;
2803 if (cmp_mode
== DImode
)
2805 if (!reg_or_0_operand (op0
, DImode
))
2806 op0
= force_reg (DImode
, op0
);
2807 if (!reg_or_8bit_operand (op1
, DImode
))
2808 op1
= force_reg (DImode
, op1
);
2811 /* ??? We mark the branch mode to be CCmode to prevent the compare
2812 and cmov from being combined, since the compare insn follows IEEE
2813 rules that the cmov does not. */
2814 if (cmp_mode
== DFmode
&& !local_fast_math
)
2817 tem
= gen_reg_rtx (cmp_mode
);
2818 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_mode
, op0
, op1
));
2819 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_mode
));
2822 /* Simplify a conditional move of two constants into a setcc with
2823 arithmetic. This is done with a splitter since combine would
2824 just undo the work if done during code generation. It also catches
2825 cases we wouldn't have before cse. */
2828 alpha_split_conditional_move (enum rtx_code code
, rtx dest
, rtx cond
,
2829 rtx t_rtx
, rtx f_rtx
)
2831 HOST_WIDE_INT t
, f
, diff
;
2832 enum machine_mode mode
;
2833 rtx target
, subtarget
, tmp
;
2835 mode
= GET_MODE (dest
);
2840 if (((code
== NE
|| code
== EQ
) && diff
< 0)
2841 || (code
== GE
|| code
== GT
))
2843 code
= reverse_condition (code
);
2844 diff
= t
, t
= f
, f
= diff
;
2848 subtarget
= target
= dest
;
2851 target
= gen_lowpart (DImode
, dest
);
2852 if (can_create_pseudo_p ())
2853 subtarget
= gen_reg_rtx (DImode
);
2857 /* Below, we must be careful to use copy_rtx on target and subtarget
2858 in intermediate insns, as they may be a subreg rtx, which may not
2861 if (f
== 0 && exact_log2 (diff
) > 0
2862 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2863 viable over a longer latency cmove. On EV5, the E0 slot is a
2864 scarce resource, and on EV4 shift has the same latency as a cmove. */
2865 && (diff
<= 8 || alpha_tune
== PROCESSOR_EV6
))
2867 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2868 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2870 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
2871 GEN_INT (exact_log2 (t
)));
2872 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2874 else if (f
== 0 && t
== -1)
2876 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2877 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2879 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
2881 else if (diff
== 1 || diff
== 4 || diff
== 8)
2885 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
2886 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
2889 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
2892 add_op
= GEN_INT (f
);
2893 if (sext_add_operand (add_op
, mode
))
2895 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
2897 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
2898 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
2910 /* Look up the function X_floating library function name for the
2913 struct GTY(()) xfloating_op
2915 const enum rtx_code code
;
2916 const char *const GTY((skip
)) osf_func
;
2917 const char *const GTY((skip
)) vms_func
;
2921 static GTY(()) struct xfloating_op xfloating_ops
[] =
2923 { PLUS
, "_OtsAddX", "OTS$ADD_X", 0 },
2924 { MINUS
, "_OtsSubX", "OTS$SUB_X", 0 },
2925 { MULT
, "_OtsMulX", "OTS$MUL_X", 0 },
2926 { DIV
, "_OtsDivX", "OTS$DIV_X", 0 },
2927 { EQ
, "_OtsEqlX", "OTS$EQL_X", 0 },
2928 { NE
, "_OtsNeqX", "OTS$NEQ_X", 0 },
2929 { LT
, "_OtsLssX", "OTS$LSS_X", 0 },
2930 { LE
, "_OtsLeqX", "OTS$LEQ_X", 0 },
2931 { GT
, "_OtsGtrX", "OTS$GTR_X", 0 },
2932 { GE
, "_OtsGeqX", "OTS$GEQ_X", 0 },
2933 { FIX
, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2934 { FLOAT
, "_OtsCvtQX", "OTS$CVTQX", 0 },
2935 { UNSIGNED_FLOAT
, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2936 { FLOAT_EXTEND
, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2937 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2940 static GTY(()) struct xfloating_op vax_cvt_ops
[] =
2942 { FLOAT_EXTEND
, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2943 { FLOAT_TRUNCATE
, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2947 alpha_lookup_xfloating_lib_func (enum rtx_code code
)
2949 struct xfloating_op
*ops
= xfloating_ops
;
2950 long n
= ARRAY_SIZE (xfloating_ops
);
2953 gcc_assert (TARGET_HAS_XFLOATING_LIBS
);
2955 /* How irritating. Nothing to key off for the main table. */
2956 if (TARGET_FLOAT_VAX
&& (code
== FLOAT_EXTEND
|| code
== FLOAT_TRUNCATE
))
2959 n
= ARRAY_SIZE (vax_cvt_ops
);
2962 for (i
= 0; i
< n
; ++i
, ++ops
)
2963 if (ops
->code
== code
)
2965 rtx func
= ops
->libcall
;
2968 func
= init_one_libfunc (TARGET_ABI_OPEN_VMS
2969 ? ops
->vms_func
: ops
->osf_func
);
2970 ops
->libcall
= func
;
2978 /* Most X_floating operations take the rounding mode as an argument.
2979 Compute that here. */
2982 alpha_compute_xfloating_mode_arg (enum rtx_code code
,
2983 enum alpha_fp_rounding_mode round
)
2989 case ALPHA_FPRM_NORM
:
2992 case ALPHA_FPRM_MINF
:
2995 case ALPHA_FPRM_CHOP
:
2998 case ALPHA_FPRM_DYN
:
3004 /* XXX For reference, round to +inf is mode = 3. */
3007 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3013 /* Emit an X_floating library function call.
3015 Note that these functions do not follow normal calling conventions:
3016 TFmode arguments are passed in two integer registers (as opposed to
3017 indirect); TFmode return values appear in R16+R17.
3019 FUNC is the function to call.
3020 TARGET is where the output belongs.
3021 OPERANDS are the inputs.
3022 NOPERANDS is the count of inputs.
3023 EQUIV is the expression equivalent for the function.
3027 alpha_emit_xfloating_libcall (rtx func
, rtx target
, rtx operands
[],
3028 int noperands
, rtx equiv
)
3030 rtx usage
= NULL_RTX
, tmp
, reg
;
3035 for (i
= 0; i
< noperands
; ++i
)
3037 switch (GET_MODE (operands
[i
]))
3040 reg
= gen_rtx_REG (TFmode
, regno
);
3045 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3050 gcc_assert (CONST_INT_P (operands
[i
]));
3053 reg
= gen_rtx_REG (DImode
, regno
);
3061 emit_move_insn (reg
, operands
[i
]);
3062 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3065 switch (GET_MODE (target
))
3068 reg
= gen_rtx_REG (TFmode
, 16);
3071 reg
= gen_rtx_REG (DFmode
, 32);
3074 reg
= gen_rtx_REG (DImode
, 0);
3080 tmp
= gen_rtx_MEM (QImode
, func
);
3081 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3082 const0_rtx
, const0_rtx
));
3083 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3084 RTL_CONST_CALL_P (tmp
) = 1;
3089 emit_libcall_block (tmp
, target
, reg
, equiv
);
3092 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3095 alpha_emit_xfloating_arith (enum rtx_code code
, rtx operands
[])
3099 rtx out_operands
[3];
3101 func
= alpha_lookup_xfloating_lib_func (code
);
3102 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3104 out_operands
[0] = operands
[1];
3105 out_operands
[1] = operands
[2];
3106 out_operands
[2] = GEN_INT (mode
);
3107 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3108 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3112 /* Emit an X_floating library function call for a comparison. */
3115 alpha_emit_xfloating_compare (enum rtx_code
*pcode
, rtx op0
, rtx op1
)
3117 enum rtx_code cmp_code
, res_code
;
3118 rtx func
, out
, operands
[2], note
;
3120 /* X_floating library comparison functions return
3124 Convert the compare against the raw return value. */
3152 func
= alpha_lookup_xfloating_lib_func (cmp_code
);
3156 out
= gen_reg_rtx (DImode
);
3158 /* What's actually returned is -1,0,1, not a proper boolean value,
3159 so use an EXPR_LIST as with a generic libcall instead of a
3160 comparison type expression. */
3161 note
= gen_rtx_EXPR_LIST (VOIDmode
, op1
, NULL_RTX
);
3162 note
= gen_rtx_EXPR_LIST (VOIDmode
, op0
, note
);
3163 note
= gen_rtx_EXPR_LIST (VOIDmode
, func
, note
);
3164 alpha_emit_xfloating_libcall (func
, out
, operands
, 2, note
);
3169 /* Emit an X_floating library function call for a conversion. */
3172 alpha_emit_xfloating_cvt (enum rtx_code orig_code
, rtx operands
[])
3174 int noperands
= 1, mode
;
3175 rtx out_operands
[2];
3177 enum rtx_code code
= orig_code
;
3179 if (code
== UNSIGNED_FIX
)
3182 func
= alpha_lookup_xfloating_lib_func (code
);
3184 out_operands
[0] = operands
[1];
3189 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3190 out_operands
[1] = GEN_INT (mode
);
3193 case FLOAT_TRUNCATE
:
3194 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3195 out_operands
[1] = GEN_INT (mode
);
3202 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3203 gen_rtx_fmt_e (orig_code
,
3204 GET_MODE (operands
[0]),
3208 /* Split a TImode or TFmode move from OP[1] to OP[0] into a pair of
3209 DImode moves from OP[2,3] to OP[0,1]. If FIXUP_OVERLAP is true,
3210 guarantee that the sequence
3213 is valid. Naturally, output operand ordering is little-endian.
3214 This is used by *movtf_internal and *movti_internal. */
3217 alpha_split_tmode_pair (rtx operands
[4], enum machine_mode mode
,
3220 switch (GET_CODE (operands
[1]))
3223 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3224 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3228 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3229 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3234 gcc_assert (operands
[1] == CONST0_RTX (mode
));
3235 operands
[2] = operands
[3] = const0_rtx
;
3242 switch (GET_CODE (operands
[0]))
3245 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3246 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3250 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3251 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3258 if (fixup_overlap
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
3261 tmp
= operands
[0], operands
[0] = operands
[1], operands
[1] = tmp
;
3262 tmp
= operands
[2], operands
[2] = operands
[3], operands
[3] = tmp
;
3266 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3267 op2 is a register containing the sign bit, operation is the
3268 logical operation to be performed. */
3271 alpha_split_tfmode_frobsign (rtx operands
[3], rtx (*operation
) (rtx
, rtx
, rtx
))
3273 rtx high_bit
= operands
[2];
3277 alpha_split_tmode_pair (operands
, TFmode
, false);
3279 /* Detect three flavors of operand overlap. */
3281 if (rtx_equal_p (operands
[0], operands
[2]))
3283 else if (rtx_equal_p (operands
[1], operands
[2]))
3285 if (rtx_equal_p (operands
[0], high_bit
))
3292 emit_move_insn (operands
[0], operands
[2]);
3294 /* ??? If the destination overlaps both source tf and high_bit, then
3295 assume source tf is dead in its entirety and use the other half
3296 for a scratch register. Otherwise "scratch" is just the proper
3297 destination register. */
3298 scratch
= operands
[move
< 2 ? 1 : 3];
3300 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3304 emit_move_insn (operands
[0], operands
[2]);
3306 emit_move_insn (operands
[1], scratch
);
3310 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3314 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3315 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3316 lda r3,X(r11) lda r3,X+2(r11)
3317 extwl r1,r3,r1 extql r1,r3,r1
3318 extwh r2,r3,r2 extqh r2,r3,r2
3319 or r1.r2.r1 or r1,r2,r1
3322 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3323 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3324 lda r3,X(r11) lda r3,X(r11)
3325 extll r1,r3,r1 extll r1,r3,r1
3326 extlh r2,r3,r2 extlh r2,r3,r2
3327 or r1.r2.r1 addl r1,r2,r1
3329 quad: ldq_u r1,X(r11)
3338 alpha_expand_unaligned_load (rtx tgt
, rtx mem
, HOST_WIDE_INT size
,
3339 HOST_WIDE_INT ofs
, int sign
)
3341 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3342 enum machine_mode mode
;
3344 if (TARGET_BWX
&& size
== 2)
3346 meml
= adjust_address (mem
, QImode
, ofs
);
3347 memh
= adjust_address (mem
, QImode
, ofs
+1);
3348 if (BYTES_BIG_ENDIAN
)
3349 tmp
= meml
, meml
= memh
, memh
= tmp
;
3350 extl
= gen_reg_rtx (DImode
);
3351 exth
= gen_reg_rtx (DImode
);
3352 emit_insn (gen_zero_extendqidi2 (extl
, meml
));
3353 emit_insn (gen_zero_extendqidi2 (exth
, memh
));
3354 exth
= expand_simple_binop (DImode
, ASHIFT
, exth
, GEN_INT (8),
3355 NULL
, 1, OPTAB_LIB_WIDEN
);
3356 addr
= expand_simple_binop (DImode
, IOR
, extl
, exth
,
3357 NULL
, 1, OPTAB_LIB_WIDEN
);
3359 if (sign
&& GET_MODE (tgt
) != HImode
)
3361 addr
= gen_lowpart (HImode
, addr
);
3362 emit_insn (gen_extend_insn (tgt
, addr
, GET_MODE (tgt
), HImode
, 0));
3366 if (GET_MODE (tgt
) != DImode
)
3367 addr
= gen_lowpart (GET_MODE (tgt
), addr
);
3368 emit_move_insn (tgt
, addr
);
3373 meml
= gen_reg_rtx (DImode
);
3374 memh
= gen_reg_rtx (DImode
);
3375 addr
= gen_reg_rtx (DImode
);
3376 extl
= gen_reg_rtx (DImode
);
3377 exth
= gen_reg_rtx (DImode
);
3379 mema
= XEXP (mem
, 0);
3380 if (GET_CODE (mema
) == LO_SUM
)
3381 mema
= force_reg (Pmode
, mema
);
3383 /* AND addresses cannot be in any alias set, since they may implicitly
3384 alias surrounding code. Ideally we'd have some alias set that
3385 covered all types except those with alignment 8 or higher. */
3387 tmp
= change_address (mem
, DImode
,
3388 gen_rtx_AND (DImode
,
3389 plus_constant (mema
, ofs
),
3391 set_mem_alias_set (tmp
, 0);
3392 emit_move_insn (meml
, tmp
);
3394 tmp
= change_address (mem
, DImode
,
3395 gen_rtx_AND (DImode
,
3396 plus_constant (mema
, ofs
+ size
- 1),
3398 set_mem_alias_set (tmp
, 0);
3399 emit_move_insn (memh
, tmp
);
3401 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3403 emit_move_insn (addr
, plus_constant (mema
, -1));
3405 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3406 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3408 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3409 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3410 addr
, 1, OPTAB_WIDEN
);
3412 else if (sign
&& size
== 2)
3414 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3416 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3417 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3419 /* We must use tgt here for the target. Alpha-vms port fails if we use
3420 addr for the target, because addr is marked as a pointer and combine
3421 knows that pointers are always sign-extended 32-bit values. */
3422 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3423 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3424 addr
, 1, OPTAB_WIDEN
);
3428 if (WORDS_BIG_ENDIAN
)
3430 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3434 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3439 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3444 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3451 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3455 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3456 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
3460 emit_insn (gen_extwh_le (exth
, memh
, addr
));
3465 emit_insn (gen_extlh_le (exth
, memh
, addr
));
3470 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3479 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3480 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3485 emit_move_insn (tgt
, gen_lowpart (GET_MODE (tgt
), addr
));
3488 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3491 alpha_expand_unaligned_store (rtx dst
, rtx src
,
3492 HOST_WIDE_INT size
, HOST_WIDE_INT ofs
)
3494 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3496 if (TARGET_BWX
&& size
== 2)
3498 if (src
!= const0_rtx
)
3500 dstl
= gen_lowpart (QImode
, src
);
3501 dsth
= expand_simple_binop (DImode
, LSHIFTRT
, src
, GEN_INT (8),
3502 NULL
, 1, OPTAB_LIB_WIDEN
);
3503 dsth
= gen_lowpart (QImode
, dsth
);
3506 dstl
= dsth
= const0_rtx
;
3508 meml
= adjust_address (dst
, QImode
, ofs
);
3509 memh
= adjust_address (dst
, QImode
, ofs
+1);
3510 if (BYTES_BIG_ENDIAN
)
3511 addr
= meml
, meml
= memh
, memh
= addr
;
3513 emit_move_insn (meml
, dstl
);
3514 emit_move_insn (memh
, dsth
);
3518 dstl
= gen_reg_rtx (DImode
);
3519 dsth
= gen_reg_rtx (DImode
);
3520 insl
= gen_reg_rtx (DImode
);
3521 insh
= gen_reg_rtx (DImode
);
3523 dsta
= XEXP (dst
, 0);
3524 if (GET_CODE (dsta
) == LO_SUM
)
3525 dsta
= force_reg (Pmode
, dsta
);
3527 /* AND addresses cannot be in any alias set, since they may implicitly
3528 alias surrounding code. Ideally we'd have some alias set that
3529 covered all types except those with alignment 8 or higher. */
3531 meml
= change_address (dst
, DImode
,
3532 gen_rtx_AND (DImode
,
3533 plus_constant (dsta
, ofs
),
3535 set_mem_alias_set (meml
, 0);
3537 memh
= change_address (dst
, DImode
,
3538 gen_rtx_AND (DImode
,
3539 plus_constant (dsta
, ofs
+ size
- 1),
3541 set_mem_alias_set (memh
, 0);
3543 emit_move_insn (dsth
, memh
);
3544 emit_move_insn (dstl
, meml
);
3545 if (WORDS_BIG_ENDIAN
)
3547 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
3549 if (src
!= const0_rtx
)
3554 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
3557 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
3560 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
3563 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
3564 GEN_INT (size
*8), addr
));
3570 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
3574 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3575 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
3579 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
3583 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
3587 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3589 if (src
!= CONST0_RTX (GET_MODE (src
)))
3591 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3592 GEN_INT (size
*8), addr
));
3597 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
3600 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
3603 emit_insn (gen_insql_le (insl
, gen_lowpart (DImode
, src
), addr
));
3608 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3613 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
3617 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
3618 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
3622 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
3627 if (src
!= CONST0_RTX (GET_MODE (src
)))
3629 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3630 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3633 if (WORDS_BIG_ENDIAN
)
3635 emit_move_insn (meml
, dstl
);
3636 emit_move_insn (memh
, dsth
);
3640 /* Must store high before low for degenerate case of aligned. */
3641 emit_move_insn (memh
, dsth
);
3642 emit_move_insn (meml
, dstl
);
3646 /* The block move code tries to maximize speed by separating loads and
3647 stores at the expense of register pressure: we load all of the data
3648 before we store it back out. There are two secondary effects worth
3649 mentioning, that this speeds copying to/from aligned and unaligned
3650 buffers, and that it makes the code significantly easier to write. */
3652 #define MAX_MOVE_WORDS 8
3654 /* Load an integral number of consecutive unaligned quadwords. */
3657 alpha_expand_unaligned_load_words (rtx
*out_regs
, rtx smem
,
3658 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3660 rtx
const im8
= GEN_INT (-8);
3661 rtx
const i64
= GEN_INT (64);
3662 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3663 rtx sreg
, areg
, tmp
, smema
;
3666 smema
= XEXP (smem
, 0);
3667 if (GET_CODE (smema
) == LO_SUM
)
3668 smema
= force_reg (Pmode
, smema
);
3670 /* Generate all the tmp registers we need. */
3671 for (i
= 0; i
< words
; ++i
)
3673 data_regs
[i
] = out_regs
[i
];
3674 ext_tmps
[i
] = gen_reg_rtx (DImode
);
3676 data_regs
[words
] = gen_reg_rtx (DImode
);
3679 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
3681 /* Load up all of the source data. */
3682 for (i
= 0; i
< words
; ++i
)
3684 tmp
= change_address (smem
, DImode
,
3685 gen_rtx_AND (DImode
,
3686 plus_constant (smema
, 8*i
),
3688 set_mem_alias_set (tmp
, 0);
3689 emit_move_insn (data_regs
[i
], tmp
);
3692 tmp
= change_address (smem
, DImode
,
3693 gen_rtx_AND (DImode
,
3694 plus_constant (smema
, 8*words
- 1),
3696 set_mem_alias_set (tmp
, 0);
3697 emit_move_insn (data_regs
[words
], tmp
);
3699 /* Extract the half-word fragments. Unfortunately DEC decided to make
3700 extxh with offset zero a noop instead of zeroing the register, so
3701 we must take care of that edge condition ourselves with cmov. */
3703 sreg
= copy_addr_to_reg (smema
);
3704 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
3706 if (WORDS_BIG_ENDIAN
)
3707 emit_move_insn (sreg
, plus_constant (sreg
, 7));
3708 for (i
= 0; i
< words
; ++i
)
3710 if (WORDS_BIG_ENDIAN
)
3712 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
3713 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
3717 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
3718 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
3720 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
3721 gen_rtx_IF_THEN_ELSE (DImode
,
3722 gen_rtx_EQ (DImode
, areg
,
3724 const0_rtx
, ext_tmps
[i
])));
3727 /* Merge the half-words into whole words. */
3728 for (i
= 0; i
< words
; ++i
)
3730 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3731 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
3735 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3736 may be NULL to store zeros. */
3739 alpha_expand_unaligned_store_words (rtx
*data_regs
, rtx dmem
,
3740 HOST_WIDE_INT words
, HOST_WIDE_INT ofs
)
3742 rtx
const im8
= GEN_INT (-8);
3743 rtx
const i64
= GEN_INT (64);
3744 rtx ins_tmps
[MAX_MOVE_WORDS
];
3745 rtx st_tmp_1
, st_tmp_2
, dreg
;
3746 rtx st_addr_1
, st_addr_2
, dmema
;
3749 dmema
= XEXP (dmem
, 0);
3750 if (GET_CODE (dmema
) == LO_SUM
)
3751 dmema
= force_reg (Pmode
, dmema
);
3753 /* Generate all the tmp registers we need. */
3754 if (data_regs
!= NULL
)
3755 for (i
= 0; i
< words
; ++i
)
3756 ins_tmps
[i
] = gen_reg_rtx(DImode
);
3757 st_tmp_1
= gen_reg_rtx(DImode
);
3758 st_tmp_2
= gen_reg_rtx(DImode
);
3761 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
3763 st_addr_2
= change_address (dmem
, DImode
,
3764 gen_rtx_AND (DImode
,
3765 plus_constant (dmema
, words
*8 - 1),
3767 set_mem_alias_set (st_addr_2
, 0);
3769 st_addr_1
= change_address (dmem
, DImode
,
3770 gen_rtx_AND (DImode
, dmema
, im8
));
3771 set_mem_alias_set (st_addr_1
, 0);
3773 /* Load up the destination end bits. */
3774 emit_move_insn (st_tmp_2
, st_addr_2
);
3775 emit_move_insn (st_tmp_1
, st_addr_1
);
3777 /* Shift the input data into place. */
3778 dreg
= copy_addr_to_reg (dmema
);
3779 if (WORDS_BIG_ENDIAN
)
3780 emit_move_insn (dreg
, plus_constant (dreg
, 7));
3781 if (data_regs
!= NULL
)
3783 for (i
= words
-1; i
>= 0; --i
)
3785 if (WORDS_BIG_ENDIAN
)
3787 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
3788 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
3792 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
3793 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
3796 for (i
= words
-1; i
> 0; --i
)
3798 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
3799 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
3804 /* Split and merge the ends with the destination data. */
3805 if (WORDS_BIG_ENDIAN
)
3807 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
3808 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
3812 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
3813 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
3816 if (data_regs
!= NULL
)
3818 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
3819 st_tmp_2
, 1, OPTAB_WIDEN
);
3820 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
3821 st_tmp_1
, 1, OPTAB_WIDEN
);
3825 if (WORDS_BIG_ENDIAN
)
3826 emit_move_insn (st_addr_1
, st_tmp_1
);
3828 emit_move_insn (st_addr_2
, st_tmp_2
);
3829 for (i
= words
-1; i
> 0; --i
)
3831 rtx tmp
= change_address (dmem
, DImode
,
3832 gen_rtx_AND (DImode
,
3833 plus_constant(dmema
,
3834 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
3836 set_mem_alias_set (tmp
, 0);
3837 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
3839 if (WORDS_BIG_ENDIAN
)
3840 emit_move_insn (st_addr_2
, st_tmp_2
);
3842 emit_move_insn (st_addr_1
, st_tmp_1
);
3846 /* Expand string/block move operations.
3848 operands[0] is the pointer to the destination.
3849 operands[1] is the pointer to the source.
3850 operands[2] is the number of bytes to move.
3851 operands[3] is the alignment. */
3854 alpha_expand_block_move (rtx operands
[])
3856 rtx bytes_rtx
= operands
[2];
3857 rtx align_rtx
= operands
[3];
3858 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
3859 HOST_WIDE_INT bytes
= orig_bytes
;
3860 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
3861 HOST_WIDE_INT dst_align
= src_align
;
3862 rtx orig_src
= operands
[1];
3863 rtx orig_dst
= operands
[0];
3864 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
3866 unsigned int i
, words
, ofs
, nregs
= 0;
3868 if (orig_bytes
<= 0)
3870 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
3873 /* Look for additional alignment information from recorded register info. */
3875 tmp
= XEXP (orig_src
, 0);
3877 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3878 else if (GET_CODE (tmp
) == PLUS
3879 && REG_P (XEXP (tmp
, 0))
3880 && CONST_INT_P (XEXP (tmp
, 1)))
3882 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3883 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3887 if (a
>= 64 && c
% 8 == 0)
3889 else if (a
>= 32 && c
% 4 == 0)
3891 else if (a
>= 16 && c
% 2 == 0)
3896 tmp
= XEXP (orig_dst
, 0);
3898 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
3899 else if (GET_CODE (tmp
) == PLUS
3900 && REG_P (XEXP (tmp
, 0))
3901 && CONST_INT_P (XEXP (tmp
, 1)))
3903 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
3904 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
3908 if (a
>= 64 && c
% 8 == 0)
3910 else if (a
>= 32 && c
% 4 == 0)
3912 else if (a
>= 16 && c
% 2 == 0)
3918 if (src_align
>= 64 && bytes
>= 8)
3922 for (i
= 0; i
< words
; ++i
)
3923 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3925 for (i
= 0; i
< words
; ++i
)
3926 emit_move_insn (data_regs
[nregs
+ i
],
3927 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
3934 if (src_align
>= 32 && bytes
>= 4)
3938 for (i
= 0; i
< words
; ++i
)
3939 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
3941 for (i
= 0; i
< words
; ++i
)
3942 emit_move_insn (data_regs
[nregs
+ i
],
3943 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
3954 for (i
= 0; i
< words
+1; ++i
)
3955 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
3957 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
3965 if (! TARGET_BWX
&& bytes
>= 4)
3967 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
3968 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
3975 if (src_align
>= 16)
3978 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3979 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
3982 } while (bytes
>= 2);
3984 else if (! TARGET_BWX
)
3986 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
3987 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
3995 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
3996 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4001 gcc_assert (nregs
<= ARRAY_SIZE (data_regs
));
4003 /* Now save it back out again. */
4007 /* Write out the data in whatever chunks reading the source allowed. */
4008 if (dst_align
>= 64)
4010 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4012 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4019 if (dst_align
>= 32)
4021 /* If the source has remaining DImode regs, write them out in
4023 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4025 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4026 NULL_RTX
, 1, OPTAB_WIDEN
);
4028 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4029 gen_lowpart (SImode
, data_regs
[i
]));
4030 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4031 gen_lowpart (SImode
, tmp
));
4036 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4038 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4045 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4047 /* Write out a remaining block of words using unaligned methods. */
4049 for (words
= 1; i
+ words
< nregs
; words
++)
4050 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4054 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4056 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4063 /* Due to the above, this won't be aligned. */
4064 /* ??? If we have more than one of these, consider constructing full
4065 words in registers and using alpha_expand_unaligned_store_words. */
4066 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4068 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4073 if (dst_align
>= 16)
4074 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4076 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4081 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4083 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4088 /* The remainder must be byte copies. */
4091 gcc_assert (GET_MODE (data_regs
[i
]) == QImode
);
4092 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4101 alpha_expand_block_clear (rtx operands
[])
4103 rtx bytes_rtx
= operands
[1];
4104 rtx align_rtx
= operands
[3];
4105 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4106 HOST_WIDE_INT bytes
= orig_bytes
;
4107 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4108 HOST_WIDE_INT alignofs
= 0;
4109 rtx orig_dst
= operands
[0];
4111 int i
, words
, ofs
= 0;
4113 if (orig_bytes
<= 0)
4115 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4118 /* Look for stricter alignment. */
4119 tmp
= XEXP (orig_dst
, 0);
4121 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4122 else if (GET_CODE (tmp
) == PLUS
4123 && REG_P (XEXP (tmp
, 0))
4124 && CONST_INT_P (XEXP (tmp
, 1)))
4126 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4127 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4132 align
= a
, alignofs
= 8 - c
% 8;
4134 align
= a
, alignofs
= 4 - c
% 4;
4136 align
= a
, alignofs
= 2 - c
% 2;
4140 /* Handle an unaligned prefix first. */
4144 #if HOST_BITS_PER_WIDE_INT >= 64
4145 /* Given that alignofs is bounded by align, the only time BWX could
4146 generate three stores is for a 7 byte fill. Prefer two individual
4147 stores over a load/mask/store sequence. */
4148 if ((!TARGET_BWX
|| alignofs
== 7)
4150 && !(alignofs
== 4 && bytes
>= 4))
4152 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4153 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4157 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4158 set_mem_alias_set (mem
, 0);
4160 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4161 if (bytes
< alignofs
)
4163 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4174 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4175 NULL_RTX
, 1, OPTAB_WIDEN
);
4177 emit_move_insn (mem
, tmp
);
4181 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4183 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4188 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4190 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4195 if (alignofs
== 4 && bytes
>= 4)
4197 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4203 /* If we've not used the extra lead alignment information by now,
4204 we won't be able to. Downgrade align to match what's left over. */
4207 alignofs
= alignofs
& -alignofs
;
4208 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4212 /* Handle a block of contiguous long-words. */
4214 if (align
>= 64 && bytes
>= 8)
4218 for (i
= 0; i
< words
; ++i
)
4219 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4226 /* If the block is large and appropriately aligned, emit a single
4227 store followed by a sequence of stq_u insns. */
4229 if (align
>= 32 && bytes
> 16)
4233 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4237 orig_dsta
= XEXP (orig_dst
, 0);
4238 if (GET_CODE (orig_dsta
) == LO_SUM
)
4239 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4242 for (i
= 0; i
< words
; ++i
)
4245 = change_address (orig_dst
, DImode
,
4246 gen_rtx_AND (DImode
,
4247 plus_constant (orig_dsta
, ofs
+ i
*8),
4249 set_mem_alias_set (mem
, 0);
4250 emit_move_insn (mem
, const0_rtx
);
4253 /* Depending on the alignment, the first stq_u may have overlapped
4254 with the initial stl, which means that the last stq_u didn't
4255 write as much as it would appear. Leave those questionable bytes
4257 bytes
-= words
* 8 - 4;
4258 ofs
+= words
* 8 - 4;
4261 /* Handle a smaller block of aligned words. */
4263 if ((align
>= 64 && bytes
== 4)
4264 || (align
== 32 && bytes
>= 4))
4268 for (i
= 0; i
< words
; ++i
)
4269 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4276 /* An unaligned block uses stq_u stores for as many as possible. */
4282 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4288 /* Next clean up any trailing pieces. */
4290 #if HOST_BITS_PER_WIDE_INT >= 64
4291 /* Count the number of bits in BYTES for which aligned stores could
4294 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4298 /* If we have appropriate alignment (and it wouldn't take too many
4299 instructions otherwise), mask out the bytes we need. */
4300 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4307 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4308 set_mem_alias_set (mem
, 0);
4310 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4312 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4313 NULL_RTX
, 1, OPTAB_WIDEN
);
4315 emit_move_insn (mem
, tmp
);
4318 else if (align
>= 32 && bytes
< 4)
4323 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4324 set_mem_alias_set (mem
, 0);
4326 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4328 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4329 NULL_RTX
, 1, OPTAB_WIDEN
);
4331 emit_move_insn (mem
, tmp
);
4337 if (!TARGET_BWX
&& bytes
>= 4)
4339 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4349 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4353 } while (bytes
>= 2);
4355 else if (! TARGET_BWX
)
4357 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4365 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4373 /* Returns a mask so that zap(x, value) == x & mask. */
4376 alpha_expand_zap_mask (HOST_WIDE_INT value
)
4381 if (HOST_BITS_PER_WIDE_INT
>= 64)
4383 HOST_WIDE_INT mask
= 0;
4385 for (i
= 7; i
>= 0; --i
)
4388 if (!((value
>> i
) & 1))
4392 result
= gen_int_mode (mask
, DImode
);
4396 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
4398 gcc_assert (HOST_BITS_PER_WIDE_INT
== 32);
4400 for (i
= 7; i
>= 4; --i
)
4403 if (!((value
>> i
) & 1))
4407 for (i
= 3; i
>= 0; --i
)
4410 if (!((value
>> i
) & 1))
4414 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
4421 alpha_expand_builtin_vector_binop (rtx (*gen
) (rtx
, rtx
, rtx
),
4422 enum machine_mode mode
,
4423 rtx op0
, rtx op1
, rtx op2
)
4425 op0
= gen_lowpart (mode
, op0
);
4427 if (op1
== const0_rtx
)
4428 op1
= CONST0_RTX (mode
);
4430 op1
= gen_lowpart (mode
, op1
);
4432 if (op2
== const0_rtx
)
4433 op2
= CONST0_RTX (mode
);
4435 op2
= gen_lowpart (mode
, op2
);
4437 emit_insn ((*gen
) (op0
, op1
, op2
));
4440 /* A subroutine of the atomic operation splitters. Jump to LABEL if
4441 COND is true. Mark the jump as unlikely to be taken. */
4444 emit_unlikely_jump (rtx cond
, rtx label
)
4446 rtx very_unlikely
= GEN_INT (REG_BR_PROB_BASE
/ 100 - 1);
4449 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
4450 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
4451 add_reg_note (x
, REG_BR_PROB
, very_unlikely
);
4454 /* A subroutine of the atomic operation splitters. Emit a load-locked
4455 instruction in MODE. */
4458 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
4460 rtx (*fn
) (rtx
, rtx
) = NULL
;
4462 fn
= gen_load_locked_si
;
4463 else if (mode
== DImode
)
4464 fn
= gen_load_locked_di
;
4465 emit_insn (fn (reg
, mem
));
4468 /* A subroutine of the atomic operation splitters. Emit a store-conditional
4469 instruction in MODE. */
4472 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
4474 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
4476 fn
= gen_store_conditional_si
;
4477 else if (mode
== DImode
)
4478 fn
= gen_store_conditional_di
;
4479 emit_insn (fn (res
, mem
, val
));
4482 /* A subroutine of the atomic operation splitters. Emit an insxl
4483 instruction in MODE. */
4486 emit_insxl (enum machine_mode mode
, rtx op1
, rtx op2
)
4488 rtx ret
= gen_reg_rtx (DImode
);
4489 rtx (*fn
) (rtx
, rtx
, rtx
);
4491 if (WORDS_BIG_ENDIAN
)
4505 /* The insbl and inswl patterns require a register operand. */
4506 op1
= force_reg (mode
, op1
);
4507 emit_insn (fn (ret
, op1
, op2
));
4512 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
4513 to perform. MEM is the memory on which to operate. VAL is the second
4514 operand of the binary operator. BEFORE and AFTER are optional locations to
4515 return the value of MEM either before of after the operation. SCRATCH is
4516 a scratch register. */
4519 alpha_split_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
4520 rtx before
, rtx after
, rtx scratch
)
4522 enum machine_mode mode
= GET_MODE (mem
);
4523 rtx label
, x
, cond
= gen_rtx_REG (DImode
, REGNO (scratch
));
4525 emit_insn (gen_memory_barrier ());
4527 label
= gen_label_rtx ();
4529 label
= gen_rtx_LABEL_REF (DImode
, label
);
4533 emit_load_locked (mode
, before
, mem
);
4537 x
= gen_rtx_AND (mode
, before
, val
);
4538 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
4540 x
= gen_rtx_NOT (mode
, val
);
4543 x
= gen_rtx_fmt_ee (code
, mode
, before
, val
);
4545 emit_insn (gen_rtx_SET (VOIDmode
, after
, copy_rtx (x
)));
4546 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, x
));
4548 emit_store_conditional (mode
, cond
, mem
, scratch
);
4550 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4551 emit_unlikely_jump (x
, label
);
4553 emit_insn (gen_memory_barrier ());
4556 /* Expand a compare and swap operation. */
4559 alpha_split_compare_and_swap (rtx retval
, rtx mem
, rtx oldval
, rtx newval
,
4562 enum machine_mode mode
= GET_MODE (mem
);
4563 rtx label1
, label2
, x
, cond
= gen_lowpart (DImode
, scratch
);
4565 emit_insn (gen_memory_barrier ());
4567 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4568 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4569 emit_label (XEXP (label1
, 0));
4571 emit_load_locked (mode
, retval
, mem
);
4573 x
= gen_lowpart (DImode
, retval
);
4574 if (oldval
== const0_rtx
)
4575 x
= gen_rtx_NE (DImode
, x
, const0_rtx
);
4578 x
= gen_rtx_EQ (DImode
, x
, oldval
);
4579 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4580 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4582 emit_unlikely_jump (x
, label2
);
4584 emit_move_insn (scratch
, newval
);
4585 emit_store_conditional (mode
, cond
, mem
, scratch
);
4587 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4588 emit_unlikely_jump (x
, label1
);
4590 emit_insn (gen_memory_barrier ());
4591 emit_label (XEXP (label2
, 0));
4595 alpha_expand_compare_and_swap_12 (rtx dst
, rtx mem
, rtx oldval
, rtx newval
)
4597 enum machine_mode mode
= GET_MODE (mem
);
4598 rtx addr
, align
, wdst
;
4599 rtx (*fn5
) (rtx
, rtx
, rtx
, rtx
, rtx
);
4601 addr
= force_reg (DImode
, XEXP (mem
, 0));
4602 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4603 NULL_RTX
, 1, OPTAB_DIRECT
);
4605 oldval
= convert_modes (DImode
, mode
, oldval
, 1);
4606 newval
= emit_insxl (mode
, newval
, addr
);
4608 wdst
= gen_reg_rtx (DImode
);
4610 fn5
= gen_sync_compare_and_swapqi_1
;
4612 fn5
= gen_sync_compare_and_swaphi_1
;
4613 emit_insn (fn5 (wdst
, addr
, oldval
, newval
, align
));
4615 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4619 alpha_split_compare_and_swap_12 (enum machine_mode mode
, rtx dest
, rtx addr
,
4620 rtx oldval
, rtx newval
, rtx align
,
4621 rtx scratch
, rtx cond
)
4623 rtx label1
, label2
, mem
, width
, mask
, x
;
4625 mem
= gen_rtx_MEM (DImode
, align
);
4626 MEM_VOLATILE_P (mem
) = 1;
4628 emit_insn (gen_memory_barrier ());
4629 label1
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4630 label2
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4631 emit_label (XEXP (label1
, 0));
4633 emit_load_locked (DImode
, scratch
, mem
);
4635 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4636 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4637 if (WORDS_BIG_ENDIAN
)
4638 emit_insn (gen_extxl_be (dest
, scratch
, width
, addr
));
4640 emit_insn (gen_extxl_le (dest
, scratch
, width
, addr
));
4642 if (oldval
== const0_rtx
)
4643 x
= gen_rtx_NE (DImode
, dest
, const0_rtx
);
4646 x
= gen_rtx_EQ (DImode
, dest
, oldval
);
4647 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
4648 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4650 emit_unlikely_jump (x
, label2
);
4652 if (WORDS_BIG_ENDIAN
)
4653 emit_insn (gen_mskxl_be (scratch
, scratch
, mask
, addr
));
4655 emit_insn (gen_mskxl_le (scratch
, scratch
, mask
, addr
));
4656 emit_insn (gen_iordi3 (scratch
, scratch
, newval
));
4658 emit_store_conditional (DImode
, scratch
, mem
, scratch
);
4660 x
= gen_rtx_EQ (DImode
, scratch
, const0_rtx
);
4661 emit_unlikely_jump (x
, label1
);
4663 emit_insn (gen_memory_barrier ());
4664 emit_label (XEXP (label2
, 0));
4667 /* Expand an atomic exchange operation. */
4670 alpha_split_lock_test_and_set (rtx retval
, rtx mem
, rtx val
, rtx scratch
)
4672 enum machine_mode mode
= GET_MODE (mem
);
4673 rtx label
, x
, cond
= gen_lowpart (DImode
, scratch
);
4675 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4676 emit_label (XEXP (label
, 0));
4678 emit_load_locked (mode
, retval
, mem
);
4679 emit_move_insn (scratch
, val
);
4680 emit_store_conditional (mode
, cond
, mem
, scratch
);
4682 x
= gen_rtx_EQ (DImode
, cond
, const0_rtx
);
4683 emit_unlikely_jump (x
, label
);
4685 emit_insn (gen_memory_barrier ());
4689 alpha_expand_lock_test_and_set_12 (rtx dst
, rtx mem
, rtx val
)
4691 enum machine_mode mode
= GET_MODE (mem
);
4692 rtx addr
, align
, wdst
;
4693 rtx (*fn4
) (rtx
, rtx
, rtx
, rtx
);
4695 /* Force the address into a register. */
4696 addr
= force_reg (DImode
, XEXP (mem
, 0));
4698 /* Align it to a multiple of 8. */
4699 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-8),
4700 NULL_RTX
, 1, OPTAB_DIRECT
);
4702 /* Insert val into the correct byte location within the word. */
4703 val
= emit_insxl (mode
, val
, addr
);
4705 wdst
= gen_reg_rtx (DImode
);
4707 fn4
= gen_sync_lock_test_and_setqi_1
;
4709 fn4
= gen_sync_lock_test_and_sethi_1
;
4710 emit_insn (fn4 (wdst
, addr
, val
, align
));
4712 emit_move_insn (dst
, gen_lowpart (mode
, wdst
));
4716 alpha_split_lock_test_and_set_12 (enum machine_mode mode
, rtx dest
, rtx addr
,
4717 rtx val
, rtx align
, rtx scratch
)
4719 rtx label
, mem
, width
, mask
, x
;
4721 mem
= gen_rtx_MEM (DImode
, align
);
4722 MEM_VOLATILE_P (mem
) = 1;
4724 label
= gen_rtx_LABEL_REF (DImode
, gen_label_rtx ());
4725 emit_label (XEXP (label
, 0));
4727 emit_load_locked (DImode
, scratch
, mem
);
4729 width
= GEN_INT (GET_MODE_BITSIZE (mode
));
4730 mask
= GEN_INT (mode
== QImode
? 0xff : 0xffff);
4731 if (WORDS_BIG_ENDIAN
)
4733 emit_insn (gen_extxl_be (dest
, scratch
, width
, addr
));
4734 emit_insn (gen_mskxl_be (scratch
, scratch
, mask
, addr
));
4738 emit_insn (gen_extxl_le (dest
, scratch
, width
, addr
));
4739 emit_insn (gen_mskxl_le (scratch
, scratch
, mask
, addr
));
4741 emit_insn (gen_iordi3 (scratch
, scratch
, val
));
4743 emit_store_conditional (DImode
, scratch
, mem
, scratch
);
4745 x
= gen_rtx_EQ (DImode
, scratch
, const0_rtx
);
4746 emit_unlikely_jump (x
, label
);
4748 emit_insn (gen_memory_barrier ());
4751 /* Adjust the cost of a scheduling dependency. Return the new cost of
4752 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4755 alpha_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
4757 enum attr_type dep_insn_type
;
4759 /* If the dependence is an anti-dependence, there is no cost. For an
4760 output dependence, there is sometimes a cost, but it doesn't seem
4761 worth handling those few cases. */
4762 if (REG_NOTE_KIND (link
) != 0)
4765 /* If we can't recognize the insns, we can't really do anything. */
4766 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4769 dep_insn_type
= get_attr_type (dep_insn
);
4771 /* Bring in the user-defined memory latency. */
4772 if (dep_insn_type
== TYPE_ILD
4773 || dep_insn_type
== TYPE_FLD
4774 || dep_insn_type
== TYPE_LDSYM
)
4775 cost
+= alpha_memory_latency
-1;
4777 /* Everything else handled in DFA bypasses now. */
4782 /* The number of instructions that can be issued per cycle. */
4785 alpha_issue_rate (void)
4787 return (alpha_tune
== PROCESSOR_EV4
? 2 : 4);
4790 /* How many alternative schedules to try. This should be as wide as the
4791 scheduling freedom in the DFA, but no wider. Making this value too
4792 large results extra work for the scheduler.
4794 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4795 alternative schedules. For EV5, we can choose between E0/E1 and
4796 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4799 alpha_multipass_dfa_lookahead (void)
4801 return (alpha_tune
== PROCESSOR_EV6
? 4 : 2);
4804 /* Machine-specific function data. */
4806 struct GTY(()) machine_function
4809 /* List of call information words for calls from this function. */
4810 struct rtx_def
*first_ciw
;
4811 struct rtx_def
*last_ciw
;
4814 /* List of deferred case vectors. */
4815 struct rtx_def
*addr_list
;
4818 const char *some_ld_name
;
4820 /* For TARGET_LD_BUGGY_LDGP. */
4821 struct rtx_def
*gp_save_rtx
;
4823 /* For VMS condition handlers. */
4824 bool uses_condition_handler
;
4827 /* How to allocate a 'struct machine_function'. */
4829 static struct machine_function
*
4830 alpha_init_machine_status (void)
4832 return ggc_alloc_cleared_machine_function ();
4835 /* Support for frame based VMS condition handlers. */
4837 /* A VMS condition handler may be established for a function with a call to
4838 __builtin_establish_vms_condition_handler, and cancelled with a call to
4839 __builtin_revert_vms_condition_handler.
4841 The VMS Condition Handling Facility knows about the existence of a handler
4842 from the procedure descriptor .handler field. As the VMS native compilers,
4843 we store the user specified handler's address at a fixed location in the
4844 stack frame and point the procedure descriptor at a common wrapper which
4845 fetches the real handler's address and issues an indirect call.
4847 The indirection wrapper is "__gcc_shell_handler", provided by libgcc.
4849 We force the procedure kind to PT_STACK, and the fixed frame location is
4850 fp+8, just before the register save area. We use the handler_data field in
4851 the procedure descriptor to state the fp offset at which the installed
4852 handler address can be found. */
4854 #define VMS_COND_HANDLER_FP_OFFSET 8
4856 /* Expand code to store the currently installed user VMS condition handler
4857 into TARGET and install HANDLER as the new condition handler. */
4860 alpha_expand_builtin_establish_vms_condition_handler (rtx target
, rtx handler
)
4862 rtx handler_slot_address
4863 = plus_constant (hard_frame_pointer_rtx
, VMS_COND_HANDLER_FP_OFFSET
);
4866 = gen_rtx_MEM (DImode
, handler_slot_address
);
4868 emit_move_insn (target
, handler_slot
);
4869 emit_move_insn (handler_slot
, handler
);
4871 /* Notify the start/prologue/epilogue emitters that the condition handler
4872 slot is needed. In addition to reserving the slot space, this will force
4873 the procedure kind to PT_STACK so ensure that the hard_frame_pointer_rtx
4874 use above is correct. */
4875 cfun
->machine
->uses_condition_handler
= true;
4878 /* Expand code to store the current VMS condition handler into TARGET and
4882 alpha_expand_builtin_revert_vms_condition_handler (rtx target
)
4884 /* We implement this by establishing a null condition handler, with the tiny
4885 side effect of setting uses_condition_handler. This is a little bit
4886 pessimistic if no actual builtin_establish call is ever issued, which is
4887 not a real problem and expected never to happen anyway. */
4889 alpha_expand_builtin_establish_vms_condition_handler (target
, const0_rtx
);
4892 /* Functions to save and restore alpha_return_addr_rtx. */
4894 /* Start the ball rolling with RETURN_ADDR_RTX. */
4897 alpha_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
4902 return get_hard_reg_initial_val (Pmode
, REG_RA
);
4905 /* Return or create a memory slot containing the gp value for the current
4906 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4909 alpha_gp_save_rtx (void)
4911 rtx seq
, m
= cfun
->machine
->gp_save_rtx
;
4917 m
= assign_stack_local (DImode
, UNITS_PER_WORD
, BITS_PER_WORD
);
4918 m
= validize_mem (m
);
4919 emit_move_insn (m
, pic_offset_table_rtx
);
4924 /* We used to simply emit the sequence after entry_of_function.
4925 However this breaks the CFG if the first instruction in the
4926 first block is not the NOTE_INSN_BASIC_BLOCK, for example a
4927 label. Emit the sequence properly on the edge. We are only
4928 invoked from dw2_build_landing_pads and finish_eh_generation
4929 will call commit_edge_insertions thanks to a kludge. */
4930 insert_insn_on_edge (seq
, single_succ_edge (ENTRY_BLOCK_PTR
));
4932 cfun
->machine
->gp_save_rtx
= m
;
4939 alpha_ra_ever_killed (void)
4943 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
4944 return (int)df_regs_ever_live_p (REG_RA
);
4946 push_topmost_sequence ();
4948 pop_topmost_sequence ();
4950 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
4954 /* Return the trap mode suffix applicable to the current
4955 instruction, or NULL. */
4958 get_trap_mode_suffix (void)
4960 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
4964 case TRAP_SUFFIX_NONE
:
4967 case TRAP_SUFFIX_SU
:
4968 if (alpha_fptm
>= ALPHA_FPTM_SU
)
4972 case TRAP_SUFFIX_SUI
:
4973 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
4977 case TRAP_SUFFIX_V_SV
:
4985 case ALPHA_FPTM_SUI
:
4991 case TRAP_SUFFIX_V_SV_SVI
:
5000 case ALPHA_FPTM_SUI
:
5007 case TRAP_SUFFIX_U_SU_SUI
:
5016 case ALPHA_FPTM_SUI
:
5029 /* Return the rounding mode suffix applicable to the current
5030 instruction, or NULL. */
5033 get_round_mode_suffix (void)
5035 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5039 case ROUND_SUFFIX_NONE
:
5041 case ROUND_SUFFIX_NORMAL
:
5044 case ALPHA_FPRM_NORM
:
5046 case ALPHA_FPRM_MINF
:
5048 case ALPHA_FPRM_CHOP
:
5050 case ALPHA_FPRM_DYN
:
5057 case ROUND_SUFFIX_C
:
5066 /* Locate some local-dynamic symbol still in use by this function
5067 so that we can print its name in some movdi_er_tlsldm pattern. */
5070 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5074 if (GET_CODE (x
) == SYMBOL_REF
5075 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5077 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5085 get_some_local_dynamic_name (void)
5089 if (cfun
->machine
->some_ld_name
)
5090 return cfun
->machine
->some_ld_name
;
5092 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5094 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5095 return cfun
->machine
->some_ld_name
;
5100 /* Print an operand. Recognize special options, documented below. */
5103 print_operand (FILE *file
, rtx x
, int code
)
5110 /* Print the assembler name of the current function. */
5111 assemble_name (file
, alpha_fnname
);
5115 assemble_name (file
, get_some_local_dynamic_name ());
5120 const char *trap
= get_trap_mode_suffix ();
5121 const char *round
= get_round_mode_suffix ();
5124 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5125 (trap
? trap
: ""), (round
? round
: ""));
5130 /* Generates single precision instruction suffix. */
5131 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5135 /* Generates double precision instruction suffix. */
5136 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5140 if (alpha_this_literal_sequence_number
== 0)
5141 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5142 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5146 if (alpha_this_gpdisp_sequence_number
== 0)
5147 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5148 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5152 if (GET_CODE (x
) == HIGH
)
5153 output_addr_const (file
, XEXP (x
, 0));
5155 output_operand_lossage ("invalid %%H value");
5162 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5164 x
= XVECEXP (x
, 0, 0);
5165 lituse
= "lituse_tlsgd";
5167 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5169 x
= XVECEXP (x
, 0, 0);
5170 lituse
= "lituse_tlsldm";
5172 else if (CONST_INT_P (x
))
5173 lituse
= "lituse_jsr";
5176 output_operand_lossage ("invalid %%J value");
5180 if (x
!= const0_rtx
)
5181 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5189 #ifdef HAVE_AS_JSRDIRECT_RELOCS
5190 lituse
= "lituse_jsrdirect";
5192 lituse
= "lituse_jsr";
5195 gcc_assert (INTVAL (x
) != 0);
5196 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5200 /* If this operand is the constant zero, write it as "$31". */
5202 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5203 else if (x
== CONST0_RTX (GET_MODE (x
)))
5204 fprintf (file
, "$31");
5206 output_operand_lossage ("invalid %%r value");
5210 /* Similar, but for floating-point. */
5212 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5213 else if (x
== CONST0_RTX (GET_MODE (x
)))
5214 fprintf (file
, "$f31");
5216 output_operand_lossage ("invalid %%R value");
5220 /* Write the 1's complement of a constant. */
5221 if (!CONST_INT_P (x
))
5222 output_operand_lossage ("invalid %%N value");
5224 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5228 /* Write 1 << C, for a constant C. */
5229 if (!CONST_INT_P (x
))
5230 output_operand_lossage ("invalid %%P value");
5232 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5236 /* Write the high-order 16 bits of a constant, sign-extended. */
5237 if (!CONST_INT_P (x
))
5238 output_operand_lossage ("invalid %%h value");
5240 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5244 /* Write the low-order 16 bits of a constant, sign-extended. */
5245 if (!CONST_INT_P (x
))
5246 output_operand_lossage ("invalid %%L value");
5248 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5249 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5253 /* Write mask for ZAP insn. */
5254 if (GET_CODE (x
) == CONST_DOUBLE
)
5256 HOST_WIDE_INT mask
= 0;
5257 HOST_WIDE_INT value
;
5259 value
= CONST_DOUBLE_LOW (x
);
5260 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5265 value
= CONST_DOUBLE_HIGH (x
);
5266 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5269 mask
|= (1 << (i
+ sizeof (int)));
5271 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5274 else if (CONST_INT_P (x
))
5276 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5278 for (i
= 0; i
< 8; i
++, value
>>= 8)
5282 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5285 output_operand_lossage ("invalid %%m value");
5289 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5290 if (!CONST_INT_P (x
)
5291 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5292 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5293 output_operand_lossage ("invalid %%M value");
5295 fprintf (file
, "%s",
5296 (INTVAL (x
) == 8 ? "b"
5297 : INTVAL (x
) == 16 ? "w"
5298 : INTVAL (x
) == 32 ? "l"
5303 /* Similar, except do it from the mask. */
5304 if (CONST_INT_P (x
))
5306 HOST_WIDE_INT value
= INTVAL (x
);
5313 if (value
== 0xffff)
5318 if (value
== 0xffffffff)
5329 else if (HOST_BITS_PER_WIDE_INT
== 32
5330 && GET_CODE (x
) == CONST_DOUBLE
5331 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5332 && CONST_DOUBLE_HIGH (x
) == 0)
5337 output_operand_lossage ("invalid %%U value");
5341 /* Write the constant value divided by 8 for little-endian mode or
5342 (56 - value) / 8 for big-endian mode. */
5344 if (!CONST_INT_P (x
)
5345 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5348 || (INTVAL (x
) & 7) != 0)
5349 output_operand_lossage ("invalid %%s value");
5351 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5353 ? (56 - INTVAL (x
)) / 8
5358 /* Same, except compute (64 - c) / 8 */
5360 if (!CONST_INT_P (x
)
5361 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5362 && (INTVAL (x
) & 7) != 8)
5363 output_operand_lossage ("invalid %%s value");
5365 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5370 /* On Unicos/Mk systems: use a DEX expression if the symbol
5371 clashes with a register name. */
5372 int dex
= unicosmk_need_dex (x
);
5374 fprintf (file
, "DEX(%d)", dex
);
5376 output_addr_const (file
, x
);
5380 case 'C': case 'D': case 'c': case 'd':
5381 /* Write out comparison name. */
5383 enum rtx_code c
= GET_CODE (x
);
5385 if (!COMPARISON_P (x
))
5386 output_operand_lossage ("invalid %%C value");
5388 else if (code
== 'D')
5389 c
= reverse_condition (c
);
5390 else if (code
== 'c')
5391 c
= swap_condition (c
);
5392 else if (code
== 'd')
5393 c
= swap_condition (reverse_condition (c
));
5396 fprintf (file
, "ule");
5398 fprintf (file
, "ult");
5399 else if (c
== UNORDERED
)
5400 fprintf (file
, "un");
5402 fprintf (file
, "%s", GET_RTX_NAME (c
));
5407 /* Write the divide or modulus operator. */
5408 switch (GET_CODE (x
))
5411 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5414 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5417 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5420 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5423 output_operand_lossage ("invalid %%E value");
5429 /* Write "_u" for unaligned access. */
5430 if (MEM_P (x
) && GET_CODE (XEXP (x
, 0)) == AND
)
5431 fprintf (file
, "_u");
5436 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5438 output_address (XEXP (x
, 0));
5439 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5441 switch (XINT (XEXP (x
, 0), 1))
5445 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5448 output_operand_lossage ("unknown relocation unspec");
5453 output_addr_const (file
, x
);
5457 output_operand_lossage ("invalid %%xn code");
5462 print_operand_address (FILE *file
, rtx addr
)
5465 HOST_WIDE_INT offset
= 0;
5467 if (GET_CODE (addr
) == AND
)
5468 addr
= XEXP (addr
, 0);
5470 if (GET_CODE (addr
) == PLUS
5471 && CONST_INT_P (XEXP (addr
, 1)))
5473 offset
= INTVAL (XEXP (addr
, 1));
5474 addr
= XEXP (addr
, 0);
5477 if (GET_CODE (addr
) == LO_SUM
)
5479 const char *reloc16
, *reloclo
;
5480 rtx op1
= XEXP (addr
, 1);
5482 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5484 op1
= XEXP (op1
, 0);
5485 switch (XINT (op1
, 1))
5489 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5493 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5496 output_operand_lossage ("unknown relocation unspec");
5500 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5505 reloclo
= "gprellow";
5506 output_addr_const (file
, op1
);
5510 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
5512 addr
= XEXP (addr
, 0);
5513 switch (GET_CODE (addr
))
5516 basereg
= REGNO (addr
);
5520 basereg
= subreg_regno (addr
);
5527 fprintf (file
, "($%d)\t\t!%s", basereg
,
5528 (basereg
== 29 ? reloc16
: reloclo
));
5532 switch (GET_CODE (addr
))
5535 basereg
= REGNO (addr
);
5539 basereg
= subreg_regno (addr
);
5543 offset
= INTVAL (addr
);
5546 #if TARGET_ABI_OPEN_VMS
5548 fprintf (file
, "%s", XSTR (addr
, 0));
5552 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
5553 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
);
5554 fprintf (file
, "%s+" HOST_WIDE_INT_PRINT_DEC
,
5555 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5556 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5564 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"($%d)", offset
, basereg
);
5567 /* Emit RTL insns to initialize the variable parts of a trampoline at
5568 M_TRAMP. FNDECL is target function's decl. CHAIN_VALUE is an rtx
5569 for the static chain value for the function. */
5572 alpha_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
5574 rtx fnaddr
, mem
, word1
, word2
;
5576 fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
5578 #ifdef POINTERS_EXTEND_UNSIGNED
5579 fnaddr
= convert_memory_address (Pmode
, fnaddr
);
5580 chain_value
= convert_memory_address (Pmode
, chain_value
);
5583 if (TARGET_ABI_OPEN_VMS
)
5588 /* Construct the name of the trampoline entry point. */
5589 fnname
= XSTR (fnaddr
, 0);
5590 trname
= (char *) alloca (strlen (fnname
) + 5);
5591 strcpy (trname
, fnname
);
5592 strcat (trname
, "..tr");
5593 fnname
= ggc_alloc_string (trname
, strlen (trname
) + 1);
5594 word2
= gen_rtx_SYMBOL_REF (Pmode
, fnname
);
5596 /* Trampoline (or "bounded") procedure descriptor is constructed from
5597 the function's procedure descriptor with certain fields zeroed IAW
5598 the VMS calling standard. This is stored in the first quadword. */
5599 word1
= force_reg (DImode
, gen_const_mem (DImode
, fnaddr
));
5600 word1
= expand_and (DImode
, word1
, GEN_INT (0xffff0fff0000fff0), NULL
);
5604 /* These 4 instructions are:
5609 We don't bother setting the HINT field of the jump; the nop
5610 is merely there for padding. */
5611 word1
= GEN_INT (0xa77b0010a43b0018);
5612 word2
= GEN_INT (0x47ff041f6bfb0000);
5615 /* Store the first two words, as computed above. */
5616 mem
= adjust_address (m_tramp
, DImode
, 0);
5617 emit_move_insn (mem
, word1
);
5618 mem
= adjust_address (m_tramp
, DImode
, 8);
5619 emit_move_insn (mem
, word2
);
5621 /* Store function address and static chain value. */
5622 mem
= adjust_address (m_tramp
, Pmode
, 16);
5623 emit_move_insn (mem
, fnaddr
);
5624 mem
= adjust_address (m_tramp
, Pmode
, 24);
5625 emit_move_insn (mem
, chain_value
);
5627 if (!TARGET_ABI_OPEN_VMS
)
5629 emit_insn (gen_imb ());
5630 #ifdef ENABLE_EXECUTE_STACK
5631 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5632 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
5637 /* Determine where to put an argument to a function.
5638 Value is zero to push the argument on the stack,
5639 or a hard register in which to store the argument.
5641 MODE is the argument's machine mode.
5642 TYPE is the data type of the argument (as a tree).
5643 This is null for libcalls where that information may
5645 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5646 the preceding args and about the function being called.
5647 NAMED is nonzero if this argument is a named parameter
5648 (otherwise it is an extra parameter matching an ellipsis).
5650 On Alpha the first 6 words of args are normally in registers
5651 and the rest are pushed. */
5654 alpha_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5655 const_tree type
, bool named ATTRIBUTE_UNUSED
)
5660 /* Don't get confused and pass small structures in FP registers. */
5661 if (type
&& AGGREGATE_TYPE_P (type
))
5665 #ifdef ENABLE_CHECKING
5666 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5668 gcc_assert (!COMPLEX_MODE_P (mode
));
5671 /* Set up defaults for FP operands passed in FP registers, and
5672 integral operands passed in integer registers. */
5673 if (TARGET_FPREGS
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5679 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5680 the two platforms, so we can't avoid conditional compilation. */
5681 #if TARGET_ABI_OPEN_VMS
5683 if (mode
== VOIDmode
)
5684 return alpha_arg_info_reg_val (*cum
);
5686 num_args
= cum
->num_args
;
5688 || targetm
.calls
.must_pass_in_stack (mode
, type
))
5691 #elif TARGET_ABI_OSF
5697 /* VOID is passed as a special flag for "last argument". */
5698 if (type
== void_type_node
)
5700 else if (targetm
.calls
.must_pass_in_stack (mode
, type
))
5704 #error Unhandled ABI
5707 return gen_rtx_REG (mode
, num_args
+ basereg
);
5710 /* Update the data in CUM to advance over an argument
5711 of mode MODE and data type TYPE.
5712 (TYPE is null for libcalls where that information may not be available.) */
5715 alpha_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5716 const_tree type
, bool named ATTRIBUTE_UNUSED
)
5718 bool onstack
= targetm
.calls
.must_pass_in_stack (mode
, type
);
5719 int increment
= onstack
? 6 : ALPHA_ARG_SIZE (mode
, type
, named
);
5724 if (!onstack
&& cum
->num_args
< 6)
5725 cum
->atypes
[cum
->num_args
] = alpha_arg_type (mode
);
5726 cum
->num_args
+= increment
;
5731 alpha_arg_partial_bytes (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5732 enum machine_mode mode ATTRIBUTE_UNUSED
,
5733 tree type ATTRIBUTE_UNUSED
,
5734 bool named ATTRIBUTE_UNUSED
)
5738 #if TARGET_ABI_OPEN_VMS
5739 if (cum
->num_args
< 6
5740 && 6 < cum
->num_args
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5741 words
= 6 - cum
->num_args
;
5742 #elif TARGET_ABI_UNICOSMK
5743 /* Never any split arguments. */
5744 #elif TARGET_ABI_OSF
5745 if (*cum
< 6 && 6 < *cum
+ ALPHA_ARG_SIZE (mode
, type
, named
))
5748 #error Unhandled ABI
5751 return words
* UNITS_PER_WORD
;
5755 /* Return true if TYPE must be returned in memory, instead of in registers. */
5758 alpha_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5760 enum machine_mode mode
= VOIDmode
;
5765 mode
= TYPE_MODE (type
);
5767 /* All aggregates are returned in memory, except on OpenVMS where
5768 records that fit 64 bits should be returned by immediate value
5769 as required by section 3.8.7.1 of the OpenVMS Calling Standard. */
5770 if (TARGET_ABI_OPEN_VMS
5771 && TREE_CODE (type
) != ARRAY_TYPE
5772 && (unsigned HOST_WIDE_INT
) int_size_in_bytes(type
) <= 8)
5775 if (AGGREGATE_TYPE_P (type
))
5779 size
= GET_MODE_SIZE (mode
);
5780 switch (GET_MODE_CLASS (mode
))
5782 case MODE_VECTOR_FLOAT
:
5783 /* Pass all float vectors in memory, like an aggregate. */
5786 case MODE_COMPLEX_FLOAT
:
5787 /* We judge complex floats on the size of their element,
5788 not the size of the whole type. */
5789 size
= GET_MODE_UNIT_SIZE (mode
);
5794 case MODE_COMPLEX_INT
:
5795 case MODE_VECTOR_INT
:
5799 /* ??? We get called on all sorts of random stuff from
5800 aggregate_value_p. We must return something, but it's not
5801 clear what's safe to return. Pretend it's a struct I
5806 /* Otherwise types must fit in one register. */
5807 return size
> UNITS_PER_WORD
;
5810 /* Return true if TYPE should be passed by invisible reference. */
5813 alpha_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
5814 enum machine_mode mode
,
5815 const_tree type ATTRIBUTE_UNUSED
,
5816 bool named ATTRIBUTE_UNUSED
)
5818 return mode
== TFmode
|| mode
== TCmode
;
5821 /* Define how to find the value returned by a function. VALTYPE is the
5822 data type of the value (as a tree). If the precise function being
5823 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5824 MODE is set instead of VALTYPE for libcalls.
5826 On Alpha the value is found in $0 for integer functions and
5827 $f0 for floating-point functions. */
5830 function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
5831 enum machine_mode mode
)
5833 unsigned int regnum
, dummy ATTRIBUTE_UNUSED
;
5834 enum mode_class mclass
;
5836 gcc_assert (!valtype
|| !alpha_return_in_memory (valtype
, func
));
5839 mode
= TYPE_MODE (valtype
);
5841 mclass
= GET_MODE_CLASS (mode
);
5845 /* Do the same thing as PROMOTE_MODE except for libcalls on VMS,
5846 where we have them returning both SImode and DImode. */
5847 if (!(TARGET_ABI_OPEN_VMS
&& valtype
&& AGGREGATE_TYPE_P (valtype
)))
5848 PROMOTE_MODE (mode
, dummy
, valtype
);
5851 case MODE_COMPLEX_INT
:
5852 case MODE_VECTOR_INT
:
5860 case MODE_COMPLEX_FLOAT
:
5862 enum machine_mode cmode
= GET_MODE_INNER (mode
);
5864 return gen_rtx_PARALLEL
5867 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 32),
5869 gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (cmode
, 33),
5870 GEN_INT (GET_MODE_SIZE (cmode
)))));
5874 /* We should only reach here for BLKmode on VMS. */
5875 gcc_assert (TARGET_ABI_OPEN_VMS
&& mode
== BLKmode
);
5883 return gen_rtx_REG (mode
, regnum
);
5886 /* TCmode complex values are passed by invisible reference. We
5887 should not split these values. */
5890 alpha_split_complex_arg (const_tree type
)
5892 return TYPE_MODE (type
) != TCmode
;
5896 alpha_build_builtin_va_list (void)
5898 tree base
, ofs
, space
, record
, type_decl
;
5900 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5901 return ptr_type_node
;
5903 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5904 type_decl
= build_decl (BUILTINS_LOCATION
,
5905 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5906 TYPE_STUB_DECL (record
) = type_decl
;
5907 TYPE_NAME (record
) = type_decl
;
5909 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5911 /* Dummy field to prevent alignment warnings. */
5912 space
= build_decl (BUILTINS_LOCATION
,
5913 FIELD_DECL
, NULL_TREE
, integer_type_node
);
5914 DECL_FIELD_CONTEXT (space
) = record
;
5915 DECL_ARTIFICIAL (space
) = 1;
5916 DECL_IGNORED_P (space
) = 1;
5918 ofs
= build_decl (BUILTINS_LOCATION
,
5919 FIELD_DECL
, get_identifier ("__offset"),
5921 DECL_FIELD_CONTEXT (ofs
) = record
;
5922 DECL_CHAIN (ofs
) = space
;
5923 /* ??? This is a hack, __offset is marked volatile to prevent
5924 DCE that confuses stdarg optimization and results in
5925 gcc.c-torture/execute/stdarg-1.c failure. See PR 41089. */
5926 TREE_THIS_VOLATILE (ofs
) = 1;
5928 base
= build_decl (BUILTINS_LOCATION
,
5929 FIELD_DECL
, get_identifier ("__base"),
5931 DECL_FIELD_CONTEXT (base
) = record
;
5932 DECL_CHAIN (base
) = ofs
;
5934 TYPE_FIELDS (record
) = base
;
5935 layout_type (record
);
5937 va_list_gpr_counter_field
= ofs
;
5942 /* Helper function for alpha_stdarg_optimize_hook. Skip over casts
5943 and constant additions. */
5946 va_list_skip_additions (tree lhs
)
5952 enum tree_code code
;
5954 stmt
= SSA_NAME_DEF_STMT (lhs
);
5956 if (gimple_code (stmt
) == GIMPLE_PHI
)
5959 if (!is_gimple_assign (stmt
)
5960 || gimple_assign_lhs (stmt
) != lhs
)
5963 if (TREE_CODE (gimple_assign_rhs1 (stmt
)) != SSA_NAME
)
5965 code
= gimple_assign_rhs_code (stmt
);
5966 if (!CONVERT_EXPR_CODE_P (code
)
5967 && ((code
!= PLUS_EXPR
&& code
!= POINTER_PLUS_EXPR
)
5968 || TREE_CODE (gimple_assign_rhs2 (stmt
)) != INTEGER_CST
5969 || !host_integerp (gimple_assign_rhs2 (stmt
), 1)))
5972 lhs
= gimple_assign_rhs1 (stmt
);
5976 /* Check if LHS = RHS statement is
5977 LHS = *(ap.__base + ap.__offset + cst)
5980 + ((ap.__offset + cst <= 47)
5981 ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2).
5982 If the former, indicate that GPR registers are needed,
5983 if the latter, indicate that FPR registers are needed.
5985 Also look for LHS = (*ptr).field, where ptr is one of the forms
5988 On alpha, cfun->va_list_gpr_size is used as size of the needed
5989 regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if GPR
5990 registers are needed and bit 1 set if FPR registers are needed.
5991 Return true if va_list references should not be scanned for the
5992 current statement. */
5995 alpha_stdarg_optimize_hook (struct stdarg_info
*si
, const_gimple stmt
)
5997 tree base
, offset
, rhs
;
6001 if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt
))
6002 != GIMPLE_SINGLE_RHS
)
6005 rhs
= gimple_assign_rhs1 (stmt
);
6006 while (handled_component_p (rhs
))
6007 rhs
= TREE_OPERAND (rhs
, 0);
6008 if (TREE_CODE (rhs
) != MEM_REF
6009 || TREE_CODE (TREE_OPERAND (rhs
, 0)) != SSA_NAME
)
6012 stmt
= va_list_skip_additions (TREE_OPERAND (rhs
, 0));
6014 || !is_gimple_assign (stmt
)
6015 || gimple_assign_rhs_code (stmt
) != POINTER_PLUS_EXPR
)
6018 base
= gimple_assign_rhs1 (stmt
);
6019 if (TREE_CODE (base
) == SSA_NAME
)
6021 base_stmt
= va_list_skip_additions (base
);
6023 && is_gimple_assign (base_stmt
)
6024 && gimple_assign_rhs_code (base_stmt
) == COMPONENT_REF
)
6025 base
= gimple_assign_rhs1 (base_stmt
);
6028 if (TREE_CODE (base
) != COMPONENT_REF
6029 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
6031 base
= gimple_assign_rhs2 (stmt
);
6032 if (TREE_CODE (base
) == SSA_NAME
)
6034 base_stmt
= va_list_skip_additions (base
);
6036 && is_gimple_assign (base_stmt
)
6037 && gimple_assign_rhs_code (base_stmt
) == COMPONENT_REF
)
6038 base
= gimple_assign_rhs1 (base_stmt
);
6041 if (TREE_CODE (base
) != COMPONENT_REF
6042 || TREE_OPERAND (base
, 1) != TYPE_FIELDS (va_list_type_node
))
6048 base
= get_base_address (base
);
6049 if (TREE_CODE (base
) != VAR_DECL
6050 || !bitmap_bit_p (si
->va_list_vars
, DECL_UID (base
)))
6053 offset
= gimple_op (stmt
, 1 + offset_arg
);
6054 if (TREE_CODE (offset
) == SSA_NAME
)
6056 gimple offset_stmt
= va_list_skip_additions (offset
);
6059 && gimple_code (offset_stmt
) == GIMPLE_PHI
)
6062 gimple arg1_stmt
, arg2_stmt
;
6064 enum tree_code code1
, code2
;
6066 if (gimple_phi_num_args (offset_stmt
) != 2)
6070 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt
, 0));
6072 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt
, 1));
6073 if (arg1_stmt
== NULL
6074 || !is_gimple_assign (arg1_stmt
)
6075 || arg2_stmt
== NULL
6076 || !is_gimple_assign (arg2_stmt
))
6079 code1
= gimple_assign_rhs_code (arg1_stmt
);
6080 code2
= gimple_assign_rhs_code (arg2_stmt
);
6081 if (code1
== COMPONENT_REF
6082 && (code2
== MINUS_EXPR
|| code2
== PLUS_EXPR
))
6084 else if (code2
== COMPONENT_REF
6085 && (code1
== MINUS_EXPR
|| code1
== PLUS_EXPR
))
6087 gimple tem
= arg1_stmt
;
6089 arg1_stmt
= arg2_stmt
;
6095 if (!host_integerp (gimple_assign_rhs2 (arg2_stmt
), 0))
6098 sub
= tree_low_cst (gimple_assign_rhs2 (arg2_stmt
), 0);
6099 if (code2
== MINUS_EXPR
)
6101 if (sub
< -48 || sub
> -32)
6104 arg1
= gimple_assign_rhs1 (arg1_stmt
);
6105 arg2
= gimple_assign_rhs1 (arg2_stmt
);
6106 if (TREE_CODE (arg2
) == SSA_NAME
)
6108 arg2_stmt
= va_list_skip_additions (arg2
);
6109 if (arg2_stmt
== NULL
6110 || !is_gimple_assign (arg2_stmt
)
6111 || gimple_assign_rhs_code (arg2_stmt
) != COMPONENT_REF
)
6113 arg2
= gimple_assign_rhs1 (arg2_stmt
);
6118 if (TREE_CODE (arg1
) != COMPONENT_REF
6119 || TREE_OPERAND (arg1
, 1) != va_list_gpr_counter_field
6120 || get_base_address (arg1
) != base
)
6123 /* Need floating point regs. */
6124 cfun
->va_list_fpr_size
|= 2;
6128 && is_gimple_assign (offset_stmt
)
6129 && gimple_assign_rhs_code (offset_stmt
) == COMPONENT_REF
)
6130 offset
= gimple_assign_rhs1 (offset_stmt
);
6132 if (TREE_CODE (offset
) != COMPONENT_REF
6133 || TREE_OPERAND (offset
, 1) != va_list_gpr_counter_field
6134 || get_base_address (offset
) != base
)
6137 /* Need general regs. */
6138 cfun
->va_list_fpr_size
|= 1;
6142 si
->va_list_escapes
= true;
6147 /* Perform any needed actions needed for a function that is receiving a
6148 variable number of arguments. */
6151 alpha_setup_incoming_varargs (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
6152 tree type
, int *pretend_size
, int no_rtl
)
6154 CUMULATIVE_ARGS cum
= *pcum
;
6156 /* Skip the current argument. */
6157 targetm
.calls
.function_arg_advance (&cum
, mode
, type
, true);
6159 #if TARGET_ABI_UNICOSMK
6160 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6161 arguments on the stack. Unfortunately, it doesn't always store the first
6162 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6163 with stdargs as we always have at least one named argument there. */
6164 if (cum
.num_reg_words
< 6)
6168 emit_insn (gen_umk_mismatch_args (GEN_INT (cum
.num_reg_words
)));
6169 emit_insn (gen_arg_home_umk ());
6173 #elif TARGET_ABI_OPEN_VMS
6174 /* For VMS, we allocate space for all 6 arg registers plus a count.
6176 However, if NO registers need to be saved, don't allocate any space.
6177 This is not only because we won't need the space, but because AP
6178 includes the current_pretend_args_size and we don't want to mess up
6179 any ap-relative addresses already made. */
6180 if (cum
.num_args
< 6)
6184 emit_move_insn (gen_rtx_REG (DImode
, 1), virtual_incoming_args_rtx
);
6185 emit_insn (gen_arg_home ());
6187 *pretend_size
= 7 * UNITS_PER_WORD
;
6190 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6191 only push those that are remaining. However, if NO registers need to
6192 be saved, don't allocate any space. This is not only because we won't
6193 need the space, but because AP includes the current_pretend_args_size
6194 and we don't want to mess up any ap-relative addresses already made.
6196 If we are not to use the floating-point registers, save the integer
6197 registers where we would put the floating-point registers. This is
6198 not the most efficient way to implement varargs with just one register
6199 class, but it isn't worth doing anything more efficient in this rare
6207 alias_set_type set
= get_varargs_alias_set ();
6210 count
= cfun
->va_list_gpr_size
/ UNITS_PER_WORD
;
6211 if (count
> 6 - cum
)
6214 /* Detect whether integer registers or floating-point registers
6215 are needed by the detected va_arg statements. See above for
6216 how these values are computed. Note that the "escape" value
6217 is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of
6219 gcc_assert ((VA_LIST_MAX_FPR_SIZE
& 3) == 3);
6221 if (cfun
->va_list_fpr_size
& 1)
6223 tmp
= gen_rtx_MEM (BLKmode
,
6224 plus_constant (virtual_incoming_args_rtx
,
6225 (cum
+ 6) * UNITS_PER_WORD
));
6226 MEM_NOTRAP_P (tmp
) = 1;
6227 set_mem_alias_set (tmp
, set
);
6228 move_block_from_reg (16 + cum
, tmp
, count
);
6231 if (cfun
->va_list_fpr_size
& 2)
6233 tmp
= gen_rtx_MEM (BLKmode
,
6234 plus_constant (virtual_incoming_args_rtx
,
6235 cum
* UNITS_PER_WORD
));
6236 MEM_NOTRAP_P (tmp
) = 1;
6237 set_mem_alias_set (tmp
, set
);
6238 move_block_from_reg (16 + cum
+ TARGET_FPREGS
*32, tmp
, count
);
6241 *pretend_size
= 12 * UNITS_PER_WORD
;
6246 alpha_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
6248 HOST_WIDE_INT offset
;
6249 tree t
, offset_field
, base_field
;
6251 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6254 if (TARGET_ABI_UNICOSMK
)
6255 std_expand_builtin_va_start (valist
, nextarg
);
6257 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6258 up by 48, storing fp arg registers in the first 48 bytes, and the
6259 integer arg registers in the next 48 bytes. This is only done,
6260 however, if any integer registers need to be stored.
6262 If no integer registers need be stored, then we must subtract 48
6263 in order to account for the integer arg registers which are counted
6264 in argsize above, but which are not actually stored on the stack.
6265 Must further be careful here about structures straddling the last
6266 integer argument register; that futzes with pretend_args_size,
6267 which changes the meaning of AP. */
6270 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6272 offset
= -6 * UNITS_PER_WORD
+ crtl
->args
.pretend_args_size
;
6274 if (TARGET_ABI_OPEN_VMS
)
6276 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6277 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
6278 size_int (offset
+ NUM_ARGS
* UNITS_PER_WORD
));
6279 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6280 TREE_SIDE_EFFECTS (t
) = 1;
6281 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6285 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6286 offset_field
= DECL_CHAIN (base_field
);
6288 base_field
= build3 (COMPONENT_REF
, TREE_TYPE (base_field
),
6289 valist
, base_field
, NULL_TREE
);
6290 offset_field
= build3 (COMPONENT_REF
, TREE_TYPE (offset_field
),
6291 valist
, offset_field
, NULL_TREE
);
6293 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6294 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
6296 t
= build2 (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6297 TREE_SIDE_EFFECTS (t
) = 1;
6298 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6300 t
= build_int_cst (NULL_TREE
, NUM_ARGS
* UNITS_PER_WORD
);
6301 t
= build2 (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6302 TREE_SIDE_EFFECTS (t
) = 1;
6303 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6308 alpha_gimplify_va_arg_1 (tree type
, tree base
, tree offset
,
6311 tree type_size
, ptr_type
, addend
, t
, addr
;
6312 gimple_seq internal_post
;
6314 /* If the type could not be passed in registers, skip the block
6315 reserved for the registers. */
6316 if (targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
6318 t
= build_int_cst (TREE_TYPE (offset
), 6*8);
6319 gimplify_assign (offset
,
6320 build2 (MAX_EXPR
, TREE_TYPE (offset
), offset
, t
),
6325 ptr_type
= build_pointer_type_for_mode (type
, ptr_mode
, true);
6327 if (TREE_CODE (type
) == COMPLEX_TYPE
)
6329 tree real_part
, imag_part
, real_temp
;
6331 real_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6334 /* Copy the value into a new temporary, lest the formal temporary
6335 be reused out from under us. */
6336 real_temp
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
6338 imag_part
= alpha_gimplify_va_arg_1 (TREE_TYPE (type
), base
,
6341 return build2 (COMPLEX_EXPR
, type
, real_temp
, imag_part
);
6343 else if (TREE_CODE (type
) == REAL_TYPE
)
6345 tree fpaddend
, cond
, fourtyeight
;
6347 fourtyeight
= build_int_cst (TREE_TYPE (addend
), 6*8);
6348 fpaddend
= fold_build2 (MINUS_EXPR
, TREE_TYPE (addend
),
6349 addend
, fourtyeight
);
6350 cond
= fold_build2 (LT_EXPR
, boolean_type_node
, addend
, fourtyeight
);
6351 addend
= fold_build3 (COND_EXPR
, TREE_TYPE (addend
), cond
,
6355 /* Build the final address and force that value into a temporary. */
6356 addr
= build2 (POINTER_PLUS_EXPR
, ptr_type
, fold_convert (ptr_type
, base
),
6357 fold_convert (sizetype
, addend
));
6358 internal_post
= NULL
;
6359 gimplify_expr (&addr
, pre_p
, &internal_post
, is_gimple_val
, fb_rvalue
);
6360 gimple_seq_add_seq (pre_p
, internal_post
);
6362 /* Update the offset field. */
6363 type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
));
6364 if (type_size
== NULL
|| TREE_OVERFLOW (type_size
))
6368 t
= size_binop (PLUS_EXPR
, type_size
, size_int (7));
6369 t
= size_binop (TRUNC_DIV_EXPR
, t
, size_int (8));
6370 t
= size_binop (MULT_EXPR
, t
, size_int (8));
6372 t
= fold_convert (TREE_TYPE (offset
), t
);
6373 gimplify_assign (offset
, build2 (PLUS_EXPR
, TREE_TYPE (offset
), offset
, t
),
6376 return build_va_arg_indirect_ref (addr
);
6380 alpha_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6383 tree offset_field
, base_field
, offset
, base
, t
, r
;
6386 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6387 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6389 base_field
= TYPE_FIELDS (va_list_type_node
);
6390 offset_field
= DECL_CHAIN (base_field
);
6391 base_field
= build3 (COMPONENT_REF
, TREE_TYPE (base_field
),
6392 valist
, base_field
, NULL_TREE
);
6393 offset_field
= build3 (COMPONENT_REF
, TREE_TYPE (offset_field
),
6394 valist
, offset_field
, NULL_TREE
);
6396 /* Pull the fields of the structure out into temporaries. Since we never
6397 modify the base field, we can use a formal temporary. Sign-extend the
6398 offset field so that it's the proper width for pointer arithmetic. */
6399 base
= get_formal_tmp_var (base_field
, pre_p
);
6401 t
= fold_convert (lang_hooks
.types
.type_for_size (64, 0), offset_field
);
6402 offset
= get_initialized_tmp_var (t
, pre_p
, NULL
);
6404 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6406 type
= build_pointer_type_for_mode (type
, ptr_mode
, true);
6408 /* Find the value. Note that this will be a stable indirection, or
6409 a composite of stable indirections in the case of complex. */
6410 r
= alpha_gimplify_va_arg_1 (type
, base
, offset
, pre_p
);
6412 /* Stuff the offset temporary back into its field. */
6413 gimplify_assign (unshare_expr (offset_field
),
6414 fold_convert (TREE_TYPE (offset_field
), offset
), pre_p
);
6417 r
= build_va_arg_indirect_ref (r
);
6426 ALPHA_BUILTIN_CMPBGE
,
6427 ALPHA_BUILTIN_EXTBL
,
6428 ALPHA_BUILTIN_EXTWL
,
6429 ALPHA_BUILTIN_EXTLL
,
6430 ALPHA_BUILTIN_EXTQL
,
6431 ALPHA_BUILTIN_EXTWH
,
6432 ALPHA_BUILTIN_EXTLH
,
6433 ALPHA_BUILTIN_EXTQH
,
6434 ALPHA_BUILTIN_INSBL
,
6435 ALPHA_BUILTIN_INSWL
,
6436 ALPHA_BUILTIN_INSLL
,
6437 ALPHA_BUILTIN_INSQL
,
6438 ALPHA_BUILTIN_INSWH
,
6439 ALPHA_BUILTIN_INSLH
,
6440 ALPHA_BUILTIN_INSQH
,
6441 ALPHA_BUILTIN_MSKBL
,
6442 ALPHA_BUILTIN_MSKWL
,
6443 ALPHA_BUILTIN_MSKLL
,
6444 ALPHA_BUILTIN_MSKQL
,
6445 ALPHA_BUILTIN_MSKWH
,
6446 ALPHA_BUILTIN_MSKLH
,
6447 ALPHA_BUILTIN_MSKQH
,
6448 ALPHA_BUILTIN_UMULH
,
6450 ALPHA_BUILTIN_ZAPNOT
,
6451 ALPHA_BUILTIN_AMASK
,
6452 ALPHA_BUILTIN_IMPLVER
,
6454 ALPHA_BUILTIN_THREAD_POINTER
,
6455 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6456 ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER
,
6457 ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER
,
6460 ALPHA_BUILTIN_MINUB8
,
6461 ALPHA_BUILTIN_MINSB8
,
6462 ALPHA_BUILTIN_MINUW4
,
6463 ALPHA_BUILTIN_MINSW4
,
6464 ALPHA_BUILTIN_MAXUB8
,
6465 ALPHA_BUILTIN_MAXSB8
,
6466 ALPHA_BUILTIN_MAXUW4
,
6467 ALPHA_BUILTIN_MAXSW4
,
6471 ALPHA_BUILTIN_UNPKBL
,
6472 ALPHA_BUILTIN_UNPKBW
,
6477 ALPHA_BUILTIN_CTPOP
,
6482 static enum insn_code
const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6483 CODE_FOR_builtin_cmpbge
,
6484 CODE_FOR_builtin_extbl
,
6485 CODE_FOR_builtin_extwl
,
6486 CODE_FOR_builtin_extll
,
6487 CODE_FOR_builtin_extql
,
6488 CODE_FOR_builtin_extwh
,
6489 CODE_FOR_builtin_extlh
,
6490 CODE_FOR_builtin_extqh
,
6491 CODE_FOR_builtin_insbl
,
6492 CODE_FOR_builtin_inswl
,
6493 CODE_FOR_builtin_insll
,
6494 CODE_FOR_builtin_insql
,
6495 CODE_FOR_builtin_inswh
,
6496 CODE_FOR_builtin_inslh
,
6497 CODE_FOR_builtin_insqh
,
6498 CODE_FOR_builtin_mskbl
,
6499 CODE_FOR_builtin_mskwl
,
6500 CODE_FOR_builtin_mskll
,
6501 CODE_FOR_builtin_mskql
,
6502 CODE_FOR_builtin_mskwh
,
6503 CODE_FOR_builtin_msklh
,
6504 CODE_FOR_builtin_mskqh
,
6505 CODE_FOR_umuldi3_highpart
,
6506 CODE_FOR_builtin_zap
,
6507 CODE_FOR_builtin_zapnot
,
6508 CODE_FOR_builtin_amask
,
6509 CODE_FOR_builtin_implver
,
6510 CODE_FOR_builtin_rpcc
,
6513 CODE_FOR_builtin_establish_vms_condition_handler
,
6514 CODE_FOR_builtin_revert_vms_condition_handler
,
6517 CODE_FOR_builtin_minub8
,
6518 CODE_FOR_builtin_minsb8
,
6519 CODE_FOR_builtin_minuw4
,
6520 CODE_FOR_builtin_minsw4
,
6521 CODE_FOR_builtin_maxub8
,
6522 CODE_FOR_builtin_maxsb8
,
6523 CODE_FOR_builtin_maxuw4
,
6524 CODE_FOR_builtin_maxsw4
,
6525 CODE_FOR_builtin_perr
,
6526 CODE_FOR_builtin_pklb
,
6527 CODE_FOR_builtin_pkwb
,
6528 CODE_FOR_builtin_unpkbl
,
6529 CODE_FOR_builtin_unpkbw
,
6534 CODE_FOR_popcountdi2
6537 struct alpha_builtin_def
6540 enum alpha_builtin code
;
6541 unsigned int target_mask
;
6545 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6546 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0, true },
6547 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0, false }
6550 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6551 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0, true },
6552 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
, true },
6553 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
, true },
6554 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
, true },
6555 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
, true },
6556 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
, true },
6557 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
, true },
6558 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
, true }
6561 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6562 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0, true },
6563 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0, true },
6564 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0, true },
6565 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0, true },
6566 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0, true },
6567 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0, true },
6568 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0, true },
6569 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0, true },
6570 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0, true },
6571 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0, true },
6572 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0, true },
6573 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0, true },
6574 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0, true },
6575 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0, true },
6576 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0, true },
6577 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0, true },
6578 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0, true },
6579 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0, true },
6580 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0, true },
6581 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0, true },
6582 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0, true },
6583 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0, true },
6584 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0, true },
6585 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0, true },
6586 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0, true },
6587 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
, true },
6588 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
, true },
6589 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
, true },
6590 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
, true },
6591 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
, true },
6592 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
, true },
6593 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
, true },
6594 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
, true },
6595 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
, true }
6598 static GTY(()) tree alpha_v8qi_u
;
6599 static GTY(()) tree alpha_v8qi_s
;
6600 static GTY(()) tree alpha_v4hi_u
;
6601 static GTY(()) tree alpha_v4hi_s
;
6603 static GTY(()) tree alpha_builtins
[(int) ALPHA_BUILTIN_max
];
6605 /* Return the alpha builtin for CODE. */
6608 alpha_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
6610 if (code
>= ALPHA_BUILTIN_max
)
6611 return error_mark_node
;
6612 return alpha_builtins
[code
];
6615 /* Helper function of alpha_init_builtins. Add the built-in specified
6616 by NAME, TYPE, CODE, and ECF. */
6619 alpha_builtin_function (const char *name
, tree ftype
,
6620 enum alpha_builtin code
, unsigned ecf
)
6622 tree decl
= add_builtin_function (name
, ftype
, (int) code
,
6623 BUILT_IN_MD
, NULL
, NULL_TREE
);
6625 if (ecf
& ECF_CONST
)
6626 TREE_READONLY (decl
) = 1;
6627 if (ecf
& ECF_NOTHROW
)
6628 TREE_NOTHROW (decl
) = 1;
6630 alpha_builtins
[(int) code
] = decl
;
6633 /* Helper function of alpha_init_builtins. Add the COUNT built-in
6634 functions pointed to by P, with function type FTYPE. */
6637 alpha_add_builtins (const struct alpha_builtin_def
*p
, size_t count
,
6642 for (i
= 0; i
< count
; ++i
, ++p
)
6643 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6644 alpha_builtin_function (p
->name
, ftype
, p
->code
,
6645 (p
->is_const
? ECF_CONST
: 0) | ECF_NOTHROW
);
6649 alpha_init_builtins (void)
6651 tree dimode_integer_type_node
;
6654 dimode_integer_type_node
= lang_hooks
.types
.type_for_mode (DImode
, 0);
6656 /* Fwrite on VMS is non-standard. */
6657 #if TARGET_ABI_OPEN_VMS
6658 implicit_built_in_decls
[(int) BUILT_IN_FWRITE
] = NULL_TREE
;
6659 implicit_built_in_decls
[(int) BUILT_IN_FWRITE_UNLOCKED
] = NULL_TREE
;
6662 ftype
= build_function_type (dimode_integer_type_node
, void_list_node
);
6663 alpha_add_builtins (zero_arg_builtins
, ARRAY_SIZE (zero_arg_builtins
),
6666 ftype
= build_function_type_list (dimode_integer_type_node
,
6667 dimode_integer_type_node
, NULL_TREE
);
6668 alpha_add_builtins (one_arg_builtins
, ARRAY_SIZE (one_arg_builtins
),
6671 ftype
= build_function_type_list (dimode_integer_type_node
,
6672 dimode_integer_type_node
,
6673 dimode_integer_type_node
, NULL_TREE
);
6674 alpha_add_builtins (two_arg_builtins
, ARRAY_SIZE (two_arg_builtins
),
6677 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6678 alpha_builtin_function ("__builtin_thread_pointer", ftype
,
6679 ALPHA_BUILTIN_THREAD_POINTER
, ECF_NOTHROW
);
6681 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6682 alpha_builtin_function ("__builtin_set_thread_pointer", ftype
,
6683 ALPHA_BUILTIN_SET_THREAD_POINTER
, ECF_NOTHROW
);
6685 if (TARGET_ABI_OPEN_VMS
)
6687 ftype
= build_function_type_list (ptr_type_node
, ptr_type_node
,
6689 alpha_builtin_function ("__builtin_establish_vms_condition_handler",
6691 ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER
,
6694 ftype
= build_function_type_list (ptr_type_node
, void_type_node
,
6696 alpha_builtin_function ("__builtin_revert_vms_condition_handler", ftype
,
6697 ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER
, 0);
6700 alpha_v8qi_u
= build_vector_type (unsigned_intQI_type_node
, 8);
6701 alpha_v8qi_s
= build_vector_type (intQI_type_node
, 8);
6702 alpha_v4hi_u
= build_vector_type (unsigned_intHI_type_node
, 4);
6703 alpha_v4hi_s
= build_vector_type (intHI_type_node
, 4);
6706 /* Expand an expression EXP that calls a built-in function,
6707 with result going to TARGET if that's convenient
6708 (and in mode MODE if that's convenient).
6709 SUBTARGET may be used as the target for computing one of EXP's operands.
6710 IGNORE is nonzero if the value is to be ignored. */
6713 alpha_expand_builtin (tree exp
, rtx target
,
6714 rtx subtarget ATTRIBUTE_UNUSED
,
6715 enum machine_mode mode ATTRIBUTE_UNUSED
,
6716 int ignore ATTRIBUTE_UNUSED
)
6720 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
6721 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6723 call_expr_arg_iterator iter
;
6724 enum insn_code icode
;
6725 rtx op
[MAX_ARGS
], pat
;
6729 if (fcode
>= ALPHA_BUILTIN_max
)
6730 internal_error ("bad builtin fcode");
6731 icode
= code_for_builtin
[fcode
];
6733 internal_error ("bad builtin fcode");
6735 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6738 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
6740 const struct insn_operand_data
*insn_op
;
6742 if (arg
== error_mark_node
)
6744 if (arity
> MAX_ARGS
)
6747 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6749 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
6751 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6752 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6758 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6760 || GET_MODE (target
) != tmode
6761 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6762 target
= gen_reg_rtx (tmode
);
6768 pat
= GEN_FCN (icode
) (target
);
6772 pat
= GEN_FCN (icode
) (target
, op
[0]);
6774 pat
= GEN_FCN (icode
) (op
[0]);
6777 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6793 /* Several bits below assume HWI >= 64 bits. This should be enforced
6795 #if HOST_BITS_PER_WIDE_INT < 64
6796 # error "HOST_WIDE_INT too small"
6799 /* Fold the builtin for the CMPBGE instruction. This is a vector comparison
6800 with an 8-bit output vector. OPINT contains the integer operands; bit N
6801 of OP_CONST is set if OPINT[N] is valid. */
6804 alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint
[], long op_const
)
6809 for (i
= 0, val
= 0; i
< 8; ++i
)
6811 unsigned HOST_WIDE_INT c0
= (opint
[0] >> (i
* 8)) & 0xff;
6812 unsigned HOST_WIDE_INT c1
= (opint
[1] >> (i
* 8)) & 0xff;
6816 return build_int_cst (long_integer_type_node
, val
);
6818 else if (op_const
== 2 && opint
[1] == 0)
6819 return build_int_cst (long_integer_type_node
, 0xff);
6823 /* Fold the builtin for the ZAPNOT instruction. This is essentially a
6824 specialized form of an AND operation. Other byte manipulation instructions
6825 are defined in terms of this instruction, so this is also used as a
6826 subroutine for other builtins.
6828 OP contains the tree operands; OPINT contains the extracted integer values.
6829 Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only
6830 OPINT may be considered. */
6833 alpha_fold_builtin_zapnot (tree
*op
, unsigned HOST_WIDE_INT opint
[],
6838 unsigned HOST_WIDE_INT mask
= 0;
6841 for (i
= 0; i
< 8; ++i
)
6842 if ((opint
[1] >> i
) & 1)
6843 mask
|= (unsigned HOST_WIDE_INT
)0xff << (i
* 8);
6846 return build_int_cst (long_integer_type_node
, opint
[0] & mask
);
6849 return fold_build2 (BIT_AND_EXPR
, long_integer_type_node
, op
[0],
6850 build_int_cst (long_integer_type_node
, mask
));
6852 else if ((op_const
& 1) && opint
[0] == 0)
6853 return build_int_cst (long_integer_type_node
, 0);
6857 /* Fold the builtins for the EXT family of instructions. */
6860 alpha_fold_builtin_extxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6861 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6865 tree
*zap_op
= NULL
;
6869 unsigned HOST_WIDE_INT loc
;
6872 if (BYTES_BIG_ENDIAN
)
6880 unsigned HOST_WIDE_INT temp
= opint
[0];
6893 opint
[1] = bytemask
;
6894 return alpha_fold_builtin_zapnot (zap_op
, opint
, zap_const
);
6897 /* Fold the builtins for the INS family of instructions. */
6900 alpha_fold_builtin_insxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6901 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6904 if ((op_const
& 1) && opint
[0] == 0)
6905 return build_int_cst (long_integer_type_node
, 0);
6909 unsigned HOST_WIDE_INT temp
, loc
, byteloc
;
6910 tree
*zap_op
= NULL
;
6913 if (BYTES_BIG_ENDIAN
)
6920 byteloc
= (64 - (loc
* 8)) & 0x3f;
6937 opint
[1] = bytemask
;
6938 return alpha_fold_builtin_zapnot (zap_op
, opint
, op_const
);
6945 alpha_fold_builtin_mskxx (tree op
[], unsigned HOST_WIDE_INT opint
[],
6946 long op_const
, unsigned HOST_WIDE_INT bytemask
,
6951 unsigned HOST_WIDE_INT loc
;
6954 if (BYTES_BIG_ENDIAN
)
6961 opint
[1] = bytemask
^ 0xff;
6964 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
6968 alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint
[], long op_const
)
6974 unsigned HOST_WIDE_INT l
;
6977 mul_double (opint
[0], 0, opint
[1], 0, &l
, &h
);
6979 #if HOST_BITS_PER_WIDE_INT > 64
6983 return build_int_cst (long_integer_type_node
, h
);
6987 opint
[1] = opint
[0];
6990 /* Note that (X*1) >> 64 == 0. */
6991 if (opint
[1] == 0 || opint
[1] == 1)
6992 return build_int_cst (long_integer_type_node
, 0);
6999 alpha_fold_vector_minmax (enum tree_code code
, tree op
[], tree vtype
)
7001 tree op0
= fold_convert (vtype
, op
[0]);
7002 tree op1
= fold_convert (vtype
, op
[1]);
7003 tree val
= fold_build2 (code
, vtype
, op0
, op1
);
7004 return fold_build1 (VIEW_CONVERT_EXPR
, long_integer_type_node
, val
);
7008 alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint
[], long op_const
)
7010 unsigned HOST_WIDE_INT temp
= 0;
7016 for (i
= 0; i
< 8; ++i
)
7018 unsigned HOST_WIDE_INT a
= (opint
[0] >> (i
* 8)) & 0xff;
7019 unsigned HOST_WIDE_INT b
= (opint
[1] >> (i
* 8)) & 0xff;
7026 return build_int_cst (long_integer_type_node
, temp
);
7030 alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint
[], long op_const
)
7032 unsigned HOST_WIDE_INT temp
;
7037 temp
= opint
[0] & 0xff;
7038 temp
|= (opint
[0] >> 24) & 0xff00;
7040 return build_int_cst (long_integer_type_node
, temp
);
7044 alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint
[], long op_const
)
7046 unsigned HOST_WIDE_INT temp
;
7051 temp
= opint
[0] & 0xff;
7052 temp
|= (opint
[0] >> 8) & 0xff00;
7053 temp
|= (opint
[0] >> 16) & 0xff0000;
7054 temp
|= (opint
[0] >> 24) & 0xff000000;
7056 return build_int_cst (long_integer_type_node
, temp
);
7060 alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint
[], long op_const
)
7062 unsigned HOST_WIDE_INT temp
;
7067 temp
= opint
[0] & 0xff;
7068 temp
|= (opint
[0] & 0xff00) << 24;
7070 return build_int_cst (long_integer_type_node
, temp
);
7074 alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint
[], long op_const
)
7076 unsigned HOST_WIDE_INT temp
;
7081 temp
= opint
[0] & 0xff;
7082 temp
|= (opint
[0] & 0x0000ff00) << 8;
7083 temp
|= (opint
[0] & 0x00ff0000) << 16;
7084 temp
|= (opint
[0] & 0xff000000) << 24;
7086 return build_int_cst (long_integer_type_node
, temp
);
7090 alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint
[], long op_const
)
7092 unsigned HOST_WIDE_INT temp
;
7100 temp
= exact_log2 (opint
[0] & -opint
[0]);
7102 return build_int_cst (long_integer_type_node
, temp
);
7106 alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint
[], long op_const
)
7108 unsigned HOST_WIDE_INT temp
;
7116 temp
= 64 - floor_log2 (opint
[0]) - 1;
7118 return build_int_cst (long_integer_type_node
, temp
);
7122 alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint
[], long op_const
)
7124 unsigned HOST_WIDE_INT temp
, op
;
7132 temp
++, op
&= op
- 1;
7134 return build_int_cst (long_integer_type_node
, temp
);
7137 /* Fold one of our builtin functions. */
7140 alpha_fold_builtin (tree fndecl
, int n_args
, tree
*op
,
7141 bool ignore ATTRIBUTE_UNUSED
)
7143 unsigned HOST_WIDE_INT opint
[MAX_ARGS
];
7147 if (n_args
>= MAX_ARGS
)
7150 for (i
= 0; i
< n_args
; i
++)
7153 if (arg
== error_mark_node
)
7157 if (TREE_CODE (arg
) == INTEGER_CST
)
7159 op_const
|= 1L << i
;
7160 opint
[i
] = int_cst_value (arg
);
7164 switch (DECL_FUNCTION_CODE (fndecl
))
7166 case ALPHA_BUILTIN_CMPBGE
:
7167 return alpha_fold_builtin_cmpbge (opint
, op_const
);
7169 case ALPHA_BUILTIN_EXTBL
:
7170 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x01, false);
7171 case ALPHA_BUILTIN_EXTWL
:
7172 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, false);
7173 case ALPHA_BUILTIN_EXTLL
:
7174 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, false);
7175 case ALPHA_BUILTIN_EXTQL
:
7176 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, false);
7177 case ALPHA_BUILTIN_EXTWH
:
7178 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x03, true);
7179 case ALPHA_BUILTIN_EXTLH
:
7180 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0x0f, true);
7181 case ALPHA_BUILTIN_EXTQH
:
7182 return alpha_fold_builtin_extxx (op
, opint
, op_const
, 0xff, true);
7184 case ALPHA_BUILTIN_INSBL
:
7185 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x01, false);
7186 case ALPHA_BUILTIN_INSWL
:
7187 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, false);
7188 case ALPHA_BUILTIN_INSLL
:
7189 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, false);
7190 case ALPHA_BUILTIN_INSQL
:
7191 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, false);
7192 case ALPHA_BUILTIN_INSWH
:
7193 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x03, true);
7194 case ALPHA_BUILTIN_INSLH
:
7195 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0x0f, true);
7196 case ALPHA_BUILTIN_INSQH
:
7197 return alpha_fold_builtin_insxx (op
, opint
, op_const
, 0xff, true);
7199 case ALPHA_BUILTIN_MSKBL
:
7200 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x01, false);
7201 case ALPHA_BUILTIN_MSKWL
:
7202 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, false);
7203 case ALPHA_BUILTIN_MSKLL
:
7204 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, false);
7205 case ALPHA_BUILTIN_MSKQL
:
7206 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, false);
7207 case ALPHA_BUILTIN_MSKWH
:
7208 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x03, true);
7209 case ALPHA_BUILTIN_MSKLH
:
7210 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0x0f, true);
7211 case ALPHA_BUILTIN_MSKQH
:
7212 return alpha_fold_builtin_mskxx (op
, opint
, op_const
, 0xff, true);
7214 case ALPHA_BUILTIN_UMULH
:
7215 return alpha_fold_builtin_umulh (opint
, op_const
);
7217 case ALPHA_BUILTIN_ZAP
:
7220 case ALPHA_BUILTIN_ZAPNOT
:
7221 return alpha_fold_builtin_zapnot (op
, opint
, op_const
);
7223 case ALPHA_BUILTIN_MINUB8
:
7224 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_u
);
7225 case ALPHA_BUILTIN_MINSB8
:
7226 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v8qi_s
);
7227 case ALPHA_BUILTIN_MINUW4
:
7228 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_u
);
7229 case ALPHA_BUILTIN_MINSW4
:
7230 return alpha_fold_vector_minmax (MIN_EXPR
, op
, alpha_v4hi_s
);
7231 case ALPHA_BUILTIN_MAXUB8
:
7232 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_u
);
7233 case ALPHA_BUILTIN_MAXSB8
:
7234 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v8qi_s
);
7235 case ALPHA_BUILTIN_MAXUW4
:
7236 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_u
);
7237 case ALPHA_BUILTIN_MAXSW4
:
7238 return alpha_fold_vector_minmax (MAX_EXPR
, op
, alpha_v4hi_s
);
7240 case ALPHA_BUILTIN_PERR
:
7241 return alpha_fold_builtin_perr (opint
, op_const
);
7242 case ALPHA_BUILTIN_PKLB
:
7243 return alpha_fold_builtin_pklb (opint
, op_const
);
7244 case ALPHA_BUILTIN_PKWB
:
7245 return alpha_fold_builtin_pkwb (opint
, op_const
);
7246 case ALPHA_BUILTIN_UNPKBL
:
7247 return alpha_fold_builtin_unpkbl (opint
, op_const
);
7248 case ALPHA_BUILTIN_UNPKBW
:
7249 return alpha_fold_builtin_unpkbw (opint
, op_const
);
7251 case ALPHA_BUILTIN_CTTZ
:
7252 return alpha_fold_builtin_cttz (opint
, op_const
);
7253 case ALPHA_BUILTIN_CTLZ
:
7254 return alpha_fold_builtin_ctlz (opint
, op_const
);
7255 case ALPHA_BUILTIN_CTPOP
:
7256 return alpha_fold_builtin_ctpop (opint
, op_const
);
7258 case ALPHA_BUILTIN_AMASK
:
7259 case ALPHA_BUILTIN_IMPLVER
:
7260 case ALPHA_BUILTIN_RPCC
:
7261 case ALPHA_BUILTIN_THREAD_POINTER
:
7262 case ALPHA_BUILTIN_SET_THREAD_POINTER
:
7263 /* None of these are foldable at compile-time. */
7269 /* This page contains routines that are used to determine what the function
7270 prologue and epilogue code will do and write them out. */
7272 /* Compute the size of the save area in the stack. */
7274 /* These variables are used for communication between the following functions.
7275 They indicate various things about the current function being compiled
7276 that are used to tell what kind of prologue, epilogue and procedure
7277 descriptor to generate. */
7279 /* Nonzero if we need a stack procedure. */
7280 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
7281 static enum alpha_procedure_types alpha_procedure_type
;
7283 /* Register number (either FP or SP) that is used to unwind the frame. */
7284 static int vms_unwind_regno
;
7286 /* Register number used to save FP. We need not have one for RA since
7287 we don't modify it for register procedures. This is only defined
7288 for register frame procedures. */
7289 static int vms_save_fp_regno
;
7291 /* Register number used to reference objects off our PV. */
7292 static int vms_base_regno
;
7294 /* Compute register masks for saved registers. */
7297 alpha_sa_mask (unsigned long *imaskP
, unsigned long *fmaskP
)
7299 unsigned long imask
= 0;
7300 unsigned long fmask
= 0;
7303 /* When outputting a thunk, we don't have valid register life info,
7304 but assemble_start_function wants to output .frame and .mask
7313 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7314 imask
|= (1UL << HARD_FRAME_POINTER_REGNUM
);
7316 /* One for every register we have to save. */
7317 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
7318 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
7319 && df_regs_ever_live_p (i
) && i
!= REG_RA
7320 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
7323 imask
|= (1UL << i
);
7325 fmask
|= (1UL << (i
- 32));
7328 /* We need to restore these for the handler. */
7329 if (crtl
->calls_eh_return
)
7333 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
7334 if (regno
== INVALID_REGNUM
)
7336 imask
|= 1UL << regno
;
7340 /* If any register spilled, then spill the return address also. */
7341 /* ??? This is required by the Digital stack unwind specification
7342 and isn't needed if we're doing Dwarf2 unwinding. */
7343 if (imask
|| fmask
|| alpha_ra_ever_killed ())
7344 imask
|= (1UL << REG_RA
);
7351 alpha_sa_size (void)
7353 unsigned long mask
[2];
7357 alpha_sa_mask (&mask
[0], &mask
[1]);
7359 if (TARGET_ABI_UNICOSMK
)
7361 if (mask
[0] || mask
[1])
7366 for (j
= 0; j
< 2; ++j
)
7367 for (i
= 0; i
< 32; ++i
)
7368 if ((mask
[j
] >> i
) & 1)
7372 if (TARGET_ABI_UNICOSMK
)
7374 /* We might not need to generate a frame if we don't make any calls
7375 (including calls to __T3E_MISMATCH if this is a vararg function),
7376 don't have any local variables which require stack slots, don't
7377 use alloca and have not determined that we need a frame for other
7380 alpha_procedure_type
7381 = (sa_size
|| get_frame_size() != 0
7382 || crtl
->outgoing_args_size
7383 || cfun
->stdarg
|| cfun
->calls_alloca
7384 || frame_pointer_needed
)
7385 ? PT_STACK
: PT_REGISTER
;
7387 /* Always reserve space for saving callee-saved registers if we
7388 need a frame as required by the calling convention. */
7389 if (alpha_procedure_type
== PT_STACK
)
7392 else if (TARGET_ABI_OPEN_VMS
)
7394 /* Start with a stack procedure if we make any calls (REG_RA used), or
7395 need a frame pointer, with a register procedure if we otherwise need
7396 at least a slot, and with a null procedure in other cases. */
7397 if ((mask
[0] >> REG_RA
) & 1 || frame_pointer_needed
)
7398 alpha_procedure_type
= PT_STACK
;
7399 else if (get_frame_size() != 0)
7400 alpha_procedure_type
= PT_REGISTER
;
7402 alpha_procedure_type
= PT_NULL
;
7404 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7405 made the final decision on stack procedure vs register procedure. */
7406 if (alpha_procedure_type
== PT_STACK
)
7409 /* Decide whether to refer to objects off our PV via FP or PV.
7410 If we need FP for something else or if we receive a nonlocal
7411 goto (which expects PV to contain the value), we must use PV.
7412 Otherwise, start by assuming we can use FP. */
7415 = (frame_pointer_needed
7416 || cfun
->has_nonlocal_label
7417 || alpha_procedure_type
== PT_STACK
7418 || crtl
->outgoing_args_size
)
7419 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
7421 /* If we want to copy PV into FP, we need to find some register
7422 in which to save FP. */
7424 vms_save_fp_regno
= -1;
7425 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
7426 for (i
= 0; i
< 32; i
++)
7427 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! df_regs_ever_live_p (i
))
7428 vms_save_fp_regno
= i
;
7430 /* A VMS condition handler requires a stack procedure in our
7431 implementation. (not required by the calling standard). */
7432 if ((vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
7433 || cfun
->machine
->uses_condition_handler
)
7434 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
7435 else if (alpha_procedure_type
== PT_NULL
)
7436 vms_base_regno
= REG_PV
;
7438 /* Stack unwinding should be done via FP unless we use it for PV. */
7439 vms_unwind_regno
= (vms_base_regno
== REG_PV
7440 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
7442 /* If this is a stack procedure, allow space for saving FP, RA and
7443 a condition handler slot if needed. */
7444 if (alpha_procedure_type
== PT_STACK
)
7445 sa_size
+= 2 + cfun
->machine
->uses_condition_handler
;
7449 /* Our size must be even (multiple of 16 bytes). */
7457 /* Define the offset between two registers, one to be eliminated,
7458 and the other its replacement, at the start of a routine. */
7461 alpha_initial_elimination_offset (unsigned int from
,
7462 unsigned int to ATTRIBUTE_UNUSED
)
7466 ret
= alpha_sa_size ();
7467 ret
+= ALPHA_ROUND (crtl
->outgoing_args_size
);
7471 case FRAME_POINTER_REGNUM
:
7474 case ARG_POINTER_REGNUM
:
7475 ret
+= (ALPHA_ROUND (get_frame_size ()
7476 + crtl
->args
.pretend_args_size
)
7477 - crtl
->args
.pretend_args_size
);
7487 #if TARGET_ABI_OPEN_VMS
7489 /* Worker function for TARGET_CAN_ELIMINATE. */
7492 alpha_vms_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
7494 /* We need the alpha_procedure_type to decide. Evaluate it now. */
7497 switch (alpha_procedure_type
)
7500 /* NULL procedures have no frame of their own and we only
7501 know how to resolve from the current stack pointer. */
7502 return to
== STACK_POINTER_REGNUM
;
7506 /* We always eliminate except to the stack pointer if there is no
7507 usable frame pointer at hand. */
7508 return (to
!= STACK_POINTER_REGNUM
7509 || vms_unwind_regno
!= HARD_FRAME_POINTER_REGNUM
);
7515 /* FROM is to be eliminated for TO. Return the offset so that TO+offset
7516 designates the same location as FROM. */
7519 alpha_vms_initial_elimination_offset (unsigned int from
, unsigned int to
)
7521 /* The only possible attempts we ever expect are ARG or FRAME_PTR to
7522 HARD_FRAME or STACK_PTR. We need the alpha_procedure_type to decide
7523 on the proper computations and will need the register save area size
7526 HOST_WIDE_INT sa_size
= alpha_sa_size ();
7528 /* PT_NULL procedures have no frame of their own and we only allow
7529 elimination to the stack pointer. This is the argument pointer and we
7530 resolve the soft frame pointer to that as well. */
7532 if (alpha_procedure_type
== PT_NULL
)
7535 /* For a PT_STACK procedure the frame layout looks as follows
7537 -----> decreasing addresses
7539 < size rounded up to 16 | likewise >
7540 --------------#------------------------------+++--------------+++-------#
7541 incoming args # pretended args | "frame" | regs sa | PV | outgoing args #
7542 --------------#---------------------------------------------------------#
7544 ARG_PTR FRAME_PTR HARD_FRAME_PTR STACK_PTR
7547 PT_REGISTER procedures are similar in that they may have a frame of their
7548 own. They have no regs-sa/pv/outgoing-args area.
7550 We first compute offset to HARD_FRAME_PTR, then add what we need to get
7551 to STACK_PTR if need be. */
7554 HOST_WIDE_INT offset
;
7555 HOST_WIDE_INT pv_save_size
= alpha_procedure_type
== PT_STACK
? 8 : 0;
7559 case FRAME_POINTER_REGNUM
:
7560 offset
= ALPHA_ROUND (sa_size
+ pv_save_size
);
7562 case ARG_POINTER_REGNUM
:
7563 offset
= (ALPHA_ROUND (sa_size
+ pv_save_size
7565 + crtl
->args
.pretend_args_size
)
7566 - crtl
->args
.pretend_args_size
);
7572 if (to
== STACK_POINTER_REGNUM
)
7573 offset
+= ALPHA_ROUND (crtl
->outgoing_args_size
);
7579 #define COMMON_OBJECT "common_object"
7582 common_object_handler (tree
*node
, tree name ATTRIBUTE_UNUSED
,
7583 tree args ATTRIBUTE_UNUSED
, int flags ATTRIBUTE_UNUSED
,
7584 bool *no_add_attrs ATTRIBUTE_UNUSED
)
7587 gcc_assert (DECL_P (decl
));
7589 DECL_COMMON (decl
) = 1;
7593 static const struct attribute_spec vms_attribute_table
[] =
7595 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
7596 affects_type_identity } */
7597 { COMMON_OBJECT
, 0, 1, true, false, false, common_object_handler
, false },
7598 { NULL
, 0, 0, false, false, false, NULL
, false }
7602 vms_output_aligned_decl_common(FILE *file
, tree decl
, const char *name
,
7603 unsigned HOST_WIDE_INT size
,
7606 tree attr
= DECL_ATTRIBUTES (decl
);
7607 fprintf (file
, "%s", COMMON_ASM_OP
);
7608 assemble_name (file
, name
);
7609 fprintf (file
, "," HOST_WIDE_INT_PRINT_UNSIGNED
, size
);
7610 /* ??? Unlike on OSF/1, the alignment factor is not in log units. */
7611 fprintf (file
, ",%u", align
/ BITS_PER_UNIT
);
7614 attr
= lookup_attribute (COMMON_OBJECT
, attr
);
7616 fprintf (file
, ",%s",
7617 IDENTIFIER_POINTER (TREE_VALUE (TREE_VALUE (attr
))));
7622 #undef COMMON_OBJECT
7627 find_lo_sum_using_gp (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
7629 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7633 alpha_find_lo_sum_using_gp (rtx insn
)
7635 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7639 alpha_does_function_need_gp (void)
7643 /* The GP being variable is an OSF abi thing. */
7644 if (! TARGET_ABI_OSF
)
7647 /* We need the gp to load the address of __mcount. */
7648 if (TARGET_PROFILING_NEEDS_GP
&& crtl
->profile
)
7651 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7655 /* The nonlocal receiver pattern assumes that the gp is valid for
7656 the nested function. Reasonable because it's almost always set
7657 correctly already. For the cases where that's wrong, make sure
7658 the nested function loads its gp on entry. */
7659 if (crtl
->has_nonlocal_goto
)
7662 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7663 Even if we are a static function, we still need to do this in case
7664 our address is taken and passed to something like qsort. */
7666 push_topmost_sequence ();
7667 insn
= get_insns ();
7668 pop_topmost_sequence ();
7670 for (; insn
; insn
= NEXT_INSN (insn
))
7671 if (NONDEBUG_INSN_P (insn
)
7672 && ! JUMP_TABLE_DATA_P (insn
)
7673 && GET_CODE (PATTERN (insn
)) != USE
7674 && GET_CODE (PATTERN (insn
)) != CLOBBER
7675 && get_attr_usegp (insn
))
7682 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7686 set_frame_related_p (void)
7688 rtx seq
= get_insns ();
7699 while (insn
!= NULL_RTX
)
7701 RTX_FRAME_RELATED_P (insn
) = 1;
7702 insn
= NEXT_INSN (insn
);
7704 seq
= emit_insn (seq
);
7708 seq
= emit_insn (seq
);
7709 RTX_FRAME_RELATED_P (seq
) = 1;
7714 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7716 /* Generates a store with the proper unwind info attached. VALUE is
7717 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
7718 contains SP+FRAME_BIAS, and that is the unwind info that should be
7719 generated. If FRAME_REG != VALUE, then VALUE is being stored on
7720 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
7723 emit_frame_store_1 (rtx value
, rtx base_reg
, HOST_WIDE_INT frame_bias
,
7724 HOST_WIDE_INT base_ofs
, rtx frame_reg
)
7726 rtx addr
, mem
, insn
;
7728 addr
= plus_constant (base_reg
, base_ofs
);
7729 mem
= gen_rtx_MEM (DImode
, addr
);
7730 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7732 insn
= emit_move_insn (mem
, value
);
7733 RTX_FRAME_RELATED_P (insn
) = 1;
7735 if (frame_bias
|| value
!= frame_reg
)
7739 addr
= plus_constant (stack_pointer_rtx
, frame_bias
+ base_ofs
);
7740 mem
= gen_rtx_MEM (DImode
, addr
);
7743 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
7744 gen_rtx_SET (VOIDmode
, mem
, frame_reg
));
7749 emit_frame_store (unsigned int regno
, rtx base_reg
,
7750 HOST_WIDE_INT frame_bias
, HOST_WIDE_INT base_ofs
)
7752 rtx reg
= gen_rtx_REG (DImode
, regno
);
7753 emit_frame_store_1 (reg
, base_reg
, frame_bias
, base_ofs
, reg
);
7756 /* Compute the frame size. SIZE is the size of the "naked" frame
7757 and SA_SIZE is the size of the register save area. */
7759 static HOST_WIDE_INT
7760 compute_frame_size (HOST_WIDE_INT size
, HOST_WIDE_INT sa_size
)
7762 if (TARGET_ABI_OPEN_VMS
)
7763 return ALPHA_ROUND (sa_size
7764 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7766 + crtl
->args
.pretend_args_size
);
7767 else if (TARGET_ABI_UNICOSMK
)
7768 /* We have to allocate space for the DSIB if we generate a frame. */
7769 return ALPHA_ROUND (sa_size
7770 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7772 + crtl
->outgoing_args_size
);
7774 return ALPHA_ROUND (crtl
->outgoing_args_size
)
7777 + crtl
->args
.pretend_args_size
);
7780 /* Write function prologue. */
7782 /* On vms we have two kinds of functions:
7784 - stack frame (PROC_STACK)
7785 these are 'normal' functions with local vars and which are
7786 calling other functions
7787 - register frame (PROC_REGISTER)
7788 keeps all data in registers, needs no stack
7790 We must pass this to the assembler so it can generate the
7791 proper pdsc (procedure descriptor)
7792 This is done with the '.pdesc' command.
7794 On not-vms, we don't really differentiate between the two, as we can
7795 simply allocate stack without saving registers. */
7798 alpha_expand_prologue (void)
7800 /* Registers to save. */
7801 unsigned long imask
= 0;
7802 unsigned long fmask
= 0;
7803 /* Stack space needed for pushing registers clobbered by us. */
7804 HOST_WIDE_INT sa_size
;
7805 /* Complete stack size needed. */
7806 HOST_WIDE_INT frame_size
;
7807 /* Probed stack size; it additionally includes the size of
7808 the "reserve region" if any. */
7809 HOST_WIDE_INT probed_size
;
7810 /* Offset from base reg to register save area. */
7811 HOST_WIDE_INT reg_offset
;
7815 sa_size
= alpha_sa_size ();
7816 frame_size
= compute_frame_size (get_frame_size (), sa_size
);
7818 if (flag_stack_usage
)
7819 current_function_static_stack_size
= frame_size
;
7821 if (TARGET_ABI_OPEN_VMS
)
7822 reg_offset
= 8 + 8 * cfun
->machine
->uses_condition_handler
;
7824 reg_offset
= ALPHA_ROUND (crtl
->outgoing_args_size
);
7826 alpha_sa_mask (&imask
, &fmask
);
7828 /* Emit an insn to reload GP, if needed. */
7831 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7832 if (alpha_function_needs_gp
)
7833 emit_insn (gen_prologue_ldgp ());
7836 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7837 the call to mcount ourselves, rather than having the linker do it
7838 magically in response to -pg. Since _mcount has special linkage,
7839 don't represent the call as a call. */
7840 if (TARGET_PROFILING_NEEDS_GP
&& crtl
->profile
)
7841 emit_insn (gen_prologue_mcount ());
7843 if (TARGET_ABI_UNICOSMK
)
7844 unicosmk_gen_dsib (&imask
);
7846 /* Adjust the stack by the frame size. If the frame size is > 4096
7847 bytes, we need to be sure we probe somewhere in the first and last
7848 4096 bytes (we can probably get away without the latter test) and
7849 every 8192 bytes in between. If the frame size is > 32768, we
7850 do this in a loop. Otherwise, we generate the explicit probe
7853 Note that we are only allowed to adjust sp once in the prologue. */
7855 probed_size
= frame_size
;
7856 if (flag_stack_check
)
7857 probed_size
+= STACK_CHECK_PROTECT
;
7859 if (probed_size
<= 32768)
7861 if (probed_size
> 4096)
7865 for (probed
= 4096; probed
< probed_size
; probed
+= 8192)
7866 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7870 /* We only have to do this probe if we aren't saving registers or
7871 if we are probing beyond the frame because of -fstack-check. */
7872 if ((sa_size
== 0 && probed_size
> probed
- 4096)
7873 || flag_stack_check
)
7874 emit_insn (gen_probe_stack (GEN_INT (-probed_size
)));
7877 if (frame_size
!= 0)
7878 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7879 GEN_INT (TARGET_ABI_UNICOSMK
7885 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7886 number of 8192 byte blocks to probe. We then probe each block
7887 in the loop and then set SP to the proper location. If the
7888 amount remaining is > 4096, we have to do one more probe if we
7889 are not saving any registers or if we are probing beyond the
7890 frame because of -fstack-check. */
7892 HOST_WIDE_INT blocks
= (probed_size
+ 4096) / 8192;
7893 HOST_WIDE_INT leftover
= probed_size
+ 4096 - blocks
* 8192;
7894 rtx ptr
= gen_rtx_REG (DImode
, 22);
7895 rtx count
= gen_rtx_REG (DImode
, 23);
7898 emit_move_insn (count
, GEN_INT (blocks
));
7899 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7900 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7902 /* Because of the difficulty in emitting a new basic block this
7903 late in the compilation, generate the loop as a single insn. */
7904 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7906 if ((leftover
> 4096 && sa_size
== 0) || flag_stack_check
)
7908 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7909 MEM_VOLATILE_P (last
) = 1;
7910 emit_move_insn (last
, const0_rtx
);
7913 if (TARGET_ABI_WINDOWS_NT
|| flag_stack_check
)
7915 /* For NT stack unwind (done by 'reverse execution'), it's
7916 not OK to take the result of a loop, even though the value
7917 is already in ptr, so we reload it via a single operation
7918 and subtract it to sp.
7920 Same if -fstack-check is specified, because the probed stack
7921 size is not equal to the frame size.
7923 Yes, that's correct -- we have to reload the whole constant
7924 into a temporary via ldah+lda then subtract from sp. */
7926 HOST_WIDE_INT lo
, hi
;
7927 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7928 hi
= frame_size
- lo
;
7930 emit_move_insn (ptr
, GEN_INT (hi
));
7931 emit_insn (gen_adddi3 (ptr
, ptr
, GEN_INT (lo
)));
7932 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7937 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7938 GEN_INT (-leftover
)));
7941 /* This alternative is special, because the DWARF code cannot
7942 possibly intuit through the loop above. So we invent this
7943 note it looks at instead. */
7944 RTX_FRAME_RELATED_P (seq
) = 1;
7945 add_reg_note (seq
, REG_FRAME_RELATED_EXPR
,
7946 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7947 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7948 GEN_INT (TARGET_ABI_UNICOSMK
7953 if (!TARGET_ABI_UNICOSMK
)
7955 HOST_WIDE_INT sa_bias
= 0;
7957 /* Cope with very large offsets to the register save area. */
7958 sa_reg
= stack_pointer_rtx
;
7959 if (reg_offset
+ sa_size
> 0x8000)
7961 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7964 if (low
+ sa_size
<= 0x8000)
7965 sa_bias
= reg_offset
- low
, reg_offset
= low
;
7967 sa_bias
= reg_offset
, reg_offset
= 0;
7969 sa_reg
= gen_rtx_REG (DImode
, 24);
7970 sa_bias_rtx
= GEN_INT (sa_bias
);
7972 if (add_operand (sa_bias_rtx
, DImode
))
7973 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_bias_rtx
));
7976 emit_move_insn (sa_reg
, sa_bias_rtx
);
7977 emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
, sa_reg
));
7981 /* Save regs in stack order. Beginning with VMS PV. */
7982 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7983 emit_frame_store (REG_PV
, stack_pointer_rtx
, 0, 0);
7985 /* Save register RA next. */
7986 if (imask
& (1UL << REG_RA
))
7988 emit_frame_store (REG_RA
, sa_reg
, sa_bias
, reg_offset
);
7989 imask
&= ~(1UL << REG_RA
);
7993 /* Now save any other registers required to be saved. */
7994 for (i
= 0; i
< 31; i
++)
7995 if (imask
& (1UL << i
))
7997 emit_frame_store (i
, sa_reg
, sa_bias
, reg_offset
);
8001 for (i
= 0; i
< 31; i
++)
8002 if (fmask
& (1UL << i
))
8004 emit_frame_store (i
+32, sa_reg
, sa_bias
, reg_offset
);
8008 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
8010 /* The standard frame on the T3E includes space for saving registers.
8011 We just have to use it. We don't have to save the return address and
8012 the old frame pointer here - they are saved in the DSIB. */
8015 for (i
= 9; i
< 15; i
++)
8016 if (imask
& (1UL << i
))
8018 emit_frame_store (i
, hard_frame_pointer_rtx
, 0, reg_offset
);
8021 for (i
= 2; i
< 10; i
++)
8022 if (fmask
& (1UL << i
))
8024 emit_frame_store (i
+32, hard_frame_pointer_rtx
, 0, reg_offset
);
8029 if (TARGET_ABI_OPEN_VMS
)
8031 /* Register frame procedures save the fp. */
8032 if (alpha_procedure_type
== PT_REGISTER
)
8034 rtx insn
= emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
8035 hard_frame_pointer_rtx
);
8036 add_reg_note (insn
, REG_CFA_REGISTER
, NULL
);
8037 RTX_FRAME_RELATED_P (insn
) = 1;
8040 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
8041 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
8042 gen_rtx_REG (DImode
, REG_PV
)));
8044 if (alpha_procedure_type
!= PT_NULL
8045 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
8046 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
8048 /* If we have to allocate space for outgoing args, do it now. */
8049 if (crtl
->outgoing_args_size
!= 0)
8052 = emit_move_insn (stack_pointer_rtx
,
8054 (hard_frame_pointer_rtx
,
8056 (crtl
->outgoing_args_size
))));
8058 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
8059 if ! frame_pointer_needed. Setting the bit will change the CFA
8060 computation rule to use sp again, which would be wrong if we had
8061 frame_pointer_needed, as this means sp might move unpredictably
8065 frame_pointer_needed
8066 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
8068 crtl->outgoing_args_size != 0
8069 => alpha_procedure_type != PT_NULL,
8071 so when we are not setting the bit here, we are guaranteed to
8072 have emitted an FRP frame pointer update just before. */
8073 RTX_FRAME_RELATED_P (seq
) = ! frame_pointer_needed
;
8076 else if (!TARGET_ABI_UNICOSMK
)
8078 /* If we need a frame pointer, set it from the stack pointer. */
8079 if (frame_pointer_needed
)
8081 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
8082 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
8084 /* This must always be the last instruction in the
8085 prologue, thus we emit a special move + clobber. */
8086 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
8087 stack_pointer_rtx
, sa_reg
)));
8091 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
8092 the prologue, for exception handling reasons, we cannot do this for
8093 any insn that might fault. We could prevent this for mems with a
8094 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
8095 have to prevent all such scheduling with a blockage.
8097 Linux, on the other hand, never bothered to implement OSF/1's
8098 exception handling, and so doesn't care about such things. Anyone
8099 planning to use dwarf2 frame-unwind info can also omit the blockage. */
8101 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
8102 emit_insn (gen_blockage ());
8105 /* Count the number of .file directives, so that .loc is up to date. */
8106 int num_source_filenames
= 0;
8108 /* Output the textual info surrounding the prologue. */
8111 alpha_start_function (FILE *file
, const char *fnname
,
8112 tree decl ATTRIBUTE_UNUSED
)
8114 unsigned long imask
= 0;
8115 unsigned long fmask
= 0;
8116 /* Stack space needed for pushing registers clobbered by us. */
8117 HOST_WIDE_INT sa_size
;
8118 /* Complete stack size needed. */
8119 unsigned HOST_WIDE_INT frame_size
;
8120 /* The maximum debuggable frame size (512 Kbytes using Tru64 as). */
8121 unsigned HOST_WIDE_INT max_frame_size
= TARGET_ABI_OSF
&& !TARGET_GAS
8124 /* Offset from base reg to register save area. */
8125 HOST_WIDE_INT reg_offset
;
8126 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
8127 char *tramp_label
= (char *) alloca (strlen (fnname
) + 6);
8130 /* Don't emit an extern directive for functions defined in the same file. */
8131 if (TARGET_ABI_UNICOSMK
)
8134 name_tree
= get_identifier (fnname
);
8135 TREE_ASM_WRITTEN (name_tree
) = 1;
8138 #if TARGET_ABI_OPEN_VMS
8140 && strncmp (vms_debug_main
, fnname
, strlen (vms_debug_main
)) == 0)
8142 targetm
.asm_out
.globalize_label (asm_out_file
, VMS_DEBUG_MAIN_POINTER
);
8143 ASM_OUTPUT_DEF (asm_out_file
, VMS_DEBUG_MAIN_POINTER
, fnname
);
8144 switch_to_section (text_section
);
8145 vms_debug_main
= NULL
;
8149 alpha_fnname
= fnname
;
8150 sa_size
= alpha_sa_size ();
8151 frame_size
= compute_frame_size (get_frame_size (), sa_size
);
8153 if (TARGET_ABI_OPEN_VMS
)
8154 reg_offset
= 8 + 8 * cfun
->machine
->uses_condition_handler
;
8156 reg_offset
= ALPHA_ROUND (crtl
->outgoing_args_size
);
8158 alpha_sa_mask (&imask
, &fmask
);
8160 /* Ecoff can handle multiple .file directives, so put out file and lineno.
8161 We have to do that before the .ent directive as we cannot switch
8162 files within procedures with native ecoff because line numbers are
8163 linked to procedure descriptors.
8164 Outputting the lineno helps debugging of one line functions as they
8165 would otherwise get no line number at all. Please note that we would
8166 like to put out last_linenum from final.c, but it is not accessible. */
8168 if (write_symbols
== SDB_DEBUG
)
8170 #ifdef ASM_OUTPUT_SOURCE_FILENAME
8171 ASM_OUTPUT_SOURCE_FILENAME (file
,
8172 DECL_SOURCE_FILE (current_function_decl
));
8174 #ifdef SDB_OUTPUT_SOURCE_LINE
8175 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
8176 SDB_OUTPUT_SOURCE_LINE (file
,
8177 DECL_SOURCE_LINE (current_function_decl
));
8181 /* Issue function start and label. */
8182 if (TARGET_ABI_OPEN_VMS
8183 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
8185 fputs ("\t.ent ", file
);
8186 assemble_name (file
, fnname
);
8189 /* If the function needs GP, we'll write the "..ng" label there.
8190 Otherwise, do it here. */
8192 && ! alpha_function_needs_gp
8193 && ! cfun
->is_thunk
)
8196 assemble_name (file
, fnname
);
8197 fputs ("..ng:\n", file
);
8200 /* Nested functions on VMS that are potentially called via trampoline
8201 get a special transfer entry point that loads the called functions
8202 procedure descriptor and static chain. */
8203 if (TARGET_ABI_OPEN_VMS
8204 && !TREE_PUBLIC (decl
)
8205 && DECL_CONTEXT (decl
)
8206 && !TYPE_P (DECL_CONTEXT (decl
)))
8208 strcpy (tramp_label
, fnname
);
8209 strcat (tramp_label
, "..tr");
8210 ASM_OUTPUT_LABEL (file
, tramp_label
);
8211 fprintf (file
, "\tldq $1,24($27)\n");
8212 fprintf (file
, "\tldq $27,16($27)\n");
8215 strcpy (entry_label
, fnname
);
8216 if (TARGET_ABI_OPEN_VMS
)
8217 strcat (entry_label
, "..en");
8219 /* For public functions, the label must be globalized by appending an
8220 additional colon. */
8221 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
8222 strcat (entry_label
, ":");
8224 ASM_OUTPUT_LABEL (file
, entry_label
);
8225 inside_function
= TRUE
;
8227 if (TARGET_ABI_OPEN_VMS
)
8228 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
8230 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
8231 && !flag_inhibit_size_directive
)
8233 /* Set flags in procedure descriptor to request IEEE-conformant
8234 math-library routines. The value we set it to is PDSC_EXC_IEEE
8235 (/usr/include/pdsc.h). */
8236 fputs ("\t.eflag 48\n", file
);
8239 /* Set up offsets to alpha virtual arg/local debugging pointer. */
8240 alpha_auto_offset
= -frame_size
+ crtl
->args
.pretend_args_size
;
8241 alpha_arg_offset
= -frame_size
+ 48;
8243 /* Describe our frame. If the frame size is larger than an integer,
8244 print it as zero to avoid an assembler error. We won't be
8245 properly describing such a frame, but that's the best we can do. */
8246 if (TARGET_ABI_UNICOSMK
)
8248 else if (TARGET_ABI_OPEN_VMS
)
8249 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,"
8250 HOST_WIDE_INT_PRINT_DEC
"\n",
8252 frame_size
>= (1UL << 31) ? 0 : frame_size
,
8254 else if (!flag_inhibit_size_directive
)
8255 fprintf (file
, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC
",$26,%d\n",
8256 (frame_pointer_needed
8257 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
),
8258 frame_size
>= max_frame_size
? 0 : frame_size
,
8259 crtl
->args
.pretend_args_size
);
8261 /* Describe which registers were spilled. */
8262 if (TARGET_ABI_UNICOSMK
)
8264 else if (TARGET_ABI_OPEN_VMS
)
8267 /* ??? Does VMS care if mask contains ra? The old code didn't
8268 set it, so I don't here. */
8269 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1UL << REG_RA
));
8271 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
8272 if (alpha_procedure_type
== PT_REGISTER
)
8273 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
8275 else if (!flag_inhibit_size_directive
)
8279 fprintf (file
, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", imask
,
8280 frame_size
>= max_frame_size
? 0 : reg_offset
- frame_size
);
8282 for (i
= 0; i
< 32; ++i
)
8283 if (imask
& (1UL << i
))
8288 fprintf (file
, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC
"\n", fmask
,
8289 frame_size
>= max_frame_size
? 0 : reg_offset
- frame_size
);
8292 #if TARGET_ABI_OPEN_VMS
8293 /* If a user condition handler has been installed at some point, emit
8294 the procedure descriptor bits to point the Condition Handling Facility
8295 at the indirection wrapper, and state the fp offset at which the user
8296 handler may be found. */
8297 if (cfun
->machine
->uses_condition_handler
)
8299 fprintf (file
, "\t.handler __gcc_shell_handler\n");
8300 fprintf (file
, "\t.handler_data %d\n", VMS_COND_HANDLER_FP_OFFSET
);
8303 /* Ifdef'ed cause link_section are only available then. */
8304 switch_to_section (readonly_data_section
);
8305 fprintf (file
, "\t.align 3\n");
8306 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
8307 fputs ("\t.ascii \"", file
);
8308 assemble_name (file
, fnname
);
8309 fputs ("\\0\"\n", file
);
8310 alpha_need_linkage (fnname
, 1);
8311 switch_to_section (text_section
);
8315 /* Emit the .prologue note at the scheduled end of the prologue. */
8318 alpha_output_function_end_prologue (FILE *file
)
8320 if (TARGET_ABI_UNICOSMK
)
8322 else if (TARGET_ABI_OPEN_VMS
)
8323 fputs ("\t.prologue\n", file
);
8324 else if (TARGET_ABI_WINDOWS_NT
)
8325 fputs ("\t.prologue 0\n", file
);
8326 else if (!flag_inhibit_size_directive
)
8327 fprintf (file
, "\t.prologue %d\n",
8328 alpha_function_needs_gp
|| cfun
->is_thunk
);
8331 /* Write function epilogue. */
8334 alpha_expand_epilogue (void)
8336 /* Registers to save. */
8337 unsigned long imask
= 0;
8338 unsigned long fmask
= 0;
8339 /* Stack space needed for pushing registers clobbered by us. */
8340 HOST_WIDE_INT sa_size
;
8341 /* Complete stack size needed. */
8342 HOST_WIDE_INT frame_size
;
8343 /* Offset from base reg to register save area. */
8344 HOST_WIDE_INT reg_offset
;
8345 int fp_is_frame_pointer
, fp_offset
;
8346 rtx sa_reg
, sa_reg_exp
= NULL
;
8347 rtx sp_adj1
, sp_adj2
, mem
, reg
, insn
;
8349 rtx cfa_restores
= NULL_RTX
;
8352 sa_size
= alpha_sa_size ();
8353 frame_size
= compute_frame_size (get_frame_size (), sa_size
);
8355 if (TARGET_ABI_OPEN_VMS
)
8357 if (alpha_procedure_type
== PT_STACK
)
8358 reg_offset
= 8 + 8 * cfun
->machine
->uses_condition_handler
;
8363 reg_offset
= ALPHA_ROUND (crtl
->outgoing_args_size
);
8365 alpha_sa_mask (&imask
, &fmask
);
8368 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
8369 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
8371 sa_reg
= stack_pointer_rtx
;
8373 if (crtl
->calls_eh_return
)
8374 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
8378 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
8380 /* If we have a frame pointer, restore SP from it. */
8381 if ((TARGET_ABI_OPEN_VMS
8382 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
8383 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
8384 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
8386 /* Cope with very large offsets to the register save area. */
8387 if (reg_offset
+ sa_size
> 0x8000)
8389 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
8392 if (low
+ sa_size
<= 0x8000)
8393 bias
= reg_offset
- low
, reg_offset
= low
;
8395 bias
= reg_offset
, reg_offset
= 0;
8397 sa_reg
= gen_rtx_REG (DImode
, 22);
8398 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
8400 emit_move_insn (sa_reg
, sa_reg_exp
);
8403 /* Restore registers in order, excepting a true frame pointer. */
8405 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
8407 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8408 reg
= gen_rtx_REG (DImode
, REG_RA
);
8409 emit_move_insn (reg
, mem
);
8410 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8413 imask
&= ~(1UL << REG_RA
);
8415 for (i
= 0; i
< 31; ++i
)
8416 if (imask
& (1UL << i
))
8418 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
8419 fp_offset
= reg_offset
;
8422 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
8423 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8424 reg
= gen_rtx_REG (DImode
, i
);
8425 emit_move_insn (reg
, mem
);
8426 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8432 for (i
= 0; i
< 31; ++i
)
8433 if (fmask
& (1UL << i
))
8435 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
8436 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8437 reg
= gen_rtx_REG (DFmode
, i
+32);
8438 emit_move_insn (reg
, mem
);
8439 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8443 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
8445 /* Restore callee-saved general-purpose registers. */
8449 for (i
= 9; i
< 15; i
++)
8450 if (imask
& (1UL << i
))
8452 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
8454 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8455 reg
= gen_rtx_REG (DImode
, i
);
8456 emit_move_insn (reg
, mem
);
8457 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8461 for (i
= 2; i
< 10; i
++)
8462 if (fmask
& (1UL << i
))
8464 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
8466 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8467 reg
= gen_rtx_REG (DFmode
, i
+32);
8468 emit_move_insn (reg
, mem
);
8469 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8473 /* Restore the return address from the DSIB. */
8474 mem
= gen_rtx_MEM (DImode
, plus_constant (hard_frame_pointer_rtx
, -8));
8475 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8476 reg
= gen_rtx_REG (DImode
, REG_RA
);
8477 emit_move_insn (reg
, mem
);
8478 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
8481 if (frame_size
|| eh_ofs
)
8483 sp_adj1
= stack_pointer_rtx
;
8487 sp_adj1
= gen_rtx_REG (DImode
, 23);
8488 emit_move_insn (sp_adj1
,
8489 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
8492 /* If the stack size is large, begin computation into a temporary
8493 register so as not to interfere with a potential fp restore,
8494 which must be consecutive with an SP restore. */
8495 if (frame_size
< 32768
8496 && ! (TARGET_ABI_UNICOSMK
&& cfun
->calls_alloca
))
8497 sp_adj2
= GEN_INT (frame_size
);
8498 else if (TARGET_ABI_UNICOSMK
)
8500 sp_adj1
= gen_rtx_REG (DImode
, 23);
8501 emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
);
8502 sp_adj2
= const0_rtx
;
8504 else if (frame_size
< 0x40007fffL
)
8506 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
8508 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
8509 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
8513 sp_adj1
= gen_rtx_REG (DImode
, 23);
8514 emit_move_insn (sp_adj1
, sp_adj2
);
8516 sp_adj2
= GEN_INT (low
);
8520 rtx tmp
= gen_rtx_REG (DImode
, 23);
8521 sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3, false);
8524 /* We can't drop new things to memory this late, afaik,
8525 so build it up by pieces. */
8526 sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
8528 gcc_assert (sp_adj2
);
8532 /* From now on, things must be in order. So emit blockages. */
8534 /* Restore the frame pointer. */
8535 if (TARGET_ABI_UNICOSMK
)
8537 emit_insn (gen_blockage ());
8538 mem
= gen_rtx_MEM (DImode
,
8539 plus_constant (hard_frame_pointer_rtx
, -16));
8540 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8541 emit_move_insn (hard_frame_pointer_rtx
, mem
);
8542 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
8543 hard_frame_pointer_rtx
, cfa_restores
);
8545 else if (fp_is_frame_pointer
)
8547 emit_insn (gen_blockage ());
8548 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
8549 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8550 emit_move_insn (hard_frame_pointer_rtx
, mem
);
8551 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
8552 hard_frame_pointer_rtx
, cfa_restores
);
8554 else if (TARGET_ABI_OPEN_VMS
)
8556 emit_insn (gen_blockage ());
8557 emit_move_insn (hard_frame_pointer_rtx
,
8558 gen_rtx_REG (DImode
, vms_save_fp_regno
));
8559 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
8560 hard_frame_pointer_rtx
, cfa_restores
);
8563 /* Restore the stack pointer. */
8564 emit_insn (gen_blockage ());
8565 if (sp_adj2
== const0_rtx
)
8566 insn
= emit_move_insn (stack_pointer_rtx
, sp_adj1
);
8568 insn
= emit_move_insn (stack_pointer_rtx
,
8569 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
));
8570 REG_NOTES (insn
) = cfa_restores
;
8571 add_reg_note (insn
, REG_CFA_DEF_CFA
, stack_pointer_rtx
);
8572 RTX_FRAME_RELATED_P (insn
) = 1;
8576 gcc_assert (cfa_restores
== NULL
);
8578 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
8580 emit_insn (gen_blockage ());
8581 insn
= emit_move_insn (hard_frame_pointer_rtx
,
8582 gen_rtx_REG (DImode
, vms_save_fp_regno
));
8583 add_reg_note (insn
, REG_CFA_RESTORE
, hard_frame_pointer_rtx
);
8584 RTX_FRAME_RELATED_P (insn
) = 1;
8586 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
8588 /* Decrement the frame pointer if the function does not have a
8590 emit_insn (gen_blockage ());
8591 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8592 hard_frame_pointer_rtx
, constm1_rtx
));
8597 /* Output the rest of the textual info surrounding the epilogue. */
8600 alpha_end_function (FILE *file
, const char *fnname
, tree decl ATTRIBUTE_UNUSED
)
8604 /* We output a nop after noreturn calls at the very end of the function to
8605 ensure that the return address always remains in the caller's code range,
8606 as not doing so might confuse unwinding engines. */
8607 insn
= get_last_insn ();
8609 insn
= prev_active_insn (insn
);
8610 if (insn
&& CALL_P (insn
))
8611 output_asm_insn (get_insn_template (CODE_FOR_nop
, NULL
), NULL
);
8613 #if TARGET_ABI_OPEN_VMS
8614 alpha_write_linkage (file
, fnname
, decl
);
8617 /* End the function. */
8618 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
8620 fputs ("\t.end ", file
);
8621 assemble_name (file
, fnname
);
8624 inside_function
= FALSE
;
8626 /* Output jump tables and the static subroutine information block. */
8627 if (TARGET_ABI_UNICOSMK
)
8629 unicosmk_output_ssib (file
, fnname
);
8630 unicosmk_output_deferred_case_vectors (file
);
8634 #if TARGET_ABI_OPEN_VMS
8635 void avms_asm_output_external (FILE *file
, tree decl ATTRIBUTE_UNUSED
, const char *name
)
8637 #ifdef DO_CRTL_NAMES
8644 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8646 In order to avoid the hordes of differences between generated code
8647 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8648 lots of code loading up large constants, generate rtl and emit it
8649 instead of going straight to text.
8651 Not sure why this idea hasn't been explored before... */
8654 alpha_output_mi_thunk_osf (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
8655 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8658 HOST_WIDE_INT hi
, lo
;
8659 rtx this_rtx
, insn
, funexp
;
8661 /* We always require a valid GP. */
8662 emit_insn (gen_prologue_ldgp ());
8663 emit_note (NOTE_INSN_PROLOGUE_END
);
8665 /* Find the "this" pointer. If the function returns a structure,
8666 the structure return pointer is in $16. */
8667 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8668 this_rtx
= gen_rtx_REG (Pmode
, 17);
8670 this_rtx
= gen_rtx_REG (Pmode
, 16);
8672 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8673 entire constant for the add. */
8674 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8675 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8676 if (hi
+ lo
== delta
)
8679 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, GEN_INT (hi
)));
8681 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, GEN_INT (lo
)));
8685 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8686 delta
, -(delta
< 0));
8687 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
8690 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8695 tmp
= gen_rtx_REG (Pmode
, 0);
8696 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
8698 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8699 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8700 if (hi
+ lo
== vcall_offset
)
8703 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8707 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8708 vcall_offset
, -(vcall_offset
< 0));
8709 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8713 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8716 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8718 emit_insn (gen_adddi3 (this_rtx
, this_rtx
, tmp
));
8721 /* Generate a tail call to the target function. */
8722 if (! TREE_USED (function
))
8724 assemble_external (function
);
8725 TREE_USED (function
) = 1;
8727 funexp
= XEXP (DECL_RTL (function
), 0);
8728 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8729 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8730 SIBLING_CALL_P (insn
) = 1;
8732 /* Run just enough of rest_of_compilation to get the insns emitted.
8733 There's not really enough bulk here to make other passes such as
8734 instruction scheduling worth while. Note that use_thunk calls
8735 assemble_start_function and assemble_end_function. */
8736 insn
= get_insns ();
8737 insn_locators_alloc ();
8738 shorten_branches (insn
);
8739 final_start_function (insn
, file
, 1);
8740 final (insn
, file
, 1);
8741 final_end_function ();
8743 #endif /* TARGET_ABI_OSF */
8745 /* Debugging support. */
8749 /* Count the number of sdb related labels are generated (to find block
8750 start and end boundaries). */
8752 int sdb_label_count
= 0;
8754 /* Name of the file containing the current function. */
8756 static const char *current_function_file
= "";
8758 /* Offsets to alpha virtual arg/local debugging pointers. */
8760 long alpha_arg_offset
;
8761 long alpha_auto_offset
;
8763 /* Emit a new filename to a stream. */
8766 alpha_output_filename (FILE *stream
, const char *name
)
8768 static int first_time
= TRUE
;
8773 ++num_source_filenames
;
8774 current_function_file
= name
;
8775 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8776 output_quoted_string (stream
, name
);
8777 fprintf (stream
, "\n");
8778 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8779 fprintf (stream
, "\t#@stabs\n");
8782 else if (write_symbols
== DBX_DEBUG
)
8783 /* dbxout.c will emit an appropriate .stabs directive. */
8786 else if (name
!= current_function_file
8787 && strcmp (name
, current_function_file
) != 0)
8789 if (inside_function
&& ! TARGET_GAS
)
8790 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8793 ++num_source_filenames
;
8794 current_function_file
= name
;
8795 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8798 output_quoted_string (stream
, name
);
8799 fprintf (stream
, "\n");
8803 /* Structure to show the current status of registers and memory. */
8805 struct shadow_summary
8808 unsigned int i
: 31; /* Mask of int regs */
8809 unsigned int fp
: 31; /* Mask of fp regs */
8810 unsigned int mem
: 1; /* mem == imem | fpmem */
8814 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8815 to the summary structure. SET is nonzero if the insn is setting the
8816 object, otherwise zero. */
8819 summarize_insn (rtx x
, struct shadow_summary
*sum
, int set
)
8821 const char *format_ptr
;
8827 switch (GET_CODE (x
))
8829 /* ??? Note that this case would be incorrect if the Alpha had a
8830 ZERO_EXTRACT in SET_DEST. */
8832 summarize_insn (SET_SRC (x
), sum
, 0);
8833 summarize_insn (SET_DEST (x
), sum
, 1);
8837 summarize_insn (XEXP (x
, 0), sum
, 1);
8841 summarize_insn (XEXP (x
, 0), sum
, 0);
8845 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8846 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8850 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8851 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8855 summarize_insn (SUBREG_REG (x
), sum
, 0);
8860 int regno
= REGNO (x
);
8861 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8863 if (regno
== 31 || regno
== 63)
8869 sum
->defd
.i
|= mask
;
8871 sum
->defd
.fp
|= mask
;
8876 sum
->used
.i
|= mask
;
8878 sum
->used
.fp
|= mask
;
8889 /* Find the regs used in memory address computation: */
8890 summarize_insn (XEXP (x
, 0), sum
, 0);
8893 case CONST_INT
: case CONST_DOUBLE
:
8894 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8895 case SCRATCH
: case ASM_INPUT
:
8898 /* Handle common unary and binary ops for efficiency. */
8899 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8900 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8901 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8902 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8903 case NE
: case EQ
: case GE
: case GT
: case LE
:
8904 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8905 summarize_insn (XEXP (x
, 0), sum
, 0);
8906 summarize_insn (XEXP (x
, 1), sum
, 0);
8909 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8910 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8911 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8912 case SQRT
: case FFS
:
8913 summarize_insn (XEXP (x
, 0), sum
, 0);
8917 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8918 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8919 switch (format_ptr
[i
])
8922 summarize_insn (XEXP (x
, i
), sum
, 0);
8926 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8927 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8939 /* Ensure a sufficient number of `trapb' insns are in the code when
8940 the user requests code with a trap precision of functions or
8943 In naive mode, when the user requests a trap-precision of
8944 "instruction", a trapb is needed after every instruction that may
8945 generate a trap. This ensures that the code is resumption safe but
8948 When optimizations are turned on, we delay issuing a trapb as long
8949 as possible. In this context, a trap shadow is the sequence of
8950 instructions that starts with a (potentially) trap generating
8951 instruction and extends to the next trapb or call_pal instruction
8952 (but GCC never generates call_pal by itself). We can delay (and
8953 therefore sometimes omit) a trapb subject to the following
8956 (a) On entry to the trap shadow, if any Alpha register or memory
8957 location contains a value that is used as an operand value by some
8958 instruction in the trap shadow (live on entry), then no instruction
8959 in the trap shadow may modify the register or memory location.
8961 (b) Within the trap shadow, the computation of the base register
8962 for a memory load or store instruction may not involve using the
8963 result of an instruction that might generate an UNPREDICTABLE
8966 (c) Within the trap shadow, no register may be used more than once
8967 as a destination register. (This is to make life easier for the
8970 (d) The trap shadow may not include any branch instructions. */
8973 alpha_handle_trap_shadows (void)
8975 struct shadow_summary shadow
;
8976 int trap_pending
, exception_nesting
;
8980 exception_nesting
= 0;
8983 shadow
.used
.mem
= 0;
8984 shadow
.defd
= shadow
.used
;
8986 for (i
= get_insns (); i
; i
= NEXT_INSN (i
))
8990 switch (NOTE_KIND (i
))
8992 case NOTE_INSN_EH_REGION_BEG
:
8993 exception_nesting
++;
8998 case NOTE_INSN_EH_REGION_END
:
8999 exception_nesting
--;
9004 case NOTE_INSN_EPILOGUE_BEG
:
9005 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
9010 else if (trap_pending
)
9012 if (alpha_tp
== ALPHA_TP_FUNC
)
9015 && GET_CODE (PATTERN (i
)) == RETURN
)
9018 else if (alpha_tp
== ALPHA_TP_INSN
)
9022 struct shadow_summary sum
;
9027 sum
.defd
= sum
.used
;
9029 switch (GET_CODE (i
))
9032 /* Annoyingly, get_attr_trap will die on these. */
9033 if (GET_CODE (PATTERN (i
)) == USE
9034 || GET_CODE (PATTERN (i
)) == CLOBBER
)
9037 summarize_insn (PATTERN (i
), &sum
, 0);
9039 if ((sum
.defd
.i
& shadow
.defd
.i
)
9040 || (sum
.defd
.fp
& shadow
.defd
.fp
))
9042 /* (c) would be violated */
9046 /* Combine shadow with summary of current insn: */
9047 shadow
.used
.i
|= sum
.used
.i
;
9048 shadow
.used
.fp
|= sum
.used
.fp
;
9049 shadow
.used
.mem
|= sum
.used
.mem
;
9050 shadow
.defd
.i
|= sum
.defd
.i
;
9051 shadow
.defd
.fp
|= sum
.defd
.fp
;
9052 shadow
.defd
.mem
|= sum
.defd
.mem
;
9054 if ((sum
.defd
.i
& shadow
.used
.i
)
9055 || (sum
.defd
.fp
& shadow
.used
.fp
)
9056 || (sum
.defd
.mem
& shadow
.used
.mem
))
9058 /* (a) would be violated (also takes care of (b)) */
9059 gcc_assert (get_attr_trap (i
) != TRAP_YES
9060 || (!(sum
.defd
.i
& sum
.used
.i
)
9061 && !(sum
.defd
.fp
& sum
.used
.fp
)));
9079 n
= emit_insn_before (gen_trapb (), i
);
9080 PUT_MODE (n
, TImode
);
9081 PUT_MODE (i
, TImode
);
9085 shadow
.used
.mem
= 0;
9086 shadow
.defd
= shadow
.used
;
9091 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
9092 && NONJUMP_INSN_P (i
)
9093 && GET_CODE (PATTERN (i
)) != USE
9094 && GET_CODE (PATTERN (i
)) != CLOBBER
9095 && get_attr_trap (i
) == TRAP_YES
)
9097 if (optimize
&& !trap_pending
)
9098 summarize_insn (PATTERN (i
), &shadow
, 0);
9104 /* Alpha can only issue instruction groups simultaneously if they are
9105 suitably aligned. This is very processor-specific. */
9106 /* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe
9107 that are marked "fake". These instructions do not exist on that target,
9108 but it is possible to see these insns with deranged combinations of
9109 command-line options, such as "-mtune=ev4 -mmax". Instead of aborting,
9110 choose a result at random. */
9112 enum alphaev4_pipe
{
9119 enum alphaev5_pipe
{
9130 static enum alphaev4_pipe
9131 alphaev4_insn_pipe (rtx insn
)
9133 if (recog_memoized (insn
) < 0)
9135 if (get_attr_length (insn
) != 4)
9138 switch (get_attr_type (insn
))
9154 case TYPE_MVI
: /* fake */
9169 case TYPE_FSQRT
: /* fake */
9170 case TYPE_FTOI
: /* fake */
9171 case TYPE_ITOF
: /* fake */
9179 static enum alphaev5_pipe
9180 alphaev5_insn_pipe (rtx insn
)
9182 if (recog_memoized (insn
) < 0)
9184 if (get_attr_length (insn
) != 4)
9187 switch (get_attr_type (insn
))
9207 case TYPE_FTOI
: /* fake */
9208 case TYPE_ITOF
: /* fake */
9223 case TYPE_FSQRT
: /* fake */
9234 /* IN_USE is a mask of the slots currently filled within the insn group.
9235 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
9236 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
9238 LEN is, of course, the length of the group in bytes. */
9241 alphaev4_next_group (rtx insn
, int *pin_use
, int *plen
)
9248 || GET_CODE (PATTERN (insn
)) == CLOBBER
9249 || GET_CODE (PATTERN (insn
)) == USE
)
9254 enum alphaev4_pipe pipe
;
9256 pipe
= alphaev4_insn_pipe (insn
);
9260 /* Force complex instructions to start new groups. */
9264 /* If this is a completely unrecognized insn, it's an asm.
9265 We don't know how long it is, so record length as -1 to
9266 signal a needed realignment. */
9267 if (recog_memoized (insn
) < 0)
9270 len
= get_attr_length (insn
);
9274 if (in_use
& EV4_IB0
)
9276 if (in_use
& EV4_IB1
)
9281 in_use
|= EV4_IB0
| EV4_IBX
;
9285 if (in_use
& EV4_IB0
)
9287 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
9295 if (in_use
& EV4_IB1
)
9305 /* Haifa doesn't do well scheduling branches. */
9310 insn
= next_nonnote_insn (insn
);
9312 if (!insn
|| ! INSN_P (insn
))
9315 /* Let Haifa tell us where it thinks insn group boundaries are. */
9316 if (GET_MODE (insn
) == TImode
)
9319 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
9324 insn
= next_nonnote_insn (insn
);
9332 /* IN_USE is a mask of the slots currently filled within the insn group.
9333 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
9334 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
9336 LEN is, of course, the length of the group in bytes. */
9339 alphaev5_next_group (rtx insn
, int *pin_use
, int *plen
)
9346 || GET_CODE (PATTERN (insn
)) == CLOBBER
9347 || GET_CODE (PATTERN (insn
)) == USE
)
9352 enum alphaev5_pipe pipe
;
9354 pipe
= alphaev5_insn_pipe (insn
);
9358 /* Force complex instructions to start new groups. */
9362 /* If this is a completely unrecognized insn, it's an asm.
9363 We don't know how long it is, so record length as -1 to
9364 signal a needed realignment. */
9365 if (recog_memoized (insn
) < 0)
9368 len
= get_attr_length (insn
);
9371 /* ??? Most of the places below, we would like to assert never
9372 happen, as it would indicate an error either in Haifa, or
9373 in the scheduling description. Unfortunately, Haifa never
9374 schedules the last instruction of the BB, so we don't have
9375 an accurate TI bit to go off. */
9377 if (in_use
& EV5_E0
)
9379 if (in_use
& EV5_E1
)
9384 in_use
|= EV5_E0
| EV5_E01
;
9388 if (in_use
& EV5_E0
)
9390 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
9398 if (in_use
& EV5_E1
)
9404 if (in_use
& EV5_FA
)
9406 if (in_use
& EV5_FM
)
9411 in_use
|= EV5_FA
| EV5_FAM
;
9415 if (in_use
& EV5_FA
)
9421 if (in_use
& EV5_FM
)
9434 /* Haifa doesn't do well scheduling branches. */
9435 /* ??? If this is predicted not-taken, slotting continues, except
9436 that no more IBR, FBR, or JSR insns may be slotted. */
9441 insn
= next_nonnote_insn (insn
);
9443 if (!insn
|| ! INSN_P (insn
))
9446 /* Let Haifa tell us where it thinks insn group boundaries are. */
9447 if (GET_MODE (insn
) == TImode
)
9450 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
9455 insn
= next_nonnote_insn (insn
);
9464 alphaev4_next_nop (int *pin_use
)
9466 int in_use
= *pin_use
;
9469 if (!(in_use
& EV4_IB0
))
9474 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
9479 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
9492 alphaev5_next_nop (int *pin_use
)
9494 int in_use
= *pin_use
;
9497 if (!(in_use
& EV5_E1
))
9502 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
9507 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
9519 /* The instruction group alignment main loop. */
9522 alpha_align_insns (unsigned int max_align
,
9523 rtx (*next_group
) (rtx
, int *, int *),
9524 rtx (*next_nop
) (int *))
9526 /* ALIGN is the known alignment for the insn group. */
9528 /* OFS is the offset of the current insn in the insn group. */
9530 int prev_in_use
, in_use
, len
, ldgp
;
9533 /* Let shorten branches care for assigning alignments to code labels. */
9534 shorten_branches (get_insns ());
9536 if (align_functions
< 4)
9538 else if ((unsigned int) align_functions
< max_align
)
9539 align
= align_functions
;
9543 ofs
= prev_in_use
= 0;
9546 i
= next_nonnote_insn (i
);
9548 ldgp
= alpha_function_needs_gp
? 8 : 0;
9552 next
= (*next_group
) (i
, &in_use
, &len
);
9554 /* When we see a label, resync alignment etc. */
9557 unsigned int new_align
= 1 << label_to_alignment (i
);
9559 if (new_align
>= align
)
9561 align
= new_align
< max_align
? new_align
: max_align
;
9565 else if (ofs
& (new_align
-1))
9566 ofs
= (ofs
| (new_align
-1)) + 1;
9570 /* Handle complex instructions special. */
9571 else if (in_use
== 0)
9573 /* Asms will have length < 0. This is a signal that we have
9574 lost alignment knowledge. Assume, however, that the asm
9575 will not mis-align instructions. */
9584 /* If the known alignment is smaller than the recognized insn group,
9585 realign the output. */
9586 else if ((int) align
< len
)
9588 unsigned int new_log_align
= len
> 8 ? 4 : 3;
9591 where
= prev
= prev_nonnote_insn (i
);
9592 if (!where
|| !LABEL_P (where
))
9595 /* Can't realign between a call and its gp reload. */
9596 if (! (TARGET_EXPLICIT_RELOCS
9597 && prev
&& CALL_P (prev
)))
9599 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
9600 align
= 1 << new_log_align
;
9605 /* We may not insert padding inside the initial ldgp sequence. */
9609 /* If the group won't fit in the same INT16 as the previous,
9610 we need to add padding to keep the group together. Rather
9611 than simply leaving the insn filling to the assembler, we
9612 can make use of the knowledge of what sorts of instructions
9613 were issued in the previous group to make sure that all of
9614 the added nops are really free. */
9615 else if (ofs
+ len
> (int) align
)
9617 int nop_count
= (align
- ofs
) / 4;
9620 /* Insert nops before labels, branches, and calls to truly merge
9621 the execution of the nops with the previous instruction group. */
9622 where
= prev_nonnote_insn (i
);
9625 if (LABEL_P (where
))
9627 rtx where2
= prev_nonnote_insn (where
);
9628 if (where2
&& JUMP_P (where2
))
9631 else if (NONJUMP_INSN_P (where
))
9638 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
9639 while (--nop_count
);
9643 ofs
= (ofs
+ len
) & (align
- 1);
9644 prev_in_use
= in_use
;
9649 /* Insert an unop between a noreturn function call and GP load. */
9652 alpha_pad_noreturn (void)
9656 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9658 if (! (CALL_P (insn
)
9659 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
)))
9662 /* Make sure we do not split a call and its corresponding
9663 CALL_ARG_LOCATION note. */
9666 next
= NEXT_INSN (insn
);
9667 if (next
&& NOTE_P (next
)
9668 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
9672 next
= next_active_insn (insn
);
9676 rtx pat
= PATTERN (next
);
9678 if (GET_CODE (pat
) == SET
9679 && GET_CODE (SET_SRC (pat
)) == UNSPEC_VOLATILE
9680 && XINT (SET_SRC (pat
), 1) == UNSPECV_LDGP1
)
9681 emit_insn_after (gen_unop (), insn
);
9686 /* Machine dependent reorg pass. */
9691 /* Workaround for a linker error that triggers when an
9692 exception handler immediatelly follows a noreturn function.
9694 The instruction stream from an object file:
9696 54: 00 40 5b 6b jsr ra,(t12),58 <__func+0x58>
9697 58: 00 00 ba 27 ldah gp,0(ra)
9698 5c: 00 00 bd 23 lda gp,0(gp)
9699 60: 00 00 7d a7 ldq t12,0(gp)
9700 64: 00 40 5b 6b jsr ra,(t12),68 <__func+0x68>
9702 was converted in the final link pass to:
9704 fdb24: a0 03 40 d3 bsr ra,fe9a8 <_called_func+0x8>
9705 fdb28: 00 00 fe 2f unop
9706 fdb2c: 00 00 fe 2f unop
9707 fdb30: 30 82 7d a7 ldq t12,-32208(gp)
9708 fdb34: 00 40 5b 6b jsr ra,(t12),fdb38 <__func+0x68>
9710 GP load instructions were wrongly cleared by the linker relaxation
9711 pass. This workaround prevents removal of GP loads by inserting
9712 an unop instruction between a noreturn function call and
9713 exception handler prologue. */
9715 if (current_function_has_exception_handlers ())
9716 alpha_pad_noreturn ();
9718 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
9719 alpha_handle_trap_shadows ();
9721 /* Due to the number of extra trapb insns, don't bother fixing up
9722 alignment when trap precision is instruction. Moreover, we can
9723 only do our job when sched2 is run. */
9724 if (optimize
&& !optimize_size
9725 && alpha_tp
!= ALPHA_TP_INSN
9726 && flag_schedule_insns_after_reload
)
9728 if (alpha_tune
== PROCESSOR_EV4
)
9729 alpha_align_insns (8, alphaev4_next_group
, alphaev4_next_nop
);
9730 else if (alpha_tune
== PROCESSOR_EV5
)
9731 alpha_align_insns (16, alphaev5_next_group
, alphaev5_next_nop
);
9735 #if !TARGET_ABI_UNICOSMK
9742 alpha_file_start (void)
9744 #ifdef OBJECT_FORMAT_ELF
9745 /* If emitting dwarf2 debug information, we cannot generate a .file
9746 directive to start the file, as it will conflict with dwarf2out
9747 file numbers. So it's only useful when emitting mdebug output. */
9748 targetm
.asm_file_start_file_directive
= (write_symbols
== DBX_DEBUG
);
9751 default_file_start ();
9753 fprintf (asm_out_file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
9756 fputs ("\t.set noreorder\n", asm_out_file
);
9757 fputs ("\t.set volatile\n", asm_out_file
);
9758 if (!TARGET_ABI_OPEN_VMS
)
9759 fputs ("\t.set noat\n", asm_out_file
);
9760 if (TARGET_EXPLICIT_RELOCS
)
9761 fputs ("\t.set nomacro\n", asm_out_file
);
9762 if (TARGET_SUPPORT_ARCH
| TARGET_BWX
| TARGET_MAX
| TARGET_FIX
| TARGET_CIX
)
9766 if (alpha_cpu
== PROCESSOR_EV6
|| TARGET_FIX
|| TARGET_CIX
)
9768 else if (TARGET_MAX
)
9770 else if (TARGET_BWX
)
9772 else if (alpha_cpu
== PROCESSOR_EV5
)
9777 fprintf (asm_out_file
, "\t.arch %s\n", arch
);
9782 #ifdef OBJECT_FORMAT_ELF
9783 /* Since we don't have a .dynbss section, we should not allow global
9784 relocations in the .rodata section. */
9787 alpha_elf_reloc_rw_mask (void)
9789 return flag_pic
? 3 : 2;
9792 /* Return a section for X. The only special thing we do here is to
9793 honor small data. */
9796 alpha_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
9797 unsigned HOST_WIDE_INT align
)
9799 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9800 /* ??? Consider using mergeable sdata sections. */
9801 return sdata_section
;
9803 return default_elf_select_rtx_section (mode
, x
, align
);
9807 alpha_elf_section_type_flags (tree decl
, const char *name
, int reloc
)
9809 unsigned int flags
= 0;
9811 if (strcmp (name
, ".sdata") == 0
9812 || strncmp (name
, ".sdata.", 7) == 0
9813 || strncmp (name
, ".gnu.linkonce.s.", 16) == 0
9814 || strcmp (name
, ".sbss") == 0
9815 || strncmp (name
, ".sbss.", 6) == 0
9816 || strncmp (name
, ".gnu.linkonce.sb.", 17) == 0)
9817 flags
= SECTION_SMALL
;
9819 flags
|= default_section_type_flags (decl
, name
, reloc
);
9822 #endif /* OBJECT_FORMAT_ELF */
9824 /* Structure to collect function names for final output in link section. */
9825 /* Note that items marked with GTY can't be ifdef'ed out. */
9827 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
9828 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
9830 struct GTY(()) alpha_links
9835 enum links_kind lkind
;
9836 enum reloc_kind rkind
;
9839 struct GTY(()) alpha_funcs
9842 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9846 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9847 splay_tree alpha_links_tree
;
9848 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
9849 splay_tree alpha_funcs_tree
;
9851 static GTY(()) int alpha_funcs_num
;
9853 #if TARGET_ABI_OPEN_VMS
9855 /* Return the VMS argument type corresponding to MODE. */
9858 alpha_arg_type (enum machine_mode mode
)
9863 return TARGET_FLOAT_VAX
? FF
: FS
;
9865 return TARGET_FLOAT_VAX
? FD
: FT
;
9871 /* Return an rtx for an integer representing the VMS Argument Information
9875 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum
)
9877 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9880 for (i
= 0; i
< 6; i
++)
9881 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9883 return GEN_INT (regval
);
9886 /* Register the need for a (fake) .linkage entry for calls to function NAME.
9887 IS_LOCAL is 1 if this is for a definition, 0 if this is for a real call.
9888 Return a SYMBOL_REF suited to the call instruction. */
9891 alpha_need_linkage (const char *name
, int is_local
)
9893 splay_tree_node node
;
9894 struct alpha_links
*al
;
9903 struct alpha_funcs
*cfaf
;
9905 if (!alpha_funcs_tree
)
9906 alpha_funcs_tree
= splay_tree_new_ggc
9907 (splay_tree_compare_pointers
,
9908 ggc_alloc_splay_tree_tree_node_tree_node_splay_tree_s
,
9909 ggc_alloc_splay_tree_tree_node_tree_node_splay_tree_node_s
);
9912 cfaf
= ggc_alloc_alpha_funcs ();
9915 cfaf
->num
= ++alpha_funcs_num
;
9917 splay_tree_insert (alpha_funcs_tree
,
9918 (splay_tree_key
) current_function_decl
,
9919 (splay_tree_value
) cfaf
);
9922 if (alpha_links_tree
)
9924 /* Is this name already defined? */
9926 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9929 al
= (struct alpha_links
*) node
->value
;
9932 /* Defined here but external assumed. */
9933 if (al
->lkind
== KIND_EXTERN
)
9934 al
->lkind
= KIND_LOCAL
;
9938 /* Used here but unused assumed. */
9939 if (al
->lkind
== KIND_UNUSED
)
9940 al
->lkind
= KIND_LOCAL
;
9946 alpha_links_tree
= splay_tree_new_ggc
9947 ((splay_tree_compare_fn
) strcmp
,
9948 ggc_alloc_splay_tree_str_alpha_links_splay_tree_s
,
9949 ggc_alloc_splay_tree_str_alpha_links_splay_tree_node_s
);
9951 al
= ggc_alloc_alpha_links ();
9952 name
= ggc_strdup (name
);
9954 /* Assume external if no definition. */
9955 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9957 /* Ensure we have an IDENTIFIER so assemble_name can mark it used
9958 and find the ultimate alias target like assemble_name. */
9959 id
= get_identifier (name
);
9961 while (IDENTIFIER_TRANSPARENT_ALIAS (id
))
9963 id
= TREE_CHAIN (id
);
9964 target
= IDENTIFIER_POINTER (id
);
9967 al
->target
= target
? target
: name
;
9968 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
, name
);
9970 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9971 (splay_tree_value
) al
);
9976 /* Return a SYMBOL_REF representing the reference to the .linkage entry
9977 of function FUNC built for calls made from CFUNDECL. LFLAG is 1 if
9978 this is the reference to the linkage pointer value, 0 if this is the
9979 reference to the function entry value. RFLAG is 1 if this a reduced
9980 reference (code address only), 0 if this is a full reference. */
9983 alpha_use_linkage (rtx func
, tree cfundecl
, int lflag
, int rflag
)
9985 splay_tree_node cfunnode
;
9986 struct alpha_funcs
*cfaf
;
9987 struct alpha_links
*al
;
9988 const char *name
= XSTR (func
, 0);
9990 cfaf
= (struct alpha_funcs
*) 0;
9991 al
= (struct alpha_links
*) 0;
9993 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9994 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9998 splay_tree_node lnode
;
10000 /* Is this name already defined? */
10002 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
10004 al
= (struct alpha_links
*) lnode
->value
;
10007 cfaf
->links
= splay_tree_new_ggc
10008 ((splay_tree_compare_fn
) strcmp
,
10009 ggc_alloc_splay_tree_str_alpha_links_splay_tree_s
,
10010 ggc_alloc_splay_tree_str_alpha_links_splay_tree_node_s
);
10017 splay_tree_node node
= 0;
10018 struct alpha_links
*anl
;
10020 if (name
[0] == '*')
10023 name_len
= strlen (name
);
10024 linksym
= (char *) alloca (name_len
+ 50);
10026 al
= ggc_alloc_alpha_links ();
10027 al
->num
= cfaf
->num
;
10030 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
10033 anl
= (struct alpha_links
*) node
->value
;
10034 al
->lkind
= anl
->lkind
;
10035 name
= anl
->target
;
10038 sprintf (linksym
, "$%d..%s..lk", cfaf
->num
, name
);
10039 buflen
= strlen (linksym
);
10041 al
->linkage
= gen_rtx_SYMBOL_REF
10042 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
10044 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
10045 (splay_tree_value
) al
);
10049 al
->rkind
= KIND_CODEADDR
;
10051 al
->rkind
= KIND_LINKAGE
;
10054 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
10056 return al
->linkage
;
10060 alpha_write_one_linkage (splay_tree_node node
, void *data
)
10062 const char *const name
= (const char *) node
->key
;
10063 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
10064 FILE *stream
= (FILE *) data
;
10066 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
10067 if (link
->rkind
== KIND_CODEADDR
)
10069 if (link
->lkind
== KIND_LOCAL
)
10071 /* Local and used */
10072 fprintf (stream
, "\t.quad %s..en\n", name
);
10076 /* External and used, request code address. */
10077 fprintf (stream
, "\t.code_address %s\n", name
);
10082 if (link
->lkind
== KIND_LOCAL
)
10084 /* Local and used, build linkage pair. */
10085 fprintf (stream
, "\t.quad %s..en\n", name
);
10086 fprintf (stream
, "\t.quad %s\n", name
);
10090 /* External and used, request linkage pair. */
10091 fprintf (stream
, "\t.linkage %s\n", name
);
10099 alpha_write_linkage (FILE *stream
, const char *funname
, tree fundecl
)
10101 splay_tree_node node
;
10102 struct alpha_funcs
*func
;
10104 fprintf (stream
, "\t.link\n");
10105 fprintf (stream
, "\t.align 3\n");
10108 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
10109 func
= (struct alpha_funcs
*) node
->value
;
10111 fputs ("\t.name ", stream
);
10112 assemble_name (stream
, funname
);
10113 fputs ("..na\n", stream
);
10114 ASM_OUTPUT_LABEL (stream
, funname
);
10115 fprintf (stream
, "\t.pdesc ");
10116 assemble_name (stream
, funname
);
10117 fprintf (stream
, "..en,%s\n",
10118 alpha_procedure_type
== PT_STACK
? "stack"
10119 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
10123 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
10124 /* splay_tree_delete (func->links); */
10128 /* Switch to an arbitrary section NAME with attributes as specified
10129 by FLAGS. ALIGN specifies any known alignment requirements for
10130 the section; 0 if the default should be used. */
10133 vms_asm_named_section (const char *name
, unsigned int flags
,
10134 tree decl ATTRIBUTE_UNUSED
)
10136 fputc ('\n', asm_out_file
);
10137 fprintf (asm_out_file
, ".section\t%s", name
);
10139 if (flags
& SECTION_DEBUG
)
10140 fprintf (asm_out_file
, ",NOWRT");
10142 fputc ('\n', asm_out_file
);
10145 /* Record an element in the table of global constructors. SYMBOL is
10146 a SYMBOL_REF of the function to be called; PRIORITY is a number
10147 between 0 and MAX_INIT_PRIORITY.
10149 Differs from default_ctors_section_asm_out_constructor in that the
10150 width of the .ctors entry is always 64 bits, rather than the 32 bits
10151 used by a normal pointer. */
10154 vms_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
10156 switch_to_section (ctors_section
);
10157 assemble_align (BITS_PER_WORD
);
10158 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
10162 vms_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
10164 switch_to_section (dtors_section
);
10165 assemble_align (BITS_PER_WORD
);
10166 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
10171 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED
,
10172 int is_local ATTRIBUTE_UNUSED
)
10178 alpha_use_linkage (rtx func ATTRIBUTE_UNUSED
,
10179 tree cfundecl ATTRIBUTE_UNUSED
,
10180 int lflag ATTRIBUTE_UNUSED
,
10181 int rflag ATTRIBUTE_UNUSED
)
10186 #endif /* TARGET_ABI_OPEN_VMS */
10188 #if TARGET_ABI_UNICOSMK
10190 /* This evaluates to true if we do not know how to pass TYPE solely in
10191 registers. This is the case for all arguments that do not fit in two
10195 unicosmk_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
10200 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10202 if (TREE_ADDRESSABLE (type
))
10205 return ALPHA_ARG_SIZE (mode
, type
, 0) > 2;
10208 /* Define the offset between two registers, one to be eliminated, and the
10209 other its replacement, at the start of a routine. */
10212 unicosmk_initial_elimination_offset (int from
, int to
)
10216 fixed_size
= alpha_sa_size();
10217 if (fixed_size
!= 0)
10220 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
10221 return -fixed_size
;
10222 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
10224 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
10225 return (ALPHA_ROUND (crtl
->outgoing_args_size
)
10226 + ALPHA_ROUND (get_frame_size()));
10227 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
10228 return (ALPHA_ROUND (fixed_size
)
10229 + ALPHA_ROUND (get_frame_size()
10230 + crtl
->outgoing_args_size
));
10232 gcc_unreachable ();
10235 /* Output the module name for .ident and .end directives. We have to strip
10236 directories and add make sure that the module name starts with a letter
10240 unicosmk_output_module_name (FILE *file
)
10242 const char *name
= lbasename (main_input_filename
);
10243 unsigned len
= strlen (name
);
10244 char *clean_name
= alloca (len
+ 2);
10245 char *ptr
= clean_name
;
10247 /* CAM only accepts module names that start with a letter or '$'. We
10248 prefix the module name with a '$' if necessary. */
10250 if (!ISALPHA (*name
))
10252 memcpy (ptr
, name
, len
+ 1);
10253 clean_symbol_name (clean_name
);
10254 fputs (clean_name
, file
);
10257 /* Output the definition of a common variable. */
10260 unicosmk_output_common (FILE *file
, const char *name
, int size
, int align
)
10263 printf ("T3E__: common %s\n", name
);
10266 fputs("\t.endp\n\n\t.psect ", file
);
10267 assemble_name(file
, name
);
10268 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
10269 fprintf(file
, "\t.byte\t0:%d\n", size
);
10271 /* Mark the symbol as defined in this module. */
10272 name_tree
= get_identifier (name
);
10273 TREE_ASM_WRITTEN (name_tree
) = 1;
10276 #define SECTION_PUBLIC SECTION_MACH_DEP
10277 #define SECTION_MAIN (SECTION_PUBLIC << 1)
10278 static int current_section_align
;
10280 /* A get_unnamed_section callback for switching to the text section. */
10283 unicosmk_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
10285 static int count
= 0;
10286 fprintf (asm_out_file
, "\t.endp\n\n\t.psect\tgcc@text___%d,code\n", count
++);
10289 /* A get_unnamed_section callback for switching to the data section. */
10292 unicosmk_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
10294 static int count
= 1;
10295 fprintf (asm_out_file
, "\t.endp\n\n\t.psect\tgcc@data___%d,data\n", count
++);
10298 /* Implement TARGET_ASM_INIT_SECTIONS.
10300 The Cray assembler is really weird with respect to sections. It has only
10301 named sections and you can't reopen a section once it has been closed.
10302 This means that we have to generate unique names whenever we want to
10303 reenter the text or the data section. */
10306 unicosmk_init_sections (void)
10308 text_section
= get_unnamed_section (SECTION_CODE
,
10309 unicosmk_output_text_section_asm_op
,
10311 data_section
= get_unnamed_section (SECTION_WRITE
,
10312 unicosmk_output_data_section_asm_op
,
10314 readonly_data_section
= data_section
;
10317 static unsigned int
10318 unicosmk_section_type_flags (tree decl
, const char *name
,
10319 int reloc ATTRIBUTE_UNUSED
)
10321 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
10326 if (TREE_CODE (decl
) == FUNCTION_DECL
)
10328 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10329 if (align_functions_log
> current_section_align
)
10330 current_section_align
= align_functions_log
;
10332 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
10333 flags
|= SECTION_MAIN
;
10336 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
10338 if (TREE_PUBLIC (decl
))
10339 flags
|= SECTION_PUBLIC
;
10344 /* Generate a section name for decl and associate it with the
10348 unicosmk_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
10355 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
10356 name
= default_strip_name_encoding (name
);
10357 len
= strlen (name
);
10359 if (TREE_CODE (decl
) == FUNCTION_DECL
)
10363 /* It is essential that we prefix the section name here because
10364 otherwise the section names generated for constructors and
10365 destructors confuse collect2. */
10367 string
= alloca (len
+ 6);
10368 sprintf (string
, "code@%s", name
);
10369 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
10371 else if (TREE_PUBLIC (decl
))
10372 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
10377 string
= alloca (len
+ 6);
10378 sprintf (string
, "data@%s", name
);
10379 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
10383 /* Switch to an arbitrary section NAME with attributes as specified
10384 by FLAGS. ALIGN specifies any known alignment requirements for
10385 the section; 0 if the default should be used. */
10388 unicosmk_asm_named_section (const char *name
, unsigned int flags
,
10389 tree decl ATTRIBUTE_UNUSED
)
10393 /* Close the previous section. */
10395 fputs ("\t.endp\n\n", asm_out_file
);
10397 /* Find out what kind of section we are opening. */
10399 if (flags
& SECTION_MAIN
)
10400 fputs ("\t.start\tmain\n", asm_out_file
);
10402 if (flags
& SECTION_CODE
)
10404 else if (flags
& SECTION_PUBLIC
)
10409 if (current_section_align
!= 0)
10410 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
10411 current_section_align
, kind
);
10413 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
10417 unicosmk_insert_attributes (tree decl
, tree
*attr_ptr ATTRIBUTE_UNUSED
)
10420 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
10421 unicosmk_unique_section (decl
, 0);
10424 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
10425 in code sections because .align fill unused space with zeroes. */
10428 unicosmk_output_align (FILE *file
, int align
)
10430 if (inside_function
)
10431 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
10433 fprintf (file
, "\t.align\t%d\n", align
);
10436 /* Add a case vector to the current function's list of deferred case
10437 vectors. Case vectors have to be put into a separate section because CAM
10438 does not allow data definitions in code sections. */
10441 unicosmk_defer_case_vector (rtx lab
, rtx vec
)
10443 struct machine_function
*machine
= cfun
->machine
;
10445 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
10446 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
10447 machine
->addr_list
);
10450 /* Output a case vector. */
10453 unicosmk_output_addr_vec (FILE *file
, rtx vec
)
10455 rtx lab
= XEXP (vec
, 0);
10456 rtx body
= XEXP (vec
, 1);
10457 int vlen
= XVECLEN (body
, 0);
10460 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
10462 for (idx
= 0; idx
< vlen
; idx
++)
10464 ASM_OUTPUT_ADDR_VEC_ELT
10465 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10469 /* Output current function's deferred case vectors. */
10472 unicosmk_output_deferred_case_vectors (FILE *file
)
10474 struct machine_function
*machine
= cfun
->machine
;
10477 if (machine
->addr_list
== NULL_RTX
)
10480 switch_to_section (data_section
);
10481 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
10482 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
10485 /* Generate the name of the SSIB section for the current function. */
10487 #define SSIB_PREFIX "__SSIB_"
10488 #define SSIB_PREFIX_LEN 7
10490 static const char *
10491 unicosmk_ssib_name (void)
10493 /* This is ok since CAM won't be able to deal with names longer than that
10496 static char name
[256];
10499 const char *fnname
;
10502 x
= DECL_RTL (cfun
->decl
);
10503 gcc_assert (MEM_P (x
));
10505 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
10506 fnname
= XSTR (x
, 0);
10508 len
= strlen (fnname
);
10509 if (len
+ SSIB_PREFIX_LEN
> 255)
10510 len
= 255 - SSIB_PREFIX_LEN
;
10512 strcpy (name
, SSIB_PREFIX
);
10513 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
10514 name
[len
+ SSIB_PREFIX_LEN
] = 0;
10519 /* Set up the dynamic subprogram information block (DSIB) and update the
10520 frame pointer register ($15) for subroutines which have a frame. If the
10521 subroutine doesn't have a frame, simply increment $15. */
10524 unicosmk_gen_dsib (unsigned long *imaskP
)
10526 if (alpha_procedure_type
== PT_STACK
)
10528 const char *ssib_name
;
10531 /* Allocate 64 bytes for the DSIB. */
10533 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10535 emit_insn (gen_blockage ());
10537 /* Save the return address. */
10539 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
10540 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10541 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
10542 (*imaskP
) &= ~(1UL << REG_RA
);
10544 /* Save the old frame pointer. */
10546 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
10547 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10548 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
10549 (*imaskP
) &= ~(1UL << HARD_FRAME_POINTER_REGNUM
);
10551 emit_insn (gen_blockage ());
10553 /* Store the SSIB pointer. */
10555 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
10556 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
10557 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10559 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
10560 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
10561 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
10563 /* Save the CIW index. */
10565 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
10566 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10567 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
10569 emit_insn (gen_blockage ());
10571 /* Set the new frame pointer. */
10572 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10573 stack_pointer_rtx
, GEN_INT (64))));
10577 /* Increment the frame pointer register to indicate that we do not
10579 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10580 hard_frame_pointer_rtx
, const1_rtx
));
10584 /* Output the static subroutine information block for the current
10588 unicosmk_output_ssib (FILE *file
, const char *fnname
)
10594 struct machine_function
*machine
= cfun
->machine
;
10597 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
10598 unicosmk_ssib_name ());
10600 /* Some required stuff and the function name length. */
10602 len
= strlen (fnname
);
10603 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
10606 ??? We don't do that yet. */
10608 fputs ("\t.quad\t0\n", file
);
10610 /* Function address. */
10612 fputs ("\t.quad\t", file
);
10613 assemble_name (file
, fnname
);
10616 fputs ("\t.quad\t0\n", file
);
10617 fputs ("\t.quad\t0\n", file
);
10620 ??? We do it the same way Cray CC does it but this could be
10623 for( i
= 0; i
< len
; i
++ )
10624 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
10625 if( (len
% 8) == 0 )
10626 fputs ("\t.quad\t0\n", file
);
10628 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
10630 /* All call information words used in the function. */
10632 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
10635 #if HOST_BITS_PER_WIDE_INT == 32
10636 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX
"\n",
10637 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
10639 fprintf (file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n", INTVAL (ciw
));
10644 /* Add a call information word (CIW) to the list of the current function's
10645 CIWs and return its index.
10647 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10650 unicosmk_add_call_info_word (rtx x
)
10653 struct machine_function
*machine
= cfun
->machine
;
10655 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
10656 if (machine
->first_ciw
== NULL_RTX
)
10657 machine
->first_ciw
= node
;
10659 XEXP (machine
->last_ciw
, 1) = node
;
10661 machine
->last_ciw
= node
;
10662 ++machine
->ciw_count
;
10664 return GEN_INT (machine
->ciw_count
10665 + strlen (current_function_name ())/8 + 5);
10668 /* The Cray assembler doesn't accept extern declarations for symbols which
10669 are defined in the same file. We have to keep track of all global
10670 symbols which are referenced and/or defined in a source file and output
10671 extern declarations for those which are referenced but not defined at
10672 the end of file. */
10674 /* List of identifiers for which an extern declaration might have to be
10676 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10678 struct unicosmk_extern_list
10680 struct unicosmk_extern_list
*next
;
10684 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
10686 /* Output extern declarations which are required for every asm file. */
10689 unicosmk_output_default_externs (FILE *file
)
10691 static const char *const externs
[] =
10692 { "__T3E_MISMATCH" };
10697 n
= ARRAY_SIZE (externs
);
10699 for (i
= 0; i
< n
; i
++)
10700 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
10703 /* Output extern declarations for global symbols which are have been
10704 referenced but not defined. */
10707 unicosmk_output_externs (FILE *file
)
10709 struct unicosmk_extern_list
*p
;
10710 const char *real_name
;
10714 len
= strlen (user_label_prefix
);
10715 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10717 /* We have to strip the encoding and possibly remove user_label_prefix
10718 from the identifier in order to handle -fleading-underscore and
10719 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10720 real_name
= default_strip_name_encoding (p
->name
);
10721 if (len
&& p
->name
[0] == '*'
10722 && !memcmp (real_name
, user_label_prefix
, len
))
10725 name_tree
= get_identifier (real_name
);
10726 if (! TREE_ASM_WRITTEN (name_tree
))
10728 TREE_ASM_WRITTEN (name_tree
) = 1;
10729 fputs ("\t.extern\t", file
);
10730 assemble_name (file
, p
->name
);
10736 /* Record an extern. */
10739 unicosmk_add_extern (const char *name
)
10741 struct unicosmk_extern_list
*p
;
10743 p
= (struct unicosmk_extern_list
*)
10744 xmalloc (sizeof (struct unicosmk_extern_list
));
10745 p
->next
= unicosmk_extern_head
;
10747 unicosmk_extern_head
= p
;
10750 /* The Cray assembler generates incorrect code if identifiers which
10751 conflict with register names are used as instruction operands. We have
10752 to replace such identifiers with DEX expressions. */
10754 /* Structure to collect identifiers which have been replaced by DEX
10756 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10758 struct unicosmk_dex
{
10759 struct unicosmk_dex
*next
;
10763 /* List of identifiers which have been replaced by DEX expressions. The DEX
10764 number is determined by the position in the list. */
10766 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10768 /* The number of elements in the DEX list. */
10770 static int unicosmk_dex_count
= 0;
10772 /* Check if NAME must be replaced by a DEX expression. */
10775 unicosmk_special_name (const char *name
)
10777 if (name
[0] == '*')
10780 if (name
[0] == '$')
10783 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10788 case '1': case '2':
10789 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10792 return (name
[2] == '\0'
10793 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10796 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10800 /* Return the DEX number if X must be replaced by a DEX expression and 0
10804 unicosmk_need_dex (rtx x
)
10806 struct unicosmk_dex
*dex
;
10810 if (GET_CODE (x
) != SYMBOL_REF
)
10814 if (! unicosmk_special_name (name
))
10817 i
= unicosmk_dex_count
;
10818 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10820 if (! strcmp (name
, dex
->name
))
10825 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10827 dex
->next
= unicosmk_dex_list
;
10828 unicosmk_dex_list
= dex
;
10830 ++unicosmk_dex_count
;
10831 return unicosmk_dex_count
;
10834 /* Output the DEX definitions for this file. */
10837 unicosmk_output_dex (FILE *file
)
10839 struct unicosmk_dex
*dex
;
10842 if (unicosmk_dex_list
== NULL
)
10845 fprintf (file
, "\t.dexstart\n");
10847 i
= unicosmk_dex_count
;
10848 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10850 fprintf (file
, "\tDEX (%d) = ", i
);
10851 assemble_name (file
, dex
->name
);
10856 fprintf (file
, "\t.dexend\n");
10859 /* Output text that to appear at the beginning of an assembler file. */
10862 unicosmk_file_start (void)
10866 fputs ("\t.ident\t", asm_out_file
);
10867 unicosmk_output_module_name (asm_out_file
);
10868 fputs ("\n\n", asm_out_file
);
10870 /* The Unicos/Mk assembler uses different register names. Instead of trying
10871 to support them, we simply use micro definitions. */
10873 /* CAM has different register names: rN for the integer register N and fN
10874 for the floating-point register N. Instead of trying to use these in
10875 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10878 for (i
= 0; i
< 32; ++i
)
10879 fprintf (asm_out_file
, "$%d <- r%d\n", i
, i
);
10881 for (i
= 0; i
< 32; ++i
)
10882 fprintf (asm_out_file
, "$f%d <- f%d\n", i
, i
);
10884 putc ('\n', asm_out_file
);
10886 /* The .align directive fill unused space with zeroes which does not work
10887 in code sections. We define the macro 'gcc@code@align' which uses nops
10888 instead. Note that it assumes that code sections always have the
10889 biggest possible alignment since . refers to the current offset from
10890 the beginning of the section. */
10892 fputs ("\t.macro gcc@code@align n\n", asm_out_file
);
10893 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file
);
10894 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file
);
10895 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file
);
10896 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file
);
10897 fputs ("\tbis r31,r31,r31\n", asm_out_file
);
10898 fputs ("\t.endr\n", asm_out_file
);
10899 fputs ("\t.endif\n", asm_out_file
);
10900 fputs ("\t.endm gcc@code@align\n\n", asm_out_file
);
10902 /* Output extern declarations which should always be visible. */
10903 unicosmk_output_default_externs (asm_out_file
);
10905 /* Open a dummy section. We always need to be inside a section for the
10906 section-switching code to work correctly.
10907 ??? This should be a module id or something like that. I still have to
10908 figure out what the rules for those are. */
10909 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file
);
10912 /* Output text to appear at the end of an assembler file. This includes all
10913 pending extern declarations and DEX expressions. */
10916 unicosmk_file_end (void)
10918 fputs ("\t.endp\n\n", asm_out_file
);
10920 /* Output all pending externs. */
10922 unicosmk_output_externs (asm_out_file
);
10924 /* Output dex definitions used for functions whose names conflict with
10927 unicosmk_output_dex (asm_out_file
);
10929 fputs ("\t.end\t", asm_out_file
);
10930 unicosmk_output_module_name (asm_out_file
);
10931 putc ('\n', asm_out_file
);
10937 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED
)
10941 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED
)
10945 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED
,
10946 const char * fnname ATTRIBUTE_UNUSED
)
10950 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED
)
10956 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED
)
10961 #endif /* TARGET_ABI_UNICOSMK */
10964 alpha_init_libfuncs (void)
10966 if (TARGET_ABI_UNICOSMK
)
10968 /* Prevent gcc from generating calls to __divsi3. */
10969 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10970 set_optab_libfunc (udiv_optab
, SImode
, 0);
10972 /* Use the functions provided by the system library
10973 for DImode integer division. */
10974 set_optab_libfunc (sdiv_optab
, DImode
, "$sldiv");
10975 set_optab_libfunc (udiv_optab
, DImode
, "$uldiv");
10977 else if (TARGET_ABI_OPEN_VMS
)
10979 /* Use the VMS runtime library functions for division and
10981 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
10982 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
10983 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
10984 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
10985 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
10986 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
10987 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
10988 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
10989 abort_libfunc
= init_one_libfunc ("decc$abort");
10990 memcmp_libfunc
= init_one_libfunc ("decc$memcmp");
10991 #ifdef MEM_LIBFUNCS_INIT
10997 /* On the Alpha, we use this to disable the floating-point registers
10998 when they don't exist. */
11001 alpha_conditional_register_usage (void)
11004 if (! TARGET_FPREGS
)
11005 for (i
= 32; i
< 63; i
++)
11006 fixed_regs
[i
] = call_used_regs
[i
] = 1;
11009 /* Initialize the GCC target structure. */
11010 #if TARGET_ABI_OPEN_VMS
11011 # undef TARGET_ATTRIBUTE_TABLE
11012 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
11013 # undef TARGET_CAN_ELIMINATE
11014 # define TARGET_CAN_ELIMINATE alpha_vms_can_eliminate
11017 #undef TARGET_IN_SMALL_DATA_P
11018 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
11020 #if TARGET_ABI_UNICOSMK
11021 # undef TARGET_INSERT_ATTRIBUTES
11022 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
11023 # undef TARGET_SECTION_TYPE_FLAGS
11024 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
11025 # undef TARGET_ASM_UNIQUE_SECTION
11026 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
11027 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
11028 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
11029 # undef TARGET_ASM_GLOBALIZE_LABEL
11030 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
11031 # undef TARGET_MUST_PASS_IN_STACK
11032 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
11035 #undef TARGET_ASM_ALIGNED_HI_OP
11036 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
11037 #undef TARGET_ASM_ALIGNED_DI_OP
11038 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
11040 /* Default unaligned ops are provided for ELF systems. To get unaligned
11041 data for non-ELF systems, we have to turn off auto alignment. */
11042 #if !defined (OBJECT_FORMAT_ELF) || TARGET_ABI_OPEN_VMS
11043 #undef TARGET_ASM_UNALIGNED_HI_OP
11044 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
11045 #undef TARGET_ASM_UNALIGNED_SI_OP
11046 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
11047 #undef TARGET_ASM_UNALIGNED_DI_OP
11048 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
11051 #ifdef OBJECT_FORMAT_ELF
11052 #undef TARGET_ASM_RELOC_RW_MASK
11053 #define TARGET_ASM_RELOC_RW_MASK alpha_elf_reloc_rw_mask
11054 #undef TARGET_ASM_SELECT_RTX_SECTION
11055 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
11056 #undef TARGET_SECTION_TYPE_FLAGS
11057 #define TARGET_SECTION_TYPE_FLAGS alpha_elf_section_type_flags
11060 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
11061 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
11063 #undef TARGET_INIT_LIBFUNCS
11064 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
11066 #undef TARGET_LEGITIMIZE_ADDRESS
11067 #define TARGET_LEGITIMIZE_ADDRESS alpha_legitimize_address
11069 #if TARGET_ABI_UNICOSMK
11070 #undef TARGET_ASM_FILE_START
11071 #define TARGET_ASM_FILE_START unicosmk_file_start
11072 #undef TARGET_ASM_FILE_END
11073 #define TARGET_ASM_FILE_END unicosmk_file_end
11075 #undef TARGET_ASM_FILE_START
11076 #define TARGET_ASM_FILE_START alpha_file_start
11077 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
11078 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
11081 #undef TARGET_SCHED_ADJUST_COST
11082 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
11083 #undef TARGET_SCHED_ISSUE_RATE
11084 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
11085 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
11086 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
11087 alpha_multipass_dfa_lookahead
11089 #undef TARGET_HAVE_TLS
11090 #define TARGET_HAVE_TLS HAVE_AS_TLS
11092 #undef TARGET_BUILTIN_DECL
11093 #define TARGET_BUILTIN_DECL alpha_builtin_decl
11094 #undef TARGET_INIT_BUILTINS
11095 #define TARGET_INIT_BUILTINS alpha_init_builtins
11096 #undef TARGET_EXPAND_BUILTIN
11097 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
11098 #undef TARGET_FOLD_BUILTIN
11099 #define TARGET_FOLD_BUILTIN alpha_fold_builtin
11101 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11102 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
11103 #undef TARGET_CANNOT_COPY_INSN_P
11104 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
11105 #undef TARGET_CANNOT_FORCE_CONST_MEM
11106 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
11109 #undef TARGET_ASM_OUTPUT_MI_THUNK
11110 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
11111 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
11112 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
11113 #undef TARGET_STDARG_OPTIMIZE_HOOK
11114 #define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook
11117 #undef TARGET_RTX_COSTS
11118 #define TARGET_RTX_COSTS alpha_rtx_costs
11119 #undef TARGET_ADDRESS_COST
11120 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
11122 #undef TARGET_MACHINE_DEPENDENT_REORG
11123 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
11125 #undef TARGET_PROMOTE_FUNCTION_MODE
11126 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
11127 #undef TARGET_PROMOTE_PROTOTYPES
11128 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_false
11129 #undef TARGET_RETURN_IN_MEMORY
11130 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
11131 #undef TARGET_PASS_BY_REFERENCE
11132 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
11133 #undef TARGET_SETUP_INCOMING_VARARGS
11134 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
11135 #undef TARGET_STRICT_ARGUMENT_NAMING
11136 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
11137 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
11138 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
11139 #undef TARGET_SPLIT_COMPLEX_ARG
11140 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
11141 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
11142 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
11143 #undef TARGET_ARG_PARTIAL_BYTES
11144 #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
11145 #undef TARGET_FUNCTION_ARG
11146 #define TARGET_FUNCTION_ARG alpha_function_arg
11147 #undef TARGET_FUNCTION_ARG_ADVANCE
11148 #define TARGET_FUNCTION_ARG_ADVANCE alpha_function_arg_advance
11149 #undef TARGET_TRAMPOLINE_INIT
11150 #define TARGET_TRAMPOLINE_INIT alpha_trampoline_init
11152 #undef TARGET_SECONDARY_RELOAD
11153 #define TARGET_SECONDARY_RELOAD alpha_secondary_reload
11155 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11156 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
11157 #undef TARGET_VECTOR_MODE_SUPPORTED_P
11158 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
11160 #undef TARGET_BUILD_BUILTIN_VA_LIST
11161 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
11163 #undef TARGET_EXPAND_BUILTIN_VA_START
11164 #define TARGET_EXPAND_BUILTIN_VA_START alpha_va_start
11166 /* The Alpha architecture does not require sequential consistency. See
11167 http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
11168 for an example of how it can be violated in practice. */
11169 #undef TARGET_RELAXED_ORDERING
11170 #define TARGET_RELAXED_ORDERING true
11172 #undef TARGET_DEFAULT_TARGET_FLAGS
11173 #define TARGET_DEFAULT_TARGET_FLAGS \
11174 (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS)
11175 #undef TARGET_HANDLE_OPTION
11176 #define TARGET_HANDLE_OPTION alpha_handle_option
11178 #undef TARGET_OPTION_OVERRIDE
11179 #define TARGET_OPTION_OVERRIDE alpha_option_override
11181 #undef TARGET_OPTION_OPTIMIZATION_TABLE
11182 #define TARGET_OPTION_OPTIMIZATION_TABLE alpha_option_optimization_table
11184 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11185 #undef TARGET_MANGLE_TYPE
11186 #define TARGET_MANGLE_TYPE alpha_mangle_type
11189 #undef TARGET_LEGITIMATE_ADDRESS_P
11190 #define TARGET_LEGITIMATE_ADDRESS_P alpha_legitimate_address_p
11192 #undef TARGET_CONDITIONAL_REGISTER_USAGE
11193 #define TARGET_CONDITIONAL_REGISTER_USAGE alpha_conditional_register_usage
11195 struct gcc_target targetm
= TARGET_INITIALIZER
;
11198 #include "gt-alpha.h"